VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 43667

Last change on this file since 43667 was 43509, checked in by vboxsync, 12 years ago

HM: refactor.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 135.3 KB
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1/* $Id: HM.cpp 43509 2012-10-02 14:15:17Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hmR3InitCPU(PVM pVM);
276static int hmR3InitFinalizeR0(PVM pVM);
277static int hmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HM.
282 *
283 * @returns VBox status code.
284 * @param pVM Pointer to the VM.
285 */
286VMMR3DECL(int) HMR3Init(PVM pVM)
287{
288 LogFlow(("HMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hm.s, 32);
294 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313 /*
314 * Register the saved state data unit.
315 */
316 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
317 NULL, NULL, NULL,
318 NULL, hmR3Save, NULL,
319 NULL, hmR3Load, NULL);
320 if (RT_FAILURE(rc))
321 return rc;
322
323 /* Misc initialisation. */
324 pVM->hm.s.vmx.fSupported = false;
325 pVM->hm.s.svm.fSupported = false;
326 pVM->hm.s.vmx.fEnabled = false;
327 pVM->hm.s.svm.fEnabled = false;
328
329 pVM->hm.s.fNestedPaging = false;
330 pVM->hm.s.fLargePages = false;
331
332 /* Disabled by default. */
333 pVM->fHMEnabled = false;
334
335 /*
336 * Check CFGM options.
337 */
338 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
339 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
340 /* Nested paging: disabled by default. */
341 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
342 AssertRC(rc);
343
344 /* Large pages: disabled by default. */
345 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
346 AssertRC(rc);
347
348 /* VT-x VPID: disabled by default. */
349 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
350 AssertRC(rc);
351
352 /* HM support must be explicitely enabled in the configuration file. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
354 AssertRC(rc);
355
356 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
357 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
358 AssertRC(rc);
359
360#ifdef RT_OS_DARWIN
361 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
362#else
363 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
364#endif
365 {
366 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
367 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
368 return VERR_HM_CONFIG_MISMATCH;
369 }
370
371 if (VMMIsHwVirtExtForced(pVM))
372 pVM->fHMEnabled = true;
373
374#if HC_ARCH_BITS == 32
375 /*
376 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
377 * (To use the default, don't set 64bitEnabled in CFGM.)
378 */
379 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
380 AssertLogRelRCReturn(rc, rc);
381 if (pVM->hm.s.fAllow64BitGuests)
382 {
383# ifdef RT_OS_DARWIN
384 if (!VMMIsHwVirtExtForced(pVM))
385# else
386 if (!pVM->hm.s.fAllowed)
387# endif
388 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
389 }
390#else
391 /*
392 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
393 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
394 */
395 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
396 AssertLogRelRCReturn(rc, rc);
397#endif
398
399
400 /*
401 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
402 * or local init each time we wish to execute guest code.
403 *
404 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
405 */
406 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
407#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
408 false
409#else
410 true
411#endif
412 );
413
414 /* Max number of resume loops. */
415 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
416 AssertRC(rc);
417
418 return rc;
419}
420
421
422/**
423 * Initializes the per-VCPU HM.
424 *
425 * @returns VBox status code.
426 * @param pVM Pointer to the VM.
427 */
428static int hmR3InitCPU(PVM pVM)
429{
430 LogFlow(("HMR3InitCPU\n"));
431
432 for (VMCPUID i = 0; i < pVM->cCpus; i++)
433 {
434 PVMCPU pVCpu = &pVM->aCpus[i];
435
436 pVCpu->hm.s.fActive = false;
437 }
438
439#ifdef VBOX_WITH_STATISTICS
440 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
441 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
442 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
443 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
444
445 /*
446 * Statistics.
447 */
448 for (VMCPUID i = 0; i < pVM->cCpus; i++)
449 {
450 PVMCPU pVCpu = &pVM->aCpus[i];
451 int rc;
452
453 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
454 "Profiling of RTMpPokeCpu",
455 "/PROF/HM/CPU%d/Poke", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
458 "Profiling of poke wait",
459 "/PROF/HM/CPU%d/PokeWait", i);
460 AssertRC(rc);
461 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
462 "Profiling of poke wait when RTMpPokeCpu fails",
463 "/PROF/HM/CPU%d/PokeWaitFailed", i);
464 AssertRC(rc);
465 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
466 "Profiling of VMXR0RunGuestCode entry",
467 "/PROF/HM/CPU%d/SwitchToGC", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
470 "Profiling of VMXR0RunGuestCode exit part 1",
471 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
472 AssertRC(rc);
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of VMXR0RunGuestCode exit part 2",
475 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
476 AssertRC(rc);
477# if 1 /* temporary for tracking down darwin holdup. */
478 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
479 "Temporary - I/O",
480 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
481 AssertRC(rc);
482 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
483 "Temporary - CRx RWs",
484 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
485 AssertRC(rc);
486 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
487 "Temporary - Exceptions",
488 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
489 AssertRC(rc);
490# endif
491 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
492 "Profiling of vmlaunch",
493 "/PROF/HM/CPU%d/InGC", i);
494 AssertRC(rc);
495
496# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
497 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
498 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
499 "/PROF/HM/CPU%d/Switcher3264", i);
500 AssertRC(rc);
501# endif
502
503# define HM_REG_COUNTER(a, b) \
504 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
505 AssertRC(rc);
506
507 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
508 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
509 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
510 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
511 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
512 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
513 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
514 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
515 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
516 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
517 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
518 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
519 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
520 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
521 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
522 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
523 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
524 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
525 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
526 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLMSW, "/HM/CPU%d/Exit/Instr/LMSW");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIrqWindow, "/HM/CPU%d/Exit/IrqWindow");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
551
552 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
554
555 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
558
559 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbCRxChange, "/HM/CPU%d/Flush/TLB/CRx");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageInvlpg, "/HM/CPU%d/Flush/Page/Invlpg");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpga, "/HM/CPU%d/Flush/TLB/PhysInvl");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
573
574 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
577
578 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
581
582 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
583 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
584
585#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
586 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
587 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
588#endif
589
590 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
591 {
592 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
593 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
594 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
595 AssertRC(rc);
596 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
597 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
598 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
599 AssertRC(rc);
600 }
601
602#undef HM_REG_COUNTER
603
604 pVCpu->hm.s.paStatExitReason = NULL;
605
606 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
607 (void **)&pVCpu->hm.s.paStatExitReason);
608 AssertRC(rc);
609 if (RT_SUCCESS(rc))
610 {
611 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
612 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
613 {
614 if (papszDesc[j])
615 {
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
617 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
618 AssertRC(rc);
619 }
620 }
621 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
622 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
623 AssertRC(rc);
624 }
625 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
626# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
627 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
628# else
629 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
630# endif
631
632 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
633 AssertRCReturn(rc, rc);
634 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
635# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
636 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
637# else
638 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
639# endif
640 for (unsigned j = 0; j < 255; j++)
641 {
642 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
643 "Forwarded interrupts.",
644 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
645 }
646
647 }
648#endif /* VBOX_WITH_STATISTICS */
649
650#ifdef VBOX_WITH_CRASHDUMP_MAGIC
651 /* Magic marker for searching in crash dumps. */
652 for (VMCPUID i = 0; i < pVM->cCpus; i++)
653 {
654 PVMCPU pVCpu = &pVM->aCpus[i];
655
656 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
657 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
658 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
659 }
660#endif
661 return VINF_SUCCESS;
662}
663
664
665/**
666 * Called when a init phase has completed.
667 *
668 * @returns VBox status code.
669 * @param pVM The VM.
670 * @param enmWhat The phase that completed.
671 */
672VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
673{
674 switch (enmWhat)
675 {
676 case VMINITCOMPLETED_RING3:
677 return hmR3InitCPU(pVM);
678 case VMINITCOMPLETED_RING0:
679 return hmR3InitFinalizeR0(pVM);
680 default:
681 return VINF_SUCCESS;
682 }
683}
684
685
686/**
687 * Turns off normal raw mode features.
688 *
689 * @param pVM Pointer to the VM.
690 */
691static void hmR3DisableRawMode(PVM pVM)
692{
693 /* Disable PATM & CSAM. */
694 PATMR3AllowPatching(pVM, false);
695 CSAMDisableScanning(pVM);
696
697 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
698 SELMR3DisableMonitoring(pVM);
699 TRPMR3DisableMonitoring(pVM);
700
701 /* Disable the switcher code (safety precaution). */
702 VMMR3DisableSwitcher(pVM);
703
704 /* Disable mapping of the hypervisor into the shadow page table. */
705 PGMR3MappingsDisable(pVM);
706
707 /* Disable the switcher */
708 VMMR3DisableSwitcher(pVM);
709
710 /* Reinit the paging mode to force the new shadow mode. */
711 for (VMCPUID i = 0; i < pVM->cCpus; i++)
712 {
713 PVMCPU pVCpu = &pVM->aCpus[i];
714
715 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
716 }
717}
718
719
720/**
721 * Initialize VT-x or AMD-V.
722 *
723 * @returns VBox status code.
724 * @param pVM Pointer to the VM.
725 */
726static int hmR3InitFinalizeR0(PVM pVM)
727{
728 int rc;
729
730 /*
731 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
732 * is already using AMD-V.
733 */
734 if ( !pVM->hm.s.vmx.fSupported
735 && !pVM->hm.s.svm.fSupported
736 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
737 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
738 {
739 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
740 pVM->hm.s.svm.fSupported = true;
741 pVM->hm.s.svm.fIgnoreInUseError = true;
742 }
743 else
744 if ( !pVM->hm.s.vmx.fSupported
745 && !pVM->hm.s.svm.fSupported)
746 {
747 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
748 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
749
750 if (VMMIsHwVirtExtForced(pVM))
751 {
752 switch (pVM->hm.s.lLastError)
753 {
754 case VERR_VMX_NO_VMX:
755 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
756 case VERR_VMX_IN_VMX_ROOT_MODE:
757 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
758 case VERR_SVM_IN_USE:
759 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
760 case VERR_SVM_NO_SVM:
761 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
762 case VERR_SVM_DISABLED:
763 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
764 default:
765 return pVM->hm.s.lLastError;
766 }
767 }
768 return VINF_SUCCESS;
769 }
770
771 if (pVM->hm.s.vmx.fSupported)
772 {
773 rc = SUPR3QueryVTxSupported();
774 if (RT_FAILURE(rc))
775 {
776#ifdef RT_OS_LINUX
777 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
778#else
779 LogRel(("HM: The host kernel does not support VT-x!\n"));
780#endif
781 if ( pVM->cCpus > 1
782 || VMMIsHwVirtExtForced(pVM))
783 return rc;
784
785 /* silently fall back to raw mode */
786 return VINF_SUCCESS;
787 }
788 }
789
790 if (!pVM->hm.s.fAllowed)
791 return VINF_SUCCESS; /* nothing to do */
792
793 /* Enable VT-x or AMD-V on all host CPUs. */
794 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
795 if (RT_FAILURE(rc))
796 {
797 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
798 return rc;
799 }
800 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
801
802 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
803 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
804 if (!pVM->hm.s.fHasIoApic)
805 {
806 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
807 pVM->hm.s.fTRPPatchingAllowed = false;
808 }
809
810 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
811 if (pVM->hm.s.vmx.fSupported)
812 {
813 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
814
815 if ( pVM->hm.s.fInitialized == false
816 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
817 {
818 uint64_t val;
819 RTGCPHYS GCPhys = 0;
820
821 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
822 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
823 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
824 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
825 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
826 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
827 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
828 LogRel(("HM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
829
830 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
831 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
832 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
833 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
834 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
835 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
836 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
837 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
838 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
839 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
840 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
841 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
842 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
843 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
844 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
845 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
846 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
847 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
848 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
849
850 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
851 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
853 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
855 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
857 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
859 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
860 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
861 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
863 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
865 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
867 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
869 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
871 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
873 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
875 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
876 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
877 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
878 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
879 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
881 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
883 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
885 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
887 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
889 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
891 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
893 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
894
895 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
896 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
897 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
899 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
901 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
903 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
904 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
905 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
906 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
907 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
908 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
909 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
910 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
911 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
912 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
913 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
914 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
915 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
916 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
917 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
918 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
919 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
920 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
921 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
922 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
923 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
924 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
925 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
926 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
927 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
928 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
929 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
930 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
931 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
932 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
933 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
934 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
935 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
936 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
937 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
938
939 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
940 {
941 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
942 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
943 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
944 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
945 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
946 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
947 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
948 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
949 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
950 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n"));
951 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
952 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
953 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
954 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
955 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
956 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
957 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
958 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
959 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
960 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
961
962 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
963 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
964 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
965 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
966 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
967 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
968 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n"));
969 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
970 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
971 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
972 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
973 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
974 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
975 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
976 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
977 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
978 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
979 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
980 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
981 }
982
983 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
984 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
985 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
986 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
987 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
988 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
989 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
990 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
991 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
992 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
993 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
994 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
995 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
996 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
997 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
998 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
999 val = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1000 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
1001 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
1002 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
1003 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
1004 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
1005 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
1006 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
1007 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
1008 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
1009 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
1010 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
1011 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
1012 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
1013 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
1014
1015 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1016 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1017 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1018 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1019 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1020 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
1021 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1022 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
1023 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1024 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1025 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1026 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1027 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1028 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1029 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1030 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1031 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1032 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1033 val = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1034 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1035 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1036 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1037 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
1038 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1039 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
1040 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1041 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1042 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1043 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1044 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1045 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1046 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1047 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1048 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1049 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1050
1051 if (pVM->hm.s.vmx.msr.vmx_eptcaps)
1052 {
1053 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hm.s.vmx.msr.vmx_eptcaps));
1054
1055 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1056 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1057 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1058 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1059 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1060 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1061 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1062 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1063 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1064 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1065 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1066 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1067 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1068 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1069 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1070 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1071 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1072 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1073 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1074 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1075 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1076 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1077 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1078 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1079 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1080 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1081 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1082 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1083 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1084 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1085 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1086 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1087 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1088 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1089 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1090 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1091 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT)
1092 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n"));
1093 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS)
1094 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n"));
1095 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1096 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1097 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR)
1098 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n"));
1099 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT)
1100 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n"));
1101 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)
1102 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n"));
1103 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS)
1104 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1105 }
1106
1107 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1108 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1109 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1110 else
1111 {
1112 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n",
1113 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1114 }
1115 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1116 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1117 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1118 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1119
1120 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1121 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1122 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1123 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1124 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1125
1126 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1127
1128 /* Paranoia */
1129 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1130
1131 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1132 {
1133 LogRel(("HM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1134 LogRel(("HM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
1135 }
1136
1137 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1138 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1139
1140 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1141 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1142
1143 /*
1144 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1145 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1146 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1147 */
1148 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1149 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1150 {
1151 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1152 }
1153
1154 /* Unrestricted guest execution relies on EPT. */
1155 if ( pVM->hm.s.fNestedPaging
1156 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1157 {
1158 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1159 }
1160
1161 /* Only try once. */
1162 pVM->hm.s.fInitialized = true;
1163
1164 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1165 {
1166 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1167 rc = PDMR3VMMDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1168 if (RT_SUCCESS(rc))
1169 {
1170 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1171 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1172 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1173 /* Bit set to 0 means redirection enabled. */
1174 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1175 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1176 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1177 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1178
1179 /*
1180 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1181 * real and protected mode without paging with EPT.
1182 */
1183 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1184 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1185 {
1186 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1187 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1188 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1189 | X86_PDE4M_G;
1190 }
1191
1192 /* We convert it here every time as pci regions could be reconfigured. */
1193 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1194 AssertRC(rc);
1195 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1196
1197 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1198 AssertRC(rc);
1199 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1200 }
1201 else
1202 {
1203 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1204 pVM->hm.s.vmx.pRealModeTSS = NULL;
1205 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1206 }
1207 }
1208
1209 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1210 AssertRC(rc);
1211 if (rc == VINF_SUCCESS)
1212 {
1213 pVM->fHMEnabled = true;
1214 pVM->hm.s.vmx.fEnabled = true;
1215 hmR3DisableRawMode(pVM);
1216
1217 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1218#ifdef VBOX_ENABLE_64_BITS_GUESTS
1219 if (pVM->hm.s.fAllow64BitGuests)
1220 {
1221 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1222 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1223 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1224 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1225 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1226 }
1227 else
1228 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1229 /* Todo: this needs to be fixed properly!! */
1230 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1231 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1232 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1233
1234 LogRel((pVM->hm.s.fAllow64BitGuests
1235 ? "HM: 32-bit and 64-bit guests supported.\n"
1236 : "HM: 32-bit guests supported.\n"));
1237#else
1238 LogRel(("HM: 32-bit guests supported.\n"));
1239#endif
1240 LogRel(("HM: VMX enabled!\n"));
1241 if (pVM->hm.s.fNestedPaging)
1242 {
1243 LogRel(("HM: Enabled nested paging\n"));
1244 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1245 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1246 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1247 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1248 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1249 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1250 LogRel(("HM: enmFlushEpt = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1251 else
1252 LogRel(("HM: enmFlushEpt = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1253
1254 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1255 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1256
1257#if HC_ARCH_BITS == 64
1258 if (pVM->hm.s.fLargePages)
1259 {
1260 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1261 PGMSetLargePageUsage(pVM, true);
1262 LogRel(("HM: Large page support enabled!\n"));
1263 }
1264#endif
1265 }
1266 else
1267 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1268
1269 if (pVM->hm.s.vmx.fVpid)
1270 {
1271 LogRel(("HM: Enabled VPID\n"));
1272 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1273 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1274 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1275 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1276 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1277 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1278 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1279 LogRel(("HM: enmFlushVpid = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1280 else
1281 LogRel(("HM: enmFlushVpid = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1282 }
1283 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1284 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1285
1286 /* TPR patching status logging. */
1287 if (pVM->hm.s.fTRPPatchingAllowed)
1288 {
1289 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1290 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1291 {
1292 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1293 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1294 }
1295 else
1296 {
1297 uint32_t u32Eax, u32Dummy;
1298
1299 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1300 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1301 if ( u32Eax < 0x80000001
1302 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1303 {
1304 pVM->hm.s.fTRPPatchingAllowed = false;
1305 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1306 }
1307 }
1308 }
1309 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1310
1311 /*
1312 * Check for preemption timer config override and log the state of it.
1313 */
1314 if (pVM->hm.s.vmx.fUsePreemptTimer)
1315 {
1316 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1317 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1318 AssertLogRelRC(rc2);
1319 }
1320 if (pVM->hm.s.vmx.fUsePreemptTimer)
1321 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1322 }
1323 else
1324 {
1325 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1326 LogRel(("HM: Last instruction error %x\n", pVM->aCpus[0].hm.s.vmx.lasterror.ulInstrError));
1327 pVM->fHMEnabled = false;
1328 }
1329 }
1330 }
1331 else
1332 if (pVM->hm.s.svm.fSupported)
1333 {
1334 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1335
1336 if (pVM->hm.s.fInitialized == false)
1337 {
1338 /* Erratum 170 which requires a forced TLB flush for each world switch:
1339 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1340 *
1341 * All BH-G1/2 and DH-G1/2 models include a fix:
1342 * Athlon X2: 0x6b 1/2
1343 * 0x68 1/2
1344 * Athlon 64: 0x7f 1
1345 * 0x6f 2
1346 * Sempron: 0x7f 1/2
1347 * 0x6f 2
1348 * 0x6c 2
1349 * 0x7c 2
1350 * Turion 64: 0x68 2
1351 *
1352 */
1353 uint32_t u32Dummy;
1354 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1355 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1356 u32BaseFamily= (u32Version >> 8) & 0xf;
1357 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1358 u32Model = ((u32Version >> 4) & 0xf);
1359 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1360 u32Stepping = u32Version & 0xf;
1361 if ( u32Family == 0xf
1362 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1363 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1364 {
1365 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1366 }
1367
1368 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1369 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1370 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1371 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1372 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1373 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1374 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1375 {
1376#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1377 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1378 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1379 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1380 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1381 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1382 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1383 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1384 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1385 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1386 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1387 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1388#undef FLAG_NAME
1389 };
1390 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1391 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1392 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1393 {
1394 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1395 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1396 }
1397 if (fSvmFeatures)
1398 for (unsigned iBit = 0; iBit < 32; iBit++)
1399 if (RT_BIT_32(iBit) & fSvmFeatures)
1400 LogRel(("HM: Reserved bit %u\n", iBit));
1401
1402 /* Only try once. */
1403 pVM->hm.s.fInitialized = true;
1404
1405 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1406 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1407
1408 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1409 AssertRC(rc);
1410 if (rc == VINF_SUCCESS)
1411 {
1412 pVM->fHMEnabled = true;
1413 pVM->hm.s.svm.fEnabled = true;
1414
1415 if (pVM->hm.s.fNestedPaging)
1416 {
1417 LogRel(("HM: Enabled nested paging\n"));
1418#if HC_ARCH_BITS == 64
1419 if (pVM->hm.s.fLargePages)
1420 {
1421 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1422 PGMSetLargePageUsage(pVM, true);
1423 LogRel(("HM: Large page support enabled!\n"));
1424 }
1425#endif
1426 }
1427
1428 hmR3DisableRawMode(pVM);
1429 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1430 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1431#ifdef VBOX_ENABLE_64_BITS_GUESTS
1432 if (pVM->hm.s.fAllow64BitGuests)
1433 {
1434 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1435 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1436 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1437 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1438 }
1439 else
1440 /* Turn on NXE if PAE has been enabled. */
1441 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1442 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1443#endif
1444
1445 LogRel((pVM->hm.s.fAllow64BitGuests
1446 ? "HM: 32-bit and 64-bit guest supported.\n"
1447 : "HM: 32-bit guest supported.\n"));
1448
1449 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1450 }
1451 else
1452 {
1453 pVM->fHMEnabled = false;
1454 }
1455 }
1456 }
1457 if (pVM->fHMEnabled)
1458 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1459 RTLogRelSetBuffering(fOldBuffered);
1460 return VINF_SUCCESS;
1461}
1462
1463
1464/**
1465 * Applies relocations to data and code managed by this
1466 * component. This function will be called at init and
1467 * whenever the VMM need to relocate it self inside the GC.
1468 *
1469 * @param pVM The VM.
1470 */
1471VMMR3DECL(void) HMR3Relocate(PVM pVM)
1472{
1473 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1474
1475 /* Fetch the current paging mode during the relocate callback during state loading. */
1476 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1477 {
1478 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1479 {
1480 PVMCPU pVCpu = &pVM->aCpus[i];
1481
1482 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1483 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1484 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1485 }
1486 }
1487#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1488 if (pVM->fHMEnabled)
1489 {
1490 int rc;
1491 switch (PGMGetHostMode(pVM))
1492 {
1493 case PGMMODE_32_BIT:
1494 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1495 break;
1496
1497 case PGMMODE_PAE:
1498 case PGMMODE_PAE_NX:
1499 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1500 break;
1501
1502 default:
1503 AssertFailed();
1504 break;
1505 }
1506 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1507 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1508
1509 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1510 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1511
1512 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1513 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1514
1515 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1516 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1517
1518# ifdef DEBUG
1519 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1520 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1521# endif
1522 }
1523#endif
1524 return;
1525}
1526
1527
1528/**
1529 * Checks if hardware accelerated raw mode is allowed.
1530 *
1531 * @returns true if hardware acceleration is allowed, otherwise false.
1532 * @param pVM Pointer to the VM.
1533 */
1534VMMR3DECL(bool) HMR3IsAllowed(PVM pVM)
1535{
1536 return pVM->hm.s.fAllowed;
1537}
1538
1539
1540/**
1541 * Notification callback which is called whenever there is a chance that a CR3
1542 * value might have changed.
1543 *
1544 * This is called by PGM.
1545 *
1546 * @param pVM Pointer to the VM.
1547 * @param pVCpu Pointer to the VMCPU.
1548 * @param enmShadowMode New shadow paging mode.
1549 * @param enmGuestMode New guest paging mode.
1550 */
1551VMMR3DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1552{
1553 /* Ignore page mode changes during state loading. */
1554 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1555 return;
1556
1557 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1558
1559 if ( pVM->hm.s.vmx.fEnabled
1560 && pVM->fHMEnabled)
1561 {
1562 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1563 && enmGuestMode >= PGMMODE_PROTECTED)
1564 {
1565 PCPUMCTX pCtx;
1566
1567 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1568
1569 /* After a real mode switch to protected mode we must force
1570 CPL to 0. Our real mode emulation had to set it to 3. */
1571 pCtx->ss.Attr.n.u2Dpl = 0;
1572 }
1573 }
1574
1575 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1576 {
1577 /* Keep track of paging mode changes. */
1578 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1579 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1580
1581 /* Did we miss a change, because all code was executed in the recompiler? */
1582 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1583 {
1584 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1585 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1586 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1587 }
1588 }
1589
1590 /* Reset the contents of the read cache. */
1591 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1592 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1593 pCache->Read.aFieldVal[j] = 0;
1594}
1595
1596
1597/**
1598 * Terminates the HM.
1599 *
1600 * Termination means cleaning up and freeing all resources,
1601 * the VM itself is, at this point, powered off or suspended.
1602 *
1603 * @returns VBox status code.
1604 * @param pVM Pointer to the VM.
1605 */
1606VMMR3DECL(int) HMR3Term(PVM pVM)
1607{
1608 if (pVM->hm.s.vmx.pRealModeTSS)
1609 {
1610 PDMR3VMMDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1611 pVM->hm.s.vmx.pRealModeTSS = 0;
1612 }
1613 hmR3TermCPU(pVM);
1614 return 0;
1615}
1616
1617
1618/**
1619 * Terminates the per-VCPU HM.
1620 *
1621 * @returns VBox status code.
1622 * @param pVM Pointer to the VM.
1623 */
1624static int hmR3TermCPU(PVM pVM)
1625{
1626 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1627 {
1628 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1629
1630#ifdef VBOX_WITH_STATISTICS
1631 if (pVCpu->hm.s.paStatExitReason)
1632 {
1633 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1634 pVCpu->hm.s.paStatExitReason = NULL;
1635 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1636 }
1637 if (pVCpu->hm.s.paStatInjectedIrqs)
1638 {
1639 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1640 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1641 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1642 }
1643#endif
1644
1645#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1646 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1647 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1648 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1649#endif
1650 }
1651 return 0;
1652}
1653
1654
1655/**
1656 * Resets a virtual CPU.
1657 *
1658 * Used by HMR3Reset and CPU hot plugging.
1659 *
1660 * @param pVCpu The CPU to reset.
1661 */
1662VMMR3DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1663{
1664 /* On first entry we'll sync everything. */
1665 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1666
1667 pVCpu->hm.s.vmx.cr0_mask = 0;
1668 pVCpu->hm.s.vmx.cr4_mask = 0;
1669
1670 pVCpu->hm.s.fActive = false;
1671 pVCpu->hm.s.Event.fPending = false;
1672
1673 /* Reset state information for real-mode emulation in VT-x. */
1674 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1675 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1676 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1677
1678 /* Reset the contents of the read cache. */
1679 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1680 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1681 pCache->Read.aFieldVal[j] = 0;
1682
1683#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1684 /* Magic marker for searching in crash dumps. */
1685 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1686 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1687#endif
1688}
1689
1690
1691/**
1692 * The VM is being reset.
1693 *
1694 * For the HM component this means that any GDT/LDT/TSS monitors
1695 * needs to be removed.
1696 *
1697 * @param pVM Pointer to the VM.
1698 */
1699VMMR3DECL(void) HMR3Reset(PVM pVM)
1700{
1701 LogFlow(("HMR3Reset:\n"));
1702
1703 if (pVM->fHMEnabled)
1704 hmR3DisableRawMode(pVM);
1705
1706 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1707 {
1708 PVMCPU pVCpu = &pVM->aCpus[i];
1709
1710 HMR3ResetCpu(pVCpu);
1711 }
1712
1713 /* Clear all patch information. */
1714 pVM->hm.s.pGuestPatchMem = 0;
1715 pVM->hm.s.pFreeGuestPatchMem = 0;
1716 pVM->hm.s.cbGuestPatchMem = 0;
1717 pVM->hm.s.cPatches = 0;
1718 pVM->hm.s.PatchTree = 0;
1719 pVM->hm.s.fTPRPatchingActive = false;
1720 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1721}
1722
1723
1724/**
1725 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1726 *
1727 * @returns VBox strict status code.
1728 * @param pVM Pointer to the VM.
1729 * @param pVCpu The VMCPU for the EMT we're being called on.
1730 * @param pvUser Unused.
1731 */
1732DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1733{
1734 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1735
1736 /* Only execute the handler on the VCPU the original patch request was issued. */
1737 if (pVCpu->idCpu != idCpu)
1738 return VINF_SUCCESS;
1739
1740 Log(("hmR3RemovePatches\n"));
1741 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1742 {
1743 uint8_t abInstr[15];
1744 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1745 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1746 int rc;
1747
1748#ifdef LOG_ENABLED
1749 char szOutput[256];
1750
1751 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1752 szOutput, sizeof(szOutput), NULL);
1753 if (RT_SUCCESS(rc))
1754 Log(("Patched instr: %s\n", szOutput));
1755#endif
1756
1757 /* Check if the instruction is still the same. */
1758 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1759 if (rc != VINF_SUCCESS)
1760 {
1761 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1762 continue; /* swapped out or otherwise removed; skip it. */
1763 }
1764
1765 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1766 {
1767 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1768 continue; /* skip it. */
1769 }
1770
1771 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1772 AssertRC(rc);
1773
1774#ifdef LOG_ENABLED
1775 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1776 szOutput, sizeof(szOutput), NULL);
1777 if (RT_SUCCESS(rc))
1778 Log(("Original instr: %s\n", szOutput));
1779#endif
1780 }
1781 pVM->hm.s.cPatches = 0;
1782 pVM->hm.s.PatchTree = 0;
1783 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1784 pVM->hm.s.fTPRPatchingActive = false;
1785 return VINF_SUCCESS;
1786}
1787
1788
1789/**
1790 * Worker for enabling patching in a VT-x/AMD-V guest.
1791 *
1792 * @returns VBox status code.
1793 * @param pVM Pointer to the VM.
1794 * @param idCpu VCPU to execute hmR3RemovePatches on.
1795 * @param pPatchMem Patch memory range.
1796 * @param cbPatchMem Size of the memory range.
1797 */
1798static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1799{
1800 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1801 AssertRC(rc);
1802
1803 pVM->hm.s.pGuestPatchMem = pPatchMem;
1804 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1805 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1806 return VINF_SUCCESS;
1807}
1808
1809
1810/**
1811 * Enable patching in a VT-x/AMD-V guest
1812 *
1813 * @returns VBox status code.
1814 * @param pVM Pointer to the VM.
1815 * @param pPatchMem Patch memory range.
1816 * @param cbPatchMem Size of the memory range.
1817 */
1818VMMR3DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1819{
1820 VM_ASSERT_EMT(pVM);
1821 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1822 if (pVM->cCpus > 1)
1823 {
1824 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1825 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1826 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1827 AssertRC(rc);
1828 return rc;
1829 }
1830 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1831}
1832
1833
1834/**
1835 * Disable patching in a VT-x/AMD-V guest.
1836 *
1837 * @returns VBox status code.
1838 * @param pVM Pointer to the VM.
1839 * @param pPatchMem Patch memory range.
1840 * @param cbPatchMem Size of the memory range.
1841 */
1842VMMR3DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1843{
1844 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1845
1846 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1847 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1848
1849 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1850 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1851 (void *)(uintptr_t)VMMGetCpuId(pVM));
1852 AssertRC(rc);
1853
1854 pVM->hm.s.pGuestPatchMem = 0;
1855 pVM->hm.s.pFreeGuestPatchMem = 0;
1856 pVM->hm.s.cbGuestPatchMem = 0;
1857 pVM->hm.s.fTPRPatchingActive = false;
1858 return VINF_SUCCESS;
1859}
1860
1861
1862/**
1863 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1864 *
1865 * @returns VBox strict status code.
1866 * @param pVM Pointer to the VM.
1867 * @param pVCpu The VMCPU for the EMT we're being called on.
1868 * @param pvUser User specified CPU context.
1869 *
1870 */
1871DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1872{
1873 /*
1874 * Only execute the handler on the VCPU the original patch request was
1875 * issued. (The other CPU(s) might not yet have switched to protected
1876 * mode, nor have the correct memory context.)
1877 */
1878 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1879 if (pVCpu->idCpu != idCpu)
1880 return VINF_SUCCESS;
1881
1882 /*
1883 * We're racing other VCPUs here, so don't try patch the instruction twice
1884 * and make sure there is still room for our patch record.
1885 */
1886 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1887 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1888 if (pPatch)
1889 {
1890 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1891 return VINF_SUCCESS;
1892 }
1893 uint32_t const idx = pVM->hm.s.cPatches;
1894 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1895 {
1896 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1897 return VINF_SUCCESS;
1898 }
1899 pPatch = &pVM->hm.s.aPatches[idx];
1900
1901 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1902
1903 /*
1904 * Disassembler the instruction and get cracking.
1905 */
1906 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3ReplaceTprInstr");
1907 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1908 uint32_t cbOp;
1909 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1910 AssertRC(rc);
1911 if ( rc == VINF_SUCCESS
1912 && pDis->pCurInstr->uOpcode == OP_MOV
1913 && cbOp >= 3)
1914 {
1915 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1916
1917 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1918 AssertRC(rc);
1919
1920 pPatch->cbOp = cbOp;
1921
1922 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1923 {
1924 /* write. */
1925 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1926 {
1927 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1928 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1929 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1930 }
1931 else
1932 {
1933 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1934 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1935 pPatch->uSrcOperand = pDis->Param2.uValue;
1936 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1937 }
1938 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1939 AssertRC(rc);
1940
1941 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1942 pPatch->cbNewOp = sizeof(s_abVMMCall);
1943 }
1944 else
1945 {
1946 /*
1947 * TPR Read.
1948 *
1949 * Found:
1950 * mov eax, dword [fffe0080] (5 bytes)
1951 * Check if next instruction is:
1952 * shr eax, 4
1953 */
1954 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1955
1956 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1957 uint8_t const cbOpMmio = cbOp;
1958 uint64_t const uSavedRip = pCtx->rip;
1959
1960 pCtx->rip += cbOp;
1961 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1962 DBGFR3DisasInstrCurrentLog(pVCpu, "Following read");
1963 pCtx->rip = uSavedRip;
1964
1965 if ( rc == VINF_SUCCESS
1966 && pDis->pCurInstr->uOpcode == OP_SHR
1967 && pDis->Param1.fUse == DISUSE_REG_GEN32
1968 && pDis->Param1.Base.idxGenReg == idxMmioReg
1969 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1970 && pDis->Param2.uValue == 4
1971 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1972 {
1973 uint8_t abInstr[15];
1974
1975 /* Replacing two instructions now. */
1976 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1977 AssertRC(rc);
1978
1979 pPatch->cbOp = cbOpMmio + cbOp;
1980
1981 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1982 abInstr[0] = 0xF0;
1983 abInstr[1] = 0x0F;
1984 abInstr[2] = 0x20;
1985 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1986 for (unsigned i = 4; i < pPatch->cbOp; i++)
1987 abInstr[i] = 0x90; /* nop */
1988
1989 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1990 AssertRC(rc);
1991
1992 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1993 pPatch->cbNewOp = pPatch->cbOp;
1994
1995 Log(("Acceptable read/shr candidate!\n"));
1996 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1997 }
1998 else
1999 {
2000 pPatch->enmType = HMTPRINSTR_READ;
2001 pPatch->uDstOperand = idxMmioReg;
2002
2003 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2004 AssertRC(rc);
2005
2006 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2007 pPatch->cbNewOp = sizeof(s_abVMMCall);
2008 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2009 }
2010 }
2011
2012 pPatch->Core.Key = pCtx->eip;
2013 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2014 AssertRC(rc);
2015
2016 pVM->hm.s.cPatches++;
2017 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2018 return VINF_SUCCESS;
2019 }
2020
2021 /*
2022 * Save invalid patch, so we will not try again.
2023 */
2024 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2025 pPatch->Core.Key = pCtx->eip;
2026 pPatch->enmType = HMTPRINSTR_INVALID;
2027 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2028 AssertRC(rc);
2029 pVM->hm.s.cPatches++;
2030 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2031 return VINF_SUCCESS;
2032}
2033
2034
2035/**
2036 * Callback to patch a TPR instruction (jump to generated code).
2037 *
2038 * @returns VBox strict status code.
2039 * @param pVM Pointer to the VM.
2040 * @param pVCpu The VMCPU for the EMT we're being called on.
2041 * @param pvUser User specified CPU context.
2042 *
2043 */
2044DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2045{
2046 /*
2047 * Only execute the handler on the VCPU the original patch request was
2048 * issued. (The other CPU(s) might not yet have switched to protected
2049 * mode, nor have the correct memory context.)
2050 */
2051 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2052 if (pVCpu->idCpu != idCpu)
2053 return VINF_SUCCESS;
2054
2055 /*
2056 * We're racing other VCPUs here, so don't try patch the instruction twice
2057 * and make sure there is still room for our patch record.
2058 */
2059 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2060 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2061 if (pPatch)
2062 {
2063 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2064 return VINF_SUCCESS;
2065 }
2066 uint32_t const idx = pVM->hm.s.cPatches;
2067 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2068 {
2069 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2070 return VINF_SUCCESS;
2071 }
2072 pPatch = &pVM->hm.s.aPatches[idx];
2073
2074 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2075 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3PatchTprInstr");
2076
2077 /*
2078 * Disassemble the instruction and get cracking.
2079 */
2080 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2081 uint32_t cbOp;
2082 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2083 AssertRC(rc);
2084 if ( rc == VINF_SUCCESS
2085 && pDis->pCurInstr->uOpcode == OP_MOV
2086 && cbOp >= 5)
2087 {
2088 uint8_t aPatch[64];
2089 uint32_t off = 0;
2090
2091 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2092 AssertRC(rc);
2093
2094 pPatch->cbOp = cbOp;
2095 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2096
2097 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2098 {
2099 /*
2100 * TPR write:
2101 *
2102 * push ECX [51]
2103 * push EDX [52]
2104 * push EAX [50]
2105 * xor EDX,EDX [31 D2]
2106 * mov EAX,EAX [89 C0]
2107 * or
2108 * mov EAX,0000000CCh [B8 CC 00 00 00]
2109 * mov ECX,0C0000082h [B9 82 00 00 C0]
2110 * wrmsr [0F 30]
2111 * pop EAX [58]
2112 * pop EDX [5A]
2113 * pop ECX [59]
2114 * jmp return_address [E9 return_address]
2115 *
2116 */
2117 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2118
2119 aPatch[off++] = 0x51; /* push ecx */
2120 aPatch[off++] = 0x52; /* push edx */
2121 if (!fUsesEax)
2122 aPatch[off++] = 0x50; /* push eax */
2123 aPatch[off++] = 0x31; /* xor edx, edx */
2124 aPatch[off++] = 0xD2;
2125 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2126 {
2127 if (!fUsesEax)
2128 {
2129 aPatch[off++] = 0x89; /* mov eax, src_reg */
2130 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2131 }
2132 }
2133 else
2134 {
2135 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2136 aPatch[off++] = 0xB8; /* mov eax, immediate */
2137 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2138 off += sizeof(uint32_t);
2139 }
2140 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2141 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2142 off += sizeof(uint32_t);
2143
2144 aPatch[off++] = 0x0F; /* wrmsr */
2145 aPatch[off++] = 0x30;
2146 if (!fUsesEax)
2147 aPatch[off++] = 0x58; /* pop eax */
2148 aPatch[off++] = 0x5A; /* pop edx */
2149 aPatch[off++] = 0x59; /* pop ecx */
2150 }
2151 else
2152 {
2153 /*
2154 * TPR read:
2155 *
2156 * push ECX [51]
2157 * push EDX [52]
2158 * push EAX [50]
2159 * mov ECX,0C0000082h [B9 82 00 00 C0]
2160 * rdmsr [0F 32]
2161 * mov EAX,EAX [89 C0]
2162 * pop EAX [58]
2163 * pop EDX [5A]
2164 * pop ECX [59]
2165 * jmp return_address [E9 return_address]
2166 *
2167 */
2168 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2169
2170 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2171 aPatch[off++] = 0x51; /* push ecx */
2172 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2173 aPatch[off++] = 0x52; /* push edx */
2174 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2175 aPatch[off++] = 0x50; /* push eax */
2176
2177 aPatch[off++] = 0x31; /* xor edx, edx */
2178 aPatch[off++] = 0xD2;
2179
2180 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2181 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2182 off += sizeof(uint32_t);
2183
2184 aPatch[off++] = 0x0F; /* rdmsr */
2185 aPatch[off++] = 0x32;
2186
2187 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2188 {
2189 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2190 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2191 }
2192
2193 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2194 aPatch[off++] = 0x58; /* pop eax */
2195 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2196 aPatch[off++] = 0x5A; /* pop edx */
2197 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2198 aPatch[off++] = 0x59; /* pop ecx */
2199 }
2200 aPatch[off++] = 0xE9; /* jmp return_address */
2201 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2202 off += sizeof(RTRCUINTPTR);
2203
2204 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2205 {
2206 /* Write new code to the patch buffer. */
2207 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2208 AssertRC(rc);
2209
2210#ifdef LOG_ENABLED
2211 uint32_t cbCurInstr;
2212 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2213 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2214 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2215 {
2216 char szOutput[256];
2217 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2218 szOutput, sizeof(szOutput), &cbCurInstr);
2219 if (RT_SUCCESS(rc))
2220 Log(("Patch instr %s\n", szOutput));
2221 else
2222 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2223 }
2224#endif
2225
2226 pPatch->aNewOpcode[0] = 0xE9;
2227 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2228
2229 /* Overwrite the TPR instruction with a jump. */
2230 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2231 AssertRC(rc);
2232
2233 DBGFR3DisasInstrCurrentLog(pVCpu, "Jump");
2234
2235 pVM->hm.s.pFreeGuestPatchMem += off;
2236 pPatch->cbNewOp = 5;
2237
2238 pPatch->Core.Key = pCtx->eip;
2239 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2240 AssertRC(rc);
2241
2242 pVM->hm.s.cPatches++;
2243 pVM->hm.s.fTPRPatchingActive = true;
2244 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2245 return VINF_SUCCESS;
2246 }
2247
2248 Log(("Ran out of space in our patch buffer!\n"));
2249 }
2250 else
2251 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2252
2253
2254 /*
2255 * Save invalid patch, so we will not try again.
2256 */
2257 pPatch = &pVM->hm.s.aPatches[idx];
2258 pPatch->Core.Key = pCtx->eip;
2259 pPatch->enmType = HMTPRINSTR_INVALID;
2260 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2261 AssertRC(rc);
2262 pVM->hm.s.cPatches++;
2263 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2264 return VINF_SUCCESS;
2265}
2266
2267
2268/**
2269 * Attempt to patch TPR mmio instructions.
2270 *
2271 * @returns VBox status code.
2272 * @param pVM Pointer to the VM.
2273 * @param pVCpu Pointer to the VMCPU.
2274 * @param pCtx Pointer to the guest CPU context.
2275 */
2276VMMR3DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2277{
2278 NOREF(pCtx);
2279 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2280 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2281 (void *)(uintptr_t)pVCpu->idCpu);
2282 AssertRC(rc);
2283 return rc;
2284}
2285
2286
2287/**
2288 * Force execution of the current IO code in the recompiler.
2289 *
2290 * @returns VBox status code.
2291 * @param pVM Pointer to the VM.
2292 * @param pCtx Partial VM execution context.
2293 */
2294VMMR3DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2295{
2296 PVMCPU pVCpu = VMMGetCpu(pVM);
2297
2298 Assert(pVM->fHMEnabled);
2299 Log(("HMR3EmulateIoBlock\n"));
2300
2301 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2302 if (HMCanEmulateIoBlockEx(pCtx))
2303 {
2304 Log(("HMR3EmulateIoBlock -> enabled\n"));
2305 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2306 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2307 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2308 return VINF_EM_RESCHEDULE_REM;
2309 }
2310 return VINF_SUCCESS;
2311}
2312
2313
2314/**
2315 * Checks if we can currently use hardware accelerated raw mode.
2316 *
2317 * @returns true if we can currently use hardware acceleration, otherwise false.
2318 * @param pVM Pointer to the VM.
2319 * @param pCtx Partial VM execution context.
2320 */
2321VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2322{
2323 PVMCPU pVCpu = VMMGetCpu(pVM);
2324
2325 Assert(pVM->fHMEnabled);
2326
2327 /* If we're still executing the IO code, then return false. */
2328 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2329 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2330 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2331 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2332 return false;
2333
2334 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2335
2336 /* AMD-V supports real & protected mode with or without paging. */
2337 if (pVM->hm.s.svm.fEnabled)
2338 {
2339 pVCpu->hm.s.fActive = true;
2340 return true;
2341 }
2342
2343 pVCpu->hm.s.fActive = false;
2344
2345 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2346 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2347 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2348
2349 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2350 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2351 {
2352 /*
2353 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2354 * guest execution feature i missing (VT-x only).
2355 */
2356 if (fSupportsRealMode)
2357 {
2358 if (CPUMIsGuestInRealModeEx(pCtx))
2359 {
2360 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2361 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2362 * If this is not true, we cannot execute real mode as V86 and have to fall
2363 * back to emulation.
2364 */
2365 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2366 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2367 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2368 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2369 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2370 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2371 || (pCtx->cs.u32Limit != 0xffff)
2372 || (pCtx->ds.u32Limit != 0xffff)
2373 || (pCtx->es.u32Limit != 0xffff)
2374 || (pCtx->ss.u32Limit != 0xffff)
2375 || (pCtx->fs.u32Limit != 0xffff)
2376 || (pCtx->gs.u32Limit != 0xffff))
2377 {
2378 return false;
2379 }
2380 }
2381 else
2382 {
2383 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2384 /* Verify the requirements for executing code in protected
2385 mode. VT-x can't handle the CPU state right after a switch
2386 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2387 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2388 && enmGuestMode >= PGMMODE_PROTECTED)
2389 {
2390 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2391 || (pCtx->ds.Sel & X86_SEL_RPL)
2392 || (pCtx->es.Sel & X86_SEL_RPL)
2393 || (pCtx->fs.Sel & X86_SEL_RPL)
2394 || (pCtx->gs.Sel & X86_SEL_RPL)
2395 || (pCtx->ss.Sel & X86_SEL_RPL))
2396 {
2397 return false;
2398 }
2399 }
2400 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2401 if ( pCtx->gdtr.cbGdt
2402 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2403 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2404 {
2405 return false;
2406 }
2407 }
2408 }
2409 else
2410 {
2411 if ( !CPUMIsGuestInLongModeEx(pCtx)
2412 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2413 {
2414 /** @todo This should (probably) be set on every excursion to the REM,
2415 * however it's too risky right now. So, only apply it when we go
2416 * back to REM for real mode execution. (The XP hack below doesn't
2417 * work reliably without this.)
2418 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2419 pVM->aCpus[0].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2420
2421 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2422 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2423 return false;
2424
2425 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2426 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2427 return false;
2428
2429 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2430 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2431 * hidden registers (possible recompiler bug; see load_seg_vm) */
2432 if (pCtx->cs.Attr.n.u1Present == 0)
2433 return false;
2434 if (pCtx->ss.Attr.n.u1Present == 0)
2435 return false;
2436
2437 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2438 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2439 /** @todo This check is actually wrong, it doesn't take the direction of the
2440 * stack segment into account. But, it does the job for now. */
2441 if (pCtx->rsp >= pCtx->ss.u32Limit)
2442 return false;
2443#if 0
2444 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2445 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2446 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2447 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2448 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2449 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2450 return false;
2451#endif
2452 }
2453 }
2454 }
2455
2456 if (pVM->hm.s.vmx.fEnabled)
2457 {
2458 uint32_t mask;
2459
2460 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2461 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2462 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2463 mask &= ~X86_CR0_NE;
2464
2465 if (fSupportsRealMode)
2466 {
2467 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2468 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2469 }
2470 else
2471 {
2472 /* We support protected mode without paging using identity mapping. */
2473 mask &= ~X86_CR0_PG;
2474 }
2475 if ((pCtx->cr0 & mask) != mask)
2476 return false;
2477
2478 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2479 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2480 if ((pCtx->cr0 & mask) != 0)
2481 return false;
2482
2483 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2484 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2485 mask &= ~X86_CR4_VMXE;
2486 if ((pCtx->cr4 & mask) != mask)
2487 return false;
2488
2489 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2490 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2491 if ((pCtx->cr4 & mask) != 0)
2492 return false;
2493
2494 pVCpu->hm.s.fActive = true;
2495 return true;
2496 }
2497
2498 return false;
2499}
2500
2501
2502/**
2503 * Checks if we need to reschedule due to VMM device heap changes.
2504 *
2505 * @returns true if a reschedule is required, otherwise false.
2506 * @param pVM Pointer to the VM.
2507 * @param pCtx VM execution context.
2508 */
2509VMMR3DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2510{
2511 /*
2512 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2513 * when the unrestricted guest execution feature is missing (VT-x only).
2514 */
2515 if ( pVM->hm.s.vmx.fEnabled
2516 && !pVM->hm.s.vmx.fUnrestrictedGuest
2517 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2518 && !PDMVMMDevHeapIsEnabled(pVM)
2519 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2520 return true;
2521
2522 return false;
2523}
2524
2525
2526/**
2527 * Notification from EM about a rescheduling into hardware assisted execution
2528 * mode.
2529 *
2530 * @param pVCpu Pointer to the current VMCPU.
2531 */
2532VMMR3DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2533{
2534 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2535}
2536
2537
2538/**
2539 * Notification from EM about returning from instruction emulation (REM / EM).
2540 *
2541 * @param pVCpu Pointer to the VMCPU.
2542 */
2543VMMR3DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2544{
2545 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2546}
2547
2548
2549/**
2550 * Checks if we are currently using hardware accelerated raw mode.
2551 *
2552 * @returns true if hardware acceleration is being used, otherwise false.
2553 * @param pVCpu Pointer to the VMCPU.
2554 */
2555VMMR3DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2556{
2557 return pVCpu->hm.s.fActive;
2558}
2559
2560
2561/**
2562 * Checks if we are currently using nested paging.
2563 *
2564 * @returns true if nested paging is being used, otherwise false.
2565 * @param pVM Pointer to the VM.
2566 */
2567VMMR3DECL(bool) HMR3IsNestedPagingActive(PVM pVM)
2568{
2569 return pVM->hm.s.fNestedPaging;
2570}
2571
2572
2573/**
2574 * Checks if we are currently using VPID in VT-x mode.
2575 *
2576 * @returns true if VPID is being used, otherwise false.
2577 * @param pVM Pointer to the VM.
2578 */
2579VMMR3DECL(bool) HMR3IsVPIDActive(PVM pVM)
2580{
2581 return pVM->hm.s.vmx.fVpid;
2582}
2583
2584
2585/**
2586 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2587 *
2588 * @returns true if an internal event is pending, otherwise false.
2589 * @param pVM Pointer to the VM.
2590 */
2591VMMR3DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2592{
2593 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2594}
2595
2596
2597/**
2598 * Checks if the VMX-preemption timer is being used.
2599 *
2600 * @returns true if the VMX-preemption timer is being used, otherwise false.
2601 * @param pVM Pointer to the VM.
2602 */
2603VMMR3DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2604{
2605 return HMIsEnabled(pVM)
2606 && pVM->hm.s.vmx.fEnabled
2607 && pVM->hm.s.vmx.fUsePreemptTimer;
2608}
2609
2610
2611/**
2612 * Restart an I/O instruction that was refused in ring-0
2613 *
2614 * @returns Strict VBox status code. Informational status codes other than the one documented
2615 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2616 * @retval VINF_SUCCESS Success.
2617 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2618 * status code must be passed on to EM.
2619 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2620 *
2621 * @param pVM Pointer to the VM.
2622 * @param pVCpu Pointer to the VMCPU.
2623 * @param pCtx Pointer to the guest CPU context.
2624 */
2625VMMR3DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2626{
2627 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2628
2629 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2630
2631 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2632 || enmType == HMPENDINGIO_INVALID)
2633 return VERR_NOT_FOUND;
2634
2635 VBOXSTRICTRC rcStrict;
2636 switch (enmType)
2637 {
2638 case HMPENDINGIO_PORT_READ:
2639 {
2640 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2641 uint32_t u32Val = 0;
2642
2643 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2644 &u32Val,
2645 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2646 if (IOM_SUCCESS(rcStrict))
2647 {
2648 /* Write back to the EAX register. */
2649 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2650 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2651 }
2652 break;
2653 }
2654
2655 case HMPENDINGIO_PORT_WRITE:
2656 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2657 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2658 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2659 if (IOM_SUCCESS(rcStrict))
2660 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2661 break;
2662
2663 default:
2664 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2665 }
2666
2667 return rcStrict;
2668}
2669
2670
2671/**
2672 * Inject an NMI into a running VM (only VCPU 0!)
2673 *
2674 * @returns boolean
2675 * @param pVM Pointer to the VM.
2676 */
2677VMMR3DECL(int) HMR3InjectNMI(PVM pVM)
2678{
2679 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2680 return VINF_SUCCESS;
2681}
2682
2683
2684/**
2685 * Check fatal VT-x/AMD-V error and produce some meaningful
2686 * log release message.
2687 *
2688 * @param pVM Pointer to the VM.
2689 * @param iStatusCode VBox status code.
2690 */
2691VMMR3DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2692{
2693 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2694 {
2695 switch (iStatusCode)
2696 {
2697 case VERR_VMX_INVALID_VMCS_FIELD:
2698 break;
2699
2700 case VERR_VMX_INVALID_VMCS_PTR:
2701 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
2702 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulVMCSRevision));
2703 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2704 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2705 break;
2706
2707 case VERR_VMX_UNABLE_TO_START_VM:
2708 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError));
2709 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulExitReason));
2710 if (pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2711 {
2712 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2713#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2714 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2715 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2716 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d Cached MSRs %x\n", i, pVM->aCpus[i].hm.s.vmx.cCachedMsrs));
2717#endif
2718 }
2719 /** @todo Log VM-entry event injection control fields
2720 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2721 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2722 break;
2723
2724 case VERR_VMX_UNABLE_TO_RESUME_VM:
2725 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError));
2726 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulExitReason));
2727 break;
2728
2729 case VERR_VMX_INVALID_VMXON_PTR:
2730 break;
2731 }
2732 }
2733
2734 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2735 {
2736 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2737 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2738 }
2739}
2740
2741
2742/**
2743 * Execute state save operation.
2744 *
2745 * @returns VBox status code.
2746 * @param pVM Pointer to the VM.
2747 * @param pSSM SSM operation handle.
2748 */
2749static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2750{
2751 int rc;
2752
2753 Log(("hmR3Save:\n"));
2754
2755 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2756 {
2757 /*
2758 * Save the basic bits - fortunately all the other things can be resynced on load.
2759 */
2760 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2761 AssertRCReturn(rc, rc);
2762 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.errCode);
2763 AssertRCReturn(rc, rc);
2764 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.intInfo);
2765 AssertRCReturn(rc, rc);
2766
2767 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2768 AssertRCReturn(rc, rc);
2769 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2770 AssertRCReturn(rc, rc);
2771 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2772 AssertRCReturn(rc, rc);
2773 }
2774#ifdef VBOX_HM_WITH_GUEST_PATCHING
2775 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2776 AssertRCReturn(rc, rc);
2777 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2778 AssertRCReturn(rc, rc);
2779 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2780 AssertRCReturn(rc, rc);
2781
2782 /* Store all the guest patch records too. */
2783 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2784 AssertRCReturn(rc, rc);
2785
2786 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2787 {
2788 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2789
2790 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2791 AssertRCReturn(rc, rc);
2792
2793 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2794 AssertRCReturn(rc, rc);
2795
2796 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2797 AssertRCReturn(rc, rc);
2798
2799 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2800 AssertRCReturn(rc, rc);
2801
2802 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2803 AssertRCReturn(rc, rc);
2804
2805 AssertCompileSize(HMTPRINSTR, 4);
2806 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2807 AssertRCReturn(rc, rc);
2808
2809 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2819 AssertRCReturn(rc, rc);
2820 }
2821#endif
2822 return VINF_SUCCESS;
2823}
2824
2825
2826/**
2827 * Execute state load operation.
2828 *
2829 * @returns VBox status code.
2830 * @param pVM Pointer to the VM.
2831 * @param pSSM SSM operation handle.
2832 * @param uVersion Data layout version.
2833 * @param uPass The data pass.
2834 */
2835static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2836{
2837 int rc;
2838
2839 Log(("hmR3Load:\n"));
2840 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2841
2842 /*
2843 * Validate version.
2844 */
2845 if ( uVersion != HM_SSM_VERSION
2846 && uVersion != HM_SSM_VERSION_NO_PATCHING
2847 && uVersion != HM_SSM_VERSION_2_0_X)
2848 {
2849 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2850 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2851 }
2852 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2853 {
2854 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2855 AssertRCReturn(rc, rc);
2856 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.errCode);
2857 AssertRCReturn(rc, rc);
2858 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.intInfo);
2859 AssertRCReturn(rc, rc);
2860
2861 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2862 {
2863 uint32_t val;
2864
2865 rc = SSMR3GetU32(pSSM, &val);
2866 AssertRCReturn(rc, rc);
2867 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2868
2869 rc = SSMR3GetU32(pSSM, &val);
2870 AssertRCReturn(rc, rc);
2871 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2872
2873 rc = SSMR3GetU32(pSSM, &val);
2874 AssertRCReturn(rc, rc);
2875 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2876 }
2877 }
2878#ifdef VBOX_HM_WITH_GUEST_PATCHING
2879 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2880 {
2881 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2882 AssertRCReturn(rc, rc);
2883 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2884 AssertRCReturn(rc, rc);
2885 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2886 AssertRCReturn(rc, rc);
2887
2888 /* Fetch all TPR patch records. */
2889 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2890 AssertRCReturn(rc, rc);
2891
2892 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2893 {
2894 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2895
2896 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2897 AssertRCReturn(rc, rc);
2898
2899 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2900 AssertRCReturn(rc, rc);
2901
2902 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2903 AssertRCReturn(rc, rc);
2904
2905 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2906 AssertRCReturn(rc, rc);
2907
2908 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2909 AssertRCReturn(rc, rc);
2910
2911 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2912 AssertRCReturn(rc, rc);
2913
2914 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2915 pVM->hm.s.fTPRPatchingActive = true;
2916
2917 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2918
2919 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2920 AssertRCReturn(rc, rc);
2921
2922 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2923 AssertRCReturn(rc, rc);
2924
2925 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2926 AssertRCReturn(rc, rc);
2927
2928 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2929 AssertRCReturn(rc, rc);
2930
2931 Log(("hmR3Load: patch %d\n", i));
2932 Log(("Key = %x\n", pPatch->Core.Key));
2933 Log(("cbOp = %d\n", pPatch->cbOp));
2934 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2935 Log(("type = %d\n", pPatch->enmType));
2936 Log(("srcop = %d\n", pPatch->uSrcOperand));
2937 Log(("dstop = %d\n", pPatch->uDstOperand));
2938 Log(("cFaults = %d\n", pPatch->cFaults));
2939 Log(("target = %x\n", pPatch->pJumpTarget));
2940 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2941 AssertRC(rc);
2942 }
2943 }
2944#endif
2945
2946 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2947 if (HMIsEnabled(pVM))
2948 {
2949 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2950 {
2951 PVMCPU pVCpu = &pVM->aCpus[i];
2952
2953 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2954 }
2955 }
2956 return VINF_SUCCESS;
2957}
2958
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