VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp

Last change on this file was 103270, checked in by vboxsync, 3 months ago

VMM/HM: Partly revert r161536, RT_FALLTHROUGH is not necessary here, bugref:3409

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1/* $Id: HM.cpp 103270 2024-02-08 08:28:49Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_hm HM - Hardware Assisted Virtualization Manager
29 *
30 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
31 * extensions.
32 *
33 * {summary of what HM does}
34 *
35 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
36 * however that was cumbersome to write and parse for such a central component,
37 * so it was shortened to HM when refactoring the code in the 4.3 development
38 * cycle.
39 *
40 * {add sections with more details}
41 *
42 * @sa @ref grp_hm
43 */
44
45
46/*********************************************************************************************************************************
47* Header Files *
48*********************************************************************************************************************************/
49#define LOG_GROUP LOG_GROUP_HM
50#define VMCPU_INCL_CPUM_GST_CTX
51#include <VBox/vmm/cpum.h>
52#include <VBox/vmm/stam.h>
53#include <VBox/vmm/em.h>
54#include <VBox/vmm/pdmapi.h>
55#include <VBox/vmm/pgm.h>
56#include <VBox/vmm/ssm.h>
57#include <VBox/vmm/gim.h>
58#include <VBox/vmm/gcm.h>
59#include <VBox/vmm/trpm.h>
60#include <VBox/vmm/dbgf.h>
61#include <VBox/vmm/iom.h>
62#include <VBox/vmm/iem.h>
63#include <VBox/vmm/selm.h>
64#include <VBox/vmm/nem.h>
65#include <VBox/vmm/hm_vmx.h>
66#include <VBox/vmm/hm_svm.h>
67#include "HMInternal.h"
68#include <VBox/vmm/vmcc.h>
69#include <VBox/err.h>
70#include <VBox/param.h>
71
72#include <iprt/assert.h>
73#include <VBox/log.h>
74#include <iprt/asm.h>
75#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
76# include <iprt/asm-amd64-x86.h>
77#endif
78#include <iprt/env.h>
79#include <iprt/thread.h>
80
81
82/*********************************************************************************************************************************
83* Defined Constants And Macros *
84*********************************************************************************************************************************/
85/** @def HMVMX_REPORT_FEAT
86 * Reports VT-x feature to the release log.
87 *
88 * @param a_uAllowed1 Mask of allowed-1 feature bits.
89 * @param a_uAllowed0 Mask of allowed-0 feature bits.
90 * @param a_StrDesc The description string to report.
91 * @param a_Featflag Mask of the feature to report.
92 */
93#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
94 do { \
95 if ((a_uAllowed1) & (a_Featflag)) \
96 { \
97 if ((a_uAllowed0) & (a_Featflag)) \
98 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
99 else \
100 LogRel(("HM: " a_StrDesc "\n")); \
101 } \
102 else \
103 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
104 } while (0)
105
106/** @def HMVMX_REPORT_ALLOWED_FEAT
107 * Reports an allowed VT-x feature to the release log.
108 *
109 * @param a_uAllowed1 Mask of allowed-1 feature bits.
110 * @param a_StrDesc The description string to report.
111 * @param a_FeatFlag Mask of the feature to report.
112 */
113#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
114 do { \
115 if ((a_uAllowed1) & (a_FeatFlag)) \
116 LogRel(("HM: " a_StrDesc "\n")); \
117 else \
118 LogRel(("HM: " a_StrDesc " not supported\n")); \
119 } while (0)
120
121/** @def HMVMX_REPORT_MSR_CAP
122 * Reports MSR feature capability.
123 *
124 * @param a_MsrCaps Mask of MSR feature bits.
125 * @param a_StrDesc The description string to report.
126 * @param a_fCap Mask of the feature to report.
127 */
128#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
129 do { \
130 if ((a_MsrCaps) & (a_fCap)) \
131 LogRel(("HM: " a_StrDesc "\n")); \
132 } while (0)
133
134/** @def HMVMX_LOGREL_FEAT
135 * Dumps a feature flag from a bitmap of features to the release log.
136 *
137 * @param a_fVal The value of all the features.
138 * @param a_fMask The specific bitmask of the feature.
139 */
140#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
141 do { \
142 if ((a_fVal) & (a_fMask)) \
143 LogRel(("HM: %s\n", #a_fMask)); \
144 } while (0)
145
146
147/*********************************************************************************************************************************
148* Internal Functions *
149*********************************************************************************************************************************/
150static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
151static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
152static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
153static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
154static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
155static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156static int hmR3InitFinalizeR3(PVM pVM);
157static int hmR3InitFinalizeR0(PVM pVM);
158static int hmR3InitFinalizeR0Intel(PVM pVM);
159static int hmR3InitFinalizeR0Amd(PVM pVM);
160static int hmR3TermCPU(PVM pVM);
161
162
163#ifdef VBOX_WITH_STATISTICS
164/**
165 * Returns the name of the hardware exception.
166 *
167 * @returns The name of the hardware exception.
168 * @param uVector The exception vector.
169 */
170static const char *hmR3GetXcptName(uint8_t uVector)
171{
172 switch (uVector)
173 {
174 case X86_XCPT_DE: return "#DE";
175 case X86_XCPT_DB: return "#DB";
176 case X86_XCPT_NMI: return "#NMI";
177 case X86_XCPT_BP: return "#BP";
178 case X86_XCPT_OF: return "#OF";
179 case X86_XCPT_BR: return "#BR";
180 case X86_XCPT_UD: return "#UD";
181 case X86_XCPT_NM: return "#NM";
182 case X86_XCPT_DF: return "#DF";
183 case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
184 case X86_XCPT_TS: return "#TS";
185 case X86_XCPT_NP: return "#NP";
186 case X86_XCPT_SS: return "#SS";
187 case X86_XCPT_GP: return "#GP";
188 case X86_XCPT_PF: return "#PF";
189 case X86_XCPT_MF: return "#MF";
190 case X86_XCPT_AC: return "#AC";
191 case X86_XCPT_MC: return "#MC";
192 case X86_XCPT_XF: return "#XF";
193 case X86_XCPT_VE: return "#VE";
194 case X86_XCPT_CP: return "#CP";
195 case X86_XCPT_VC: return "#VC";
196 case X86_XCPT_SX: return "#SX";
197 }
198 return "Reserved";
199}
200#endif /* VBOX_WITH_STATISTICS */
201
202
203/**
204 * Initializes the HM.
205 *
206 * This is the very first component to really do init after CFGM so that we can
207 * establish the predominant execution engine for the VM prior to initializing
208 * other modules. It takes care of NEM initialization if needed (HM disabled or
209 * not available in HW).
210 *
211 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
212 * hypervisor API via NEM, and then back on raw-mode if that isn't available
213 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
214 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
215 * X, OS/2 and others).
216 *
217 * Note that a lot of the set up work is done in ring-0 and thus postponed till
218 * the ring-3 and ring-0 callback to HMR3InitCompleted.
219 *
220 * @returns VBox status code.
221 * @param pVM The cross context VM structure.
222 *
223 * @remarks Be careful with what we call here, since most of the VMM components
224 * are uninitialized.
225 */
226VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
227{
228 LogFlowFunc(("\n"));
229
230 /*
231 * Assert alignment and sizes.
232 */
233 AssertCompileMemberAlignment(VM, hm.s, 32);
234 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
235
236 /*
237 * Register the saved state data unit.
238 */
239 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
240 NULL, NULL, NULL,
241 NULL, hmR3Save, NULL,
242 NULL, hmR3Load, NULL);
243 if (RT_FAILURE(rc))
244 return rc;
245
246 /*
247 * Read configuration.
248 */
249 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
250
251 /*
252 * Validate the HM settings.
253 */
254 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
255 "HMForced" /* implied 'true' these days */
256 "|UseNEMInstead"
257 "|FallbackToNEM"
258 "|FallbackToIEM"
259 "|EnableNestedPaging"
260 "|EnableUX"
261 "|EnableLargePages"
262 "|EnableVPID"
263 "|IBPBOnVMExit"
264 "|IBPBOnVMEntry"
265 "|SpecCtrlByHost"
266 "|L1DFlushOnSched"
267 "|L1DFlushOnVMEntry"
268 "|MDSClearOnSched"
269 "|MDSClearOnVMEntry"
270 "|TPRPatchingEnabled"
271 "|64bitEnabled"
272 "|Exclusive"
273 "|MaxResumeLoops"
274 "|VmxPleGap"
275 "|VmxPleWindow"
276 "|VmxLbr"
277 "|UseVmxPreemptTimer"
278 "|SvmPauseFilter"
279 "|SvmPauseFilterThreshold"
280 "|SvmVirtVmsaveVmload"
281 "|SvmVGif"
282 "|LovelyMesaDrvWorkaround"
283 "|MissingOS2TlbFlushWorkaround"
284 "|AlwaysInterceptVmxMovDRx"
285 , "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
286 if (RT_FAILURE(rc))
287 return rc;
288
289 /** @cfgm{/HM/HMForced, bool, false}
290 * Forces hardware virtualization, no falling back on raw-mode. HM must be
291 * enabled, i.e. /HMEnabled must be true. */
292 bool const fHMForced = true;
293#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
294 AssertRelease(pVM->fHMEnabled);
295#else
296 AssertRelease(!pVM->fHMEnabled);
297#endif
298
299 /** @cfgm{/HM/UseNEMInstead, bool, true}
300 * Don't use HM, use NEM instead. */
301 bool fUseNEMInstead = false;
302 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
303 AssertRCReturn(rc, rc);
304 if (fUseNEMInstead && pVM->fHMEnabled)
305 {
306 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
307 pVM->fHMEnabled = false;
308 }
309
310 /** @cfgm{/HM/FallbackToNEM, bool, true}
311 * Enables fallback on NEM. */
312 bool fFallbackToNEM = true;
313 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
314 AssertRCReturn(rc, rc);
315
316 /** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
317 * Enables fallback on NEM. */
318#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
319 bool fFallbackToIEM = false;
320#else
321 bool fFallbackToIEM = true;
322#endif
323 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
324 AssertRCReturn(rc, rc);
325
326 /** @cfgm{/HM/EnableNestedPaging, bool, false}
327 * Enables nested paging (aka extended page tables). */
328 bool fAllowNestedPaging = false;
329 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
330 AssertRCReturn(rc, rc);
331
332 /** @cfgm{/HM/EnableUX, bool, true}
333 * Enables the VT-x unrestricted execution feature. */
334 bool fAllowUnrestricted = true;
335 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
336 AssertRCReturn(rc, rc);
337
338 /** @cfgm{/HM/EnableLargePages, bool, false}
339 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
340 * page table walking and maybe better TLB hit rate in some cases. */
341 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
342 AssertRCReturn(rc, rc);
343
344 /** @cfgm{/HM/EnableVPID, bool, false}
345 * Enables the VT-x VPID feature. */
346 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
347 AssertRCReturn(rc, rc);
348
349 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
350 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
351 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
352 AssertRCReturn(rc, rc);
353
354 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
355 * Enables AMD64 cpu features.
356 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
357 * already have the support. */
358#ifdef VBOX_WITH_64_BITS_GUESTS
359 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
360 AssertLogRelRCReturn(rc, rc);
361#else
362 pVM->hm.s.fAllow64BitGuestsCfg = false;
363#endif
364
365 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
366 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
367 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
368 * latest PAUSE instruction to be start of a new PAUSE loop.
369 */
370 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
371 AssertRCReturn(rc, rc);
372
373 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
374 * The pause-filter exiting window in TSC ticks. When the number of ticks
375 * between the current PAUSE instruction and first PAUSE of a loop exceeds
376 * VmxPleWindow, a VM-exit is triggered.
377 *
378 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
379 */
380 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
381 AssertRCReturn(rc, rc);
382
383 /** @cfgm{/HM/VmxLbr, bool, false}
384 * Whether to enable LBR for the guest. This is disabled by default as it's only
385 * useful while debugging and enabling it causes a noticeable performance hit. */
386 rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
387 AssertRCReturn(rc, rc);
388
389 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
390 * A counter that is decrement each time a PAUSE instruction is executed by the
391 * guest. When the counter is 0, a \#VMEXIT is triggered.
392 *
393 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
394 */
395 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
396 AssertRCReturn(rc, rc);
397
398 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
399 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
400 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
401 * PauseFilter count is reset to its initial value. However, if PAUSE is
402 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
403 * be triggered.
404 *
405 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
406 * activated.
407 */
408 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
409 AssertRCReturn(rc, rc);
410
411 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
412 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
413 * available. */
414 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
415 AssertRCReturn(rc, rc);
416
417 /** @cfgm{/HM/SvmVGif, bool, true}
418 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
419 * if it's available. */
420 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
421 AssertRCReturn(rc, rc);
422
423 /** @cfgm{/HM/SvmLbrVirt, bool, false}
424 * Whether to make use of the LBR virtualization feature of the CPU if it's
425 * available. This is disabled by default as it's only useful while debugging
426 * and enabling it causes a small hit to performance. */
427 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
428 AssertRCReturn(rc, rc);
429
430 /** @cfgm{/HM/Exclusive, bool}
431 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
432 * global init for each host CPU. If false, we do local init each time we wish
433 * to execute guest code.
434 *
435 * On Windows, default is false due to the higher risk of conflicts with other
436 * hypervisors.
437 *
438 * On Mac OS X, this setting is ignored since the code does not handle local
439 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
440 */
441#if defined(RT_OS_DARWIN)
442 pVM->hm.s.fGlobalInit = true;
443#else
444 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
445# if defined(RT_OS_WINDOWS)
446 false
447# else
448 true
449# endif
450 );
451 AssertLogRelRCReturn(rc, rc);
452#endif
453
454 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
455 * The number of times to resume guest execution before we forcibly return to
456 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
457 * determines the default value. */
458 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
459 AssertLogRelRCReturn(rc, rc);
460
461 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
462 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
463 * available. */
464 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
465 AssertLogRelRCReturn(rc, rc);
466
467 /** @cfgm{/HM/IBPBOnVMExit, bool}
468 * Costly paranoia setting. */
469 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
470 AssertLogRelRCReturn(rc, rc);
471
472 /** @cfgm{/HM/IBPBOnVMEntry, bool}
473 * Costly paranoia setting. */
474 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
475 AssertLogRelRCReturn(rc, rc);
476
477 /** @cfgm{/HM/L1DFlushOnSched, bool, true}
478 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
479 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
480 AssertLogRelRCReturn(rc, rc);
481
482 /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
483 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
484 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
485 AssertLogRelRCReturn(rc, rc);
486
487 /* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
488 if (pVM->hm.s.fL1dFlushOnVmEntry)
489 pVM->hm.s.fL1dFlushOnSched = false;
490
491 /** @cfgm{/HM/SpecCtrlByHost, bool}
492 * Another expensive paranoia setting. */
493 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
494 AssertLogRelRCReturn(rc, rc);
495
496 /** @cfgm{/HM/MDSClearOnSched, bool, true}
497 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
498 * ignored on CPUs that aren't affected. */
499 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
500 AssertLogRelRCReturn(rc, rc);
501
502 /** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
503 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
504 * ignored on CPUs that aren't affected. */
505 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
506 AssertLogRelRCReturn(rc, rc);
507
508 /* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
509 if (pVM->hm.s.fMdsClearOnVmEntry)
510 pVM->hm.s.fMdsClearOnSched = false;
511
512 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
513 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
514 * the hypervisor it is running under. */
515 bool fMesaWorkaround;
516 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
517 AssertLogRelRCReturn(rc, rc);
518 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
519 {
520 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
521 pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
522 }
523
524 /** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
525 * Workaround OS/2 not flushing the TLB after page directory and page table
526 * modifications when returning to protected mode from a real mode call
527 * (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
528 rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
529 AssertLogRelRCReturn(rc, rc);
530
531 /** @cfgm{/HM/AlwaysInterceptVmxMovDRx,int8_t,0}
532 * Whether to always intercept MOV DRx when using VMX.
533 * The value is a tristate: 1 for always intercepting, -1 for lazy intercept,
534 * and 0 for default. The default means that it's always intercepted when the
535 * host DR6 contains bits not known to the guest.
536 *
537 * With the introduction of transactional synchronization extensions new
538 * instructions, aka TSX-NI or RTM, bit 16 in DR6 is cleared to indicate that a
539 * \#DB was related to a transaction. The bit is also cleared when writing zero
540 * to it, so guest lazily resetting DR6 by writing 0 to it, ends up with an
541 * unexpected value. Similiarly, bit 11 in DR7 is used to enabled RTM
542 * debugging support and therefore writable by the guest.
543 *
544 * Out of caution/paranoia, we will by default intercept DRx moves when setting
545 * DR6 to zero (on the host) doesn't result in 0xffff0ff0 (X86_DR6_RA1_MASK).
546 * Note that it seems DR6.RTM remains writable even after the microcode updates
547 * disabling TSX. */
548 rc = CFGMR3QueryS8Def(pCfgHm, "AlwaysInterceptVmxMovDRx", &pVM->hm.s.vmx.fAlwaysInterceptMovDRxCfg, 0);
549 AssertLogRelRCReturn(rc, rc);
550
551 /*
552 * Check if VT-x or AMD-v support according to the users wishes.
553 */
554 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
555 * VERR_SVM_IN_USE. */
556 if (pVM->fHMEnabled)
557 {
558 uint32_t fCaps;
559 rc = SUPR3QueryVTCaps(&fCaps);
560 if (RT_SUCCESS(rc))
561 {
562 if (fCaps & SUPVTCAPS_AMD_V)
563 {
564 pVM->hm.s.svm.fSupported = true;
565 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
566 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
567 }
568 else if (fCaps & SUPVTCAPS_VT_X)
569 {
570 const char *pszWhy;
571 rc = SUPR3QueryVTxSupported(&pszWhy);
572 if (RT_SUCCESS(rc))
573 {
574 pVM->hm.s.vmx.fSupported = true;
575 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
576 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
577 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
578 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
579 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
580 }
581 else
582 {
583 /*
584 * Before failing, try fallback to NEM if we're allowed to do that.
585 */
586 pVM->fHMEnabled = false;
587 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
588 if (fFallbackToNEM)
589 {
590 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
591 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
592
593 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
594 if ( RT_SUCCESS(rc2)
595 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
596 rc = VINF_SUCCESS;
597 }
598 if (RT_FAILURE(rc))
599 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
600 }
601 }
602 else
603 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
604 VERR_INTERNAL_ERROR_5);
605
606 /*
607 * Disable nested paging and unrestricted guest execution now if they're
608 * configured so that CPUM can make decisions based on our configuration.
609 */
610 if ( fAllowNestedPaging
611 && (fCaps & SUPVTCAPS_NESTED_PAGING))
612 {
613 pVM->hm.s.fNestedPagingCfg = true;
614 if (fCaps & SUPVTCAPS_VT_X)
615 {
616 if ( fAllowUnrestricted
617 && (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
618 pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
619 else
620 Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
621 }
622 }
623 else
624 Assert(!pVM->hm.s.fNestedPagingCfg);
625 }
626 else
627 {
628 const char *pszMsg;
629 switch (rc)
630 {
631 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
632 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
633 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
634 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
635 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
636 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
637 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
638 case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
639 default:
640 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
641 }
642
643 /*
644 * Before failing, try fallback to NEM if we're allowed to do that.
645 */
646 pVM->fHMEnabled = false;
647 if (fFallbackToNEM)
648 {
649 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
650 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
651 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
652 if ( RT_SUCCESS(rc2)
653 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
654 {
655 rc = VINF_SUCCESS;
656
657 /* For some reason, HM is in charge or large pages. Make sure to enable them: */
658 PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
659 }
660 }
661
662 /*
663 * Then try fall back on IEM if NEM isn't available and we're allowed to.
664 */
665 if (RT_FAILURE(rc))
666 {
667 if ( fFallbackToIEM
668 && (!fFallbackToNEM || rc == VERR_NEM_NOT_AVAILABLE || rc == VERR_SUP_DRIVERLESS))
669 {
670 LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
671 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
672#ifdef VBOX_WITH_PGM_NEM_MODE
673 PGMR3EnableNemMode(pVM);
674#endif
675 }
676 else
677 return VM_SET_ERROR(pVM, rc, pszMsg);
678 }
679 }
680 }
681 else
682 {
683 /*
684 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
685 */
686 rc = VERR_NEM_NOT_AVAILABLE;
687 if (fUseNEMInstead)
688 {
689 rc = NEMR3Init(pVM, false /*fFallback*/, true);
690 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
691 if (RT_SUCCESS(rc))
692 {
693 /* For some reason, HM is in charge or large pages. Make sure to enable them: */
694 PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
695 }
696 else if (!fFallbackToIEM || rc != VERR_NEM_NOT_AVAILABLE)
697 return rc;
698 }
699
700 if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
701 {
702 LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
703 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
704#ifdef VBOX_WITH_PGM_NEM_MODE
705 PGMR3EnableNemMode(pVM);
706#endif
707 }
708
709 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
710 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
711 return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
712 }
713
714 if (pVM->fHMEnabled)
715 {
716 /*
717 * Register info handlers now that HM is used for sure.
718 */
719 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
720 AssertRCReturn(rc, rc);
721
722 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
723 DBGFINFO_FLAGS_ALL_EMTS);
724 AssertRCReturn(rc, rc);
725
726 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
727 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
728 AssertRCReturn(rc, rc);
729
730 rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
731 AssertRCReturn(rc, rc);
732 }
733
734 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
735 return VINF_SUCCESS;
736}
737
738
739/**
740 * Initializes HM components after ring-3 phase has been fully initialized.
741 *
742 * @returns VBox status code.
743 * @param pVM The cross context VM structure.
744 */
745static int hmR3InitFinalizeR3(PVM pVM)
746{
747 LogFlowFunc(("\n"));
748
749 if (!HMIsEnabled(pVM))
750 return VINF_SUCCESS;
751
752 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
753 {
754 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
755 pVCpu->hm.s.fActive = false;
756 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
757 pVCpu->hm.s.fGCMTrapXcptDE = GCMShouldTrapXcptDE(pVCpu); /* Is safe to call now since GCMR3Init() has completed. */
758 }
759
760#if defined(RT_ARCH_AMD64) ||defined(RT_ARCH_X86)
761 /*
762 * Check if L1D flush is needed/possible.
763 */
764 if ( !g_CpumHostFeatures.s.fFlushCmd
765 || g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
766 || g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
767 || g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d
768 || g_CpumHostFeatures.s.fArchRdclNo)
769 pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
770
771 /*
772 * Check if MDS flush is needed/possible.
773 * On atoms and knight family CPUs, we will only allow clearing on scheduling.
774 */
775 if ( !g_CpumHostFeatures.s.fMdsClear
776 || g_CpumHostFeatures.s.fArchMdsNo)
777 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
778 else if ( ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
779 && g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
780 || ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
781 && g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
782 {
783 if (!pVM->hm.s.fMdsClearOnSched)
784 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
785 pVM->hm.s.fMdsClearOnVmEntry = false;
786 }
787 else if ( g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
788 || g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
789 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
790#endif
791
792 /*
793 * Statistics.
794 */
795#ifdef VBOX_WITH_STATISTICS
796 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
797 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
798 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
799 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
800 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
801#endif
802
803#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
804 bool const fCpuSupportsVmx = ASMIsIntelCpu() || ASMIsViaCentaurCpu() || ASMIsShanghaiCpu();
805#else
806 bool const fCpuSupportsVmx = false;
807#endif
808 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
809 {
810 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
811 PHMCPU pHmCpu = &pVCpu->hm.s;
812 int rc;
813
814# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
815 rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
816 AssertRC(rc); \
817 } while (0)
818# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
819 HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
820
821#ifdef VBOX_WITH_STATISTICS
822 HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
823 HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
824 HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
825 HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
826 HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
827 HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
828 HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
829 HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
830 HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
831 HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
832 HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
833 HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
834 HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
835 HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
836# ifdef HM_PROFILE_EXIT_DISPATCH
837 HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
838 "/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
839# endif
840#endif
841# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
842
843 HM_REG_COUNTER(&pHmCpu->StatImportGuestStateFallback, "/HM/CPU%u/ImportGuestStateFallback", "Times vmxHCImportGuestState took the fallback code path.");
844 HM_REG_COUNTER(&pHmCpu->StatReadToTransientFallback, "/HM/CPU%u/ReadToTransientFallback", "Times vmxHCReadToTransient took the fallback code path.");
845#ifdef VBOX_WITH_STATISTICS
846 HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
847 HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
848 HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/ExitNestedGuest/All", "Total nested-guest exits.");
849 HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
850 HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
851 HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
852 HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
853 HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
854 HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
855 HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
856 HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
857 HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
858 HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
859 HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
860 HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
861 HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
862 HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
863#endif
864 HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
865 if (fCpuSupportsVmx)
866 HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
867#ifdef VBOX_WITH_STATISTICS
868 HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
869 HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
870 HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
871 HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
872 HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
873 HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
874 HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
875 HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
876 HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
877 HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
878 HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
879 HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
880 HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
881 HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
882 HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
883 HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
884 HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
885 HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
886 HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
887 HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
888 HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
889 HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
890 HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
891 HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
892 HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
893 HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
894 HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
895 HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
896#endif
897 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
898 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
899 HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
900#ifdef VBOX_WITH_STATISTICS
901 HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
902 HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
903 HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
904
905 HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
906 HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
907 HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
908 HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
909 HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
910 HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
911 HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
912 HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
913 HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
914 HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
915 HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
916 HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
917#endif
918 HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
919#ifdef VBOX_WITH_STATISTICS
920 HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
921
922 HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
923 HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
924 HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
925 HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
926 HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
927 HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
928
929 HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
930 HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
931 HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
932 HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
933 HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
934 HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
935 HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
936 HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
937 HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
938 HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
939 HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
940 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
941 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
942 HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
943 HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
944
945 HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
946 HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
947 HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
948
949 HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
950 HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
951 HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
952
953 HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
954 HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
955 HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
956 HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
957
958 if (fCpuSupportsVmx)
959 {
960 HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
961 HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
962 HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
963 HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
964 }
965
966 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
967 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
968 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
969
970 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
971 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
972 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
973
974 HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
975 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
976 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
977 HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
978 HM_REG_COUNTER(&pHmCpu->StatVmxCheck1, "/HM/CPU%u/VMXCheck/1", "Could not use VMX due to unsuitable state and no VMMDev heap");
979 HM_REG_COUNTER(&pHmCpu->StatVmxCheck2, "/HM/CPU%u/VMXCheck/2", "CR0/CR4 fixed stuff.");
980 HM_REG_COUNTER(&pHmCpu->StatVmxCheckDisabled, "/HM/CPU%u/VMXCheck/Disabled", "VMX is not enabled.");
981 HM_REG_COUNTER(&pHmCpu->StatVmxCheckOk, "/HM/CPU%u/VMXCheck/Ok", "We could do VMX!");
982#endif
983 if (fCpuSupportsVmx)
984 {
985 HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
986 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
987 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
988 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
989 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
990 }
991#ifdef VBOX_WITH_STATISTICS
992 /*
993 * Guest Exit reason stats.
994 */
995 if (fCpuSupportsVmx)
996 {
997 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
998 {
999 const char *pszExitName = HMGetVmxExitName(j);
1000 if (pszExitName)
1001 {
1002 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1003 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1004 AssertRCReturn(rc, rc);
1005 }
1006 }
1007 }
1008 else
1009 {
1010 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1011 {
1012 const char *pszExitName = HMGetSvmExitName(j);
1013 if (pszExitName)
1014 {
1015 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1016 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1017 AssertRC(rc);
1018 }
1019 }
1020 }
1021 HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
1022
1023#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1024 /*
1025 * Nested-guest VM-exit reason stats.
1026 */
1027 if (fCpuSupportsVmx)
1028 {
1029 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1030 {
1031 const char *pszExitName = HMGetVmxExitName(j);
1032 if (pszExitName)
1033 {
1034 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1035 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1036 AssertRC(rc);
1037 }
1038 }
1039 HM_REG_COUNTER(&pHmCpu->StatNestedExitACSplitLock, "/HM/CPU%u/ExitNestedGuest/Trap/#AC-split-lock", "Nested-guest triggered #AC due to split-lock being enabled on the host.");
1040 }
1041 else
1042 {
1043 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1044 {
1045 const char *pszExitName = HMGetSvmExitName(j);
1046 if (pszExitName)
1047 {
1048 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1049 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1050 AssertRC(rc);
1051 }
1052 }
1053 }
1054 HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/ExitNestedGuest/Reason/#NPF", "Nested page faults");
1055#endif
1056
1057 /*
1058 * Injected interrupts stats.
1059 */
1060 char szDesc[64];
1061 for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1062 {
1063 RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1064 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1065 STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1066 AssertRC(rc);
1067 }
1068
1069 /*
1070 * Injected exception stats.
1071 */
1072 for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1073 {
1074 RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1075 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1076 STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1077 AssertRC(rc);
1078 }
1079
1080#endif /* VBOX_WITH_STATISTICS */
1081#undef HM_REG_COUNTER
1082#undef HM_REG_PROFILE
1083#undef HM_REG_STAT
1084 }
1085
1086 return VINF_SUCCESS;
1087}
1088
1089
1090/**
1091 * Called when a init phase has completed.
1092 *
1093 * @returns VBox status code.
1094 * @param pVM The cross context VM structure.
1095 * @param enmWhat The phase that completed.
1096 */
1097VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1098{
1099 switch (enmWhat)
1100 {
1101 case VMINITCOMPLETED_RING3:
1102 return hmR3InitFinalizeR3(pVM);
1103 case VMINITCOMPLETED_RING0:
1104 return hmR3InitFinalizeR0(pVM);
1105 default:
1106 return VINF_SUCCESS;
1107 }
1108}
1109
1110
1111/**
1112 * Turns off normal raw mode features.
1113 *
1114 * @param pVM The cross context VM structure.
1115 */
1116static void hmR3DisableRawMode(PVM pVM)
1117{
1118/** @todo r=bird: HM shouldn't be doing this crap. */
1119 /* Reinit the paging mode to force the new shadow mode. */
1120 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1121 {
1122 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1123 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1124 }
1125}
1126
1127
1128/**
1129 * Initialize VT-x or AMD-V.
1130 *
1131 * @returns VBox status code.
1132 * @param pVM The cross context VM structure.
1133 */
1134static int hmR3InitFinalizeR0(PVM pVM)
1135{
1136 int rc;
1137
1138 /*
1139 * Since HM is in charge of large pages, if large pages isn't supported on Intel CPUs,
1140 * we must disable it here. Doing it here rather than in hmR3InitFinalizeR0Intel covers
1141 * the case of informing PGM even when NEM is the execution engine.
1142 */
1143 if ( pVM->hm.s.fLargePages
1144 && pVM->hm.s.vmx.fSupported
1145 && !(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M))
1146 {
1147 pVM->hm.s.fLargePages = false;
1148 PGMSetLargePageUsage(pVM, false);
1149 LogRel(("HM: Disabled large page support as the CPU doesn't allow EPT PDEs to map 2MB pages\n"));
1150 }
1151
1152 if (!HMIsEnabled(pVM))
1153 return VINF_SUCCESS;
1154
1155 /*
1156 * Hack to allow users to work around broken BIOSes that incorrectly set
1157 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1158 */
1159 if ( !pVM->hm.s.vmx.fSupported
1160 && !pVM->hm.s.svm.fSupported
1161 && pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1162 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1163 {
1164 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1165 pVM->hm.s.svm.fSupported = true;
1166 pVM->hm.s.svm.fIgnoreInUseError = true;
1167 pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1168 }
1169
1170 /*
1171 * Report ring-0 init errors.
1172 */
1173 if ( !pVM->hm.s.vmx.fSupported
1174 && !pVM->hm.s.svm.fSupported)
1175 {
1176 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1177 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1178 switch (pVM->hm.s.ForR3.rcInit)
1179 {
1180 case VERR_VMX_IN_VMX_ROOT_MODE:
1181 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1182 case VERR_VMX_NO_VMX:
1183 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1184 case VERR_VMX_MSR_VMX_DISABLED:
1185 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1186 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1187 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1188 case VERR_VMX_MSR_LOCKING_FAILED:
1189 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1190 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1191 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1192 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1193 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1194
1195 case VERR_SVM_IN_USE:
1196 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1197 case VERR_SVM_NO_SVM:
1198 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1199 case VERR_SVM_DISABLED:
1200 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1201 }
1202 return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1203 }
1204
1205 /*
1206 * Enable VT-x or AMD-V on all host CPUs.
1207 */
1208 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1209 if (RT_FAILURE(rc))
1210 {
1211 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1212 HMR3CheckError(pVM, rc);
1213 return rc;
1214 }
1215
1216 /*
1217 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1218 * (Main should have taken care of this already)
1219 */
1220 if (!PDMHasIoApic(pVM))
1221 {
1222 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1223 pVM->hm.s.fTprPatchingAllowed = false;
1224 }
1225
1226 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1227 pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1228 pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1229
1230 /*
1231 * Do the vendor specific initialization
1232 *
1233 * Note! We disable release log buffering here since we're doing relatively
1234 * lot of logging and doesn't want to hit the disk with each LogRel
1235 * statement.
1236 */
1237 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1238 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1239 if (pVM->hm.s.vmx.fSupported)
1240 rc = hmR3InitFinalizeR0Intel(pVM);
1241 else
1242 rc = hmR3InitFinalizeR0Amd(pVM);
1243 LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1244 : "HM: VT-x/AMD-V init method: Local\n"));
1245 RTLogRelSetBuffering(fOldBuffered);
1246 pVM->hm.s.fInitialized = true;
1247
1248 return rc;
1249}
1250
1251
1252/**
1253 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1254 */
1255static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1256{
1257 NOREF(pVM);
1258 NOREF(pvAllocation);
1259 NOREF(GCPhysAllocation);
1260}
1261
1262
1263/**
1264 * Returns a description of the VMCS (and associated regions') memory type given the
1265 * IA32_VMX_BASIC MSR.
1266 *
1267 * @returns The descriptive memory type.
1268 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1269 */
1270static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1271{
1272 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1273 switch (uMemType)
1274 {
1275 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1276 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1277 }
1278 return "Unknown";
1279}
1280
1281
1282/**
1283 * Returns a single-line description of all the activity-states supported by the CPU
1284 * given the IA32_VMX_MISC MSR.
1285 *
1286 * @returns All supported activity states.
1287 * @param uMsrMisc IA32_VMX_MISC MSR value.
1288 */
1289static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1290{
1291 static const char * const s_apszActStates[] =
1292 {
1293 "",
1294 " ( HLT )",
1295 " ( SHUTDOWN )",
1296 " ( HLT SHUTDOWN )",
1297 " ( SIPI_WAIT )",
1298 " ( HLT SIPI_WAIT )",
1299 " ( SHUTDOWN SIPI_WAIT )",
1300 " ( HLT SHUTDOWN SIPI_WAIT )"
1301 };
1302 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1303 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1304 return s_apszActStates[idxActStates];
1305}
1306
1307
1308/**
1309 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1310 *
1311 * @param fFeatMsr The feature control MSR value.
1312 */
1313static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1314{
1315 uint64_t const val = fFeatMsr;
1316 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1317 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1318 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1319 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1320 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1321 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1322 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1323 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1324 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1325 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1326 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1327 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1328 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1329 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1330 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1331 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1332 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1333}
1334
1335
1336/**
1337 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1338 *
1339 * @param uBasicMsr The VMX basic MSR value.
1340 */
1341static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1342{
1343 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1344 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1345 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1346 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1347 "< 4 GB" : "None"));
1348 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1349 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1350 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1351 LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1352 LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1353}
1354
1355
1356/**
1357 * Reports MSR_IA32_PINBASED_CTLS to the log.
1358 *
1359 * @param pVmxMsr Pointer to the VMX MSR.
1360 */
1361static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1362{
1363 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1364 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1365 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1366 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1367 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1368 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1369 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1370 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1371}
1372
1373
1374/**
1375 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1376 *
1377 * @param pVmxMsr Pointer to the VMX MSR.
1378 */
1379static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1380{
1381 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1382 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1383 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1384 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1385 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1386 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1387 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1388 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1389 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1390 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1391 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1392 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1393 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1394 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1395 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1396 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1397 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1398 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1399 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1400 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1401 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1402 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1403 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1404 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1405 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1406}
1407
1408
1409/**
1410 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1411 *
1412 * @param pVmxMsr Pointer to the VMX MSR.
1413 */
1414static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1415{
1416 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1417 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1418 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1419 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1420 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1421 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1422 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1423 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1424 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1425 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1426 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1427 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1428 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1429 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1430 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1431 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1432 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1433 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1434 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1435 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1436 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1437 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1438 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1439 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1440 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PASID_TRANSLATE", VMX_PROC_CTLS2_PASID_TRANSLATE);
1441 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1442 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1443 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1444 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1445 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1446 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PCONFIG", VMX_PROC_CTLS2_PCONFIG);
1447 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1448 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "BUS_LOCK_DETECT", VMX_PROC_CTLS2_BUS_LOCK_DETECT);
1449 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INSTR_TIMEOUT", VMX_PROC_CTLS2_INSTR_TIMEOUT);
1450}
1451
1452
1453/**
1454 * Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1455 *
1456 * @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1457 */
1458static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1459{
1460 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1461 LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1462 LogRel(("HM: HLAT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_HLAT)));
1463 LogRel(("HM: EPT_PAGING_WRITE = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_EPT_PAGING_WRITE)));
1464 LogRel(("HM: GST_PAGING_VERIFY = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_GST_PAGING_VERIFY)));
1465 LogRel(("HM: IPI_VIRT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_IPI_VIRT)));
1466 LogRel(("HM: VIRT_SPEC_CTRL = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_VIRT_SPEC_CTRL)));
1467}
1468
1469
1470/**
1471 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1472 *
1473 * @param pVmxMsr Pointer to the VMX MSR.
1474 */
1475static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1476{
1477 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1478 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1479 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1480 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1481 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1482 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1483 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1484 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1485 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1486 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1487 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1488 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1489 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1490 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_UINV", VMX_ENTRY_CTLS_LOAD_UINV);
1491 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1492 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_LBR_CTL_MSR", VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR);
1493 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1494}
1495
1496
1497/**
1498 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1499 *
1500 * @param pVmxMsr Pointer to the VMX MSR.
1501 */
1502static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1503{
1504 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1505 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1506 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1507 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1508 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1509 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1510 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1511 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1512 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1513 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1514 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1515 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1516 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1517 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1518 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1519 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_LBR_CTL_MSR", VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR);
1520 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_UINV", VMX_EXIT_CTLS_CLEAR_UINV);
1521 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1522 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1523 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PERF_MSR", VMX_EXIT_CTLS_SAVE_PERF_MSR);
1524}
1525
1526
1527/**
1528 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1529 *
1530 * @param fCaps The VMX EPT/VPID capability MSR value.
1531 */
1532static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1533{
1534 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1535 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1536 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1537 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1538 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1539 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1540 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1541 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1542 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1543 HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1544 HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1545 HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1546 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1547 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1548 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1549 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1550 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1551 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1552 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1553}
1554
1555
1556/**
1557 * Reports MSR_IA32_VMX_MISC MSR to the log.
1558 *
1559 * @param pVM Pointer to the VM.
1560 * @param fMisc The VMX misc. MSR value.
1561 */
1562static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1563{
1564 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1565 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1566 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1567 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1568 else
1569 {
1570 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1571 pVM->hm.s.vmx.cPreemptTimerShift));
1572 }
1573 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1574 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1575 hmR3VmxGetActivityStateAllDesc(fMisc)));
1576 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1577 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1578 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1579 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1580 VMX_MISC_MAX_MSRS(fMisc)));
1581 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1582 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1583 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1584 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1585}
1586
1587
1588/**
1589 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1590 *
1591 * @param uVmcsEnum The VMX VMCS enum MSR value.
1592 */
1593static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1594{
1595 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1596 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1597}
1598
1599
1600/**
1601 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1602 *
1603 * @param uVmFunc The VMX VMFUNC MSR value.
1604 */
1605static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1606{
1607 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1608 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1609}
1610
1611
1612/**
1613 * Reports VMX CR0, CR4 fixed MSRs.
1614 *
1615 * @param pMsrs Pointer to the VMX MSRs.
1616 */
1617static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1618{
1619 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1620 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1621 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1622 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1623}
1624
1625
1626/**
1627 * Finish VT-x initialization (after ring-0 init).
1628 *
1629 * @returns VBox status code.
1630 * @param pVM The cross context VM structure.
1631 */
1632static int hmR3InitFinalizeR0Intel(PVM pVM)
1633{
1634 int rc;
1635
1636 LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1637 AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1638
1639 LogRel(("HM: Using VT-x implementation 3.0\n"));
1640 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1641 LogRel(("HM: Host CR0 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr0));
1642 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1643 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1644 LogRel(("HM: Host SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1645 LogRel(("HM: Host CORE_CAPABILITIES = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCoreCap));
1646 LogRel(("HM: Host MEMORY_CTRL = %#RX64%s\n", pVM->hm.s.ForR3.vmx.u64HostMemoryCtrl,
1647 pVM->hm.s.ForR3.vmx.u64HostMemoryCtrl & MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE ? " - split-lock disable!" : ""));
1648 LogRel(("HM: Host DR6 zero'ed = %#RX64%s\n", pVM->hm.s.ForR3.vmx.u64HostDr6Zeroed,
1649 pVM->hm.s.ForR3.vmx.fAlwaysInterceptMovDRx ? " - always intercept MOV DRx" : ""));
1650
1651 hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1652 hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1653
1654 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1655 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1656 if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1657 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1658 if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1659 hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1660
1661 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1662 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1663
1664 if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1665 {
1666 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1667 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1668 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1669 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1670 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1671 }
1672
1673 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1674 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1675 if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1676 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1677 if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1678 hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1679 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1680
1681#ifdef TODO_9217_VMCSINFO
1682 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1683 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1684 {
1685 PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1686 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1687 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1688 }
1689#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1690 if (pVM->cpum.ro.GuestFeatures.fVmx)
1691 {
1692 LogRel(("HM: Nested-guest:\n"));
1693 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1694 {
1695 PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1696 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1697 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1698 }
1699 }
1700#endif
1701#endif /* TODO_9217_VMCSINFO */
1702
1703 /*
1704 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1705 */
1706 AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1707 || (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1708 VERR_HM_IPE_1);
1709 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1710 || ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1711 && pVM->hm.s.fNestedPagingCfg),
1712 VERR_HM_IPE_1);
1713
1714 /*
1715 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1716 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1717 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1718 */
1719 if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1720 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1721 {
1722 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1723 LogRel(("HM: Disabled RDTSCP\n"));
1724 }
1725
1726 if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1727 {
1728 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1729 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1730 if (RT_SUCCESS(rc))
1731 {
1732 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1733 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1734 esp. Figure 20-5.*/
1735 RT_BZERO(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1736 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1737
1738 /* Bit set to 0 means software interrupts are redirected to the
1739 8086 program interrupt handler rather than switching to
1740 protected-mode handler. */
1741 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1742
1743 /* Allow all port IO, so that port IO instructions do not cause
1744 exceptions and would instead cause a VM-exit (based on VT-x's
1745 IO bitmap which we currently configure to always cause an exit). */
1746 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1747 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1748
1749 /*
1750 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1751 * page table used in real and protected mode without paging with EPT.
1752 */
1753 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE * 3);
1754 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1755 {
1756 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1757 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1758 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1759 | X86_PDE4M_G;
1760 }
1761
1762 /* We convert it here every time as PCI regions could be reconfigured. */
1763 if (PDMVmmDevHeapIsEnabled(pVM))
1764 {
1765 RTGCPHYS GCPhys;
1766 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1767 AssertRCReturn(rc, rc);
1768 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1769
1770 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1771 AssertRCReturn(rc, rc);
1772 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1773 }
1774 }
1775 else
1776 {
1777 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1778 pVM->hm.s.vmx.pRealModeTSS = NULL;
1779 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1780 return VMSetError(pVM, rc, RT_SRC_POS,
1781 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1782 }
1783 }
1784
1785 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1786 : "HM: Guest support: 32-bit only\n"));
1787
1788 /*
1789 * Call ring-0 to set up the VM.
1790 */
1791 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1792 if (rc != VINF_SUCCESS)
1793 {
1794 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1795 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1796 {
1797 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1798 LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1799 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1800 }
1801 HMR3CheckError(pVM, rc);
1802 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1803 }
1804
1805 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1806 LogRel(("HM: Enabled VMX\n"));
1807 pVM->hm.s.vmx.fEnabled = true;
1808
1809 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1810
1811 /*
1812 * Log configuration details.
1813 */
1814 if (pVM->hm.s.fNestedPagingCfg)
1815 {
1816 LogRel(("HM: Enabled nested paging\n"));
1817 if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1818 LogRel(("HM: EPT flush type = Single context\n"));
1819 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1820 LogRel(("HM: EPT flush type = All contexts\n"));
1821 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1822 LogRel(("HM: EPT flush type = Not supported\n"));
1823 else
1824 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1825
1826 if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1827 LogRel(("HM: Enabled unrestricted guest execution\n"));
1828
1829 if (pVM->hm.s.fLargePages)
1830 {
1831 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1832 PGMSetLargePageUsage(pVM, true);
1833 LogRel(("HM: Enabled large page support\n"));
1834 }
1835 }
1836 else
1837 Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1838
1839 if (pVM->hm.s.ForR3.vmx.fVpid)
1840 {
1841 LogRel(("HM: Enabled VPID\n"));
1842 if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1843 LogRel(("HM: VPID flush type = Individual addresses\n"));
1844 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1845 LogRel(("HM: VPID flush type = Single context\n"));
1846 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1847 LogRel(("HM: VPID flush type = All contexts\n"));
1848 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1849 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1850 else
1851 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1852 }
1853 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1854 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1855
1856 if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1857 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1858 else
1859 LogRel(("HM: Disabled VMX-preemption timer\n"));
1860
1861 if (pVM->hm.s.fVirtApicRegs)
1862 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1863
1864 if (pVM->hm.s.fPostedIntrs)
1865 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1866
1867 if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1868 {
1869 bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1870 LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1871 }
1872
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/**
1878 * Finish AMD-V initialization (after ring-0 init).
1879 *
1880 * @returns VBox status code.
1881 * @param pVM The cross context VM structure.
1882 */
1883static int hmR3InitFinalizeR0Amd(PVM pVM)
1884{
1885 LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1886
1887 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1888
1889#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1890 uint32_t u32Family;
1891 uint32_t u32Model;
1892 uint32_t u32Stepping;
1893 if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1894 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1895#endif
1896 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1897 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1898 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1899 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1900 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1901
1902 /*
1903 * Enumerate AMD-V features.
1904 */
1905 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1906 {
1907#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1908 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1909 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1910 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1911 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1912 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1913 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1914 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1915 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1916 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1917 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1918 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1919 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1920 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1921 HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1922 HMSVM_REPORT_FEATURE("X2AVIC", X86_CPUID_SVM_FEATURE_EDX_X2AVIC),
1923 HMSVM_REPORT_FEATURE("SSSCHECK", X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
1924 HMSVM_REPORT_FEATURE("SPEC_CTRL", X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
1925 HMSVM_REPORT_FEATURE("ROGPT", X86_CPUID_SVM_FEATURE_EDX_ROGPT),
1926 HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE", X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
1927 HMSVM_REPORT_FEATURE("TLBICTL", X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
1928 HMSVM_REPORT_FEATURE("VNMI", X86_CPUID_SVM_FEATURE_EDX_VNMI),
1929 HMSVM_REPORT_FEATURE("IBS_VIRT", X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT),
1930 HMSVM_REPORT_FEATURE("EXT_LVT_AVIC_ACCESS_CHG", X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG),
1931 HMSVM_REPORT_FEATURE("NST_VIRT_VMCB_ADDR_CHK", X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK),
1932 HMSVM_REPORT_FEATURE("BUS_LOCK_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD),
1933#undef HMSVM_REPORT_FEATURE
1934 };
1935
1936 uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1937 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1938 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1939 {
1940 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1941 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1942 }
1943 if (fSvmFeatures)
1944 for (unsigned iBit = 0; iBit < 32; iBit++)
1945 if (RT_BIT_32(iBit) & fSvmFeatures)
1946 LogRel(("HM: Reserved bit %u\n", iBit));
1947
1948 /*
1949 * Nested paging is determined in HMR3Init, verify the sanity of that.
1950 */
1951 AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1952 || (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1953 VERR_HM_IPE_1);
1954
1955#if 0
1956 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1957 * here. */
1958 if (RTR0IsPostIpiSupport())
1959 pVM->hm.s.fPostedIntrs = true;
1960#endif
1961
1962 /*
1963 * Determine whether we need to intercept #UD in SVM mode for emulating
1964 * intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1965 * when executed in long-mode. This is only really applicable when
1966 * non-default CPU profiles are in effect, i.e. guest vendor differs
1967 * from the host one.
1968 */
1969 if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1970 switch (CPUMGetGuestCpuVendor(pVM))
1971 {
1972 case CPUMCPUVENDOR_INTEL:
1973 case CPUMCPUVENDOR_VIA: /*?*/
1974 case CPUMCPUVENDOR_SHANGHAI: /*?*/
1975 {
1976 switch (CPUMGetHostCpuVendor(pVM))
1977 {
1978 case CPUMCPUVENDOR_AMD:
1979 case CPUMCPUVENDOR_HYGON:
1980 {
1981 if (pVM->hm.s.fAllow64BitGuestsCfg)
1982 {
1983 LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1984 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1985 pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1986 }
1987 break;
1988 }
1989 default:
1990 break;
1991 }
1992 break;
1993 }
1994 default:
1995 break;
1996 }
1997
1998 /*
1999 * Call ring-0 to set up the VM.
2000 */
2001 int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
2002 if (rc != VINF_SUCCESS)
2003 {
2004 AssertMsgFailed(("%Rrc\n", rc));
2005 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
2006 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
2007 }
2008
2009 LogRel(("HM: Enabled SVM\n"));
2010 pVM->hm.s.svm.fEnabled = true;
2011
2012 if (pVM->hm.s.fNestedPagingCfg)
2013 {
2014 LogRel(("HM: Enabled nested paging\n"));
2015
2016 /*
2017 * Enable large pages (2 MB) if applicable.
2018 */
2019 if (pVM->hm.s.fLargePages)
2020 {
2021 PGMSetLargePageUsage(pVM, true);
2022 LogRel(("HM: Enabled large page support\n"));
2023 }
2024 }
2025
2026 if (pVM->hm.s.fVirtApicRegs)
2027 LogRel(("HM: Enabled APIC-register virtualization support\n"));
2028
2029 if (pVM->hm.s.fPostedIntrs)
2030 LogRel(("HM: Enabled posted-interrupt processing support\n"));
2031
2032 hmR3DisableRawMode(pVM);
2033
2034 LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
2035 : "HM: Disabled TPR patching\n"));
2036
2037 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
2038 : "HM: Guest support: 32-bit only\n"));
2039 return VINF_SUCCESS;
2040}
2041
2042
2043/**
2044 * Applies relocations to data and code managed by this
2045 * component. This function will be called at init and
2046 * whenever the VMM need to relocate it self inside the GC.
2047 *
2048 * @param pVM The cross context VM structure.
2049 */
2050VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2051{
2052 /* Fetch the current paging mode during the relocate callback during state loading. */
2053 if (VMR3GetState(pVM) == VMSTATE_LOADING)
2054 {
2055 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2056 {
2057 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2058 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2059 }
2060 }
2061}
2062
2063
2064/**
2065 * Terminates the HM.
2066 *
2067 * Termination means cleaning up and freeing all resources,
2068 * the VM itself is, at this point, powered off or suspended.
2069 *
2070 * @returns VBox status code.
2071 * @param pVM The cross context VM structure.
2072 */
2073VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2074{
2075 if (pVM->hm.s.vmx.pRealModeTSS)
2076 {
2077 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2078 pVM->hm.s.vmx.pRealModeTSS = 0;
2079 }
2080 hmR3TermCPU(pVM);
2081 return 0;
2082}
2083
2084
2085/**
2086 * Terminates the per-VCPU HM.
2087 *
2088 * @returns VBox status code.
2089 * @param pVM The cross context VM structure.
2090 */
2091static int hmR3TermCPU(PVM pVM)
2092{
2093 RT_NOREF(pVM);
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * Resets a virtual CPU.
2100 *
2101 * Used by HMR3Reset and CPU hot plugging.
2102 *
2103 * @param pVCpu The cross context virtual CPU structure to reset.
2104 */
2105VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2106{
2107 /* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2108 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2109 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2110
2111 pVCpu->hm.s.fActive = false;
2112 pVCpu->hm.s.Event.fPending = false;
2113 pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2114 pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2115#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2116 if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2117 pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2118#endif
2119}
2120
2121
2122/**
2123 * The VM is being reset.
2124 *
2125 * For the HM component this means that any GDT/LDT/TSS monitors
2126 * needs to be removed.
2127 *
2128 * @param pVM The cross context VM structure.
2129 */
2130VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2131{
2132 LogFlow(("HMR3Reset:\n"));
2133
2134 if (HMIsEnabled(pVM))
2135 hmR3DisableRawMode(pVM);
2136
2137 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2138 HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2139
2140 /* Clear all patch information. */
2141 pVM->hm.s.pGuestPatchMem = 0;
2142 pVM->hm.s.pFreeGuestPatchMem = 0;
2143 pVM->hm.s.cbGuestPatchMem = 0;
2144 pVM->hm.s.cPatches = 0;
2145 pVM->hm.s.PatchTree = 0;
2146 pVM->hm.s.fTprPatchingActive = false;
2147 RT_BZERO(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2148}
2149
2150
2151/**
2152 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2153 *
2154 * @returns VBox strict status code.
2155 * @param pVM The cross context VM structure.
2156 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2157 * @param pvUser Unused.
2158 */
2159static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2160{
2161 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2162
2163 /* Only execute the handler on the VCPU the original patch request was issued. */
2164 if (pVCpu->idCpu != idCpu)
2165 return VINF_SUCCESS;
2166
2167 Log(("hmR3RemovePatches\n"));
2168 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2169 {
2170 uint8_t abInstr[15];
2171 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2172 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2173 int rc;
2174
2175#ifdef LOG_ENABLED
2176 char szOutput[256];
2177 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2178 szOutput, sizeof(szOutput), NULL);
2179 if (RT_SUCCESS(rc))
2180 Log(("Patched instr: %s\n", szOutput));
2181#endif
2182
2183 /* Check if the instruction is still the same. */
2184 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2185 if (rc != VINF_SUCCESS)
2186 {
2187 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2188 continue; /* swapped out or otherwise removed; skip it. */
2189 }
2190
2191 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2192 {
2193 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2194 continue; /* skip it. */
2195 }
2196
2197 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2198 AssertRC(rc);
2199
2200#ifdef LOG_ENABLED
2201 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2202 szOutput, sizeof(szOutput), NULL);
2203 if (RT_SUCCESS(rc))
2204 Log(("Original instr: %s\n", szOutput));
2205#endif
2206 }
2207 pVM->hm.s.cPatches = 0;
2208 pVM->hm.s.PatchTree = 0;
2209 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2210 pVM->hm.s.fTprPatchingActive = false;
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/**
2216 * Worker for enabling patching in a VT-x/AMD-V guest.
2217 *
2218 * @returns VBox status code.
2219 * @param pVM The cross context VM structure.
2220 * @param idCpu VCPU to execute hmR3RemovePatches on.
2221 * @param pPatchMem Patch memory range.
2222 * @param cbPatchMem Size of the memory range.
2223 */
2224static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2225{
2226 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2227 AssertRC(rc);
2228
2229 pVM->hm.s.pGuestPatchMem = pPatchMem;
2230 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2231 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/**
2237 * Enable patching in a VT-x/AMD-V guest
2238 *
2239 * @returns VBox status code.
2240 * @param pVM The cross context VM structure.
2241 * @param pPatchMem Patch memory range.
2242 * @param cbPatchMem Size of the memory range.
2243 */
2244VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2245{
2246 VM_ASSERT_EMT(pVM);
2247 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2248 if (pVM->cCpus > 1)
2249 {
2250 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2251 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2252 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2253 AssertRC(rc);
2254 return rc;
2255 }
2256 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2257}
2258
2259
2260/**
2261 * Disable patching in a VT-x/AMD-V guest.
2262 *
2263 * @returns VBox status code.
2264 * @param pVM The cross context VM structure.
2265 * @param pPatchMem Patch memory range.
2266 * @param cbPatchMem Size of the memory range.
2267 */
2268VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2269{
2270 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2271 RT_NOREF2(pPatchMem, cbPatchMem);
2272
2273 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2274 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2275
2276 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2277 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2278 (void *)(uintptr_t)VMMGetCpuId(pVM));
2279 AssertRC(rc);
2280
2281 pVM->hm.s.pGuestPatchMem = 0;
2282 pVM->hm.s.pFreeGuestPatchMem = 0;
2283 pVM->hm.s.cbGuestPatchMem = 0;
2284 pVM->hm.s.fTprPatchingActive = false;
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/**
2290 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2291 *
2292 * @returns VBox strict status code.
2293 * @param pVM The cross context VM structure.
2294 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2295 * @param pvUser User specified CPU context.
2296 *
2297 */
2298static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2299{
2300 /*
2301 * Only execute the handler on the VCPU the original patch request was
2302 * issued. (The other CPU(s) might not yet have switched to protected
2303 * mode, nor have the correct memory context.)
2304 */
2305 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2306 if (pVCpu->idCpu != idCpu)
2307 return VINF_SUCCESS;
2308
2309 /*
2310 * We're racing other VCPUs here, so don't try patch the instruction twice
2311 * and make sure there is still room for our patch record.
2312 */
2313 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2314 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2315 if (pPatch)
2316 {
2317 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2318 return VINF_SUCCESS;
2319 }
2320 uint32_t const idx = pVM->hm.s.cPatches;
2321 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2322 {
2323 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2324 return VINF_SUCCESS;
2325 }
2326 pPatch = &pVM->hm.s.aPatches[idx];
2327
2328 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2329
2330 /*
2331 * Disassembler the instruction and get cracking.
2332 */
2333 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2334 DISSTATE Dis;
2335 uint32_t cbOp;
2336 int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2337 AssertRC(rc);
2338 if ( rc == VINF_SUCCESS
2339 && Dis.pCurInstr->uOpcode == OP_MOV
2340 && cbOp >= 3)
2341 {
2342 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2343
2344 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2345 AssertRC(rc);
2346
2347 pPatch->cbOp = cbOp;
2348
2349 if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2350 {
2351 /* write. */
2352 if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2353 {
2354 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2355 pPatch->uSrcOperand = Dis.Param2.x86.Base.idxGenReg;
2356 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.x86.Base.idxGenReg));
2357 }
2358 else
2359 {
2360 Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2361 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2362 pPatch->uSrcOperand = Dis.Param2.uValue;
2363 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2364 }
2365 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2366 AssertRC(rc);
2367
2368 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2369 pPatch->cbNewOp = sizeof(s_abVMMCall);
2370 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2371 }
2372 else
2373 {
2374 /*
2375 * TPR Read.
2376 *
2377 * Found:
2378 * mov eax, dword [fffe0080] (5 bytes)
2379 * Check if next instruction is:
2380 * shr eax, 4
2381 */
2382 Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2383
2384 uint8_t const idxMmioReg = Dis.Param1.x86.Base.idxGenReg;
2385 uint8_t const cbOpMmio = cbOp;
2386 uint64_t const uSavedRip = pCtx->rip;
2387
2388 pCtx->rip += cbOp;
2389 rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2390 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2391 pCtx->rip = uSavedRip;
2392
2393 if ( rc == VINF_SUCCESS
2394 && Dis.pCurInstr->uOpcode == OP_SHR
2395 && Dis.Param1.fUse == DISUSE_REG_GEN32
2396 && Dis.Param1.x86.Base.idxGenReg == idxMmioReg
2397 && Dis.Param2.fUse == DISUSE_IMMEDIATE8
2398 && Dis.Param2.uValue == 4
2399 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2400 {
2401 uint8_t abInstr[15];
2402
2403 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2404 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2405 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2406 AssertRC(rc);
2407
2408 pPatch->cbOp = cbOpMmio + cbOp;
2409
2410 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2411 abInstr[0] = 0xf0;
2412 abInstr[1] = 0x0f;
2413 abInstr[2] = 0x20;
2414 abInstr[3] = 0xc0 | Dis.Param1.x86.Base.idxGenReg;
2415 for (unsigned i = 4; i < pPatch->cbOp; i++)
2416 abInstr[i] = 0x90; /* nop */
2417
2418 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2419 AssertRC(rc);
2420
2421 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2422 pPatch->cbNewOp = pPatch->cbOp;
2423 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2424
2425 Log(("Acceptable read/shr candidate!\n"));
2426 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2427 }
2428 else
2429 {
2430 pPatch->enmType = HMTPRINSTR_READ;
2431 pPatch->uDstOperand = idxMmioReg;
2432
2433 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2434 AssertRC(rc);
2435
2436 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2437 pPatch->cbNewOp = sizeof(s_abVMMCall);
2438 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2439 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2440 }
2441 }
2442
2443 pPatch->Core.Key = pCtx->eip;
2444 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2445 AssertRC(rc);
2446
2447 pVM->hm.s.cPatches++;
2448 return VINF_SUCCESS;
2449 }
2450
2451 /*
2452 * Save invalid patch, so we will not try again.
2453 */
2454 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2455 pPatch->Core.Key = pCtx->eip;
2456 pPatch->enmType = HMTPRINSTR_INVALID;
2457 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2458 AssertRC(rc);
2459 pVM->hm.s.cPatches++;
2460 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2461 return VINF_SUCCESS;
2462}
2463
2464
2465/**
2466 * Callback to patch a TPR instruction (jump to generated code).
2467 *
2468 * @returns VBox strict status code.
2469 * @param pVM The cross context VM structure.
2470 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2471 * @param pvUser User specified CPU context.
2472 *
2473 */
2474static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2475{
2476 /*
2477 * Only execute the handler on the VCPU the original patch request was
2478 * issued. (The other CPU(s) might not yet have switched to protected
2479 * mode, nor have the correct memory context.)
2480 */
2481 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2482 if (pVCpu->idCpu != idCpu)
2483 return VINF_SUCCESS;
2484
2485 /*
2486 * We're racing other VCPUs here, so don't try patch the instruction twice
2487 * and make sure there is still room for our patch record.
2488 */
2489 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2490 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2491 if (pPatch)
2492 {
2493 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2494 return VINF_SUCCESS;
2495 }
2496 uint32_t const idx = pVM->hm.s.cPatches;
2497 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2498 {
2499 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2500 return VINF_SUCCESS;
2501 }
2502 pPatch = &pVM->hm.s.aPatches[idx];
2503
2504 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2505 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2506
2507 /*
2508 * Disassemble the instruction and get cracking.
2509 */
2510 DISSTATE Dis;
2511 uint32_t cbOp;
2512 int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2513 AssertRC(rc);
2514 if ( rc == VINF_SUCCESS
2515 && Dis.pCurInstr->uOpcode == OP_MOV
2516 && cbOp >= 5)
2517 {
2518 uint8_t aPatch[64];
2519 uint32_t off = 0;
2520
2521 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2522 AssertRC(rc);
2523
2524 pPatch->cbOp = cbOp;
2525 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2526
2527 if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2528 {
2529 /*
2530 * TPR write:
2531 *
2532 * push ECX [51]
2533 * push EDX [52]
2534 * push EAX [50]
2535 * xor EDX,EDX [31 D2]
2536 * mov EAX,EAX [89 C0]
2537 * or
2538 * mov EAX,0000000CCh [B8 CC 00 00 00]
2539 * mov ECX,0C0000082h [B9 82 00 00 C0]
2540 * wrmsr [0F 30]
2541 * pop EAX [58]
2542 * pop EDX [5A]
2543 * pop ECX [59]
2544 * jmp return_address [E9 return_address]
2545 */
2546 bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.x86.Base.idxGenReg == DISGREG_EAX);
2547
2548 aPatch[off++] = 0x51; /* push ecx */
2549 aPatch[off++] = 0x52; /* push edx */
2550 if (!fUsesEax)
2551 aPatch[off++] = 0x50; /* push eax */
2552 aPatch[off++] = 0x31; /* xor edx, edx */
2553 aPatch[off++] = 0xd2;
2554 if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2555 {
2556 if (!fUsesEax)
2557 {
2558 aPatch[off++] = 0x89; /* mov eax, src_reg */
2559 aPatch[off++] = MAKE_MODRM(3, Dis.Param2.x86.Base.idxGenReg, DISGREG_EAX);
2560 }
2561 }
2562 else
2563 {
2564 Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2565 aPatch[off++] = 0xb8; /* mov eax, immediate */
2566 *(uint32_t *)&aPatch[off] = Dis.Param2.uValue;
2567 off += sizeof(uint32_t);
2568 }
2569 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2570 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2571 off += sizeof(uint32_t);
2572
2573 aPatch[off++] = 0x0f; /* wrmsr */
2574 aPatch[off++] = 0x30;
2575 if (!fUsesEax)
2576 aPatch[off++] = 0x58; /* pop eax */
2577 aPatch[off++] = 0x5a; /* pop edx */
2578 aPatch[off++] = 0x59; /* pop ecx */
2579 }
2580 else
2581 {
2582 /*
2583 * TPR read:
2584 *
2585 * push ECX [51]
2586 * push EDX [52]
2587 * push EAX [50]
2588 * mov ECX,0C0000082h [B9 82 00 00 C0]
2589 * rdmsr [0F 32]
2590 * mov EAX,EAX [89 C0]
2591 * pop EAX [58]
2592 * pop EDX [5A]
2593 * pop ECX [59]
2594 * jmp return_address [E9 return_address]
2595 */
2596 Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2597
2598 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_ECX)
2599 aPatch[off++] = 0x51; /* push ecx */
2600 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_EDX )
2601 aPatch[off++] = 0x52; /* push edx */
2602 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_EAX)
2603 aPatch[off++] = 0x50; /* push eax */
2604
2605 aPatch[off++] = 0x31; /* xor edx, edx */
2606 aPatch[off++] = 0xd2;
2607
2608 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2609 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2610 off += sizeof(uint32_t);
2611
2612 aPatch[off++] = 0x0f; /* rdmsr */
2613 aPatch[off++] = 0x32;
2614
2615 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_EAX)
2616 {
2617 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2618 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.x86.Base.idxGenReg);
2619 }
2620
2621 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_EAX)
2622 aPatch[off++] = 0x58; /* pop eax */
2623 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_EDX )
2624 aPatch[off++] = 0x5a; /* pop edx */
2625 if (Dis.Param1.x86.Base.idxGenReg != DISGREG_ECX)
2626 aPatch[off++] = 0x59; /* pop ecx */
2627 }
2628 aPatch[off++] = 0xe9; /* jmp return_address */
2629 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2630 off += sizeof(RTRCUINTPTR);
2631
2632 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2633 {
2634 /* Write new code to the patch buffer. */
2635 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2636 AssertRC(rc);
2637
2638#ifdef LOG_ENABLED
2639 uint32_t cbCurInstr;
2640 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2641 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2642 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2643 {
2644 char szOutput[256];
2645 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2646 szOutput, sizeof(szOutput), &cbCurInstr);
2647 if (RT_SUCCESS(rc))
2648 Log(("Patch instr %s\n", szOutput));
2649 else
2650 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2651 }
2652#endif
2653
2654 pPatch->aNewOpcode[0] = 0xE9;
2655 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2656
2657 /* Overwrite the TPR instruction with a jump. */
2658 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2659 AssertRC(rc);
2660
2661 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2662
2663 pVM->hm.s.pFreeGuestPatchMem += off;
2664 pPatch->cbNewOp = 5;
2665
2666 pPatch->Core.Key = pCtx->eip;
2667 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2668 AssertRC(rc);
2669
2670 pVM->hm.s.cPatches++;
2671 pVM->hm.s.fTprPatchingActive = true;
2672 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2673 return VINF_SUCCESS;
2674 }
2675
2676 Log(("Ran out of space in our patch buffer!\n"));
2677 }
2678 else
2679 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2680
2681
2682 /*
2683 * Save invalid patch, so we will not try again.
2684 */
2685 pPatch = &pVM->hm.s.aPatches[idx];
2686 pPatch->Core.Key = pCtx->eip;
2687 pPatch->enmType = HMTPRINSTR_INVALID;
2688 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2689 AssertRC(rc);
2690 pVM->hm.s.cPatches++;
2691 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2692 return VINF_SUCCESS;
2693}
2694
2695
2696/**
2697 * Attempt to patch TPR mmio instructions.
2698 *
2699 * @returns VBox status code.
2700 * @param pVM The cross context VM structure.
2701 * @param pVCpu The cross context virtual CPU structure.
2702 */
2703VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2704{
2705 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2706 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2707 (void *)(uintptr_t)pVCpu->idCpu);
2708 AssertRC(rc);
2709 return rc;
2710}
2711
2712
2713/**
2714 * Checks if we need to reschedule due to VMM device heap changes.
2715 *
2716 * @returns true if a reschedule is required, otherwise false.
2717 * @param pVM The cross context VM structure.
2718 * @param pCtx VM execution context.
2719 */
2720VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2721{
2722 /*
2723 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2724 * when the unrestricted guest execution feature is missing (VT-x only).
2725 */
2726 if ( pVM->hm.s.vmx.fEnabled
2727 && !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2728 && CPUMIsGuestInRealModeEx(pCtx)
2729 && !PDMVmmDevHeapIsEnabled(pVM))
2730 return true;
2731
2732 return false;
2733}
2734
2735
2736/**
2737 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2738 * event settings changes.
2739 *
2740 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2741 * function is just updating the VM globals.
2742 *
2743 * @param pVM The VM cross context VM structure.
2744 * @thread EMT(0)
2745 */
2746VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2747{
2748 /* Interrupts. */
2749 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2750 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2751
2752 /* CPU Exceptions. */
2753 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2754 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2755 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2756 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2757
2758 /* Common VM exits. */
2759 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2760 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2761 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2762 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2763
2764 /* Vendor specific VM exits. */
2765 if (HMR3IsVmxEnabled(pVM->pUVM))
2766 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2767 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2768 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2769 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2770 else
2771 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2772 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2773 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2774 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2775
2776 /* Done. */
2777 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2778}
2779
2780
2781/**
2782 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2783 *
2784 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2785 * per CPU settings.
2786 *
2787 * @param pVM The VM cross context VM structure.
2788 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2789 */
2790VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2791{
2792 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2793}
2794
2795
2796#if 0 /* evil */
2797/**
2798 * Checks if we are currently using hardware acceleration.
2799 *
2800 * @returns true if hardware acceleration is being used, otherwise false.
2801 * @param pVCpu The cross context virtual CPU structure.
2802 */
2803VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2804{
2805 return pVCpu->hm.s.fActive;
2806}
2807#endif
2808
2809
2810/**
2811 * External interface for querying whether hardware acceleration is enabled.
2812 *
2813 * @returns true if VT-x or AMD-V is being used, otherwise false.
2814 * @param pUVM The user mode VM handle.
2815 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2816 */
2817VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2818{
2819 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2820 PVM pVM = pUVM->pVM;
2821 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2822 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2823}
2824
2825
2826/**
2827 * External interface for querying whether VT-x is being used.
2828 *
2829 * @returns true if VT-x is being used, otherwise false.
2830 * @param pUVM The user mode VM handle.
2831 * @sa HMR3IsSvmEnabled, HMIsEnabled
2832 */
2833VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2834{
2835 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2836 PVM pVM = pUVM->pVM;
2837 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2838 return pVM->hm.s.vmx.fEnabled
2839 && pVM->hm.s.vmx.fSupported
2840 && pVM->fHMEnabled;
2841}
2842
2843
2844/**
2845 * External interface for querying whether AMD-V is being used.
2846 *
2847 * @returns true if VT-x is being used, otherwise false.
2848 * @param pUVM The user mode VM handle.
2849 * @sa HMR3IsVmxEnabled, HMIsEnabled
2850 */
2851VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2852{
2853 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2854 PVM pVM = pUVM->pVM;
2855 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2856 return pVM->hm.s.svm.fEnabled
2857 && pVM->hm.s.svm.fSupported
2858 && pVM->fHMEnabled;
2859}
2860
2861
2862/**
2863 * Checks if we are currently using nested paging.
2864 *
2865 * @returns true if nested paging is being used, otherwise false.
2866 * @param pUVM The user mode VM handle.
2867 */
2868VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2869{
2870 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2871 PVM pVM = pUVM->pVM;
2872 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2873 return pVM->hm.s.fNestedPagingCfg;
2874}
2875
2876
2877/**
2878 * Checks if virtualized APIC registers are enabled.
2879 *
2880 * When enabled this feature allows the hardware to access most of the
2881 * APIC registers in the virtual-APIC page without causing VM-exits. See
2882 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2883 *
2884 * @returns true if virtualized APIC registers is enabled, otherwise
2885 * false.
2886 * @param pUVM The user mode VM handle.
2887 */
2888VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2889{
2890 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2891 PVM pVM = pUVM->pVM;
2892 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2893 return pVM->hm.s.fVirtApicRegs;
2894}
2895
2896
2897/**
2898 * Checks if APIC posted-interrupt processing is enabled.
2899 *
2900 * This returns whether we can deliver interrupts to the guest without
2901 * leaving guest-context by updating APIC state from host-context.
2902 *
2903 * @returns true if APIC posted-interrupt processing is enabled,
2904 * otherwise false.
2905 * @param pUVM The user mode VM handle.
2906 */
2907VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2908{
2909 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2910 PVM pVM = pUVM->pVM;
2911 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2912 return pVM->hm.s.fPostedIntrs;
2913}
2914
2915
2916/**
2917 * Checks if we are currently using VPID in VT-x mode.
2918 *
2919 * @returns true if VPID is being used, otherwise false.
2920 * @param pUVM The user mode VM handle.
2921 */
2922VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2923{
2924 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2925 PVM pVM = pUVM->pVM;
2926 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2927 return pVM->hm.s.ForR3.vmx.fVpid;
2928}
2929
2930
2931/**
2932 * Checks if we are currently using VT-x unrestricted execution,
2933 * aka UX.
2934 *
2935 * @returns true if UX is being used, otherwise false.
2936 * @param pUVM The user mode VM handle.
2937 */
2938VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2939{
2940 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2941 PVM pVM = pUVM->pVM;
2942 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2943 return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2944 || pVM->hm.s.svm.fSupported;
2945}
2946
2947
2948/**
2949 * Checks if the VMX-preemption timer is being used.
2950 *
2951 * @returns true if the VMX-preemption timer is being used, otherwise false.
2952 * @param pVM The cross context VM structure.
2953 */
2954VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2955{
2956 return HMIsEnabled(pVM)
2957 && pVM->hm.s.vmx.fEnabled
2958 && pVM->hm.s.vmx.fUsePreemptTimerCfg;
2959}
2960
2961
2962#ifdef TODO_9217_VMCSINFO
2963/**
2964 * Helper for HMR3CheckError to log VMCS controls to the release log.
2965 *
2966 * @param idCpu The Virtual CPU ID.
2967 * @param pVmcsInfo The VMCS info. object.
2968 */
2969static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2970{
2971 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2972 {
2973 uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2974 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2975 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2976 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2977 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2978 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2979 }
2980 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2981 {
2982 uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2983 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2984 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2985 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2986 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2987 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2988 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2989 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2990 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2991 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2992 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2993 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2994 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2995 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2996 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2997 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2998 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2999 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
3000 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
3001 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
3002 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
3003 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
3004 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
3005 }
3006 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
3007 {
3008 uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
3009 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
3010 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
3011 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
3012 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
3013 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
3014 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
3015 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
3016 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
3017 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
3018 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
3019 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
3020 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
3021 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
3022 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
3023 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
3024 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
3025 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
3026 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
3027 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
3028 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
3029 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
3030 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PASID_TRANSLATE );
3031 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
3032 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
3033 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
3034 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
3035 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
3036 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PCONFIG );
3037 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
3038 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_BUS_LOCK_DETECT );
3039 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INSTR_TIMEOUT );
3040 }
3041 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
3042 {
3043 uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
3044 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3045 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3046 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3047 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3048 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3049 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3050 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3051 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3052 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3053 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3054 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_UINV );
3055 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
3056 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR );
3057 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
3058 }
3059 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3060 {
3061 uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3062 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3063 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3064 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3065 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3066 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3067 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3068 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3069 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3070 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3071 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3072 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3073 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3074 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR );
3075 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_UINV );
3076 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
3077 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
3078 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PERF_MSR );
3079 }
3080}
3081#endif
3082
3083
3084/**
3085 * Check fatal VT-x/AMD-V error and produce some meaningful
3086 * log release message.
3087 *
3088 * @param pVM The cross context VM structure.
3089 * @param iStatusCode VBox status code.
3090 */
3091VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3092{
3093 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3094 {
3095 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3096 * might be getting inaccurate values for non-guru'ing EMTs. */
3097 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3098#ifdef TODO_9217_VMCSINFO
3099 PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3100#endif
3101 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3102 switch (iStatusCode)
3103 {
3104 case VERR_VMX_INVALID_VMCS_PTR:
3105 {
3106 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3107 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3108#ifdef TODO_9217_VMCSINFO
3109 LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3110 pVmcsInfo->HCPhysVmcs));
3111#endif
3112 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3113 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3114 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3115 break;
3116 }
3117
3118 case VERR_VMX_UNABLE_TO_START_VM:
3119 {
3120 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3121 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3122 LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3123 LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3124
3125 if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3126 || pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3127 {
3128 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3129 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3130 }
3131 else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3132 {
3133#ifdef TODO_9217_VMCSINFO
3134 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3135 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3136 LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3137 LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3138 LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3139 LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3140 LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3141 LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3142#endif
3143 }
3144 /** @todo Log VM-entry event injection control fields
3145 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3146 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3147 break;
3148 }
3149
3150 case VERR_VMX_INVALID_GUEST_STATE:
3151 {
3152 LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3153 LogRel(("HM: CPU[%u] HM error = %#RX32 (%RU32)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
3154 LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3155#ifdef TODO_9217_VMCSINFO
3156 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3157#endif
3158 break;
3159 }
3160
3161 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3162 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3163 case VERR_VMX_INVALID_VMXON_PTR:
3164 case VERR_VMX_UNEXPECTED_EXIT:
3165 case VERR_VMX_INVALID_VMCS_FIELD:
3166 case VERR_SVM_UNKNOWN_EXIT:
3167 case VERR_SVM_UNEXPECTED_EXIT:
3168 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3169 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3170 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3171 break;
3172 }
3173 }
3174
3175 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3176 {
3177 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3178 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3179 }
3180 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3181 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3182}
3183
3184
3185/**
3186 * Execute state save operation.
3187 *
3188 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3189 * is because we always save the VM state from ring-3 and thus most HM state
3190 * will be re-synced dynamically at runtime and don't need to be part of the VM
3191 * saved state.
3192 *
3193 * @returns VBox status code.
3194 * @param pVM The cross context VM structure.
3195 * @param pSSM SSM operation handle.
3196 */
3197static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3198{
3199 Log(("hmR3Save:\n"));
3200
3201 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3202 {
3203 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3204 Assert(!pVCpu->hm.s.Event.fPending);
3205 if (pVM->cpum.ro.GuestFeatures.fSvm)
3206 {
3207 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3208 SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3209 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3210 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3211 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3212 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3213 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3214 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3215 SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3216 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3217 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3218 SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3219 SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3220 SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3221 }
3222 }
3223
3224 /* Save the guest patch data. */
3225 SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3226 SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3227 SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3228
3229 /* Store all the guest patch records too. */
3230 int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3231 if (RT_FAILURE(rc))
3232 return rc;
3233
3234 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3235 {
3236 AssertCompileSize(HMTPRINSTR, 4);
3237 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3238 SSMR3PutU32(pSSM, pPatch->Core.Key);
3239 SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3240 SSMR3PutU32(pSSM, pPatch->cbOp);
3241 SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3242 SSMR3PutU32(pSSM, pPatch->cbNewOp);
3243 SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3244 SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3245 SSMR3PutU32(pSSM, pPatch->uDstOperand);
3246 SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3247 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3248 if (RT_FAILURE(rc))
3249 return rc;
3250 }
3251
3252 return VINF_SUCCESS;
3253}
3254
3255
3256/**
3257 * Execute state load operation.
3258 *
3259 * @returns VBox status code.
3260 * @param pVM The cross context VM structure.
3261 * @param pSSM SSM operation handle.
3262 * @param uVersion Data layout version.
3263 * @param uPass The data pass.
3264 */
3265static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3266{
3267 int rc;
3268
3269 LogFlowFunc(("uVersion=%u\n", uVersion));
3270 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3271
3272 /*
3273 * Validate version.
3274 */
3275 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3276 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3277 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3278 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3279 {
3280 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3281 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3282 }
3283
3284 /*
3285 * Load per-VCPU state.
3286 */
3287 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3288 {
3289 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3290 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3291 {
3292 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3293 if (pVM->cpum.ro.GuestFeatures.fSvm)
3294 {
3295 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3296 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3297 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3298 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3299 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3300 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3301 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3302 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3303 SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3304 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3305 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3306 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3307 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3308 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3309 AssertRCReturn(rc, rc);
3310 }
3311 }
3312 else
3313 {
3314 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3315 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3316 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3317 SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3318
3319 /* VMX fWasInRealMode related data. */
3320 uint32_t uDummy;
3321 SSMR3GetU32(pSSM, &uDummy);
3322 SSMR3GetU32(pSSM, &uDummy);
3323 rc = SSMR3GetU32(pSSM, &uDummy);
3324 AssertRCReturn(rc, rc);
3325 }
3326 }
3327
3328 /*
3329 * Load TPR patching data.
3330 */
3331 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3332 {
3333 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3334 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3335 SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3336
3337 /* Fetch all TPR patch records. */
3338 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3339 AssertRCReturn(rc, rc);
3340 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3341 {
3342 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3343 SSMR3GetU32(pSSM, &pPatch->Core.Key);
3344 SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3345 SSMR3GetU32(pSSM, &pPatch->cbOp);
3346 SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3347 SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3348 SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3349
3350 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3351 pVM->hm.s.fTprPatchingActive = true;
3352 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTprPatchingActive == false);
3353
3354 SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3355 SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3356 SSMR3GetU32(pSSM, &pPatch->cFaults);
3357 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3358 AssertRCReturn(rc, rc);
3359
3360 LogFlow(("hmR3Load: patch %d\n", i));
3361 LogFlow(("Key = %x\n", pPatch->Core.Key));
3362 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3363 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3364 LogFlow(("type = %d\n", pPatch->enmType));
3365 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3366 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3367 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3368 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3369
3370 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3371 AssertRCReturn(rc, rc);
3372 }
3373 }
3374
3375 return VINF_SUCCESS;
3376}
3377
3378
3379/**
3380 * Displays HM info.
3381 *
3382 * @param pVM The cross context VM structure.
3383 * @param pHlp The info helper functions.
3384 * @param pszArgs Arguments, ignored.
3385 */
3386static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3387{
3388 NOREF(pszArgs);
3389 PVMCPU pVCpu = VMMGetCpu(pVM);
3390 if (!pVCpu)
3391 pVCpu = pVM->apCpusR3[0];
3392
3393 if (HMIsEnabled(pVM))
3394 {
3395 if (pVM->hm.s.vmx.fSupported)
3396 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3397 else
3398 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3399 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3400 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3401 if (pVM->hm.s.vmx.fSupported)
3402 {
3403 PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3404 bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3405 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3406
3407 pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3408 pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3409 if (fRealOnV86Active)
3410 {
3411 pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3412 pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3413 pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3414 pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3415 pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3416 pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3417 pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3418 }
3419 }
3420 }
3421 else
3422 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3423}
3424
3425
3426/**
3427 * Displays the HM Last-Branch-Record info. for the guest.
3428 *
3429 * @param pVM The cross context VM structure.
3430 * @param pHlp The info helper functions.
3431 * @param pszArgs Arguments, ignored.
3432 */
3433static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3434{
3435 NOREF(pszArgs);
3436 PVMCPU pVCpu = VMMGetCpu(pVM);
3437 if (!pVCpu)
3438 pVCpu = pVM->apCpusR3[0];
3439
3440 if (!HMIsEnabled(pVM))
3441 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3442 else if (HMIsVmxActive(pVM))
3443 {
3444 if (pVM->hm.s.vmx.fLbrCfg)
3445 {
3446 PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3447 uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3448
3449 /** @todo r=ramshankar: The index technically varies depending on the CPU, but
3450 * 0xf should cover everything we support thus far. Fix if necessary
3451 * later. */
3452 uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3453 if (idxTopOfStack > cLbrStack)
3454 {
3455 pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3456 idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3457 return;
3458 }
3459
3460 /*
3461 * Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3462 */
3463 pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3464 uint32_t idxCurrent = idxTopOfStack;
3465 Assert(idxTopOfStack < cLbrStack);
3466 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3467 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3468 for (;;)
3469 {
3470 if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3471 pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3472 pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3473 else
3474 pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3475
3476 idxCurrent = (idxCurrent - 1) % cLbrStack;
3477 if (idxCurrent == idxTopOfStack)
3478 break;
3479 }
3480 }
3481 else
3482 pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3483 }
3484 else
3485 {
3486 Assert(HMIsSvmActive(pVM));
3487 /** @todo SVM: LBRs (get them from VMCB if possible). */
3488 pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3489 }
3490}
3491
3492
3493/**
3494 * Displays the HM pending event.
3495 *
3496 * @param pVM The cross context VM structure.
3497 * @param pHlp The info helper functions.
3498 * @param pszArgs Arguments, ignored.
3499 */
3500static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3501{
3502 NOREF(pszArgs);
3503 PVMCPU pVCpu = VMMGetCpu(pVM);
3504 if (!pVCpu)
3505 pVCpu = pVM->apCpusR3[0];
3506
3507 if (HMIsEnabled(pVM))
3508 {
3509 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3510 if (pVCpu->hm.s.Event.fPending)
3511 {
3512 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3513 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3514 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3515 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3516 }
3517 }
3518 else
3519 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3520}
3521
3522
3523/**
3524 * Displays the SVM nested-guest VMCB cache.
3525 *
3526 * @param pVM The cross context VM structure.
3527 * @param pHlp The info helper functions.
3528 * @param pszArgs Arguments, ignored.
3529 */
3530static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3531{
3532 NOREF(pszArgs);
3533 PVMCPU pVCpu = VMMGetCpu(pVM);
3534 if (!pVCpu)
3535 pVCpu = pVM->apCpusR3[0];
3536
3537 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3538 if ( fSvmEnabled
3539 && pVM->cpum.ro.GuestFeatures.fSvm)
3540 {
3541 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3542 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3543 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3544 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3545 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3546 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3547 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3548 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3549 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3550 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3551 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3552 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3553 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3554 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3555 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3556 }
3557 else
3558 {
3559 if (!fSvmEnabled)
3560 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3561 else
3562 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3563 }
3564}
3565
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