HM.cpp

Last change on this file was 108739, checked in by vboxsync, 5 weeks ago
VMM/HM: Don't assert and fake success on a driverless build because the RING0 init completed notification is triggered always, even if there is no R0 component available, bugref:10391
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File size: 164.2 KB

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1	/* $Id: HM.cpp 108739 2025-03-25 14:08:37Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
29	*
30	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
31	* extensions.
32	*
33	* {summary of what HM does}
34	*
35	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
36	* however that was cumbersome to write and parse for such a central component,
37	* so it was shortened to HM when refactoring the code in the 4.3 development
38	* cycle.
39	*
40	* {add sections with more details}
41	*
42	* @sa @ref grp_hm
43	*/
44
45
46	/*********************************************************************************************************************************
47	* Header Files *
48	*********************************************************************************************************************************/
49	#define LOG_GROUP LOG_GROUP_HM
50	#define VMCPU_INCL_CPUM_GST_CTX
51	#include <VBox/vmm/cpum.h>
52	#include <VBox/vmm/stam.h>
53	#include <VBox/vmm/em.h>
54	#include <VBox/vmm/pdmapi.h>
55	#include <VBox/vmm/pgm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/gim.h>
58	#include <VBox/vmm/gcm.h>
59	#include <VBox/vmm/trpm.h>
60	#include <VBox/vmm/dbgf.h>
61	#include <VBox/vmm/iom.h>
62	#include <VBox/vmm/iem.h>
63	#include <VBox/vmm/selm.h>
64	#include <VBox/vmm/nem.h>
65	#include <VBox/vmm/hm_vmx.h>
66	#include <VBox/vmm/hm_svm.h>
67	#include "HMInternal.h"
68	#include <VBox/vmm/vmcc.h>
69	#include <VBox/err.h>
70	#include <VBox/param.h>
71
72	#include <iprt/assert.h>
73	#include <VBox/log.h>
74	#include <iprt/asm.h>
75	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
76	# include <iprt/asm-amd64-x86.h>
77	#endif
78	#include <iprt/env.h>
79	#include <iprt/thread.h>
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @def HMVMX_REPORT_FEAT
86	* Reports VT-x feature to the release log.
87	*
88	* @param a_uAllowed1 Mask of allowed-1 feature bits.
89	* @param a_uAllowed0 Mask of allowed-0 feature bits.
90	* @param a_StrDesc The description string to report.
91	* @param a_Featflag Mask of the feature to report.
92	*/
93	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
94	do { \
95	if ((a_uAllowed1) & (a_Featflag)) \
96	{ \
97	if ((a_uAllowed0) & (a_Featflag)) \
98	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
99	else \
100	LogRel(("HM: " a_StrDesc "\n")); \
101	} \
102	else \
103	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
104	} while (0)
105
106	/** @def HMVMX_REPORT_ALLOWED_FEAT
107	* Reports an allowed VT-x feature to the release log.
108	*
109	* @param a_uAllowed1 Mask of allowed-1 feature bits.
110	* @param a_StrDesc The description string to report.
111	* @param a_FeatFlag Mask of the feature to report.
112	*/
113	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
114	do { \
115	if ((a_uAllowed1) & (a_FeatFlag)) \
116	LogRel(("HM: " a_StrDesc "\n")); \
117	else \
118	LogRel(("HM: " a_StrDesc " not supported\n")); \
119	} while (0)
120
121	/** @def HMVMX_REPORT_MSR_CAP
122	* Reports MSR feature capability.
123	*
124	* @param a_MsrCaps Mask of MSR feature bits.
125	* @param a_StrDesc The description string to report.
126	* @param a_fCap Mask of the feature to report.
127	*/
128	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
129	do { \
130	if ((a_MsrCaps) & (a_fCap)) \
131	LogRel(("HM: " a_StrDesc "\n")); \
132	} while (0)
133
134	/** @def HMVMX_LOGREL_FEAT
135	* Dumps a feature flag from a bitmap of features to the release log.
136	*
137	* @param a_fVal The value of all the features.
138	* @param a_fMask The specific bitmask of the feature.
139	*/
140	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
141	do { \
142	if ((a_fVal) & (a_fMask)) \
143	LogRel(("HM: %s\n", #a_fMask)); \
144	} while (0)
145
146
147	/*********************************************************************************************************************************
148	* Internal Functions *
149	*********************************************************************************************************************************/
150	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
151	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
152	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
153	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
154	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
155	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static int hmR3InitFinalizeR3(PVM pVM);
157	#if defined(RT_ARCH_AMD64)
158	static int hmR3InitFinalizeR0(PVM pVM);
159	static int hmR3InitFinalizeR0Intel(PVM pVM);
160	static int hmR3InitFinalizeR0Amd(PVM pVM);
161	#endif
162	static int hmR3TermCPU(PVM pVM);
163
164
165	#ifdef VBOX_WITH_STATISTICS
166	/**
167	* Returns the name of the hardware exception.
168	*
169	* @returns The name of the hardware exception.
170	* @param uVector The exception vector.
171	*/
172	static const char *hmR3GetXcptName(uint8_t uVector)
173	{
174	switch (uVector)
175	{
176	case X86_XCPT_DE: return "#DE";
177	case X86_XCPT_DB: return "#DB";
178	case X86_XCPT_NMI: return "#NMI";
179	case X86_XCPT_BP: return "#BP";
180	case X86_XCPT_OF: return "#OF";
181	case X86_XCPT_BR: return "#BR";
182	case X86_XCPT_UD: return "#UD";
183	case X86_XCPT_NM: return "#NM";
184	case X86_XCPT_DF: return "#DF";
185	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
186	case X86_XCPT_TS: return "#TS";
187	case X86_XCPT_NP: return "#NP";
188	case X86_XCPT_SS: return "#SS";
189	case X86_XCPT_GP: return "#GP";
190	case X86_XCPT_PF: return "#PF";
191	case X86_XCPT_MF: return "#MF";
192	case X86_XCPT_AC: return "#AC";
193	case X86_XCPT_MC: return "#MC";
194	case X86_XCPT_XF: return "#XF";
195	case X86_XCPT_VE: return "#VE";
196	case X86_XCPT_CP: return "#CP";
197	case X86_XCPT_VC: return "#VC";
198	case X86_XCPT_SX: return "#SX";
199	}
200	return "Reserved";
201	}
202	#endif /* VBOX_WITH_STATISTICS */
203
204
205	/**
206	* Initializes the HM.
207	*
208	* This is the very first component to really do init after CFGM so that we can
209	* establish the predominant execution engine for the VM prior to initializing
210	* other modules. It takes care of NEM initialization if needed (HM disabled or
211	* not available in HW).
212	*
213	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
214	* hypervisor API via NEM, and then back on raw-mode if that isn't available
215	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
216	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
217	* X, OS/2 and others).
218	*
219	* Note that a lot of the set up work is done in ring-0 and thus postponed till
220	* the ring-3 and ring-0 callback to HMR3InitCompleted.
221	*
222	* @returns VBox status code.
223	* @param pVM The cross context VM structure.
224	*
225	* @remarks Be careful with what we call here, since most of the VMM components
226	* are uninitialized.
227	*/
228	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
229	{
230	LogFlowFunc(("\n"));
231
232	/*
233	* Assert alignment and sizes.
234	*/
235	AssertCompileMemberAlignment(VM, hm.s, 32);
236	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
237
238	/*
239	* Register the saved state data unit.
240	*/
241	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
242	NULL, NULL, NULL,
243	NULL, hmR3Save, NULL,
244	NULL, hmR3Load, NULL);
245	if (RT_FAILURE(rc))
246	return rc;
247
248	/*
249	* Read configuration.
250	*/
251	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
252
253	/*
254	* Validate the HM settings.
255	*/
256	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
257	"HMForced" /* implied 'true' these days */
258	"\|UseNEMInstead"
259	"\|FallbackToNEM"
260	"\|FallbackToIEM"
261	"\|EnableNestedPaging"
262	"\|EnableUX"
263	"\|EnableLargePages"
264	"\|EnableVPID"
265	"\|IBPBOnVMExit"
266	"\|IBPBOnVMEntry"
267	"\|SpecCtrlByHost"
268	"\|L1DFlushOnSched"
269	"\|L1DFlushOnVMEntry"
270	"\|MDSClearOnSched"
271	"\|MDSClearOnVMEntry"
272	"\|TPRPatchingEnabled"
273	"\|64bitEnabled"
274	"\|Exclusive"
275	"\|MaxResumeLoops"
276	"\|VmxPleGap"
277	"\|VmxPleWindow"
278	"\|VmxLbr"
279	"\|UseVmxPreemptTimer"
280	"\|SvmPauseFilter"
281	"\|SvmPauseFilterThreshold"
282	"\|SvmVirtVmsaveVmload"
283	"\|SvmVGif"
284	"\|LovelyMesaDrvWorkaround"
285	"\|MissingOS2TlbFlushWorkaround"
286	"\|AlwaysInterceptVmxMovDRx"
287	, "" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
288	if (RT_FAILURE(rc))
289	return rc;
290
291	/** @cfgm{/HM/HMForced, bool, false}
292	* Forces hardware virtualization, no falling back on raw-mode. HM must be
293	* enabled, i.e. /HMEnabled must be true. */
294	bool const fHMForced = true;
295	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
296	AssertRelease(pVM->fHMEnabled);
297	#else
298	AssertRelease(!pVM->fHMEnabled);
299	#endif
300
301	/** @cfgm{/HM/UseNEMInstead, bool, true}
302	* Don't use HM, use NEM instead. */
303	bool fUseNEMInstead = false;
304	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
305	AssertRCReturn(rc, rc);
306	if (fUseNEMInstead && pVM->fHMEnabled)
307	{
308	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
309	pVM->fHMEnabled = false;
310	}
311
312	/** @cfgm{/HM/FallbackToNEM, bool, true}
313	* Enables fallback on NEM. */
314	bool fFallbackToNEM = true;
315	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
319	* Enables fallback on NEM. */
320	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
321	bool fFallbackToIEM = false;
322	#else
323	bool fFallbackToIEM = true;
324	#endif
325	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
326	AssertRCReturn(rc, rc);
327
328	/** @cfgm{/HM/EnableNestedPaging, bool, false}
329	* Enables nested paging (aka extended page tables). */
330	bool fAllowNestedPaging = false;
331	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
332	AssertRCReturn(rc, rc);
333
334	/** @cfgm{/HM/EnableUX, bool, true}
335	* Enables the VT-x unrestricted execution feature. */
336	bool fAllowUnrestricted = true;
337	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
338	AssertRCReturn(rc, rc);
339
340	/** @cfgm{/HM/EnableLargePages, bool, false}
341	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
342	* page table walking and maybe better TLB hit rate in some cases. */
343	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
344	AssertRCReturn(rc, rc);
345
346	/** @cfgm{/HM/EnableVPID, bool, false}
347	* Enables the VT-x VPID feature. */
348	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
349	AssertRCReturn(rc, rc);
350
351	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
352	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
353	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
354	AssertRCReturn(rc, rc);
355
356	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
357	* Enables AMD64 cpu features.
358	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
359	* already have the support. */
360	#ifdef VBOX_WITH_64_BITS_GUESTS
361	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
362	AssertLogRelRCReturn(rc, rc);
363	#else
364	pVM->hm.s.fAllow64BitGuestsCfg = false;
365	#endif
366
367	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
368	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
369	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
370	* latest PAUSE instruction to be start of a new PAUSE loop.
371	*/
372	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
373	AssertRCReturn(rc, rc);
374
375	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
376	* The pause-filter exiting window in TSC ticks. When the number of ticks
377	* between the current PAUSE instruction and first PAUSE of a loop exceeds
378	* VmxPleWindow, a VM-exit is triggered.
379	*
380	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
381	*/
382	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
383	AssertRCReturn(rc, rc);
384
385	/** @cfgm{/HM/VmxLbr, bool, false}
386	* Whether to enable LBR for the guest. This is disabled by default as it's only
387	* useful while debugging and enabling it causes a noticeable performance hit. */
388	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
389	AssertRCReturn(rc, rc);
390
391	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
392	* A counter that is decrement each time a PAUSE instruction is executed by the
393	* guest. When the counter is 0, a \#VMEXIT is triggered.
394	*
395	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
396	*/
397	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
398	AssertRCReturn(rc, rc);
399
400	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
401	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
402	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
403	* PauseFilter count is reset to its initial value. However, if PAUSE is
404	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
405	* be triggered.
406	*
407	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
408	* activated.
409	*/
410	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
411	AssertRCReturn(rc, rc);
412
413	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
414	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
415	* available. */
416	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
417	AssertRCReturn(rc, rc);
418
419	/** @cfgm{/HM/SvmVGif, bool, true}
420	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
421	* if it's available. */
422	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
423	AssertRCReturn(rc, rc);
424
425	/** @cfgm{/HM/SvmLbrVirt, bool, false}
426	* Whether to make use of the LBR virtualization feature of the CPU if it's
427	* available. This is disabled by default as it's only useful while debugging
428	* and enabling it causes a small hit to performance. */
429	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
430	AssertRCReturn(rc, rc);
431
432	/** @cfgm{/HM/Exclusive, bool}
433	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
434	* global init for each host CPU. If false, we do local init each time we wish
435	* to execute guest code.
436	*
437	* On Windows, default is false due to the higher risk of conflicts with other
438	* hypervisors.
439	*
440	* On Mac OS X, this setting is ignored since the code does not handle local
441	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
442	*/
443	#if defined(RT_OS_DARWIN)
444	pVM->hm.s.fGlobalInit = true;
445	#else
446	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
447	# if defined(RT_OS_WINDOWS)
448	false
449	# else
450	true
451	# endif
452	);
453	AssertLogRelRCReturn(rc, rc);
454	#endif
455
456	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
457	* The number of times to resume guest execution before we forcibly return to
458	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
459	* determines the default value. */
460	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
461	AssertLogRelRCReturn(rc, rc);
462
463	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
464	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
465	* available. */
466	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
467	AssertLogRelRCReturn(rc, rc);
468
469	/** @cfgm{/HM/IBPBOnVMExit, bool}
470	* Costly paranoia setting. */
471	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
472	AssertLogRelRCReturn(rc, rc);
473
474	/** @cfgm{/HM/IBPBOnVMEntry, bool}
475	* Costly paranoia setting. */
476	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
477	AssertLogRelRCReturn(rc, rc);
478
479	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
480	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
481	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
482	AssertLogRelRCReturn(rc, rc);
483
484	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
485	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
486	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
487	AssertLogRelRCReturn(rc, rc);
488
489	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
490	if (pVM->hm.s.fL1dFlushOnVmEntry)
491	pVM->hm.s.fL1dFlushOnSched = false;
492
493	/** @cfgm{/HM/SpecCtrlByHost, bool}
494	* Another expensive paranoia setting. */
495	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
496	AssertLogRelRCReturn(rc, rc);
497
498	/** @cfgm{/HM/MDSClearOnSched, bool, true}
499	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
500	* ignored on CPUs that aren't affected. */
501	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
502	AssertLogRelRCReturn(rc, rc);
503
504	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
505	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
506	* ignored on CPUs that aren't affected. */
507	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
508	AssertLogRelRCReturn(rc, rc);
509
510	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
511	if (pVM->hm.s.fMdsClearOnVmEntry)
512	pVM->hm.s.fMdsClearOnSched = false;
513
514	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
515	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
516	* the hypervisor it is running under. */
517	bool fMesaWorkaround;
518	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
519	AssertLogRelRCReturn(rc, rc);
520	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
521	{
522	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
523	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
524	}
525
526	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
527	* Workaround OS/2 not flushing the TLB after page directory and page table
528	* modifications when returning to protected mode from a real mode call
529	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
530	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
531	AssertLogRelRCReturn(rc, rc);
532
533	/** @cfgm{/HM/AlwaysInterceptVmxMovDRx,int8_t,0}
534	* Whether to always intercept MOV DRx when using VMX.
535	* The value is a tristate: 1 for always intercepting, -1 for lazy intercept,
536	* and 0 for default. The default means that it's always intercepted when the
537	* host DR6 contains bits not known to the guest.
538	*
539	* With the introduction of transactional synchronization extensions new
540	* instructions, aka TSX-NI or RTM, bit 16 in DR6 is cleared to indicate that a
541	* \#DB was related to a transaction. The bit is also cleared when writing zero
542	* to it, so guest lazily resetting DR6 by writing 0 to it, ends up with an
543	* unexpected value. Similiarly, bit 11 in DR7 is used to enabled RTM
544	* debugging support and therefore writable by the guest.
545	*
546	* Out of caution/paranoia, we will by default intercept DRx moves when setting
547	* DR6 to zero (on the host) doesn't result in 0xffff0ff0 (X86_DR6_RA1_MASK).
548	* Note that it seems DR6.RTM remains writable even after the microcode updates
549	* disabling TSX. */
550	rc = CFGMR3QueryS8Def(pCfgHm, "AlwaysInterceptVmxMovDRx", &pVM->hm.s.vmx.fAlwaysInterceptMovDRxCfg, 0);
551	AssertLogRelRCReturn(rc, rc);
552
553	/*
554	* Check if VT-x or AMD-v support according to the users wishes.
555	*/
556	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
557	* VERR_SVM_IN_USE. */
558	if (pVM->fHMEnabled)
559	{
560	uint32_t fCaps;
561	rc = SUPR3QueryVTCaps(&fCaps);
562	if (RT_SUCCESS(rc))
563	{
564	if (fCaps & SUPVTCAPS_AMD_V)
565	{
566	pVM->hm.s.svm.fSupported = true;
567	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
568	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
569	}
570	else if (fCaps & SUPVTCAPS_VT_X)
571	{
572	const char *pszWhy;
573	rc = SUPR3QueryVTxSupported(&pszWhy);
574	if (RT_SUCCESS(rc))
575	{
576	pVM->hm.s.vmx.fSupported = true;
577	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
578	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
579	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
580	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
581	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
582	}
583	else
584	{
585	/*
586	* Before failing, try fallback to NEM if we're allowed to do that.
587	*/
588	pVM->fHMEnabled = false;
589	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
590	if (fFallbackToNEM)
591	{
592	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
593	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
594
595	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
596	if ( RT_SUCCESS(rc2)
597	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
598	rc = VINF_SUCCESS;
599	}
600	if (RT_FAILURE(rc))
601	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
602	}
603	}
604	else
605	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
606	VERR_INTERNAL_ERROR_5);
607
608	/*
609	* Disable nested paging and unrestricted guest execution now if they're
610	* configured so that CPUM can make decisions based on our configuration.
611	*/
612	if ( fAllowNestedPaging
613	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
614	{
615	pVM->hm.s.fNestedPagingCfg = true;
616	if (fCaps & SUPVTCAPS_VT_X)
617	{
618	if ( fAllowUnrestricted
619	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
620	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
621	else
622	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
623	}
624	}
625	else
626	Assert(!pVM->hm.s.fNestedPagingCfg);
627	}
628	else
629	{
630	const char *pszMsg;
631	switch (rc)
632	{
633	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
634	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
635	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
636	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
637	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
638	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
639	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
640	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
641	default:
642	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
643	}
644
645	/*
646	* Before failing, try fallback to NEM if we're allowed to do that.
647	*/
648	pVM->fHMEnabled = false;
649	if (fFallbackToNEM)
650	{
651	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
652	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
653	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
654	if ( RT_SUCCESS(rc2)
655	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
656	{
657	rc = VINF_SUCCESS;
658
659	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
660	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
661	}
662	}
663
664	/*
665	* Then try fall back on IEM if NEM isn't available and we're allowed to.
666	*/
667	if (RT_FAILURE(rc))
668	{
669	if ( fFallbackToIEM
670	&& (!fFallbackToNEM \|\| rc == VERR_NEM_NOT_AVAILABLE \|\| rc == VERR_SUP_DRIVERLESS))
671	{
672	LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
673	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
674	#ifdef VBOX_WITH_PGM_NEM_MODE
675	PGMR3EnableNemMode(pVM);
676	#endif
677	}
678	else
679	return VM_SET_ERROR(pVM, rc, pszMsg);
680	}
681	}
682	}
683	else
684	{
685	/*
686	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
687	*/
688	rc = VERR_NEM_NOT_AVAILABLE;
689	if (fUseNEMInstead)
690	{
691	rc = NEMR3Init(pVM, false /fFallback/, true);
692	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
693	if (RT_SUCCESS(rc))
694	{
695	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
696	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
697	}
698	else if (!fFallbackToIEM \|\| rc != VERR_NEM_NOT_AVAILABLE)
699	return rc;
700	}
701
702	if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
703	{
704	LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
705	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
706	#ifdef VBOX_WITH_PGM_NEM_MODE
707	PGMR3EnableNemMode(pVM);
708	#endif
709	}
710
711	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
712	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
713	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
714	}
715
716	if (pVM->fHMEnabled)
717	{
718	/*
719	* Register info handlers now that HM is used for sure.
720	*/
721	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
722	AssertRCReturn(rc, rc);
723
724	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
725	DBGFINFO_FLAGS_ALL_EMTS);
726	AssertRCReturn(rc, rc);
727
728	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
729	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
730	AssertRCReturn(rc, rc);
731
732	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
733	AssertRCReturn(rc, rc);
734	}
735
736	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
737	return VINF_SUCCESS;
738	}
739
740
741	/**
742	* Initializes HM components after ring-3 phase has been fully initialized.
743	*
744	* @returns VBox status code.
745	* @param pVM The cross context VM structure.
746	*/
747	static int hmR3InitFinalizeR3(PVM pVM)
748	{
749	LogFlowFunc(("\n"));
750
751	if (!HMIsEnabled(pVM))
752	return VINF_SUCCESS;
753
754	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
755	{
756	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
757	pVCpu->hm.s.fActive = false;
758	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
759	pVCpu->hm.s.fGCMTrapXcptDE = GCMIsInterceptingXcptDE(pVCpu); /* Is safe to call now since GCMR3Init() has completed. */
760	}
761
762	#if defined(RT_ARCH_AMD64) \|\|defined(RT_ARCH_X86) /* This section is duplicated in nemR3InitFinalizeSpecCtrl. */
763	/*
764	* Check if L1D flush is needed/possible.
765	*/
766	if ( !g_CpumHostFeatures.s.fFlushCmd
767	\|\| g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
768	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
769	\|\| g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d
770	\|\| g_CpumHostFeatures.s.fArchRdclNo)
771	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
772
773	/*
774	* Check if MDS flush is needed/possible.
775	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
776	*/
777	if ( !g_CpumHostFeatures.s.fMdsClear
778	\|\| g_CpumHostFeatures.s.fArchMdsNo)
779	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
780	else if ( ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
781	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
782	\|\| ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
783	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
784	{
785	if (!pVM->hm.s.fMdsClearOnSched)
786	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
787	pVM->hm.s.fMdsClearOnVmEntry = false;
788	}
789	else if ( g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
790	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
791	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
792	#endif
793
794	/*
795	* Statistics.
796	*/
797	#ifdef VBOX_WITH_STATISTICS
798	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
799	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
800	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
801	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
802	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
803	#endif
804
805	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
806	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
807	#else
808	bool const fCpuSupportsVmx = false;
809	#endif
810	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
811	{
812	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
813	PHMCPU pHmCpu = &pVCpu->hm.s;
814	int rc;
815
816	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
817	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
818	AssertRC(rc); \
819	} while (0)
820	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
821	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
822
823	#ifdef VBOX_WITH_STATISTICS
824	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
825	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
826	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
827	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
828	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
829	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
830	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
831	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
832	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
833	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
834	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
835	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
836	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
837	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
838	# ifdef HM_PROFILE_EXIT_DISPATCH
839	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
840	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
841	# endif
842	#endif
843	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
844
845	HM_REG_COUNTER(&pHmCpu->StatImportGuestStateFallback, "/HM/CPU%u/ImportGuestStateFallback", "Times vmxHCImportGuestState took the fallback code path.");
846	HM_REG_COUNTER(&pHmCpu->StatReadToTransientFallback, "/HM/CPU%u/ReadToTransientFallback", "Times vmxHCReadToTransient took the fallback code path.");
847	#ifdef VBOX_WITH_STATISTICS
848	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
849	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
850	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/ExitNestedGuest/All", "Total nested-guest exits.");
851	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
852	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
853	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
854	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
855	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
856	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
857	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
858	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
859	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
860	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
861	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
862	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
863	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
864	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
865	#endif
866	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
867	if (fCpuSupportsVmx)
868	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
869	#ifdef VBOX_WITH_STATISTICS
870	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
871	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
872	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
873	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
874	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
875	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
876	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
877	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
878	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
879	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
880	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
881	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
882	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
883	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
884	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
885	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
886	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
887	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
888	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
889	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
890	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
891	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
892	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
893	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
894	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
895	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
896	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
897	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
898	#endif
899	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
900	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
901	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
902	#ifdef VBOX_WITH_STATISTICS
903	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
904	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
905	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
906
907	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
908	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
909	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
910	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
911	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
912	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
913	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
914	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
915	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
916	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
917	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
918	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
919	#endif
920	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
921	#ifdef VBOX_WITH_STATISTICS
922	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
923
924	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
925	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
926	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
927	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
928	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
929	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
930
931	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
932	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
933	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
934	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
935	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
936	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
937	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
938	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
939	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
940	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
941	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
942	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
943	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
944	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
945	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
946
947	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
948	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
949	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
950
951	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
952	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
953	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
954
955	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
956	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
957	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
958	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
959
960	if (fCpuSupportsVmx)
961	{
962	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
963	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
964	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
965	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
966	}
967
968	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
969	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
970	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
971
972	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
973	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
974	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
975
976	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
977	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
978	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
979	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
980	HM_REG_COUNTER(&pHmCpu->StatVmxCheck1, "/HM/CPU%u/VMXCheck/1", "Could not use VMX due to unsuitable state and no VMMDev heap");
981	HM_REG_COUNTER(&pHmCpu->StatVmxCheck2, "/HM/CPU%u/VMXCheck/2", "CR0/CR4 fixed stuff.");
982	HM_REG_COUNTER(&pHmCpu->StatVmxCheckDisabled, "/HM/CPU%u/VMXCheck/Disabled", "VMX is not enabled.");
983	HM_REG_COUNTER(&pHmCpu->StatVmxCheckOk, "/HM/CPU%u/VMXCheck/Ok", "We could do VMX!");
984	#endif
985	if (fCpuSupportsVmx)
986	{
987	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
988	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
989	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
990	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
991	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
992	}
993	#ifdef VBOX_WITH_STATISTICS
994	/*
995	* Guest Exit reason stats.
996	*/
997	if (fCpuSupportsVmx)
998	{
999	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1000	{
1001	const char *pszExitName = HMGetVmxExitName(j);
1002	if (pszExitName)
1003	{
1004	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1005	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1006	AssertRCReturn(rc, rc);
1007	}
1008	}
1009	}
1010	else
1011	{
1012	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1013	{
1014	const char *pszExitName = HMGetSvmExitName(j);
1015	if (pszExitName)
1016	{
1017	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1018	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
1019	AssertRC(rc);
1020	}
1021	}
1022	}
1023	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
1024
1025	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1026	/*
1027	* Nested-guest VM-exit reason stats.
1028	*/
1029	if (fCpuSupportsVmx)
1030	{
1031	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1032	{
1033	const char *pszExitName = HMGetVmxExitName(j);
1034	if (pszExitName)
1035	{
1036	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1037	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1038	AssertRC(rc);
1039	}
1040	}
1041	HM_REG_COUNTER(&pHmCpu->StatNestedExitACSplitLock, "/HM/CPU%u/ExitNestedGuest/Trap/#AC-split-lock", "Nested-guest triggered #AC due to split-lock being enabled on the host.");
1042	}
1043	else
1044	{
1045	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1046	{
1047	const char *pszExitName = HMGetSvmExitName(j);
1048	if (pszExitName)
1049	{
1050	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1051	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/ExitNestedGuest/Reason/%02x", idCpu, j);
1052	AssertRC(rc);
1053	}
1054	}
1055	}
1056	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/ExitNestedGuest/Reason/#NPF", "Nested page faults");
1057	#endif
1058
1059	/*
1060	* Injected interrupts stats.
1061	*/
1062	char szDesc[64];
1063	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1064	{
1065	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1066	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1067	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1068	AssertRC(rc);
1069	}
1070
1071	/*
1072	* Injected exception stats.
1073	*/
1074	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1075	{
1076	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1077	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1078	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1079	AssertRC(rc);
1080	}
1081
1082	#endif /* VBOX_WITH_STATISTICS */
1083	#undef HM_REG_COUNTER
1084	#undef HM_REG_PROFILE
1085	#undef HM_REG_STAT
1086	}
1087
1088	return VINF_SUCCESS;
1089	}
1090
1091
1092	/**
1093	* Called when a init phase has completed.
1094	*
1095	* @returns VBox status code.
1096	* @param pVM The cross context VM structure.
1097	* @param enmWhat The phase that completed.
1098	*/
1099	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1100	{
1101	switch (enmWhat)
1102	{
1103	case VMINITCOMPLETED_RING3:
1104	return hmR3InitFinalizeR3(pVM);
1105	#if defined(RT_ARCH_AMD64)
1106	case VMINITCOMPLETED_RING0:
1107	return hmR3InitFinalizeR0(pVM);
1108	#else
1109	case VMINITCOMPLETED_RING0:
1110	#endif
1111	default:
1112	return VINF_SUCCESS;
1113	}
1114	}
1115
1116
1117	/**
1118	* Turns off normal raw mode features.
1119	*
1120	* @param pVM The cross context VM structure.
1121	*/
1122	static void hmR3DisableRawMode(PVM pVM)
1123	{
1124	/** @todo r=bird: HM shouldn't be doing this crap. */
1125	/* Reinit the paging mode to force the new shadow mode. */
1126	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1127	{
1128	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1129	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1130	}
1131	}
1132
1133
1134	#if defined(RT_ARCH_AMD64)
1135	/**
1136	* Initialize VT-x or AMD-V.
1137	*
1138	* @returns VBox status code.
1139	* @param pVM The cross context VM structure.
1140	*/
1141	static int hmR3InitFinalizeR0(PVM pVM)
1142	{
1143	int rc;
1144
1145	/*
1146	* Since HM is in charge of large pages, if large pages isn't supported on Intel CPUs,
1147	* we must disable it here. Doing it here rather than in hmR3InitFinalizeR0Intel covers
1148	* the case of informing PGM even when NEM is the execution engine.
1149	*/
1150	if ( pVM->hm.s.fLargePages
1151	&& pVM->hm.s.vmx.fSupported
1152	&& !(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps & MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M))
1153	{
1154	pVM->hm.s.fLargePages = false;
1155	PGMSetLargePageUsage(pVM, false);
1156	LogRel(("HM: Disabled large page support as the CPU doesn't allow EPT PDEs to map 2MB pages\n"));
1157	}
1158
1159	if (!HMIsEnabled(pVM))
1160	return VINF_SUCCESS;
1161
1162	/*
1163	* Hack to allow users to work around broken BIOSes that incorrectly set
1164	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1165	*/
1166	if ( !pVM->hm.s.vmx.fSupported
1167	&& !pVM->hm.s.svm.fSupported
1168	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1169	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1170	{
1171	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1172	pVM->hm.s.svm.fSupported = true;
1173	pVM->hm.s.svm.fIgnoreInUseError = true;
1174	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1175	}
1176
1177	/*
1178	* Report ring-0 init errors.
1179	*/
1180	if ( !pVM->hm.s.vmx.fSupported
1181	&& !pVM->hm.s.svm.fSupported)
1182	{
1183	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1184	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1185	switch (pVM->hm.s.ForR3.rcInit)
1186	{
1187	case VERR_VMX_IN_VMX_ROOT_MODE:
1188	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1189	case VERR_VMX_NO_VMX:
1190	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1191	case VERR_VMX_MSR_VMX_DISABLED:
1192	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1193	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1194	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1195	case VERR_VMX_MSR_LOCKING_FAILED:
1196	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1197	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1198	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1199	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1200	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1201
1202	case VERR_SVM_IN_USE:
1203	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1204	case VERR_SVM_NO_SVM:
1205	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1206	case VERR_SVM_DISABLED:
1207	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1208	}
1209	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1210	}
1211
1212	/*
1213	* Enable VT-x or AMD-V on all host CPUs.
1214	*/
1215	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1216	if (RT_FAILURE(rc))
1217	{
1218	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1219	HMR3CheckError(pVM, rc);
1220	return rc;
1221	}
1222
1223	/*
1224	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1225	* (Main should have taken care of this already)
1226	*/
1227	if (!PDMHasIoApic(pVM))
1228	{
1229	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1230	pVM->hm.s.fTprPatchingAllowed = false;
1231	}
1232
1233	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1234	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1235	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1236
1237	/*
1238	* Do the vendor specific initialization
1239	*
1240	* Note! We disable release log buffering here since we're doing relatively
1241	* lot of logging and doesn't want to hit the disk with each LogRel
1242	* statement.
1243	*/
1244	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1245	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1246	if (pVM->hm.s.vmx.fSupported)
1247	rc = hmR3InitFinalizeR0Intel(pVM);
1248	else
1249	rc = hmR3InitFinalizeR0Amd(pVM);
1250	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1251	: "HM: VT-x/AMD-V init method: Local\n"));
1252	RTLogRelSetBuffering(fOldBuffered);
1253	pVM->hm.s.fInitialized = true;
1254
1255	return rc;
1256	}
1257
1258
1259	/**
1260	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1261	*/
1262	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1263	{
1264	NOREF(pVM);
1265	NOREF(pvAllocation);
1266	NOREF(GCPhysAllocation);
1267	}
1268
1269
1270	/**
1271	* Returns a description of the VMCS (and associated regions') memory type given the
1272	* IA32_VMX_BASIC MSR.
1273	*
1274	* @returns The descriptive memory type.
1275	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1276	*/
1277	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1278	{
1279	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1280	switch (uMemType)
1281	{
1282	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1283	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1284	}
1285	return "Unknown";
1286	}
1287
1288
1289	/**
1290	* Returns a single-line description of all the activity-states supported by the CPU
1291	* given the IA32_VMX_MISC MSR.
1292	*
1293	* @returns All supported activity states.
1294	* @param uMsrMisc IA32_VMX_MISC MSR value.
1295	*/
1296	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1297	{
1298	static const char * const s_apszActStates[] =
1299	{
1300	"",
1301	" ( HLT )",
1302	" ( SHUTDOWN )",
1303	" ( HLT SHUTDOWN )",
1304	" ( SIPI_WAIT )",
1305	" ( HLT SIPI_WAIT )",
1306	" ( SHUTDOWN SIPI_WAIT )",
1307	" ( HLT SHUTDOWN SIPI_WAIT )"
1308	};
1309	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1310	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1311	return s_apszActStates[idxActStates];
1312	}
1313
1314
1315	/**
1316	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1317	*
1318	* @param fFeatMsr The feature control MSR value.
1319	*/
1320	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1321	{
1322	uint64_t const val = fFeatMsr;
1323	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1324	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1325	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1326	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1327	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1328	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1329	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1330	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1331	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1332	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1333	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1334	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1335	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1336	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1337	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1338	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1339	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1340	}
1341
1342
1343	/**
1344	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1345	*
1346	* @param uBasicMsr The VMX basic MSR value.
1347	*/
1348	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1349	{
1350	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1351	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1352	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1353	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1354	"< 4 GB" : "None"));
1355	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1356	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1357	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1358	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1359	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1360	}
1361
1362
1363	/**
1364	* Reports MSR_IA32_PINBASED_CTLS to the log.
1365	*
1366	* @param pVmxMsr Pointer to the VMX MSR.
1367	*/
1368	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1369	{
1370	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1371	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1372	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1378	}
1379
1380
1381	/**
1382	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1383	*
1384	* @param pVmxMsr Pointer to the VMX MSR.
1385	*/
1386	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1387	{
1388	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1389	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1390	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1410	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1411	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1412	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1413	}
1414
1415
1416	/**
1417	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1418	*
1419	* @param pVmxMsr Pointer to the VMX MSR.
1420	*/
1421	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1422	{
1423	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1424	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1425	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1432	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1433	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1434	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1435	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1436	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1437	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1438	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1439	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1440	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1441	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1442	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1443	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1444	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1445	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1446	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1447	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PASID_TRANSLATE", VMX_PROC_CTLS2_PASID_TRANSLATE);
1448	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1449	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1450	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1451	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1452	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1453	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PCONFIG", VMX_PROC_CTLS2_PCONFIG);
1454	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1455	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "BUS_LOCK_DETECT", VMX_PROC_CTLS2_BUS_LOCK_DETECT);
1456	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INSTR_TIMEOUT", VMX_PROC_CTLS2_INSTR_TIMEOUT);
1457	}
1458
1459
1460	/**
1461	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1462	*
1463	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1464	*/
1465	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1466	{
1467	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1468	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1469	LogRel(("HM: HLAT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_HLAT)));
1470	LogRel(("HM: EPT_PAGING_WRITE = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_EPT_PAGING_WRITE)));
1471	LogRel(("HM: GST_PAGING_VERIFY = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_GST_PAGING_VERIFY)));
1472	LogRel(("HM: IPI_VIRT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_IPI_VIRT)));
1473	LogRel(("HM: VIRT_SPEC_CTRL = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_VIRT_SPEC_CTRL)));
1474	}
1475
1476
1477	/**
1478	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1479	*
1480	* @param pVmxMsr Pointer to the VMX MSR.
1481	*/
1482	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1483	{
1484	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1485	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1486	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1487	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1488	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1489	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1490	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1491	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1492	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1493	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1494	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1495	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1496	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1497	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_UINV", VMX_ENTRY_CTLS_LOAD_UINV);
1498	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1499	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_LBR_CTL_MSR", VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR);
1500	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1501	}
1502
1503
1504	/**
1505	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1506	*
1507	* @param pVmxMsr Pointer to the VMX MSR.
1508	*/
1509	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1510	{
1511	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1512	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1513	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1514	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1515	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1516	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1517	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1518	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1519	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1520	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1521	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1522	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1523	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1524	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1525	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1526	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_LBR_CTL_MSR", VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR);
1527	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_UINV", VMX_EXIT_CTLS_CLEAR_UINV);
1528	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1529	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1530	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PERF_MSR", VMX_EXIT_CTLS_SAVE_PERF_MSR);
1531	}
1532
1533
1534	/**
1535	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1536	*
1537	* @param fCaps The VMX EPT/VPID capability MSR value.
1538	*/
1539	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1540	{
1541	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1542	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1543	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1544	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1545	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1546	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1547	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1548	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1549	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1550	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1551	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1552	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1553	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1554	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1555	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1556	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1557	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1558	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1559	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1560	}
1561
1562
1563	/**
1564	* Reports MSR_IA32_VMX_MISC MSR to the log.
1565	*
1566	* @param pVM Pointer to the VM.
1567	* @param fMisc The VMX misc. MSR value.
1568	*/
1569	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1570	{
1571	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1572	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1573	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1574	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1575	else
1576	{
1577	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1578	pVM->hm.s.vmx.cPreemptTimerShift));
1579	}
1580	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1581	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1582	hmR3VmxGetActivityStateAllDesc(fMisc)));
1583	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1584	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1585	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1586	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1587	VMX_MISC_MAX_MSRS(fMisc)));
1588	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1589	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1590	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1591	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1592	}
1593
1594
1595	/**
1596	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1597	*
1598	* @param uVmcsEnum The VMX VMCS enum MSR value.
1599	*/
1600	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1601	{
1602	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1603	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1604	}
1605
1606
1607	/**
1608	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1609	*
1610	* @param uVmFunc The VMX VMFUNC MSR value.
1611	*/
1612	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1613	{
1614	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1615	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1616	}
1617
1618
1619	/**
1620	* Reports VMX CR0, CR4 fixed MSRs.
1621	*
1622	* @param pMsrs Pointer to the VMX MSRs.
1623	*/
1624	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1625	{
1626	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1627	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1628	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1629	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1630	}
1631
1632
1633	/**
1634	* Finish VT-x initialization (after ring-0 init).
1635	*
1636	* @returns VBox status code.
1637	* @param pVM The cross context VM structure.
1638	*/
1639	static int hmR3InitFinalizeR0Intel(PVM pVM)
1640	{
1641	int rc;
1642
1643	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1644	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1645
1646	LogRel(("HM: Using VT-x implementation 3.0\n"));
1647	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1648	LogRel(("HM: Host CR0 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr0));
1649	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1650	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1651	LogRel(("HM: Host SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1652	LogRel(("HM: Host CORE_CAPABILITIES = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCoreCap));
1653	LogRel(("HM: Host MEMORY_CTRL = %#RX64%s\n", pVM->hm.s.ForR3.vmx.u64HostMemoryCtrl,
1654	pVM->hm.s.ForR3.vmx.u64HostMemoryCtrl & MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE ? " - split-lock disable!" : ""));
1655	LogRel(("HM: Host DR6 zero'ed = %#RX64%s\n", pVM->hm.s.ForR3.vmx.u64HostDr6Zeroed,
1656	pVM->hm.s.ForR3.vmx.fAlwaysInterceptMovDRx ? " - always intercept MOV DRx" : ""));
1657
1658	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1659	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1660
1661	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1662	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1663	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1664	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1665	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1666	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1667
1668	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1669	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1670
1671	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1672	{
1673	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1674	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1675	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1676	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1677	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1678	}
1679
1680	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1681	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1682	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1683	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1684	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1685	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1686	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1687
1688	#ifdef TODO_9217_VMCSINFO
1689	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1690	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1691	{
1692	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1693	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1694	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1695	}
1696	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1697	if (pVM->cpum.ro.GuestFeatures.fVmx)
1698	{
1699	LogRel(("HM: Nested-guest:\n"));
1700	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1701	{
1702	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1703	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1704	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1705	}
1706	}
1707	#endif
1708	#endif /* TODO_9217_VMCSINFO */
1709
1710	/*
1711	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1712	*/
1713	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1714	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1715	VERR_HM_IPE_1);
1716	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1717	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1718	&& pVM->hm.s.fNestedPagingCfg),
1719	VERR_HM_IPE_1);
1720
1721	/*
1722	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1723	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1724	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1725	*/
1726	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1727	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1728	{
1729	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1730	LogRel(("HM: Disabled RDTSCP\n"));
1731	}
1732
1733	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1734	{
1735	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1736	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1737	if (RT_SUCCESS(rc))
1738	{
1739	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1740	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1741	esp. Figure 20-5.*/
1742	RT_BZERO(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1743	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1744
1745	/* Bit set to 0 means software interrupts are redirected to the
1746	8086 program interrupt handler rather than switching to
1747	protected-mode handler. */
1748	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1749
1750	/* Allow all port IO, so that port IO instructions do not cause
1751	exceptions and would instead cause a VM-exit (based on VT-x's
1752	IO bitmap which we currently configure to always cause an exit). */
1753	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1754	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1755
1756	/*
1757	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1758	* page table used in real and protected mode without paging with EPT.
1759	*/
1760	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1761	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1762	{
1763	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1764	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1765	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1766	\| X86_PDE4M_G;
1767	}
1768
1769	/* We convert it here every time as PCI regions could be reconfigured. */
1770	if (PDMVmmDevHeapIsEnabled(pVM))
1771	{
1772	RTGCPHYS GCPhys;
1773	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1774	AssertRCReturn(rc, rc);
1775	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1776
1777	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1778	AssertRCReturn(rc, rc);
1779	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1780	}
1781	}
1782	else
1783	{
1784	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1785	pVM->hm.s.vmx.pRealModeTSS = NULL;
1786	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1787	return VMSetError(pVM, rc, RT_SRC_POS,
1788	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1789	}
1790	}
1791
1792	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1793	: "HM: Guest support: 32-bit only\n"));
1794
1795	/*
1796	* Call ring-0 to set up the VM.
1797	*/
1798	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1799	if (rc != VINF_SUCCESS)
1800	{
1801	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1802	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1803	{
1804	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1805	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1806	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1807	}
1808	HMR3CheckError(pVM, rc);
1809	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1810	}
1811
1812	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1813	LogRel(("HM: Enabled VMX\n"));
1814	pVM->hm.s.vmx.fEnabled = true;
1815
1816	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1817
1818	/*
1819	* Log configuration details.
1820	*/
1821	if (pVM->hm.s.fNestedPagingCfg)
1822	{
1823	LogRel(("HM: Enabled nested paging\n"));
1824	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1825	LogRel(("HM: EPT flush type = Single context\n"));
1826	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1827	LogRel(("HM: EPT flush type = All contexts\n"));
1828	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1829	LogRel(("HM: EPT flush type = Not supported\n"));
1830	else
1831	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1832
1833	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1834	LogRel(("HM: Enabled unrestricted guest execution\n"));
1835
1836	if (pVM->hm.s.fLargePages)
1837	{
1838	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1839	PGMSetLargePageUsage(pVM, true);
1840	LogRel(("HM: Enabled large page support\n"));
1841	}
1842	}
1843	else
1844	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1845
1846	if (pVM->hm.s.ForR3.vmx.fVpid)
1847	{
1848	LogRel(("HM: Enabled VPID\n"));
1849	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1850	LogRel(("HM: VPID flush type = Individual addresses\n"));
1851	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1852	LogRel(("HM: VPID flush type = Single context\n"));
1853	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1854	LogRel(("HM: VPID flush type = All contexts\n"));
1855	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1856	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1857	else
1858	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1859	}
1860	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1861	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1862
1863	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1864	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1865	else
1866	LogRel(("HM: Disabled VMX-preemption timer\n"));
1867
1868	if (pVM->hm.s.fVirtApicRegs)
1869	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1870
1871	if (pVM->hm.s.fPostedIntrs)
1872	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1873
1874	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1875	{
1876	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1877	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1878	}
1879
1880	return VINF_SUCCESS;
1881	}
1882
1883
1884	/**
1885	* Finish AMD-V initialization (after ring-0 init).
1886	*
1887	* @returns VBox status code.
1888	* @param pVM The cross context VM structure.
1889	*/
1890	static int hmR3InitFinalizeR0Amd(PVM pVM)
1891	{
1892	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1893
1894	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1895
1896	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1897	uint32_t u32Family;
1898	uint32_t u32Model;
1899	uint32_t u32Stepping;
1900	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1901	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1902	#endif
1903	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1904	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1905	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1906	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1907	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1908
1909	/*
1910	* Enumerate AMD-V features.
1911	*/
1912	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1913	{
1914	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1915	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1916	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1917	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1918	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1919	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1920	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1921	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1922	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1923	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1924	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1925	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1926	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1927	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1928	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1929	HMSVM_REPORT_FEATURE("X2AVIC", X86_CPUID_SVM_FEATURE_EDX_X2AVIC),
1930	HMSVM_REPORT_FEATURE("SSSCHECK", X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
1931	HMSVM_REPORT_FEATURE("SPEC_CTRL", X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
1932	HMSVM_REPORT_FEATURE("ROGPT", X86_CPUID_SVM_FEATURE_EDX_ROGPT),
1933	HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE", X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
1934	HMSVM_REPORT_FEATURE("TLBICTL", X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
1935	HMSVM_REPORT_FEATURE("VNMI", X86_CPUID_SVM_FEATURE_EDX_VNMI),
1936	HMSVM_REPORT_FEATURE("IBS_VIRT", X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT),
1937	HMSVM_REPORT_FEATURE("EXT_LVT_AVIC_ACCESS_CHG", X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG),
1938	HMSVM_REPORT_FEATURE("NST_VIRT_VMCB_ADDR_CHK", X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK),
1939	HMSVM_REPORT_FEATURE("BUS_LOCK_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD),
1940	#undef HMSVM_REPORT_FEATURE
1941	};
1942
1943	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1944	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1945	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1946	{
1947	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1948	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1949	}
1950	if (fSvmFeatures)
1951	for (unsigned iBit = 0; iBit < 32; iBit++)
1952	if (RT_BIT_32(iBit) & fSvmFeatures)
1953	LogRel(("HM: Reserved bit %u\n", iBit));
1954
1955	/*
1956	* Nested paging is determined in HMR3Init, verify the sanity of that.
1957	*/
1958	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1959	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1960	VERR_HM_IPE_1);
1961
1962	#if 0
1963	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1964	* here. */
1965	if (RTR0IsPostIpiSupport())
1966	pVM->hm.s.fPostedIntrs = true;
1967	#endif
1968
1969	/*
1970	* Determine whether we need to intercept #UD in SVM mode for emulating
1971	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1972	* when executed in long-mode. This is only really applicable when
1973	* non-default CPU profiles are in effect, i.e. guest vendor differs
1974	* from the host one.
1975	*/
1976	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1977	switch (CPUMGetGuestCpuVendor(pVM))
1978	{
1979	case CPUMCPUVENDOR_INTEL:
1980	case CPUMCPUVENDOR_VIA: /?/
1981	case CPUMCPUVENDOR_SHANGHAI: /?/
1982	{
1983	switch (CPUMGetHostCpuVendor(pVM))
1984	{
1985	case CPUMCPUVENDOR_AMD:
1986	case CPUMCPUVENDOR_HYGON:
1987	{
1988	if (pVM->hm.s.fAllow64BitGuestsCfg)
1989	{
1990	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1991	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1992	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1993	}
1994	break;
1995	}
1996	default:
1997	break;
1998	}
1999	break;
2000	}
2001	default:
2002	break;
2003	}
2004
2005	/*
2006	* Call ring-0 to set up the VM.
2007	*/
2008	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
2009	if (rc != VINF_SUCCESS)
2010	{
2011	AssertMsgFailed(("%Rrc\n", rc));
2012	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
2013	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
2014	}
2015
2016	LogRel(("HM: Enabled SVM\n"));
2017	pVM->hm.s.svm.fEnabled = true;
2018
2019	if (pVM->hm.s.fNestedPagingCfg)
2020	{
2021	LogRel(("HM: Enabled nested paging\n"));
2022
2023	/*
2024	* Enable large pages (2 MB) if applicable.
2025	*/
2026	if (pVM->hm.s.fLargePages)
2027	{
2028	PGMSetLargePageUsage(pVM, true);
2029	LogRel(("HM: Enabled large page support\n"));
2030	}
2031	}
2032
2033	if (pVM->hm.s.fVirtApicRegs)
2034	LogRel(("HM: Enabled APIC-register virtualization support\n"));
2035
2036	if (pVM->hm.s.fPostedIntrs)
2037	LogRel(("HM: Enabled posted-interrupt processing support\n"));
2038
2039	hmR3DisableRawMode(pVM);
2040
2041	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
2042	: "HM: Disabled TPR patching\n"));
2043
2044	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
2045	: "HM: Guest support: 32-bit only\n"));
2046	return VINF_SUCCESS;
2047	}
2048	#endif
2049
2050
2051	/**
2052	* Applies relocations to data and code managed by this
2053	* component. This function will be called at init and
2054	* whenever the VMM need to relocate it self inside the GC.
2055	*
2056	* @param pVM The cross context VM structure.
2057	*/
2058	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2059	{
2060	/* Fetch the current paging mode during the relocate callback during state loading. */
2061	if (VMR3GetState(pVM) == VMSTATE_LOADING)
2062	{
2063	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2064	{
2065	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2066	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2067	}
2068	}
2069	}
2070
2071
2072	/**
2073	* Terminates the HM.
2074	*
2075	* Termination means cleaning up and freeing all resources,
2076	* the VM itself is, at this point, powered off or suspended.
2077	*
2078	* @returns VBox status code.
2079	* @param pVM The cross context VM structure.
2080	*/
2081	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2082	{
2083	if (pVM->hm.s.vmx.pRealModeTSS)
2084	{
2085	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2086	pVM->hm.s.vmx.pRealModeTSS = 0;
2087	}
2088	hmR3TermCPU(pVM);
2089	return 0;
2090	}
2091
2092
2093	/**
2094	* Terminates the per-VCPU HM.
2095	*
2096	* @returns VBox status code.
2097	* @param pVM The cross context VM structure.
2098	*/
2099	static int hmR3TermCPU(PVM pVM)
2100	{
2101	RT_NOREF(pVM);
2102	return VINF_SUCCESS;
2103	}
2104
2105
2106	/**
2107	* Resets a virtual CPU.
2108	*
2109	* Used by HMR3Reset and CPU hot plugging.
2110	*
2111	* @param pVCpu The cross context virtual CPU structure to reset.
2112	*/
2113	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2114	{
2115	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2116	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2117	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2118
2119	pVCpu->hm.s.fActive = false;
2120	pVCpu->hm.s.Event.fPending = false;
2121	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2122	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2123	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2124	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2125	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2126	#endif
2127	}
2128
2129
2130	/**
2131	* The VM is being reset.
2132	*
2133	* For the HM component this means that any GDT/LDT/TSS monitors
2134	* needs to be removed.
2135	*
2136	* @param pVM The cross context VM structure.
2137	*/
2138	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2139	{
2140	LogFlow(("HMR3Reset:\n"));
2141
2142	if (HMIsEnabled(pVM))
2143	hmR3DisableRawMode(pVM);
2144
2145	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2146	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2147
2148	/* Clear all patch information. */
2149	pVM->hm.s.pGuestPatchMem = 0;
2150	pVM->hm.s.pFreeGuestPatchMem = 0;
2151	pVM->hm.s.cbGuestPatchMem = 0;
2152	pVM->hm.s.cPatches = 0;
2153	pVM->hm.s.PatchTree = 0;
2154	pVM->hm.s.fTprPatchingActive = false;
2155	RT_BZERO(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2156	}
2157
2158
2159	/**
2160	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2161	*
2162	* @returns VBox strict status code.
2163	* @param pVM The cross context VM structure.
2164	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2165	* @param pvUser Unused.
2166	*/
2167	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2168	{
2169	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2170
2171	/* Only execute the handler on the VCPU the original patch request was issued. */
2172	if (pVCpu->idCpu != idCpu)
2173	return VINF_SUCCESS;
2174
2175	Log(("hmR3RemovePatches\n"));
2176	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2177	{
2178	uint8_t abInstr[15];
2179	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2180	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2181	int rc;
2182
2183	#ifdef LOG_ENABLED
2184	char szOutput[256];
2185	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2186	szOutput, sizeof(szOutput), NULL);
2187	if (RT_SUCCESS(rc))
2188	Log(("Patched instr: %s\n", szOutput));
2189	#endif
2190
2191	/* Check if the instruction is still the same. */
2192	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2193	if (rc != VINF_SUCCESS)
2194	{
2195	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2196	continue; /* swapped out or otherwise removed; skip it. */
2197	}
2198
2199	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2200	{
2201	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2202	continue; /* skip it. */
2203	}
2204
2205	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2206	AssertRC(rc);
2207
2208	#ifdef LOG_ENABLED
2209	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2210	szOutput, sizeof(szOutput), NULL);
2211	if (RT_SUCCESS(rc))
2212	Log(("Original instr: %s\n", szOutput));
2213	#endif
2214	}
2215	pVM->hm.s.cPatches = 0;
2216	pVM->hm.s.PatchTree = 0;
2217	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2218	pVM->hm.s.fTprPatchingActive = false;
2219	return VINF_SUCCESS;
2220	}
2221
2222
2223	/**
2224	* Worker for enabling patching in a VT-x/AMD-V guest.
2225	*
2226	* @returns VBox status code.
2227	* @param pVM The cross context VM structure.
2228	* @param idCpu VCPU to execute hmR3RemovePatches on.
2229	* @param pPatchMem Patch memory range.
2230	* @param cbPatchMem Size of the memory range.
2231	*/
2232	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2233	{
2234	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2235	AssertRC(rc);
2236
2237	pVM->hm.s.pGuestPatchMem = pPatchMem;
2238	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2239	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244	/**
2245	* Enable patching in a VT-x/AMD-V guest
2246	*
2247	* @returns VBox status code.
2248	* @param pVM The cross context VM structure.
2249	* @param pPatchMem Patch memory range.
2250	* @param cbPatchMem Size of the memory range.
2251	*/
2252	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2253	{
2254	VM_ASSERT_EMT(pVM);
2255	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2256	if (pVM->cCpus > 1)
2257	{
2258	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2259	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2260	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2261	AssertRC(rc);
2262	return rc;
2263	}
2264	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2265	}
2266
2267
2268	/**
2269	* Disable patching in a VT-x/AMD-V guest.
2270	*
2271	* @returns VBox status code.
2272	* @param pVM The cross context VM structure.
2273	* @param pPatchMem Patch memory range.
2274	* @param cbPatchMem Size of the memory range.
2275	*/
2276	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2277	{
2278	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2279	RT_NOREF2(pPatchMem, cbPatchMem);
2280
2281	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2282	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2283
2284	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2285	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2286	(void *)(uintptr_t)VMMGetCpuId(pVM));
2287	AssertRC(rc);
2288
2289	pVM->hm.s.pGuestPatchMem = 0;
2290	pVM->hm.s.pFreeGuestPatchMem = 0;
2291	pVM->hm.s.cbGuestPatchMem = 0;
2292	pVM->hm.s.fTprPatchingActive = false;
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/**
2298	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2299	*
2300	* @returns VBox strict status code.
2301	* @param pVM The cross context VM structure.
2302	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2303	* @param pvUser User specified CPU context.
2304	*
2305	*/
2306	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2307	{
2308	/*
2309	* Only execute the handler on the VCPU the original patch request was
2310	* issued. (The other CPU(s) might not yet have switched to protected
2311	* mode, nor have the correct memory context.)
2312	*/
2313	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2314	if (pVCpu->idCpu != idCpu)
2315	return VINF_SUCCESS;
2316
2317	/*
2318	* We're racing other VCPUs here, so don't try patch the instruction twice
2319	* and make sure there is still room for our patch record.
2320	*/
2321	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2322	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2323	if (pPatch)
2324	{
2325	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2326	return VINF_SUCCESS;
2327	}
2328	uint32_t const idx = pVM->hm.s.cPatches;
2329	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2330	{
2331	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2332	return VINF_SUCCESS;
2333	}
2334	pPatch = &pVM->hm.s.aPatches[idx];
2335
2336	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2337
2338	/*
2339	* Disassembler the instruction and get cracking.
2340	*/
2341	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2342	DISSTATE Dis;
2343	uint32_t cbOp;
2344	int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2345	AssertRC(rc);
2346	if ( rc == VINF_SUCCESS
2347	&& Dis.pCurInstr->uOpcode == OP_MOV
2348	&& cbOp >= 3)
2349	{
2350	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2351
2352	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2353	AssertRC(rc);
2354
2355	pPatch->cbOp = cbOp;
2356
2357	if (Dis.aParams[0].fUse == DISUSE_DISPLACEMENT32)
2358	{
2359	/* write. */
2360	if (Dis.aParams[1].fUse == DISUSE_REG_GEN32)
2361	{
2362	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2363	pPatch->uSrcOperand = Dis.aParams[1].x86.Base.idxGenReg;
2364	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.aParams[1].x86.Base.idxGenReg));
2365	}
2366	else
2367	{
2368	Assert(Dis.aParams[1].fUse == DISUSE_IMMEDIATE32);
2369	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2370	pPatch->uSrcOperand = Dis.aParams[1].uValue;
2371	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.aParams[1].uValue));
2372	}
2373	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2374	AssertRC(rc);
2375
2376	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2377	pPatch->cbNewOp = sizeof(s_abVMMCall);
2378	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2379	}
2380	else
2381	{
2382	/*
2383	* TPR Read.
2384	*
2385	* Found:
2386	* mov eax, dword [fffe0080] (5 bytes)
2387	* Check if next instruction is:
2388	* shr eax, 4
2389	*/
2390	Assert(Dis.aParams[0].fUse == DISUSE_REG_GEN32);
2391
2392	uint8_t const idxMmioReg = Dis.aParams[0].x86.Base.idxGenReg;
2393	uint8_t const cbOpMmio = cbOp;
2394	uint64_t const uSavedRip = pCtx->rip;
2395
2396	pCtx->rip += cbOp;
2397	rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2398	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2399	pCtx->rip = uSavedRip;
2400
2401	if ( rc == VINF_SUCCESS
2402	&& Dis.pCurInstr->uOpcode == OP_SHR
2403	&& Dis.aParams[0].fUse == DISUSE_REG_GEN32
2404	&& Dis.aParams[0].x86.Base.idxGenReg == idxMmioReg
2405	&& Dis.aParams[1].fUse == DISUSE_IMMEDIATE8
2406	&& Dis.aParams[1].uValue == 4
2407	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2408	{
2409	uint8_t abInstr[15];
2410
2411	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2412	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2413	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2414	AssertRC(rc);
2415
2416	pPatch->cbOp = cbOpMmio + cbOp;
2417
2418	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2419	abInstr[0] = 0xf0;
2420	abInstr[1] = 0x0f;
2421	abInstr[2] = 0x20;
2422	abInstr[3] = 0xc0 \| Dis.aParams[0].x86.Base.idxGenReg;
2423	for (unsigned i = 4; i < pPatch->cbOp; i++)
2424	abInstr[i] = 0x90; /* nop */
2425
2426	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2427	AssertRC(rc);
2428
2429	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2430	pPatch->cbNewOp = pPatch->cbOp;
2431	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2432
2433	Log(("Acceptable read/shr candidate!\n"));
2434	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2435	}
2436	else
2437	{
2438	pPatch->enmType = HMTPRINSTR_READ;
2439	pPatch->uDstOperand = idxMmioReg;
2440
2441	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2442	AssertRC(rc);
2443
2444	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2445	pPatch->cbNewOp = sizeof(s_abVMMCall);
2446	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2447	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2448	}
2449	}
2450
2451	pPatch->Core.Key = pCtx->eip;
2452	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2453	AssertRC(rc);
2454
2455	pVM->hm.s.cPatches++;
2456	return VINF_SUCCESS;
2457	}
2458
2459	/*
2460	* Save invalid patch, so we will not try again.
2461	*/
2462	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2463	pPatch->Core.Key = pCtx->eip;
2464	pPatch->enmType = HMTPRINSTR_INVALID;
2465	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2466	AssertRC(rc);
2467	pVM->hm.s.cPatches++;
2468	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2469	return VINF_SUCCESS;
2470	}
2471
2472
2473	/**
2474	* Callback to patch a TPR instruction (jump to generated code).
2475	*
2476	* @returns VBox strict status code.
2477	* @param pVM The cross context VM structure.
2478	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2479	* @param pvUser User specified CPU context.
2480	*
2481	*/
2482	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2483	{
2484	/*
2485	* Only execute the handler on the VCPU the original patch request was
2486	* issued. (The other CPU(s) might not yet have switched to protected
2487	* mode, nor have the correct memory context.)
2488	*/
2489	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2490	if (pVCpu->idCpu != idCpu)
2491	return VINF_SUCCESS;
2492
2493	/*
2494	* We're racing other VCPUs here, so don't try patch the instruction twice
2495	* and make sure there is still room for our patch record.
2496	*/
2497	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2498	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2499	if (pPatch)
2500	{
2501	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2502	return VINF_SUCCESS;
2503	}
2504	uint32_t const idx = pVM->hm.s.cPatches;
2505	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2506	{
2507	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2508	return VINF_SUCCESS;
2509	}
2510	pPatch = &pVM->hm.s.aPatches[idx];
2511
2512	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2513	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2514
2515	/*
2516	* Disassemble the instruction and get cracking.
2517	*/
2518	DISSTATE Dis;
2519	uint32_t cbOp;
2520	int rc = EMInterpretDisasCurrent(pVCpu, &Dis, &cbOp);
2521	AssertRC(rc);
2522	if ( rc == VINF_SUCCESS
2523	&& Dis.pCurInstr->uOpcode == OP_MOV
2524	&& cbOp >= 5)
2525	{
2526	uint8_t aPatch[64];
2527	uint32_t off = 0;
2528
2529	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2530	AssertRC(rc);
2531
2532	pPatch->cbOp = cbOp;
2533	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2534
2535	if (Dis.aParams[0].fUse == DISUSE_DISPLACEMENT32)
2536	{
2537	/*
2538	* TPR write:
2539	*
2540	* push ECX [51]
2541	* push EDX [52]
2542	* push EAX [50]
2543	* xor EDX,EDX [31 D2]
2544	* mov EAX,EAX [89 C0]
2545	* or
2546	* mov EAX,0000000CCh [B8 CC 00 00 00]
2547	* mov ECX,0C0000082h [B9 82 00 00 C0]
2548	* wrmsr [0F 30]
2549	* pop EAX [58]
2550	* pop EDX [5A]
2551	* pop ECX [59]
2552	* jmp return_address [E9 return_address]
2553	*/
2554	bool fUsesEax = (Dis.aParams[1].fUse == DISUSE_REG_GEN32 && Dis.aParams[1].x86.Base.idxGenReg == DISGREG_EAX);
2555
2556	aPatch[off++] = 0x51; /* push ecx */
2557	aPatch[off++] = 0x52; /* push edx */
2558	if (!fUsesEax)
2559	aPatch[off++] = 0x50; /* push eax */
2560	aPatch[off++] = 0x31; /* xor edx, edx */
2561	aPatch[off++] = 0xd2;
2562	if (Dis.aParams[1].fUse == DISUSE_REG_GEN32)
2563	{
2564	if (!fUsesEax)
2565	{
2566	aPatch[off++] = 0x89; /* mov eax, src_reg */
2567	aPatch[off++] = MAKE_MODRM(3, Dis.aParams[1].x86.Base.idxGenReg, DISGREG_EAX);
2568	}
2569	}
2570	else
2571	{
2572	Assert(Dis.aParams[1].fUse == DISUSE_IMMEDIATE32);
2573	aPatch[off++] = 0xb8; /* mov eax, immediate */
2574	(uint32_t )&aPatch[off] = Dis.aParams[1].uValue;
2575	off += sizeof(uint32_t);
2576	}
2577	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2578	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2579	off += sizeof(uint32_t);
2580
2581	aPatch[off++] = 0x0f; /* wrmsr */
2582	aPatch[off++] = 0x30;
2583	if (!fUsesEax)
2584	aPatch[off++] = 0x58; /* pop eax */
2585	aPatch[off++] = 0x5a; /* pop edx */
2586	aPatch[off++] = 0x59; /* pop ecx */
2587	}
2588	else
2589	{
2590	/*
2591	* TPR read:
2592	*
2593	* push ECX [51]
2594	* push EDX [52]
2595	* push EAX [50]
2596	* mov ECX,0C0000082h [B9 82 00 00 C0]
2597	* rdmsr [0F 32]
2598	* mov EAX,EAX [89 C0]
2599	* pop EAX [58]
2600	* pop EDX [5A]
2601	* pop ECX [59]
2602	* jmp return_address [E9 return_address]
2603	*/
2604	Assert(Dis.aParams[0].fUse == DISUSE_REG_GEN32);
2605
2606	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_ECX)
2607	aPatch[off++] = 0x51; /* push ecx */
2608	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_EDX )
2609	aPatch[off++] = 0x52; /* push edx */
2610	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_EAX)
2611	aPatch[off++] = 0x50; /* push eax */
2612
2613	aPatch[off++] = 0x31; /* xor edx, edx */
2614	aPatch[off++] = 0xd2;
2615
2616	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2617	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2618	off += sizeof(uint32_t);
2619
2620	aPatch[off++] = 0x0f; /* rdmsr */
2621	aPatch[off++] = 0x32;
2622
2623	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_EAX)
2624	{
2625	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2626	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.aParams[0].x86.Base.idxGenReg);
2627	}
2628
2629	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_EAX)
2630	aPatch[off++] = 0x58; /* pop eax */
2631	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_EDX )
2632	aPatch[off++] = 0x5a; /* pop edx */
2633	if (Dis.aParams[0].x86.Base.idxGenReg != DISGREG_ECX)
2634	aPatch[off++] = 0x59; /* pop ecx */
2635	}
2636	aPatch[off++] = 0xe9; /* jmp return_address */
2637	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2638	off += sizeof(RTRCUINTPTR);
2639
2640	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2641	{
2642	/* Write new code to the patch buffer. */
2643	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2644	AssertRC(rc);
2645
2646	#ifdef LOG_ENABLED
2647	uint32_t cbCurInstr;
2648	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2649	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2650	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2651	{
2652	char szOutput[256];
2653	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2654	szOutput, sizeof(szOutput), &cbCurInstr);
2655	if (RT_SUCCESS(rc))
2656	Log(("Patch instr %s\n", szOutput));
2657	else
2658	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2659	}
2660	#endif
2661
2662	pPatch->aNewOpcode[0] = 0xE9;
2663	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2664
2665	/* Overwrite the TPR instruction with a jump. */
2666	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2667	AssertRC(rc);
2668
2669	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2670
2671	pVM->hm.s.pFreeGuestPatchMem += off;
2672	pPatch->cbNewOp = 5;
2673
2674	pPatch->Core.Key = pCtx->eip;
2675	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2676	AssertRC(rc);
2677
2678	pVM->hm.s.cPatches++;
2679	pVM->hm.s.fTprPatchingActive = true;
2680	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2681	return VINF_SUCCESS;
2682	}
2683
2684	Log(("Ran out of space in our patch buffer!\n"));
2685	}
2686	else
2687	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2688
2689
2690	/*
2691	* Save invalid patch, so we will not try again.
2692	*/
2693	pPatch = &pVM->hm.s.aPatches[idx];
2694	pPatch->Core.Key = pCtx->eip;
2695	pPatch->enmType = HMTPRINSTR_INVALID;
2696	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2697	AssertRC(rc);
2698	pVM->hm.s.cPatches++;
2699	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2700	return VINF_SUCCESS;
2701	}
2702
2703
2704	/**
2705	* Attempt to patch TPR mmio instructions.
2706	*
2707	* @returns VBox status code.
2708	* @param pVM The cross context VM structure.
2709	* @param pVCpu The cross context virtual CPU structure.
2710	*/
2711	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2712	{
2713	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2714	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2715	(void *)(uintptr_t)pVCpu->idCpu);
2716	AssertRC(rc);
2717	return rc;
2718	}
2719
2720
2721	/**
2722	* Checks if we need to reschedule due to VMM device heap changes.
2723	*
2724	* @returns true if a reschedule is required, otherwise false.
2725	* @param pVM The cross context VM structure.
2726	* @param pCtx VM execution context.
2727	*/
2728	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2729	{
2730	/*
2731	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2732	* when the unrestricted guest execution feature is missing (VT-x only).
2733	*/
2734	if ( pVM->hm.s.vmx.fEnabled
2735	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2736	&& CPUMIsGuestInRealModeEx(pCtx)
2737	&& !PDMVmmDevHeapIsEnabled(pVM))
2738	return true;
2739
2740	return false;
2741	}
2742
2743
2744	/**
2745	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2746	* event settings changes.
2747	*
2748	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2749	* function is just updating the VM globals.
2750	*
2751	* @param pVM The VM cross context VM structure.
2752	* @thread EMT(0)
2753	*/
2754	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2755	{
2756	/* Interrupts. */
2757	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2758	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2759
2760	/* CPU Exceptions. */
2761	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2762	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2763	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2764	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2765
2766	/* Common VM exits. */
2767	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2768	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2769	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2770	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2771
2772	/* Vendor specific VM exits. */
2773	if (HMR3IsVmxEnabled(pVM->pUVM))
2774	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2775	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2776	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2777	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2778	else
2779	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2780	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2781	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2782	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2783
2784	/* Done. */
2785	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2786	}
2787
2788
2789	/**
2790	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2791	*
2792	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2793	* per CPU settings.
2794	*
2795	* @param pVM The VM cross context VM structure.
2796	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2797	*/
2798	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2799	{
2800	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2801	}
2802
2803
2804	#if 0 /* evil */
2805	/**
2806	* Checks if we are currently using hardware acceleration.
2807	*
2808	* @returns true if hardware acceleration is being used, otherwise false.
2809	* @param pVCpu The cross context virtual CPU structure.
2810	*/
2811	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2812	{
2813	return pVCpu->hm.s.fActive;
2814	}
2815	#endif
2816
2817
2818	/**
2819	* External interface for querying whether hardware acceleration is enabled.
2820	*
2821	* @returns true if VT-x or AMD-V is being used, otherwise false.
2822	* @param pUVM The user mode VM handle.
2823	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2824	*/
2825	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2826	{
2827	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2828	PVM pVM = pUVM->pVM;
2829	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2830	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2831	}
2832
2833
2834	/**
2835	* External interface for querying whether VT-x is being used.
2836	*
2837	* @returns true if VT-x is being used, otherwise false.
2838	* @param pUVM The user mode VM handle.
2839	* @sa HMR3IsSvmEnabled, HMIsEnabled
2840	*/
2841	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2842	{
2843	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2844	PVM pVM = pUVM->pVM;
2845	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2846	return pVM->hm.s.vmx.fEnabled
2847	&& pVM->hm.s.vmx.fSupported
2848	&& pVM->fHMEnabled;
2849	}
2850
2851
2852	/**
2853	* External interface for querying whether AMD-V is being used.
2854	*
2855	* @returns true if VT-x is being used, otherwise false.
2856	* @param pUVM The user mode VM handle.
2857	* @sa HMR3IsVmxEnabled, HMIsEnabled
2858	*/
2859	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2860	{
2861	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2862	PVM pVM = pUVM->pVM;
2863	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2864	return pVM->hm.s.svm.fEnabled
2865	&& pVM->hm.s.svm.fSupported
2866	&& pVM->fHMEnabled;
2867	}
2868
2869
2870	/**
2871	* Checks if we are currently using nested paging.
2872	*
2873	* @returns true if nested paging is being used, otherwise false.
2874	* @param pUVM The user mode VM handle.
2875	*/
2876	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2877	{
2878	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2879	PVM pVM = pUVM->pVM;
2880	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2881	return pVM->hm.s.fNestedPagingCfg;
2882	}
2883
2884
2885	/**
2886	* Checks if virtualized APIC registers are enabled.
2887	*
2888	* When enabled this feature allows the hardware to access most of the
2889	* APIC registers in the virtual-APIC page without causing VM-exits. See
2890	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2891	*
2892	* @returns true if virtualized APIC registers is enabled, otherwise
2893	* false.
2894	* @param pUVM The user mode VM handle.
2895	*/
2896	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2897	{
2898	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2899	PVM pVM = pUVM->pVM;
2900	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2901	return pVM->hm.s.fVirtApicRegs;
2902	}
2903
2904
2905	/**
2906	* Checks if APIC posted-interrupt processing is enabled.
2907	*
2908	* This returns whether we can deliver interrupts to the guest without
2909	* leaving guest-context by updating APIC state from host-context.
2910	*
2911	* @returns true if APIC posted-interrupt processing is enabled,
2912	* otherwise false.
2913	* @param pUVM The user mode VM handle.
2914	*/
2915	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2916	{
2917	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2918	PVM pVM = pUVM->pVM;
2919	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2920	return pVM->hm.s.fPostedIntrs;
2921	}
2922
2923
2924	/**
2925	* Checks if we are currently using VPID in VT-x mode.
2926	*
2927	* @returns true if VPID is being used, otherwise false.
2928	* @param pUVM The user mode VM handle.
2929	*/
2930	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2931	{
2932	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2933	PVM pVM = pUVM->pVM;
2934	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2935	return pVM->hm.s.ForR3.vmx.fVpid;
2936	}
2937
2938
2939	/**
2940	* Checks if we are currently using VT-x unrestricted execution,
2941	* aka UX.
2942	*
2943	* @returns true if UX is being used, otherwise false.
2944	* @param pUVM The user mode VM handle.
2945	*/
2946	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2947	{
2948	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2949	PVM pVM = pUVM->pVM;
2950	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2951	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2952	\|\| pVM->hm.s.svm.fSupported;
2953	}
2954
2955
2956	/**
2957	* Checks if the VMX-preemption timer is being used.
2958	*
2959	* @returns true if the VMX-preemption timer is being used, otherwise false.
2960	* @param pVM The cross context VM structure.
2961	*/
2962	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2963	{
2964	return HMIsEnabled(pVM)
2965	&& pVM->hm.s.vmx.fEnabled
2966	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2967	}
2968
2969
2970	#ifdef TODO_9217_VMCSINFO
2971	/**
2972	* Helper for HMR3CheckError to log VMCS controls to the release log.
2973	*
2974	* @param idCpu The Virtual CPU ID.
2975	* @param pVmcsInfo The VMCS info. object.
2976	*/
2977	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2978	{
2979	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2980	{
2981	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2987	}
2988	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2989	{
2990	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2999	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
3000	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
3007	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
3008	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
3009	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
3010	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
3011	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
3012	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
3013	}
3014	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
3015	{
3016	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
3017	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
3018	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
3019	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
3020	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
3021	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
3022	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
3023	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
3024	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
3025	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
3026	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
3027	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
3028	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
3029	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
3030	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
3031	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
3032	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
3033	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
3034	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
3035	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
3036	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
3037	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
3038	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PASID_TRANSLATE );
3039	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
3040	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
3041	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
3042	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
3043	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
3044	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PCONFIG );
3045	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
3046	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_BUS_LOCK_DETECT );
3047	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INSTR_TIMEOUT );
3048	}
3049	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
3050	{
3051	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
3052	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3053	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3054	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3055	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3056	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3057	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3058	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3059	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3060	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3061	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3062	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_UINV );
3063	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
3064	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_LBR_CTL_MSR );
3065	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
3066	}
3067	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3068	{
3069	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3070	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3071	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3072	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3073	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3074	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3075	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3076	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3077	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3078	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3079	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3080	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3081	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3082	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_LBR_CTL_MSR );
3083	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_UINV );
3084	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
3085	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
3086	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PERF_MSR );
3087	}
3088	}
3089	#endif
3090
3091
3092	/**
3093	* Check fatal VT-x/AMD-V error and produce some meaningful
3094	* log release message.
3095	*
3096	* @param pVM The cross context VM structure.
3097	* @param iStatusCode VBox status code.
3098	*/
3099	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3100	{
3101	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3102	{
3103	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3104	* might be getting inaccurate values for non-guru'ing EMTs. */
3105	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3106	#ifdef TODO_9217_VMCSINFO
3107	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3108	#endif
3109	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3110	switch (iStatusCode)
3111	{
3112	case VERR_VMX_INVALID_VMCS_PTR:
3113	{
3114	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3115	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3116	#ifdef TODO_9217_VMCSINFO
3117	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3118	pVmcsInfo->HCPhysVmcs));
3119	#endif
3120	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3121	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3122	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3123	break;
3124	}
3125
3126	case VERR_VMX_UNABLE_TO_START_VM:
3127	{
3128	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3129	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3130	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3131	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3132
3133	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3134	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3135	{
3136	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3137	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3138	}
3139	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3140	{
3141	#ifdef TODO_9217_VMCSINFO
3142	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3143	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3144	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3145	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3146	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3147	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3148	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3149	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3150	#endif
3151	}
3152	/** @todo Log VM-entry event injection control fields
3153	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3154	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3155	break;
3156	}
3157
3158	case VERR_VMX_INVALID_GUEST_STATE:
3159	{
3160	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3161	LogRel(("HM: CPU[%u] HM error = %#RX32 (%RU32)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
3162	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3163	#ifdef TODO_9217_VMCSINFO
3164	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3165	#endif
3166	break;
3167	}
3168
3169	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3170	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3171	case VERR_VMX_INVALID_VMXON_PTR:
3172	case VERR_VMX_UNEXPECTED_EXIT:
3173	case VERR_VMX_INVALID_VMCS_FIELD:
3174	case VERR_SVM_UNKNOWN_EXIT:
3175	case VERR_SVM_UNEXPECTED_EXIT:
3176	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3177	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3178	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3179	break;
3180	}
3181	}
3182
3183	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3184	{
3185	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3186	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3187	}
3188	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3189	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3190	}
3191
3192
3193	/**
3194	* Execute state save operation.
3195	*
3196	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3197	* is because we always save the VM state from ring-3 and thus most HM state
3198	* will be re-synced dynamically at runtime and don't need to be part of the VM
3199	* saved state.
3200	*
3201	* @returns VBox status code.
3202	* @param pVM The cross context VM structure.
3203	* @param pSSM SSM operation handle.
3204	*/
3205	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3206	{
3207	Log(("hmR3Save:\n"));
3208
3209	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3210	{
3211	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3212	Assert(!pVCpu->hm.s.Event.fPending);
3213	if (pVM->cpum.ro.GuestFeatures.fSvm)
3214	{
3215	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3216	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3217	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3218	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3219	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3220	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3221	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3222	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3223	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3224	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3225	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3226	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3227	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3228	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3229	}
3230	}
3231
3232	/* Save the guest patch data. */
3233	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3234	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3235	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3236
3237	/* Store all the guest patch records too. */
3238	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3239	if (RT_FAILURE(rc))
3240	return rc;
3241
3242	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3243	{
3244	AssertCompileSize(HMTPRINSTR, 4);
3245	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3246	SSMR3PutU32(pSSM, pPatch->Core.Key);
3247	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3248	SSMR3PutU32(pSSM, pPatch->cbOp);
3249	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3250	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3251	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3252	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3253	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3254	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3255	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3256	if (RT_FAILURE(rc))
3257	return rc;
3258	}
3259
3260	return VINF_SUCCESS;
3261	}
3262
3263
3264	/**
3265	* Execute state load operation.
3266	*
3267	* @returns VBox status code.
3268	* @param pVM The cross context VM structure.
3269	* @param pSSM SSM operation handle.
3270	* @param uVersion Data layout version.
3271	* @param uPass The data pass.
3272	*/
3273	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3274	{
3275	int rc;
3276
3277	LogFlowFunc(("uVersion=%u\n", uVersion));
3278	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3279
3280	/*
3281	* Validate version.
3282	*/
3283	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3284	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3285	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3286	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3287	{
3288	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3289	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3290	}
3291
3292	/*
3293	* Load per-VCPU state.
3294	*/
3295	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3296	{
3297	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3298	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3299	{
3300	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3301	if (pVM->cpum.ro.GuestFeatures.fSvm)
3302	{
3303	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3304	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3305	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3306	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3307	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3308	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3309	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3310	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3311	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3312	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3313	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3314	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3315	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3316	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3317	AssertRCReturn(rc, rc);
3318	}
3319	}
3320	else
3321	{
3322	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3323	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3324	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3325	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3326
3327	/* VMX fWasInRealMode related data. */
3328	uint32_t uDummy;
3329	SSMR3GetU32(pSSM, &uDummy);
3330	SSMR3GetU32(pSSM, &uDummy);
3331	rc = SSMR3GetU32(pSSM, &uDummy);
3332	AssertRCReturn(rc, rc);
3333	}
3334	}
3335
3336	/*
3337	* Load TPR patching data.
3338	*/
3339	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3340	{
3341	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3342	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3343	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3344
3345	/* Fetch all TPR patch records. */
3346	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3347	AssertRCReturn(rc, rc);
3348	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3349	{
3350	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3351	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3352	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3353	SSMR3GetU32(pSSM, &pPatch->cbOp);
3354	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3355	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3356	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3357
3358	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3359	pVM->hm.s.fTprPatchingActive = true;
3360	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3361
3362	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3363	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3364	SSMR3GetU32(pSSM, &pPatch->cFaults);
3365	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3366	AssertRCReturn(rc, rc);
3367
3368	LogFlow(("hmR3Load: patch %d\n", i));
3369	LogFlow(("Key = %x\n", pPatch->Core.Key));
3370	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3371	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3372	LogFlow(("type = %d\n", pPatch->enmType));
3373	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3374	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3375	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3376	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3377
3378	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3379	AssertRCReturn(rc, rc);
3380	}
3381	}
3382
3383	return VINF_SUCCESS;
3384	}
3385
3386
3387	/**
3388	* Displays HM info.
3389	*
3390	* @param pVM The cross context VM structure.
3391	* @param pHlp The info helper functions.
3392	* @param pszArgs Arguments, ignored.
3393	*/
3394	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3395	{
3396	NOREF(pszArgs);
3397	PVMCPU pVCpu = VMMGetCpu(pVM);
3398	if (!pVCpu)
3399	pVCpu = pVM->apCpusR3[0];
3400
3401	if (HMIsEnabled(pVM))
3402	{
3403	if (pVM->hm.s.vmx.fSupported)
3404	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3405	else
3406	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3407	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3408	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3409	if (pVM->hm.s.vmx.fSupported)
3410	{
3411	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3412	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3413	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3414
3415	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3416	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3417	if (fRealOnV86Active)
3418	{
3419	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3420	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3421	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3422	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3423	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3424	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3425	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3426	}
3427	}
3428	}
3429	else
3430	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3431	}
3432
3433
3434	/**
3435	* Displays the HM Last-Branch-Record info. for the guest.
3436	*
3437	* @param pVM The cross context VM structure.
3438	* @param pHlp The info helper functions.
3439	* @param pszArgs Arguments, ignored.
3440	*/
3441	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3442	{
3443	NOREF(pszArgs);
3444	PVMCPU pVCpu = VMMGetCpu(pVM);
3445	if (!pVCpu)
3446	pVCpu = pVM->apCpusR3[0];
3447
3448	if (!HMIsEnabled(pVM))
3449	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3450	else if (HMIsVmxActive(pVM))
3451	{
3452	if (pVM->hm.s.vmx.fLbrCfg)
3453	{
3454	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3455	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3456
3457	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3458	* 0xf should cover everything we support thus far. Fix if necessary
3459	* later. */
3460	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3461	if (idxTopOfStack > cLbrStack)
3462	{
3463	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3464	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3465	return;
3466	}
3467
3468	/*
3469	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3470	*/
3471	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3472	uint32_t idxCurrent = idxTopOfStack;
3473	Assert(idxTopOfStack < cLbrStack);
3474	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3475	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3476	for (;;)
3477	{
3478	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3479	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3480	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3481	else
3482	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3483
3484	idxCurrent = (idxCurrent - 1) % cLbrStack;
3485	if (idxCurrent == idxTopOfStack)
3486	break;
3487	}
3488	}
3489	else
3490	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3491	}
3492	else
3493	{
3494	Assert(HMIsSvmActive(pVM));
3495	/** @todo SVM: LBRs (get them from VMCB if possible). */
3496	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3497	}
3498	}
3499
3500
3501	/**
3502	* Displays the HM pending event.
3503	*
3504	* @param pVM The cross context VM structure.
3505	* @param pHlp The info helper functions.
3506	* @param pszArgs Arguments, ignored.
3507	*/
3508	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3509	{
3510	NOREF(pszArgs);
3511	PVMCPU pVCpu = VMMGetCpu(pVM);
3512	if (!pVCpu)
3513	pVCpu = pVM->apCpusR3[0];
3514
3515	if (HMIsEnabled(pVM))
3516	{
3517	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3518	if (pVCpu->hm.s.Event.fPending)
3519	{
3520	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3521	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3522	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3523	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3524	}
3525	}
3526	else
3527	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3528	}
3529
3530
3531	/**
3532	* Displays the SVM nested-guest VMCB cache.
3533	*
3534	* @param pVM The cross context VM structure.
3535	* @param pHlp The info helper functions.
3536	* @param pszArgs Arguments, ignored.
3537	*/
3538	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3539	{
3540	NOREF(pszArgs);
3541	PVMCPU pVCpu = VMMGetCpu(pVM);
3542	if (!pVCpu)
3543	pVCpu = pVM->apCpusR3[0];
3544
3545	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3546	if ( fSvmEnabled
3547	&& pVM->cpum.ro.GuestFeatures.fSvm)
3548	{
3549	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3550	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3551	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3552	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3553	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3554	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3555	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3556	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3557	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3558	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3559	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3560	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3561	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3562	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3563	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3564	}
3565	else
3566	{
3567	if (!fSvmEnabled)
3568	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3569	else
3570	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3571	}
3572	}
3573

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp

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