VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 43667

Last change on this file since 43667 was 42420, checked in by vboxsync, 12 years ago

Eliminating CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID and CPUMAreHiddenSelRegsValid. Addressing some LDTR and TR things (saved stated, transition to REM).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 25.4 KB
Line 
1/* $Id: DBGFDisas.cpp 42420 2012-07-26 17:33:01Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_DBGF
22#include <VBox/vmm/dbgf.h>
23#include <VBox/vmm/selm.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/cpum.h>
27#include "DBGFInternal.h"
28#include <VBox/dis.h>
29#include <VBox/err.h>
30#include <VBox/param.h>
31#include <VBox/vmm/vm.h>
32#include "internal/pgm.h"
33
34#include <VBox/log.h>
35#include <iprt/assert.h>
36#include <iprt/string.h>
37#include <iprt/alloca.h>
38#include <iprt/ctype.h>
39
40
41/*******************************************************************************
42* Structures and Typedefs *
43*******************************************************************************/
44/**
45 * Structure used when disassembling and instructions in DBGF.
46 * This is used so the reader function can get the stuff it needs.
47 */
48typedef struct
49{
50 /** The core structure. */
51 DISCPUSTATE Cpu;
52 /** Pointer to the VM. */
53 PVM pVM;
54 /** Pointer to the VMCPU. */
55 PVMCPU pVCpu;
56 /** The address space for resolving symbol. */
57 RTDBGAS hAs;
58 /** Pointer to the first byte in the segment. */
59 RTGCUINTPTR GCPtrSegBase;
60 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
61 RTGCUINTPTR GCPtrSegEnd;
62 /** The size of the segment minus 1. */
63 RTGCUINTPTR cbSegLimit;
64 /** The guest paging mode. */
65 PGMMODE enmMode;
66 /** Pointer to the current page - R3 Ptr. */
67 void const *pvPageR3;
68 /** Pointer to the current page - GC Ptr. */
69 RTGCPTR GCPtrPage;
70 /** Pointer to the next instruction (relative to GCPtrSegBase). */
71 RTGCUINTPTR GCPtrNext;
72 /** The lock information that PGMPhysReleasePageMappingLock needs. */
73 PGMPAGEMAPLOCK PageMapLock;
74 /** Whether the PageMapLock is valid or not. */
75 bool fLocked;
76 /** 64 bits mode or not. */
77 bool f64Bits;
78} DBGFDISASSTATE, *PDBGFDISASSTATE;
79
80
81/*******************************************************************************
82* Internal Functions *
83*******************************************************************************/
84static FNDISREADBYTES dbgfR3DisasInstrRead;
85
86
87
88/**
89 * Calls the disassembler with the proper reader functions and such for disa
90 *
91 * @returns VBox status code.
92 * @param pVM Pointer to the VM.
93 * @param pVCpu Pointer to the VMCPU.
94 * @param pSelInfo The selector info.
95 * @param enmMode The guest paging mode.
96 * @param fFlags DBGF_DISAS_FLAGS_XXX.
97 * @param GCPtr The GC pointer (selector offset).
98 * @param pState The disas CPU state.
99 */
100static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
101 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
102{
103 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
104 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
105 pState->cbSegLimit = pSelInfo->cbLimit;
106 pState->enmMode = enmMode;
107 pState->GCPtrPage = 0;
108 pState->pvPageR3 = NULL;
109 pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas*. */
110 ? DBGF_AS_RC_AND_GC_GLOBAL
111 : DBGF_AS_GLOBAL;
112 pState->pVM = pVM;
113 pState->pVCpu = pVCpu;
114 pState->fLocked = false;
115 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
116
117 DISCPUMODE enmCpuMode;
118 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
119 {
120 default:
121 AssertFailed();
122 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
123 enmCpuMode = pState->f64Bits
124 ? DISCPUMODE_64BIT
125 : pSelInfo->u.Raw.Gen.u1DefBig
126 ? DISCPUMODE_32BIT
127 : DISCPUMODE_16BIT;
128 break;
129 case DBGF_DISAS_FLAGS_16BIT_MODE:
130 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
131 enmCpuMode = DISCPUMODE_16BIT;
132 break;
133 case DBGF_DISAS_FLAGS_32BIT_MODE:
134 enmCpuMode = DISCPUMODE_32BIT;
135 break;
136 case DBGF_DISAS_FLAGS_64BIT_MODE:
137 enmCpuMode = DISCPUMODE_64BIT;
138 break;
139 }
140
141 uint32_t cbInstr;
142 int rc = DISInstrWithReader(GCPtr,
143 enmCpuMode,
144 dbgfR3DisasInstrRead,
145 &pState->Cpu,
146 &pState->Cpu,
147 &cbInstr);
148 if (RT_SUCCESS(rc))
149 {
150 pState->GCPtrNext = GCPtr + cbInstr;
151 return VINF_SUCCESS;
152 }
153
154 /* cleanup */
155 if (pState->fLocked)
156 {
157 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
158 pState->fLocked = false;
159 }
160 return rc;
161}
162
163
164#if 0
165/**
166 * Calls the disassembler for disassembling the next instruction.
167 *
168 * @returns VBox status code.
169 * @param pState The disas CPU state.
170 */
171static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
172{
173 uint32_t cbInstr;
174 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
175 if (RT_SUCCESS(rc))
176 {
177 pState->GCPtrNext = GCPtr + cbInstr;
178 return VINF_SUCCESS;
179 }
180 return rc;
181}
182#endif
183
184
185/**
186 * Done with the disassembler state, free associated resources.
187 *
188 * @param pState The disas CPU state ++.
189 */
190static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
191{
192 if (pState->fLocked)
193 {
194 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
195 pState->fLocked = false;
196 }
197}
198
199
200/**
201 * @callback_method_impl{FNDISREADBYTES}
202 *
203 * @remarks The source is relative to the base address indicated by
204 * DBGFDISASSTATE::GCPtrSegBase.
205 */
206static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
207{
208 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
209 for (;;)
210 {
211 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
212
213 /*
214 * Need to update the page translation?
215 */
216 if ( !pState->pvPageR3
217 || (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
218 {
219 int rc = VINF_SUCCESS;
220
221 /* translate the address */
222 pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
223 if (MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
224 {
225 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
226 if (!pState->pvPageR3)
227 rc = VERR_INVALID_POINTER;
228 }
229 else
230 {
231 if (pState->fLocked)
232 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
233
234 if (pState->enmMode <= PGMMODE_PROTECTED)
235 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
236 else
237 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
238 pState->fLocked = RT_SUCCESS_NP(rc);
239 }
240 if (RT_FAILURE(rc))
241 {
242 pState->pvPageR3 = NULL;
243 return rc;
244 }
245 }
246
247 /*
248 * Check the segment limit.
249 */
250 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
251 return VERR_OUT_OF_SELECTOR_BOUNDS;
252
253 /*
254 * Calc how much we can read, maxing out the read.
255 */
256 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
257 if (!pState->f64Bits)
258 {
259 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
260 if (cb > cbSeg && cbSeg)
261 cb = cbSeg;
262 }
263 if (cb > cbMaxRead)
264 cb = cbMaxRead;
265
266 /*
267 * Read and advance,
268 */
269 memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
270 offInstr += (uint8_t)cb;
271 if (cb >= cbMinRead)
272 {
273 pDis->cbCachedInstr = offInstr;
274 return VINF_SUCCESS;
275 }
276 cbMaxRead -= (uint8_t)cb;
277 cbMinRead -= (uint8_t)cb;
278 }
279}
280
281
282/**
283 * @copydoc FNDISGETSYMBOL
284 */
285static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
286{
287 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
288 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
289 DBGFADDRESS Addr;
290 RTDBGSYMBOL Sym;
291 RTGCINTPTR off;
292 int rc;
293
294 if ( DIS_FMT_SEL_IS_REG(u32Sel)
295 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
296 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
297 {
298 rc = DBGFR3AddrFromSelInfoOff(pState->pVM, &Addr, pSelInfo, uAddress);
299 if (RT_SUCCESS(rc))
300 rc = DBGFR3AsSymbolByAddr(pState->pVM, pState->hAs, &Addr, &off, &Sym, NULL /*phMod*/);
301 }
302 else
303 rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
304 if (RT_SUCCESS(rc))
305 {
306 size_t cchName = strlen(Sym.szName);
307 if (cchName >= cchBuf)
308 cchName = cchBuf - 1;
309 memcpy(pszBuf, Sym.szName, cchName);
310 pszBuf[cchName] = '\0';
311
312 *poff = off;
313 }
314
315 return rc;
316}
317
318
319/**
320 * Disassembles the one instruction according to the specified flags and
321 * address, internal worker executing on the EMT of the specified virtual CPU.
322 *
323 * @returns VBox status code.
324 * @param pVM Pointer to the VM.
325 * @param pVCpu Pointer to the VMCPU.
326 * @param Sel The code selector. This used to determine the 32/16 bit ness and
327 * calculation of the actual instruction address.
328 * @param pGCPtr Pointer to the variable holding the code address
329 * relative to the base of Sel.
330 * @param fFlags Flags controlling where to start and how to format.
331 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
332 * @param pszOutput Output buffer.
333 * @param cbOutput Size of the output buffer.
334 * @param pcbInstr Where to return the size of the instruction.
335 */
336static DECLCALLBACK(int)
337dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
338 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
339{
340 VMCPU_ASSERT_EMT(pVCpu);
341 RTGCPTR GCPtr = *pGCPtr;
342 int rc;
343
344 /*
345 * Get the Sel and GCPtr if fFlags requests that.
346 */
347 PCCPUMCTXCORE pCtxCore = NULL;
348 PCCPUMSELREG pSRegCS = NULL;
349 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
350 {
351 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
352 Sel = pCtxCore->cs.Sel;
353 pSRegCS = &pCtxCore->cs;
354 GCPtr = pCtxCore->rip;
355 }
356 else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
357 {
358 pCtxCore = CPUMGetHyperCtxCore(pVCpu);
359 Sel = pCtxCore->cs.Sel;
360 GCPtr = pCtxCore->rip;
361 }
362 /*
363 * Check if the selector matches the guest CS, use the hidden
364 * registers from that if they are valid. Saves time and effort.
365 */
366 else
367 {
368 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
369 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
370 pSRegCS = &pCtxCore->cs;
371 else
372 pCtxCore = NULL;
373 }
374
375 /*
376 * Read the selector info - assume no stale selectors and nasty stuff like that.
377 *
378 * Note! We CANNOT load invalid hidden selector registers since that would
379 * mean that log/debug statements or the debug will influence the
380 * guest state and make things behave differently.
381 */
382 DBGFSELINFO SelInfo;
383 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
384 bool fRealModeAddress = false;
385
386 if ( pSRegCS
387 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
388 {
389 SelInfo.Sel = Sel;
390 SelInfo.SelGate = 0;
391 SelInfo.GCPtrBase = pSRegCS->u64Base;
392 SelInfo.cbLimit = pSRegCS->u32Limit;
393 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
394 ? DBGFSELINFO_FLAGS_LONG_MODE
395 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
396 ? DBGFSELINFO_FLAGS_PROT_MODE
397 : DBGFSELINFO_FLAGS_REAL_MODE;
398
399 SelInfo.u.Raw.au32[0] = 0;
400 SelInfo.u.Raw.au32[1] = 0;
401 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
402 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
403 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
404 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
405 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
406 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
407 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
408 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
409 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
410 }
411 else if (Sel == DBGF_SEL_FLAT)
412 {
413 SelInfo.Sel = Sel;
414 SelInfo.SelGate = 0;
415 SelInfo.GCPtrBase = 0;
416 SelInfo.cbLimit = ~0;
417 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
418 ? DBGFSELINFO_FLAGS_LONG_MODE
419 : enmMode != PGMMODE_REAL
420 ? DBGFSELINFO_FLAGS_PROT_MODE
421 : DBGFSELINFO_FLAGS_REAL_MODE;
422 SelInfo.u.Raw.au32[0] = 0;
423 SelInfo.u.Raw.au32[1] = 0;
424 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
425 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
426
427 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
428 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
429 {
430 /* Assume the current CS defines the execution mode. */
431 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
432 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
433 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
434 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
435 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
436 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
437 }
438 else
439 {
440 pSRegCS = NULL;
441 SelInfo.u.Raw.Gen.u1Present = 1;
442 SelInfo.u.Raw.Gen.u1Granularity = 1;
443 SelInfo.u.Raw.Gen.u1DefBig = 1;
444 SelInfo.u.Raw.Gen.u1DescType = 1;
445 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
446 }
447 }
448 else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
449 && ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
450 || enmMode == PGMMODE_REAL
451 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
452 )
453 )
454 { /* V86 mode or real mode - real mode addressing */
455 SelInfo.Sel = Sel;
456 SelInfo.SelGate = 0;
457 SelInfo.GCPtrBase = Sel * 16;
458 SelInfo.cbLimit = ~0;
459 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
460 SelInfo.u.Raw.au32[0] = 0;
461 SelInfo.u.Raw.au32[1] = 0;
462 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
463 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
464 SelInfo.u.Raw.Gen.u1Present = 1;
465 SelInfo.u.Raw.Gen.u1Granularity = 1;
466 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
467 SelInfo.u.Raw.Gen.u1DescType = 1;
468 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
469 fRealModeAddress = true;
470 }
471 else
472 {
473 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
474 if (RT_FAILURE(rc))
475 {
476 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
477 return rc;
478 }
479 }
480
481 /*
482 * Disassemble it.
483 */
484 DBGFDISASSTATE State;
485 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
486 if (RT_FAILURE(rc))
487 {
488 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
489 return rc;
490 }
491
492 /*
493 * Format it.
494 */
495 char szBuf[512];
496 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
497 DIS_FMT_FLAGS_RELATIVE_BRANCH,
498 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
499 &SelInfo);
500
501 /*
502 * Print it to the user specified buffer.
503 */
504 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
505 {
506 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
507 RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
508 else if (fRealModeAddress)
509 RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
510 else if (Sel == DBGF_SEL_FLAT)
511 {
512 if (enmMode >= PGMMODE_AMD64)
513 RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
514 else
515 RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
516 }
517 else
518 {
519 if (enmMode >= PGMMODE_AMD64)
520 RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
521 else
522 RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
523 }
524 }
525 else
526 {
527 uint32_t cbInstr = State.Cpu.cbInstr;
528 uint8_t const *pabInstr = State.Cpu.abInstr;
529 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
530 RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
531 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
532 szBuf);
533 else if (fRealModeAddress)
534 RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
535 Sel, (unsigned)GCPtr,
536 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
537 szBuf);
538 else if (Sel == DBGF_SEL_FLAT)
539 {
540 if (enmMode >= PGMMODE_AMD64)
541 RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
542 GCPtr,
543 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
544 szBuf);
545 else
546 RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
547 (uint32_t)GCPtr,
548 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
549 szBuf);
550 }
551 else
552 {
553 if (enmMode >= PGMMODE_AMD64)
554 RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
555 Sel, GCPtr,
556 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
557 szBuf);
558 else
559 RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
560 Sel, (uint32_t)GCPtr,
561 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
562 szBuf);
563 }
564 }
565
566 if (pcbInstr)
567 *pcbInstr = State.Cpu.cbInstr;
568
569 dbgfR3DisasInstrDone(&State);
570 return VINF_SUCCESS;
571}
572
573
574/**
575 * Disassembles the one instruction according to the specified flags and address.
576 *
577 * @returns VBox status code.
578 * @param pVM Pointer to the VM.
579 * @param idCpu The ID of virtual CPU.
580 * @param Sel The code selector. This used to determine the 32/16 bit ness and
581 * calculation of the actual instruction address.
582 * @param GCPtr The code address relative to the base of Sel.
583 * @param fFlags Flags controlling where to start and how to format.
584 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
585 * @param pszOutput Output buffer. This will always be properly
586 * terminated if @a cbOutput is greater than zero.
587 * @param cbOutput Size of the output buffer.
588 * @param pcbInstr Where to return the size of the instruction.
589 *
590 * @remarks May have to switch to the EMT of the virtual CPU in order to do
591 * address conversion.
592 */
593VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
594 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
595{
596 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
597 *pszOutput = '\0';
598 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
599 AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID);
600 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
601 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
602
603 /*
604 * Optimize the common case where we're called on the EMT of idCpu since
605 * we're using this all the time when logging.
606 */
607 int rc;
608 PVMCPU pVCpu = VMMGetCpu(pVM);
609 if ( pVCpu
610 && pVCpu->idCpu == idCpu)
611 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
612 else
613 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
614 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
615 return rc;
616}
617
618
619/**
620 * Disassembles the current guest context instruction.
621 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
622 *
623 * @returns VBox status code.
624 * @param pVCpu Pointer to the VMCPU.
625 * @param pszOutput Output buffer. This will always be properly
626 * terminated if @a cbOutput is greater than zero.
627 * @param cbOutput Size of the output buffer.
628 */
629VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
630{
631 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
632 *pszOutput = '\0';
633 AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
634 return DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, 0, 0,
635 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
636 pszOutput, cbOutput, NULL);
637}
638
639
640/**
641 * Disassembles the current guest context instruction and writes it to the log.
642 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
643 *
644 * @returns VBox status code.
645 * @param pVCpu Pointer to the VMCPU.
646 * @param pszPrefix Short prefix string to the disassembly string. (optional)
647 */
648VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
649{
650 char szBuf[256];
651 szBuf[0] = '\0';
652 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
653 if (RT_FAILURE(rc))
654 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
655 if (pszPrefix && *pszPrefix)
656 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
657 else
658 RTLogPrintf("%s\n", szBuf);
659 return rc;
660}
661
662
663
664/**
665 * Disassembles the specified guest context instruction and writes it to the log.
666 * Addresses will be attempted resolved to symbols.
667 *
668 * @returns VBox status code.
669 * @param pVM Pointer to the VM.
670 * @param pVCpu Pointer to the VMCPU, defaults to CPU 0 if NULL.
671 * @param Sel The code selector. This used to determine the 32/16 bit-ness and
672 * calculation of the actual instruction address.
673 * @param GCPtr The code address relative to the base of Sel.
674 * @param pszPrefix Short prefix string to the disassembly string. (optional)
675 */
676VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
677{
678 char szBuf[256];
679 int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, Sel, GCPtr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
680 &szBuf[0], sizeof(szBuf), NULL);
681 if (RT_FAILURE(rc))
682 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
683 if (pszPrefix && *pszPrefix)
684 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
685 else
686 RTLogPrintf("%s\n", szBuf);
687 return rc;
688}
689
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