VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp

Last change on this file was 102560, checked in by vboxsync, 5 months ago

VMM/DBGFDisas: Convert AssertReleaseFailed() -> AssertFailed() to make the VM process not crash in the testcase, bugref:10393
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1/* $Id: DBGFDisas.cpp 102560 2023-12-10 09:00:59Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DBGF
33#include <VBox/vmm/dbgf.h>
34#include <VBox/vmm/selm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/cpum.h>
39#include "DBGFInternal.h"
40#include <VBox/dis.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43#include <VBox/vmm/vm.h>
44#include <VBox/vmm/uvm.h>
45
46#include <VBox/log.h>
47#include <iprt/assert.h>
48#include <iprt/string.h>
49#include <iprt/alloca.h>
50#include <iprt/ctype.h>
51
52
53/*********************************************************************************************************************************
54* Structures and Typedefs *
55*********************************************************************************************************************************/
56/**
57 * Structure used when disassembling and instructions in DBGF.
58 * This is used so the reader function can get the stuff it needs.
59 */
60typedef struct
61{
62 /** The core structure. */
63 DISSTATE Dis;
64 /** The cross context VM structure. */
65 PVM pVM;
66 /** The cross context virtual CPU structure. */
67 PVMCPU pVCpu;
68 /** The address space for resolving symbol. */
69 RTDBGAS hDbgAs;
70 /** Pointer to the first byte in the segment. */
71 RTGCUINTPTR GCPtrSegBase;
72 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
73 RTGCUINTPTR GCPtrSegEnd;
74 /** The size of the segment minus 1. */
75 RTGCUINTPTR cbSegLimit;
76 /** The guest paging mode. */
77 PGMMODE enmMode;
78 /** Pointer to the current page - R3 Ptr. */
79 void const *pvPageR3;
80 /** Pointer to the current page - GC Ptr. */
81 RTGCPTR GCPtrPage;
82 /** Pointer to the next instruction (relative to GCPtrSegBase). */
83 RTGCUINTPTR GCPtrNext;
84 /** The lock information that PGMPhysReleasePageMappingLock needs. */
85 PGMPAGEMAPLOCK PageMapLock;
86 /** Whether the PageMapLock is valid or not. */
87 bool fLocked;
88 /** 64 bits mode or not. */
89 bool f64Bits;
90} DBGFDISASSTATE, *PDBGFDISASSTATE;
91
92
93/*********************************************************************************************************************************
94* Internal Functions *
95*********************************************************************************************************************************/
96#if !defined(VBOX_VMM_TARGET_ARMV8)
97static FNDISREADBYTES dbgfR3DisasInstrRead;
98
99
100
101/**
102 * Calls the disassembler with the proper reader functions and such for disa
103 *
104 * @returns VBox status code.
105 * @param pVM The cross context VM structure.
106 * @param pVCpu The cross context virtual CPU structure.
107 * @param pSelInfo The selector info.
108 * @param enmMode The guest paging mode.
109 * @param fFlags DBGF_DISAS_FLAGS_XXX.
110 * @param GCPtr The GC pointer (selector offset).
111 * @param pState The disas CPU state.
112 */
113static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
114 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
115{
116 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
117 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
118 pState->cbSegLimit = pSelInfo->cbLimit;
119 pState->enmMode = enmMode;
120 pState->GCPtrPage = 0;
121 pState->pvPageR3 = NULL;
122 pState->hDbgAs = DBGF_AS_GLOBAL;
123 pState->pVM = pVM;
124 pState->pVCpu = pVCpu;
125 pState->fLocked = false;
126 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
127
128 DISCPUMODE enmCpuMode;
129 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
130 {
131 default:
132 AssertFailed();
133 RT_FALL_THRU();
134 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
135 enmCpuMode = pState->f64Bits
136 ? DISCPUMODE_64BIT
137 : pSelInfo->u.Raw.Gen.u1DefBig
138 ? DISCPUMODE_32BIT
139 : DISCPUMODE_16BIT;
140 break;
141 case DBGF_DISAS_FLAGS_16BIT_MODE:
142 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
143 enmCpuMode = DISCPUMODE_16BIT;
144 break;
145 case DBGF_DISAS_FLAGS_32BIT_MODE:
146 enmCpuMode = DISCPUMODE_32BIT;
147 break;
148 case DBGF_DISAS_FLAGS_64BIT_MODE:
149 enmCpuMode = DISCPUMODE_64BIT;
150 break;
151 }
152
153 uint32_t cbInstr;
154 int rc = DISInstrWithReader(GCPtr,
155 enmCpuMode,
156 dbgfR3DisasInstrRead,
157 &pState->Dis,
158 &pState->Dis,
159 &cbInstr);
160 if (RT_SUCCESS(rc))
161 {
162 pState->GCPtrNext = GCPtr + cbInstr;
163 return VINF_SUCCESS;
164 }
165
166 /* cleanup */
167 if (pState->fLocked)
168 {
169 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
170 pState->fLocked = false;
171 }
172 return rc;
173}
174
175
176#if 0
177/**
178 * Calls the disassembler for disassembling the next instruction.
179 *
180 * @returns VBox status code.
181 * @param pState The disas CPU state.
182 */
183static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
184{
185 uint32_t cbInstr;
186 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
187 if (RT_SUCCESS(rc))
188 {
189 pState->GCPtrNext = GCPtr + cbInstr;
190 return VINF_SUCCESS;
191 }
192 return rc;
193}
194#endif
195
196
197/**
198 * Done with the disassembler state, free associated resources.
199 *
200 * @param pState The disas CPU state ++.
201 */
202static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
203{
204 if (pState->fLocked)
205 {
206 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
207 pState->fLocked = false;
208 }
209}
210
211
212/**
213 * @callback_method_impl{FNDISREADBYTES}
214 *
215 * @remarks The source is relative to the base address indicated by
216 * DBGFDISASSTATE::GCPtrSegBase.
217 */
218static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
219{
220 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
221 for (;;)
222 {
223 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
224
225 /*
226 * Need to update the page translation?
227 */
228 if ( !pState->pvPageR3
229 || (GCPtr >> GUEST_PAGE_SHIFT) != (pState->GCPtrPage >> GUEST_PAGE_SHIFT))
230 {
231 int rc = VINF_SUCCESS;
232
233 /* translate the address */
234 pState->GCPtrPage = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
235 if (pState->fLocked)
236 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
237 if (pState->enmMode <= PGMMODE_PROTECTED)
238 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
239 else
240 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
241 if (RT_SUCCESS(rc))
242 pState->fLocked = true;
243 else
244 {
245 pState->fLocked = false;
246 pState->pvPageR3 = NULL;
247 return rc;
248 }
249 }
250
251 /*
252 * Check the segment limit.
253 */
254 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
255 return VERR_OUT_OF_SELECTOR_BOUNDS;
256
257 /*
258 * Calc how much we can read, maxing out the read.
259 */
260 uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
261 if (!pState->f64Bits)
262 {
263 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
264 if (cb > cbSeg && cbSeg)
265 cb = cbSeg;
266 }
267 if (cb > cbMaxRead)
268 cb = cbMaxRead;
269
270 /*
271 * Read and advance,
272 */
273 memcpy(&pDis->Instr.ab[offInstr], (char *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
274 offInstr += (uint8_t)cb;
275 if (cb >= cbMinRead)
276 {
277 pDis->cbCachedInstr = offInstr;
278 return VINF_SUCCESS;
279 }
280 cbMaxRead -= (uint8_t)cb;
281 cbMinRead -= (uint8_t)cb;
282 }
283}
284
285
286/**
287 * @callback_method_impl{FNDISGETSYMBOL}
288 */
289static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
290 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
291{
292 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
293 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
294
295 /*
296 * Address conversion
297 */
298 DBGFADDRESS Addr;
299 int rc;
300 /* Start with CS. */
301 if ( DIS_FMT_SEL_IS_REG(u32Sel)
302 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
303 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
304 rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
305 /* In long mode everything but FS and GS is easy. */
306 else if ( pState->Dis.uCpuMode == DISCPUMODE_64BIT
307 && DIS_FMT_SEL_IS_REG(u32Sel)
308 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
309 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
310 {
311 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
312 rc = VINF_SUCCESS;
313 }
314 /* Here's a quick hack to catch patch manager SS relative access. */
315 else if ( DIS_FMT_SEL_IS_REG(u32Sel)
316 && DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
317 && pSelInfo->GCPtrBase == 0
318 && pSelInfo->cbLimit >= UINT32_MAX)
319 {
320 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
321 rc = VINF_SUCCESS;
322 }
323 else
324 {
325 /** @todo implement a generic solution here. */
326 rc = VERR_SYMBOL_NOT_FOUND;
327 }
328
329 /*
330 * If we got an address, try resolve it into a symbol.
331 */
332 if (RT_SUCCESS(rc))
333 {
334 RTDBGSYMBOL Sym;
335 RTGCINTPTR off;
336 rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr,
337 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL | RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
338 &off, &Sym, NULL /*phMod*/);
339 if (RT_SUCCESS(rc))
340 {
341 /*
342 * Return the symbol and offset.
343 */
344 size_t cchName = strlen(Sym.szName);
345 if (cchName >= cchBuf)
346 cchName = cchBuf - 1;
347 memcpy(pszBuf, Sym.szName, cchName);
348 pszBuf[cchName] = '\0';
349
350 *poff = off;
351 }
352 }
353 return rc;
354}
355#endif /* VBOX_VMM_TARGET_ARMV8 */
356
357
358/**
359 * Disassembles the one instruction according to the specified flags and
360 * address, internal worker executing on the EMT of the specified virtual CPU.
361 *
362 * @returns VBox status code.
363 * @param pVM The cross context VM structure.
364 * @param pVCpu The cross context virtual CPU structure.
365 * @param Sel The code selector. This used to determine the 32/16 bit ness and
366 * calculation of the actual instruction address.
367 * @param pGCPtr Pointer to the variable holding the code address
368 * relative to the base of Sel.
369 * @param fFlags Flags controlling where to start and how to format.
370 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
371 * @param pszOutput Output buffer.
372 * @param cbOutput Size of the output buffer.
373 * @param pcbInstr Where to return the size of the instruction.
374 * @param pDisState Where to store the disassembler state into.
375 */
376static DECLCALLBACK(int)
377dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
378 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr, PDBGFDISSTATE pDisState)
379{
380 VMCPU_ASSERT_EMT(pVCpu);
381 RTGCPTR GCPtr = *pGCPtr;
382 int rc;
383
384#if defined(VBOX_VMM_TARGET_ARMV8)
385 RT_NOREF(pVM, pVCpu, Sel, GCPtr, rc, fFlags, pszOutput, cbOutput, pcbInstr, pDisState);
386 AssertFailed(); /** @todo */
387 return VERR_NOT_IMPLEMENTED;
388#else
389 /*
390 * Get the Sel and GCPtr if fFlags requests that.
391 */
392 PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
393 PCCPUMSELREG pSRegCS = NULL;
394 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
395 {
396 Sel = pCtx->cs.Sel;
397 pSRegCS = &pCtx->cs;
398 GCPtr = pCtx->rip;
399 }
400 /*
401 * Check if the selector matches the guest CS, use the hidden
402 * registers from that if they are valid. Saves time and effort.
403 */
404 else
405 {
406 if (pCtx->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
407 pSRegCS = &pCtx->cs;
408 else
409 pCtx = NULL;
410 }
411
412 /*
413 * Read the selector info - assume no stale selectors and nasty stuff like that.
414 *
415 * Note! We CANNOT load invalid hidden selector registers since that would
416 * mean that log/debug statements or the debug will influence the
417 * guest state and make things behave differently.
418 */
419 DBGFSELINFO SelInfo;
420 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
421 bool fRealModeAddress = false;
422
423 if ( pSRegCS
424 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
425 {
426 SelInfo.Sel = Sel;
427 SelInfo.SelGate = 0;
428 SelInfo.GCPtrBase = pSRegCS->u64Base;
429 SelInfo.cbLimit = pSRegCS->u32Limit;
430 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
431 ? DBGFSELINFO_FLAGS_LONG_MODE
432 : enmMode != PGMMODE_REAL && !pCtx->eflags.Bits.u1VM
433 ? DBGFSELINFO_FLAGS_PROT_MODE
434 : DBGFSELINFO_FLAGS_REAL_MODE;
435
436 SelInfo.u.Raw.au32[0] = 0;
437 SelInfo.u.Raw.au32[1] = 0;
438 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
439 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
440 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
441 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
442 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
443 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
444 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
445 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
446 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
447 }
448 else if (Sel == DBGF_SEL_FLAT)
449 {
450 SelInfo.Sel = Sel;
451 SelInfo.SelGate = 0;
452 SelInfo.GCPtrBase = 0;
453 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
454 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
455 ? DBGFSELINFO_FLAGS_LONG_MODE
456 : enmMode != PGMMODE_REAL
457 ? DBGFSELINFO_FLAGS_PROT_MODE
458 : DBGFSELINFO_FLAGS_REAL_MODE;
459 SelInfo.u.Raw.au32[0] = 0;
460 SelInfo.u.Raw.au32[1] = 0;
461 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
462 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
463
464 pSRegCS = &CPUMQueryGuestCtxPtr(pVCpu)->cs;
465 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
466 {
467 /* Assume the current CS defines the execution mode. */
468 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
469 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
470 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
471 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
472 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
473 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
474 }
475 else
476 {
477 pSRegCS = NULL;
478 SelInfo.u.Raw.Gen.u1Present = 1;
479 SelInfo.u.Raw.Gen.u1Granularity = 1;
480 SelInfo.u.Raw.Gen.u1DefBig = 1;
481 SelInfo.u.Raw.Gen.u1DescType = 1;
482 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
483 }
484 }
485 else if ( (pCtx && pCtx->eflags.Bits.u1VM)
486 || enmMode == PGMMODE_REAL
487 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE)
488 { /* V86 mode or real mode - real mode addressing */
489 SelInfo.Sel = Sel;
490 SelInfo.SelGate = 0;
491 SelInfo.GCPtrBase = Sel * 16;
492 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
493 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
494 SelInfo.u.Raw.au32[0] = 0;
495 SelInfo.u.Raw.au32[1] = 0;
496 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
497 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
498 SelInfo.u.Raw.Gen.u1Present = 1;
499 SelInfo.u.Raw.Gen.u1Granularity = 1;
500 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
501 SelInfo.u.Raw.Gen.u1DescType = 1;
502 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
503 fRealModeAddress = true;
504 }
505 else
506 {
507 rc = SELMR3GetSelectorInfo(pVCpu, Sel, &SelInfo);
508 if (RT_FAILURE(rc))
509 {
510 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
511 return rc;
512 }
513 }
514
515 /*
516 * Disassemble it.
517 */
518 DBGFDISASSTATE State;
519 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
520 if (RT_FAILURE(rc))
521 {
522 if (State.Dis.cbCachedInstr)
523 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Dis.cbCachedInstr, State.Dis.Instr.ab);
524 else
525 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
526 return rc;
527 }
528
529 /*
530 * Format it.
531 */
532 char szBuf[512];
533 DISFormatYasmEx(&State.Dis, szBuf, sizeof(szBuf),
534 DIS_FMT_FLAGS_RELATIVE_BRANCH,
535 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
536 &SelInfo);
537
538 /*
539 * Print it to the user specified buffer.
540 */
541 size_t cch;
542 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
543 {
544 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
545 cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
546 else if (fRealModeAddress)
547 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
548 else if (Sel == DBGF_SEL_FLAT)
549 {
550 if (enmMode >= PGMMODE_AMD64)
551 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
552 else
553 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
554 }
555 else
556 {
557 if (enmMode >= PGMMODE_AMD64)
558 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
559 else
560 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
561 }
562 }
563 else
564 {
565 uint32_t cbInstr = State.Dis.cbInstr;
566 uint8_t const *pabInstr = State.Dis.Instr.ab;
567 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
568 cch = RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
569 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
570 szBuf);
571 else if (fRealModeAddress)
572 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
573 Sel, (unsigned)GCPtr,
574 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
575 szBuf);
576 else if (Sel == DBGF_SEL_FLAT)
577 {
578 if (enmMode >= PGMMODE_AMD64)
579 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
580 GCPtr,
581 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
582 szBuf);
583 else
584 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
585 (uint32_t)GCPtr,
586 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
587 szBuf);
588 }
589 else
590 {
591 if (enmMode >= PGMMODE_AMD64)
592 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
593 Sel, GCPtr,
594 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
595 szBuf);
596 else
597 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
598 Sel, (uint32_t)GCPtr,
599 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
600 szBuf);
601 }
602 }
603
604 if (pcbInstr)
605 *pcbInstr = State.Dis.cbInstr;
606
607 if (pDisState)
608 {
609 pDisState->pCurInstr = State.Dis.pCurInstr;
610 pDisState->cbInstr = State.Dis.cbInstr;
611 pDisState->Param1 = State.Dis.Param1;
612 pDisState->Param2 = State.Dis.Param2;
613 pDisState->Param3 = State.Dis.Param3;
614 pDisState->Param4 = State.Dis.Param4;
615 }
616
617 dbgfR3DisasInstrDone(&State);
618 return VINF_SUCCESS;
619#endif /* !VBOX_VMM_TARGET_ARMV8*/
620}
621
622
623/**
624 * Disassembles the one instruction according to the specified flags and address
625 * returning part of the disassembler state.
626 *
627 * @returns VBox status code.
628 * @param pUVM The user mode VM handle.
629 * @param idCpu The ID of virtual CPU.
630 * @param pAddr The code address.
631 * @param fFlags Flags controlling where to start and how to format.
632 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
633 * @param pszOutput Output buffer. This will always be properly
634 * terminated if @a cbOutput is greater than zero.
635 * @param cbOutput Size of the output buffer.
636 * @param pDisState The disassembler state to fill in.
637 *
638 * @remarks May have to switch to the EMT of the virtual CPU in order to do
639 * address conversion.
640 */
641DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
642 char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
643{
644 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
645 *pszOutput = '\0';
646 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
647 PVM pVM = pUVM->pVM;
648 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
649 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
650 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
651 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
652
653 /*
654 * Optimize the common case where we're called on the EMT of idCpu since
655 * we're using this all the time when logging.
656 */
657 int rc;
658 PVMCPU pVCpu = VMMGetCpu(pVM);
659 if ( pVCpu
660 && pVCpu->idCpu == idCpu)
661 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
662 else
663 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
664 pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
665 return rc;
666}
667
668/**
669 * Disassembles the one instruction according to the specified flags and address.
670 *
671 * @returns VBox status code.
672 * @param pUVM The user mode VM handle.
673 * @param idCpu The ID of virtual CPU.
674 * @param Sel The code selector. This used to determine the 32/16 bit ness and
675 * calculation of the actual instruction address.
676 * @param GCPtr The code address relative to the base of Sel.
677 * @param fFlags Flags controlling where to start and how to format.
678 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
679 * @param pszOutput Output buffer. This will always be properly
680 * terminated if @a cbOutput is greater than zero.
681 * @param cbOutput Size of the output buffer.
682 * @param pcbInstr Where to return the size of the instruction.
683 *
684 * @remarks May have to switch to the EMT of the virtual CPU in order to do
685 * address conversion.
686 */
687VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
688 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
689{
690 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
691 *pszOutput = '\0';
692 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
693 PVM pVM = pUVM->pVM;
694 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
695 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
696 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
697 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
698
699 /*
700 * Optimize the common case where we're called on the EMT of idCpu since
701 * we're using this all the time when logging.
702 */
703 int rc;
704 PVMCPU pVCpu = VMMGetCpu(pVM);
705 if ( pVCpu
706 && pVCpu->idCpu == idCpu)
707 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
708 else
709 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
710 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
711 return rc;
712}
713
714
715/**
716 * Disassembles the current guest context instruction.
717 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
718 *
719 * @returns VBox status code.
720 * @param pVCpu The cross context virtual CPU structure.
721 * @param pszOutput Output buffer. This will always be properly
722 * terminated if @a cbOutput is greater than zero.
723 * @param cbOutput Size of the output buffer.
724 * @thread EMT(pVCpu)
725 */
726VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
727{
728 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
729 *pszOutput = '\0';
730 Assert(VMCPU_IS_EMT(pVCpu));
731
732 RTGCPTR GCPtr = 0;
733 return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
734 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE
735 | DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
736 pszOutput, cbOutput, NULL, NULL);
737}
738
739
740/**
741 * Disassembles the current guest context instruction and writes it to the log.
742 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
743 *
744 * @returns VBox status code.
745 * @param pVCpu The cross context virtual CPU structure.
746 * @param pszPrefix Short prefix string to the disassembly string. (optional)
747 * @thread EMT(pVCpu)
748 */
749VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
750{
751 char szBuf[256];
752 szBuf[0] = '\0';
753 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
754 if (RT_FAILURE(rc))
755 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
756 if (pszPrefix && *pszPrefix)
757 {
758 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
759 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
760 else
761 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
762 }
763 else
764 RTLogPrintf("%s\n", szBuf);
765 return rc;
766}
767
768
769
770/**
771 * Disassembles the specified guest context instruction and writes it to the log.
772 * Addresses will be attempted resolved to symbols.
773 *
774 * @returns VBox status code.
775 * @param pVCpu The cross context virtual CPU structure of the calling
776 * EMT.
777 * @param Sel The code selector. This used to determine the 32/16
778 * bit-ness and calculation of the actual instruction
779 * address.
780 * @param GCPtr The code address relative to the base of Sel.
781 * @param pszPrefix Short prefix string to the disassembly string.
782 * (optional)
783 * @thread EMT(pVCpu)
784 */
785VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
786{
787 Assert(VMCPU_IS_EMT(pVCpu));
788
789 char szBuf[256];
790 RTGCPTR GCPtrTmp = GCPtr;
791 int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
792 &szBuf[0], sizeof(szBuf), NULL, NULL);
793 if (RT_FAILURE(rc))
794 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
795 if (pszPrefix && *pszPrefix)
796 {
797 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
798 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
799 else
800 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
801 }
802 else
803 RTLogPrintf("%s\n", szBuf);
804 return rc;
805}
806
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