VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 43667

Last change on this file since 43667 was 43387, checked in by vboxsync, 12 years ago

VMM: HM cleanup.
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File size: 29.0 KB
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1/* $Id: CPUMR0.cpp 43387 2012-09-21 09:40:25Z vboxsync $ */
2/** @file
3 * CPUM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include "CPUMInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/err.h>
27#include <VBox/log.h>
28#include <VBox/vmm/hm.h>
29#include <iprt/assert.h>
30#include <iprt/asm-amd64-x86.h>
31#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
32# include <iprt/mem.h>
33# include <iprt/memobj.h>
34# include <VBox/apic.h>
35#endif
36#include <iprt/x86.h>
37
38
39/*******************************************************************************
40* Structures and Typedefs *
41*******************************************************************************/
42#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
43/**
44 * Local APIC mappings.
45 */
46typedef struct CPUMHOSTLAPIC
47{
48 /** Indicates that the entry is in use and have valid data. */
49 bool fEnabled;
50 /** Has APIC_REG_LVT_THMR. Not used. */
51 uint32_t fHasThermal;
52 /** The physical address of the APIC registers. */
53 RTHCPHYS PhysBase;
54 /** The memory object entering the physical address. */
55 RTR0MEMOBJ hMemObj;
56 /** The mapping object for hMemObj. */
57 RTR0MEMOBJ hMapObj;
58 /** The mapping address APIC registers.
59 * @remarks Different CPUs may use the same physical address to map their
60 * APICs, so this pointer is only valid when on the CPU owning the
61 * APIC. */
62 void *pv;
63} CPUMHOSTLAPIC;
64#endif
65
66
67/*******************************************************************************
68* Global Variables *
69*******************************************************************************/
70#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
71static CPUMHOSTLAPIC g_aLApics[RTCPUSET_MAX_CPUS];
72#endif
73
74
75/*******************************************************************************
76* Internal Functions *
77*******************************************************************************/
78#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
79static int cpumR0MapLocalApics(void);
80static void cpumR0UnmapLocalApics(void);
81#endif
82
83
84/**
85 * Does the Ring-0 CPU initialization once during module load.
86 * XXX Host-CPU hot-plugging?
87 */
88VMMR0DECL(int) CPUMR0ModuleInit(void)
89{
90 int rc = VINF_SUCCESS;
91#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
92 rc = cpumR0MapLocalApics();
93#endif
94 return rc;
95}
96
97
98/**
99 * Terminate the module.
100 */
101VMMR0DECL(int) CPUMR0ModuleTerm(void)
102{
103#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
104 cpumR0UnmapLocalApics();
105#endif
106 return VINF_SUCCESS;
107}
108
109
110/**
111 * Does Ring-0 CPUM initialization.
112 *
113 * This is mainly to check that the Host CPU mode is compatible
114 * with VBox.
115 *
116 * @returns VBox status code.
117 * @param pVM Pointer to the VM.
118 */
119VMMR0DECL(int) CPUMR0Init(PVM pVM)
120{
121 LogFlow(("CPUMR0Init: %p\n", pVM));
122
123 /*
124 * Check CR0 & CR4 flags.
125 */
126 uint32_t u32CR0 = ASMGetCR0();
127 if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
128 {
129 Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
130 return VERR_UNSUPPORTED_CPU_MODE;
131 }
132
133 /*
134 * Check for sysenter and syscall usage.
135 */
136 if (ASMHasCpuId())
137 {
138 /*
139 * SYSENTER/SYSEXIT
140 *
141 * Intel docs claim you should test both the flag and family, model &
142 * stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
143 * but don't support it. AMD CPUs may support this feature in legacy
144 * mode, they've banned it from long mode. Since we switch to 32-bit
145 * mode when entering raw-mode context the feature would become
146 * accessible again on AMD CPUs, so we have to check regardless of
147 * host bitness.
148 */
149 uint32_t u32CpuVersion;
150 uint32_t u32Dummy;
151 uint32_t fFeatures;
152 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
153 uint32_t u32Family = u32CpuVersion >> 8;
154 uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
155 uint32_t u32Stepping = u32CpuVersion & 0xF;
156 if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
157 && ( u32Family != 6 /* (> pentium pro) */
158 || u32Model >= 3
159 || u32Stepping >= 3
160 || !ASMIsIntelCpu())
161 )
162 {
163 /*
164 * Read the MSR and see if it's in use or not.
165 */
166 uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
167 if (u32)
168 {
169 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSENTER;
170 Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
171 }
172 }
173
174 /*
175 * SYSCALL/SYSRET
176 *
177 * This feature is indicated by the SEP bit returned in EDX by CPUID
178 * function 0x80000001. Intel CPUs only supports this feature in
179 * long mode. Since we're not running 64-bit guests in raw-mode there
180 * are no issues with 32-bit intel hosts.
181 */
182 uint32_t cExt = 0;
183 ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
184 if ( cExt >= 0x80000001
185 && cExt <= 0x8000ffff)
186 {
187 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
188 if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
189 {
190#ifdef RT_ARCH_X86
191# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
192 if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
193# else
194 if (!ASMIsIntelCpu())
195# endif
196#endif
197 {
198 uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
199 if (fEfer & MSR_K6_EFER_SCE)
200 {
201 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSCALL;
202 Log(("CPUMR0Init: host uses syscall\n"));
203 }
204 }
205 }
206 }
207 }
208
209
210 /*
211 * Check if debug registers are armed.
212 * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
213 */
214 uint32_t u32DR7 = ASMGetDR7();
215 if (u32DR7 & X86_DR7_ENABLED_MASK)
216 {
217 for (VMCPUID i = 0; i < pVM->cCpus; i++)
218 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
219 Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
220 }
221
222 return VINF_SUCCESS;
223}
224
225
226/**
227 * Lazily sync in the FPU/XMM state
228 *
229 * @returns VBox status code.
230 * @param pVM Pointer to the VM.
231 * @param pVCpu Pointer to the VMCPU.
232 * @param pCtx Pointer to the guest CPU context.
233 */
234VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
235{
236 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
237 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
238
239 /* If the FPU state has already been loaded, then it's a guest trap. */
240 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU)
241 {
242 Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
243 || ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)));
244 return VINF_EM_RAW_GUEST_TRAP;
245 }
246
247 /*
248 * There are two basic actions:
249 * 1. Save host fpu and restore guest fpu.
250 * 2. Generate guest trap.
251 *
252 * When entering the hypervisor we'll always enable MP (for proper wait
253 * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
254 * is taken from the guest OS in order to get proper SSE handling.
255 *
256 *
257 * Actions taken depending on the guest CR0 flags:
258 *
259 * 3 2 1
260 * TS | EM | MP | FPUInstr | WAIT :: VMM Action
261 * ------------------------------------------------------------------------
262 * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
263 * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
264 * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
265 * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
266 * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
267 * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
268 * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
269 * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
270 */
271
272 switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
273 {
274 case X86_CR0_MP | X86_CR0_TS:
275 case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
276 return VINF_EM_RAW_GUEST_TRAP;
277 default:
278 break;
279 }
280
281#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
282 if (CPUMIsGuestInLongModeEx(pCtx))
283 {
284 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE));
285
286 /* Save the host state and record the fact (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM). */
287 cpumR0SaveHostFPUState(&pVCpu->cpum.s);
288
289 /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
290 pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_FPU_STATE;
291 }
292 else
293#endif
294 {
295#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
296# if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined(VBOX_WITH_KERNEL_USING_XMM) /** @todo remove the #else here and move cpumHandleLazyFPUAsm back to VMMGC after branching out 3.0!!. */
297 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE));
298 /** @todo Move the FFXR handling down into
299 * cpumR0SaveHostRestoreguestFPUState to optimize the
300 * VBOX_WITH_KERNEL_USING_XMM handling. */
301 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
302 uint64_t SavedEFER = 0;
303 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
304 {
305 SavedEFER = ASMRdMsr(MSR_K6_EFER);
306 if (SavedEFER & MSR_K6_EFER_FFXSR)
307 {
308 ASMWrMsr(MSR_K6_EFER, SavedEFER & ~MSR_K6_EFER_FFXSR);
309 pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
310 }
311 }
312
313 /* Do the job and record that we've switched FPU state. */
314 cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
315
316 /* Restore EFER. */
317 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
318 ASMWrMsr(MSR_K6_EFER, SavedEFER);
319
320# else
321 uint64_t oldMsrEFERHost = 0;
322 uint32_t oldCR0 = ASMGetCR0();
323
324 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
325 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
326 {
327 /** @todo Do we really need to read this every time?? The host could change this on the fly though.
328 * bird: what about starting by skipping the ASMWrMsr below if we didn't
329 * change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
330 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
331 if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
332 {
333 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
334 pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
335 }
336 }
337
338 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
339 int rc = CPUMHandleLazyFPU(pVCpu);
340 AssertRC(rc);
341 Assert(CPUMIsGuestFPUStateActive(pVCpu));
342
343 /* Restore EFER MSR */
344 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
345 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
346
347 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
348 ASMSetCR0(oldCR0);
349# endif
350
351#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
352
353 /*
354 * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
355 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
356 */
357 pVCpu->cpum.s.Host.fpu.FCW = CPUMGetFCW();
358 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
359 pVCpu->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
360
361 cpumR0LoadFPU(pCtx);
362
363 /*
364 * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
365 *
366 * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
367 */
368 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
369 {
370 /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
371 uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
372
373 if (msrEFERHost & MSR_K6_EFER_FFXSR)
374 {
375 /* fxrstor doesn't restore the XMM state! */
376 cpumR0LoadXMM(pCtx);
377 pVCpu->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
378 }
379 }
380
381#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
382 }
383
384 Assert((pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM)) == (CPUM_USED_FPU | CPUM_USED_FPU_SINCE_REM));
385 return VINF_SUCCESS;
386}
387
388
389/**
390 * Save guest FPU/XMM state
391 *
392 * @returns VBox status code.
393 * @param pVM Pointer to the VM.
394 * @param pVCpu Pointer to the VMCPU.
395 * @param pCtx Pointer to the guest CPU context.
396 */
397VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
398{
399 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
400 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
401 AssertReturn((pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
402 NOREF(pCtx);
403
404#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
405 if (CPUMIsGuestInLongModeEx(pCtx))
406 {
407 if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_FPU_STATE))
408 {
409 HMR0SaveFPUState(pVM, pVCpu, pCtx);
410 cpumR0RestoreHostFPUState(&pVCpu->cpum.s);
411 }
412 /* else nothing to do; we didn't perform a world switch */
413 }
414 else
415#endif
416 {
417#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
418# ifdef VBOX_WITH_KERNEL_USING_XMM
419 /*
420 * We've already saved the XMM registers in the assembly wrapper, so
421 * we have to save them before saving the entire FPU state and put them
422 * back afterwards.
423 */
424 /** @todo This could be skipped if MSR_K6_EFER_FFXSR is set, but
425 * I'm not able to test such an optimization tonight.
426 * We could just all this in assembly. */
427 uint128_t aGuestXmmRegs[16];
428 memcpy(&aGuestXmmRegs[0], &pVCpu->cpum.s.Guest.fpu.aXMM[0], sizeof(aGuestXmmRegs));
429# endif
430
431 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
432 uint64_t oldMsrEFERHost = 0;
433 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
434 {
435 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
436 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
437 }
438 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
439
440 /* Restore EFER MSR */
441 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
442 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
443
444# ifdef VBOX_WITH_KERNEL_USING_XMM
445 memcpy(&pVCpu->cpum.s.Guest.fpu.aXMM[0], &aGuestXmmRegs[0], sizeof(aGuestXmmRegs));
446# endif
447
448#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
449# ifdef VBOX_WITH_KERNEL_USING_XMM
450# error "Fix all the NM_TRAPS_IN_KERNEL_MODE code path. I'm not going to fix unused code now."
451# endif
452 cpumR0SaveFPU(pCtx);
453 if (pVCpu->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
454 {
455 /* fxsave doesn't save the XMM state! */
456 cpumR0SaveXMM(pCtx);
457 }
458
459 /*
460 * Restore the original FPU control word and MXCSR.
461 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
462 */
463 cpumR0SetFCW(pVCpu->cpum.s.Host.fpu.FCW);
464 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
465 cpumR0SetMXCSR(pVCpu->cpum.s.Host.fpu.MXCSR);
466#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
467 }
468
469 pVCpu->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_SYNC_FPU_STATE | CPUM_MANUAL_XMM_RESTORE);
470 return VINF_SUCCESS;
471}
472
473
474/**
475 * Save guest debug state
476 *
477 * @returns VBox status code.
478 * @param pVM Pointer to the VM.
479 * @param pVCpu Pointer to the VMCPU.
480 * @param pCtx Pointer to the guest CPU context.
481 * @param fDR6 Whether to include DR6 or not.
482 */
483VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
484{
485 Assert(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
486
487 /* Save the guest's debug state. The caller is responsible for DR7. */
488#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
489 if (CPUMIsGuestInLongModeEx(pCtx))
490 {
491 if (!(pVCpu->cpum.s.fUseFlags & CPUM_SYNC_DEBUG_STATE))
492 {
493 uint64_t dr6 = pCtx->dr[6];
494
495 HMR0SaveDebugState(pVM, pVCpu, pCtx);
496 if (!fDR6) /* dr6 was already up-to-date */
497 pCtx->dr[6] = dr6;
498 }
499 }
500 else
501#endif
502 {
503#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
504 cpumR0SaveDRx(&pCtx->dr[0]);
505#else
506 pCtx->dr[0] = ASMGetDR0();
507 pCtx->dr[1] = ASMGetDR1();
508 pCtx->dr[2] = ASMGetDR2();
509 pCtx->dr[3] = ASMGetDR3();
510#endif
511 if (fDR6)
512 pCtx->dr[6] = ASMGetDR6();
513 }
514
515 /*
516 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
517 * DR7 contains 0x400 right now.
518 */
519 CPUMR0LoadHostDebugState(pVM, pVCpu);
520 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS));
521 return VINF_SUCCESS;
522}
523
524
525/**
526 * Lazily sync in the debug state
527 *
528 * @returns VBox status code.
529 * @param pVM Pointer to the VM.
530 * @param pVCpu Pointer to the VMCPU.
531 * @param pCtx Pointer to the guest CPU context.
532 * @param fDR6 Whether to include DR6 or not.
533 */
534VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
535{
536 /* Save the host state. */
537 CPUMR0SaveHostDebugState(pVM, pVCpu);
538 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
539
540 /* Activate the guest state DR0-3; DR7 is left to the caller. */
541#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
542 if (CPUMIsGuestInLongModeEx(pCtx))
543 {
544 /* Restore the state on entry as we need to be in 64 bits mode to access the full state. */
545 pVCpu->cpum.s.fUseFlags |= CPUM_SYNC_DEBUG_STATE;
546 }
547 else
548#endif
549 {
550#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
551 cpumR0LoadDRx(&pCtx->dr[0]);
552#else
553 ASMSetDR0(pCtx->dr[0]);
554 ASMSetDR1(pCtx->dr[1]);
555 ASMSetDR2(pCtx->dr[2]);
556 ASMSetDR3(pCtx->dr[3]);
557#endif
558 if (fDR6)
559 ASMSetDR6(pCtx->dr[6]);
560 }
561
562 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
563 return VINF_SUCCESS;
564}
565
566/**
567 * Save the host debug state
568 *
569 * @returns VBox status code.
570 * @param pVM Pointer to the VM.
571 * @param pVCpu Pointer to the VMCPU.
572 */
573VMMR0DECL(int) CPUMR0SaveHostDebugState(PVM pVM, PVMCPU pVCpu)
574{
575 NOREF(pVM);
576
577 /* Save the host state. */
578#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
579 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
580 cpumR0SaveDRx(&pVCpu->cpum.s.Host.dr0);
581#else
582 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
583 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
584 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
585 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
586#endif
587 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
588 /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
589 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
590 /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
591 ASMSetDR7(X86_DR7_INIT_VAL);
592
593 return VINF_SUCCESS;
594}
595
596/**
597 * Load the host debug state
598 *
599 * @returns VBox status code.
600 * @param pVM Pointer to the VM.
601 * @param pVCpu Pointer to the VMCPU.
602 */
603VMMR0DECL(int) CPUMR0LoadHostDebugState(PVM pVM, PVMCPU pVCpu)
604{
605 Assert(pVCpu->cpum.s.fUseFlags & (CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HYPER));
606 NOREF(pVM);
607
608 /*
609 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
610 * DR7 contains 0x400 right now.
611 */
612#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
613 AssertCompile((uintptr_t)&pVCpu->cpum.s.Host.dr3 - (uintptr_t)&pVCpu->cpum.s.Host.dr0 == sizeof(uint64_t) * 3);
614 cpumR0LoadDRx(&pVCpu->cpum.s.Host.dr0);
615#else
616 ASMSetDR0(pVCpu->cpum.s.Host.dr0);
617 ASMSetDR1(pVCpu->cpum.s.Host.dr1);
618 ASMSetDR2(pVCpu->cpum.s.Host.dr2);
619 ASMSetDR3(pVCpu->cpum.s.Host.dr3);
620#endif
621 ASMSetDR6(pVCpu->cpum.s.Host.dr6);
622 ASMSetDR7(pVCpu->cpum.s.Host.dr7);
623
624 pVCpu->cpum.s.fUseFlags &= ~(CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HYPER);
625 return VINF_SUCCESS;
626}
627
628
629/**
630 * Lazily sync in the hypervisor debug state
631 *
632 * @returns VBox status code.
633 * @param pVM Pointer to the VM.
634 * @param pVCpu Pointer to the VMCPU.
635 * @param pCtx Pointer to the guest CPU context.
636 * @param fDR6 Whether to include DR6 or not.
637 */
638VMMR0DECL(int) CPUMR0LoadHyperDebugState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, bool fDR6)
639{
640 NOREF(pCtx);
641
642 /* Save the host state. */
643 CPUMR0SaveHostDebugState(pVM, pVCpu);
644 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
645
646 /* Activate the guest state DR0-3; DR7 is left to the caller. */
647#if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
648 if (CPUMIsGuestInLongModeEx(pCtx))
649 {
650 AssertFailed();
651 return VERR_NOT_IMPLEMENTED;
652 }
653 else
654#endif
655 {
656#ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
657 AssertFailed();
658 return VERR_NOT_IMPLEMENTED;
659#else
660 ASMSetDR0(CPUMGetHyperDR0(pVCpu));
661 ASMSetDR1(CPUMGetHyperDR1(pVCpu));
662 ASMSetDR2(CPUMGetHyperDR2(pVCpu));
663 ASMSetDR3(CPUMGetHyperDR3(pVCpu));
664#endif
665 if (fDR6)
666 ASMSetDR6(CPUMGetHyperDR6(pVCpu));
667 }
668
669 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HYPER;
670 return VINF_SUCCESS;
671}
672
673#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
674
675/**
676 * Worker for cpumR0MapLocalApics. Check each CPU for a present Local APIC.
677 * Play safe and treat each CPU separate.
678 */
679static DECLCALLBACK(void) cpumR0MapLocalApicWorker(RTCPUID idCpu, void *pvUser1, void *pvUser2)
680{
681 NOREF(pvUser1); NOREF(pvUser2);
682 int iCpu = RTMpCpuIdToSetIndex(idCpu);
683 AssertReturnVoid(iCpu >= 0 && (unsigned)iCpu < RT_ELEMENTS(g_aLApics));
684
685 uint32_t u32MaxIdx, u32EBX, u32ECX, u32EDX;
686 ASMCpuId(0, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
687 if ( ( ( u32EBX == X86_CPUID_VENDOR_INTEL_EBX
688 && u32ECX == X86_CPUID_VENDOR_INTEL_ECX
689 && u32EDX == X86_CPUID_VENDOR_INTEL_EDX)
690 || ( u32EBX == X86_CPUID_VENDOR_AMD_EBX
691 && u32ECX == X86_CPUID_VENDOR_AMD_ECX
692 && u32EDX == X86_CPUID_VENDOR_AMD_EDX)
693 || ( u32EBX == X86_CPUID_VENDOR_VIA_EBX
694 && u32ECX == X86_CPUID_VENDOR_VIA_ECX
695 && u32EDX == X86_CPUID_VENDOR_VIA_EDX))
696 && u32MaxIdx >= 1)
697 {
698 ASMCpuId(1, &u32MaxIdx, &u32EBX, &u32ECX, &u32EDX);
699 if ( (u32EDX & X86_CPUID_FEATURE_EDX_APIC)
700 && (u32EDX & X86_CPUID_FEATURE_EDX_MSR))
701 {
702 uint64_t u64ApicBase = ASMRdMsr(MSR_IA32_APICBASE);
703 uint64_t u64Mask = UINT64_C(0x0000000ffffff000);
704
705 /* see Intel Manual: Local APIC Status and Location: MAXPHYADDR default is bit 36 */
706 uint32_t u32MaxExtIdx;
707 ASMCpuId(0x80000000, &u32MaxExtIdx, &u32EBX, &u32ECX, &u32EDX);
708 if ( u32MaxExtIdx >= UINT32_C(0x80000008)
709 && u32MaxExtIdx < UINT32_C(0x8000ffff))
710 {
711 uint32_t u32PhysBits;
712 ASMCpuId(0x80000008, &u32PhysBits, &u32EBX, &u32ECX, &u32EDX);
713 u32PhysBits &= 0xff;
714 u64Mask = ((UINT64_C(1) << u32PhysBits) - 1) & UINT64_C(0xfffffffffffff000);
715 }
716
717 uint64_t const u64PhysBase = u64ApicBase & u64Mask;
718 g_aLApics[iCpu].PhysBase = (RTHCPHYS)u64PhysBase;
719 g_aLApics[iCpu].fEnabled = g_aLApics[iCpu].PhysBase == u64PhysBase;
720 }
721 }
722}
723
724
725/**
726 * Map the MMIO page of each local APIC in the system.
727 */
728static int cpumR0MapLocalApics(void)
729{
730 /*
731 * Check that we'll always stay within the array bounds.
732 */
733 if (RTMpGetArraySize() > RT_ELEMENTS(g_aLApics))
734 {
735 LogRel(("CPUM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aLApics)));
736 return VERR_TOO_MANY_CPUS;
737 }
738
739 /*
740 * Create mappings for all online CPUs we think have APICs.
741 */
742 /** @todo r=bird: This code is not adequately handling CPUs that are
743 * offline or unplugged at init time and later bought into action. */
744 int rc = RTMpOnAll(cpumR0MapLocalApicWorker, NULL, NULL);
745
746 for (unsigned iCpu = 0; RT_SUCCESS(rc) && iCpu < RT_ELEMENTS(g_aLApics); iCpu++)
747 {
748 if (g_aLApics[iCpu].fEnabled)
749 {
750 rc = RTR0MemObjEnterPhys(&g_aLApics[iCpu].hMemObj, g_aLApics[iCpu].PhysBase,
751 PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
752 if (RT_SUCCESS(rc))
753 {
754 rc = RTR0MemObjMapKernel(&g_aLApics[iCpu].hMapObj, g_aLApics[iCpu].hMemObj, (void *)-1,
755 PAGE_SIZE, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
756 if (RT_SUCCESS(rc))
757 {
758 void *pvApicBase = RTR0MemObjAddress(g_aLApics[iCpu].hMapObj);
759
760 /*
761 * 0x0X 82489 external APIC
762 * 0x1X Local APIC
763 * 0x2X..0xFF reserved
764 */
765 /** @todo r=bird: The local APIC is usually at the same address for all CPUs,
766 * and therefore inaccessible by the other CPUs. */
767 uint32_t ApicVersion = ApicRegRead(pvApicBase, APIC_REG_VERSION);
768 if ((APIC_REG_VERSION_GET_VER(ApicVersion) & 0xF0) == 0x10)
769 {
770 g_aLApics[iCpu].fHasThermal = APIC_REG_VERSION_GET_MAX_LVT(ApicVersion) >= 5;
771 g_aLApics[iCpu].pv = pvApicBase;
772 Log(("CPUM: APIC %02u at %RGp (mapped at %p) - ver %#x, lint0=%#x lint1=%#x pc=%#x thmr=%#x\n",
773 iCpu, g_aLApics[iCpu].PhysBase, g_aLApics[iCpu].pv, ApicVersion,
774 ApicRegRead(pvApicBase, APIC_REG_LVT_LINT0),
775 ApicRegRead(pvApicBase, APIC_REG_LVT_LINT1),
776 ApicRegRead(pvApicBase, APIC_REG_LVT_PC),
777 ApicRegRead(pvApicBase, APIC_REG_LVT_THMR)
778 ));
779 continue;
780 }
781
782 RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
783 }
784 RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
785 }
786 g_aLApics[iCpu].fEnabled = false;
787 }
788 }
789 if (RT_FAILURE(rc))
790 {
791 cpumR0UnmapLocalApics();
792 return rc;
793 }
794
795 return VINF_SUCCESS;
796}
797
798
799/**
800 * Unmap the Local APIC of all host CPUs.
801 */
802static void cpumR0UnmapLocalApics(void)
803{
804 for (unsigned iCpu = RT_ELEMENTS(g_aLApics); iCpu-- > 0;)
805 {
806 if (g_aLApics[iCpu].pv)
807 {
808 RTR0MemObjFree(g_aLApics[iCpu].hMapObj, true /* fFreeMappings */);
809 RTR0MemObjFree(g_aLApics[iCpu].hMemObj, true /* fFreeMappings */);
810 g_aLApics[iCpu].hMapObj = NIL_RTR0MEMOBJ;
811 g_aLApics[iCpu].hMemObj = NIL_RTR0MEMOBJ;
812 g_aLApics[iCpu].fEnabled = false;
813 g_aLApics[iCpu].pv = NULL;
814 }
815 }
816}
817
818
819/**
820 * Write the Local APIC mapping address of the current host CPU to CPUM to be
821 * able to access the APIC registers in the raw mode switcher for disabling/
822 * re-enabling the NMI. Must be called with disabled preemption or disabled
823 * interrupts!
824 *
825 * @param pVM Pointer to the VM.
826 * @param idHostCpu The ID of the current host CPU.
827 */
828VMMR0DECL(void) CPUMR0SetLApic(PVM pVM, RTCPUID idHostCpu)
829{
830 pVM->cpum.s.pvApicBase = g_aLApics[RTMpCpuIdToSetIndex(idHostCpu)].pv;
831}
832
833#endif /* VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI */
834
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