VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

Last change on this file was 99739, checked in by vboxsync, 12 months ago

*: doxygen corrections (mostly about removing @returns from functions returning void).
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1/* $Id: CPUMR0.cpp 99739 2023-05-11 01:01:08Z vboxsync $ */
2/** @file
3 * CPUM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_CPUM
33#define CPUM_WITH_NONCONST_HOST_FEATURES
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/hm.h>
36#include "CPUMInternal.h"
37#include <VBox/vmm/vmcc.h>
38#include <VBox/vmm/gvm.h>
39#include <VBox/err.h>
40#include <VBox/log.h>
41#include <VBox/vmm/hm.h>
42#include <iprt/assert.h>
43#include <iprt/asm-amd64-x86.h>
44#include <iprt/mem.h>
45#include <iprt/x86.h>
46
47
48/*********************************************************************************************************************************
49* Global Variables *
50*********************************************************************************************************************************/
51/** Host CPU features. */
52DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
53/** Static storage for host MSRs. */
54static CPUMMSRS g_CpumHostMsrs;
55
56/**
57 * CPUID bits to unify among all cores.
58 */
59static struct
60{
61 uint32_t uLeaf; /**< Leaf to check. */
62 uint32_t uEcx; /**< which bits in ecx to unify between CPUs. */
63 uint32_t uEdx; /**< which bits in edx to unify between CPUs. */
64}
65const g_aCpuidUnifyBits[] =
66{
67 {
68 0x00000001,
69 X86_CPUID_FEATURE_ECX_CX16 | X86_CPUID_FEATURE_ECX_MONITOR,
70 X86_CPUID_FEATURE_EDX_CX8
71 }
72};
73
74
75
76/*********************************************************************************************************************************
77* Internal Functions *
78*********************************************************************************************************************************/
79static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
80
81
82/**
83 * Check the CPUID features of this particular CPU and disable relevant features
84 * for the guest which do not exist on this CPU.
85 *
86 * We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
87 * only set on some host CPUs, see @bugref{5436}.
88 *
89 * @note This function might be called simultaneously on more than one CPU!
90 *
91 * @param idCpu The identifier for the CPU the function is called on.
92 * @param pvUser1 Leaf array.
93 * @param pvUser2 Number of leaves.
94 */
95static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void *pvUser1, void *pvUser2)
96{
97 PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
98 uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
99 RT_NOREF(idCpu);
100
101 for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
102 {
103 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
104 if (pLeaf)
105 {
106 uint32_t uEax, uEbx, uEcx, uEdx;
107 ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
108
109 ASMAtomicAndU32(&pLeaf->uEcx, uEcx | ~g_aCpuidUnifyBits[i].uEcx);
110 ASMAtomicAndU32(&pLeaf->uEdx, uEdx | ~g_aCpuidUnifyBits[i].uEdx);
111 }
112 }
113}
114
115
116/**
117 * Does the Ring-0 CPU initialization once during module load.
118 * XXX Host-CPU hot-plugging?
119 */
120VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
121{
122 /*
123 * Query the hardware virtualization capabilities of the host CPU first.
124 */
125 uint32_t fHwCaps = 0;
126 int rc = SUPR0GetVTSupport(&fHwCaps);
127 AssertLogRelMsg(RT_SUCCESS(rc) || rc == VERR_UNSUPPORTED_CPU || rc == VERR_SVM_NO_SVM || rc == VERR_VMX_NO_VMX,
128 ("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
129 if (RT_SUCCESS(rc))
130 {
131 SUPHWVIRTMSRS HwvirtMsrs;
132 rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /*fIgnored*/);
133 AssertLogRelRC(rc);
134 if (RT_SUCCESS(rc))
135 {
136 if (fHwCaps & SUPVTCAPS_VT_X)
137 HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
138 else
139 HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
140 }
141 }
142
143 /*
144 * Collect CPUID leaves.
145 */
146 PCPUMCPUIDLEAF paLeaves;
147 uint32_t cLeaves;
148 rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
149 AssertLogRelRCReturn(rc, rc);
150
151 /*
152 * Unify/cross check some CPUID feature bits on all available CPU cores
153 * and threads. We've seen CPUs where the monitor support differed.
154 */
155 RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
156
157 /*
158 * Populate the host CPU feature global variable.
159 */
160 rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
161 RTMemFree(paLeaves);
162 AssertLogRelRCReturn(rc, rc);
163
164 /*
165 * Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
166 */
167 if (ASMHasCpuId())
168 {
169 /** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
170 g_CpumHostFeatures.s.fArchRdclNo = 0;
171 g_CpumHostFeatures.s.fArchIbrsAll = 0;
172 g_CpumHostFeatures.s.fArchRsbOverride = 0;
173 g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
174 g_CpumHostFeatures.s.fArchMdsNo = 0;
175 uint32_t const cStdRange = ASMCpuId_EAX(0);
176 if ( RTX86IsValidStdRange(cStdRange)
177 && cStdRange >= 7)
178 {
179 uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
180 uint32_t fStdExtFeaturesEdx;
181 ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
182 if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
183 && (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
184 {
185 uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
186 g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
187 g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
188 g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
189 g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
190 g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
191 }
192 else
193 g_CpumHostFeatures.s.fArchCap = 0;
194 }
195 }
196
197 return VINF_SUCCESS;
198}
199
200
201/**
202 * Terminate the module.
203 */
204VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
205{
206 return VINF_SUCCESS;
207}
208
209
210/**
211 * Initializes the CPUM data in the VM structure.
212 *
213 * @param pGVM The global VM structure.
214 */
215VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
216{
217 /* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
218 pGVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
219}
220
221
222/**
223 * Check the CPUID features of this particular CPU and disable relevant features
224 * for the guest which do not exist on this CPU. We have seen systems where the
225 * X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
226 * @bugref{5436}.
227 *
228 * @note This function might be called simultaneously on more than one CPU!
229 *
230 * @param idCpu The identifier for the CPU the function is called on.
231 * @param pvUser1 Pointer to the VM structure.
232 * @param pvUser2 Ignored.
233 */
234static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void *pvUser1, void *pvUser2)
235{
236 PVMCC pVM = (PVMCC)pvUser1;
237
238 NOREF(idCpu); NOREF(pvUser2);
239 for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
240 {
241 /* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
242 necessarily in the VM process context. So, we using the
243 legacy arrays as temporary storage. */
244
245 uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
246 PCPUMCPUID pLegacyLeaf;
247 if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
248 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
249 else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
250 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
251 else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
252 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
253 else
254 continue;
255
256 uint32_t eax, ebx, ecx, edx;
257 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
258
259 ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx | ~g_aCpuidUnifyBits[i].uEcx);
260 ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx | ~g_aCpuidUnifyBits[i].uEdx);
261 }
262}
263
264
265/**
266 * Does Ring-0 CPUM initialization.
267 *
268 * This is mainly to check that the Host CPU mode is compatible
269 * with VBox.
270 *
271 * @returns VBox status code.
272 * @param pVM The cross context VM structure.
273 */
274VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
275{
276 LogFlow(("CPUMR0Init: %p\n", pVM));
277 AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
278
279 /*
280 * Check CR0 & CR4 flags.
281 */
282 uint32_t u32CR0 = ASMGetCR0();
283 if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
284 {
285 Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
286 return VERR_UNSUPPORTED_CPU_MODE;
287 }
288
289 /*
290 * Check for sysenter and syscall usage.
291 */
292 if (ASMHasCpuId())
293 {
294 /*
295 * SYSENTER/SYSEXIT
296 *
297 * Intel docs claim you should test both the flag and family, model &
298 * stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
299 * but don't support it. AMD CPUs may support this feature in legacy
300 * mode, they've banned it from long mode. Since we switch to 32-bit
301 * mode when entering raw-mode context the feature would become
302 * accessible again on AMD CPUs, so we have to check regardless of
303 * host bitness.
304 */
305 uint32_t u32CpuVersion;
306 uint32_t u32Dummy;
307 uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
308 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
309 uint32_t const u32Family = u32CpuVersion >> 8;
310 uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
311 uint32_t const u32Stepping = u32CpuVersion & 0xF;
312 if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
313 && ( u32Family != 6 /* (> pentium pro) */
314 || u32Model >= 3
315 || u32Stepping >= 3
316 || !ASMIsIntelCpu())
317 )
318 {
319 /*
320 * Read the MSR and see if it's in use or not.
321 */
322 uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
323 if (u32)
324 {
325 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSENTER;
326 Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
327 }
328 }
329
330 /*
331 * SYSCALL/SYSRET
332 *
333 * This feature is indicated by the SEP bit returned in EDX by CPUID
334 * function 0x80000001. Intel CPUs only supports this feature in
335 * long mode. Since we're not running 64-bit guests in raw-mode there
336 * are no issues with 32-bit intel hosts.
337 */
338 uint32_t cExt = 0;
339 ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
340 if (RTX86IsValidExtRange(cExt))
341 {
342 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
343 if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
344 {
345#ifdef RT_ARCH_X86
346 if (!ASMIsIntelCpu())
347#endif
348 {
349 uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
350 if (fEfer & MSR_K6_EFER_SCE)
351 {
352 pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSCALL;
353 Log(("CPUMR0Init: host uses syscall\n"));
354 }
355 }
356 }
357 }
358
359 /*
360 * Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
361 * structure and as well as the guest MSR.
362 * Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
363 */
364 pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
365 pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
366 pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
367 pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
368 pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
369 uint32_t const cStdRange = ASMCpuId_EAX(0);
370 if ( RTX86IsValidStdRange(cStdRange)
371 && cStdRange >= 7)
372 {
373 uint32_t fEdxFeatures = ASMCpuId_EDX(7);
374 if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
375 && (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
376 {
377 /* Host: */
378 uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
379 pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
380 pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
381 pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
382 pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
383 pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
384
385 /* guest: */
386 if (!pVM->cpum.s.GuestFeatures.fArchCap)
387 fArchVal = 0;
388 else if (!pVM->cpum.s.GuestFeatures.fIbrs)
389 fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
390 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
391 pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
392 pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
393 pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
394 pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
395 pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
396 }
397 else
398 pVM->cpum.s.HostFeatures.fArchCap = 0;
399 }
400
401 /*
402 * Unify/cross check some CPUID feature bits on all available CPU cores
403 * and threads. We've seen CPUs where the monitor support differed.
404 *
405 * Because the hyper heap isn't always mapped into ring-0, we cannot
406 * access it from a RTMpOnAll callback. We use the legacy CPUID arrays
407 * as temp ring-0 accessible memory instead, ASSUMING that they're all
408 * up to date when we get here.
409 */
410 RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
411
412 for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
413 {
414 bool fIgnored;
415 uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
416 PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
417 if (pLeaf)
418 {
419 PCPUMCPUID pLegacyLeaf;
420 if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
421 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
422 else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
423 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
424 else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
425 pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
426 else
427 continue;
428
429 pLeaf->uEcx = pLegacyLeaf->uEcx;
430 pLeaf->uEdx = pLegacyLeaf->uEdx;
431 }
432 }
433
434 }
435
436
437 /*
438 * Check if debug registers are armed.
439 * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
440 */
441 uint32_t u32DR7 = ASMGetDR7();
442 if (u32DR7 & X86_DR7_ENABLED_MASK)
443 {
444 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST);
445 Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
446 }
447
448 return VINF_SUCCESS;
449}
450
451
452/**
453 * Trap handler for device-not-available fault (\#NM).
454 * Device not available, FP or (F)WAIT instruction.
455 *
456 * @returns VBox status code.
457 * @retval VINF_SUCCESS if the guest FPU state is loaded.
458 * @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
459 * @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
460 *
461 * @param pVM The cross context VM structure.
462 * @param pVCpu The cross context virtual CPU structure.
463 */
464VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
465{
466 Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
467 Assert(ASMGetCR4() & X86_CR4_OSFXSR);
468
469 /* If the FPU state has already been loaded, then it's a guest trap. */
470 if (CPUMIsGuestFPUStateActive(pVCpu))
471 {
472 Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))
473 || ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS | X86_CR0_EM)));
474 return VINF_EM_RAW_GUEST_TRAP;
475 }
476
477 /*
478 * There are two basic actions:
479 * 1. Save host fpu and restore guest fpu.
480 * 2. Generate guest trap.
481 *
482 * When entering the hypervisor we'll always enable MP (for proper wait
483 * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
484 * is taken from the guest OS in order to get proper SSE handling.
485 *
486 *
487 * Actions taken depending on the guest CR0 flags:
488 *
489 * 3 2 1
490 * TS | EM | MP | FPUInstr | WAIT :: VMM Action
491 * ------------------------------------------------------------------------
492 * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
493 * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
494 * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
495 * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
496 * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
497 * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
498 * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
499 * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
500 */
501
502 switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
503 {
504 case X86_CR0_MP | X86_CR0_TS:
505 case X86_CR0_MP | X86_CR0_TS | X86_CR0_EM:
506 return VINF_EM_RAW_GUEST_TRAP;
507 default:
508 break;
509 }
510
511 return CPUMR0LoadGuestFPU(pVM, pVCpu);
512}
513
514
515/**
516 * Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
517 * state into the CPU.
518 *
519 * @returns VINF_SUCCESS on success, host CR0 unmodified.
520 * @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
521 * modified and VT-x needs to update the value in the VMCS.
522 *
523 * @param pVM The cross context VM structure.
524 * @param pVCpu The cross context virtual CPU structure.
525 */
526VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
527{
528 int rc;
529 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
530 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
531
532 /* Notify the support driver prior to loading the guest-FPU register state. */
533 SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
534 /** @todo use return value? Currently skipping that to be on the safe side
535 * wrt. extended state (linux). */
536
537 if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
538 {
539 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
540 rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
541 }
542 else
543 {
544 Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) || (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
545 /** @todo r=ramshankar: Can't we used a cached value here
546 * instead of reading the MSR? host EFER doesn't usually
547 * change. */
548 uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
549 if (!(uHostEfer & MSR_K6_EFER_FFXSR))
550 rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
551 else
552 {
553 RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
554 pVCpu->cpum.s.fUseFlags |= CPUM_USED_MANUAL_XMM_RESTORE;
555 ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
556 rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
557 ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
558 ASMSetFlags(uSavedFlags);
559 }
560 }
561 Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_FPU_SINCE_REM))
562 == (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_FPU_SINCE_REM));
563 Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
564 return rc;
565}
566
567
568/**
569 * Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
570 * needed.
571 *
572 * @returns true if we saved the guest state.
573 * @param pVCpu The cross context virtual CPU structure.
574 */
575VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
576{
577 bool fSavedGuest;
578 Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
579 Assert(ASMGetCR4() & X86_CR4_OSFXSR);
580 if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST))
581 {
582 fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
583 Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
584 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
585 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
586 else
587 {
588 /* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
589 save/restore the XMM state with fxsave/fxrstor. */
590 uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
591 if (uHostEfer & MSR_K6_EFER_FFXSR)
592 {
593 RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
594 ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
595 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
596 ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
597 ASMSetFlags(uSavedFlags);
598 }
599 else
600 cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
601 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
602 }
603
604 /* Notify the support driver after loading the host-FPU register state. */
605 SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
606 }
607 else
608 fSavedGuest = false;
609 Assert(!( pVCpu->cpum.s.fUseFlags
610 & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_MANUAL_XMM_RESTORE)));
611 Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
612 return fSavedGuest;
613}
614
615
616/**
617 * Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
618 * DR7 with safe values.
619 *
620 * @returns VBox status code.
621 * @param pVCpu The cross context virtual CPU structure.
622 */
623static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
624{
625 /*
626 * Save the host state.
627 */
628 pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
629 pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
630 pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
631 pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
632 pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
633 /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
634 pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
635
636 /* Preemption paranoia. */
637 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
638
639 /*
640 * Make sure DR7 is harmless or else we could trigger breakpoints when
641 * load guest or hypervisor DRx values later.
642 */
643 if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
644 ASMSetDR7(X86_DR7_INIT_VAL);
645
646 return VINF_SUCCESS;
647}
648
649
650/**
651 * Saves the guest DRx state residing in host registers and restore the host
652 * register values.
653 *
654 * The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
655 * since it's assumed that we're shadowing the guest DRx register values
656 * accurately when using the combined hypervisor debug register values
657 * (CPUMR0LoadHyperDebugState).
658 *
659 * @returns true if either guest or hypervisor debug registers were loaded.
660 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
661 * @param fDr6 Whether to include DR6 or not.
662 * @thread EMT(pVCpu)
663 */
664VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
665{
666 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
667 bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
668
669 /*
670 * Do we need to save the guest DRx registered loaded into host registers?
671 * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
672 */
673 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
674 {
675 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
676 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
677 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
678 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
679 if (fDr6)
680 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6() | X86_DR6_RA1_MASK; /* ASSUMES no guest supprot for TSX-NI / RTM. */
681 }
682 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
683
684 /*
685 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
686 */
687 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
688 {
689 /* A bit of paranoia first... */
690 uint64_t uCurDR7 = ASMGetDR7();
691 if (uCurDR7 != X86_DR7_INIT_VAL)
692 ASMSetDR7(X86_DR7_INIT_VAL);
693
694 ASMSetDR0(pVCpu->cpum.s.Host.dr0);
695 ASMSetDR1(pVCpu->cpum.s.Host.dr1);
696 ASMSetDR2(pVCpu->cpum.s.Host.dr2);
697 ASMSetDR3(pVCpu->cpum.s.Host.dr3);
698 /** @todo consider only updating if they differ, esp. DR6. Need to figure how
699 * expensive DRx reads are over DRx writes. */
700 ASMSetDR6(pVCpu->cpum.s.Host.dr6);
701 ASMSetDR7(pVCpu->cpum.s.Host.dr7);
702
703 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
704 }
705
706 return fDrXLoaded;
707}
708
709
710/**
711 * Saves the guest DRx state if it resides host registers.
712 *
713 * This does NOT clear any use flags, so the host registers remains loaded with
714 * the guest DRx state upon return. The purpose is only to make sure the values
715 * in the CPU context structure is up to date.
716 *
717 * @returns true if the host registers contains guest values, false if not.
718 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
719 * @param fDr6 Whether to include DR6 or not.
720 * @thread EMT(pVCpu)
721 */
722VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
723{
724 /*
725 * Do we need to save the guest DRx registered loaded into host registers?
726 * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
727 */
728 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
729 {
730 pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
731 pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
732 pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
733 pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
734 if (fDr6)
735 pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
736 return true;
737 }
738 return false;
739}
740
741
742/**
743 * Lazily sync in the debug state.
744 *
745 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
746 * @param fDr6 Whether to include DR6 or not.
747 * @thread EMT(pVCpu)
748 */
749VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
750{
751 /*
752 * Save the host state and disarm all host BPs.
753 */
754 cpumR0SaveHostDebugState(pVCpu);
755 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
756
757 /*
758 * Activate the guest state DR0-3.
759 * DR7 and DR6 (if fDr6 is true) are left to the caller.
760 */
761 ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
762 ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
763 ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
764 ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
765 if (fDr6)
766 ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
767
768 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
769}
770
771
772/**
773 * Lazily sync in the hypervisor debug state
774 *
775 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
776 * @param fDr6 Whether to include DR6 or not.
777 * @thread EMT(pVCpu)
778 */
779VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
780{
781 /*
782 * Save the host state and disarm all host BPs.
783 */
784 cpumR0SaveHostDebugState(pVCpu);
785 Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
786
787 /*
788 * Make sure the hypervisor values are up to date.
789 */
790 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
791
792 /*
793 * Activate the guest state DR0-3.
794 * DR7 and DR6 (if fDr6 is true) are left to the caller.
795 */
796 ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
797 ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
798 ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
799 ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
800 if (fDr6)
801 ASMSetDR6(X86_DR6_INIT_VAL);
802
803 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
804}
805
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