[23] | 1 | /* $Id: CPUMR0.cpp 99739 2023-05-11 01:01:08Z vboxsync $ */
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[1] | 2 | /** @file
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| 3 | * CPUM - Host Context Ring 0.
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[1] | 26 | */
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| 27 |
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| 28 |
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[57358] | 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[1] | 32 | #define LOG_GROUP LOG_GROUP_CPUM
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[94931] | 33 | #define CPUM_WITH_NONCONST_HOST_FEATURES
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[35346] | 34 | #include <VBox/vmm/cpum.h>
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[94931] | 35 | #include <VBox/vmm/hm.h>
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[1] | 36 | #include "CPUMInternal.h"
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[80274] | 37 | #include <VBox/vmm/vmcc.h>
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[78431] | 38 | #include <VBox/vmm/gvm.h>
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[1] | 39 | #include <VBox/err.h>
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| 40 | #include <VBox/log.h>
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[43387] | 41 | #include <VBox/vmm/hm.h>
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[1] | 42 | #include <iprt/assert.h>
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[29250] | 43 | #include <iprt/asm-amd64-x86.h>
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[94933] | 44 | #include <iprt/mem.h>
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[37955] | 45 | #include <iprt/x86.h>
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[1] | 46 |
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| 47 |
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[57358] | 48 | /*********************************************************************************************************************************
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| 49 | * Global Variables *
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| 50 | *********************************************************************************************************************************/
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[94931] | 51 | /** Host CPU features. */
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| 52 | DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
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| 53 | /** Static storage for host MSRs. */
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| 54 | static CPUMMSRS g_CpumHostMsrs;
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| 55 |
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[49893] | 56 | /**
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| 57 | * CPUID bits to unify among all cores.
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| 58 | */
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| 59 | static struct
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| 60 | {
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| 61 | uint32_t uLeaf; /**< Leaf to check. */
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[54714] | 62 | uint32_t uEcx; /**< which bits in ecx to unify between CPUs. */
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| 63 | uint32_t uEdx; /**< which bits in edx to unify between CPUs. */
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[49893] | 64 | }
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| 65 | const g_aCpuidUnifyBits[] =
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| 66 | {
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| 67 | {
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| 68 | 0x00000001,
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| 69 | X86_CPUID_FEATURE_ECX_CX16 | X86_CPUID_FEATURE_ECX_MONITOR,
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| 70 | X86_CPUID_FEATURE_EDX_CX8
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| 71 | }
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| 72 | };
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[38868] | 73 |
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[49893] | 74 |
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| 75 |
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[57358] | 76 | /*********************************************************************************************************************************
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| 77 | * Internal Functions *
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| 78 | *********************************************************************************************************************************/
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[80274] | 79 | static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu);
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[33935] | 80 |
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| 81 |
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[1] | 82 | /**
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[94940] | 83 | * Check the CPUID features of this particular CPU and disable relevant features
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| 84 | * for the guest which do not exist on this CPU.
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| 85 | *
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| 86 | * We have seen systems where the X86_CPUID_FEATURE_ECX_MONITOR feature flag is
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| 87 | * only set on some host CPUs, see @bugref{5436}.
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| 88 | *
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| 89 | * @note This function might be called simultaneously on more than one CPU!
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| 90 | *
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| 91 | * @param idCpu The identifier for the CPU the function is called on.
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| 92 | * @param pvUser1 Leaf array.
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| 93 | * @param pvUser2 Number of leaves.
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| 94 | */
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| 95 | static DECLCALLBACK(void) cpumR0CheckCpuid(RTCPUID idCpu, void *pvUser1, void *pvUser2)
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| 96 | {
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| 97 | PCPUMCPUIDLEAF const paLeaves = (PCPUMCPUIDLEAF)pvUser1;
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| 98 | uint32_t const cLeaves = (uint32_t)(uintptr_t)pvUser2;
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| 99 | RT_NOREF(idCpu);
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| 100 |
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| 101 | for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
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| 102 | {
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| 103 | PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, g_aCpuidUnifyBits[i].uLeaf, 0);
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| 104 | if (pLeaf)
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| 105 | {
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| 106 | uint32_t uEax, uEbx, uEcx, uEdx;
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| 107 | ASMCpuIdExSlow(g_aCpuidUnifyBits[i].uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
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| 108 |
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| 109 | ASMAtomicAndU32(&pLeaf->uEcx, uEcx | ~g_aCpuidUnifyBits[i].uEcx);
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| 110 | ASMAtomicAndU32(&pLeaf->uEdx, uEdx | ~g_aCpuidUnifyBits[i].uEdx);
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| 111 | }
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| 112 | }
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| 113 | }
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| 114 |
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| 115 |
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| 116 | /**
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[33935] | 117 | * Does the Ring-0 CPU initialization once during module load.
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| 118 | * XXX Host-CPU hot-plugging?
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| 119 | */
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[47681] | 120 | VMMR0_INT_DECL(int) CPUMR0ModuleInit(void)
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[33935] | 121 | {
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[94931] | 122 | /*
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| 123 | * Query the hardware virtualization capabilities of the host CPU first.
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| 124 | */
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| 125 | uint32_t fHwCaps = 0;
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| 126 | int rc = SUPR0GetVTSupport(&fHwCaps);
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| 127 | AssertLogRelMsg(RT_SUCCESS(rc) || rc == VERR_UNSUPPORTED_CPU || rc == VERR_SVM_NO_SVM || rc == VERR_VMX_NO_VMX,
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| 128 | ("SUPR0GetHwvirtMsrs -> %Rrc\n", rc));
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| 129 | if (RT_SUCCESS(rc))
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| 130 | {
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| 131 | SUPHWVIRTMSRS HwvirtMsrs;
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| 132 | rc = SUPR0GetHwvirtMsrs(&HwvirtMsrs, fHwCaps, false /*fIgnored*/);
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| 133 | AssertLogRelRC(rc);
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| 134 | if (RT_SUCCESS(rc))
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| 135 | {
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| 136 | if (fHwCaps & SUPVTCAPS_VT_X)
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| 137 | HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.vmx);
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| 138 | else
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| 139 | HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &g_CpumHostMsrs.hwvirt.svm);
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| 140 | }
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| 141 | }
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| 142 |
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| 143 | /*
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| 144 | * Collect CPUID leaves.
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| 145 | */
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| 146 | PCPUMCPUIDLEAF paLeaves;
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| 147 | uint32_t cLeaves;
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| 148 | rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
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| 149 | AssertLogRelRCReturn(rc, rc);
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| 150 |
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| 151 | /*
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[94940] | 152 | * Unify/cross check some CPUID feature bits on all available CPU cores
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| 153 | * and threads. We've seen CPUs where the monitor support differed.
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| 154 | */
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| 155 | RTMpOnAll(cpumR0CheckCpuid, paLeaves, (void *)(uintptr_t)cLeaves);
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| 156 |
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| 157 | /*
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[94931] | 158 | * Populate the host CPU feature global variable.
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| 159 | */
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| 160 | rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &g_CpumHostMsrs, &g_CpumHostFeatures.s);
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| 161 | RTMemFree(paLeaves);
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| 162 | AssertLogRelRCReturn(rc, rc);
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| 163 |
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[94940] | 164 | /*
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| 165 | * Get MSR_IA32_ARCH_CAPABILITIES and expand it into the host feature structure.
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| 166 | */
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| 167 | if (ASMHasCpuId())
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| 168 | {
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| 169 | /** @todo Should add this MSR to CPUMMSRS and expose it via SUPDrv... */
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| 170 | g_CpumHostFeatures.s.fArchRdclNo = 0;
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| 171 | g_CpumHostFeatures.s.fArchIbrsAll = 0;
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| 172 | g_CpumHostFeatures.s.fArchRsbOverride = 0;
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| 173 | g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = 0;
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| 174 | g_CpumHostFeatures.s.fArchMdsNo = 0;
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| 175 | uint32_t const cStdRange = ASMCpuId_EAX(0);
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| 176 | if ( RTX86IsValidStdRange(cStdRange)
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| 177 | && cStdRange >= 7)
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| 178 | {
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| 179 | uint32_t const fStdFeaturesEdx = ASMCpuId_EDX(1);
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| 180 | uint32_t fStdExtFeaturesEdx;
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| 181 | ASMCpuIdExSlow(7, 0, 0, 0, NULL, NULL, NULL, &fStdExtFeaturesEdx);
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| 182 | if ( (fStdExtFeaturesEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
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| 183 | && (fStdFeaturesEdx & X86_CPUID_FEATURE_EDX_MSR))
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| 184 | {
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| 185 | uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
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| 186 | g_CpumHostFeatures.s.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
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| 187 | g_CpumHostFeatures.s.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
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| 188 | g_CpumHostFeatures.s.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
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| 189 | g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
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| 190 | g_CpumHostFeatures.s.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
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| 191 | }
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| 192 | else
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| 193 | g_CpumHostFeatures.s.fArchCap = 0;
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| 194 | }
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| 195 | }
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| 196 |
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[94931] | 197 | return VINF_SUCCESS;
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[33935] | 198 | }
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| 199 |
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| 200 |
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| 201 | /**
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| 202 | * Terminate the module.
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| 203 | */
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[47681] | 204 | VMMR0_INT_DECL(int) CPUMR0ModuleTerm(void)
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[33935] | 205 | {
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| 206 | return VINF_SUCCESS;
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| 207 | }
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| 208 |
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| 209 |
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| 210 | /**
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[94943] | 211 | * Initializes the CPUM data in the VM structure.
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| 212 | *
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| 213 | * @param pGVM The global VM structure.
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| 214 | */
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| 215 | VMMR0_INT_DECL(void) CPUMR0InitPerVMData(PGVM pGVM)
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| 216 | {
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| 217 | /* Copy the ring-0 host feature set to the shared part so ring-3 can pick it up. */
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| 218 | pGVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
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| 219 | }
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| 220 |
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| 221 |
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| 222 | /**
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[44076] | 223 | * Check the CPUID features of this particular CPU and disable relevant features
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| 224 | * for the guest which do not exist on this CPU. We have seen systems where the
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| 225 | * X86_CPUID_FEATURE_ECX_MONITOR feature flag is only set on some host CPUs, see
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[49019] | 226 | * @bugref{5436}.
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[44076] | 227 | *
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[44078] | 228 | * @note This function might be called simultaneously on more than one CPU!
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| 229 | *
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[44076] | 230 | * @param idCpu The identifier for the CPU the function is called on.
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| 231 | * @param pvUser1 Pointer to the VM structure.
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| 232 | * @param pvUser2 Ignored.
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| 233 | */
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[94940] | 234 | static DECLCALLBACK(void) cpumR0CheckCpuidLegacy(RTCPUID idCpu, void *pvUser1, void *pvUser2)
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[44076] | 235 | {
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[80274] | 236 | PVMCC pVM = (PVMCC)pvUser1;
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[49893] | 237 |
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[49479] | 238 | NOREF(idCpu); NOREF(pvUser2);
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[49893] | 239 | for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
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| 240 | {
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| 241 | /* Note! Cannot use cpumCpuIdGetLeaf from here because we're not
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| 242 | necessarily in the VM process context. So, we using the
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| 243 | legacy arrays as temporary storage. */
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[49479] | 244 |
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[49893] | 245 | uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
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| 246 | PCPUMCPUID pLegacyLeaf;
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[54674] | 247 | if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
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| 248 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
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| 249 | else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
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| 250 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
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| 251 | else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
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| 252 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
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[49893] | 253 | else
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| 254 | continue;
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| 255 |
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[44076] | 256 | uint32_t eax, ebx, ecx, edx;
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[49893] | 257 | ASMCpuIdExSlow(uLeaf, 0, 0, 0, &eax, &ebx, &ecx, &edx);
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[44076] | 258 |
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[54714] | 259 | ASMAtomicAndU32(&pLegacyLeaf->uEcx, ecx | ~g_aCpuidUnifyBits[i].uEcx);
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| 260 | ASMAtomicAndU32(&pLegacyLeaf->uEdx, edx | ~g_aCpuidUnifyBits[i].uEdx);
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[44076] | 261 | }
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| 262 | }
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| 263 |
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| 264 |
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| 265 | /**
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[1] | 266 | * Does Ring-0 CPUM initialization.
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| 267 | *
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| 268 | * This is mainly to check that the Host CPU mode is compatible
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| 269 | * with VBox.
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| 270 | *
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| 271 | * @returns VBox status code.
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[58122] | 272 | * @param pVM The cross context VM structure.
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[1] | 273 | */
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[80274] | 274 | VMMR0_INT_DECL(int) CPUMR0InitVM(PVMCC pVM)
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[1] | 275 | {
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[5953] | 276 | LogFlow(("CPUMR0Init: %p\n", pVM));
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[91283] | 277 | AssertCompile(sizeof(pVM->aCpus[0].cpum.s.Host.abXState) >= sizeof(pVM->aCpus[0].cpum.s.Guest.abXState));
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[1] | 278 |
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| 279 | /*
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| 280 | * Check CR0 & CR4 flags.
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| 281 | */
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[12657] | 282 | uint32_t u32CR0 = ASMGetCR0();
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[1] | 283 | if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
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| 284 | {
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[5953] | 285 | Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
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[1] | 286 | return VERR_UNSUPPORTED_CPU_MODE;
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| 287 | }
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| 288 |
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| 289 | /*
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[21942] | 290 | * Check for sysenter and syscall usage.
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[1] | 291 | */
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| 292 | if (ASMHasCpuId())
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| 293 | {
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[21942] | 294 | /*
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| 295 | * SYSENTER/SYSEXIT
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| 296 | *
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| 297 | * Intel docs claim you should test both the flag and family, model &
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| 298 | * stepping because some Pentium Pro CPUs have the SEP cpuid flag set,
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| 299 | * but don't support it. AMD CPUs may support this feature in legacy
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| 300 | * mode, they've banned it from long mode. Since we switch to 32-bit
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| 301 | * mode when entering raw-mode context the feature would become
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| 302 | * accessible again on AMD CPUs, so we have to check regardless of
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| 303 | * host bitness.
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| 304 | */
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[1] | 305 | uint32_t u32CpuVersion;
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| 306 | uint32_t u32Dummy;
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[76678] | 307 | uint32_t fFeatures; /* (Used further down to check for MSRs, so don't clobber.) */
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[21942] | 308 | ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &fFeatures);
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[48683] | 309 | uint32_t const u32Family = u32CpuVersion >> 8;
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| 310 | uint32_t const u32Model = (u32CpuVersion >> 4) & 0xF;
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| 311 | uint32_t const u32Stepping = u32CpuVersion & 0xF;
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[21942] | 312 | if ( (fFeatures & X86_CPUID_FEATURE_EDX_SEP)
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| 313 | && ( u32Family != 6 /* (> pentium pro) */
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| 314 | || u32Model >= 3
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| 315 | || u32Stepping >= 3
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| 316 | || !ASMIsIntelCpu())
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| 317 | )
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[1] | 318 | {
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| 319 | /*
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| 320 | * Read the MSR and see if it's in use or not.
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| 321 | */
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[13960] | 322 | uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
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[1] | 323 | if (u32)
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| 324 | {
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[21937] | 325 | pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSENTER;
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[5953] | 326 | Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
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[1] | 327 | }
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| 328 | }
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| 329 |
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[21942] | 330 | /*
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| 331 | * SYSCALL/SYSRET
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| 332 | *
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| 333 | * This feature is indicated by the SEP bit returned in EDX by CPUID
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| 334 | * function 0x80000001. Intel CPUs only supports this feature in
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| 335 | * long mode. Since we're not running 64-bit guests in raw-mode there
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| 336 | * are no issues with 32-bit intel hosts.
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| 337 | */
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| 338 | uint32_t cExt = 0;
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| 339 | ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
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[93515] | 340 | if (RTX86IsValidExtRange(cExt))
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[21942] | 341 | {
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| 342 | uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
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[42024] | 343 | if (fExtFeaturesEDX & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
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[21942] | 344 | {
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| 345 | #ifdef RT_ARCH_X86
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| 346 | if (!ASMIsIntelCpu())
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| 347 | #endif
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| 348 | {
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| 349 | uint64_t fEfer = ASMRdMsr(MSR_K6_EFER);
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| 350 | if (fEfer & MSR_K6_EFER_SCE)
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| 351 | {
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| 352 | pVM->cpum.s.fHostUseFlags |= CPUM_USE_SYSCALL;
|
---|
| 353 | Log(("CPUMR0Init: host uses syscall\n"));
|
---|
| 354 | }
|
---|
| 355 | }
|
---|
| 356 | }
|
---|
| 357 | }
|
---|
[44076] | 358 |
|
---|
[49893] | 359 | /*
|
---|
[78632] | 360 | * Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
|
---|
| 361 | * structure and as well as the guest MSR.
|
---|
[82577] | 362 | * Note! we assume this happens after the CPUMR3Init is done, so CPUID bits are settled.
|
---|
[76678] | 363 | */
|
---|
| 364 | pVM->cpum.s.HostFeatures.fArchRdclNo = 0;
|
---|
| 365 | pVM->cpum.s.HostFeatures.fArchIbrsAll = 0;
|
---|
| 366 | pVM->cpum.s.HostFeatures.fArchRsbOverride = 0;
|
---|
| 367 | pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
|
---|
[78632] | 368 | pVM->cpum.s.HostFeatures.fArchMdsNo = 0;
|
---|
[76678] | 369 | uint32_t const cStdRange = ASMCpuId_EAX(0);
|
---|
[93515] | 370 | if ( RTX86IsValidStdRange(cStdRange)
|
---|
[76678] | 371 | && cStdRange >= 7)
|
---|
| 372 | {
|
---|
| 373 | uint32_t fEdxFeatures = ASMCpuId_EDX(7);
|
---|
| 374 | if ( (fEdxFeatures & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
|
---|
| 375 | && (fFeatures & X86_CPUID_FEATURE_EDX_MSR))
|
---|
| 376 | {
|
---|
[82577] | 377 | /* Host: */
|
---|
| 378 | uint64_t fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
|
---|
| 379 | pVM->cpum.s.HostFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
|
---|
| 380 | pVM->cpum.s.HostFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
|
---|
| 381 | pVM->cpum.s.HostFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
|
---|
| 382 | pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
|
---|
| 383 | pVM->cpum.s.HostFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
|
---|
[78632] | 384 |
|
---|
[82577] | 385 | /* guest: */
|
---|
| 386 | if (!pVM->cpum.s.GuestFeatures.fArchCap)
|
---|
| 387 | fArchVal = 0;
|
---|
| 388 | else if (!pVM->cpum.s.GuestFeatures.fIbrs)
|
---|
| 389 | fArchVal &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL;
|
---|
| 390 | VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = fArchVal);
|
---|
| 391 | pVM->cpum.s.GuestFeatures.fArchRdclNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
|
---|
| 392 | pVM->cpum.s.GuestFeatures.fArchIbrsAll = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
|
---|
| 393 | pVM->cpum.s.GuestFeatures.fArchRsbOverride = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
|
---|
| 394 | pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
|
---|
| 395 | pVM->cpum.s.GuestFeatures.fArchMdsNo = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
|
---|
[76678] | 396 | }
|
---|
| 397 | else
|
---|
| 398 | pVM->cpum.s.HostFeatures.fArchCap = 0;
|
---|
| 399 | }
|
---|
| 400 |
|
---|
| 401 | /*
|
---|
[49893] | 402 | * Unify/cross check some CPUID feature bits on all available CPU cores
|
---|
| 403 | * and threads. We've seen CPUs where the monitor support differed.
|
---|
| 404 | *
|
---|
| 405 | * Because the hyper heap isn't always mapped into ring-0, we cannot
|
---|
| 406 | * access it from a RTMpOnAll callback. We use the legacy CPUID arrays
|
---|
| 407 | * as temp ring-0 accessible memory instead, ASSUMING that they're all
|
---|
| 408 | * up to date when we get here.
|
---|
| 409 | */
|
---|
[94940] | 410 | RTMpOnAll(cpumR0CheckCpuidLegacy, pVM, NULL);
|
---|
[49893] | 411 |
|
---|
| 412 | for (uint32_t i = 0; i < RT_ELEMENTS(g_aCpuidUnifyBits); i++)
|
---|
| 413 | {
|
---|
[54737] | 414 | bool fIgnored;
|
---|
[49893] | 415 | uint32_t uLeaf = g_aCpuidUnifyBits[i].uLeaf;
|
---|
[54737] | 416 | PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafEx(pVM, uLeaf, 0, &fIgnored);
|
---|
[49893] | 417 | if (pLeaf)
|
---|
| 418 | {
|
---|
| 419 | PCPUMCPUID pLegacyLeaf;
|
---|
[54674] | 420 | if (uLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
|
---|
| 421 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmStd[uLeaf];
|
---|
| 422 | else if (uLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
|
---|
| 423 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmExt[uLeaf - UINT32_C(0x80000000)];
|
---|
| 424 | else if (uLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
|
---|
| 425 | pLegacyLeaf = &pVM->cpum.s.aGuestCpuIdPatmCentaur[uLeaf - UINT32_C(0xc0000000)];
|
---|
[49893] | 426 | else
|
---|
| 427 | continue;
|
---|
| 428 |
|
---|
[54714] | 429 | pLeaf->uEcx = pLegacyLeaf->uEcx;
|
---|
| 430 | pLeaf->uEdx = pLegacyLeaf->uEdx;
|
---|
[49893] | 431 | }
|
---|
| 432 | }
|
---|
| 433 |
|
---|
[1] | 434 | }
|
---|
| 435 |
|
---|
| 436 |
|
---|
| 437 | /*
|
---|
| 438 | * Check if debug registers are armed.
|
---|
[12227] | 439 | * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
|
---|
[1] | 440 | */
|
---|
[12657] | 441 | uint32_t u32DR7 = ASMGetDR7();
|
---|
[1] | 442 | if (u32DR7 & X86_DR7_ENABLED_MASK)
|
---|
| 443 | {
|
---|
[80274] | 444 | VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST);
|
---|
[5953] | 445 | Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
|
---|
[1] | 446 | }
|
---|
| 447 |
|
---|
| 448 | return VINF_SUCCESS;
|
---|
| 449 | }
|
---|
| 450 |
|
---|
| 451 |
|
---|
[10630] | 452 | /**
|
---|
[58116] | 453 | * Trap handler for device-not-available fault (\#NM).
|
---|
[49019] | 454 | * Device not available, FP or (F)WAIT instruction.
|
---|
[10630] | 455 | *
|
---|
| 456 | * @returns VBox status code.
|
---|
[48545] | 457 | * @retval VINF_SUCCESS if the guest FPU state is loaded.
|
---|
| 458 | * @retval VINF_EM_RAW_GUEST_TRAP if it is a guest trap.
|
---|
[61317] | 459 | * @retval VINF_CPUM_HOST_CR0_MODIFIED if we modified the host CR0.
|
---|
[48545] | 460 | *
|
---|
[58122] | 461 | * @param pVM The cross context VM structure.
|
---|
[58123] | 462 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[10630] | 463 | */
|
---|
[80274] | 464 | VMMR0_INT_DECL(int) CPUMR0Trap07Handler(PVMCC pVM, PVMCPUCC pVCpu)
|
---|
[10630] | 465 | {
|
---|
[55062] | 466 | Assert(pVM->cpum.s.HostFeatures.fFxSaveRstor);
|
---|
[54862] | 467 | Assert(ASMGetCR4() & X86_CR4_OSFXSR);
|
---|
[10630] | 468 |
|
---|
| 469 | /* If the FPU state has already been loaded, then it's a guest trap. */
|
---|
[47064] | 470 | if (CPUMIsGuestFPUStateActive(pVCpu))
|
---|
[10630] | 471 | {
|
---|
[61058] | 472 | Assert( ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))
|
---|
| 473 | || ((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS | X86_CR0_EM)));
|
---|
[10630] | 474 | return VINF_EM_RAW_GUEST_TRAP;
|
---|
| 475 | }
|
---|
| 476 |
|
---|
| 477 | /*
|
---|
| 478 | * There are two basic actions:
|
---|
| 479 | * 1. Save host fpu and restore guest fpu.
|
---|
| 480 | * 2. Generate guest trap.
|
---|
| 481 | *
|
---|
| 482 | * When entering the hypervisor we'll always enable MP (for proper wait
|
---|
| 483 | * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
|
---|
| 484 | * is taken from the guest OS in order to get proper SSE handling.
|
---|
| 485 | *
|
---|
| 486 | *
|
---|
| 487 | * Actions taken depending on the guest CR0 flags:
|
---|
| 488 | *
|
---|
| 489 | * 3 2 1
|
---|
| 490 | * TS | EM | MP | FPUInstr | WAIT :: VMM Action
|
---|
| 491 | * ------------------------------------------------------------------------
|
---|
| 492 | * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
|
---|
| 493 | * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
|
---|
| 494 | * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
|
---|
| 495 | * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
|
---|
| 496 | * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
|
---|
| 497 | * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
|
---|
| 498 | * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
|
---|
| 499 | * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
|
---|
| 500 | */
|
---|
| 501 |
|
---|
[61058] | 502 | switch (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
|
---|
[10630] | 503 | {
|
---|
[12657] | 504 | case X86_CR0_MP | X86_CR0_TS:
|
---|
[47064] | 505 | case X86_CR0_MP | X86_CR0_TS | X86_CR0_EM:
|
---|
[12657] | 506 | return VINF_EM_RAW_GUEST_TRAP;
|
---|
| 507 | default:
|
---|
| 508 | break;
|
---|
[10630] | 509 | }
|
---|
[10858] | 510 |
|
---|
[61058] | 511 | return CPUMR0LoadGuestFPU(pVM, pVCpu);
|
---|
[49019] | 512 | }
|
---|
| 513 |
|
---|
| 514 |
|
---|
| 515 | /**
|
---|
[61058] | 516 | * Saves the host-FPU/XMM state (if necessary) and (always) loads the guest-FPU
|
---|
| 517 | * state into the CPU.
|
---|
[49019] | 518 | *
|
---|
[61317] | 519 | * @returns VINF_SUCCESS on success, host CR0 unmodified.
|
---|
| 520 | * @returns VINF_CPUM_HOST_CR0_MODIFIED on success when the host CR0 was
|
---|
| 521 | * modified and VT-x needs to update the value in the VMCS.
|
---|
[49019] | 522 | *
|
---|
[58122] | 523 | * @param pVM The cross context VM structure.
|
---|
[58123] | 524 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[49019] | 525 | */
|
---|
[80274] | 526 | VMMR0_INT_DECL(int) CPUMR0LoadGuestFPU(PVMCC pVM, PVMCPUCC pVCpu)
|
---|
[49019] | 527 | {
|
---|
[80064] | 528 | int rc;
|
---|
[49019] | 529 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[61058] | 530 | Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST));
|
---|
| 531 |
|
---|
[95088] | 532 | /* Notify the support driver prior to loading the guest-FPU register state. */
|
---|
[95134] | 533 | SUPR0FpuBegin(VMMR0ThreadCtxHookIsEnabled(pVCpu));
|
---|
| 534 | /** @todo use return value? Currently skipping that to be on the safe side
|
---|
| 535 | * wrt. extended state (linux). */
|
---|
[95088] | 536 |
|
---|
[80064] | 537 | if (!pVM->cpum.s.HostFeatures.fLeakyFxSR)
|
---|
[14859] | 538 | {
|
---|
[61058] | 539 | Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE));
|
---|
[80064] | 540 | rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
|
---|
[14859] | 541 | }
|
---|
| 542 | else
|
---|
| 543 | {
|
---|
[80064] | 544 | Assert(!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE) || (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_HOST));
|
---|
| 545 | /** @todo r=ramshankar: Can't we used a cached value here
|
---|
| 546 | * instead of reading the MSR? host EFER doesn't usually
|
---|
| 547 | * change. */
|
---|
| 548 | uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
|
---|
| 549 | if (!(uHostEfer & MSR_K6_EFER_FFXSR))
|
---|
[61317] | 550 | rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
|
---|
[61058] | 551 | else
|
---|
| 552 | {
|
---|
[80064] | 553 | RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
|
---|
| 554 | pVCpu->cpum.s.fUseFlags |= CPUM_USED_MANUAL_XMM_RESTORE;
|
---|
| 555 | ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
|
---|
| 556 | rc = cpumR0SaveHostRestoreGuestFPUState(&pVCpu->cpum.s);
|
---|
| 557 | ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
|
---|
| 558 | ASMSetFlags(uSavedFlags);
|
---|
[16108] | 559 | }
|
---|
[10647] | 560 | }
|
---|
[80064] | 561 | Assert( (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_FPU_SINCE_REM))
|
---|
| 562 | == (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_FPU_SINCE_REM));
|
---|
[87361] | 563 | Assert(pVCpu->cpum.s.Guest.fUsedFpuGuest);
|
---|
[61317] | 564 | return rc;
|
---|
[10630] | 565 | }
|
---|
| 566 |
|
---|
| 567 |
|
---|
| 568 | /**
|
---|
[61058] | 569 | * Saves the guest FPU/XMM state if needed, restores the host FPU/XMM state as
|
---|
| 570 | * needed.
|
---|
[10630] | 571 | *
|
---|
[61058] | 572 | * @returns true if we saved the guest state.
|
---|
[58123] | 573 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[10630] | 574 | */
|
---|
[80274] | 575 | VMMR0_INT_DECL(bool) CPUMR0FpuStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu)
|
---|
[10630] | 576 | {
|
---|
[61058] | 577 | bool fSavedGuest;
|
---|
| 578 | Assert(pVCpu->CTX_SUFF(pVM)->cpum.s.HostFeatures.fFxSaveRstor);
|
---|
[54862] | 579 | Assert(ASMGetCR4() & X86_CR4_OSFXSR);
|
---|
[61058] | 580 | if (pVCpu->cpum.s.fUseFlags & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST))
|
---|
| 581 | {
|
---|
| 582 | fSavedGuest = RT_BOOL(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_GUEST);
|
---|
[87361] | 583 | Assert(fSavedGuest == pVCpu->cpum.s.Guest.fUsedFpuGuest);
|
---|
[80052] | 584 | if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_MANUAL_XMM_RESTORE))
|
---|
| 585 | cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
|
---|
| 586 | else
|
---|
[16113] | 587 | {
|
---|
[80052] | 588 | /* Temporarily clear MSR_K6_EFER_FFXSR or else we'll be unable to
|
---|
| 589 | save/restore the XMM state with fxsave/fxrstor. */
|
---|
| 590 | uint64_t uHostEfer = ASMRdMsr(MSR_K6_EFER);
|
---|
| 591 | if (uHostEfer & MSR_K6_EFER_FFXSR)
|
---|
[61058] | 592 | {
|
---|
[80052] | 593 | RTCCUINTREG const uSavedFlags = ASMIntDisableFlags();
|
---|
| 594 | ASMWrMsr(MSR_K6_EFER, uHostEfer & ~MSR_K6_EFER_FFXSR);
|
---|
| 595 | cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
|
---|
| 596 | ASMWrMsr(MSR_K6_EFER, uHostEfer | MSR_K6_EFER_FFXSR);
|
---|
| 597 | ASMSetFlags(uSavedFlags);
|
---|
[61058] | 598 | }
|
---|
| 599 | else
|
---|
| 600 | cpumR0SaveGuestRestoreHostFPUState(&pVCpu->cpum.s);
|
---|
[80052] | 601 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_MANUAL_XMM_RESTORE;
|
---|
[14859] | 602 | }
|
---|
[95123] | 603 |
|
---|
| 604 | /* Notify the support driver after loading the host-FPU register state. */
|
---|
[95134] | 605 | SUPR0FpuEnd(VMMR0ThreadCtxHookIsEnabled(pVCpu));
|
---|
[14859] | 606 | }
|
---|
[61058] | 607 | else
|
---|
| 608 | fSavedGuest = false;
|
---|
| 609 | Assert(!( pVCpu->cpum.s.fUseFlags
|
---|
[87345] | 610 | & (CPUM_USED_FPU_GUEST | CPUM_USED_FPU_HOST | CPUM_USED_MANUAL_XMM_RESTORE)));
|
---|
[87361] | 611 | Assert(!pVCpu->cpum.s.Guest.fUsedFpuGuest);
|
---|
[61058] | 612 | return fSavedGuest;
|
---|
[10630] | 613 | }
|
---|
[12578] | 614 |
|
---|
| 615 |
|
---|
| 616 | /**
|
---|
[47660] | 617 | * Saves the host debug state, setting CPUM_USED_HOST_DEBUG_STATE and loading
|
---|
| 618 | * DR7 with safe values.
|
---|
[12578] | 619 | *
|
---|
| 620 | * @returns VBox status code.
|
---|
[58123] | 621 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[12578] | 622 | */
|
---|
[80274] | 623 | static int cpumR0SaveHostDebugState(PVMCPUCC pVCpu)
|
---|
[12578] | 624 | {
|
---|
[47660] | 625 | /*
|
---|
| 626 | * Save the host state.
|
---|
| 627 | */
|
---|
| 628 | pVCpu->cpum.s.Host.dr0 = ASMGetDR0();
|
---|
| 629 | pVCpu->cpum.s.Host.dr1 = ASMGetDR1();
|
---|
| 630 | pVCpu->cpum.s.Host.dr2 = ASMGetDR2();
|
---|
| 631 | pVCpu->cpum.s.Host.dr3 = ASMGetDR3();
|
---|
| 632 | pVCpu->cpum.s.Host.dr6 = ASMGetDR6();
|
---|
| 633 | /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
|
---|
| 634 | pVCpu->cpum.s.Host.dr7 = ASMGetDR7();
|
---|
[12578] | 635 |
|
---|
[47660] | 636 | /* Preemption paranoia. */
|
---|
| 637 | ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HOST);
|
---|
| 638 |
|
---|
[12657] | 639 | /*
|
---|
[47660] | 640 | * Make sure DR7 is harmless or else we could trigger breakpoints when
|
---|
| 641 | * load guest or hypervisor DRx values later.
|
---|
[12593] | 642 | */
|
---|
[47660] | 643 | if (pVCpu->cpum.s.Host.dr7 != X86_DR7_INIT_VAL)
|
---|
| 644 | ASMSetDR7(X86_DR7_INIT_VAL);
|
---|
| 645 |
|
---|
[12578] | 646 | return VINF_SUCCESS;
|
---|
| 647 | }
|
---|
| 648 |
|
---|
| 649 |
|
---|
| 650 | /**
|
---|
[47660] | 651 | * Saves the guest DRx state residing in host registers and restore the host
|
---|
| 652 | * register values.
|
---|
[12578] | 653 | *
|
---|
[47660] | 654 | * The guest DRx state is only saved if CPUMR0LoadGuestDebugState was called,
|
---|
| 655 | * since it's assumed that we're shadowing the guest DRx register values
|
---|
| 656 | * accurately when using the combined hypervisor debug register values
|
---|
| 657 | * (CPUMR0LoadHyperDebugState).
|
---|
| 658 | *
|
---|
| 659 | * @returns true if either guest or hypervisor debug registers were loaded.
|
---|
[58123] | 660 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[47681] | 661 | * @param fDr6 Whether to include DR6 or not.
|
---|
[47660] | 662 | * @thread EMT(pVCpu)
|
---|
[12578] | 663 | */
|
---|
[80274] | 664 | VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(PVMCPUCC pVCpu, bool fDr6)
|
---|
[12578] | 665 | {
|
---|
[49019] | 666 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[47660] | 667 | bool const fDrXLoaded = RT_BOOL(pVCpu->cpum.s.fUseFlags & (CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
|
---|
[21252] | 668 |
|
---|
[47660] | 669 | /*
|
---|
| 670 | * Do we need to save the guest DRx registered loaded into host registers?
|
---|
[47681] | 671 | * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
|
---|
[47660] | 672 | */
|
---|
| 673 | if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
|
---|
| 674 | {
|
---|
[80052] | 675 | pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
|
---|
| 676 | pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
|
---|
| 677 | pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
|
---|
| 678 | pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
|
---|
| 679 | if (fDr6)
|
---|
[97562] | 680 | pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6() | X86_DR6_RA1_MASK; /* ASSUMES no guest supprot for TSX-NI / RTM. */
|
---|
[21252] | 681 | }
|
---|
[87345] | 682 | ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~(CPUM_USED_DEBUG_REGS_GUEST | CPUM_USED_DEBUG_REGS_HYPER));
|
---|
[21252] | 683 |
|
---|
[47660] | 684 | /*
|
---|
| 685 | * Restore the host's debug state. DR0-3, DR6 and only then DR7!
|
---|
| 686 | */
|
---|
| 687 | if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_HOST)
|
---|
| 688 | {
|
---|
| 689 | /* A bit of paranoia first... */
|
---|
| 690 | uint64_t uCurDR7 = ASMGetDR7();
|
---|
| 691 | if (uCurDR7 != X86_DR7_INIT_VAL)
|
---|
| 692 | ASMSetDR7(X86_DR7_INIT_VAL);
|
---|
[21252] | 693 |
|
---|
[47660] | 694 | ASMSetDR0(pVCpu->cpum.s.Host.dr0);
|
---|
| 695 | ASMSetDR1(pVCpu->cpum.s.Host.dr1);
|
---|
| 696 | ASMSetDR2(pVCpu->cpum.s.Host.dr2);
|
---|
| 697 | ASMSetDR3(pVCpu->cpum.s.Host.dr3);
|
---|
| 698 | /** @todo consider only updating if they differ, esp. DR6. Need to figure how
|
---|
| 699 | * expensive DRx reads are over DRx writes. */
|
---|
| 700 | ASMSetDR6(pVCpu->cpum.s.Host.dr6);
|
---|
| 701 | ASMSetDR7(pVCpu->cpum.s.Host.dr7);
|
---|
[12578] | 702 |
|
---|
[47660] | 703 | ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HOST);
|
---|
| 704 | }
|
---|
| 705 |
|
---|
| 706 | return fDrXLoaded;
|
---|
[21252] | 707 | }
|
---|
| 708 |
|
---|
[47660] | 709 |
|
---|
[21252] | 710 | /**
|
---|
[47681] | 711 | * Saves the guest DRx state if it resides host registers.
|
---|
| 712 | *
|
---|
| 713 | * This does NOT clear any use flags, so the host registers remains loaded with
|
---|
| 714 | * the guest DRx state upon return. The purpose is only to make sure the values
|
---|
| 715 | * in the CPU context structure is up to date.
|
---|
| 716 | *
|
---|
| 717 | * @returns true if the host registers contains guest values, false if not.
|
---|
[58123] | 718 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[47681] | 719 | * @param fDr6 Whether to include DR6 or not.
|
---|
| 720 | * @thread EMT(pVCpu)
|
---|
| 721 | */
|
---|
[80274] | 722 | VMMR0_INT_DECL(bool) CPUMR0DebugStateMaybeSaveGuest(PVMCPUCC pVCpu, bool fDr6)
|
---|
[47681] | 723 | {
|
---|
| 724 | /*
|
---|
| 725 | * Do we need to save the guest DRx registered loaded into host registers?
|
---|
| 726 | * (DR7 and DR6 (if fDr6 is true) are left to the caller.)
|
---|
| 727 | */
|
---|
| 728 | if (pVCpu->cpum.s.fUseFlags & CPUM_USED_DEBUG_REGS_GUEST)
|
---|
| 729 | {
|
---|
[80052] | 730 | pVCpu->cpum.s.Guest.dr[0] = ASMGetDR0();
|
---|
| 731 | pVCpu->cpum.s.Guest.dr[1] = ASMGetDR1();
|
---|
| 732 | pVCpu->cpum.s.Guest.dr[2] = ASMGetDR2();
|
---|
| 733 | pVCpu->cpum.s.Guest.dr[3] = ASMGetDR3();
|
---|
| 734 | if (fDr6)
|
---|
| 735 | pVCpu->cpum.s.Guest.dr[6] = ASMGetDR6();
|
---|
[47681] | 736 | return true;
|
---|
| 737 | }
|
---|
| 738 | return false;
|
---|
| 739 | }
|
---|
| 740 |
|
---|
| 741 |
|
---|
| 742 | /**
|
---|
[47660] | 743 | * Lazily sync in the debug state.
|
---|
[21252] | 744 | *
|
---|
[58123] | 745 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[47681] | 746 | * @param fDr6 Whether to include DR6 or not.
|
---|
[47660] | 747 | * @thread EMT(pVCpu)
|
---|
[21252] | 748 | */
|
---|
[80274] | 749 | VMMR0_INT_DECL(void) CPUMR0LoadGuestDebugState(PVMCPUCC pVCpu, bool fDr6)
|
---|
[21252] | 750 | {
|
---|
[47660] | 751 | /*
|
---|
| 752 | * Save the host state and disarm all host BPs.
|
---|
| 753 | */
|
---|
| 754 | cpumR0SaveHostDebugState(pVCpu);
|
---|
| 755 | Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
|
---|
[21252] | 756 |
|
---|
| 757 | /*
|
---|
[47660] | 758 | * Activate the guest state DR0-3.
|
---|
[47681] | 759 | * DR7 and DR6 (if fDr6 is true) are left to the caller.
|
---|
[21252] | 760 | */
|
---|
[80064] | 761 | ASMSetDR0(pVCpu->cpum.s.Guest.dr[0]);
|
---|
| 762 | ASMSetDR1(pVCpu->cpum.s.Guest.dr[1]);
|
---|
| 763 | ASMSetDR2(pVCpu->cpum.s.Guest.dr[2]);
|
---|
| 764 | ASMSetDR3(pVCpu->cpum.s.Guest.dr[3]);
|
---|
| 765 | if (fDr6)
|
---|
| 766 | ASMSetDR6(pVCpu->cpum.s.Guest.dr[6]);
|
---|
[21252] | 767 |
|
---|
[80064] | 768 | ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
|
---|
[21252] | 769 | }
|
---|
| 770 |
|
---|
| 771 |
|
---|
| 772 | /**
|
---|
| 773 | * Lazily sync in the hypervisor debug state
|
---|
| 774 | *
|
---|
[58123] | 775 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
[47681] | 776 | * @param fDr6 Whether to include DR6 or not.
|
---|
[47660] | 777 | * @thread EMT(pVCpu)
|
---|
[21252] | 778 | */
|
---|
[80274] | 779 | VMMR0_INT_DECL(void) CPUMR0LoadHyperDebugState(PVMCPUCC pVCpu, bool fDr6)
|
---|
[21252] | 780 | {
|
---|
[47660] | 781 | /*
|
---|
| 782 | * Save the host state and disarm all host BPs.
|
---|
| 783 | */
|
---|
| 784 | cpumR0SaveHostDebugState(pVCpu);
|
---|
[21252] | 785 | Assert(ASMGetDR7() == X86_DR7_INIT_VAL);
|
---|
| 786 |
|
---|
[47660] | 787 | /*
|
---|
| 788 | * Make sure the hypervisor values are up to date.
|
---|
| 789 | */
|
---|
[87346] | 790 | CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
|
---|
[47660] | 791 |
|
---|
| 792 | /*
|
---|
| 793 | * Activate the guest state DR0-3.
|
---|
[47681] | 794 | * DR7 and DR6 (if fDr6 is true) are left to the caller.
|
---|
[47660] | 795 | */
|
---|
[80064] | 796 | ASMSetDR0(pVCpu->cpum.s.Hyper.dr[0]);
|
---|
| 797 | ASMSetDR1(pVCpu->cpum.s.Hyper.dr[1]);
|
---|
| 798 | ASMSetDR2(pVCpu->cpum.s.Hyper.dr[2]);
|
---|
| 799 | ASMSetDR3(pVCpu->cpum.s.Hyper.dr[3]);
|
---|
| 800 | if (fDr6)
|
---|
| 801 | ASMSetDR6(X86_DR6_INIT_VAL);
|
---|
[47660] | 802 |
|
---|
[80064] | 803 | ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
|
---|
[12578] | 804 | }
|
---|
[12657] | 805 |
|
---|