VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 43667

Last change on this file since 43667 was 42188, checked in by vboxsync, 12 years ago

VMM: Changed a few ifndef IN_RING0 to ifndef VBOX_WITH_RAW_MODE_NOT_R0.
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1/* $Id: PGMAllMap.cpp 42188 2012-07-17 13:50:51Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/em.h>
24#include "PGMInternal.h"
25#include <VBox/vmm/vm.h>
26#include "PGMInline.h"
27#include <VBox/err.h>
28#include <iprt/asm-amd64-x86.h>
29#include <iprt/assert.h>
30
31
32/**
33 * Maps a range of physical pages at a given virtual address
34 * in the guest context.
35 *
36 * The GC virtual address range must be within an existing mapping.
37 *
38 * @returns VBox status code.
39 * @param pVM The virtual machine.
40 * @param GCPtr Where to map the page(s). Must be page aligned.
41 * @param HCPhys Start of the range of physical pages. Must be page aligned.
42 * @param cbPages Number of bytes to map. Must be page aligned.
43 * @param fFlags Page flags (X86_PTE_*).
44 */
45VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
46{
47 AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
48
49 /*
50 * Validate input.
51 */
52 AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
53 AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
54 AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
55
56 /* hypervisor defaults */
57 if (!fFlags)
58 fFlags = X86_PTE_P | X86_PTE_A | X86_PTE_D;
59
60 /*
61 * Find the mapping.
62 */
63 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
64 while (pCur)
65 {
66 if (GCPtr - pCur->GCPtr < pCur->cb)
67 {
68 if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
69 {
70 AssertMsgFailed(("Invalid range!!\n"));
71 return VERR_INVALID_PARAMETER;
72 }
73
74 /*
75 * Setup PTE.
76 */
77 X86PTEPAE Pte;
78 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
79
80 /*
81 * Update the page tables.
82 */
83 for (;;)
84 {
85 RTGCUINTPTR off = GCPtr - pCur->GCPtr;
86 const unsigned iPT = off >> X86_PD_SHIFT;
87 const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
88
89 /* 32-bit */
90 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
91
92 /* pae */
93 PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
94
95 /* next */
96 cbPages -= PAGE_SIZE;
97 if (!cbPages)
98 break;
99 GCPtr += PAGE_SIZE;
100 Pte.u += PAGE_SIZE;
101 }
102
103 return VINF_SUCCESS;
104 }
105
106 /* next */
107 pCur = pCur->CTX_SUFF(pNext);
108 }
109
110 AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
111 return VERR_INVALID_PARAMETER;
112}
113
114
115/**
116 * Sets (replaces) the page flags for a range of pages in a mapping.
117 *
118 * @returns VBox status.
119 * @param pVM Pointer to the VM.
120 * @param GCPtr Virtual address of the first page in the range.
121 * @param cb Size (in bytes) of the range to apply the modification to.
122 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
123 */
124VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
125{
126 return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
127}
128
129
130/**
131 * Modify page flags for a range of pages in a mapping.
132 *
133 * The existing flags are ANDed with the fMask and ORed with the fFlags.
134 *
135 * @returns VBox status code.
136 * @param pVM Pointer to the VM.
137 * @param GCPtr Virtual address of the first page in the range.
138 * @param cb Size (in bytes) of the range to apply the modification to.
139 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
140 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
141 */
142VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
143{
144 /*
145 * Validate input.
146 */
147 AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
148 Assert(cb);
149
150 /*
151 * Align the input.
152 */
153 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
154 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
155 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
156
157 /*
158 * Find the mapping.
159 */
160 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
161 while (pCur)
162 {
163 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
164 if (off < pCur->cb)
165 {
166 AssertMsgReturn(off + cb <= pCur->cb,
167 ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
168 GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
169 VERR_INVALID_PARAMETER);
170
171 /*
172 * Perform the requested operation.
173 */
174 while (cb > 0)
175 {
176 unsigned iPT = off >> X86_PD_SHIFT;
177 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
178 while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
179 {
180 /* 32-Bit */
181 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask | X86_PTE_PG_MASK;
182 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u |= fFlags & ~X86_PTE_PG_MASK;
183
184 /* PAE */
185 PPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
186 PGMSHWPTEPAE_SET(*pPtePae,
187 ( PGMSHWPTEPAE_GET_U(*pPtePae)
188 & (fMask | X86_PTE_PAE_PG_MASK))
189 | (fFlags & ~(X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)));
190
191 /* invalidate tls */
192 PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
193
194 /* next */
195 iPTE++;
196 cb -= PAGE_SIZE;
197 off += PAGE_SIZE;
198 }
199 }
200
201 return VINF_SUCCESS;
202 }
203 /* next */
204 pCur = pCur->CTX_SUFF(pNext);
205 }
206
207 AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
208 return VERR_INVALID_PARAMETER;
209}
210
211
212/**
213 * Get information about a page in a mapping.
214 *
215 * This differs from PGMShwGetPage and PGMGstGetPage in that it only consults
216 * the page table to calculate the flags.
217 *
218 * @returns VINF_SUCCESS, VERR_PAGE_NOT_PRESENT or VERR_NOT_FOUND.
219 * @param pVM Pointer to the VM.
220 * @param GCPtr The page address.
221 * @param pfFlags Where to return the flags. Optional.
222 * @param pHCPhys Where to return the address. Optional.
223 */
224VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
225{
226 /*
227 * Find the mapping.
228 */
229 GCPtr &= PAGE_BASE_GC_MASK;
230 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
231 while (pCur)
232 {
233 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
234 if (off < pCur->cb)
235 {
236 /*
237 * Dig out the information.
238 */
239 int rc = VINF_SUCCESS;
240 unsigned iPT = off >> X86_PD_SHIFT;
241 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
242 PCPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
243 if (PGMSHWPTEPAE_IS_P(*pPtePae))
244 {
245 if (pfFlags)
246 *pfFlags = PGMSHWPTEPAE_GET_U(*pPtePae) & ~X86_PTE_PAE_PG_MASK;
247 if (pHCPhys)
248 *pHCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPtePae);
249 }
250 else
251 rc = VERR_PAGE_NOT_PRESENT;
252 return rc;
253 }
254 /* next */
255 pCur = pCur->CTX_SUFF(pNext);
256 }
257
258 return VERR_NOT_FOUND;
259}
260
261
262#ifdef VBOX_WITH_RAW_MODE_NOT_R0
263/**
264 * Sets all PDEs involved with the mapping in the shadow page table.
265 *
266 * @param pVM Pointer to the VM.
267 * @param pMap Pointer to the mapping in question.
268 * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
269 */
270void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
271{
272 Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(pVM)));
273
274 if ( !pgmMapAreMappingsEnabled(pVM)
275 || pVM->cCpus > 1)
276 return;
277
278 /* This only applies to raw mode where we only support 1 VCPU. */
279 PVMCPU pVCpu = VMMGetCpu0(pVM);
280 if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
281 return; /* too early */
282
283 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
284 Assert(enmShadowMode <= PGMMODE_PAE_NX);
285
286 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
287
288 /*
289 * Insert the page tables into the shadow page directories.
290 */
291 unsigned i = pMap->cPTs;
292 iNewPDE += i;
293 while (i-- > 0)
294 {
295 iNewPDE--;
296
297 switch (enmShadowMode)
298 {
299 case PGMMODE_32_BIT:
300 {
301 PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(pVCpu);
302 AssertFatal(pShw32BitPd);
303
304 /* Free any previous user, unless it's us. */
305 Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
306 || (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
307 if ( pShw32BitPd->a[iNewPDE].n.u1Present
308 && !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
309 pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
310
311 /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
312 pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
313 | (uint32_t)pMap->aPTs[i].HCPhysPT;
314 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShw32BitPd);
315 break;
316 }
317
318 case PGMMODE_PAE:
319 case PGMMODE_PAE_NX:
320 {
321 const uint32_t iPdPt = iNewPDE / 256;
322 unsigned iPaePde = iNewPDE * 2 % 512;
323 PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
324 Assert(pShwPdpt);
325
326 /*
327 * Get the shadow PD.
328 * If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
329 * Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
330 * accessed bit causes invalid VT-x guest state errors.
331 */
332 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
333 if (!pShwPaePd)
334 {
335 X86PDPE GstPdpe;
336 if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
337 GstPdpe.u = X86_PDPE_P;
338 else
339 {
340 PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
341 if (pGstPdpe)
342 GstPdpe = *pGstPdpe;
343 else
344 GstPdpe.u = X86_PDPE_P;
345 }
346 int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, GstPdpe.u, &pShwPaePd);
347 AssertFatalRC(rc);
348 }
349 Assert(pShwPaePd);
350
351 /*
352 * Mark the page as locked; disallow flushing.
353 */
354 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
355 AssertFatal(pPoolPagePd);
356 if (!pgmPoolIsPageLocked(pPoolPagePd))
357 pgmPoolLockPage(pPool, pPoolPagePd);
358#ifdef VBOX_STRICT
359 else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
360 {
361 Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
362 AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
363 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
364 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
365 Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
366 AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
367 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
368 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
369 }
370#endif
371
372 /*
373 * Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
374 */
375 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
376 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
377 if ( pShwPaePd->a[iPaePde].n.u1Present
378 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
379 {
380 Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
381 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK, pPoolPagePd->idx, iPaePde);
382 }
383 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
384 | pMap->aPTs[i].HCPhysPaePT0;
385
386 /* 2nd 2 MB PDE of the 4 MB region, same as above. */
387 iPaePde++;
388 AssertFatal(iPaePde < 512);
389 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
390 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
391 if ( pShwPaePd->a[iPaePde].n.u1Present
392 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
393 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
394 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
395 | pMap->aPTs[i].HCPhysPaePT1;
396
397 /*
398 * Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
399 */
400 pShwPdpt->a[iPdPt].u |= PGM_PLXFLAGS_MAPPING;
401
402 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPaePd);
403 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPdpt);
404 break;
405 }
406
407 default:
408 AssertFailed();
409 break;
410 }
411 }
412}
413
414
415/**
416 * Clears all PDEs involved with the mapping in the shadow page table.
417 *
418 * @param pVM Pointer to the VM.
419 * @param pShwPageCR3 CR3 root page
420 * @param pMap Pointer to the mapping in question.
421 * @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
422 * @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
423 */
424void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
425{
426 Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(pVM), fDeactivateCR3));
427
428 /*
429 * Skip this if disabled or if it doesn't apply.
430 */
431 if ( !pgmMapAreMappingsEnabled(pVM)
432 || pVM->cCpus > 1)
433 return;
434
435 Assert(pShwPageCR3);
436
437 /* This only applies to raw mode where we only support 1 VCPU. */
438 PVMCPU pVCpu = VMMGetCpu0(pVM);
439# ifdef IN_RC
440 Assert(pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
441# endif
442
443 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
444
445 PX86PDPT pCurrentShwPdpt = NULL;
446 if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
447 && pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
448 pCurrentShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
449
450 unsigned i = pMap->cPTs;
451 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
452
453 iOldPDE += i;
454 while (i-- > 0)
455 {
456 iOldPDE--;
457
458 switch(enmShadowMode)
459 {
460 case PGMMODE_32_BIT:
461 {
462 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
463 AssertFatal(pShw32BitPd);
464
465 Assert(!pShw32BitPd->a[iOldPDE].n.u1Present || (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
466 pShw32BitPd->a[iOldPDE].u = 0;
467 break;
468 }
469
470 case PGMMODE_PAE:
471 case PGMMODE_PAE_NX:
472 {
473 const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
474 unsigned iPaePde = iOldPDE * 2 % 512;
475 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
476 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
477
478 /*
479 * Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
480 */
481 if (fDeactivateCR3)
482 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
483 else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
484 {
485 /* See if there are any other mappings here. This is suboptimal code. */
486 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
487 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
488 if ( pCur != pMap
489 && ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
490 || (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
491 {
492 pShwPdpt->a[iPdpt].u |= PGM_PLXFLAGS_MAPPING;
493 break;
494 }
495 }
496
497 /*
498 * If the page directory of the old CR3 is reused in the new one, then don't
499 * clear the hypervisor mappings.
500 */
501 if ( pCurrentShwPdpt
502 && (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
503 {
504 LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
505 break;
506 }
507
508 /*
509 * Clear the mappings in the PD.
510 */
511 AssertFatal(pShwPaePd);
512 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
513 pShwPaePd->a[iPaePde].u = 0;
514
515 iPaePde++;
516 AssertFatal(iPaePde < 512);
517 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
518 pShwPaePd->a[iPaePde].u = 0;
519
520 /*
521 * Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
522 */
523 if ( fDeactivateCR3
524 || !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
525 {
526 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
527 AssertFatal(pPoolPagePd);
528 if (pgmPoolIsPageLocked(pPoolPagePd))
529 pgmPoolUnlockPage(pPool, pPoolPagePd);
530 }
531 break;
532 }
533
534 default:
535 AssertFailed();
536 break;
537 }
538 }
539
540 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pCurrentShwPdpt);
541}
542#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
543
544#if defined(VBOX_STRICT) && !defined(IN_RING0)
545/**
546 * Clears all PDEs involved with the mapping in the shadow page table.
547 *
548 * @param pVM Pointer to the VM.
549 * @param pVCpu Pointer to the VMCPU.
550 * @param pShwPageCR3 CR3 root page
551 * @param pMap Pointer to the mapping in question.
552 * @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
553 */
554static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
555{
556 Assert(pShwPageCR3);
557
558 uint32_t i = pMap->cPTs;
559 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
560 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
561
562 iPDE += i;
563 while (i-- > 0)
564 {
565 iPDE--;
566
567 switch (enmShadowMode)
568 {
569 case PGMMODE_32_BIT:
570 {
571 PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
572 AssertFatal(pShw32BitPd);
573
574 AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
575 ("Expected %x vs %x; iPDE=%#x %RGv %s\n",
576 pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
577 iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
578 break;
579 }
580
581 case PGMMODE_PAE:
582 case PGMMODE_PAE_NX:
583 {
584 const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
585 unsigned iPaePDE = iPDE * 2 % 512;
586 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
587 PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
588 AssertFatal(pShwPaePd);
589
590 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
591 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
592 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
593 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
594
595 iPaePDE++;
596 AssertFatal(iPaePDE < 512);
597
598 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
599 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
600 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
601 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
602
603 AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
604 ("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
605 pShwPdpt->a[iPdpt].u,
606 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
607
608 PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
609 AssertFatal(pPoolPagePd);
610 AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
611 break;
612 }
613
614 default:
615 AssertFailed();
616 break;
617 }
618 }
619}
620
621
622/**
623 * Check the hypervisor mappings in the active CR3.
624 *
625 * @param pVM The virtual machine.
626 */
627VMMDECL(void) PGMMapCheck(PVM pVM)
628{
629 /*
630 * Can skip this if mappings are disabled.
631 */
632 if (!pgmMapAreMappingsEnabled(pVM))
633 return;
634
635 /* This only applies to raw mode where we only support 1 VCPU. */
636 Assert(pVM->cCpus == 1);
637 PVMCPU pVCpu = VMMGetCpu0(pVM);
638 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
639
640 /*
641 * Iterate mappings.
642 */
643 pgmLock(pVM); /* to avoid assertions */
644 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
645 {
646 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
647 pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
648 }
649 pgmUnlock(pVM);
650}
651#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
652
653#ifdef VBOX_WITH_RAW_MODE_NOT_R0
654
655/**
656 * Apply the hypervisor mappings to the active CR3.
657 *
658 * @returns VBox status.
659 * @param pVM The virtual machine.
660 * @param pShwPageCR3 CR3 root page
661 */
662int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
663{
664 /*
665 * Skip this if disabled or if it doesn't apply.
666 */
667 if ( !pgmMapAreMappingsEnabled(pVM)
668 || pVM->cCpus > 1)
669 return VINF_SUCCESS;
670
671 /* Note! This might not be logged successfully in RC because we usually
672 cannot flush the log at this point. */
673 Log4(("pgmMapActivateCR3: fixed mappings=%RTbool idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
674
675#ifdef VBOX_STRICT
676 PVMCPU pVCpu = VMMGetCpu0(pVM);
677 Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
678#endif
679
680 /*
681 * Iterate mappings.
682 */
683 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
684 {
685 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
686 pgmMapSetShadowPDEs(pVM, pCur, iPDE);
687 }
688 return VINF_SUCCESS;
689}
690
691
692/**
693 * Remove the hypervisor mappings from the specified CR3
694 *
695 * @returns VBox status.
696 * @param pVM The virtual machine.
697 * @param pShwPageCR3 CR3 root page
698 */
699int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
700{
701 /*
702 * Skip this if disabled or if it doesn't apply.
703 */
704 if ( !pgmMapAreMappingsEnabled(pVM)
705 || pVM->cCpus > 1)
706 return VINF_SUCCESS;
707
708 Assert(pShwPageCR3);
709 Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
710
711 /*
712 * Iterate mappings.
713 */
714 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
715 {
716 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
717 pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /*fDeactivateCR3*/);
718 }
719 return VINF_SUCCESS;
720}
721
722
723/**
724 * Checks guest PD for conflicts with VMM GC mappings.
725 *
726 * @returns true if conflict detected.
727 * @returns false if not.
728 * @param pVM The virtual machine.
729 */
730VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
731{
732 /*
733 * Can skip this if mappings are safely fixed.
734 */
735 if (!pgmMapAreMappingsFloating(pVM))
736 return false;
737
738 Assert(pVM->cCpus == 1);
739
740 /* This only applies to raw mode where we only support 1 VCPU. */
741 PVMCPU pVCpu = &pVM->aCpus[0];
742
743 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
744 Assert(enmGuestMode <= PGMMODE_PAE_NX);
745
746 /*
747 * Iterate mappings.
748 */
749 if (enmGuestMode == PGMMODE_32_BIT)
750 {
751 /*
752 * Resolve the page directory.
753 */
754 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
755 Assert(pPD);
756
757 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
758 {
759 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
760 unsigned iPT = pCur->cPTs;
761 while (iPT-- > 0)
762 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
763 && (EMIsRawRing0Enabled(pVM) || pPD->a[iPDE + iPT].n.u1User))
764 {
765 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
766
767#ifdef IN_RING3
768 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
769 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
770 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
771 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
772#else
773 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
774 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
775 (iPT + iPDE) << X86_PD_SHIFT,
776 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
777#endif
778 return true;
779 }
780 }
781 }
782 else if ( enmGuestMode == PGMMODE_PAE
783 || enmGuestMode == PGMMODE_PAE_NX)
784 {
785 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
786 {
787 RTGCPTR GCPtr = pCur->GCPtr;
788
789 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
790 while (iPT-- > 0)
791 {
792 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
793
794 if ( Pde.n.u1Present
795 && (EMIsRawRing0Enabled(pVM) || Pde.n.u1User))
796 {
797 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
798#ifdef IN_RING3
799 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
800 " PDE=%016RX64.\n",
801 GCPtr, pCur->pszDesc, Pde.u));
802#else
803 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
804 " PDE=%016RX64.\n",
805 GCPtr, Pde.u));
806#endif
807 return true;
808 }
809 GCPtr += (1 << X86_PD_PAE_SHIFT);
810 }
811 }
812 }
813 else
814 AssertFailed();
815
816 return false;
817}
818
819
820/**
821 * Checks and resolves (ring 3 only) guest conflicts with the guest mappings.
822 *
823 * @returns VBox status.
824 * @param pVM The virtual machine.
825 */
826int pgmMapResolveConflicts(PVM pVM)
827{
828 /* The caller is expected to check these two conditions. */
829 Assert(!pVM->pgm.s.fMappingsFixed);
830 Assert(!pVM->pgm.s.fMappingsDisabled);
831
832 /* This only applies to raw mode where we only support 1 VCPU. */
833 Assert(pVM->cCpus == 1);
834 PVMCPU pVCpu = &pVM->aCpus[0];
835 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
836 Assert(enmGuestMode <= PGMMODE_PAE_NX);
837
838 if (enmGuestMode == PGMMODE_32_BIT)
839 {
840 /*
841 * Resolve the page directory.
842 */
843 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
844 Assert(pPD);
845
846 /*
847 * Iterate mappings.
848 */
849 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
850 {
851 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
852 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
853 unsigned iPT = pCur->cPTs;
854 while (iPT-- > 0)
855 {
856 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
857 && ( EMIsRawRing0Enabled(pVM)
858 || pPD->a[iPDE + iPT].n.u1User))
859 {
860 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
861
862#ifdef IN_RING3
863 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
864 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
865 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
866 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
867 int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
868 AssertRCReturn(rc, rc);
869 break;
870#else
871 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
872 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
873 (iPT + iPDE) << X86_PD_SHIFT,
874 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
875 return VINF_PGM_SYNC_CR3;
876#endif
877 }
878 }
879 pCur = pNext;
880 }
881 }
882 else if ( enmGuestMode == PGMMODE_PAE
883 || enmGuestMode == PGMMODE_PAE_NX)
884 {
885 /*
886 * Iterate mappings.
887 */
888 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
889 {
890 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
891 RTGCPTR GCPtr = pCur->GCPtr;
892 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
893 while (iPT-- > 0)
894 {
895 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
896
897 if ( Pde.n.u1Present
898 && (EMIsRawRing0Enabled(pVM) || Pde.n.u1User))
899 {
900 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
901#ifdef IN_RING3
902 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
903 " PDE=%016RX64.\n",
904 GCPtr, pCur->pszDesc, Pde.u));
905 int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
906 AssertRCReturn(rc, rc);
907 break;
908#else
909 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
910 " PDE=%016RX64.\n",
911 GCPtr, Pde.u));
912 return VINF_PGM_SYNC_CR3;
913#endif
914 }
915 GCPtr += (1 << X86_PD_PAE_SHIFT);
916 }
917 pCur = pNext;
918 }
919 }
920 else
921 AssertFailed();
922
923 Assert(!PGMMapHasConflicts(pVM));
924 return VINF_SUCCESS;
925}
926
927#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
928
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