VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp@ 41965

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1/* $Id: PGMAllMap.cpp 41965 2012-06-29 02:52:49Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor - All context code.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_PGM
22#include <VBox/vmm/pgm.h>
23#include <VBox/vmm/em.h>
24#include "PGMInternal.h"
25#include <VBox/vmm/vm.h>
26#include "PGMInline.h"
27#include <VBox/err.h>
28#include <iprt/asm-amd64-x86.h>
29#include <iprt/assert.h>
30
31
32/**
33 * Maps a range of physical pages at a given virtual address
34 * in the guest context.
35 *
36 * The GC virtual address range must be within an existing mapping.
37 *
38 * @returns VBox status code.
39 * @param pVM The virtual machine.
40 * @param GCPtr Where to map the page(s). Must be page aligned.
41 * @param HCPhys Start of the range of physical pages. Must be page aligned.
42 * @param cbPages Number of bytes to map. Must be page aligned.
43 * @param fFlags Page flags (X86_PTE_*).
44 */
45VMMDECL(int) PGMMap(PVM pVM, RTGCUINTPTR GCPtr, RTHCPHYS HCPhys, uint32_t cbPages, unsigned fFlags)
46{
47 AssertMsg(pVM->pgm.s.offVM, ("Bad init order\n"));
48
49 /*
50 * Validate input.
51 */
52 AssertMsg(RT_ALIGN_T(GCPtr, PAGE_SIZE, RTGCUINTPTR) == GCPtr, ("Invalid alignment GCPtr=%#x\n", GCPtr));
53 AssertMsg(cbPages > 0 && RT_ALIGN_32(cbPages, PAGE_SIZE) == cbPages, ("Invalid cbPages=%#x\n", cbPages));
54 AssertMsg(!(fFlags & X86_PDE_PG_MASK), ("Invalid flags %#x\n", fFlags));
55
56 /* hypervisor defaults */
57 if (!fFlags)
58 fFlags = X86_PTE_P | X86_PTE_A | X86_PTE_D;
59
60 /*
61 * Find the mapping.
62 */
63 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
64 while (pCur)
65 {
66 if (GCPtr - pCur->GCPtr < pCur->cb)
67 {
68 if (GCPtr + cbPages - 1 > pCur->GCPtrLast)
69 {
70 AssertMsgFailed(("Invalid range!!\n"));
71 return VERR_INVALID_PARAMETER;
72 }
73
74 /*
75 * Setup PTE.
76 */
77 X86PTEPAE Pte;
78 Pte.u = fFlags | (HCPhys & X86_PTE_PAE_PG_MASK);
79
80 /*
81 * Update the page tables.
82 */
83 for (;;)
84 {
85 RTGCUINTPTR off = GCPtr - pCur->GCPtr;
86 const unsigned iPT = off >> X86_PD_SHIFT;
87 const unsigned iPageNo = (off >> PAGE_SHIFT) & X86_PT_MASK;
88
89 /* 32-bit */
90 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPageNo].u = (uint32_t)Pte.u; /* ASSUMES HCPhys < 4GB and/or that we're never gonna do 32-bit on a PAE host! */
91
92 /* pae */
93 PGMSHWPTEPAE_SET(pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPageNo / 512].a[iPageNo % 512], Pte.u);
94
95 /* next */
96 cbPages -= PAGE_SIZE;
97 if (!cbPages)
98 break;
99 GCPtr += PAGE_SIZE;
100 Pte.u += PAGE_SIZE;
101 }
102
103 return VINF_SUCCESS;
104 }
105
106 /* next */
107 pCur = pCur->CTX_SUFF(pNext);
108 }
109
110 AssertMsgFailed(("GCPtr=%#x was not found in any mapping ranges!\n", GCPtr));
111 return VERR_INVALID_PARAMETER;
112}
113
114
115/**
116 * Sets (replaces) the page flags for a range of pages in a mapping.
117 *
118 * @returns VBox status.
119 * @param pVM Pointer to the VM.
120 * @param GCPtr Virtual address of the first page in the range.
121 * @param cb Size (in bytes) of the range to apply the modification to.
122 * @param fFlags Page flags X86_PTE_*, excluding the page mask of course.
123 */
124VMMDECL(int) PGMMapSetPage(PVM pVM, RTGCPTR GCPtr, uint64_t cb, uint64_t fFlags)
125{
126 return PGMMapModifyPage(pVM, GCPtr, cb, fFlags, 0);
127}
128
129
130/**
131 * Modify page flags for a range of pages in a mapping.
132 *
133 * The existing flags are ANDed with the fMask and ORed with the fFlags.
134 *
135 * @returns VBox status code.
136 * @param pVM Pointer to the VM.
137 * @param GCPtr Virtual address of the first page in the range.
138 * @param cb Size (in bytes) of the range to apply the modification to.
139 * @param fFlags The OR mask - page flags X86_PTE_*, excluding the page mask of course.
140 * @param fMask The AND mask - page flags X86_PTE_*, excluding the page mask of course.
141 */
142VMMDECL(int) PGMMapModifyPage(PVM pVM, RTGCPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask)
143{
144 /*
145 * Validate input.
146 */
147 AssertMsg(!(fFlags & (X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)), ("fFlags=%#x\n", fFlags));
148 Assert(cb);
149
150 /*
151 * Align the input.
152 */
153 cb += (RTGCUINTPTR)GCPtr & PAGE_OFFSET_MASK;
154 cb = RT_ALIGN_Z(cb, PAGE_SIZE);
155 GCPtr = (RTGCPTR)((RTGCUINTPTR)GCPtr & PAGE_BASE_GC_MASK);
156
157 /*
158 * Find the mapping.
159 */
160 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
161 while (pCur)
162 {
163 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
164 if (off < pCur->cb)
165 {
166 AssertMsgReturn(off + cb <= pCur->cb,
167 ("Invalid page range %#x LB%#x. mapping '%s' %#x to %#x\n",
168 GCPtr, cb, pCur->pszDesc, pCur->GCPtr, pCur->GCPtrLast),
169 VERR_INVALID_PARAMETER);
170
171 /*
172 * Perform the requested operation.
173 */
174 while (cb > 0)
175 {
176 unsigned iPT = off >> X86_PD_SHIFT;
177 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
178 while (cb > 0 && iPTE < RT_ELEMENTS(pCur->aPTs[iPT].CTX_SUFF(pPT)->a))
179 {
180 /* 32-Bit */
181 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u &= fMask | X86_PTE_PG_MASK;
182 pCur->aPTs[iPT].CTX_SUFF(pPT)->a[iPTE].u |= fFlags & ~X86_PTE_PG_MASK;
183
184 /* PAE */
185 PPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
186 PGMSHWPTEPAE_SET(*pPtePae,
187 ( PGMSHWPTEPAE_GET_U(*pPtePae)
188 & (fMask | X86_PTE_PAE_PG_MASK))
189 | (fFlags & ~(X86_PTE_PAE_PG_MASK | X86_PTE_PAE_MBZ_MASK_NX)));
190
191 /* invalidate tls */
192 PGM_INVL_PG(VMMGetCpu(pVM), (RTGCUINTPTR)pCur->GCPtr + off);
193
194 /* next */
195 iPTE++;
196 cb -= PAGE_SIZE;
197 off += PAGE_SIZE;
198 }
199 }
200
201 return VINF_SUCCESS;
202 }
203 /* next */
204 pCur = pCur->CTX_SUFF(pNext);
205 }
206
207 AssertMsgFailed(("Page range %#x LB%#x not found\n", GCPtr, cb));
208 return VERR_INVALID_PARAMETER;
209}
210
211
212/**
213 * Get information about a page in a mapping.
214 *
215 * This differs from PGMShwGetPage and PGMGstGetPage in that it only consults
216 * the page table to calculate the flags.
217 *
218 * @returns VINF_SUCCESS, VERR_PAGE_NOT_PRESENT or VERR_NOT_FOUND.
219 * @param pVM Pointer to the VM.
220 * @param GCPtr The page address.
221 * @param pfFlags Where to return the flags. Optional.
222 * @param pHCPhys Where to return the address. Optional.
223 */
224VMMDECL(int) PGMMapGetPage(PVM pVM, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
225{
226 /*
227 * Find the mapping.
228 */
229 GCPtr &= PAGE_BASE_GC_MASK;
230 PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings);
231 while (pCur)
232 {
233 RTGCUINTPTR off = (RTGCUINTPTR)GCPtr - (RTGCUINTPTR)pCur->GCPtr;
234 if (off < pCur->cb)
235 {
236 /*
237 * Dig out the information.
238 */
239 int rc = VINF_SUCCESS;
240 unsigned iPT = off >> X86_PD_SHIFT;
241 unsigned iPTE = (off >> PAGE_SHIFT) & X86_PT_MASK;
242 PCPGMSHWPTEPAE pPtePae = &pCur->aPTs[iPT].CTX_SUFF(paPaePTs)[iPTE / 512].a[iPTE % 512];
243 if (PGMSHWPTEPAE_IS_P(*pPtePae))
244 {
245 if (pfFlags)
246 *pfFlags = PGMSHWPTEPAE_GET_U(*pPtePae) & ~X86_PTE_PAE_PG_MASK;
247 if (pHCPhys)
248 *pHCPhys = PGMSHWPTEPAE_GET_HCPHYS(*pPtePae);
249 }
250 else
251 rc = VERR_PAGE_NOT_PRESENT;
252 return rc;
253 }
254 /* next */
255 pCur = pCur->CTX_SUFF(pNext);
256 }
257
258 return VERR_NOT_FOUND;
259}
260
261
262
263#ifndef IN_RING0
264/**
265 * Sets all PDEs involved with the mapping in the shadow page table.
266 *
267 * @param pVM Pointer to the VM.
268 * @param pMap Pointer to the mapping in question.
269 * @param iNewPDE The index of the 32-bit PDE corresponding to the base of the mapping.
270 */
271void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE)
272{
273 Log4(("pgmMapSetShadowPDEs new pde %x (mappings enabled %d)\n", iNewPDE, pgmMapAreMappingsEnabled(pVM)));
274
275 if ( !pgmMapAreMappingsEnabled(pVM)
276 || pVM->cCpus > 1)
277 return;
278
279 /* This only applies to raw mode where we only support 1 VCPU. */
280 PVMCPU pVCpu = VMMGetCpu0(pVM);
281 if (!pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
282 return; /* too early */
283
284 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
285 Assert(enmShadowMode <= PGMMODE_PAE_NX);
286
287 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
288
289 /*
290 * Insert the page tables into the shadow page directories.
291 */
292 unsigned i = pMap->cPTs;
293 iNewPDE += i;
294 while (i-- > 0)
295 {
296 iNewPDE--;
297
298 switch (enmShadowMode)
299 {
300 case PGMMODE_32_BIT:
301 {
302 PX86PD pShw32BitPd = pgmShwGet32BitPDPtr(pVCpu);
303 AssertFatal(pShw32BitPd);
304
305 /* Free any previous user, unless it's us. */
306 Assert( (pShw32BitPd->a[iNewPDE].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
307 || (pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK) == pMap->aPTs[i].HCPhysPT);
308 if ( pShw32BitPd->a[iNewPDE].n.u1Present
309 && !(pShw32BitPd->a[iNewPDE].u & PGM_PDFLAGS_MAPPING))
310 pgmPoolFree(pVM, pShw32BitPd->a[iNewPDE].u & X86_PDE_PG_MASK, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iNewPDE);
311
312 /* Default mapping page directory flags are read/write and supervisor; individual page attributes determine the final flags. */
313 pShw32BitPd->a[iNewPDE].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
314 | (uint32_t)pMap->aPTs[i].HCPhysPT;
315 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShw32BitPd);
316 break;
317 }
318
319 case PGMMODE_PAE:
320 case PGMMODE_PAE_NX:
321 {
322 const uint32_t iPdPt = iNewPDE / 256;
323 unsigned iPaePde = iNewPDE * 2 % 512;
324 PX86PDPT pShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
325 Assert(pShwPdpt);
326
327 /*
328 * Get the shadow PD.
329 * If no PD, sync it (PAE guest) or fake (not present or 32-bit guest).
330 * Note! The RW, US and A bits are reserved for PAE PDPTEs. Setting the
331 * accessed bit causes invalid VT-x guest state errors.
332 */
333 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
334 if (!pShwPaePd)
335 {
336 X86PDPE GstPdpe;
337 if (PGMGetGuestMode(pVCpu) < PGMMODE_PAE)
338 GstPdpe.u = X86_PDPE_P;
339 else
340 {
341 PX86PDPE pGstPdpe = pgmGstGetPaePDPEPtr(pVCpu, iPdPt << X86_PDPT_SHIFT);
342 if (pGstPdpe)
343 GstPdpe = *pGstPdpe;
344 else
345 GstPdpe.u = X86_PDPE_P;
346 }
347 int rc = pgmShwSyncPaePDPtr(pVCpu, iPdPt << X86_PDPT_SHIFT, GstPdpe.u, &pShwPaePd);
348 AssertFatalRC(rc);
349 }
350 Assert(pShwPaePd);
351
352 /*
353 * Mark the page as locked; disallow flushing.
354 */
355 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdPt].u & X86_PDPE_PG_MASK);
356 AssertFatal(pPoolPagePd);
357 if (!pgmPoolIsPageLocked(pPoolPagePd))
358 pgmPoolLockPage(pPool, pPoolPagePd);
359#ifdef VBOX_STRICT
360 else if (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING)
361 {
362 Assert(PGMGetGuestMode(pVCpu) >= PGMMODE_PAE); /** @todo We may hit this during reset, will fix later. */
363 AssertFatalMsg( (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0
364 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
365 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT0));
366 Assert(pShwPaePd->a[iPaePde+1].u & PGM_PDFLAGS_MAPPING);
367 AssertFatalMsg( (pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1
368 || !PGMMODE_WITH_PAGING(PGMGetGuestMode(pVCpu)),
369 ("%RX64 vs %RX64\n", pShwPaePd->a[iPaePde+1].u & X86_PDE_PAE_PG_MASK, pMap->aPTs[i].HCPhysPaePT1));
370 }
371#endif
372
373 /*
374 * Insert our first PT, freeing anything we might be replacing unless it's a mapping (i.e. us).
375 */
376 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
377 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT0);
378 if ( pShwPaePd->a[iPaePde].n.u1Present
379 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
380 {
381 Assert(!(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
382 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK, pPoolPagePd->idx, iPaePde);
383 }
384 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
385 | pMap->aPTs[i].HCPhysPaePT0;
386
387 /* 2nd 2 MB PDE of the 4 MB region, same as above. */
388 iPaePde++;
389 AssertFatal(iPaePde < 512);
390 Assert( (pShwPaePd->a[iPaePde].u & (X86_PDE_P | PGM_PDFLAGS_MAPPING)) != (X86_PDE_P | PGM_PDFLAGS_MAPPING)
391 || (pShwPaePd->a[iPaePde].u & X86_PDE_PAE_PG_MASK) == pMap->aPTs[i].HCPhysPaePT1);
392 if ( pShwPaePd->a[iPaePde].n.u1Present
393 && !(pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING))
394 pgmPoolFree(pVM, pShwPaePd->a[iPaePde].u & X86_PDE_PG_MASK, pPoolPagePd->idx, iPaePde);
395 pShwPaePd->a[iPaePde].u = PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US
396 | pMap->aPTs[i].HCPhysPaePT1;
397
398 /*
399 * Set the PGM_PDFLAGS_MAPPING flag in the page directory pointer entry. (legacy PAE guest mode)
400 */
401 pShwPdpt->a[iPdPt].u |= PGM_PLXFLAGS_MAPPING;
402
403 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPaePd);
404 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pShwPdpt);
405 break;
406 }
407
408 default:
409 AssertFailed();
410 break;
411 }
412 }
413}
414
415
416/**
417 * Clears all PDEs involved with the mapping in the shadow page table.
418 *
419 * @param pVM Pointer to the VM.
420 * @param pShwPageCR3 CR3 root page
421 * @param pMap Pointer to the mapping in question.
422 * @param iOldPDE The index of the 32-bit PDE corresponding to the base of the mapping.
423 * @param fDeactivateCR3 Set if it's pgmMapDeactivateCR3 calling.
424 */
425void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3)
426{
427 Log(("pgmMapClearShadowPDEs: old pde %x (cPTs=%x) (mappings enabled %d) fDeactivateCR3=%RTbool\n", iOldPDE, pMap->cPTs, pgmMapAreMappingsEnabled(pVM), fDeactivateCR3));
428
429 /*
430 * Skip this if disabled or if it doesn't apply.
431 */
432 if ( !pgmMapAreMappingsEnabled(pVM)
433 || pVM->cCpus > 1)
434 return;
435
436 Assert(pShwPageCR3);
437
438 /* This only applies to raw mode where we only support 1 VCPU. */
439 PVMCPU pVCpu = VMMGetCpu0(pVM);
440# ifdef IN_RC
441 Assert(pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
442# endif
443
444 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
445
446 PX86PDPT pCurrentShwPdpt = NULL;
447 if ( PGMGetGuestMode(pVCpu) >= PGMMODE_PAE
448 && pShwPageCR3 != pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
449 pCurrentShwPdpt = pgmShwGetPaePDPTPtr(pVCpu);
450
451 unsigned i = pMap->cPTs;
452 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
453
454 iOldPDE += i;
455 while (i-- > 0)
456 {
457 iOldPDE--;
458
459 switch(enmShadowMode)
460 {
461 case PGMMODE_32_BIT:
462 {
463 PX86PD pShw32BitPd = (PX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
464 AssertFatal(pShw32BitPd);
465
466 Assert(!pShw32BitPd->a[iOldPDE].n.u1Present || (pShw32BitPd->a[iOldPDE].u & PGM_PDFLAGS_MAPPING));
467 pShw32BitPd->a[iOldPDE].u = 0;
468 break;
469 }
470
471 case PGMMODE_PAE:
472 case PGMMODE_PAE_NX:
473 {
474 const unsigned iPdpt = iOldPDE / 256; /* iOldPDE * 2 / 512; iOldPDE is in 4 MB pages */
475 unsigned iPaePde = iOldPDE * 2 % 512;
476 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
477 PX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, (iPdpt << X86_PDPT_SHIFT));
478
479 /*
480 * Clear the PGM_PDFLAGS_MAPPING flag for the page directory pointer entry. (legacy PAE guest mode)
481 */
482 if (fDeactivateCR3)
483 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
484 else if (pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING)
485 {
486 /* See if there are any other mappings here. This is suboptimal code. */
487 pShwPdpt->a[iPdpt].u &= ~PGM_PLXFLAGS_MAPPING;
488 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
489 if ( pCur != pMap
490 && ( (pCur->GCPtr >> X86_PDPT_SHIFT) == iPdpt
491 || (pCur->GCPtrLast >> X86_PDPT_SHIFT) == iPdpt))
492 {
493 pShwPdpt->a[iPdpt].u |= PGM_PLXFLAGS_MAPPING;
494 break;
495 }
496 }
497
498 /*
499 * If the page directory of the old CR3 is reused in the new one, then don't
500 * clear the hypervisor mappings.
501 */
502 if ( pCurrentShwPdpt
503 && (pCurrentShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) == (pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK) )
504 {
505 LogFlow(("pgmMapClearShadowPDEs: Pdpe %d reused -> don't clear hypervisor mappings!\n", iPdpt));
506 break;
507 }
508
509 /*
510 * Clear the mappings in the PD.
511 */
512 AssertFatal(pShwPaePd);
513 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
514 pShwPaePd->a[iPaePde].u = 0;
515
516 iPaePde++;
517 AssertFatal(iPaePde < 512);
518 Assert(!pShwPaePd->a[iPaePde].n.u1Present || (pShwPaePd->a[iPaePde].u & PGM_PDFLAGS_MAPPING));
519 pShwPaePd->a[iPaePde].u = 0;
520
521 /*
522 * Unlock the shadow pool PD page if the PDPTE no longer holds any mappings.
523 */
524 if ( fDeactivateCR3
525 || !(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
526 {
527 PPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
528 AssertFatal(pPoolPagePd);
529 if (pgmPoolIsPageLocked(pPoolPagePd))
530 pgmPoolUnlockPage(pPool, pPoolPagePd);
531 }
532 break;
533 }
534
535 default:
536 AssertFailed();
537 break;
538 }
539 }
540
541 PGM_DYNMAP_UNUSED_HINT_VM(pVM, pCurrentShwPdpt);
542}
543#endif /* !IN_RING0 */
544
545#if defined(VBOX_STRICT) && !defined(IN_RING0)
546/**
547 * Clears all PDEs involved with the mapping in the shadow page table.
548 *
549 * @param pVM Pointer to the VM.
550 * @param pVCpu Pointer to the VMCPU.
551 * @param pShwPageCR3 CR3 root page
552 * @param pMap Pointer to the mapping in question.
553 * @param iPDE The index of the 32-bit PDE corresponding to the base of the mapping.
554 */
555static void pgmMapCheckShadowPDEs(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iPDE)
556{
557 Assert(pShwPageCR3);
558
559 uint32_t i = pMap->cPTs;
560 PGMMODE enmShadowMode = PGMGetShadowMode(pVCpu);
561 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
562
563 iPDE += i;
564 while (i-- > 0)
565 {
566 iPDE--;
567
568 switch (enmShadowMode)
569 {
570 case PGMMODE_32_BIT:
571 {
572 PCX86PD pShw32BitPd = (PCX86PD)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
573 AssertFatal(pShw32BitPd);
574
575 AssertMsg(pShw32BitPd->a[iPDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
576 ("Expected %x vs %x; iPDE=%#x %RGv %s\n",
577 pShw32BitPd->a[iPDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | (uint32_t)pMap->aPTs[i].HCPhysPT),
578 iPDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
579 break;
580 }
581
582 case PGMMODE_PAE:
583 case PGMMODE_PAE_NX:
584 {
585 const unsigned iPdpt = iPDE / 256; /* iPDE * 2 / 512; iPDE is in 4 MB pages */
586 unsigned iPaePDE = iPDE * 2 % 512;
587 PX86PDPT pShwPdpt = (PX86PDPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPageCR3);
588 PCX86PDPAE pShwPaePd = pgmShwGetPaePDPtr(pVCpu, pShwPdpt, iPdpt << X86_PDPT_SHIFT);
589 AssertFatal(pShwPaePd);
590
591 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
592 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
593 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT0),
594 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
595
596 iPaePDE++;
597 AssertFatal(iPaePDE < 512);
598
599 AssertMsg(pShwPaePd->a[iPaePDE].u == (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
600 ("Expected %RX64 vs %RX64; iPDE=%#x iPdpt=%#x iPaePDE=%#x %RGv %s\n",
601 pShwPaePd->a[iPaePDE].u, (PGM_PDFLAGS_MAPPING | X86_PDE_P | X86_PDE_A | X86_PDE_RW | X86_PDE_US | pMap->aPTs[i].HCPhysPaePT1),
602 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
603
604 AssertMsg(pShwPdpt->a[iPdpt].u & PGM_PLXFLAGS_MAPPING,
605 ("%RX64; iPdpt=%#x iPDE=%#x iPaePDE=%#x %RGv %s\n",
606 pShwPdpt->a[iPdpt].u,
607 iPDE, iPdpt, iPaePDE, pMap->GCPtr, R3STRING(pMap->pszDesc) ));
608
609 PCPGMPOOLPAGE pPoolPagePd = pgmPoolGetPage(pPool, pShwPdpt->a[iPdpt].u & X86_PDPE_PG_MASK);
610 AssertFatal(pPoolPagePd);
611 AssertMsg(pPoolPagePd->cLocked, (".idx=%d .type=%d\n", pPoolPagePd->idx, pPoolPagePd->enmKind));
612 break;
613 }
614
615 default:
616 AssertFailed();
617 break;
618 }
619 }
620}
621
622
623/**
624 * Check the hypervisor mappings in the active CR3.
625 *
626 * @param pVM The virtual machine.
627 */
628VMMDECL(void) PGMMapCheck(PVM pVM)
629{
630 /*
631 * Can skip this if mappings are disabled.
632 */
633 if (!pgmMapAreMappingsEnabled(pVM))
634 return;
635
636 /* This only applies to raw mode where we only support 1 VCPU. */
637 Assert(pVM->cCpus == 1);
638 PVMCPU pVCpu = VMMGetCpu0(pVM);
639 Assert(pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
640
641 /*
642 * Iterate mappings.
643 */
644 pgmLock(pVM); /* to avoid assertions */
645 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
646 {
647 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
648 pgmMapCheckShadowPDEs(pVM, pVCpu, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pCur, iPDE);
649 }
650 pgmUnlock(pVM);
651}
652#endif /* defined(VBOX_STRICT) && !defined(IN_RING0) */
653
654#ifndef IN_RING0
655
656/**
657 * Apply the hypervisor mappings to the active CR3.
658 *
659 * @returns VBox status.
660 * @param pVM The virtual machine.
661 * @param pShwPageCR3 CR3 root page
662 */
663int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
664{
665 /*
666 * Skip this if disabled or if it doesn't apply.
667 */
668 if ( !pgmMapAreMappingsEnabled(pVM)
669 || pVM->cCpus > 1)
670 return VINF_SUCCESS;
671
672 /* Note! This might not be logged successfully in RC because we usually
673 cannot flush the log at this point. */
674 Log4(("pgmMapActivateCR3: fixed mappings=%RTbool idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
675
676#ifdef VBOX_STRICT
677 PVMCPU pVCpu = VMMGetCpu0(pVM);
678 Assert(pShwPageCR3 && pShwPageCR3 == pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
679#endif
680
681 /*
682 * Iterate mappings.
683 */
684 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
685 {
686 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
687 pgmMapSetShadowPDEs(pVM, pCur, iPDE);
688 }
689 return VINF_SUCCESS;
690}
691
692
693/**
694 * Remove the hypervisor mappings from the specified CR3
695 *
696 * @returns VBox status.
697 * @param pVM The virtual machine.
698 * @param pShwPageCR3 CR3 root page
699 */
700int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3)
701{
702 /*
703 * Skip this if disabled or if it doesn't apply.
704 */
705 if ( !pgmMapAreMappingsEnabled(pVM)
706 || pVM->cCpus > 1)
707 return VINF_SUCCESS;
708
709 Assert(pShwPageCR3);
710 Log4(("pgmMapDeactivateCR3: fixed mappings=%d idxShwPageCR3=%#x\n", pVM->pgm.s.fMappingsFixed, pShwPageCR3 ? pShwPageCR3->idx : NIL_PGMPOOL_IDX));
711
712 /*
713 * Iterate mappings.
714 */
715 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
716 {
717 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
718 pgmMapClearShadowPDEs(pVM, pShwPageCR3, pCur, iPDE, true /*fDeactivateCR3*/);
719 }
720 return VINF_SUCCESS;
721}
722
723
724/**
725 * Checks guest PD for conflicts with VMM GC mappings.
726 *
727 * @returns true if conflict detected.
728 * @returns false if not.
729 * @param pVM The virtual machine.
730 */
731VMMDECL(bool) PGMMapHasConflicts(PVM pVM)
732{
733 /*
734 * Can skip this if mappings are safely fixed.
735 */
736 if (!pgmMapAreMappingsFloating(pVM))
737 return false;
738
739 Assert(pVM->cCpus == 1);
740
741 /* This only applies to raw mode where we only support 1 VCPU. */
742 PVMCPU pVCpu = &pVM->aCpus[0];
743
744 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
745 Assert(enmGuestMode <= PGMMODE_PAE_NX);
746
747 /*
748 * Iterate mappings.
749 */
750 if (enmGuestMode == PGMMODE_32_BIT)
751 {
752 /*
753 * Resolve the page directory.
754 */
755 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
756 Assert(pPD);
757
758 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
759 {
760 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
761 unsigned iPT = pCur->cPTs;
762 while (iPT-- > 0)
763 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
764 && (EMIsRawRing0Enabled(pVM) || pPD->a[iPDE + iPT].n.u1User))
765 {
766 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
767
768#ifdef IN_RING3
769 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
770 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
771 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
772 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
773#else
774 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
775 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
776 (iPT + iPDE) << X86_PD_SHIFT,
777 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
778#endif
779 return true;
780 }
781 }
782 }
783 else if ( enmGuestMode == PGMMODE_PAE
784 || enmGuestMode == PGMMODE_PAE_NX)
785 {
786 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; pCur = pCur->CTX_SUFF(pNext))
787 {
788 RTGCPTR GCPtr = pCur->GCPtr;
789
790 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
791 while (iPT-- > 0)
792 {
793 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
794
795 if ( Pde.n.u1Present
796 && (EMIsRawRing0Enabled(pVM) || Pde.n.u1User))
797 {
798 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
799#ifdef IN_RING3
800 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
801 " PDE=%016RX64.\n",
802 GCPtr, pCur->pszDesc, Pde.u));
803#else
804 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
805 " PDE=%016RX64.\n",
806 GCPtr, Pde.u));
807#endif
808 return true;
809 }
810 GCPtr += (1 << X86_PD_PAE_SHIFT);
811 }
812 }
813 }
814 else
815 AssertFailed();
816
817 return false;
818}
819
820
821/**
822 * Checks and resolves (ring 3 only) guest conflicts with the guest mappings.
823 *
824 * @returns VBox status.
825 * @param pVM The virtual machine.
826 */
827int pgmMapResolveConflicts(PVM pVM)
828{
829 /* The caller is expected to check these two conditions. */
830 Assert(!pVM->pgm.s.fMappingsFixed);
831 Assert(!pVM->pgm.s.fMappingsDisabled);
832
833 /* This only applies to raw mode where we only support 1 VCPU. */
834 Assert(pVM->cCpus == 1);
835 PVMCPU pVCpu = &pVM->aCpus[0];
836 PGMMODE const enmGuestMode = PGMGetGuestMode(pVCpu);
837 Assert(enmGuestMode <= PGMMODE_PAE_NX);
838
839 if (enmGuestMode == PGMMODE_32_BIT)
840 {
841 /*
842 * Resolve the page directory.
843 */
844 PX86PD pPD = pgmGstGet32bitPDPtr(pVCpu);
845 Assert(pPD);
846
847 /*
848 * Iterate mappings.
849 */
850 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur; )
851 {
852 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
853 unsigned iPDE = pCur->GCPtr >> X86_PD_SHIFT;
854 unsigned iPT = pCur->cPTs;
855 while (iPT-- > 0)
856 {
857 if ( pPD->a[iPDE + iPT].n.u1Present /** @todo PGMGstGetPDE. */
858 && ( EMIsRawRing0Enabled(pVM)
859 || pPD->a[iPDE + iPT].n.u1User))
860 {
861 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
862
863#ifdef IN_RING3
864 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping %s (32 bits)\n"
865 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
866 (iPT + iPDE) << X86_PD_SHIFT, pCur->pszDesc,
867 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
868 int rc = pgmR3SyncPTResolveConflict(pVM, pCur, pPD, iPDE << X86_PD_SHIFT);
869 AssertRCReturn(rc, rc);
870 break;
871#else
872 Log(("PGMHasMappingConflicts: Conflict was detected at %08RX32 for mapping (32 bits)\n"
873 " iPDE=%#x iPT=%#x PDE=%RGp.\n",
874 (iPT + iPDE) << X86_PD_SHIFT,
875 iPDE, iPT, pPD->a[iPDE + iPT].au32[0]));
876 return VINF_PGM_SYNC_CR3;
877#endif
878 }
879 }
880 pCur = pNext;
881 }
882 }
883 else if ( enmGuestMode == PGMMODE_PAE
884 || enmGuestMode == PGMMODE_PAE_NX)
885 {
886 /*
887 * Iterate mappings.
888 */
889 for (PPGMMAPPING pCur = pVM->pgm.s.CTX_SUFF(pMappings); pCur;)
890 {
891 PPGMMAPPING pNext = pCur->CTX_SUFF(pNext);
892 RTGCPTR GCPtr = pCur->GCPtr;
893 unsigned iPT = pCur->cb >> X86_PD_PAE_SHIFT;
894 while (iPT-- > 0)
895 {
896 X86PDEPAE Pde = pgmGstGetPaePDE(pVCpu, GCPtr);
897
898 if ( Pde.n.u1Present
899 && (EMIsRawRing0Enabled(pVM) || Pde.n.u1User))
900 {
901 STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatR3DetectedConflicts);
902#ifdef IN_RING3
903 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping %s (PAE)\n"
904 " PDE=%016RX64.\n",
905 GCPtr, pCur->pszDesc, Pde.u));
906 int rc = pgmR3SyncPTResolveConflictPAE(pVM, pCur, pCur->GCPtr);
907 AssertRCReturn(rc, rc);
908 break;
909#else
910 Log(("PGMHasMappingConflicts: Conflict was detected at %RGv for mapping (PAE)\n"
911 " PDE=%016RX64.\n",
912 GCPtr, Pde.u));
913 return VINF_PGM_SYNC_CR3;
914#endif
915 }
916 GCPtr += (1 << X86_PD_PAE_SHIFT);
917 }
918 pCur = pNext;
919 }
920 }
921 else
922 AssertFailed();
923
924 Assert(!PGMMapHasConflicts(pVM));
925 return VINF_SUCCESS;
926}
927
928#endif /* IN_RING0 */
929
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