VirtualBox

source: vbox/trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp@ 43667

Last change on this file since 43667 was 42676, checked in by vboxsync, 12 years ago

IEM: IRET to V8086 (had to try). Set CPUM_CHANGED_FPU_REM. Added missing RIP advancing to fincstp and fdecstp.
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1/* $Id: tstIEMCheckMc.cpp 42676 2012-08-08 09:23:50Z vboxsync $ */
2/** @file
3 * IEM Testcase - Check the "Microcode".
4 */
5
6/*
7 * Copyright (C) 2011 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#include <iprt/assert.h>
22#include <iprt/rand.h>
23#include <iprt/test.h>
24
25#include <VBox/types.h>
26#include <VBox/err.h>
27#include <VBox/log.h>
28#include "../include/IEMInternal.h"
29
30
31/*******************************************************************************
32* Global Variables *
33*******************************************************************************/
34bool volatile g_fRandom;
35uint8_t volatile g_bRandom;
36
37
38/** For hacks. */
39#define TST_IEM_CHECK_MC
40
41#define CHK_TYPE(a_ExpectedType, a_Param) \
42 do { a_ExpectedType const * pCheckType = &(a_Param); NOREF(pCheckType); } while (0)
43#define CHK_PTYPE(a_ExpectedType, a_Param) \
44 do { a_ExpectedType pCheckType = (a_Param); NOREF(pCheckType); } while (0)
45
46#define CHK_CONST(a_ExpectedType, a_Const) \
47 do { \
48 AssertCompile(((a_Const) >> 1) == ((a_Const) >> 1)); \
49 AssertCompile((a_ExpectedType)(a_Const) == (a_Const)); \
50 } while (0)
51
52#define CHK_SINGLE_BIT(a_ExpectedType, a_fBitMask) \
53 do { \
54 CHK_CONST(a_ExpectedType, a_fBitMask); \
55 AssertCompile(RT_IS_POWER_OF_TWO(a_fBitMask)); \
56 } while (0)
57
58#define CHK_GCPTR(a_EffAddr) \
59 CHK_TYPE(RTGCPTR, a_EffAddr)
60
61#define CHK_SEG_IDX(a_iSeg) \
62 do { \
63 uint8_t iMySeg = (a_iSeg); NOREF(iMySeg); /** @todo const or variable. grr. */ \
64 } while (0)
65
66
67/** @name Other stubs.
68 * @{ */
69
70typedef VBOXSTRICTRC (* PFNIEMOP)(PIEMCPU pIemCpu);
71#define FNIEMOP_DEF(a_Name) \
72 static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu) RT_NO_THROW
73#define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
74 static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0) RT_NO_THROW
75#define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
76 static VBOXSTRICTRC a_Name(PIEMCPU pIemCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW
77
78#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: return VERR_IPE_NOT_REACHED_DEFAULT_CASE
79#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
80#define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) return IEM_RETURN_ASPECT_NOT_IMPLEMENTED
81
82
83#define IEM_OPCODE_GET_NEXT_U8(a_pu8) do { *(a_pu8) = g_bRandom; CHK_PTYPE(uint8_t *, a_pu8); } while (0)
84#define IEM_OPCODE_GET_NEXT_S8(a_pi8) do { *(a_pi8) = g_bRandom; CHK_PTYPE(int8_t *, a_pi8); } while (0)
85#define IEM_OPCODE_GET_NEXT_S8_SX_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0)
86#define IEM_OPCODE_GET_NEXT_S8_SX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
87#define IEM_OPCODE_GET_NEXT_S8_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
88#define IEM_OPCODE_GET_NEXT_U16(a_pu16) do { *(a_pu16) = g_bRandom; CHK_PTYPE(uint16_t *, a_pu16); } while (0)
89#define IEM_OPCODE_GET_NEXT_U16_ZX_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
90#define IEM_OPCODE_GET_NEXT_U16_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
91#define IEM_OPCODE_GET_NEXT_S16(a_pi16) do { *(a_pi16) = g_bRandom; CHK_PTYPE(int16_t *, a_pi16); } while (0)
92#define IEM_OPCODE_GET_NEXT_U32(a_pu32) do { *(a_pu32) = g_bRandom; CHK_PTYPE(uint32_t *, a_pu32); } while (0)
93#define IEM_OPCODE_GET_NEXT_U32_ZX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
94#define IEM_OPCODE_GET_NEXT_S32(a_pi32) do { *(a_pi32) = g_bRandom; CHK_PTYPE(int32_t *, a_pi32); } while (0)
95#define IEM_OPCODE_GET_NEXT_S32_SX_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
96#define IEM_OPCODE_GET_NEXT_U64(a_pu64) do { *(a_pu64) = g_bRandom; CHK_PTYPE(uint64_t *, a_pu64); } while (0)
97#define IEMOP_HLP_NO_REAL_OR_V86_MODE() do { } while (0)
98#define IEMOP_HLP_NO_LOCK_PREFIX() do { } while (0)
99#define IEMOP_HLP_NO_64BIT() do { } while (0)
100#define IEMOP_HLP_64BIT_OP_SIZE() do { } while (0)
101#define IEMOP_HLP_DEFAULT_64BIT_OP_SIZE() do { } while (0)
102#define IEMOP_HLP_DONE_DECODING() do { } while (0)
103#define IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX() do { } while (0)
104#define IEMOP_RAISE_DIVIDE_ERROR() VERR_TRPM_ACTIVE_TRAP
105#define IEMOP_RAISE_INVALID_OPCODE() VERR_TRPM_ACTIVE_TRAP
106#define IEMOP_RAISE_INVALID_LOCK_PREFIX() VERR_TRPM_ACTIVE_TRAP
107#define IEMOP_MNEMONIC(a_szMnemonic) do { } while (0)
108#define IEMOP_MNEMONIC2(a_szMnemonic, a_szOps) do { } while (0)
109#define IEMOP_BITCH_ABOUT_STUB() do { } while (0)
110#define FNIEMOP_STUB(a_Name) \
111 FNIEMOP_DEF(a_Name) { return VERR_NOT_IMPLEMENTED; } \
112 typedef int ignore_semicolon
113#define FNIEMOP_STUB_1(a_Name, a_Type0, a_Name0) \
114 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return VERR_NOT_IMPLEMENTED; } \
115 typedef int ignore_semicolon
116
117#define FNIEMOP_UD_STUB(a_Name) \
118 FNIEMOP_DEF(a_Name) { return IEMOP_RAISE_INVALID_OPCODE(); } \
119 typedef int ignore_semicolon
120#define FNIEMOP_UD_STUB_1(a_Name, a_Type0, a_Name0) \
121 FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) { return IEMOP_RAISE_INVALID_OPCODE(); } \
122 typedef int ignore_semicolon
123
124
125#define FNIEMOP_CALL(a_pfn) (a_pfn)(pIemCpu)
126#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pIemCpu, a0)
127#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pIemCpu, a0, a1)
128
129#define IEM_IS_REAL_OR_V86_MODE(a_pIemCpu) (g_fRandom)
130#define IEM_IS_LONG_MODE(a_pIemCpu) (g_fRandom)
131#define IEM_IS_REAL_MODE(a_pIemCpu) (g_fRandom)
132#define IEM_IS_AMD_CPUID_FEATURE_PRESENT_ECX(a_fEcx) (g_fRandom)
133#define IEM_IS_AMD_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom)
134#define IEM_IS_AMD_CPUID_FEATURES_ANY_PRESENT(a_fEdx, a_fEcx) (g_fRandom)
135#define IEM_IS_INTEL_CPUID_FEATURE_PRESENT_EDX(a_fEdx) (g_fRandom)
136
137#define iemRecalEffOpSize(a_pIemCpu) do { } while (0)
138
139IEMOPBINSIZES g_iemAImpl_add;
140IEMOPBINSIZES g_iemAImpl_adc;
141IEMOPBINSIZES g_iemAImpl_sub;
142IEMOPBINSIZES g_iemAImpl_sbb;
143IEMOPBINSIZES g_iemAImpl_or;
144IEMOPBINSIZES g_iemAImpl_xor;
145IEMOPBINSIZES g_iemAImpl_and;
146IEMOPBINSIZES g_iemAImpl_cmp;
147IEMOPBINSIZES g_iemAImpl_test;
148IEMOPBINSIZES g_iemAImpl_bt;
149IEMOPBINSIZES g_iemAImpl_btc;
150IEMOPBINSIZES g_iemAImpl_btr;
151IEMOPBINSIZES g_iemAImpl_bts;
152IEMOPBINSIZES g_iemAImpl_bsf;
153IEMOPBINSIZES g_iemAImpl_bsr;
154IEMOPBINSIZES g_iemAImpl_imul_two;
155PCIEMOPBINSIZES g_apIemImplGrp1[8];
156IEMOPUNARYSIZES g_iemAImpl_inc;
157IEMOPUNARYSIZES g_iemAImpl_dec;
158IEMOPUNARYSIZES g_iemAImpl_neg;
159IEMOPUNARYSIZES g_iemAImpl_not;
160IEMOPSHIFTSIZES g_iemAImpl_rol;
161IEMOPSHIFTSIZES g_iemAImpl_ror;
162IEMOPSHIFTSIZES g_iemAImpl_rcl;
163IEMOPSHIFTSIZES g_iemAImpl_rcr;
164IEMOPSHIFTSIZES g_iemAImpl_shl;
165IEMOPSHIFTSIZES g_iemAImpl_shr;
166IEMOPSHIFTSIZES g_iemAImpl_sar;
167IEMOPMULDIVSIZES g_iemAImpl_mul;
168IEMOPMULDIVSIZES g_iemAImpl_imul;
169IEMOPMULDIVSIZES g_iemAImpl_div;
170IEMOPMULDIVSIZES g_iemAImpl_idiv;
171IEMOPSHIFTDBLSIZES g_iemAImpl_shld;
172IEMOPSHIFTDBLSIZES g_iemAImpl_shrd;
173
174
175#define iemAImpl_idiv_u8 ((PFNIEMAIMPLMULDIVU8)0)
176#define iemAImpl_div_u8 ((PFNIEMAIMPLMULDIVU8)0)
177#define iemAImpl_imul_u8 ((PFNIEMAIMPLMULDIVU8)0)
178#define iemAImpl_mul_u8 ((PFNIEMAIMPLMULDIVU8)0)
179
180#define iemAImpl_fpu_r32_to_r80 NULL
181#define iemAImpl_fcom_r80_by_r32 NULL
182#define iemAImpl_fadd_r80_by_r32 NULL
183#define iemAImpl_fmul_r80_by_r32 NULL
184#define iemAImpl_fsub_r80_by_r32 NULL
185#define iemAImpl_fsubr_r80_by_r32 NULL
186#define iemAImpl_fdiv_r80_by_r32 NULL
187#define iemAImpl_fdivr_r80_by_r32 NULL
188
189#define iemAImpl_fpu_r64_to_r80 NULL
190#define iemAImpl_fadd_r80_by_r64 NULL
191#define iemAImpl_fmul_r80_by_r64 NULL
192#define iemAImpl_fcom_r80_by_r64 NULL
193#define iemAImpl_fsub_r80_by_r64 NULL
194#define iemAImpl_fsubr_r80_by_r64 NULL
195#define iemAImpl_fdiv_r80_by_r64 NULL
196#define iemAImpl_fdivr_r80_by_r64 NULL
197
198#define iemAImpl_fadd_r80_by_r80 NULL
199#define iemAImpl_fmul_r80_by_r80 NULL
200#define iemAImpl_fsub_r80_by_r80 NULL
201#define iemAImpl_fsubr_r80_by_r80 NULL
202#define iemAImpl_fdiv_r80_by_r80 NULL
203#define iemAImpl_fdivr_r80_by_r80 NULL
204#define iemAImpl_fprem_r80_by_r80 NULL
205#define iemAImpl_fprem1_r80_by_r80 NULL
206#define iemAImpl_fscale_r80_by_r80 NULL
207
208#define iemAImpl_fpatan_r80_by_r80 NULL
209#define iemAImpl_fyl2xp1_r80_by_r80 NULL
210
211#define iemAImpl_fcom_r80_by_r80 NULL
212#define iemAImpl_fucom_r80_by_r80 NULL
213#define iemAImpl_fabs_r80 NULL
214#define iemAImpl_fchs_r80 NULL
215#define iemAImpl_ftst_r80 NULL
216#define iemAImpl_fxam_r80 NULL
217#define iemAImpl_f2xm1_r80 NULL
218#define iemAImpl_fyl2x_r80 NULL
219#define iemAImpl_fsqrt_r80 NULL
220#define iemAImpl_frndint_r80 NULL
221#define iemAImpl_fsin_r80 NULL
222#define iemAImpl_fcos_r80 NULL
223
224#define iemAImpl_fld1 NULL
225#define iemAImpl_fldl2t NULL
226#define iemAImpl_fldl2e NULL
227#define iemAImpl_fldpi NULL
228#define iemAImpl_fldlg2 NULL
229#define iemAImpl_fldln2 NULL
230#define iemAImpl_fldz NULL
231
232#define iemAImpl_fptan_r80_r80 NULL
233#define iemAImpl_fxtract_r80_r80 NULL
234#define iemAImpl_fsincos_r80_r80 NULL
235
236#define iemAImpl_fiadd_r80_by_i16 NULL
237#define iemAImpl_fimul_r80_by_i16 NULL
238#define iemAImpl_fisub_r80_by_i16 NULL
239#define iemAImpl_fisubr_r80_by_i16 NULL
240#define iemAImpl_fidiv_r80_by_i16 NULL
241#define iemAImpl_fidivr_r80_by_i16 NULL
242
243#define iemAImpl_fiadd_r80_by_i32 NULL
244#define iemAImpl_fimul_r80_by_i32 NULL
245#define iemAImpl_fisub_r80_by_i32 NULL
246#define iemAImpl_fisubr_r80_by_i32 NULL
247#define iemAImpl_fidiv_r80_by_i32 NULL
248#define iemAImpl_fidivr_r80_by_i32 NULL
249
250#define iemCImpl_callf NULL
251#define iemCImpl_FarJmp NULL
252
253/** @} */
254
255
256#define IEM_REPEAT_0(a_Callback, a_User) do { } while (0)
257#define IEM_REPEAT_1(a_Callback, a_User) a_Callback##_CALLBACK(0, a_User)
258#define IEM_REPEAT_2(a_Callback, a_User) IEM_REPEAT_1(a_Callback, a_User); a_Callback##_CALLBACK(1, a_User)
259#define IEM_REPEAT_3(a_Callback, a_User) IEM_REPEAT_2(a_Callback, a_User); a_Callback##_CALLBACK(2, a_User)
260#define IEM_REPEAT_4(a_Callback, a_User) IEM_REPEAT_3(a_Callback, a_User); a_Callback##_CALLBACK(3, a_User)
261#define IEM_REPEAT_5(a_Callback, a_User) IEM_REPEAT_4(a_Callback, a_User); a_Callback##_CALLBACK(4, a_User)
262#define IEM_REPEAT_6(a_Callback, a_User) IEM_REPEAT_5(a_Callback, a_User); a_Callback##_CALLBACK(5, a_User)
263#define IEM_REPEAT_7(a_Callback, a_User) IEM_REPEAT_6(a_Callback, a_User); a_Callback##_CALLBACK(6, a_User)
264#define IEM_REPEAT_8(a_Callback, a_User) IEM_REPEAT_7(a_Callback, a_User); a_Callback##_CALLBACK(7, a_User)
265#define IEM_REPEAT_9(a_Callback, a_User) IEM_REPEAT_8(a_Callback, a_User); a_Callback##_CALLBACK(8, a_User)
266#define IEM_REPEAT(a_cTimes, a_Callback, a_User) RT_CONCAT(IEM_REPEAT_,a_cTimes)(a_Callback, a_User)
267
268
269
270/** @name Microcode test stubs
271 * @{ */
272
273#define IEM_ARG_CHECK_CALLBACK(a_idx, a_User) int RT_CONCAT(iArgCheck_,a_idx); NOREF(RT_CONCAT(iArgCheck_,a_idx))
274#define IEM_MC_BEGIN(a_cArgs, a_cLocals) \
275 { \
276 const uint8_t cArgs = (a_cArgs); NOREF(cArgs); \
277 const uint8_t cLocals = (a_cArgs); NOREF(cLocals); \
278 IEM_REPEAT(a_cArgs, IEM_ARG_CHECK, 0); \
279
280#define IEM_MC_END() \
281 }
282
283#define IEM_MC_PAUSE() do {} while (0)
284#define IEM_MC_CONTINUE() do {} while (0)
285#define IEM_MC_ADVANCE_RIP() do {} while (0)
286#define IEM_MC_REL_JMP_S8(a_i8) CHK_TYPE(int8_t, a_i8)
287#define IEM_MC_REL_JMP_S16(a_i16) CHK_TYPE(int16_t, a_i16)
288#define IEM_MC_REL_JMP_S32(a_i32) CHK_TYPE(int32_t, a_i32)
289#define IEM_MC_SET_RIP_U16(a_u16NewIP) CHK_TYPE(uint16_t, a_u16NewIP)
290#define IEM_MC_SET_RIP_U32(a_u32NewIP) CHK_TYPE(uint32_t, a_u32NewIP)
291#define IEM_MC_SET_RIP_U64(a_u64NewIP) CHK_TYPE(uint64_t, a_u64NewIP)
292#define IEM_MC_RAISE_DIVIDE_ERROR() return VERR_TRPM_ACTIVE_TRAP
293#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() do {} while (0)
294#define IEM_MC_MAYBE_RAISE_FPU_XCPT() do {} while (0)
295#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() do {} while (0)
296
297#define IEM_MC_LOCAL(a_Type, a_Name) \
298 a_Type a_Name; NOREF(a_Name)
299#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) \
300 a_Type const a_Name = (a_Value); \
301 NOREF(a_Name)
302#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) \
303 (a_pRefArg) = &(a_Local)
304
305#define IEM_MC_ARG(a_Type, a_Name, a_iArg) \
306 RT_CONCAT(iArgCheck_,a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
307 int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
308 AssertCompile((a_iArg) < cArgs); \
309 a_Type a_Name; \
310 NOREF(a_Name)
311#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) \
312 RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
313 int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
314 AssertCompile((a_iArg) < cArgs); \
315 a_Type const a_Name = (a_Value); \
316 NOREF(a_Name)
317#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) \
318 RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
319 int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
320 AssertCompile((a_iArg) < cArgs); \
321 a_Type const a_Name = &(a_Local); \
322 NOREF(a_Name)
323#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
324 RT_CONCAT(iArgCheck_, a_iArg) = 1; NOREF(RT_CONCAT(iArgCheck_,a_iArg)); \
325 int RT_CONCAT3(iArgCheck_,a_iArg,a_Name); NOREF(RT_CONCAT3(iArgCheck_,a_iArg,a_Name)); \
326 AssertCompile((a_iArg) < cArgs); \
327 uint32_t a_Name; \
328 uint32_t *a_pName = &a_Name; \
329 NOREF(a_pName)
330
331#define IEM_MC_COMMIT_EFLAGS(a_EFlags) CHK_TYPE(uint32_t, a_EFlags)
332#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (0)
333#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
334
335#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) do { (a_u8Dst) = 0; CHK_TYPE(uint8_t, a_u8Dst); } while (0)
336#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
337#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
338#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
339#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
340#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
341#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
342#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
343#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
344#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
345#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
346#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
347#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
348#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
349#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
350#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
351#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
352#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
353#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
354#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
355#define IEM_MC_FETCH_CR0_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
356#define IEM_MC_FETCH_CR0_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
357#define IEM_MC_FETCH_CR0_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
358#define IEM_MC_FETCH_LDTR_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
359#define IEM_MC_FETCH_LDTR_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
360#define IEM_MC_FETCH_LDTR_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
361#define IEM_MC_FETCH_TR_U16(a_u16Dst) do { (a_u16Dst) = 0; CHK_TYPE(uint16_t, a_u16Dst); } while (0)
362#define IEM_MC_FETCH_TR_U32(a_u32Dst) do { (a_u32Dst) = 0; CHK_TYPE(uint32_t, a_u32Dst); } while (0)
363#define IEM_MC_FETCH_TR_U64(a_u64Dst) do { (a_u64Dst) = 0; CHK_TYPE(uint64_t, a_u64Dst); } while (0)
364#define IEM_MC_FETCH_EFLAGS(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint32_t, a_EFlags); } while (0)
365#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) do { (a_EFlags) = 0; CHK_TYPE(uint8_t, a_EFlags); } while (0)
366#define IEM_MC_FETCH_FSW(a_u16Fsw) do { (a_u16Fsw) = 0; CHK_TYPE(uint16_t, a_u16Fsw); } while (0)
367#define IEM_MC_FETCH_FCW(a_u16Fcw) do { (a_u16Fcw) = 0; CHK_TYPE(uint16_t, a_u16Fcw); } while (0)
368#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) do { CHK_TYPE(uint8_t, a_u8Value); } while (0)
369#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) do { CHK_TYPE(uint16_t, a_u16Value); } while (0)
370#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) do { } while (0)
371#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) do { } while (0)
372#define IEM_MC_STORE_GREG_U8_CONST(a_iGReg, a_u8C) do { AssertCompile((uint8_t )(a_u8C) == (a_u8C) ); } while (0)
373#define IEM_MC_STORE_GREG_U16_CONST(a_iGReg, a_u16C) do { AssertCompile((uint16_t)(a_u16C) == (a_u16C)); } while (0)
374#define IEM_MC_STORE_GREG_U32_CONST(a_iGReg, a_u32C) do { AssertCompile((uint32_t)(a_u32C) == (a_u32C)); } while (0)
375#define IEM_MC_STORE_GREG_U64_CONST(a_iGReg, a_u64C) do { AssertCompile((uint64_t)(a_u64C) == (a_u64C)); } while (0)
376#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) do { CHK_PTYPE(PCRTFLOAT80U, a_pr80Src); Assert((a_iSt) < 8); } while (0)
377#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) do { } while (0)
378#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { CHK_PTYPE(uint32_t *, a_pu32Dst); } while (0)
379#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) do { (a_pu8Dst) = (uint8_t *)((uintptr_t)0); CHK_PTYPE(uint8_t *, a_pu8Dst); } while (0)
380#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) do { (a_pu16Dst) = (uint16_t *)((uintptr_t)0); CHK_PTYPE(uint16_t *, a_pu16Dst); } while (0)
381#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) do { (a_pu32Dst) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pu32Dst); } while (0)
382#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) do { (a_pu64Dst) = (uint64_t *)((uintptr_t)0); CHK_PTYPE(uint64_t *, a_pu64Dst); } while (0)
383#define IEM_MC_REF_EFLAGS(a_pEFlags) do { (a_pEFlags) = (uint32_t *)((uintptr_t)0); CHK_PTYPE(uint32_t *, a_pEFlags); } while (0)
384
385#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
386#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
387#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
388#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
389#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
390#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
391#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
392#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
393
394#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
395#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
396#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
397#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
398#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) do { CHK_CONST(uint8_t, a_u8Value); } while (0)
399#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) do { CHK_CONST(uint16_t, a_u16Value); } while (0)
400#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) do { CHK_CONST(uint32_t, a_u32Value); } while (0)
401#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) do { CHK_CONST(uint64_t, a_u64Value); } while (0)
402
403#ifdef _MSC_VER
404#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u8Value) += 1; /*CHK_CONST(uint8_t, a_u8Value); */ } while (0)
405#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += 1; /*CHK_CONST(uint16_t, a_u16Value);*/ } while (0)
406#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += 1; /*CHK_CONST(uint32_t, a_u32Value);*/ } while (0)
407#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += 1; /*CHK_CONST(uint64_t, a_u64Value);*/ } while (0)
408#else
409#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u8Value) += 1; CHK_CONST(uint8_t, a_u8Value); } while (0)
410#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += 1; CHK_CONST(uint16_t, a_u16Value); } while (0)
411#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += 1; CHK_CONST(uint32_t, a_u32Value); } while (0)
412#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += 1; CHK_CONST(uint64_t, a_u64Value); } while (0)
413#endif
414#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); CHK_GCPTR(a_EffAddr); } while (0)
415#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); CHK_GCPTR(a_EffAddr); } while (0)
416#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); CHK_GCPTR(a_EffAddr); } while (0)
417#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); } while (0)
418#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Local); CHK_CONST(uint16_t, a_u16Mask); } while (0)
419#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); } while (0)
420#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Local); CHK_CONST(uint64_t, a_u64Mask); } while (0)
421#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); CHK_TYPE(uint16_t, a_u16Arg); CHK_CONST(uint16_t, a_u16Mask); } while (0)
422#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Arg); CHK_CONST(uint32_t, a_u32Mask); } while (0)
423#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); CHK_TYPE(uint64_t, a_u64Arg); CHK_CONST(uint64_t, a_u64Mask); } while (0)
424#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); CHK_TYPE(uint8_t, a_u8Local); CHK_CONST(uint8_t, a_u8Mask); } while (0)
425#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); CHK_CONST(uint32_t, a_u32Mask); } while (0)
426#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); } while (0)
427#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); } while (0)
428#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); } while (0)
429#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); CHK_TYPE(int16_t, a_i16Local); CHK_CONST(uint8_t, a_cShift); } while (0)
430#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); CHK_TYPE(int32_t, a_i32Local); CHK_CONST(uint8_t, a_cShift); } while (0)
431#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); CHK_TYPE(int64_t, a_i64Local); CHK_CONST(uint8_t, a_cShift); } while (0)
432#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); } while (0)
433#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); CHK_TYPE(uint32_t, a_u32Local); } while (0)
434#define IEM_MC_SET_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
435#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
436#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { CHK_SINGLE_BIT(uint32_t, a_fBit); } while (0)
437#define IEM_MC_CLEAR_FSW_EX() do { } while (0)
438
439#define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
440#define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) do { CHK_TYPE(uint16_t, a_GCPtrMem16); } while (0)
441#define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) do { CHK_TYPE(uint32_t, a_GCPtrMem32); } while (0)
442#define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
443#define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int16_t, a_i16Dst); } while (0)
444#define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
445#define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(int32_t, a_i32Dst); } while (0)
446#define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
447#define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
448
449#define IEM_MC_FETCH_MEM_U8_DISP(a_u8Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
450 do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint8_t, a_u8Dst); } while (0)
451#define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
452 do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint16_t, a_u16Dst); } while (0)
453#define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
454 do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint32_t, a_u32Dst); } while (0)
455#define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
456 do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_offDisp); CHK_TYPE(uint64_t, a_u64Dst); } while (0)
457
458#define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT32U, a_r32Dst);} while (0)
459#define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT64U, a_r64Dst);} while (0)
460#define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(RTFLOAT80U, a_r80Dst);} while (0)
461
462#define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
463#define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
464#define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
465#define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
466#define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
467#define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
468#define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
469#define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
470#define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
471#define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
472#define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
473#define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) do { CHK_GCPTR(a_GCPtrMem); } while (0)
474#define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint8_t, a_u8Value); CHK_SEG_IDX(a_iSeg); } while (0)
475#define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint16_t, a_u16Value); } while (0)
476#define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint32_t, a_u32Value); } while (0)
477#define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) do { CHK_GCPTR(a_GCPtrMem); CHK_TYPE(uint64_t, a_u64Value); } while (0)
478#define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint8_t, a_u8C); } while (0)
479#define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint16_t, a_u16C); } while (0)
480#define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint32_t, a_u32C); } while (0)
481#define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) do { CHK_GCPTR(a_GCPtrMem); CHK_CONST(uint64_t, a_u64C); } while (0)
482#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) do { CHK_TYPE(int8_t *, a_pi8Dst); CHK_CONST(int8_t, a_i8C); } while (0)
483#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) do { CHK_TYPE(int16_t *, a_pi16Dst); CHK_CONST(int16_t, a_i16C); } while (0)
484#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) do { CHK_TYPE(int32_t *, a_pi32Dst); CHK_CONST(int32_t, a_i32C); } while (0)
485#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) do { CHK_TYPE(int64_t *, a_pi64Dst); CHK_CONST(int64_t, a_i64C); } while (0)
486#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) do { CHK_TYPE(PRTFLOAT32U, a_pr32Dst); } while (0)
487#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) do { CHK_TYPE(PRTFLOAT64U, a_pr64Dst); } while (0)
488#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) do { CHK_TYPE(PRTFLOAT80U, a_pr80Dst); } while (0)
489
490#define IEM_MC_PUSH_U16(a_u16Value) do {} while (0)
491#define IEM_MC_PUSH_U32(a_u32Value) do {} while (0)
492#define IEM_MC_PUSH_U64(a_u64Value) do {} while (0)
493#define IEM_MC_POP_U16(a_pu16Value) do {} while (0)
494#define IEM_MC_POP_U32(a_pu32Value) do {} while (0)
495#define IEM_MC_POP_U64(a_pu64Value) do {} while (0)
496#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) do { NOREF(a_fAccess); } while (0)
497#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) do {} while (0)
498#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) do {} while (0)
499#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) do {} while (0)
500#define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm) do { (a_GCPtrEff) = 0; CHK_GCPTR(a_GCPtrEff); } while (0)
501#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) do {} while (0)
502#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) do {} while (0)
503#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) do {} while (0)
504#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) do {} while (0)
505#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) do { (a_rc) = VINF_SUCCESS; } while (0)
506#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return VINF_SUCCESS
507#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return VINF_SUCCESS
508#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return VINF_SUCCESS
509#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return VINF_SUCCESS
510#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return VINF_SUCCESS
511#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (VINF_SUCCESS)
512#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (VINF_SUCCESS)
513#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (VINF_SUCCESS)
514#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (VINF_SUCCESS)
515
516#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) do { } while (0)
517#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) do { } while (0)
518#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a3) do { } while (0)
519#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) do { } while (0)
520#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) do { } while (0)
521#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) do { } while (0)
522#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) do { } while (0)
523#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) do { } while (0)
524#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) do { } while (0)
525#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0)
526#define IEM_MC_STORE_FPU_RESULT_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0)
527#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStReg) do { } while (0)
528#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0)
529#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStReg) do { } while (0)
530#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStReg, a_iEffSeg, a_GCPtrEff) do { } while (0)
531#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() do { } while (0)
532#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() do { } while (0)
533#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() do { } while (0)
534#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() do { } while (0)
535#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) do { } while (0)
536#define IEM_MC_UPDATE_FPU_OPCODE_IP() do { } while (0)
537#define IEM_MC_FPU_STACK_DEC_TOP() do { } while (0)
538#define IEM_MC_FPU_STACK_INC_TOP() do { } while (0)
539#define IEM_MC_FPU_STACK_FREE(a_iStReg) do { } while (0)
540#define IEM_MC_UPDATE_FSW(a_u16FSW) do { } while (0)
541#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) do { } while (0)
542#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { } while (0)
543#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) do { } while (0)
544#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) do { } while (0)
545#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) do { } while (0)
546#define IEM_MC_USED_FPU() do { } while (0)
547
548#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (g_fRandom) {
549#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
550#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (g_fRandom) {
551#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (g_fRandom) {
552#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) if (g_fRandom) {
553#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) if (g_fRandom) {
554#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) if (g_fRandom) {
555#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) if (g_fRandom) {
556#define IEM_MC_IF_CX_IS_NZ() if (g_fRandom) {
557#define IEM_MC_IF_ECX_IS_NZ() if (g_fRandom) {
558#define IEM_MC_IF_RCX_IS_NZ() if (g_fRandom) {
559#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
560#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
561#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) if (g_fRandom) {
562#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
563#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
564#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) if (g_fRandom) {
565#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
566#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (g_fRandom) {
567#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) if (g_fRandom) {
568#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) if (g_fRandom) {
569#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
570 a_pr80Dst = NULL; \
571 if (g_fRandom) {
572#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(p0, i0, p1, i1) \
573 p0 = NULL; \
574 p1 = NULL; \
575 if (g_fRandom) {
576#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(p0, i0, i1) \
577 p0 = NULL; \
578 if (g_fRandom) {
579#define IEM_MC_IF_FCW_IM() if (g_fRandom) {
580#define IEM_MC_ELSE() } else {
581#define IEM_MC_ENDIF() } do {} while (0)
582
583/** @} */
584
585#include "../VMMAll/IEMAllInstructions.cpp.h"
586
587
588
589/**
590 * Formalities...
591 */
592int main()
593{
594 RTTEST hTest;
595 RTEXITCODE rcExit = RTTestInitAndCreate("tstIEMCheckMc", &hTest);
596 if (rcExit == RTEXITCODE_SUCCESS)
597 {
598 RTTestBanner(hTest);
599 RTTestPrintf(hTest, RTTESTLVL_ALWAYS, "(this is only a compile test.)");
600 rcExit = RTTestSummaryAndDestroy(hTest);
601 }
602 return rcExit;
603}
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