VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/VMMTests.cpp@ 43667

Last change on this file since 43667 was 43394, checked in by vboxsync, 12 years ago

VMM: HM cleanup.
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  • Property svn:keywords set to Id Revision
File size: 24.2 KB
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1/* $Id: VMMTests.cpp 43394 2012-09-21 11:11:17Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core, Tests.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18//#define NO_SUPCALLR0VMM
19
20/*******************************************************************************
21* Header Files *
22*******************************************************************************/
23#define LOG_GROUP LOG_GROUP_VMM
24#include <iprt/asm-amd64-x86.h> /* for SUPGetCpuHzFromGIP */
25#include <VBox/vmm/vmm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/cpum.h>
28#include <VBox/dbg.h>
29#include <VBox/vmm/mm.h>
30#include <VBox/vmm/trpm.h>
31#include <VBox/vmm/selm.h>
32#include "VMMInternal.h"
33#include <VBox/vmm/vm.h>
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <VBox/vmm/hm.h>
37
38#include <iprt/assert.h>
39#include <iprt/asm.h>
40#include <iprt/time.h>
41#include <iprt/stream.h>
42#include <iprt/string.h>
43#include <iprt/x86.h>
44
45static void vmmR3TestClearStack(PVMCPU pVCpu)
46{
47 /* We leave the first 64 bytes of the stack alone because of strict
48 ring-0 long jump code uses it. */
49 memset(pVCpu->vmm.s.pbEMTStackR3 + 64, 0xaa, VMM_STACK_SIZE - 64);
50}
51
52
53/**
54 * Performs a testcase.
55 *
56 * @returns return value from the test.
57 * @param pVM Pointer to the VM.
58 * @param enmTestcase The testcase operation to perform.
59 * @param uVariation The testcase variation id.
60 */
61static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
62{
63 PVMCPU pVCpu = &pVM->aCpus[0];
64
65 RTRCPTR RCPtrEP;
66 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
67 if (RT_FAILURE(rc))
68 return rc;
69
70 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
71 vmmR3TestClearStack(pVCpu);
72 CPUMPushHyper(pVCpu, uVariation);
73 CPUMPushHyper(pVCpu, enmTestcase);
74 CPUMPushHyper(pVCpu, pVM->pVMRC);
75 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
76 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
77 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
78 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
79 if (RT_LIKELY(rc == VINF_SUCCESS))
80 rc = pVCpu->vmm.s.iLastGZRc;
81 return rc;
82}
83
84
85/**
86 * Performs a trap test.
87 *
88 * @returns Return value from the trap test.
89 * @param pVM Pointer to the VM.
90 * @param u8Trap The trap number to test.
91 * @param uVariation The testcase variation.
92 * @param rcExpect The expected result.
93 * @param u32Eax The expected eax value.
94 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
95 * @param pszDesc The test description.
96 */
97static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
98{
99 PVMCPU pVCpu = &pVM->aCpus[0];
100
101 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
102
103 RTRCPTR RCPtrEP;
104 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
105 if (RT_FAILURE(rc))
106 return rc;
107
108 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
109 vmmR3TestClearStack(pVCpu);
110 CPUMPushHyper(pVCpu, uVariation);
111 CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
112 CPUMPushHyper(pVCpu, pVM->pVMRC);
113 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
114 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
115 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
116 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
117 if (RT_LIKELY(rc == VINF_SUCCESS))
118 rc = pVCpu->vmm.s.iLastGZRc;
119 bool fDump = false;
120 if (rc != rcExpect)
121 {
122 RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
123 if (rc != VERR_NOT_IMPLEMENTED)
124 fDump = true;
125 }
126 else if ( rcExpect != VINF_SUCCESS
127 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
128 && u8Trap != 3 /* guest only, we're not in guest. */
129 && u8Trap != 1 /* guest only, we're not in guest. */
130 && u8Trap != TRPMGetTrapNo(pVCpu))
131 {
132 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
133 fDump = true;
134 }
135 else if (pszFaultEIP)
136 {
137 RTRCPTR RCPtrFault;
138 int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
139 if (RT_FAILURE(rc2))
140 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
141 else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
142 {
143 RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
144 fDump = true;
145 }
146 }
147 else if (rcExpect != VINF_SUCCESS)
148 {
149 if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
150 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
151 if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
152 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
153 if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
154 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
155 if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
156 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
157 if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
158 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
159 if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
160 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
161 if (CPUMGetHyperESI(pVCpu) == 0x42000042)
162 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
163 if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
164 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
165 if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
166 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
167 if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
168 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
169 if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
170 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
171 if (CPUMGetHyperEAX(pVCpu) == u32Eax)
172 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
173 }
174 if (fDump)
175 VMMR3FatalDump(pVM, pVCpu, rc);
176 return rc;
177}
178
179
180/* execute the switch. */
181VMMR3DECL(int) VMMDoTest(PVM pVM)
182{
183#if 1
184 PVMCPU pVCpu = &pVM->aCpus[0];
185
186#ifdef NO_SUPCALLR0VMM
187 RTPrintf("NO_SUPCALLR0VMM\n");
188 return VINF_SUCCESS;
189#endif
190
191 /*
192 * Setup stack for calling VMMGCEntry().
193 */
194 RTRCPTR RCPtrEP;
195 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
196 if (RT_SUCCESS(rc))
197 {
198 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
199
200 /*
201 * Test various crashes which we must be able to recover from.
202 */
203 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
204 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
205
206#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
207 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
208 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
209 bool f;
210 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
211#if !defined(DEBUG_bird)
212 if (RT_SUCCESS(rc) && f)
213#endif
214 {
215 /* see triple fault warnings in SELM and VMMGC.cpp. */
216 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
217 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
218 }
219#endif
220
221 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
222 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
223 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
224
225 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
226 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
227 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
228 /* This test is no longer relevant as fs and gs are loaded with NULL
229 selectors and we will always return to HC if a #GP occurs while
230 returning to guest code.
231 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
232 */
233
234 /*
235 * Set a debug register and perform a context switch.
236 */
237 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
238 if (rc != VINF_SUCCESS)
239 {
240 RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
241 return rc;
242 }
243
244 /* a harmless breakpoint */
245 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
246 DBGFADDRESS Addr;
247 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
248 RTUINT iBp0;
249 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
250 AssertReleaseRC(rc);
251 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
252 if (rc != VINF_SUCCESS)
253 {
254 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
255 return rc;
256 }
257
258 /* a bad one at VMMGCEntry */
259 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
260 DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
261 RTUINT iBp1;
262 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
263 AssertReleaseRC(rc);
264 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
265 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
266 {
267 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
268 return rc;
269 }
270
271 /* resume the breakpoint */
272 RTPrintf("VMM: resuming hyper after breakpoint\n");
273 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
274 rc = VMMR3ResumeHyper(pVM, pVCpu);
275 if (rc != VINF_SUCCESS)
276 {
277 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc = KNOWN BUG\n", rc); /** @todo fix VMMR3ResumeHyper */
278 return rc;
279 }
280
281 /* engage the breakpoint again and try single stepping. */
282 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
283 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
284 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
285 {
286 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
287 return rc;
288 }
289
290 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
291 RTPrintf("%RGr=>", OldPc);
292 unsigned i;
293 for (i = 0; i < 8; i++)
294 {
295 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
296 rc = VMMR3ResumeHyper(pVM, pVCpu);
297 if (rc != VINF_EM_DBG_HYPER_STEPPED)
298 {
299 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
300 return rc;
301 }
302 RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
303 RTPrintf("%RGr=>", Pc);
304 if (Pc == OldPc)
305 {
306 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
307 return VERR_GENERAL_FAILURE;
308 }
309 OldPc = Pc;
310 }
311 RTPrintf("ok\n");
312
313 /* done, clear it */
314 if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
315 || RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
316 {
317 RTPrintf("VMM: Failed to clear breakpoints!\n");
318 return VERR_GENERAL_FAILURE;
319 }
320 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
321 if (rc != VINF_SUCCESS)
322 {
323 RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
324 return rc;
325 }
326
327 /*
328 * Interrupt masking.
329 */
330 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
331 for (i = 0; i < 10000; i++)
332 {
333 uint64_t StartTick = ASMReadTSC();
334 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
335 if (rc != VINF_SUCCESS)
336 {
337 RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
338 return rc;
339 }
340 uint64_t Ticks = ASMReadTSC() - StartTick;
341 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
342 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
343 }
344
345 /*
346 * Interrupt forwarding.
347 */
348 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
349 CPUMPushHyper(pVCpu, 0);
350 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
351 CPUMPushHyper(pVCpu, pVM->pVMRC);
352 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
353 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
354 Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
355
356 /*
357 * Switch and do da thing.
358 */
359 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
360 i = 0;
361 uint64_t tsBegin = RTTimeNanoTS();
362 uint64_t TickStart = ASMReadTSC();
363 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
364 do
365 {
366 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
367 if (RT_LIKELY(rc == VINF_SUCCESS))
368 rc = pVCpu->vmm.s.iLastGZRc;
369 if (RT_FAILURE(rc))
370 {
371 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
372 VMMR3FatalDump(pVM, pVCpu, rc);
373 return rc;
374 }
375 i++;
376 if (!(i % 32))
377 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
378 i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
379 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
380 uint64_t TickEnd = ASMReadTSC();
381 uint64_t tsEnd = RTTimeNanoTS();
382
383 uint64_t Elapsed = tsEnd - tsBegin;
384 uint64_t PerIteration = Elapsed / (uint64_t)i;
385 uint64_t cTicksElapsed = TickEnd - TickStart;
386 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
387
388 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
389 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
390 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
391 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
392
393 /*
394 * These forced actions are not necessary for the test and trigger breakpoints too.
395 */
396 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
397 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
398
399 /*
400 * Profile switching.
401 */
402 RTPrintf("VMM: profiling switcher...\n");
403 Log(("VMM: profiling switcher...\n"));
404 uint64_t TickMin = ~0;
405 tsBegin = RTTimeNanoTS();
406 TickStart = ASMReadTSC();
407 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
408 for (i = 0; i < 1000000; i++)
409 {
410 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
411 CPUMPushHyper(pVCpu, 0);
412 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
413 CPUMPushHyper(pVCpu, pVM->pVMRC);
414 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
415 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
416
417 uint64_t TickThisStart = ASMReadTSC();
418 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
419 if (RT_LIKELY(rc == VINF_SUCCESS))
420 rc = pVCpu->vmm.s.iLastGZRc;
421 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
422 if (RT_FAILURE(rc))
423 {
424 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
425 VMMR3FatalDump(pVM, pVCpu, rc);
426 return rc;
427 }
428 if (TickThisElapsed < TickMin)
429 TickMin = TickThisElapsed;
430 }
431 TickEnd = ASMReadTSC();
432 tsEnd = RTTimeNanoTS();
433
434 Elapsed = tsEnd - tsBegin;
435 PerIteration = Elapsed / (uint64_t)i;
436 cTicksElapsed = TickEnd - TickStart;
437 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
438
439 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
440 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
441 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
442 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
443
444 rc = VINF_SUCCESS;
445 }
446 else
447 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
448#endif
449 return rc;
450}
451
452#define SYNC_SEL(pHyperCtx, reg) \
453 if (pHyperCtx->reg.Sel) \
454 { \
455 DBGFSELINFO selInfo; \
456 int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg.Sel, &selInfo); \
457 AssertRC(rc2); \
458 \
459 pHyperCtx->reg.u64Base = selInfo.GCPtrBase; \
460 pHyperCtx->reg.u32Limit = selInfo.cbLimit; \
461 pHyperCtx->reg.Attr.n.u1Present = selInfo.u.Raw.Gen.u1Present; \
462 pHyperCtx->reg.Attr.n.u1DefBig = selInfo.u.Raw.Gen.u1DefBig; \
463 pHyperCtx->reg.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
464 pHyperCtx->reg.Attr.n.u4Type = selInfo.u.Raw.Gen.u4Type; \
465 pHyperCtx->reg.Attr.n.u2Dpl = selInfo.u.Raw.Gen.u2Dpl; \
466 pHyperCtx->reg.Attr.n.u1DescType = selInfo.u.Raw.Gen.u1DescType; \
467 pHyperCtx->reg.Attr.n.u1Long = selInfo.u.Raw.Gen.u1Long; \
468 }
469
470/* execute the switch. */
471VMMR3DECL(int) VMMDoHmTest(PVM pVM)
472{
473 uint32_t i;
474 int rc;
475 PCPUMCTX pHyperCtx, pGuestCtx;
476 RTGCPHYS CR3Phys = 0x0; /* fake address */
477 PVMCPU pVCpu = &pVM->aCpus[0];
478
479 if (!HMR3IsAllowed(pVM))
480 {
481 RTPrintf("VMM: Hardware accelerated test not available!\n");
482 return VERR_ACCESS_DENIED;
483 }
484
485 /*
486 * These forced actions are not necessary for the test and trigger breakpoints too.
487 */
488 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
489 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
490
491 /* Enable mapping of the hypervisor into the shadow page table. */
492 uint32_t cb;
493 rc = PGMR3MappingsSize(pVM, &cb);
494 AssertRCReturn(rc, rc);
495
496 /* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
497 rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
498 AssertRCReturn(rc, rc);
499
500 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
501
502 pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
503 pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
504 PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
505 PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
506
507 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
508 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
509 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
510 VM_FF_CLEAR(pVM, VM_FF_REQUEST);
511
512 /*
513 * Setup stack for calling VMMGCEntry().
514 */
515 RTRCPTR RCPtrEP;
516 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
517 if (RT_SUCCESS(rc))
518 {
519 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
520
521 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
522
523 /* Fill in hidden selector registers for the hypervisor state. */
524 SYNC_SEL(pHyperCtx, cs);
525 SYNC_SEL(pHyperCtx, ds);
526 SYNC_SEL(pHyperCtx, es);
527 SYNC_SEL(pHyperCtx, fs);
528 SYNC_SEL(pHyperCtx, gs);
529 SYNC_SEL(pHyperCtx, ss);
530 SYNC_SEL(pHyperCtx, tr);
531
532 /*
533 * Profile switching.
534 */
535 RTPrintf("VMM: profiling switcher...\n");
536 Log(("VMM: profiling switcher...\n"));
537 uint64_t TickMin = ~0;
538 uint64_t tsBegin = RTTimeNanoTS();
539 uint64_t TickStart = ASMReadTSC();
540 for (i = 0; i < 1000000; i++)
541 {
542 CPUMSetHyperState(pVCpu, pVM->vmm.s.pfnCallTrampolineRC, pVCpu->vmm.s.pbEMTStackBottomRC, 0, 0);
543 CPUMPushHyper(pVCpu, 0);
544 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HM_NOP);
545 CPUMPushHyper(pVCpu, pVM->pVMRC);
546 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
547 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
548
549 pHyperCtx = CPUMGetHyperCtxPtr(pVCpu);
550 pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
551
552 /* Copy the hypervisor context to make sure we have a valid guest context. */
553 *pGuestCtx = *pHyperCtx;
554 pGuestCtx->cr3 = CR3Phys;
555
556 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
557 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
558 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
559
560 uint64_t TickThisStart = ASMReadTSC();
561 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HM_RUN, 0);
562 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
563 if (RT_FAILURE(rc))
564 {
565 Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
566 VMMR3FatalDump(pVM, pVCpu, rc);
567 return rc;
568 }
569 if (TickThisElapsed < TickMin)
570 TickMin = TickThisElapsed;
571 }
572 uint64_t TickEnd = ASMReadTSC();
573 uint64_t tsEnd = RTTimeNanoTS();
574
575 uint64_t Elapsed = tsEnd - tsBegin;
576 uint64_t PerIteration = Elapsed / (uint64_t)i;
577 uint64_t cTicksElapsed = TickEnd - TickStart;
578 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
579
580 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
581 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
582 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
583 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
584
585 rc = VINF_SUCCESS;
586 }
587 else
588 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
589
590 return rc;
591}
592
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