VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/TRPM.cpp@ 74795

Last change on this file since 74795 was 74789, checked in by vboxsync, 6 years ago

vm.h,VMM,REM: s/VMCPU_FF_IS_PENDING/VMCPU_FF_IS_ANY_SET/g to emphasize the plurality of the flags argument and encourage using VMCPU_FF_IS_SET. bugref:9180
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 81.6 KB
Line 
1/* $Id: TRPM.cpp 74789 2018-10-12 10:34:32Z vboxsync $ */
2/** @file
3 * TRPM - The Trap Monitor.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_trpm TRPM - The Trap Monitor
19 *
20 * The Trap Monitor (TRPM) is responsible for all trap and interrupt handling in
21 * the VMM. It plays a major role in raw-mode execution and a lesser one in the
22 * hardware assisted mode.
23 *
24 * Note first, the following will use trap as a collective term for faults,
25 * aborts and traps.
26 *
27 * @see grp_trpm
28 *
29 *
30 * @section sec_trpm_rc Raw-Mode Context
31 *
32 * When executing in the raw-mode context, TRPM will be managing the IDT and
33 * processing all traps and interrupts. It will also monitor the guest IDT
34 * because CSAM wishes to know about changes to it (trap/interrupt/syscall
35 * handler patching) and TRPM needs to keep the \#BP gate in sync (ring-3
36 * considerations). See TRPMR3SyncIDT and CSAMR3CheckGates.
37 *
38 * External interrupts will be forwarded to the host context by the quickest
39 * possible route where they will be reasserted. The other events will be
40 * categorized into virtualization traps, genuine guest traps and hypervisor
41 * traps. The latter group may be recoverable depending on when they happen and
42 * whether there is a handler for it, otherwise it will cause a guru meditation.
43 *
44 * TRPM distinguishes the between the first two (virt and guest traps) and the
45 * latter (hyper) by checking the CPL of the trapping code, if CPL == 0 then
46 * it's a hyper trap otherwise it's a virt/guest trap. There are three trap
47 * dispatcher tables, one ad-hoc for one time traps registered via
48 * TRPMGCSetTempHandler(), one for hyper traps and one for virt/guest traps.
49 * The latter two live in TRPMGCHandlersA.asm, the former in the VM structure.
50 *
51 * The raw-mode context trap handlers found in TRPMGCHandlers.cpp (for the most
52 * part), will call up the other VMM sub-systems depending on what it things
53 * happens. The two most busy traps are page faults (\#PF) and general
54 * protection fault/trap (\#GP).
55 *
56 * Before resuming guest code after having taken a virtualization trap or
57 * injected a guest trap, TRPM will check for pending forced action and
58 * every now and again let TM check for timed out timers. This allows code that
59 * is being executed as part of virtualization traps to signal ring-3 exits,
60 * page table resyncs and similar without necessarily using the status code. It
61 * also make sure we're more responsive to timers and requests from other
62 * threads (necessarily running on some different core/cpu in most cases).
63 *
64 *
65 * @section sec_trpm_all All Contexts
66 *
67 * TRPM will also dispatch / inject interrupts and traps to the guest, both when
68 * in raw-mode and when in hardware assisted mode. See TRPMInject().
69 *
70 */
71
72
73/*********************************************************************************************************************************
74* Header Files *
75*********************************************************************************************************************************/
76#define LOG_GROUP LOG_GROUP_TRPM
77#include <VBox/vmm/trpm.h>
78#include <VBox/vmm/cpum.h>
79#include <VBox/vmm/selm.h>
80#include <VBox/vmm/ssm.h>
81#include <VBox/vmm/pdmapi.h>
82#include <VBox/vmm/em.h>
83#include <VBox/vmm/pgm.h>
84#include <VBox/vmm/dbgf.h>
85#include <VBox/vmm/mm.h>
86#include <VBox/vmm/stam.h>
87#include <VBox/vmm/csam.h>
88#include <VBox/vmm/patm.h>
89#include <VBox/vmm/iem.h>
90#include "TRPMInternal.h"
91#include <VBox/vmm/vm.h>
92#include <VBox/vmm/em.h>
93#ifdef VBOX_WITH_REM
94# include <VBox/vmm/rem.h>
95#endif
96#include <VBox/vmm/hm.h>
97
98#include <VBox/err.h>
99#include <VBox/param.h>
100#include <VBox/log.h>
101#include <iprt/assert.h>
102#include <iprt/asm.h>
103#include <iprt/string.h>
104#include <iprt/alloc.h>
105
106
107/*********************************************************************************************************************************
108* Structures and Typedefs *
109*********************************************************************************************************************************/
110/**
111 * Trap handler function.
112 * @todo need to specialize this as we go along.
113 */
114typedef enum TRPMHANDLER
115{
116 /** Generic Interrupt handler. */
117 TRPM_HANDLER_INT = 0,
118 /** Generic Trap handler. */
119 TRPM_HANDLER_TRAP,
120 /** Trap 8 (\#DF) handler. */
121 TRPM_HANDLER_TRAP_08,
122 /** Trap 12 (\#MC) handler. */
123 TRPM_HANDLER_TRAP_12,
124 /** Max. */
125 TRPM_HANDLER_MAX
126} TRPMHANDLER, *PTRPMHANDLER;
127
128
129/*********************************************************************************************************************************
130* Global Variables *
131*********************************************************************************************************************************/
132/** Preinitialized IDT.
133 * The u16OffsetLow is a value of the TRPMHANDLER enum which TRPMR3Relocate()
134 * will use to pick the right address. The u16SegSel is always VMM CS.
135 */
136static VBOXIDTE_GENERIC g_aIdt[256] =
137{
138/* special trap handler - still, this is an interrupt gate not a trap gate... */
139#define IDTE_TRAP(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
140/* generic trap handler. */
141#define IDTE_TRAP_GEN() IDTE_TRAP(TRPM_HANDLER_TRAP)
142/* special interrupt handler. */
143#define IDTE_INT(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_INT_32, 0, 1, 0 }
144/* generic interrupt handler. */
145#define IDTE_INT_GEN() IDTE_INT(TRPM_HANDLER_INT)
146/* special task gate IDT entry (for critical exceptions like #DF). */
147#define IDTE_TASK(enm) { (unsigned)enm, 0, 0, VBOX_IDTE_TYPE1, VBOX_IDTE_TYPE2_TASK, 0, 1, 0 }
148/* draft, fixme later when the handler is written. */
149#define IDTE_RESERVED() { 0, 0, 0, 0, 0, 0, 0, 0 }
150
151 /* N - M M - T - C - D i */
152 /* o - n o - y - o - e p */
153 /* - e n - p - d - s t */
154 /* - i - e - e - c . */
155 /* - c - - - r */
156 /* ============================================================= */
157 IDTE_TRAP_GEN(), /* 0 - #DE - F - N - Divide error */
158 IDTE_TRAP_GEN(), /* 1 - #DB - F/T - N - Single step, INT 1 instruction */
159#ifdef VBOX_WITH_NMI
160 IDTE_TRAP_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
161#else
162 IDTE_INT_GEN(), /* 2 - - I - N - Non-Maskable Interrupt (NMI) */
163#endif
164 IDTE_TRAP_GEN(), /* 3 - #BP - T - N - Breakpoint, INT 3 instruction. */
165 IDTE_TRAP_GEN(), /* 4 - #OF - T - N - Overflow, INTO instruction. */
166 IDTE_TRAP_GEN(), /* 5 - #BR - F - N - BOUND Range Exceeded, BOUND instruction. */
167 IDTE_TRAP_GEN(), /* 6 - #UD - F - N - Undefined(/Invalid) Opcode. */
168 IDTE_TRAP_GEN(), /* 7 - #NM - F - N - Device not available, FP or (F)WAIT instruction. */
169 IDTE_TASK(TRPM_HANDLER_TRAP_08), /* 8 - #DF - A - 0 - Double fault. */
170 IDTE_TRAP_GEN(), /* 9 - - F - N - Coprocessor Segment Overrun (obsolete). */
171 IDTE_TRAP_GEN(), /* a - #TS - F - Y - Invalid TSS, Taskswitch or TSS access. */
172 IDTE_TRAP_GEN(), /* b - #NP - F - Y - Segment not present. */
173 IDTE_TRAP_GEN(), /* c - #SS - F - Y - Stack-Segment fault. */
174 IDTE_TRAP_GEN(), /* d - #GP - F - Y - General protection fault. */
175 IDTE_TRAP_GEN(), /* e - #PF - F - Y - Page fault. - interrupt gate!!! */
176 IDTE_RESERVED(), /* f - - - - Intel Reserved. Do not use. */
177 IDTE_TRAP_GEN(), /* 10 - #MF - F - N - x86 FPU Floating-Point Error (Math fault), FP or (F)WAIT instruction. */
178 IDTE_TRAP_GEN(), /* 11 - #AC - F - 0 - Alignment Check. */
179 IDTE_TRAP(TRPM_HANDLER_TRAP_12), /* 12 - #MC - A - N - Machine Check. */
180 IDTE_TRAP_GEN(), /* 13 - #XF - F - N - SIMD Floating-Point Exception. */
181 IDTE_RESERVED(), /* 14 - - - - Intel Reserved. Do not use. */
182 IDTE_RESERVED(), /* 15 - - - - Intel Reserved. Do not use. */
183 IDTE_RESERVED(), /* 16 - - - - Intel Reserved. Do not use. */
184 IDTE_RESERVED(), /* 17 - - - - Intel Reserved. Do not use. */
185 IDTE_RESERVED(), /* 18 - - - - Intel Reserved. Do not use. */
186 IDTE_RESERVED(), /* 19 - - - - Intel Reserved. Do not use. */
187 IDTE_RESERVED(), /* 1a - - - - Intel Reserved. Do not use. */
188 IDTE_RESERVED(), /* 1b - - - - Intel Reserved. Do not use. */
189 IDTE_RESERVED(), /* 1c - - - - Intel Reserved. Do not use. */
190 IDTE_RESERVED(), /* 1d - - - - Intel Reserved. Do not use. */
191 IDTE_RESERVED(), /* 1e - - - - Intel Reserved. Do not use. */
192 IDTE_RESERVED(), /* 1f - - - - Intel Reserved. Do not use. */
193 IDTE_INT_GEN(), /* 20 - - I - - User defined Interrupts, external of INT n. */
194 IDTE_INT_GEN(), /* 21 - - I - - User defined Interrupts, external of INT n. */
195 IDTE_INT_GEN(), /* 22 - - I - - User defined Interrupts, external of INT n. */
196 IDTE_INT_GEN(), /* 23 - - I - - User defined Interrupts, external of INT n. */
197 IDTE_INT_GEN(), /* 24 - - I - - User defined Interrupts, external of INT n. */
198 IDTE_INT_GEN(), /* 25 - - I - - User defined Interrupts, external of INT n. */
199 IDTE_INT_GEN(), /* 26 - - I - - User defined Interrupts, external of INT n. */
200 IDTE_INT_GEN(), /* 27 - - I - - User defined Interrupts, external of INT n. */
201 IDTE_INT_GEN(), /* 28 - - I - - User defined Interrupts, external of INT n. */
202 IDTE_INT_GEN(), /* 29 - - I - - User defined Interrupts, external of INT n. */
203 IDTE_INT_GEN(), /* 2a - - I - - User defined Interrupts, external of INT n. */
204 IDTE_INT_GEN(), /* 2b - - I - - User defined Interrupts, external of INT n. */
205 IDTE_INT_GEN(), /* 2c - - I - - User defined Interrupts, external of INT n. */
206 IDTE_INT_GEN(), /* 2d - - I - - User defined Interrupts, external of INT n. */
207 IDTE_INT_GEN(), /* 2e - - I - - User defined Interrupts, external of INT n. */
208 IDTE_INT_GEN(), /* 2f - - I - - User defined Interrupts, external of INT n. */
209 IDTE_INT_GEN(), /* 30 - - I - - User defined Interrupts, external of INT n. */
210 IDTE_INT_GEN(), /* 31 - - I - - User defined Interrupts, external of INT n. */
211 IDTE_INT_GEN(), /* 32 - - I - - User defined Interrupts, external of INT n. */
212 IDTE_INT_GEN(), /* 33 - - I - - User defined Interrupts, external of INT n. */
213 IDTE_INT_GEN(), /* 34 - - I - - User defined Interrupts, external of INT n. */
214 IDTE_INT_GEN(), /* 35 - - I - - User defined Interrupts, external of INT n. */
215 IDTE_INT_GEN(), /* 36 - - I - - User defined Interrupts, external of INT n. */
216 IDTE_INT_GEN(), /* 37 - - I - - User defined Interrupts, external of INT n. */
217 IDTE_INT_GEN(), /* 38 - - I - - User defined Interrupts, external of INT n. */
218 IDTE_INT_GEN(), /* 39 - - I - - User defined Interrupts, external of INT n. */
219 IDTE_INT_GEN(), /* 3a - - I - - User defined Interrupts, external of INT n. */
220 IDTE_INT_GEN(), /* 3b - - I - - User defined Interrupts, external of INT n. */
221 IDTE_INT_GEN(), /* 3c - - I - - User defined Interrupts, external of INT n. */
222 IDTE_INT_GEN(), /* 3d - - I - - User defined Interrupts, external of INT n. */
223 IDTE_INT_GEN(), /* 3e - - I - - User defined Interrupts, external of INT n. */
224 IDTE_INT_GEN(), /* 3f - - I - - User defined Interrupts, external of INT n. */
225 IDTE_INT_GEN(), /* 40 - - I - - User defined Interrupts, external of INT n. */
226 IDTE_INT_GEN(), /* 41 - - I - - User defined Interrupts, external of INT n. */
227 IDTE_INT_GEN(), /* 42 - - I - - User defined Interrupts, external of INT n. */
228 IDTE_INT_GEN(), /* 43 - - I - - User defined Interrupts, external of INT n. */
229 IDTE_INT_GEN(), /* 44 - - I - - User defined Interrupts, external of INT n. */
230 IDTE_INT_GEN(), /* 45 - - I - - User defined Interrupts, external of INT n. */
231 IDTE_INT_GEN(), /* 46 - - I - - User defined Interrupts, external of INT n. */
232 IDTE_INT_GEN(), /* 47 - - I - - User defined Interrupts, external of INT n. */
233 IDTE_INT_GEN(), /* 48 - - I - - User defined Interrupts, external of INT n. */
234 IDTE_INT_GEN(), /* 49 - - I - - User defined Interrupts, external of INT n. */
235 IDTE_INT_GEN(), /* 4a - - I - - User defined Interrupts, external of INT n. */
236 IDTE_INT_GEN(), /* 4b - - I - - User defined Interrupts, external of INT n. */
237 IDTE_INT_GEN(), /* 4c - - I - - User defined Interrupts, external of INT n. */
238 IDTE_INT_GEN(), /* 4d - - I - - User defined Interrupts, external of INT n. */
239 IDTE_INT_GEN(), /* 4e - - I - - User defined Interrupts, external of INT n. */
240 IDTE_INT_GEN(), /* 4f - - I - - User defined Interrupts, external of INT n. */
241 IDTE_INT_GEN(), /* 50 - - I - - User defined Interrupts, external of INT n. */
242 IDTE_INT_GEN(), /* 51 - - I - - User defined Interrupts, external of INT n. */
243 IDTE_INT_GEN(), /* 52 - - I - - User defined Interrupts, external of INT n. */
244 IDTE_INT_GEN(), /* 53 - - I - - User defined Interrupts, external of INT n. */
245 IDTE_INT_GEN(), /* 54 - - I - - User defined Interrupts, external of INT n. */
246 IDTE_INT_GEN(), /* 55 - - I - - User defined Interrupts, external of INT n. */
247 IDTE_INT_GEN(), /* 56 - - I - - User defined Interrupts, external of INT n. */
248 IDTE_INT_GEN(), /* 57 - - I - - User defined Interrupts, external of INT n. */
249 IDTE_INT_GEN(), /* 58 - - I - - User defined Interrupts, external of INT n. */
250 IDTE_INT_GEN(), /* 59 - - I - - User defined Interrupts, external of INT n. */
251 IDTE_INT_GEN(), /* 5a - - I - - User defined Interrupts, external of INT n. */
252 IDTE_INT_GEN(), /* 5b - - I - - User defined Interrupts, external of INT n. */
253 IDTE_INT_GEN(), /* 5c - - I - - User defined Interrupts, external of INT n. */
254 IDTE_INT_GEN(), /* 5d - - I - - User defined Interrupts, external of INT n. */
255 IDTE_INT_GEN(), /* 5e - - I - - User defined Interrupts, external of INT n. */
256 IDTE_INT_GEN(), /* 5f - - I - - User defined Interrupts, external of INT n. */
257 IDTE_INT_GEN(), /* 60 - - I - - User defined Interrupts, external of INT n. */
258 IDTE_INT_GEN(), /* 61 - - I - - User defined Interrupts, external of INT n. */
259 IDTE_INT_GEN(), /* 62 - - I - - User defined Interrupts, external of INT n. */
260 IDTE_INT_GEN(), /* 63 - - I - - User defined Interrupts, external of INT n. */
261 IDTE_INT_GEN(), /* 64 - - I - - User defined Interrupts, external of INT n. */
262 IDTE_INT_GEN(), /* 65 - - I - - User defined Interrupts, external of INT n. */
263 IDTE_INT_GEN(), /* 66 - - I - - User defined Interrupts, external of INT n. */
264 IDTE_INT_GEN(), /* 67 - - I - - User defined Interrupts, external of INT n. */
265 IDTE_INT_GEN(), /* 68 - - I - - User defined Interrupts, external of INT n. */
266 IDTE_INT_GEN(), /* 69 - - I - - User defined Interrupts, external of INT n. */
267 IDTE_INT_GEN(), /* 6a - - I - - User defined Interrupts, external of INT n. */
268 IDTE_INT_GEN(), /* 6b - - I - - User defined Interrupts, external of INT n. */
269 IDTE_INT_GEN(), /* 6c - - I - - User defined Interrupts, external of INT n. */
270 IDTE_INT_GEN(), /* 6d - - I - - User defined Interrupts, external of INT n. */
271 IDTE_INT_GEN(), /* 6e - - I - - User defined Interrupts, external of INT n. */
272 IDTE_INT_GEN(), /* 6f - - I - - User defined Interrupts, external of INT n. */
273 IDTE_INT_GEN(), /* 70 - - I - - User defined Interrupts, external of INT n. */
274 IDTE_INT_GEN(), /* 71 - - I - - User defined Interrupts, external of INT n. */
275 IDTE_INT_GEN(), /* 72 - - I - - User defined Interrupts, external of INT n. */
276 IDTE_INT_GEN(), /* 73 - - I - - User defined Interrupts, external of INT n. */
277 IDTE_INT_GEN(), /* 74 - - I - - User defined Interrupts, external of INT n. */
278 IDTE_INT_GEN(), /* 75 - - I - - User defined Interrupts, external of INT n. */
279 IDTE_INT_GEN(), /* 76 - - I - - User defined Interrupts, external of INT n. */
280 IDTE_INT_GEN(), /* 77 - - I - - User defined Interrupts, external of INT n. */
281 IDTE_INT_GEN(), /* 78 - - I - - User defined Interrupts, external of INT n. */
282 IDTE_INT_GEN(), /* 79 - - I - - User defined Interrupts, external of INT n. */
283 IDTE_INT_GEN(), /* 7a - - I - - User defined Interrupts, external of INT n. */
284 IDTE_INT_GEN(), /* 7b - - I - - User defined Interrupts, external of INT n. */
285 IDTE_INT_GEN(), /* 7c - - I - - User defined Interrupts, external of INT n. */
286 IDTE_INT_GEN(), /* 7d - - I - - User defined Interrupts, external of INT n. */
287 IDTE_INT_GEN(), /* 7e - - I - - User defined Interrupts, external of INT n. */
288 IDTE_INT_GEN(), /* 7f - - I - - User defined Interrupts, external of INT n. */
289 IDTE_INT_GEN(), /* 80 - - I - - User defined Interrupts, external of INT n. */
290 IDTE_INT_GEN(), /* 81 - - I - - User defined Interrupts, external of INT n. */
291 IDTE_INT_GEN(), /* 82 - - I - - User defined Interrupts, external of INT n. */
292 IDTE_INT_GEN(), /* 83 - - I - - User defined Interrupts, external of INT n. */
293 IDTE_INT_GEN(), /* 84 - - I - - User defined Interrupts, external of INT n. */
294 IDTE_INT_GEN(), /* 85 - - I - - User defined Interrupts, external of INT n. */
295 IDTE_INT_GEN(), /* 86 - - I - - User defined Interrupts, external of INT n. */
296 IDTE_INT_GEN(), /* 87 - - I - - User defined Interrupts, external of INT n. */
297 IDTE_INT_GEN(), /* 88 - - I - - User defined Interrupts, external of INT n. */
298 IDTE_INT_GEN(), /* 89 - - I - - User defined Interrupts, external of INT n. */
299 IDTE_INT_GEN(), /* 8a - - I - - User defined Interrupts, external of INT n. */
300 IDTE_INT_GEN(), /* 8b - - I - - User defined Interrupts, external of INT n. */
301 IDTE_INT_GEN(), /* 8c - - I - - User defined Interrupts, external of INT n. */
302 IDTE_INT_GEN(), /* 8d - - I - - User defined Interrupts, external of INT n. */
303 IDTE_INT_GEN(), /* 8e - - I - - User defined Interrupts, external of INT n. */
304 IDTE_INT_GEN(), /* 8f - - I - - User defined Interrupts, external of INT n. */
305 IDTE_INT_GEN(), /* 90 - - I - - User defined Interrupts, external of INT n. */
306 IDTE_INT_GEN(), /* 91 - - I - - User defined Interrupts, external of INT n. */
307 IDTE_INT_GEN(), /* 92 - - I - - User defined Interrupts, external of INT n. */
308 IDTE_INT_GEN(), /* 93 - - I - - User defined Interrupts, external of INT n. */
309 IDTE_INT_GEN(), /* 94 - - I - - User defined Interrupts, external of INT n. */
310 IDTE_INT_GEN(), /* 95 - - I - - User defined Interrupts, external of INT n. */
311 IDTE_INT_GEN(), /* 96 - - I - - User defined Interrupts, external of INT n. */
312 IDTE_INT_GEN(), /* 97 - - I - - User defined Interrupts, external of INT n. */
313 IDTE_INT_GEN(), /* 98 - - I - - User defined Interrupts, external of INT n. */
314 IDTE_INT_GEN(), /* 99 - - I - - User defined Interrupts, external of INT n. */
315 IDTE_INT_GEN(), /* 9a - - I - - User defined Interrupts, external of INT n. */
316 IDTE_INT_GEN(), /* 9b - - I - - User defined Interrupts, external of INT n. */
317 IDTE_INT_GEN(), /* 9c - - I - - User defined Interrupts, external of INT n. */
318 IDTE_INT_GEN(), /* 9d - - I - - User defined Interrupts, external of INT n. */
319 IDTE_INT_GEN(), /* 9e - - I - - User defined Interrupts, external of INT n. */
320 IDTE_INT_GEN(), /* 9f - - I - - User defined Interrupts, external of INT n. */
321 IDTE_INT_GEN(), /* a0 - - I - - User defined Interrupts, external of INT n. */
322 IDTE_INT_GEN(), /* a1 - - I - - User defined Interrupts, external of INT n. */
323 IDTE_INT_GEN(), /* a2 - - I - - User defined Interrupts, external of INT n. */
324 IDTE_INT_GEN(), /* a3 - - I - - User defined Interrupts, external of INT n. */
325 IDTE_INT_GEN(), /* a4 - - I - - User defined Interrupts, external of INT n. */
326 IDTE_INT_GEN(), /* a5 - - I - - User defined Interrupts, external of INT n. */
327 IDTE_INT_GEN(), /* a6 - - I - - User defined Interrupts, external of INT n. */
328 IDTE_INT_GEN(), /* a7 - - I - - User defined Interrupts, external of INT n. */
329 IDTE_INT_GEN(), /* a8 - - I - - User defined Interrupts, external of INT n. */
330 IDTE_INT_GEN(), /* a9 - - I - - User defined Interrupts, external of INT n. */
331 IDTE_INT_GEN(), /* aa - - I - - User defined Interrupts, external of INT n. */
332 IDTE_INT_GEN(), /* ab - - I - - User defined Interrupts, external of INT n. */
333 IDTE_INT_GEN(), /* ac - - I - - User defined Interrupts, external of INT n. */
334 IDTE_INT_GEN(), /* ad - - I - - User defined Interrupts, external of INT n. */
335 IDTE_INT_GEN(), /* ae - - I - - User defined Interrupts, external of INT n. */
336 IDTE_INT_GEN(), /* af - - I - - User defined Interrupts, external of INT n. */
337 IDTE_INT_GEN(), /* b0 - - I - - User defined Interrupts, external of INT n. */
338 IDTE_INT_GEN(), /* b1 - - I - - User defined Interrupts, external of INT n. */
339 IDTE_INT_GEN(), /* b2 - - I - - User defined Interrupts, external of INT n. */
340 IDTE_INT_GEN(), /* b3 - - I - - User defined Interrupts, external of INT n. */
341 IDTE_INT_GEN(), /* b4 - - I - - User defined Interrupts, external of INT n. */
342 IDTE_INT_GEN(), /* b5 - - I - - User defined Interrupts, external of INT n. */
343 IDTE_INT_GEN(), /* b6 - - I - - User defined Interrupts, external of INT n. */
344 IDTE_INT_GEN(), /* b7 - - I - - User defined Interrupts, external of INT n. */
345 IDTE_INT_GEN(), /* b8 - - I - - User defined Interrupts, external of INT n. */
346 IDTE_INT_GEN(), /* b9 - - I - - User defined Interrupts, external of INT n. */
347 IDTE_INT_GEN(), /* ba - - I - - User defined Interrupts, external of INT n. */
348 IDTE_INT_GEN(), /* bb - - I - - User defined Interrupts, external of INT n. */
349 IDTE_INT_GEN(), /* bc - - I - - User defined Interrupts, external of INT n. */
350 IDTE_INT_GEN(), /* bd - - I - - User defined Interrupts, external of INT n. */
351 IDTE_INT_GEN(), /* be - - I - - User defined Interrupts, external of INT n. */
352 IDTE_INT_GEN(), /* bf - - I - - User defined Interrupts, external of INT n. */
353 IDTE_INT_GEN(), /* c0 - - I - - User defined Interrupts, external of INT n. */
354 IDTE_INT_GEN(), /* c1 - - I - - User defined Interrupts, external of INT n. */
355 IDTE_INT_GEN(), /* c2 - - I - - User defined Interrupts, external of INT n. */
356 IDTE_INT_GEN(), /* c3 - - I - - User defined Interrupts, external of INT n. */
357 IDTE_INT_GEN(), /* c4 - - I - - User defined Interrupts, external of INT n. */
358 IDTE_INT_GEN(), /* c5 - - I - - User defined Interrupts, external of INT n. */
359 IDTE_INT_GEN(), /* c6 - - I - - User defined Interrupts, external of INT n. */
360 IDTE_INT_GEN(), /* c7 - - I - - User defined Interrupts, external of INT n. */
361 IDTE_INT_GEN(), /* c8 - - I - - User defined Interrupts, external of INT n. */
362 IDTE_INT_GEN(), /* c9 - - I - - User defined Interrupts, external of INT n. */
363 IDTE_INT_GEN(), /* ca - - I - - User defined Interrupts, external of INT n. */
364 IDTE_INT_GEN(), /* cb - - I - - User defined Interrupts, external of INT n. */
365 IDTE_INT_GEN(), /* cc - - I - - User defined Interrupts, external of INT n. */
366 IDTE_INT_GEN(), /* cd - - I - - User defined Interrupts, external of INT n. */
367 IDTE_INT_GEN(), /* ce - - I - - User defined Interrupts, external of INT n. */
368 IDTE_INT_GEN(), /* cf - - I - - User defined Interrupts, external of INT n. */
369 IDTE_INT_GEN(), /* d0 - - I - - User defined Interrupts, external of INT n. */
370 IDTE_INT_GEN(), /* d1 - - I - - User defined Interrupts, external of INT n. */
371 IDTE_INT_GEN(), /* d2 - - I - - User defined Interrupts, external of INT n. */
372 IDTE_INT_GEN(), /* d3 - - I - - User defined Interrupts, external of INT n. */
373 IDTE_INT_GEN(), /* d4 - - I - - User defined Interrupts, external of INT n. */
374 IDTE_INT_GEN(), /* d5 - - I - - User defined Interrupts, external of INT n. */
375 IDTE_INT_GEN(), /* d6 - - I - - User defined Interrupts, external of INT n. */
376 IDTE_INT_GEN(), /* d7 - - I - - User defined Interrupts, external of INT n. */
377 IDTE_INT_GEN(), /* d8 - - I - - User defined Interrupts, external of INT n. */
378 IDTE_INT_GEN(), /* d9 - - I - - User defined Interrupts, external of INT n. */
379 IDTE_INT_GEN(), /* da - - I - - User defined Interrupts, external of INT n. */
380 IDTE_INT_GEN(), /* db - - I - - User defined Interrupts, external of INT n. */
381 IDTE_INT_GEN(), /* dc - - I - - User defined Interrupts, external of INT n. */
382 IDTE_INT_GEN(), /* dd - - I - - User defined Interrupts, external of INT n. */
383 IDTE_INT_GEN(), /* de - - I - - User defined Interrupts, external of INT n. */
384 IDTE_INT_GEN(), /* df - - I - - User defined Interrupts, external of INT n. */
385 IDTE_INT_GEN(), /* e0 - - I - - User defined Interrupts, external of INT n. */
386 IDTE_INT_GEN(), /* e1 - - I - - User defined Interrupts, external of INT n. */
387 IDTE_INT_GEN(), /* e2 - - I - - User defined Interrupts, external of INT n. */
388 IDTE_INT_GEN(), /* e3 - - I - - User defined Interrupts, external of INT n. */
389 IDTE_INT_GEN(), /* e4 - - I - - User defined Interrupts, external of INT n. */
390 IDTE_INT_GEN(), /* e5 - - I - - User defined Interrupts, external of INT n. */
391 IDTE_INT_GEN(), /* e6 - - I - - User defined Interrupts, external of INT n. */
392 IDTE_INT_GEN(), /* e7 - - I - - User defined Interrupts, external of INT n. */
393 IDTE_INT_GEN(), /* e8 - - I - - User defined Interrupts, external of INT n. */
394 IDTE_INT_GEN(), /* e9 - - I - - User defined Interrupts, external of INT n. */
395 IDTE_INT_GEN(), /* ea - - I - - User defined Interrupts, external of INT n. */
396 IDTE_INT_GEN(), /* eb - - I - - User defined Interrupts, external of INT n. */
397 IDTE_INT_GEN(), /* ec - - I - - User defined Interrupts, external of INT n. */
398 IDTE_INT_GEN(), /* ed - - I - - User defined Interrupts, external of INT n. */
399 IDTE_INT_GEN(), /* ee - - I - - User defined Interrupts, external of INT n. */
400 IDTE_INT_GEN(), /* ef - - I - - User defined Interrupts, external of INT n. */
401 IDTE_INT_GEN(), /* f0 - - I - - User defined Interrupts, external of INT n. */
402 IDTE_INT_GEN(), /* f1 - - I - - User defined Interrupts, external of INT n. */
403 IDTE_INT_GEN(), /* f2 - - I - - User defined Interrupts, external of INT n. */
404 IDTE_INT_GEN(), /* f3 - - I - - User defined Interrupts, external of INT n. */
405 IDTE_INT_GEN(), /* f4 - - I - - User defined Interrupts, external of INT n. */
406 IDTE_INT_GEN(), /* f5 - - I - - User defined Interrupts, external of INT n. */
407 IDTE_INT_GEN(), /* f6 - - I - - User defined Interrupts, external of INT n. */
408 IDTE_INT_GEN(), /* f7 - - I - - User defined Interrupts, external of INT n. */
409 IDTE_INT_GEN(), /* f8 - - I - - User defined Interrupts, external of INT n. */
410 IDTE_INT_GEN(), /* f9 - - I - - User defined Interrupts, external of INT n. */
411 IDTE_INT_GEN(), /* fa - - I - - User defined Interrupts, external of INT n. */
412 IDTE_INT_GEN(), /* fb - - I - - User defined Interrupts, external of INT n. */
413 IDTE_INT_GEN(), /* fc - - I - - User defined Interrupts, external of INT n. */
414 IDTE_INT_GEN(), /* fd - - I - - User defined Interrupts, external of INT n. */
415 IDTE_INT_GEN(), /* fe - - I - - User defined Interrupts, external of INT n. */
416 IDTE_INT_GEN(), /* ff - - I - - User defined Interrupts, external of INT n. */
417#undef IDTE_TRAP
418#undef IDTE_TRAP_GEN
419#undef IDTE_INT
420#undef IDTE_INT_GEN
421#undef IDTE_TASK
422#undef IDTE_UNUSED
423#undef IDTE_RESERVED
424};
425
426
427/** TRPM saved state version. */
428#define TRPM_SAVED_STATE_VERSION 9
429#define TRPM_SAVED_STATE_VERSION_UNI 8 /* SMP support bumped the version */
430
431
432/*********************************************************************************************************************************
433* Internal Functions *
434*********************************************************************************************************************************/
435static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM);
436static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
437static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
438
439
440/**
441 * Initializes the Trap Manager
442 *
443 * @returns VBox status code.
444 * @param pVM The cross context VM structure.
445 */
446VMMR3DECL(int) TRPMR3Init(PVM pVM)
447{
448 LogFlow(("TRPMR3Init\n"));
449 int rc;
450
451 /*
452 * Assert sizes and alignments.
453 */
454 AssertRelease(!(RT_UOFFSETOF(VM, trpm.s) & 31));
455 AssertRelease(!(RT_UOFFSETOF(VM, trpm.s.aIdt) & 15));
456 AssertRelease(sizeof(pVM->trpm.s) <= sizeof(pVM->trpm.padding));
457 AssertRelease(RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler) == sizeof(pVM->trpm.s.au32IdtPatched)*8);
458
459 /*
460 * Initialize members.
461 */
462 pVM->trpm.s.offVM = RT_UOFFSETOF(VM, trpm);
463 pVM->trpm.s.offTRPMCPU = RT_UOFFSETOF(VM, aCpus[0].trpm) - RT_UOFFSETOF(VM, trpm);
464
465 for (VMCPUID i = 0; i < pVM->cCpus; i++)
466 {
467 PVMCPU pVCpu = &pVM->aCpus[i];
468
469 pVCpu->trpm.s.offVM = RT_UOFFSETOF_DYN(VM, aCpus[i].trpm);
470 pVCpu->trpm.s.offVMCpu = RT_UOFFSETOF(VMCPU, trpm);
471 pVCpu->trpm.s.uActiveVector = ~0U;
472 }
473
474 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
475 pVM->trpm.s.pvMonShwIdtRC = RTRCPTR_MAX;
476 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = false;
477
478 /*
479 * Read the configuration (if any).
480 */
481 PCFGMNODE pTRPMNode = CFGMR3GetChild(CFGMR3GetRoot(pVM), "TRPM");
482 if (pTRPMNode)
483 {
484 bool f;
485 rc = CFGMR3QueryBool(pTRPMNode, "SafeToDropGuestIDTMonitoring", &f);
486 if (RT_SUCCESS(rc))
487 pVM->trpm.s.fSafeToDropGuestIDTMonitoring = f;
488 }
489
490 /* write config summary to log */
491 if (pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
492 LogRel(("TRPM: Dropping Guest IDT Monitoring\n"));
493
494 /*
495 * Initialize the IDT.
496 * The handler addresses will be set in the TRPMR3Relocate() function.
497 */
498 Assert(sizeof(pVM->trpm.s.aIdt) == sizeof(g_aIdt));
499 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
500
501 /*
502 * Register virtual access handlers.
503 */
504 pVM->trpm.s.hShadowIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
505 pVM->trpm.s.hGuestIdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
506#ifdef VBOX_WITH_RAW_MODE
507 if (VM_IS_RAW_MODE_ENABLED(pVM))
508 {
509# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
510 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /*fRelocUserRC*/,
511 NULL /*pfnInvalidateR3*/, NULL /*pfnHandlerR3*/,
512 NULL /*pszHandlerRC*/, "trpmRCShadowIDTWritePfHandler",
513 "Shadow IDT write access handler", &pVM->trpm.s.hShadowIdtWriteHandlerType);
514 AssertRCReturn(rc, rc);
515# endif
516 rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /*fRelocUserRC*/,
517 NULL /*pfnInvalidateR3*/, trpmGuestIDTWriteHandler,
518 "trpmGuestIDTWriteHandler", "trpmRCGuestIDTWritePfHandler",
519 "Guest IDT write access handler", &pVM->trpm.s.hGuestIdtWriteHandlerType);
520 AssertRCReturn(rc, rc);
521 }
522#endif /* VBOX_WITH_RAW_MODE */
523
524 /*
525 * Register the saved state data unit.
526 */
527 rc = SSMR3RegisterInternal(pVM, "trpm", 1, TRPM_SAVED_STATE_VERSION, sizeof(TRPM),
528 NULL, NULL, NULL,
529 NULL, trpmR3Save, NULL,
530 NULL, trpmR3Load, NULL);
531 if (RT_FAILURE(rc))
532 return rc;
533
534 /*
535 * Register info handlers.
536 */
537 rc = DBGFR3InfoRegisterInternalEx(pVM, "trpmevent", "Dumps TRPM pending event.", trpmR3InfoEvent,
538 DBGFINFO_FLAGS_ALL_EMTS);
539 AssertRCReturn(rc, rc);
540
541 /*
542 * Statistics.
543 */
544#ifdef VBOX_WITH_RAW_MODE
545 if (VM_IS_RAW_MODE_ENABLED(pVM))
546 {
547 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTFault, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesFault", STAMUNIT_OCCURENCES, "Guest IDT writes the we returned to R3 to handle.");
548 STAM_REG(pVM, &pVM->trpm.s.StatRCWriteGuestIDTHandled, STAMTYPE_COUNTER, "/TRPM/RC/IDTWritesHandled", STAMUNIT_OCCURENCES, "Guest IDT writes that we handled successfully.");
549 STAM_REG(pVM, &pVM->trpm.s.StatSyncIDT, STAMTYPE_PROFILE, "/PROF/TRPM/SyncIDT", STAMUNIT_TICKS_PER_CALL, "Profiling of TRPMR3SyncIDT().");
550
551 /* traps */
552 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x00], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/00", STAMUNIT_TICKS_PER_CALL, "#DE - Divide error.");
553 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x01], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/01", STAMUNIT_TICKS_PER_CALL, "#DB - Debug (single step and more).");
554 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x02], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/02", STAMUNIT_TICKS_PER_CALL, "NMI");
555 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x03], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/03", STAMUNIT_TICKS_PER_CALL, "#BP - Breakpoint.");
556 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x04], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/04", STAMUNIT_TICKS_PER_CALL, "#OF - Overflow.");
557 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x05], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/05", STAMUNIT_TICKS_PER_CALL, "#BR - Bound range exceeded.");
558 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x06], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/06", STAMUNIT_TICKS_PER_CALL, "#UD - Undefined opcode.");
559 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x07], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/07", STAMUNIT_TICKS_PER_CALL, "#NM - Device not available (FPU).");
560 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x08], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/08", STAMUNIT_TICKS_PER_CALL, "#DF - Double fault.");
561 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x09], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/09", STAMUNIT_TICKS_PER_CALL, "#?? - Coprocessor segment overrun (obsolete).");
562 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0a], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0a", STAMUNIT_TICKS_PER_CALL, "#TS - Task switch fault.");
563 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0b], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0b", STAMUNIT_TICKS_PER_CALL, "#NP - Segment not present.");
564 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0c], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0c", STAMUNIT_TICKS_PER_CALL, "#SS - Stack segment fault.");
565 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0d], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0d", STAMUNIT_TICKS_PER_CALL, "#GP - General protection fault.");
566 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0e], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0e", STAMUNIT_TICKS_PER_CALL, "#PF - Page fault.");
567 //STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x0f], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/0f", STAMUNIT_TICKS_PER_CALL, "Reserved.");
568 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x10], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/10", STAMUNIT_TICKS_PER_CALL, "#MF - Math fault..");
569 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x11], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/11", STAMUNIT_TICKS_PER_CALL, "#AC - Alignment check.");
570 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x12], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/12", STAMUNIT_TICKS_PER_CALL, "#MC - Machine check.");
571 STAM_REG(pVM, &pVM->trpm.s.aStatGCTraps[0x13], STAMTYPE_PROFILE_ADV, "/TRPM/GC/Traps/13", STAMUNIT_TICKS_PER_CALL, "#XF - SIMD Floating-Point Exception.");
572 }
573#endif
574
575# ifdef VBOX_WITH_STATISTICS
576 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatForwardedIRQR3);
577 AssertRCReturn(rc, rc);
578 pVM->trpm.s.paStatForwardedIRQRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatForwardedIRQR3);
579 for (unsigned i = 0; i < 256; i++)
580 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatForwardedIRQR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
581 i < 0x20 ? "/TRPM/ForwardRaw/TRAP/%02X" : "/TRPM/ForwardRaw/IRQ/%02X", i);
582
583# ifdef VBOX_WITH_RAW_MODE
584 if (VM_IS_RAW_MODE_ENABLED(pVM))
585 {
586 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, sizeof(STAMCOUNTER), MM_TAG_TRPM, (void **)&pVM->trpm.s.paStatHostIrqR3);
587 AssertRCReturn(rc, rc);
588 pVM->trpm.s.paStatHostIrqRC = MMHyperR3ToRC(pVM, pVM->trpm.s.paStatHostIrqR3);
589 for (unsigned i = 0; i < 256; i++)
590 STAMR3RegisterF(pVM, &pVM->trpm.s.paStatHostIrqR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
591 "Host interrupts.", "/TRPM/HostIRQs/%02x", i);
592 }
593# endif
594# endif
595
596#ifdef VBOX_WITH_RAW_MODE
597 if (VM_IS_RAW_MODE_ENABLED(pVM))
598 {
599 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfR3, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfR3", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
600 STAM_REG(pVM, &pVM->trpm.s.StatForwardProfRZ, STAMTYPE_PROFILE_ADV, "/TRPM/ForwardRaw/ProfRZ", STAMUNIT_TICKS_PER_CALL, "Profiling TRPMForwardTrap.");
601 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailNoHandler, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailNoHandler", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
602 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailPatchAddr, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailPatchAddr", STAMUNIT_OCCURENCES,"Failure to forward interrupt in raw mode.");
603 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailR3, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailR3", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
604 STAM_REG(pVM, &pVM->trpm.s.StatForwardFailRZ, STAMTYPE_COUNTER, "/TRPM/ForwardRaw/FailRZ", STAMUNIT_OCCURENCES, "Failure to forward interrupt in raw mode.");
605
606 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dDisasm, STAMTYPE_PROFILE, "/TRPM/RC/Traps/0d/Disasm", STAMUNIT_TICKS_PER_CALL, "Profiling disassembly part of trpmGCTrap0dHandler.");
607 STAM_REG(pVM, &pVM->trpm.s.StatTrap0dRdTsc, STAMTYPE_COUNTER, "/TRPM/RC/Traps/0d/RdTsc", STAMUNIT_OCCURENCES, "Number of RDTSC #GPs.");
608 }
609#endif
610
611#ifdef VBOX_WITH_RAW_MODE
612 /*
613 * Default action when entering raw mode for the first time
614 */
615 if (VM_IS_RAW_MODE_ENABLED(pVM))
616 {
617 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
618 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
619 }
620#endif
621 return 0;
622}
623
624
625/**
626 * Applies relocations to data and code managed by this component.
627 *
628 * This function will be called at init and whenever the VMM need
629 * to relocate itself inside the GC.
630 *
631 * @param pVM The cross context VM structure.
632 * @param offDelta Relocation delta relative to old location.
633 */
634VMMR3DECL(void) TRPMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
635{
636#ifdef VBOX_WITH_RAW_MODE
637 if (!VM_IS_RAW_MODE_ENABLED(pVM))
638 return;
639
640 /* Only applies to raw mode which supports only 1 VCPU. */
641 PVMCPU pVCpu = &pVM->aCpus[0];
642 LogFlow(("TRPMR3Relocate\n"));
643
644 /*
645 * Get the trap handler addresses.
646 *
647 * If VMMRC.rc is screwed, so are we. We'll assert here since it elsewise
648 * would make init order impossible if we should assert the presence of these
649 * exports in TRPMR3Init().
650 */
651 RTRCPTR aRCPtrs[TRPM_HANDLER_MAX];
652 RT_ZERO(aRCPtrs);
653 int rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aRCPtrs[TRPM_HANDLER_INT]);
654 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
655
656 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerGeneric", &aRCPtrs[TRPM_HANDLER_TRAP]);
657 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerGeneric in VMMRC.rc!\n"));
658
659 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap08", &aRCPtrs[TRPM_HANDLER_TRAP_08]);
660 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap08 in VMMRC.rc!\n"));
661
662 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerTrap12", &aRCPtrs[TRPM_HANDLER_TRAP_12]);
663 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerTrap12 in VMMRC.rc!\n"));
664
665 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
666
667 /*
668 * Iterate the idt and set the addresses.
669 */
670 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[0];
671 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[0];
672 for (unsigned i = 0; i < RT_ELEMENTS(pVM->trpm.s.aIdt); i++, pIdte++, pIdteTemplate++)
673 {
674 if ( pIdte->Gen.u1Present
675 && !ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], i)
676 )
677 {
678 Assert(pIdteTemplate->u16OffsetLow < TRPM_HANDLER_MAX);
679 RTGCPTR Offset = aRCPtrs[pIdteTemplate->u16OffsetLow];
680 switch (pIdteTemplate->u16OffsetLow)
681 {
682 /*
683 * Generic handlers have different entrypoints for each possible
684 * vector number. These entrypoints makes a sort of an array with
685 * 8 byte entries where the vector number is the index.
686 * See TRPMGCHandlersA.asm for details.
687 */
688 case TRPM_HANDLER_INT:
689 case TRPM_HANDLER_TRAP:
690 Offset += i * 8;
691 break;
692 case TRPM_HANDLER_TRAP_12:
693 break;
694 case TRPM_HANDLER_TRAP_08:
695 /* Handle #DF Task Gate in special way. */
696 pIdte->Gen.u16SegSel = SELMGetTrap8Selector(pVM);
697 pIdte->Gen.u16OffsetLow = 0;
698 pIdte->Gen.u16OffsetHigh = 0;
699 SELMSetTrap8EIP(pVM, Offset);
700 continue;
701 }
702 /* (non-task gates only ) */
703 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
704 pIdte->Gen.u16OffsetHigh = Offset >> 16;
705 pIdte->Gen.u16SegSel = SelCS;
706 }
707 }
708
709 /*
710 * Update IDTR (limit is including!).
711 */
712 CPUMSetHyperIDTR(pVCpu, VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]), sizeof(pVM->trpm.s.aIdt)-1);
713
714# ifdef TRPM_TRACK_SHADOW_IDT_CHANGES
715 if (pVM->trpm.s.pvMonShwIdtRC != RTRCPTR_MAX)
716 {
717 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.pvMonShwIdtRC, true /*fHypervisor*/);
718 AssertRC(rc);
719 }
720 pVM->trpm.s.pvMonShwIdtRC = VM_RC_ADDR(pVM, &pVM->trpm.s.aIdt[0]);
721 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hShadowIdtWriteHandlerType,
722 pVM->trpm.s.pvMonShwIdtRC, pVM->trpm.s.pvMonShwIdtRC + sizeof(pVM->trpm.s.aIdt) - 1,
723 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
724 AssertRC(rc);
725# endif
726
727 /* Relocate IDT handlers for forwarding guest traps/interrupts. */
728 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
729 {
730 if (pVM->trpm.s.aGuestTrapHandler[iTrap] != TRPM_INVALID_HANDLER)
731 {
732 Log(("TRPMR3Relocate: iGate=%2X Handler %RRv -> %RRv\n", iTrap, pVM->trpm.s.aGuestTrapHandler[iTrap], pVM->trpm.s.aGuestTrapHandler[iTrap] + offDelta));
733 pVM->trpm.s.aGuestTrapHandler[iTrap] += offDelta;
734 }
735
736 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
737 {
738 PVBOXIDTE pIdteCur = &pVM->trpm.s.aIdt[iTrap];
739 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdteCur);
740
741 Log(("TRPMR3Relocate: *iGate=%2X Handler %RGv -> %RGv\n", iTrap, pHandler, pHandler + offDelta));
742 pHandler += offDelta;
743
744 pIdteCur->Gen.u16OffsetHigh = pHandler >> 16;
745 pIdteCur->Gen.u16OffsetLow = pHandler & 0xFFFF;
746 }
747 }
748
749# ifdef VBOX_WITH_STATISTICS
750 pVM->trpm.s.paStatForwardedIRQRC += offDelta;
751 pVM->trpm.s.paStatHostIrqRC += offDelta;
752# endif
753
754#else /* !VBOX_WITH_RAW_MODE */
755 RT_NOREF(pVM, offDelta);
756#endif /* !VBOX_WITH_RAW_MODE */
757}
758
759
760/**
761 * Terminates the Trap Manager
762 *
763 * @returns VBox status code.
764 * @param pVM The cross context VM structure.
765 */
766VMMR3DECL(int) TRPMR3Term(PVM pVM)
767{
768 NOREF(pVM);
769 return VINF_SUCCESS;
770}
771
772
773/**
774 * Resets a virtual CPU.
775 *
776 * Used by TRPMR3Reset and CPU hot plugging.
777 *
778 * @param pVCpu The cross context virtual CPU structure.
779 */
780VMMR3DECL(void) TRPMR3ResetCpu(PVMCPU pVCpu)
781{
782 pVCpu->trpm.s.uActiveVector = ~0U;
783}
784
785
786/**
787 * The VM is being reset.
788 *
789 * For the TRPM component this means that any IDT write monitors
790 * needs to be removed, any pending trap cleared, and the IDT reset.
791 *
792 * @param pVM The cross context VM structure.
793 */
794VMMR3DECL(void) TRPMR3Reset(PVM pVM)
795{
796 /*
797 * Deregister any virtual handlers.
798 */
799#ifdef TRPM_TRACK_GUEST_IDT_CHANGES
800 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
801 {
802 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
803 {
804 int rc = PGMHandlerVirtualDeregister(pVM, VMMGetCpu(pVM), pVM->trpm.s.GuestIdtr.pIdt, false /*fHypervisor*/);
805 AssertRC(rc);
806 }
807 pVM->trpm.s.GuestIdtr.pIdt = RTRCPTR_MAX;
808 }
809 pVM->trpm.s.GuestIdtr.cbIdt = 0;
810#endif
811
812 /*
813 * Reinitialize other members calling the relocator to get things right.
814 */
815 for (VMCPUID i = 0; i < pVM->cCpus; i++)
816 TRPMR3ResetCpu(&pVM->aCpus[i]);
817 memcpy(&pVM->trpm.s.aIdt[0], &g_aIdt[0], sizeof(pVM->trpm.s.aIdt));
818 memset(pVM->trpm.s.aGuestTrapHandler, 0, sizeof(pVM->trpm.s.aGuestTrapHandler));
819 TRPMR3Relocate(pVM, 0);
820
821#ifdef VBOX_WITH_RAW_MODE
822 /*
823 * Default action when entering raw mode for the first time
824 */
825 if (VM_IS_RAW_MODE_ENABLED(pVM))
826 {
827 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
828 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
829 }
830#endif
831}
832
833
834# ifdef VBOX_WITH_RAW_MODE
835/**
836 * Resolve a builtin RC symbol.
837 *
838 * Called by PDM when loading or relocating RC modules.
839 *
840 * @returns VBox status
841 * @param pVM The cross context VM structure.
842 * @param pszSymbol Symbol to resolv
843 * @param pRCPtrValue Where to store the symbol value.
844 *
845 * @remark This has to work before VMMR3Relocate() is called.
846 */
847VMMR3_INT_DECL(int) TRPMR3GetImportRC(PVM pVM, const char *pszSymbol, PRTRCPTR pRCPtrValue)
848{
849 if (!strcmp(pszSymbol, "g_TRPM"))
850 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->trpm);
851 else if (!strcmp(pszSymbol, "g_TRPMCPU"))
852 *pRCPtrValue = VM_RC_ADDR(pVM, &pVM->aCpus[0].trpm);
853 else if (!strcmp(pszSymbol, "g_trpmGuestCtx"))
854 {
855 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
856 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
857 }
858 else if (!strcmp(pszSymbol, "g_trpmHyperCtx"))
859 {
860 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
861 *pRCPtrValue = VM_RC_ADDR(pVM, pCtx);
862 }
863 else if (!strcmp(pszSymbol, "g_trpmGuestCtxCore"))
864 {
865 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(VMMGetCpuById(pVM, 0));
866 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
867 }
868 else if (!strcmp(pszSymbol, "g_trpmHyperCtxCore"))
869 {
870 PCPUMCTX pCtx = CPUMGetHyperCtxPtr(VMMGetCpuById(pVM, 0));
871 *pRCPtrValue = VM_RC_ADDR(pVM, CPUMCTX2CORE(pCtx));
872 }
873 else
874 return VERR_SYMBOL_NOT_FOUND;
875 return VINF_SUCCESS;
876}
877#endif /* VBOX_WITH_RAW_MODE */
878
879
880/**
881 * Execute state save operation.
882 *
883 * @returns VBox status code.
884 * @param pVM The cross context VM structure.
885 * @param pSSM SSM operation handle.
886 */
887static DECLCALLBACK(int) trpmR3Save(PVM pVM, PSSMHANDLE pSSM)
888{
889 PTRPM pTrpm = &pVM->trpm.s;
890 LogFlow(("trpmR3Save:\n"));
891
892 /*
893 * Active and saved traps.
894 */
895 for (VMCPUID i = 0; i < pVM->cCpus; i++)
896 {
897 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
898 SSMR3PutUInt(pSSM, pTrpmCpu->uActiveVector);
899 SSMR3PutUInt(pSSM, pTrpmCpu->enmActiveType);
900 SSMR3PutGCUInt(pSSM, pTrpmCpu->uActiveErrorCode);
901 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uActiveCR2);
902 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedVector);
903 SSMR3PutUInt(pSSM, pTrpmCpu->enmSavedType);
904 SSMR3PutGCUInt(pSSM, pTrpmCpu->uSavedErrorCode);
905 SSMR3PutGCUIntPtr(pSSM, pTrpmCpu->uSavedCR2);
906 SSMR3PutGCUInt(pSSM, pTrpmCpu->uPrevVector);
907 }
908 SSMR3PutBool(pSSM, !VM_IS_RAW_MODE_ENABLED(pVM));
909 PVMCPU pVCpu0 = &pVM->aCpus[0]; NOREF(pVCpu0); /* raw mode implies 1 VCPU */
910 SSMR3PutUInt(pSSM, VM_WHEN_RAW_MODE(VMCPU_FF_IS_SET(pVCpu0, VMCPU_FF_TRPM_SYNC_IDT), 0));
911 SSMR3PutMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
912 SSMR3PutU32(pSSM, UINT32_MAX); /* separator. */
913
914 /*
915 * Save any trampoline gates.
916 */
917 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pTrpm->aGuestTrapHandler); iTrap++)
918 {
919 if (pTrpm->aGuestTrapHandler[iTrap])
920 {
921 SSMR3PutU32(pSSM, iTrap);
922 SSMR3PutGCPtr(pSSM, pTrpm->aGuestTrapHandler[iTrap]);
923 SSMR3PutMem(pSSM, &pTrpm->aIdt[iTrap], sizeof(pTrpm->aIdt[iTrap]));
924 }
925 }
926
927 return SSMR3PutU32(pSSM, UINT32_MAX); /* terminator */
928}
929
930
931/**
932 * Execute state load operation.
933 *
934 * @returns VBox status code.
935 * @param pVM The cross context VM structure.
936 * @param pSSM SSM operation handle.
937 * @param uVersion Data layout version.
938 * @param uPass The data pass.
939 */
940static DECLCALLBACK(int) trpmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
941{
942 LogFlow(("trpmR3Load:\n"));
943 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
944
945 /*
946 * Validate version.
947 */
948 if ( uVersion != TRPM_SAVED_STATE_VERSION
949 && uVersion != TRPM_SAVED_STATE_VERSION_UNI)
950 {
951 AssertMsgFailed(("trpmR3Load: Invalid version uVersion=%d!\n", uVersion));
952 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
953 }
954
955 /*
956 * Call the reset function to kick out any handled gates and other potential trouble.
957 */
958 TRPMR3Reset(pVM);
959
960 /*
961 * Active and saved traps.
962 */
963 PTRPM pTrpm = &pVM->trpm.s;
964
965 if (uVersion == TRPM_SAVED_STATE_VERSION)
966 {
967 for (VMCPUID i = 0; i < pVM->cCpus; i++)
968 {
969 PTRPMCPU pTrpmCpu = &pVM->aCpus[i].trpm.s;
970 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
971 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
972 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
973 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
974 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
975 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
976 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
977 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
978 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
979 }
980
981 bool fIgnored;
982 SSMR3GetBool(pSSM, &fIgnored);
983 }
984 else
985 {
986 PTRPMCPU pTrpmCpu = &pVM->aCpus[0].trpm.s;
987 SSMR3GetUInt(pSSM, &pTrpmCpu->uActiveVector);
988 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmActiveType);
989 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uActiveErrorCode);
990 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uActiveCR2);
991 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedVector);
992 SSMR3GetUInt(pSSM, (uint32_t *)&pTrpmCpu->enmSavedType);
993 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uSavedErrorCode);
994 SSMR3GetGCUIntPtr(pSSM, &pTrpmCpu->uSavedCR2);
995 SSMR3GetGCUInt(pSSM, &pTrpmCpu->uPrevVector);
996
997 RTGCUINT fIgnored;
998 SSMR3GetGCUInt(pSSM, &fIgnored);
999 }
1000
1001 RTUINT fSyncIDT;
1002 int rc = SSMR3GetUInt(pSSM, &fSyncIDT);
1003 if (RT_FAILURE(rc))
1004 return rc;
1005 if (fSyncIDT & ~1)
1006 {
1007 AssertMsgFailed(("fSyncIDT=%#x\n", fSyncIDT));
1008 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1009 }
1010#ifdef VBOX_WITH_RAW_MODE
1011 if (fSyncIDT)
1012 {
1013 PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies 1 VCPU */
1014 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1015 }
1016 /* else: cleared by reset call above. */
1017#endif
1018
1019 SSMR3GetMem(pSSM, &pTrpm->au32IdtPatched[0], sizeof(pTrpm->au32IdtPatched));
1020
1021 /* check the separator */
1022 uint32_t u32Sep;
1023 rc = SSMR3GetU32(pSSM, &u32Sep);
1024 if (RT_FAILURE(rc))
1025 return rc;
1026 if (u32Sep != (uint32_t)~0)
1027 {
1028 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1029 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1030 }
1031
1032 /*
1033 * Restore any trampoline gates.
1034 */
1035 for (;;)
1036 {
1037 /* gate number / terminator */
1038 uint32_t iTrap;
1039 rc = SSMR3GetU32(pSSM, &iTrap);
1040 if (RT_FAILURE(rc))
1041 return rc;
1042 if (iTrap == (uint32_t)~0)
1043 break;
1044 if ( iTrap >= RT_ELEMENTS(pTrpm->aIdt)
1045 || pTrpm->aGuestTrapHandler[iTrap])
1046 {
1047 AssertMsgFailed(("iTrap=%#x\n", iTrap));
1048 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1049 }
1050
1051 /* restore the IDT entry. */
1052 RTGCPTR GCPtrHandler;
1053 SSMR3GetGCPtr(pSSM, &GCPtrHandler);
1054 VBOXIDTE Idte;
1055 rc = SSMR3GetMem(pSSM, &Idte, sizeof(Idte));
1056 if (RT_FAILURE(rc))
1057 return rc;
1058 Assert(GCPtrHandler);
1059 pTrpm->aIdt[iTrap] = Idte;
1060 }
1061
1062 return VINF_SUCCESS;
1063}
1064
1065#ifdef VBOX_WITH_RAW_MODE
1066
1067/**
1068 * Check if gate handlers were updated
1069 * (callback for the VMCPU_FF_TRPM_SYNC_IDT forced action).
1070 *
1071 * @returns VBox status code.
1072 * @param pVM The cross context VM structure.
1073 * @param pVCpu The cross context virtual CPU structure.
1074 */
1075VMMR3DECL(int) TRPMR3SyncIDT(PVM pVM, PVMCPU pVCpu)
1076{
1077 STAM_PROFILE_START(&pVM->trpm.s.StatSyncIDT, a);
1078 const bool fRawRing0 = EMIsRawRing0Enabled(pVM);
1079 int rc;
1080
1081 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_TRPM_HM_IPE);
1082
1083 if (fRawRing0 && CSAMIsEnabled(pVM))
1084 {
1085 /* Clear all handlers */
1086 Log(("TRPMR3SyncIDT: Clear all trap handlers.\n"));
1087 /** @todo inefficient, but simple */
1088 for (unsigned iGate = 0; iGate < 256; iGate++)
1089 trpmClearGuestTrapHandler(pVM, iGate);
1090
1091 /* Scan them all (only the first time) */
1092 CSAMR3CheckGates(pVM, 0, 256);
1093 }
1094
1095 /*
1096 * Get the IDTR.
1097 */
1098 VBOXIDTR IDTR;
1099 IDTR.pIdt = CPUMGetGuestIDTR(pVCpu, &IDTR.cbIdt);
1100 if (!IDTR.cbIdt)
1101 {
1102 Log(("No IDT entries...\n"));
1103 return DBGFSTOP(pVM);
1104 }
1105
1106# ifdef TRPM_TRACK_GUEST_IDT_CHANGES
1107 /*
1108 * Check if Guest's IDTR has changed.
1109 */
1110 if ( IDTR.pIdt != pVM->trpm.s.GuestIdtr.pIdt
1111 || IDTR.cbIdt != pVM->trpm.s.GuestIdtr.cbIdt)
1112 {
1113 Log(("TRPMR3UpdateFromCPUM: Guest's IDT is changed to pIdt=%08X cbIdt=%08X\n", IDTR.pIdt, IDTR.cbIdt));
1114 if (!pVM->trpm.s.fSafeToDropGuestIDTMonitoring)
1115 {
1116 /*
1117 * [Re]Register write virtual handler for guest's IDT.
1118 */
1119 if (pVM->trpm.s.GuestIdtr.pIdt != RTRCPTR_MAX)
1120 {
1121 rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->trpm.s.GuestIdtr.pIdt, false /*fHypervisor*/);
1122 AssertRCReturn(rc, rc);
1123 }
1124 /* limit is including */
1125 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1126 IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1127 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1128
1129 if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1130 {
1131 /* Could be a conflict with CSAM */
1132 CSAMR3RemovePage(pVM, IDTR.pIdt);
1133 if (PAGE_ADDRESS(IDTR.pIdt) != PAGE_ADDRESS(IDTR.pIdt + IDTR.cbIdt))
1134 CSAMR3RemovePage(pVM, IDTR.pIdt + IDTR.cbIdt);
1135
1136 rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->trpm.s.hGuestIdtWriteHandlerType,
1137 IDTR.pIdt, IDTR.pIdt + IDTR.cbIdt /* already inclusive */,
1138 NULL /*pvUserR3*/, NIL_RTR0PTR /*pvUserRC*/, NULL /*pszDesc*/);
1139 }
1140
1141 AssertRCReturn(rc, rc);
1142 }
1143
1144 /* Update saved Guest IDTR. */
1145 pVM->trpm.s.GuestIdtr = IDTR;
1146 }
1147# endif
1148
1149 /*
1150 * Sync the interrupt gate.
1151 * Should probably check/sync the others too, but for now we'll handle that in #GP.
1152 */
1153 X86DESC Idte3;
1154 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Idte3, IDTR.pIdt + sizeof(Idte3) * 3, sizeof(Idte3));
1155 if (RT_FAILURE(rc))
1156 {
1157 AssertMsgRC(rc, ("Failed to read IDT[3]! rc=%Rrc\n", rc));
1158 return DBGFSTOP(pVM);
1159 }
1160 AssertRCReturn(rc, rc);
1161 if (fRawRing0)
1162 pVM->trpm.s.aIdt[3].Gen.u2DPL = RT_MAX(Idte3.Gen.u2Dpl, 1);
1163 else
1164 pVM->trpm.s.aIdt[3].Gen.u2DPL = Idte3.Gen.u2Dpl;
1165
1166 /*
1167 * Clear the FF and we're done.
1168 */
1169 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
1170 STAM_PROFILE_STOP(&pVM->trpm.s.StatSyncIDT, a);
1171 return VINF_SUCCESS;
1172}
1173
1174
1175/**
1176 * Clear passthrough interrupt gate handler (reset to default handler)
1177 *
1178 * @returns VBox status code.
1179 * @param pVM The cross context VM structure.
1180 * @param iTrap Trap/interrupt gate number.
1181 */
1182int trpmR3ClearPassThroughHandler(PVM pVM, unsigned iTrap)
1183{
1184 /* Only applies to raw mode which supports only 1 VCPU. */
1185 PVMCPU pVCpu = &pVM->aCpus[0];
1186 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
1187
1188 /** @todo cleanup trpmR3ClearPassThroughHandler()! */
1189 RTRCPTR aGCPtrs[TRPM_HANDLER_MAX];
1190 int rc;
1191
1192 memset(aGCPtrs, 0, sizeof(aGCPtrs));
1193
1194 rc = PDMR3LdrGetSymbolRC(pVM, VMMRC_MAIN_MODULE_NAME, "TRPMGCHandlerInterupt", &aGCPtrs[TRPM_HANDLER_INT]);
1195 AssertReleaseMsgRC(rc, ("Couldn't find TRPMGCHandlerInterupt in VMMRC.rc!\n"));
1196
1197 if ( iTrap < TRPM_HANDLER_INT_BASE
1198 || iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1199 {
1200 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %#x!\n", iTrap));
1201 return VERR_INVALID_PARAMETER;
1202 }
1203 memcpy(&pVM->trpm.s.aIdt[iTrap], &g_aIdt[iTrap], sizeof(pVM->trpm.s.aIdt[0]));
1204
1205 /* Unmark it for relocation purposes. */
1206 ASMBitClear(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1207
1208 RTSEL SelCS = CPUMGetHyperCS(pVCpu);
1209 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1210 PVBOXIDTE_GENERIC pIdteTemplate = &g_aIdt[iTrap];
1211 if (pIdte->Gen.u1Present)
1212 {
1213 Assert(pIdteTemplate->u16OffsetLow == TRPM_HANDLER_INT);
1214 Assert(sizeof(RTRCPTR) == sizeof(aGCPtrs[0]));
1215 RTRCPTR Offset = (RTRCPTR)aGCPtrs[pIdteTemplate->u16OffsetLow];
1216
1217 /*
1218 * Generic handlers have different entrypoints for each possible
1219 * vector number. These entrypoints make a sort of an array with
1220 * 8 byte entries where the vector number is the index.
1221 * See TRPMGCHandlersA.asm for details.
1222 */
1223 Offset += iTrap * 8;
1224
1225 if (pIdte->Gen.u5Type2 != VBOX_IDTE_TYPE2_TASK)
1226 {
1227 pIdte->Gen.u16OffsetLow = Offset & 0xffff;
1228 pIdte->Gen.u16OffsetHigh = Offset >> 16;
1229 pIdte->Gen.u16SegSel = SelCS;
1230 }
1231 }
1232
1233 return VINF_SUCCESS;
1234}
1235
1236
1237/**
1238 * Check if address is a gate handler (interrupt or trap).
1239 *
1240 * @returns gate nr or UINT32_MAX is not found
1241 *
1242 * @param pVM The cross context VM structure.
1243 * @param GCPtr GC address to check.
1244 */
1245VMMR3DECL(uint32_t) TRPMR3QueryGateByHandler(PVM pVM, RTRCPTR GCPtr)
1246{
1247 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), ~0U);
1248
1249 for (uint32_t iTrap = 0; iTrap < RT_ELEMENTS(pVM->trpm.s.aGuestTrapHandler); iTrap++)
1250 {
1251 if (pVM->trpm.s.aGuestTrapHandler[iTrap] == GCPtr)
1252 return iTrap;
1253
1254 /* redundant */
1255 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
1256 {
1257 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1258 RTGCPTR pHandler = VBOXIDTE_OFFSET(*pIdte);
1259
1260 if (pHandler == GCPtr)
1261 return iTrap;
1262 }
1263 }
1264 return UINT32_MAX;
1265}
1266
1267
1268/**
1269 * Get guest trap/interrupt gate handler
1270 *
1271 * @returns Guest trap handler address or TRPM_INVALID_HANDLER if none installed
1272 * @param pVM The cross context VM structure.
1273 * @param iTrap Interrupt/trap number.
1274 */
1275VMMR3DECL(RTRCPTR) TRPMR3GetGuestTrapHandler(PVM pVM, unsigned iTrap)
1276{
1277 AssertReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), TRPM_INVALID_HANDLER);
1278 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), TRPM_INVALID_HANDLER);
1279
1280 return pVM->trpm.s.aGuestTrapHandler[iTrap];
1281}
1282
1283
1284/**
1285 * Set guest trap/interrupt gate handler
1286 * Used for setting up trap gates used for kernel calls.
1287 *
1288 * @returns VBox status code.
1289 * @param pVM The cross context VM structure.
1290 * @param iTrap Interrupt/trap number.
1291 * @param pHandler GC handler pointer
1292 */
1293VMMR3DECL(int) TRPMR3SetGuestTrapHandler(PVM pVM, unsigned iTrap, RTRCPTR pHandler)
1294{
1295 /* Only valid in raw mode which implies 1 VCPU */
1296 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1297 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_TRPM_HM_IPE);
1298 PVMCPU pVCpu = &pVM->aCpus[0];
1299
1300 /*
1301 * Validate.
1302 */
1303 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
1304 {
1305 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
1306 return VERR_INVALID_PARAMETER;
1307 }
1308
1309 AssertReturn(pHandler == TRPM_INVALID_HANDLER || PATMIsPatchGCAddr(pVM, pHandler), VERR_INVALID_PARAMETER);
1310
1311 uint16_t cbIDT;
1312 RTGCPTR GCPtrIDT = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1313 if (iTrap * sizeof(VBOXIDTE) >= cbIDT)
1314 return VERR_INVALID_PARAMETER; /* Silently ignore out of range requests. */
1315
1316 if (pHandler == TRPM_INVALID_HANDLER)
1317 {
1318 /* clear trap handler */
1319 Log(("TRPMR3SetGuestTrapHandler: clear handler %x\n", iTrap));
1320 return trpmClearGuestTrapHandler(pVM, iTrap);
1321 }
1322
1323 /*
1324 * Read the guest IDT entry.
1325 */
1326 VBOXIDTE GuestIdte;
1327 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, GCPtrIDT + iTrap * sizeof(GuestIdte), sizeof(GuestIdte));
1328 if (RT_FAILURE(rc))
1329 {
1330 AssertMsgRC(rc, ("Failed to read IDTE! rc=%Rrc\n", rc));
1331 return rc;
1332 }
1333
1334 if ( EMIsRawRing0Enabled(pVM)
1335 && !EMIsRawRing1Enabled(pVM)) /* can't deal with the ambiguity of ring 1 & 2 in the patch code. */
1336 {
1337 /*
1338 * Only replace handlers for which we are 100% certain there won't be
1339 * any host interrupts.
1340 *
1341 * 0x2E is safe on Windows because it's the system service interrupt gate. Not
1342 * quite certain if this is safe or not on 64-bit Vista, it probably is.
1343 *
1344 * 0x80 is safe on Linux because it's the syscall vector and is part of the
1345 * 32-bit usermode ABI. 64-bit Linux (usually) supports 32-bit processes
1346 * and will therefor never assign hardware interrupts to 0x80.
1347 *
1348 * Exactly why 0x80 is safe on 32-bit Windows is a bit hazy, but it seems
1349 * to work ok... However on 64-bit Vista (SMP?) is doesn't work reliably.
1350 * Booting Linux/BSD guest will cause system lockups on most of the computers.
1351 * -> Update: It seems gate 0x80 is not safe on 32-bits Windows either. See
1352 * @bugref{3604}.
1353 *
1354 * PORTME - Check if your host keeps any of these gates free from hw ints.
1355 *
1356 * Note! SELMR3SyncTSS also has code related to this interrupt handler replacing.
1357 */
1358 /** @todo handle those dependencies better! */
1359 /** @todo Solve this in a proper manner. see @bugref{1186} */
1360#if defined(RT_OS_WINDOWS) && defined(RT_ARCH_X86)
1361 if (iTrap == 0x2E)
1362#elif defined(RT_OS_LINUX)
1363 if (iTrap == 0x80)
1364#else
1365 if (0)
1366#endif
1367 {
1368 if ( GuestIdte.Gen.u1Present
1369 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1370 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1371 && GuestIdte.Gen.u2DPL == 3)
1372 {
1373 PVBOXIDTE pIdte = &pVM->trpm.s.aIdt[iTrap];
1374
1375 GuestIdte.Gen.u5Type2 = VBOX_IDTE_TYPE2_TRAP_32;
1376 GuestIdte.Gen.u16OffsetHigh = pHandler >> 16;
1377 GuestIdte.Gen.u16OffsetLow = pHandler & 0xFFFF;
1378 GuestIdte.Gen.u16SegSel |= 1; //ring 1
1379 *pIdte = GuestIdte;
1380
1381 /* Mark it for relocation purposes. */
1382 ASMBitSet(&pVM->trpm.s.au32IdtPatched[0], iTrap);
1383
1384 /* Also store it in our guest trap array. */
1385 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1386
1387 Log(("Setting trap handler %x to %08X (direct)\n", iTrap, pHandler));
1388 return VINF_SUCCESS;
1389 }
1390 /* ok, let's try to install a trampoline handler then. */
1391 }
1392 }
1393
1394 if ( GuestIdte.Gen.u1Present
1395 && ( GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32
1396 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
1397 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0))
1398 {
1399 /*
1400 * Save handler which can be used for a trampoline call inside the GC
1401 */
1402 Log(("Setting trap handler %x to %08X\n", iTrap, pHandler));
1403 pVM->trpm.s.aGuestTrapHandler[iTrap] = pHandler;
1404 return VINF_SUCCESS;
1405 }
1406 return VERR_INVALID_PARAMETER;
1407}
1408
1409
1410/**
1411 * Check if address is a gate handler (interrupt/trap/task/anything).
1412 *
1413 * @returns True is gate handler, false if not.
1414 *
1415 * @param pVM The cross context VM structure.
1416 * @param GCPtr GC address to check.
1417 */
1418VMMR3DECL(bool) TRPMR3IsGateHandler(PVM pVM, RTRCPTR GCPtr)
1419{
1420 /* Only valid in raw mode which implies 1 VCPU */
1421 Assert(PATMIsEnabled(pVM) && pVM->cCpus == 1);
1422 PVMCPU pVCpu = &pVM->aCpus[0];
1423
1424 /*
1425 * Read IDTR and calc last entry.
1426 */
1427 uint16_t cbIDT;
1428 RTGCPTR GCPtrIDTE = CPUMGetGuestIDTR(pVCpu, &cbIDT);
1429 unsigned cEntries = (cbIDT + 1) / sizeof(VBOXIDTE);
1430 if (!cEntries)
1431 return false;
1432 RTGCPTR GCPtrIDTELast = GCPtrIDTE + (cEntries - 1) * sizeof(VBOXIDTE);
1433
1434 /*
1435 * Outer loop: iterate pages.
1436 */
1437 while (GCPtrIDTE <= GCPtrIDTELast)
1438 {
1439 /*
1440 * Convert this page to a HC address.
1441 * (This function checks for not-present pages.)
1442 */
1443 PCVBOXIDTE pIDTE;
1444 PGMPAGEMAPLOCK Lock;
1445 int rc = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrIDTE, (const void **)&pIDTE, &Lock);
1446 if (RT_SUCCESS(rc))
1447 {
1448 /*
1449 * Inner Loop: Iterate the data on this page looking for an entry equal to GCPtr.
1450 * N.B. Member of the Flat Earth Society...
1451 */
1452 while (GCPtrIDTE <= GCPtrIDTELast)
1453 {
1454 if (pIDTE->Gen.u1Present)
1455 {
1456 RTRCPTR GCPtrHandler = VBOXIDTE_OFFSET(*pIDTE);
1457 if (GCPtr == GCPtrHandler)
1458 {
1459 PGMPhysReleasePageMappingLock(pVM, &Lock);
1460 return true;
1461 }
1462 }
1463
1464 /* next entry */
1465 if ((GCPtrIDTE & PAGE_OFFSET_MASK) + sizeof(VBOXIDTE) >= PAGE_SIZE)
1466 {
1467 AssertMsg(!(GCPtrIDTE & (sizeof(VBOXIDTE) - 1)),
1468 ("IDT is crossing pages and it's not aligned! GCPtrIDTE=%#x cbIDT=%#x\n", GCPtrIDTE, cbIDT));
1469 GCPtrIDTE += sizeof(VBOXIDTE);
1470 break;
1471 }
1472 GCPtrIDTE += sizeof(VBOXIDTE);
1473 pIDTE++;
1474 }
1475 PGMPhysReleasePageMappingLock(pVM, &Lock);
1476 }
1477 else
1478 {
1479 /* Skip to the next page (if any). Take care not to wrap around the address space. */
1480 if ((GCPtrIDTELast >> PAGE_SHIFT) == (GCPtrIDTE >> PAGE_SHIFT))
1481 return false;
1482 GCPtrIDTE = RT_ALIGN_T(GCPtrIDTE, PAGE_SIZE, RTGCPTR) + PAGE_SIZE + (GCPtrIDTE & (sizeof(VBOXIDTE) - 1));
1483 }
1484 }
1485 return false;
1486}
1487
1488#endif /* VBOX_WITH_RAW_MODE */
1489
1490/**
1491 * Inject event (such as external irq or trap)
1492 *
1493 * @returns VBox status code.
1494 * @param pVM The cross context VM structure.
1495 * @param pVCpu The cross context virtual CPU structure.
1496 * @param enmEvent Trpm event type
1497 */
1498VMMR3DECL(int) TRPMR3InjectEvent(PVM pVM, PVMCPU pVCpu, TRPMEVENT enmEvent)
1499{
1500#ifdef VBOX_WITH_RAW_MODE
1501 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1502 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
1503#endif
1504 Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
1505
1506 /* Currently only useful for external hardware interrupts. */
1507 Assert(enmEvent == TRPM_HARDWARE_INT);
1508
1509#if defined(TRPM_FORWARD_TRAPS_IN_GC)
1510
1511# ifdef LOG_ENABLED
1512 DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "TRPMInject");
1513 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "TRPMInject");
1514# endif
1515
1516 uint8_t u8Interrupt = 0;
1517 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1518 Log(("TRPMR3InjectEvent: CPU%d u8Interrupt=%d (%#x) rc=%Rrc\n", pVCpu->idCpu, u8Interrupt, u8Interrupt, rc));
1519 if (RT_SUCCESS(rc))
1520 {
1521 if (EMIsSupervisorCodeRecompiled(pVM) || !VM_IS_RAW_MODE_ENABLED(pVM))
1522 {
1523 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1524 if (!VM_IS_NEM_ENABLED(pVM))
1525 {
1526 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1527 AssertRC(rc);
1528 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM : VINF_EM_RESCHEDULE_REM;
1529 }
1530 VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8Interrupt, enmEvent, 0, 0, 0);
1531 if (rcStrict == VINF_SUCCESS)
1532 return VINF_EM_RESCHEDULE;
1533 return VBOXSTRICTRC_TODO(rcStrict);
1534 }
1535
1536 /* If the guest gate is not patched, then we will check (again) if we can patch it. */
1537 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] == TRPM_INVALID_HANDLER)
1538 {
1539 CSAMR3CheckGates(pVM, u8Interrupt, 1);
1540 Log(("TRPMR3InjectEvent: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
1541 }
1542
1543 if (pVM->trpm.s.aGuestTrapHandler[u8Interrupt] != TRPM_INVALID_HANDLER)
1544 {
1545 /* Must check pending forced actions as our IDT or GDT might be out of sync */
1546 rc = EMR3CheckRawForcedActions(pVM, pVCpu);
1547 if (rc == VINF_SUCCESS)
1548 {
1549 /* There's a handler -> let's execute it in raw mode */
1550 rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, enmEvent, -1);
1551 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
1552 {
1553 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
1554
1555 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1556 return VINF_EM_RESCHEDULE_RAW;
1557 }
1558 }
1559 }
1560 else
1561 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
1562
1563 rc = TRPMAssertTrap(pVCpu, u8Interrupt, enmEvent);
1564 AssertRCReturn(rc, rc);
1565 }
1566 else
1567 {
1568 /* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1569 AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR || rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1570 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM
1571 : VM_IS_NEM_ENABLED(pVM) ? VINF_EM_RESCHEDULE
1572 : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1573 }
1574
1575 /** @todo check if it's safe to translate the patch address to the original guest address.
1576 * this implies a safe state in translated instructions and should take sti successors into account (instruction fusing)
1577 */
1578 /* Note: if it's a PATM address, then we'll go back to raw mode regardless of the return codes below. */
1579
1580 /* Fall back to the recompiler */
1581 return VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1582
1583#else /* !TRPM_FORWARD_TRAPS_IN_GC */
1584 RT_NOREF(pVM, enmEvent);
1585 uint8_t u8Interrupt = 0;
1586 int rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
1587 Log(("TRPMR3InjectEvent: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
1588 if (RT_SUCCESS(rc))
1589 {
1590 if (!VM_IS_NEM_ENABLED(pVM))
1591 {
1592 rc = TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
1593 AssertRC(rc);
1594 }
1595 else
1596 {
1597 VBOXSTRICTRC rcStrict = IEMInjectTrap(pVCpu, u8Interrupt, enmEvent, 0, 0, 0);
1598 if (rcStrict != VINF_SUCCESS)
1599 return VBOXSTRICTRC_TODO(rcStrict);
1600 }
1601 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]);
1602 }
1603 else
1604 {
1605 /* Can happen if the interrupt is masked by TPR or APIC is disabled. */
1606 AssertMsg(rc == VERR_APIC_INTR_MASKED_BY_TPR || rc == VERR_NO_DATA, ("PDMGetInterrupt failed. rc=%Rrc\n", rc));
1607 }
1608 return HMR3IsActive(pVCpu) ? VINF_EM_RESCHEDULE_HM
1609 : VM_IS_NEM_ENABLED(pVM) ? VINF_EM_RESCHEDULE
1610 : VINF_EM_RESCHEDULE_REM; /* (Heed the halted state if this is changed!) */
1611#endif /* !TRPM_FORWARD_TRAPS_IN_GC */
1612}
1613
1614
1615/**
1616 * Displays the pending TRPM event.
1617 *
1618 * @param pVM The cross context VM structure.
1619 * @param pHlp The info helper functions.
1620 * @param pszArgs Arguments, ignored.
1621 */
1622static DECLCALLBACK(void) trpmR3InfoEvent(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1623{
1624 NOREF(pszArgs);
1625 PVMCPU pVCpu = VMMGetCpu(pVM);
1626 if (!pVCpu)
1627 pVCpu = &pVM->aCpus[0];
1628
1629 uint8_t uVector;
1630 uint8_t cbInstr;
1631 TRPMEVENT enmTrapEvent;
1632 RTGCUINT uErrorCode;
1633 RTGCUINTPTR uCR2;
1634 int rc = TRPMQueryTrapAll(pVCpu, &uVector, &enmTrapEvent, &uErrorCode, &uCR2, &cbInstr);
1635 if (RT_SUCCESS(rc))
1636 {
1637 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event\n", pVCpu->idCpu);
1638 static const char * const s_apszTrpmEventType[] =
1639 {
1640 "Trap",
1641 "Hardware Int",
1642 "Software Int"
1643 };
1644 if (RT_LIKELY((size_t)enmTrapEvent < RT_ELEMENTS(s_apszTrpmEventType)))
1645 {
1646 pHlp->pfnPrintf(pHlp, " Type = %s\n", s_apszTrpmEventType[enmTrapEvent]);
1647 pHlp->pfnPrintf(pHlp, " uVector = %#x\n", uVector);
1648 pHlp->pfnPrintf(pHlp, " uErrorCode = %#RGu\n", uErrorCode);
1649 pHlp->pfnPrintf(pHlp, " uCR2 = %#RGp\n", uCR2);
1650 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", cbInstr);
1651 }
1652 else
1653 pHlp->pfnPrintf(pHlp, " Type = %#x (Invalid!)\n", enmTrapEvent);
1654 }
1655 else if (rc == VERR_TRPM_NO_ACTIVE_TRAP)
1656 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event (None)\n", pVCpu->idCpu);
1657 else
1658 pHlp->pfnPrintf(pHlp, "CPU[%u]: TRPM event - Query failed! rc=%Rrc\n", pVCpu->idCpu, rc);
1659}
1660
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