Changeset 74789 in vbox
- Timestamp:
- Oct 12, 2018 10:34:32 AM (6 years ago)
- Location:
- trunk
- Files:
-
- 22 edited
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include/VBox/vmm/vm.h (modified) (5 diffs)
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src/VBox/VMM/VMMAll/EMAll.cpp (modified) (2 diffs)
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src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h (modified) (4 diffs)
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src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h (modified) (1 diff)
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src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h (modified) (7 diffs)
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src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/PGMAllPhys.cpp (modified) (1 diff)
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src/VBox/VMM/VMMAll/TRPMAll.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR0/HMR0.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (8 diffs)
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src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (4 diffs)
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src/VBox/VMM/VMMR0/NEMR0Native-win.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/EM.cpp (modified) (13 diffs)
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src/VBox/VMM/VMMR3/EMHM.cpp (modified) (8 diffs)
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src/VBox/VMM/VMMR3/EMR3Nem.cpp (modified) (7 diffs)
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src/VBox/VMM/VMMR3/EMRaw.cpp (modified) (12 diffs)
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src/VBox/VMM/VMMR3/NEMR3Native-win.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/TRPM.cpp (modified) (1 diff)
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src/VBox/VMM/VMMR3/VMEmt.cpp (modified) (11 diffs)
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src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp (modified) (4 diffs)
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src/VBox/VMM/include/EMHandleRCTmpl.h (modified) (2 diffs)
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src/recompiler/VBoxRecompiler.c (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/vm.h
r74787 r74789 705 705 * @param pVCpu The cross context virtual CPU structure. 706 706 * @param fFlag The flag to check. 707 * @sa VMCPU_FF_IS_ANY_SET 707 708 */ 708 709 #if !defined(VBOX_STRICT) || !defined(RT_COMPILER_SUPPORTS_LAMBDA) … … 725 726 #define VM_FF_IS_PENDING(pVM, fFlags) RT_BOOL((pVM)->fGlobalForcedActions & (fFlags)) 726 727 727 /** @def VMCPU_FF_IS_ PENDING728 * Checks if one or more force action in the specified set is pendingfor the given VCPU.728 /** @def VMCPU_FF_IS_ANY_SET 729 * Checks if two or more force action flags in the specified set is set for the given VCPU. 729 730 * 730 731 * @param pVCpu The cross context virtual CPU structure. 731 732 * @param fFlags The flags to check for. 732 */ 733 #define VMCPU_FF_IS_PENDING(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags)) 733 * @sa VMCPU_FF_IS_SET 734 */ 735 #define VMCPU_FF_IS_ANY_SET(pVCpu, fFlags) RT_BOOL((pVCpu)->fLocalForcedActions & (fFlags)) 734 736 735 737 /** @def VM_FF_TEST_AND_CLEAR … … 739 741 * @returns false if the bit was clear. 740 742 * @param pVM The cross context VM structure. 741 * @param iBit Bit position to check and clear742 */ 743 #define VM_FF_TEST_AND_CLEAR(pVM, iBit) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, iBit##_BIT))743 * @param fFlag Flag constant to check and clear (_BIT is appended). 744 */ 745 #define VM_FF_TEST_AND_CLEAR(pVM, fFlag) (ASMAtomicBitTestAndClear(&(pVM)->fGlobalForcedActions, fFlag##_BIT)) 744 746 745 747 /** @def VMCPU_FF_TEST_AND_CLEAR … … 749 751 * @returns false if the bit was clear. 750 752 * @param pVCpu The cross context virtual CPU structure. 751 * @param iBit Bit position to check and clear752 */ 753 #define VMCPU_FF_TEST_AND_CLEAR(pVCpu, iBit) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, iBit##_BIT))753 * @param fFlag Flag constant to check and clear (_BIT is appended). 754 */ 755 #define VMCPU_FF_TEST_AND_CLEAR(pVCpu, fFlag) (ASMAtomicBitTestAndClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT)) 754 756 755 757 /** @def VM_FF_IS_PENDING_EXCEPT … … 761 763 * @param fExcpt The flags that should not be set. 762 764 */ 763 #define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) ) 765 #define VM_FF_IS_PENDING_EXCEPT(pVM, fFlags, fExcpt) \ 766 ( ((pVM)->fGlobalForcedActions & (fFlags)) && !((pVM)->fGlobalForcedActions & (fExcpt)) ) 764 767 765 768 /** @def VM_IS_EMT -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r74204 r74789 218 218 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0)) ) 219 219 { 220 if (VMCPU_FF_IS_ PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)))220 if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))) 221 221 { 222 222 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0); … … 241 241 /** @todo Shouldn't we be checking GIF here? */ 242 242 if (pCtx->eflags.Bits.u1IF) 243 return VMCPU_FF_IS_ PENDING(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC));243 return VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)); 244 244 return false; 245 245 } -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h
r74668 r74789 74 74 # define IEM_CHECK_FF_YIELD_REPSTR_MAYBE_RETURN(a_pVM, a_pVCpu, a_fEflags) \ 75 75 do { \ 76 if (RT_LIKELY( !VMCPU_FF_IS_ PENDING(a_pVCpu, (a_fEflags) & X86_EFL_IF ? VMCPU_FF_YIELD_REPSTR_MASK \76 if (RT_LIKELY( !VMCPU_FF_IS_ANY_SET(a_pVCpu, (a_fEflags) & X86_EFL_IF ? VMCPU_FF_YIELD_REPSTR_MASK \ 77 77 : VMCPU_FF_YIELD_REPSTR_NOINT_MASK) \ 78 78 && !VM_FF_IS_PENDING(a_pVM, VM_FF_YIELD_REPSTR_MASK) \ … … 97 97 # define IEM_CHECK_FF_YIELD_REPSTR_MAYBE_RETURN(a_pVM, a_pVCpu, a_fEflags) \ 98 98 do { \ 99 if (RT_LIKELY( !VMCPU_FF_IS_ PENDING(a_pVCpu, (a_fEflags) & X86_EFL_IF ? VMCPU_FF_YIELD_REPSTR_MASK \99 if (RT_LIKELY( !VMCPU_FF_IS_ANY_SET(a_pVCpu, (a_fEflags) & X86_EFL_IF ? VMCPU_FF_YIELD_REPSTR_MASK \ 100 100 : VMCPU_FF_YIELD_REPSTR_NOINT_MASK) \ 101 101 && !VM_FF_IS_PENDING(a_pVM, VM_FF_YIELD_REPSTR_MASK) \ … … 118 118 #define IEM_CHECK_FF_HIGH_PRIORITY_POST_REPSTR_MAYBE_RETURN(a_pVM, a_pVCpu, a_fExitExpr) \ 119 119 do { \ 120 if (RT_LIKELY( ( !VMCPU_FF_IS_ PENDING(a_pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK) \120 if (RT_LIKELY( ( !VMCPU_FF_IS_ANY_SET(a_pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK) \ 121 121 && !VM_FF_IS_PENDING(a_pVM, VM_FF_HIGH_PRIORITY_POST_REPSTR_MASK)) \ 122 122 || (a_fExitExpr) )) \ … … 139 139 #define IEM_CHECK_FF_CPU_HIGH_PRIORITY_POST_REPSTR_MAYBE_RETURN(a_pVM, a_pVCpu, a_fExitExpr) \ 140 140 do { \ 141 if (RT_LIKELY( !VMCPU_FF_IS_ PENDING(a_pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK) \141 if (RT_LIKELY( !VMCPU_FF_IS_ANY_SET(a_pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK) \ 142 142 || (a_fExitExpr) )) \ 143 143 { /* very likely */ } \ -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
r74785 r74789 1952 1952 pVCpu->cpum.GstCtx.hwvirt.fLocalForcedActions = pVCpu->fLocalForcedActions & VMCPU_FF_BLOCK_NMIS; 1953 1953 1954 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS))1954 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS)) 1955 1955 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS | VMCPU_FF_BLOCK_NMIS); 1956 1956 } -
trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h
r74785 r74789 434 434 aValues[iReg - 1].InterruptState.InterruptShadow = 1; 435 435 /** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */ 436 //if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))436 //if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)) 437 437 // aValues[iReg - 1].InterruptState.NmiMasked = 1; 438 438 } … … 3962 3962 { 3963 3963 APICUpdatePendingInterrupts(pVCpu); 3964 if (!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC3964 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC 3965 3965 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI)) 3966 3966 return VINF_SUCCESS; … … 4015 4015 * APIC or PIC interrupt? 4016 4016 */ 4017 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))4017 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 4018 4018 { 4019 4019 if ( !fInhibitInterrupts … … 4115 4115 */ 4116 4116 pVCpu->nem.s.fDesiredInterruptWindows = 0; 4117 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC4117 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC 4118 4118 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI)) 4119 4119 { … … 4189 4189 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt); 4190 4190 if ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC) 4191 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))4191 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 4192 4192 { 4193 4193 # ifdef NEM_WIN_TEMPLATE_MODE_OWN_RUN_API … … 4304 4304 */ 4305 4305 if ( !VM_FF_IS_PENDING( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK) 4306 && !VMCPU_FF_IS_ PENDING(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )4306 && !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) ) 4307 4307 continue; 4308 4308 … … 4357 4357 fImport = CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_NEM_WIN_INHIBIT_INT; 4358 4358 # endif 4359 else if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC4359 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC 4360 4360 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI)) 4361 4361 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK; -
trunk/src/VBox/VMM/VMMAll/PGMAll.cpp
r73327 r74789 2665 2665 { 2666 2666 AssertMsg(rc == VINF_PGM_SYNC_CR3, ("%Rrc\n", rc)); 2667 Assert(VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3));2667 Assert(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_PGM_SYNC_CR3)); 2668 2668 pVCpu->pgm.s.GCPhysCR3 = GCPhysOldCR3; 2669 2669 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_MAP_CR3; -
trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp
r73376 r74789 315 315 AssertMsg( rc == VINF_SUCCESS 316 316 || ( rc == VINF_PGM_SYNC_CR3 317 && VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))317 && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 318 318 , ("%Rrc\n", rc)); 319 319 rc = VINF_SUCCESS; -
trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp
r70948 r74789 543 543 544 544 Assert(PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame))); 545 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));545 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); 546 546 547 547 if (GCPtrIDT && iGate * sizeof(VBOXIDTE) >= cbIDT) -
trunk/src/VBox/VMM/VMMR0/HMR0.cpp
r73389 r74789 1554 1554 { 1555 1555 PHMGLOBALCPUINFO pHostCpu = &g_HmR0.aCpuInfo[RTMpCpuId()]; 1556 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));1556 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)); 1557 1557 Assert(pHostCpu->fConfigured); 1558 1558 AssertReturn(!ASMAtomicReadBool(&g_HmR0.fSuspended), VERR_HM_SUSPEND_PENDING); -
trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
r74785 r74789 3738 3738 3739 3739 Log4Func(("fVirtualGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n", 3740 fVirtualGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC),3740 fVirtualGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC), 3741 3741 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))); 3742 3742 … … 3788 3788 * see AMD spec. 15.21.4 "Injecting Virtual (INTR) Interrupts". 3789 3789 */ 3790 else if ( VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)3790 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC) 3791 3791 && !pVCpu->hm.s.fSingleInstruction) 3792 3792 { … … 3864 3864 Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n", 3865 3865 fGif, fBlockNmi, fBlockInt, fIntShadow, 3866 VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC),3866 VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC), 3867 3867 VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))); 3868 3868 … … 3899 3899 * it from the APIC device. 3900 3900 */ 3901 else if ( VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)3901 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC) 3902 3902 && !pVCpu->hm.s.fSingleInstruction) 3903 3903 { … … 4222 4222 if ( VM_FF_IS_PENDING(pVM, !pVCpu->hm.s.fSingleInstruction 4223 4223 ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK) 4224 || VMCPU_FF_IS_ PENDING(pVCpu, !pVCpu->hm.s.fSingleInstruction4224 || VMCPU_FF_IS_ANY_SET(pVCpu, !pVCpu->hm.s.fSingleInstruction 4225 4225 ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) ) 4226 4226 { 4227 4227 /* Pending PGM C3 sync. */ 4228 if (VMCPU_FF_IS_ PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))4228 if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 4229 4229 { 4230 4230 int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, … … 4240 4240 /* -XXX- what was that about single stepping? */ 4241 4241 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK) 4242 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))4242 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 4243 4243 { 4244 4244 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF); … … 4370 4370 pSvmTransient->fEFlags = ASMIntDisableFlags(); 4371 4371 if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC) 4372 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))4372 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 4373 4373 { 4374 4374 ASMSetFlags(pSvmTransient->fEFlags); … … 4483 4483 pSvmTransient->fEFlags = ASMIntDisableFlags(); 4484 4484 if ( VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC) 4485 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))4485 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 4486 4486 { 4487 4487 ASMSetFlags(pSvmTransient->fEFlags); -
trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r74785 r74789 6901 6901 if ( !fStepping 6902 6902 ? !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_MASK) 6903 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK)6903 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_MASK) 6904 6904 : !VM_FF_IS_PENDING(pVM, VM_FF_HP_R0_PRE_HM_STEP_MASK) 6905 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )6905 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) ) 6906 6906 return VINF_SUCCESS; 6907 6907 6908 6908 /* Pending PGM C3 sync. */ 6909 if (VMCPU_FF_IS_ PENDING(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))6909 if (VMCPU_FF_IS_ANY_SET(pVCpu,VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 6910 6910 { 6911 6911 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx; … … 6923 6923 /* Pending HM-to-R3 operations (critsects, timers, EMT rendezvous etc.) */ 6924 6924 if ( VM_FF_IS_PENDING(pVM, VM_FF_HM_TO_R3_MASK) 6925 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))6925 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 6926 6926 { 6927 6927 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchHmToR3FF); … … 7541 7541 * a valid interrupt we must- deliver the interrupt. We can no longer re-request it from the APIC. 7542 7542 */ 7543 else if ( VMCPU_FF_IS_ PENDING(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))7543 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 7544 7544 && !pVCpu->hm.s.fSingleInstruction) 7545 7545 { … … 8585 8585 8586 8586 if ( ( !VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC) 8587 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK))8587 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK)) 8588 8588 || ( fStepping /* Optimized for the non-stepping case, so a bit of unnecessary work when stepping. */ 8589 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) )8589 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK & ~(VMCPU_FF_TIMER | VMCPU_FF_PDM_CRITSECT))) ) 8590 8590 { 8591 8591 if (!RTThreadPreemptIsPending(NIL_RTTHREAD)) -
trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp
r74785 r74789 1239 1239 pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1; 1240 1240 /** @todo Retrieve NMI state, currently assuming it's zero. (yes this may happen on I/O) */ 1241 //if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))1241 //if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)) 1242 1242 // pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1; 1243 1243 iReg++; -
trunk/src/VBox/VMM/VMMR3/EM.cpp
r74785 r74789 1137 1137 1138 1138 #if defined(VBOX_STRICT) && defined(DEBUG_bird) 1139 AssertMsg( VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)1139 AssertMsg( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) 1140 1140 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */ 1141 1141 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu))); … … 1188 1188 */ 1189 1189 if ( VM_FF_IS_PENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET) 1190 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))1190 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST)) 1191 1191 { 1192 1192 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions)); … … 1223 1223 */ 1224 1224 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 1225 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))1225 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 1226 1226 { 1227 1227 #ifdef VBOX_WITH_REM … … 1275 1275 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER); 1276 1276 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK) 1277 || VMCPU_FF_IS_ PENDING(pVCpu,1277 || VMCPU_FF_IS_ANY_SET(pVCpu, 1278 1278 VMCPU_FF_ALL_REM_MASK 1279 1279 & VM_WHEN_RAW_MODE(~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE), UINT32_MAX)) ) … … 1400 1400 */ 1401 1401 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK) 1402 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT))1402 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT)) 1403 1403 return VINF_SUCCESS; 1404 1404 } … … 1738 1738 { 1739 1739 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI); 1740 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))1740 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 1741 1741 { 1742 1742 if (CPUMIsGuestSvmCtrlInterceptSet(pVCpu, &pVCpu->cpum.GstCtx, SVM_CTRL_INTERCEPT_INTR)) … … 1864 1864 */ 1865 1865 if ( VM_FF_IS_PENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK) 1866 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )1866 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) ) 1867 1867 { 1868 1868 /* … … 2057 2057 */ 2058 2058 if ( !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY) 2059 && VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))2059 && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK)) 2060 2060 { 2061 2061 /* … … 2095 2095 */ 2096 2096 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK) 2097 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))2097 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK)) 2098 2098 { 2099 2099 /* … … 2165 2165 { 2166 2166 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RFLAGS); 2167 if ( VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)2167 if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC) 2168 2168 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM 2169 2169 && pVCpu->cpum.GstCtx.hwvirt.fGif … … 2417 2417 && rc != VINF_EM_OFF 2418 2418 && ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK) 2419 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT)))2419 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK & ~VMCPU_FF_UNHALT))) 2420 2420 { 2421 2421 rc = emR3ForcedActions(pVM, pVCpu, rc); … … 2855 2855 APICUpdatePendingInterrupts(pVCpu); 2856 2856 2857 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC2857 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC 2858 2858 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT)) 2859 2859 { … … 2869 2869 check VMCPU_FF_UPDATE_APIC here. */ 2870 2870 if ( rc == VINF_SUCCESS 2871 && VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT))2871 && VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT)) 2872 2872 { 2873 2873 Log(("EMR3ExecuteVM: Triggering reschedule on pending NMI/SMI/UNHALT after HLT\n")); -
trunk/src/VBox/VMM/VMMR3/EMHM.cpp
r73617 r74789 96 96 */ 97 97 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 98 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))98 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 99 99 { 100 100 VBOXSTRICTRC rcStrict = emR3HmForcedActions(pVM, pVCpu); … … 120 120 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); 121 121 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 122 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))122 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 123 123 { 124 124 rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict); … … 301 301 * Sync page directory. 302 302 */ 303 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))303 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 304 304 { 305 305 CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4); … … 310 310 311 311 #ifdef VBOX_WITH_RAW_MODE 312 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));312 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 313 313 #endif 314 314 … … 333 333 /** @todo maybe prefetch the supervisor stack page as well */ 334 334 #ifdef VBOX_WITH_RAW_MODE 335 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));335 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 336 336 #endif 337 337 } … … 402 402 */ 403 403 #ifdef VBOX_WITH_RAW_MODE 404 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));404 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 405 405 #endif 406 406 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 407 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))407 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 408 408 { 409 409 rc = emR3HmForcedActions(pVM, pVCpu); … … 466 466 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); 467 467 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 468 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))468 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 469 469 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc)); 470 470 … … 486 486 #endif 487 487 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_MASK) 488 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_MASK))488 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_MASK)) 489 489 { 490 490 rc = emR3ForcedActions(pVM, pVCpu, rc); -
trunk/src/VBox/VMM/VMMR3/EMR3Nem.cpp
r74786 r74789 96 96 */ 97 97 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 98 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))98 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 99 99 { 100 100 VBOXSTRICTRC rcStrict = emR3NemForcedActions(pVM, pVCpu); … … 120 120 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); 121 121 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 122 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))122 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 123 123 { 124 124 rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict); … … 301 301 { 302 302 #ifdef VBOX_WITH_RAW_MODE 303 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));303 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 304 304 #endif 305 305 … … 307 307 * Sync page directory should not happen in NEM mode. 308 308 */ 309 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))309 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 310 310 { 311 311 Log(("NEM: TODO: Make VMCPU_FF_PGM_SYNC_CR3 / VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL quiet! (%#x)\n", pVCpu->fLocalForcedActions)); … … 380 380 */ 381 381 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 382 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))382 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 383 383 { 384 384 rcStrict = emR3NemForcedActions(pVM, pVCpu); … … 449 449 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); 450 450 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 451 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))451 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 452 452 rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict); 453 453 … … 469 469 #endif 470 470 if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_MASK) 471 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_MASK))471 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_MASK)) 472 472 { 473 473 rcStrict = emR3ForcedActions(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict)); -
trunk/src/VBox/VMM/VMMR3/EMRaw.cpp
r74785 r74789 173 173 */ 174 174 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 175 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))175 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 176 176 { 177 177 rc = emR3RawForcedActions(pVM, pVCpu); … … 1166 1166 * Sync selector tables. 1167 1167 */ 1168 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT))1168 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)) 1169 1169 { 1170 1170 VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu); … … 1209 1209 * Sync page directory. 1210 1210 */ 1211 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))1211 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 1212 1212 { 1213 1213 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI); … … 1216 1216 return rc == VERR_PGM_NO_HYPERVISOR_ADDRESS ? VINF_EM_RESCHEDULE_REM : rc; 1217 1217 1218 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));1218 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 1219 1219 1220 1220 /* Prefetch pages for EIP and ESP. */ … … 1235 1235 } 1236 1236 /** @todo maybe prefetch the supervisor stack page as well */ 1237 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));1237 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT)); 1238 1238 } 1239 1239 … … 1305 1305 || PATMShouldUseRawMode(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip), 1306 1306 ("Tried to execute code with IF at EIP=%08x!\n", pVCpu->cpum.GstCtx.eip)); 1307 if ( !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)1307 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) 1308 1308 && PGMMapHasConflicts(pVM)) 1309 1309 { … … 1318 1318 */ 1319 1319 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 1320 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))1320 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 1321 1321 { 1322 1322 rc = emR3RawForcedActions(pVM, pVCpu); … … 1349 1349 STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b); 1350 1350 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK) 1351 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))1351 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 1352 1352 { 1353 1353 rc = emR3RawForcedActions(pVM, pVCpu); … … 1418 1418 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK); 1419 1419 if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK) 1420 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))1420 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK)) 1421 1421 rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc)); 1422 1422 … … 1425 1425 * Assert TSS consistency & rc vs patch code. 1426 1426 */ 1427 if ( !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */1427 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */ 1428 1428 && EMIsRawRing0Enabled(pVM)) 1429 1429 SELMR3CheckTSS(pVM); … … 1449 1449 * Let's go paranoid! 1450 1450 */ 1451 if ( !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)1451 if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) 1452 1452 && PGMMapHasConflicts(pVM)) 1453 1453 { … … 1485 1485 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d); 1486 1486 if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK | VM_FF_PGM_NO_MEMORY) 1487 || VMCPU_FF_IS_ PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))1487 || VMCPU_FF_IS_ANY_SET(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK)) 1488 1488 { 1489 1489 Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM || (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2U : 1U)); -
trunk/src/VBox/VMM/VMMR3/NEMR3Native-win.cpp
r74616 r74789 1706 1706 { 1707 1707 if ( !VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK | VM_FF_HP_R0_PRE_HM_MASK) 1708 && !VMCPU_FF_IS_ PENDING(pVCpu, (VMCPU_FF_HIGH_PRIORITY_POST_MASK | VMCPU_FF_HP_R0_PRE_HM_MASK)1708 && !VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_HIGH_PRIORITY_POST_MASK | VMCPU_FF_HP_R0_PRE_HM_MASK) 1709 1709 & ~VMCPU_FF_RESUME_GUEST_MASK)) 1710 1710 { -
trunk/src/VBox/VMM/VMMR3/TRPM.cpp
r73097 r74789 1551 1551 if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */) 1552 1552 { 1553 Assert(!VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));1553 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); 1554 1554 1555 1555 STAM_COUNTER_INC(&pVM->trpm.s.paStatForwardedIRQR3[u8Interrupt]); -
trunk/src/VBox/VMM/VMMR3/VMEmt.cpp
r71129 r74789 373 373 STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers); 374 374 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 375 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))375 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 376 376 break; 377 377 uint64_t u64NanoTS; 378 378 TMTimerPollGIP(pVM, pVCpu, &u64NanoTS); 379 379 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 380 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))380 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 381 381 break; 382 382 … … 572 572 STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers); 573 573 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 574 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))574 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 575 575 break; 576 576 … … 581 581 TMTimerPollGIP(pVM, pVCpu, &u64NanoTS); 582 582 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 583 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))583 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 584 584 break; 585 585 … … 721 721 STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers); 722 722 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 723 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))723 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 724 724 break; 725 725 … … 731 731 uint64_t u64GipTime = TMTimerPollGIP(pVM, pVCpu, &u64Delta); 732 732 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 733 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))733 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 734 734 break; 735 735 … … 741 741 VMMR3YieldStop(pVM); 742 742 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 743 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))743 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 744 744 break; 745 745 … … 809 809 */ 810 810 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK) 811 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))811 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK)) 812 812 break; 813 813 … … 899 899 if ( pUVCpu->pVM 900 900 && ( VM_FF_IS_PENDING(pUVCpu->pVM, VM_FF_EXTERNAL_SUSPENDED_MASK) 901 || VMCPU_FF_IS_ PENDING(VMMGetCpu(pUVCpu->pVM), VMCPU_FF_EXTERNAL_SUSPENDED_MASK)901 || VMCPU_FF_IS_ANY_SET(VMMGetCpu(pUVCpu->pVM), VMCPU_FF_EXTERNAL_SUSPENDED_MASK) 902 902 ) 903 903 ) … … 961 961 */ 962 962 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK) 963 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))963 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK)) 964 964 break; 965 965 … … 1110 1110 : VMCPU_FF_EXTERNAL_HALTED_MASK & ~(VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC); 1111 1111 if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK) 1112 || VMCPU_FF_IS_ PENDING(pVCpu, fMask))1112 || VMCPU_FF_IS_ANY_SET(pVCpu, fMask)) 1113 1113 { 1114 1114 LogFlow(("VMR3WaitHalted: returns VINF_SUCCESS (FF %#x FFCPU %#x)\n", pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions)); … … 1191 1191 if ( pVM 1192 1192 && ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK) 1193 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK)1193 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK) 1194 1194 ) 1195 1195 ) -
trunk/src/VBox/VMM/VMMRC/TRPMRCHandlers.cpp
r74785 r74789 212 212 if ( rc == VINF_SUCCESS 213 213 && ( VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC | VM_FF_REQUEST | VM_FF_PGM_NO_MEMORY | VM_FF_PDM_DMA) 214 || VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_TO_R3214 || VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_TO_R3 215 215 | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC 216 216 | VMCPU_FF_REQUEST | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL … … 235 235 236 236 /* Pending Ring-3 action. */ 237 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_TO_R3 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_IEM | VMCPU_FF_IOM))237 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_TO_R3 | VMCPU_FF_PDM_CRITSECT | VMCPU_FF_IEM | VMCPU_FF_IOM)) 238 238 { 239 239 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3); … … 255 255 rc = VINF_EM_PENDING_REQUEST; 256 256 /* Pending GDT/LDT/TSS sync. */ 257 else if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS))257 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS)) 258 258 rc = VINF_SELM_SYNC_GDT; 259 259 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT)) 260 260 rc = VINF_EM_RAW_TO_R3; 261 261 /* Possibly pending interrupt: dispatch it. */ 262 else if ( VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)262 else if ( VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC) 263 263 && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS) 264 264 && PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame)) … … 296 296 * Try sync CR3? 297 297 */ 298 else if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))298 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)) 299 299 { 300 300 #if 1 -
trunk/src/VBox/VMM/include/EMHandleRCTmpl.h
r73203 r74789 136 136 */ 137 137 case VINF_PGM_SYNC_CR3: 138 AssertMsg(VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),138 AssertMsg(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL), 139 139 ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n")); 140 140 rc = VINF_SUCCESS; … … 315 315 */ 316 316 case VINF_SELM_SYNC_GDT: 317 AssertMsg(VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS),317 AssertMsg(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS), 318 318 ("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n")); 319 319 rc = VINF_SUCCESS; -
trunk/src/recompiler/VBoxRecompiler.c
r73617 r74789 1138 1138 pVM->rem.s.Env.interrupt_request = CPU_INTERRUPT_SINGLE_INSTR; 1139 1139 #endif 1140 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))1140 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 1141 1141 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD; 1142 1142 RTLogPrintf("remR3RunLoggingStep: interrupt_request=%#x halted=%d exception_index=%#x\n", … … 1164 1164 case EXCP_SINGLE_INSTR: 1165 1165 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK) 1166 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))1166 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK)) 1167 1167 continue; 1168 1168 RTLogPrintf("remR3RunLoggingStep: rc=VINF_SUCCESS w/ FFs (%#x/%#x)\n", … … 1197 1197 { 1198 1198 if ( !VM_FF_IS_PENDING(pVM, VM_FF_ALL_REM_MASK) 1199 && !VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_ALL_REM_MASK))1199 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_REM_MASK)) 1200 1200 continue; 1201 1201 … … 2540 2540 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC)) 2541 2541 APICUpdatePendingInterrupts(pVCpu); 2542 if (VMCPU_FF_IS_ PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))2542 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 2543 2543 pVM->rem.s.Env.interrupt_request |= CPU_INTERRUPT_HARD; 2544 2544 … … 4484 4484 if (RT_SUCCESS(rc)) 4485 4485 { 4486 if (VMCPU_FF_IS_ PENDING(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))4486 if (VMCPU_FF_IS_ANY_SET(env->pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)) 4487 4487 env->interrupt_request |= CPU_INTERRUPT_HARD; 4488 4488 return u8Interrupt;
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