VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PGMSavedState.cpp@ 43667

Last change on this file since 43667 was 42931, checked in by vboxsync, 12 years ago

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1/* $Id: PGMSavedState.cpp 42931 2012-08-23 08:45:35Z vboxsync $ */
2/** @file
3 * PGM - Page Manager and Monitor, The Saved State Part.
4 */
5
6/*
7 * Copyright (C) 2006-2009 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PGM
23#include <VBox/vmm/pgm.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/ssm.h>
26#include <VBox/vmm/pdmdrv.h>
27#include <VBox/vmm/pdmdev.h>
28#include "PGMInternal.h"
29#include <VBox/vmm/vm.h>
30#include "PGMInline.h"
31
32#include <VBox/param.h>
33#include <VBox/err.h>
34#include <VBox/vmm/ftm.h>
35
36#include <iprt/asm.h>
37#include <iprt/assert.h>
38#include <iprt/crc.h>
39#include <iprt/mem.h>
40#include <iprt/sha.h>
41#include <iprt/string.h>
42#include <iprt/thread.h>
43
44
45/*******************************************************************************
46* Defined Constants And Macros *
47*******************************************************************************/
48/** Saved state data unit version. */
49#define PGM_SAVED_STATE_VERSION 14
50/** Saved state data unit version before the PAE PDPE registers. */
51#define PGM_SAVED_STATE_VERSION_PRE_PAE 13
52/** Saved state data unit version after this includes ballooned page flags in
53 * the state (see @bugref{5515}). */
54#define PGM_SAVED_STATE_VERSION_BALLOON_BROKEN 12
55/** Saved state before the balloon change. */
56#define PGM_SAVED_STATE_VERSION_PRE_BALLOON 11
57/** Saved state data unit version used during 3.1 development, misses the RAM
58 * config. */
59#define PGM_SAVED_STATE_VERSION_NO_RAM_CFG 10
60/** Saved state data unit version for 3.0 (pre teleportation). */
61#define PGM_SAVED_STATE_VERSION_3_0_0 9
62/** Saved state data unit version for 2.2.2 and later. */
63#define PGM_SAVED_STATE_VERSION_2_2_2 8
64/** Saved state data unit version for 2.2.0. */
65#define PGM_SAVED_STATE_VERSION_RR_DESC 7
66/** Saved state data unit version. */
67#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
68
69
70/** @name Sparse state record types
71 * @{ */
72/** Zero page. No data. */
73#define PGM_STATE_REC_RAM_ZERO UINT8_C(0x00)
74/** Raw page. */
75#define PGM_STATE_REC_RAM_RAW UINT8_C(0x01)
76/** Raw MMIO2 page. */
77#define PGM_STATE_REC_MMIO2_RAW UINT8_C(0x02)
78/** Zero MMIO2 page. */
79#define PGM_STATE_REC_MMIO2_ZERO UINT8_C(0x03)
80/** Virgin ROM page. Followed by protection (8-bit) and the raw bits. */
81#define PGM_STATE_REC_ROM_VIRGIN UINT8_C(0x04)
82/** Raw shadowed ROM page. The protection (8-bit) precedes the raw bits. */
83#define PGM_STATE_REC_ROM_SHW_RAW UINT8_C(0x05)
84/** Zero shadowed ROM page. The protection (8-bit) is the only payload. */
85#define PGM_STATE_REC_ROM_SHW_ZERO UINT8_C(0x06)
86/** ROM protection (8-bit). */
87#define PGM_STATE_REC_ROM_PROT UINT8_C(0x07)
88/** Ballooned page. No data. */
89#define PGM_STATE_REC_RAM_BALLOONED UINT8_C(0x08)
90/** The last record type. */
91#define PGM_STATE_REC_LAST PGM_STATE_REC_RAM_BALLOONED
92/** End marker. */
93#define PGM_STATE_REC_END UINT8_C(0xff)
94/** Flag indicating that the data is preceded by the page address.
95 * For RAW pages this is a RTGCPHYS. For MMIO2 and ROM pages this is a 8-bit
96 * range ID and a 32-bit page index.
97 */
98#define PGM_STATE_REC_FLAG_ADDR UINT8_C(0x80)
99/** @} */
100
101/** The CRC-32 for a zero page. */
102#define PGM_STATE_CRC32_ZERO_PAGE UINT32_C(0xc71c0011)
103/** The CRC-32 for a zero half page. */
104#define PGM_STATE_CRC32_ZERO_HALF_PAGE UINT32_C(0xf1e8ba9e)
105
106
107/*******************************************************************************
108* Structures and Typedefs *
109*******************************************************************************/
110/** For loading old saved states. (pre-smp) */
111typedef struct
112{
113 /** If set no conflict checks are required. (boolean) */
114 bool fMappingsFixed;
115 /** Size of fixed mapping */
116 uint32_t cbMappingFixed;
117 /** Base address (GC) of fixed mapping */
118 RTGCPTR GCPtrMappingFixed;
119 /** A20 gate mask.
120 * Our current approach to A20 emulation is to let REM do it and don't bother
121 * anywhere else. The interesting guests will be operating with it enabled anyway.
122 * But should the need arise, we'll subject physical addresses to this mask. */
123 RTGCPHYS GCPhysA20Mask;
124 /** A20 gate state - boolean! */
125 bool fA20Enabled;
126 /** The guest paging mode. */
127 PGMMODE enmGuestMode;
128} PGMOLD;
129
130
131/*******************************************************************************
132* Global Variables *
133*******************************************************************************/
134/** PGM fields to save/load. */
135
136static const SSMFIELD s_aPGMFields[] =
137{
138 SSMFIELD_ENTRY( PGM, fMappingsFixed),
139 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
140 SSMFIELD_ENTRY( PGM, cbMappingFixed),
141 SSMFIELD_ENTRY( PGM, cBalloonedPages),
142 SSMFIELD_ENTRY_TERM()
143};
144
145static const SSMFIELD s_aPGMFieldsPreBalloon[] =
146{
147 SSMFIELD_ENTRY( PGM, fMappingsFixed),
148 SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
149 SSMFIELD_ENTRY( PGM, cbMappingFixed),
150 SSMFIELD_ENTRY_TERM()
151};
152
153static const SSMFIELD s_aPGMCpuFields[] =
154{
155 SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
156 SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
157 SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
158 SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[0]),
159 SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[1]),
160 SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[2]),
161 SSMFIELD_ENTRY( PGMCPU, aGCPhysGstPaePDs[3]),
162 SSMFIELD_ENTRY_TERM()
163};
164
165static const SSMFIELD s_aPGMCpuFieldsPrePae[] =
166{
167 SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
168 SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
169 SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
170 SSMFIELD_ENTRY_TERM()
171};
172
173static const SSMFIELD s_aPGMFields_Old[] =
174{
175 SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
176 SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
177 SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
178 SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
179 SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
180 SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
181 SSMFIELD_ENTRY_TERM()
182};
183
184
185/**
186 * Find the ROM tracking structure for the given page.
187 *
188 * @returns Pointer to the ROM page structure. NULL if the caller didn't check
189 * that it's a ROM page.
190 * @param pVM Pointer to the VM.
191 * @param GCPhys The address of the ROM page.
192 */
193static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys) /** @todo change this to take a hint. */
194{
195 for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
196 pRomRange;
197 pRomRange = pRomRange->CTX_SUFF(pNext))
198 {
199 RTGCPHYS off = GCPhys - pRomRange->GCPhys;
200 if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
201 return &pRomRange->aPages[off >> PAGE_SHIFT];
202 }
203 return NULL;
204}
205
206
207/**
208 * Prepares the ROM pages for a live save.
209 *
210 * @returns VBox status code.
211 * @param pVM Pointer to the VM.
212 */
213static int pgmR3PrepRomPages(PVM pVM)
214{
215 /*
216 * Initialize the live save tracking in the ROM page descriptors.
217 */
218 pgmLock(pVM);
219 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
220 {
221 PPGMRAMRANGE pRamHint = NULL;;
222 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
223
224 for (uint32_t iPage = 0; iPage < cPages; iPage++)
225 {
226 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)PGMROMPROT_INVALID;
227 pRom->aPages[iPage].LiveSave.fWrittenTo = false;
228 pRom->aPages[iPage].LiveSave.fDirty = true;
229 pRom->aPages[iPage].LiveSave.fDirtiedRecently = true;
230 if (!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED))
231 {
232 if (PGMROMPROT_IS_ROM(pRom->aPages[iPage].enmProt))
233 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
234 else
235 {
236 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
237 PPGMPAGE pPage;
238 int rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
239 AssertLogRelMsgRC(rc, ("%Rrc GCPhys=%RGp\n", rc, GCPhys));
240 if (RT_SUCCESS(rc))
241 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(pPage) && !PGM_PAGE_IS_BALLOONED(pPage);
242 else
243 pRom->aPages[iPage].LiveSave.fWrittenTo = !PGM_PAGE_IS_ZERO(&pRom->aPages[iPage].Shadow) && !PGM_PAGE_IS_BALLOONED(&pRom->aPages[iPage].Shadow);
244 }
245 }
246 }
247
248 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
249 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
250 pVM->pgm.s.LiveSave.Rom.cDirtyPages += cPages;
251 }
252 pgmUnlock(pVM);
253
254 return VINF_SUCCESS;
255}
256
257
258/**
259 * Assigns IDs to the ROM ranges and saves them.
260 *
261 * @returns VBox status code.
262 * @param pVM Pointer to the VM.
263 * @param pSSM Saved state handle.
264 */
265static int pgmR3SaveRomRanges(PVM pVM, PSSMHANDLE pSSM)
266{
267 pgmLock(pVM);
268 uint8_t id = 1;
269 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3, id++)
270 {
271 pRom->idSavedState = id;
272 SSMR3PutU8(pSSM, id);
273 SSMR3PutStrZ(pSSM, ""); /* device name */
274 SSMR3PutU32(pSSM, 0); /* device instance */
275 SSMR3PutU8(pSSM, 0); /* region */
276 SSMR3PutStrZ(pSSM, pRom->pszDesc);
277 SSMR3PutGCPhys(pSSM, pRom->GCPhys);
278 int rc = SSMR3PutGCPhys(pSSM, pRom->cb);
279 if (RT_FAILURE(rc))
280 break;
281 }
282 pgmUnlock(pVM);
283 return SSMR3PutU8(pSSM, UINT8_MAX);
284}
285
286
287/**
288 * Loads the ROM range ID assignments.
289 *
290 * @returns VBox status code.
291 *
292 * @param pVM Pointer to the VM.
293 * @param pSSM The saved state handle.
294 */
295static int pgmR3LoadRomRanges(PVM pVM, PSSMHANDLE pSSM)
296{
297 PGM_LOCK_ASSERT_OWNER(pVM);
298
299 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
300 pRom->idSavedState = UINT8_MAX;
301
302 for (;;)
303 {
304 /*
305 * Read the data.
306 */
307 uint8_t id;
308 int rc = SSMR3GetU8(pSSM, &id);
309 if (RT_FAILURE(rc))
310 return rc;
311 if (id == UINT8_MAX)
312 {
313 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
314 AssertLogRelMsg(pRom->idSavedState != UINT8_MAX,
315 ("The \"%s\" ROM was not found in the saved state. Probably due to some misconfiguration\n",
316 pRom->pszDesc));
317 return VINF_SUCCESS; /* the end */
318 }
319 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
320
321 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
322 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
323 AssertLogRelRCReturn(rc, rc);
324
325 uint32_t uInstance;
326 SSMR3GetU32(pSSM, &uInstance);
327 uint8_t iRegion;
328 SSMR3GetU8(pSSM, &iRegion);
329
330 char szDesc[64];
331 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
332 AssertLogRelRCReturn(rc, rc);
333
334 RTGCPHYS GCPhys;
335 SSMR3GetGCPhys(pSSM, &GCPhys);
336 RTGCPHYS cb;
337 rc = SSMR3GetGCPhys(pSSM, &cb);
338 if (RT_FAILURE(rc))
339 return rc;
340 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("GCPhys=%RGp %s\n", GCPhys, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
341 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
342
343 /*
344 * Locate a matching ROM range.
345 */
346 AssertLogRelMsgReturn( uInstance == 0
347 && iRegion == 0
348 && szDevName[0] == '\0',
349 ("GCPhys=%RGp %s\n", GCPhys, szDesc),
350 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
351 PPGMROMRANGE pRom;
352 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
353 {
354 if ( pRom->idSavedState == UINT8_MAX
355 && !strcmp(pRom->pszDesc, szDesc))
356 {
357 pRom->idSavedState = id;
358 break;
359 }
360 }
361 if (!pRom)
362 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("ROM at %RGp by the name '%s' was not found"), GCPhys, szDesc);
363 } /* forever */
364}
365
366
367/**
368 * Scan ROM pages.
369 *
370 * @param pVM Pointer to the VM.
371 */
372static void pgmR3ScanRomPages(PVM pVM)
373{
374 /*
375 * The shadow ROMs.
376 */
377 pgmLock(pVM);
378 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
379 {
380 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
381 {
382 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
383 for (uint32_t iPage = 0; iPage < cPages; iPage++)
384 {
385 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
386 if (pRomPage->LiveSave.fWrittenTo)
387 {
388 pRomPage->LiveSave.fWrittenTo = false;
389 if (!pRomPage->LiveSave.fDirty)
390 {
391 pRomPage->LiveSave.fDirty = true;
392 pVM->pgm.s.LiveSave.Rom.cReadyPages--;
393 pVM->pgm.s.LiveSave.Rom.cDirtyPages++;
394 }
395 pRomPage->LiveSave.fDirtiedRecently = true;
396 }
397 else
398 pRomPage->LiveSave.fDirtiedRecently = false;
399 }
400 }
401 }
402 pgmUnlock(pVM);
403}
404
405
406/**
407 * Takes care of the virgin ROM pages in the first pass.
408 *
409 * This is an attempt at simplifying the handling of ROM pages a little bit.
410 * This ASSUMES that no new ROM ranges will be added and that they won't be
411 * relinked in any way.
412 *
413 * @param pVM Pointer to the VM.
414 * @param pSSM The SSM handle.
415 * @param fLiveSave Whether we're in a live save or not.
416 */
417static int pgmR3SaveRomVirginPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave)
418{
419 if (FTMIsDeltaLoadSaveActive(pVM))
420 return VINF_SUCCESS; /* nothing to do as nothing has changed here */
421
422 pgmLock(pVM);
423 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
424 {
425 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
426 for (uint32_t iPage = 0; iPage < cPages; iPage++)
427 {
428 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
429 PGMROMPROT enmProt = pRom->aPages[iPage].enmProt;
430
431 /* Get the virgin page descriptor. */
432 PPGMPAGE pPage;
433 if (PGMROMPROT_IS_ROM(enmProt))
434 pPage = pgmPhysGetPage(pVM, GCPhys);
435 else
436 pPage = &pRom->aPages[iPage].Virgin;
437
438 /* Get the page bits. (Cannot use pgmPhysGCPhys2CCPtrInternalReadOnly here!) */
439 int rc = VINF_SUCCESS;
440 char abPage[PAGE_SIZE];
441 if ( !PGM_PAGE_IS_ZERO(pPage)
442 && !PGM_PAGE_IS_BALLOONED(pPage))
443 {
444 void const *pvPage;
445 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
446 if (RT_SUCCESS(rc))
447 memcpy(abPage, pvPage, PAGE_SIZE);
448 }
449 else
450 ASMMemZeroPage(abPage);
451 pgmUnlock(pVM);
452 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
453
454 /* Save it. */
455 if (iPage > 0)
456 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN);
457 else
458 {
459 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_VIRGIN | PGM_STATE_REC_FLAG_ADDR);
460 SSMR3PutU8(pSSM, pRom->idSavedState);
461 SSMR3PutU32(pSSM, iPage);
462 }
463 SSMR3PutU8(pSSM, (uint8_t)enmProt);
464 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
465 if (RT_FAILURE(rc))
466 return rc;
467
468 /* Update state. */
469 pgmLock(pVM);
470 pRom->aPages[iPage].LiveSave.u8Prot = (uint8_t)enmProt;
471 if (fLiveSave)
472 {
473 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
474 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
475 pVM->pgm.s.LiveSave.cSavedPages++;
476 }
477 }
478 }
479 pgmUnlock(pVM);
480 return VINF_SUCCESS;
481}
482
483
484/**
485 * Saves dirty pages in the shadowed ROM ranges.
486 *
487 * Used by pgmR3LiveExecPart2 and pgmR3SaveExecMemory.
488 *
489 * @returns VBox status code.
490 * @param pVM Pointer to the VM.
491 * @param pSSM The SSM handle.
492 * @param fLiveSave Whether it's a live save or not.
493 * @param fFinalPass Whether this is the final pass or not.
494 */
495static int pgmR3SaveShadowedRomPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, bool fFinalPass)
496{
497 if (FTMIsDeltaLoadSaveActive(pVM))
498 return VINF_SUCCESS; /* nothing to do as we deal with those pages separately */
499
500 /*
501 * The Shadowed ROMs.
502 *
503 * ASSUMES that the ROM ranges are fixed.
504 * ASSUMES that all the ROM ranges are mapped.
505 */
506 pgmLock(pVM);
507 for (PPGMROMRANGE pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
508 {
509 if (pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)
510 {
511 uint32_t const cPages = pRom->cb >> PAGE_SHIFT;
512 uint32_t iPrevPage = cPages;
513 for (uint32_t iPage = 0; iPage < cPages; iPage++)
514 {
515 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
516 if ( !fLiveSave
517 || ( pRomPage->LiveSave.fDirty
518 && ( ( !pRomPage->LiveSave.fDirtiedRecently
519 && !pRomPage->LiveSave.fWrittenTo)
520 || fFinalPass
521 )
522 )
523 )
524 {
525 uint8_t abPage[PAGE_SIZE];
526 PGMROMPROT enmProt = pRomPage->enmProt;
527 RTGCPHYS GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
528 PPGMPAGE pPage = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : pgmPhysGetPage(pVM, GCPhys);
529 bool fZero = PGM_PAGE_IS_ZERO(pPage) || PGM_PAGE_IS_BALLOONED(pPage); Assert(!PGM_PAGE_IS_BALLOONED(pPage)); /* Shouldn't be ballooned. */
530 int rc = VINF_SUCCESS;
531 if (!fZero)
532 {
533 void const *pvPage;
534 rc = pgmPhysPageMapReadOnly(pVM, pPage, GCPhys, &pvPage);
535 if (RT_SUCCESS(rc))
536 memcpy(abPage, pvPage, PAGE_SIZE);
537 }
538 if (fLiveSave && RT_SUCCESS(rc))
539 {
540 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
541 pRomPage->LiveSave.fDirty = false;
542 pVM->pgm.s.LiveSave.Rom.cReadyPages++;
543 pVM->pgm.s.LiveSave.Rom.cDirtyPages--;
544 pVM->pgm.s.LiveSave.cSavedPages++;
545 }
546 pgmUnlock(pVM);
547 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
548
549 if (iPage - 1U == iPrevPage && iPage > 0)
550 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW));
551 else
552 {
553 SSMR3PutU8(pSSM, (fZero ? PGM_STATE_REC_ROM_SHW_ZERO : PGM_STATE_REC_ROM_SHW_RAW) | PGM_STATE_REC_FLAG_ADDR);
554 SSMR3PutU8(pSSM, pRom->idSavedState);
555 SSMR3PutU32(pSSM, iPage);
556 }
557 rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
558 if (!fZero)
559 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
560 if (RT_FAILURE(rc))
561 return rc;
562
563 pgmLock(pVM);
564 iPrevPage = iPage;
565 }
566 /*
567 * In the final pass, make sure the protection is in sync.
568 */
569 else if ( fFinalPass
570 && pRomPage->LiveSave.u8Prot != pRomPage->enmProt)
571 {
572 PGMROMPROT enmProt = pRomPage->enmProt;
573 pRomPage->LiveSave.u8Prot = (uint8_t)enmProt;
574 pgmUnlock(pVM);
575
576 if (iPage - 1U == iPrevPage && iPage > 0)
577 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT);
578 else
579 {
580 SSMR3PutU8(pSSM, PGM_STATE_REC_ROM_PROT | PGM_STATE_REC_FLAG_ADDR);
581 SSMR3PutU8(pSSM, pRom->idSavedState);
582 SSMR3PutU32(pSSM, iPage);
583 }
584 int rc = SSMR3PutU8(pSSM, (uint8_t)enmProt);
585 if (RT_FAILURE(rc))
586 return rc;
587
588 pgmLock(pVM);
589 iPrevPage = iPage;
590 }
591 }
592 }
593 }
594 pgmUnlock(pVM);
595 return VINF_SUCCESS;
596}
597
598
599/**
600 * Cleans up ROM pages after a live save.
601 *
602 * @param pVM Pointer to the VM.
603 */
604static void pgmR3DoneRomPages(PVM pVM)
605{
606 NOREF(pVM);
607}
608
609
610/**
611 * Prepares the MMIO2 pages for a live save.
612 *
613 * @returns VBox status code.
614 * @param pVM Pointer to the VM.
615 */
616static int pgmR3PrepMmio2Pages(PVM pVM)
617{
618 /*
619 * Initialize the live save tracking in the MMIO2 ranges.
620 * ASSUME nothing changes here.
621 */
622 pgmLock(pVM);
623 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
624 {
625 uint32_t const cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
626 pgmUnlock(pVM);
627
628 PPGMLIVESAVEMMIO2PAGE paLSPages = (PPGMLIVESAVEMMIO2PAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMLIVESAVEMMIO2PAGE) * cPages);
629 if (!paLSPages)
630 return VERR_NO_MEMORY;
631 for (uint32_t iPage = 0; iPage < cPages; iPage++)
632 {
633 /* Initialize it as a dirty zero page. */
634 paLSPages[iPage].fDirty = true;
635 paLSPages[iPage].cUnchangedScans = 0;
636 paLSPages[iPage].fZero = true;
637 paLSPages[iPage].u32CrcH1 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
638 paLSPages[iPage].u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
639 }
640
641 pgmLock(pVM);
642 pMmio2->paLSPages = paLSPages;
643 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages += cPages;
644 }
645 pgmUnlock(pVM);
646 return VINF_SUCCESS;
647}
648
649
650/**
651 * Assigns IDs to the MMIO2 ranges and saves them.
652 *
653 * @returns VBox status code.
654 * @param pVM Pointer to the VM.
655 * @param pSSM Saved state handle.
656 */
657static int pgmR3SaveMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
658{
659 pgmLock(pVM);
660 uint8_t id = 1;
661 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3, id++)
662 {
663 pMmio2->idSavedState = id;
664 SSMR3PutU8(pSSM, id);
665 SSMR3PutStrZ(pSSM, pMmio2->pDevInsR3->pReg->szName);
666 SSMR3PutU32(pSSM, pMmio2->pDevInsR3->iInstance);
667 SSMR3PutU8(pSSM, pMmio2->iRegion);
668 SSMR3PutStrZ(pSSM, pMmio2->RamRange.pszDesc);
669 int rc = SSMR3PutGCPhys(pSSM, pMmio2->RamRange.cb);
670 if (RT_FAILURE(rc))
671 break;
672 }
673 pgmUnlock(pVM);
674 return SSMR3PutU8(pSSM, UINT8_MAX);
675}
676
677
678/**
679 * Loads the MMIO2 range ID assignments.
680 *
681 * @returns VBox status code.
682 *
683 * @param pVM Pointer to the VM.
684 * @param pSSM The saved state handle.
685 */
686static int pgmR3LoadMmio2Ranges(PVM pVM, PSSMHANDLE pSSM)
687{
688 PGM_LOCK_ASSERT_OWNER(pVM);
689
690 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
691 pMmio2->idSavedState = UINT8_MAX;
692
693 for (;;)
694 {
695 /*
696 * Read the data.
697 */
698 uint8_t id;
699 int rc = SSMR3GetU8(pSSM, &id);
700 if (RT_FAILURE(rc))
701 return rc;
702 if (id == UINT8_MAX)
703 {
704 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
705 AssertLogRelMsg(pMmio2->idSavedState != UINT8_MAX, ("%s\n", pMmio2->RamRange.pszDesc));
706 return VINF_SUCCESS; /* the end */
707 }
708 AssertLogRelReturn(id != 0, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
709
710 char szDevName[RT_SIZEOFMEMB(PDMDEVREG, szName)];
711 rc = SSMR3GetStrZ(pSSM, szDevName, sizeof(szDevName));
712 AssertLogRelRCReturn(rc, rc);
713
714 uint32_t uInstance;
715 SSMR3GetU32(pSSM, &uInstance);
716 uint8_t iRegion;
717 SSMR3GetU8(pSSM, &iRegion);
718
719 char szDesc[64];
720 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
721 AssertLogRelRCReturn(rc, rc);
722
723 RTGCPHYS cb;
724 rc = SSMR3GetGCPhys(pSSM, &cb);
725 AssertLogRelMsgReturn(!(cb & PAGE_OFFSET_MASK), ("cb=%RGp %s\n", cb, szDesc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
726
727 /*
728 * Locate a matching MMIO2 range.
729 */
730 PPGMMMIO2RANGE pMmio2;
731 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
732 {
733 if ( pMmio2->idSavedState == UINT8_MAX
734 && pMmio2->iRegion == iRegion
735 && pMmio2->pDevInsR3->iInstance == uInstance
736 && !strcmp(pMmio2->pDevInsR3->pReg->szName, szDevName))
737 {
738 pMmio2->idSavedState = id;
739 break;
740 }
741 }
742 if (!pMmio2)
743 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Failed to locate a MMIO2 range called '%s' owned by %s/%u, region %d"),
744 szDesc, szDevName, uInstance, iRegion);
745
746 /*
747 * Validate the configuration, the size of the MMIO2 region should be
748 * the same.
749 */
750 if (cb != pMmio2->RamRange.cb)
751 {
752 LogRel(("PGM: MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp\n",
753 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb));
754 if (cb > pMmio2->RamRange.cb) /* bad idea? */
755 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("MMIO2 region \"%s\" size mismatch: saved=%RGp config=%RGp"),
756 pMmio2->RamRange.pszDesc, cb, pMmio2->RamRange.cb);
757 }
758 } /* forever */
759}
760
761
762/**
763 * Scans one MMIO2 page.
764 *
765 * @returns True if changed, false if unchanged.
766 *
767 * @param pVM Pointer to the VM.
768 * @param pbPage The page bits.
769 * @param pLSPage The live save tracking structure for the page.
770 *
771 */
772DECLINLINE(bool) pgmR3ScanMmio2Page(PVM pVM, uint8_t const *pbPage, PPGMLIVESAVEMMIO2PAGE pLSPage)
773{
774 /*
775 * Special handling of zero pages.
776 */
777 bool const fZero = pLSPage->fZero;
778 if (fZero)
779 {
780 if (ASMMemIsZeroPage(pbPage))
781 {
782 /* Not modified. */
783 if (pLSPage->fDirty)
784 pLSPage->cUnchangedScans++;
785 return false;
786 }
787
788 pLSPage->fZero = false;
789 pLSPage->u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
790 }
791 else
792 {
793 /*
794 * CRC the first half, if it doesn't match the page is dirty and
795 * we won't check the 2nd half (we'll do that next time).
796 */
797 uint32_t u32CrcH1 = RTCrc32(pbPage, PAGE_SIZE / 2);
798 if (u32CrcH1 == pLSPage->u32CrcH1)
799 {
800 uint32_t u32CrcH2 = RTCrc32(pbPage + PAGE_SIZE / 2, PAGE_SIZE / 2);
801 if (u32CrcH2 == pLSPage->u32CrcH2)
802 {
803 /* Probably not modified. */
804 if (pLSPage->fDirty)
805 pLSPage->cUnchangedScans++;
806 return false;
807 }
808
809 pLSPage->u32CrcH2 = u32CrcH2;
810 }
811 else
812 {
813 pLSPage->u32CrcH1 = u32CrcH1;
814 if ( u32CrcH1 == PGM_STATE_CRC32_ZERO_HALF_PAGE
815 && ASMMemIsZeroPage(pbPage))
816 {
817 pLSPage->u32CrcH2 = PGM_STATE_CRC32_ZERO_HALF_PAGE;
818 pLSPage->fZero = true;
819 }
820 }
821 }
822
823 /* dirty page path */
824 pLSPage->cUnchangedScans = 0;
825 if (!pLSPage->fDirty)
826 {
827 pLSPage->fDirty = true;
828 pVM->pgm.s.LiveSave.Mmio2.cReadyPages--;
829 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages++;
830 if (fZero)
831 pVM->pgm.s.LiveSave.Mmio2.cZeroPages--;
832 }
833 return true;
834}
835
836
837/**
838 * Scan for MMIO2 page modifications.
839 *
840 * @param pVM Pointer to the VM.
841 * @param uPass The pass number.
842 */
843static void pgmR3ScanMmio2Pages(PVM pVM, uint32_t uPass)
844{
845 /*
846 * Since this is a bit expensive we lower the scan rate after a little while.
847 */
848 if ( ( (uPass & 3) != 0
849 && uPass > 10)
850 || uPass == SSM_PASS_FINAL)
851 return;
852
853 pgmLock(pVM); /* paranoia */
854 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
855 {
856 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
857 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
858 pgmUnlock(pVM);
859
860 for (uint32_t iPage = 0; iPage < cPages; iPage++)
861 {
862 uint8_t const *pbPage = (uint8_t const *)pMmio2->pvR3 + iPage * PAGE_SIZE;
863 pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]);
864 }
865
866 pgmLock(pVM);
867 }
868 pgmUnlock(pVM);
869
870}
871
872
873/**
874 * Save quiescent MMIO2 pages.
875 *
876 * @returns VBox status code.
877 * @param pVM Pointer to the VM.
878 * @param pSSM The SSM handle.
879 * @param fLiveSave Whether it's a live save or not.
880 * @param uPass The pass number.
881 */
882static int pgmR3SaveMmio2Pages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
883{
884 /** @todo implement live saving of MMIO2 pages. (Need some way of telling the
885 * device that we wish to know about changes.) */
886
887 int rc = VINF_SUCCESS;
888 if (uPass == SSM_PASS_FINAL)
889 {
890 /*
891 * The mop up round.
892 */
893 pgmLock(pVM);
894 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
895 pMmio2 && RT_SUCCESS(rc);
896 pMmio2 = pMmio2->pNextR3)
897 {
898 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
899 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
900 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
901 uint32_t iPageLast = cPages;
902 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
903 {
904 uint8_t u8Type;
905 if (!fLiveSave)
906 u8Type = ASMMemIsZeroPage(pbPage) ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
907 else
908 {
909 /* Try figure if it's a clean page, compare the SHA-1 to be really sure. */
910 if ( !paLSPages[iPage].fDirty
911 && !pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
912 {
913 if (paLSPages[iPage].fZero)
914 continue;
915
916 uint8_t abSha1Hash[RTSHA1_HASH_SIZE];
917 RTSha1(pbPage, PAGE_SIZE, abSha1Hash);
918 if (!memcmp(abSha1Hash, paLSPages[iPage].abSha1Saved, sizeof(abSha1Hash)))
919 continue;
920 }
921 u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
922 pVM->pgm.s.LiveSave.cSavedPages++;
923 }
924
925 if (iPage != 0 && iPage == iPageLast + 1)
926 rc = SSMR3PutU8(pSSM, u8Type);
927 else
928 {
929 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
930 SSMR3PutU8(pSSM, pMmio2->idSavedState);
931 rc = SSMR3PutU32(pSSM, iPage);
932 }
933 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
934 rc = SSMR3PutMem(pSSM, pbPage, PAGE_SIZE);
935 if (RT_FAILURE(rc))
936 break;
937 iPageLast = iPage;
938 }
939 }
940 pgmUnlock(pVM);
941 }
942 /*
943 * Reduce the rate after a little while since the current MMIO2 approach is
944 * a bit expensive.
945 * We position it two passes after the scan pass to avoid saving busy pages.
946 */
947 else if ( uPass <= 10
948 || (uPass & 3) == 2)
949 {
950 pgmLock(pVM);
951 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3;
952 pMmio2 && RT_SUCCESS(rc);
953 pMmio2 = pMmio2->pNextR3)
954 {
955 PPGMLIVESAVEMMIO2PAGE paLSPages = pMmio2->paLSPages;
956 uint8_t const *pbPage = (uint8_t const *)pMmio2->RamRange.pvR3;
957 uint32_t cPages = pMmio2->RamRange.cb >> PAGE_SHIFT;
958 uint32_t iPageLast = cPages;
959 pgmUnlock(pVM);
960
961 for (uint32_t iPage = 0; iPage < cPages; iPage++, pbPage += PAGE_SIZE)
962 {
963 /* Skip clean pages and pages which hasn't quiesced. */
964 if (!paLSPages[iPage].fDirty)
965 continue;
966 if (paLSPages[iPage].cUnchangedScans < 3)
967 continue;
968 if (pgmR3ScanMmio2Page(pVM, pbPage, &paLSPages[iPage]))
969 continue;
970
971 /* Save it. */
972 bool const fZero = paLSPages[iPage].fZero;
973 uint8_t abPage[PAGE_SIZE];
974 if (!fZero)
975 {
976 memcpy(abPage, pbPage, PAGE_SIZE);
977 RTSha1(abPage, PAGE_SIZE, paLSPages[iPage].abSha1Saved);
978 }
979
980 uint8_t u8Type = paLSPages[iPage].fZero ? PGM_STATE_REC_MMIO2_ZERO : PGM_STATE_REC_MMIO2_RAW;
981 if (iPage != 0 && iPage == iPageLast + 1)
982 rc = SSMR3PutU8(pSSM, u8Type);
983 else
984 {
985 SSMR3PutU8(pSSM, u8Type | PGM_STATE_REC_FLAG_ADDR);
986 SSMR3PutU8(pSSM, pMmio2->idSavedState);
987 rc = SSMR3PutU32(pSSM, iPage);
988 }
989 if (u8Type == PGM_STATE_REC_MMIO2_RAW)
990 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
991 if (RT_FAILURE(rc))
992 break;
993
994 /* Housekeeping. */
995 paLSPages[iPage].fDirty = false;
996 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages--;
997 pVM->pgm.s.LiveSave.Mmio2.cReadyPages++;
998 if (u8Type == PGM_STATE_REC_MMIO2_ZERO)
999 pVM->pgm.s.LiveSave.Mmio2.cZeroPages++;
1000 pVM->pgm.s.LiveSave.cSavedPages++;
1001 iPageLast = iPage;
1002 }
1003
1004 pgmLock(pVM);
1005 }
1006 pgmUnlock(pVM);
1007 }
1008
1009 return rc;
1010}
1011
1012
1013/**
1014 * Cleans up MMIO2 pages after a live save.
1015 *
1016 * @param pVM Pointer to the VM.
1017 */
1018static void pgmR3DoneMmio2Pages(PVM pVM)
1019{
1020 /*
1021 * Free the tracking structures for the MMIO2 pages.
1022 * We do the freeing outside the lock in case the VM is running.
1023 */
1024 pgmLock(pVM);
1025 for (PPGMMMIO2RANGE pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
1026 {
1027 void *pvMmio2ToFree = pMmio2->paLSPages;
1028 if (pvMmio2ToFree)
1029 {
1030 pMmio2->paLSPages = NULL;
1031 pgmUnlock(pVM);
1032 MMR3HeapFree(pvMmio2ToFree);
1033 pgmLock(pVM);
1034 }
1035 }
1036 pgmUnlock(pVM);
1037}
1038
1039
1040/**
1041 * Prepares the RAM pages for a live save.
1042 *
1043 * @returns VBox status code.
1044 * @param pVM Pointer to the VM.
1045 */
1046static int pgmR3PrepRamPages(PVM pVM)
1047{
1048
1049 /*
1050 * Try allocating tracking structures for the ram ranges.
1051 *
1052 * To avoid lock contention, we leave the lock every time we're allocating
1053 * a new array. This means we'll have to ditch the allocation and start
1054 * all over again if the RAM range list changes in-between.
1055 *
1056 * Note! pgmR3SaveDone will always be called and it is therefore responsible
1057 * for cleaning up.
1058 */
1059 PPGMRAMRANGE pCur;
1060 pgmLock(pVM);
1061 do
1062 {
1063 for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1064 {
1065 if ( !pCur->paLSPages
1066 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1067 {
1068 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1069 uint32_t const cPages = pCur->cb >> PAGE_SHIFT;
1070 pgmUnlock(pVM);
1071 PPGMLIVESAVERAMPAGE paLSPages = (PPGMLIVESAVERAMPAGE)MMR3HeapAllocZ(pVM, MM_TAG_PGM, cPages * sizeof(PGMLIVESAVERAMPAGE));
1072 if (!paLSPages)
1073 return VERR_NO_MEMORY;
1074 pgmLock(pVM);
1075 if (pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1076 {
1077 pgmUnlock(pVM);
1078 MMR3HeapFree(paLSPages);
1079 pgmLock(pVM);
1080 break; /* try again */
1081 }
1082 pCur->paLSPages = paLSPages;
1083
1084 /*
1085 * Initialize the array.
1086 */
1087 uint32_t iPage = cPages;
1088 while (iPage-- > 0)
1089 {
1090 /** @todo yield critsect! (after moving this away from EMT0) */
1091 PCPGMPAGE pPage = &pCur->aPages[iPage];
1092 paLSPages[iPage].cDirtied = 0;
1093 paLSPages[iPage].fDirty = 1; /* everything is dirty at this time */
1094 paLSPages[iPage].fWriteMonitored = 0;
1095 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1096 paLSPages[iPage].u2Reserved = 0;
1097 switch (PGM_PAGE_GET_TYPE(pPage))
1098 {
1099 case PGMPAGETYPE_RAM:
1100 if ( PGM_PAGE_IS_ZERO(pPage)
1101 || PGM_PAGE_IS_BALLOONED(pPage))
1102 {
1103 paLSPages[iPage].fZero = 1;
1104 paLSPages[iPage].fShared = 0;
1105#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1106 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1107#endif
1108 }
1109 else if (PGM_PAGE_IS_SHARED(pPage))
1110 {
1111 paLSPages[iPage].fZero = 0;
1112 paLSPages[iPage].fShared = 1;
1113#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1114 paLSPages[iPage].u32Crc = UINT32_MAX;
1115#endif
1116 }
1117 else
1118 {
1119 paLSPages[iPage].fZero = 0;
1120 paLSPages[iPage].fShared = 0;
1121#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1122 paLSPages[iPage].u32Crc = UINT32_MAX;
1123#endif
1124 }
1125 paLSPages[iPage].fIgnore = 0;
1126 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1127 break;
1128
1129 case PGMPAGETYPE_ROM_SHADOW:
1130 case PGMPAGETYPE_ROM:
1131 {
1132 paLSPages[iPage].fZero = 0;
1133 paLSPages[iPage].fShared = 0;
1134 paLSPages[iPage].fDirty = 0;
1135 paLSPages[iPage].fIgnore = 1;
1136#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1137 paLSPages[iPage].u32Crc = UINT32_MAX;
1138#endif
1139 pVM->pgm.s.LiveSave.cIgnoredPages++;
1140 break;
1141 }
1142
1143 default:
1144 AssertMsgFailed(("%R[pgmpage]", pPage));
1145 case PGMPAGETYPE_MMIO2:
1146 case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
1147 paLSPages[iPage].fZero = 0;
1148 paLSPages[iPage].fShared = 0;
1149 paLSPages[iPage].fDirty = 0;
1150 paLSPages[iPage].fIgnore = 1;
1151#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1152 paLSPages[iPage].u32Crc = UINT32_MAX;
1153#endif
1154 pVM->pgm.s.LiveSave.cIgnoredPages++;
1155 break;
1156
1157 case PGMPAGETYPE_MMIO:
1158 paLSPages[iPage].fZero = 0;
1159 paLSPages[iPage].fShared = 0;
1160 paLSPages[iPage].fDirty = 0;
1161 paLSPages[iPage].fIgnore = 1;
1162#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1163 paLSPages[iPage].u32Crc = UINT32_MAX;
1164#endif
1165 pVM->pgm.s.LiveSave.cIgnoredPages++;
1166 break;
1167 }
1168 }
1169 }
1170 }
1171 } while (pCur);
1172 pgmUnlock(pVM);
1173
1174 return VINF_SUCCESS;
1175}
1176
1177
1178/**
1179 * Saves the RAM configuration.
1180 *
1181 * @returns VBox status code.
1182 * @param pVM Pointer to the VM.
1183 * @param pSSM The saved state handle.
1184 */
1185static int pgmR3SaveRamConfig(PVM pVM, PSSMHANDLE pSSM)
1186{
1187 uint32_t cbRamHole = 0;
1188 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
1189 AssertRCReturn(rc, rc);
1190
1191 uint64_t cbRam = 0;
1192 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
1193 AssertRCReturn(rc, rc);
1194
1195 SSMR3PutU32(pSSM, cbRamHole);
1196 return SSMR3PutU64(pSSM, cbRam);
1197}
1198
1199
1200/**
1201 * Loads and verifies the RAM configuration.
1202 *
1203 * @returns VBox status code.
1204 * @param pVM Pointer to the VM.
1205 * @param pSSM The saved state handle.
1206 */
1207static int pgmR3LoadRamConfig(PVM pVM, PSSMHANDLE pSSM)
1208{
1209 uint32_t cbRamHoleCfg = 0;
1210 int rc = CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHoleCfg, MM_RAM_HOLE_SIZE_DEFAULT);
1211 AssertRCReturn(rc, rc);
1212
1213 uint64_t cbRamCfg = 0;
1214 rc = CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRamCfg, 0);
1215 AssertRCReturn(rc, rc);
1216
1217 uint32_t cbRamHoleSaved;
1218 SSMR3GetU32(pSSM, &cbRamHoleSaved);
1219
1220 uint64_t cbRamSaved;
1221 rc = SSMR3GetU64(pSSM, &cbRamSaved);
1222 AssertRCReturn(rc, rc);
1223
1224 if ( cbRamHoleCfg != cbRamHoleSaved
1225 || cbRamCfg != cbRamSaved)
1226 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Ram config mismatch: saved=%RX64/%RX32 config=%RX64/%RX32 (RAM/Hole)"),
1227 cbRamSaved, cbRamHoleSaved, cbRamCfg, cbRamHoleCfg);
1228 return VINF_SUCCESS;
1229}
1230
1231#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1232
1233/**
1234 * Calculates the CRC-32 for a RAM page and updates the live save page tracking
1235 * info with it.
1236 *
1237 * @param pVM Pointer to the VM.
1238 * @param pCur The current RAM range.
1239 * @param paLSPages The current array of live save page tracking
1240 * structures.
1241 * @param iPage The page index.
1242 */
1243static void pgmR3StateCalcCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage)
1244{
1245 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1246 PGMPAGEMAPLOCK PgMpLck;
1247 void const *pvPage;
1248 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1249 if (RT_SUCCESS(rc))
1250 {
1251 paLSPages[iPage].u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1252 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1253 }
1254 else
1255 paLSPages[iPage].u32Crc = UINT32_MAX; /* Invalid */
1256}
1257
1258
1259/**
1260 * Verifies the CRC-32 for a page given it's raw bits.
1261 *
1262 * @param pvPage The page bits.
1263 * @param pCur The current RAM range.
1264 * @param paLSPages The current array of live save page tracking
1265 * structures.
1266 * @param iPage The page index.
1267 */
1268static void pgmR3StateVerifyCrc32ForPage(void const *pvPage, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1269{
1270 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1271 {
1272 uint32_t u32Crc = RTCrc32(pvPage, PAGE_SIZE);
1273 Assert( ( !PGM_PAGE_IS_ZERO(&pCur->aPages[iPage])
1274 && !PGM_PAGE_IS_BALLOONED(&pCur->aPages[iPage]))
1275 || u32Crc == PGM_STATE_CRC32_ZERO_PAGE);
1276 AssertMsg(paLSPages[iPage].u32Crc == u32Crc,
1277 ("%08x != %08x for %RGp %R[pgmpage] %s\n", paLSPages[iPage].u32Crc, u32Crc,
1278 pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage], pszWhere));
1279 }
1280}
1281
1282
1283/**
1284 * Verifies the CRC-32 for a RAM page.
1285 *
1286 * @param pVM Pointer to the VM.
1287 * @param pCur The current RAM range.
1288 * @param paLSPages The current array of live save page tracking
1289 * structures.
1290 * @param iPage The page index.
1291 */
1292static void pgmR3StateVerifyCrc32ForRamPage(PVM pVM, PPGMRAMRANGE pCur, PPGMLIVESAVERAMPAGE paLSPages, uint32_t iPage, const char *pszWhere)
1293{
1294 if (paLSPages[iPage].u32Crc != UINT32_MAX)
1295 {
1296 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1297 PGMPAGEMAPLOCK PgMpLck;
1298 void const *pvPage;
1299 int rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, &pCur->aPages[iPage], GCPhys, &pvPage, &PgMpLck);
1300 if (RT_SUCCESS(rc))
1301 {
1302 pgmR3StateVerifyCrc32ForPage(pvPage, pCur, paLSPages, iPage, pszWhere);
1303 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1304 }
1305 }
1306}
1307
1308#endif /* PGMLIVESAVERAMPAGE_WITH_CRC32 */
1309
1310/**
1311 * Scan for RAM page modifications and reprotect them.
1312 *
1313 * @param pVM Pointer to the VM.
1314 * @param fFinalPass Whether this is the final pass or not.
1315 */
1316static void pgmR3ScanRamPages(PVM pVM, bool fFinalPass)
1317{
1318 /*
1319 * The RAM.
1320 */
1321 RTGCPHYS GCPhysCur = 0;
1322 PPGMRAMRANGE pCur;
1323 pgmLock(pVM);
1324 do
1325 {
1326 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1327 for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1328 {
1329 if ( pCur->GCPhysLast > GCPhysCur
1330 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1331 {
1332 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1333 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1334 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1335 GCPhysCur = 0;
1336 for (; iPage < cPages; iPage++)
1337 {
1338 /* Do yield first. */
1339 if ( !fFinalPass
1340#ifndef PGMLIVESAVERAMPAGE_WITH_CRC32
1341 && (iPage & 0x7ff) == 0x100
1342#endif
1343 && PDMR3CritSectYield(&pVM->pgm.s.CritSectX)
1344 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1345 {
1346 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1347 break; /* restart */
1348 }
1349
1350 /* Skip already ignored pages. */
1351 if (paLSPages[iPage].fIgnore)
1352 continue;
1353
1354 if (RT_LIKELY(PGM_PAGE_GET_TYPE(&pCur->aPages[iPage]) == PGMPAGETYPE_RAM))
1355 {
1356 /*
1357 * A RAM page.
1358 */
1359 switch (PGM_PAGE_GET_STATE(&pCur->aPages[iPage]))
1360 {
1361 case PGM_PAGE_STATE_ALLOCATED:
1362 /** @todo Optimize this: Don't always re-enable write
1363 * monitoring if the page is known to be very busy. */
1364 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1365 {
1366 AssertMsg(paLSPages[iPage].fWriteMonitored,
1367 ("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1368 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1369 Assert(pVM->pgm.s.cWrittenToPages > 0);
1370 pVM->pgm.s.cWrittenToPages--;
1371 }
1372 else
1373 {
1374 AssertMsg(!paLSPages[iPage].fWriteMonitored,
1375 ("%RGp %R[pgmpage]\n", pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT), &pCur->aPages[iPage]));
1376 pVM->pgm.s.LiveSave.Ram.cMonitoredPages++;
1377 }
1378
1379 if (!paLSPages[iPage].fDirty)
1380 {
1381 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1382 if (paLSPages[iPage].fZero)
1383 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1384 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1385 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1386 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1387 }
1388
1389 pgmPhysPageWriteMonitor(pVM, &pCur->aPages[iPage],
1390 pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT));
1391 paLSPages[iPage].fWriteMonitored = 1;
1392 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1393 paLSPages[iPage].fDirty = 1;
1394 paLSPages[iPage].fZero = 0;
1395 paLSPages[iPage].fShared = 0;
1396#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1397 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1398#endif
1399 break;
1400
1401 case PGM_PAGE_STATE_WRITE_MONITORED:
1402 Assert(paLSPages[iPage].fWriteMonitored);
1403 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) == 0)
1404 {
1405#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1406 if (paLSPages[iPage].fWriteMonitoredJustNow)
1407 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1408 else
1409 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "scan");
1410#endif
1411 paLSPages[iPage].fWriteMonitoredJustNow = 0;
1412 }
1413 else
1414 {
1415 paLSPages[iPage].fWriteMonitoredJustNow = 1;
1416#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1417 paLSPages[iPage].u32Crc = UINT32_MAX; /* invalid */
1418#endif
1419 if (!paLSPages[iPage].fDirty)
1420 {
1421 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1422 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1423 if (++paLSPages[iPage].cDirtied > PGMLIVSAVEPAGE_MAX_DIRTIED)
1424 paLSPages[iPage].cDirtied = PGMLIVSAVEPAGE_MAX_DIRTIED;
1425 }
1426 }
1427 break;
1428
1429 case PGM_PAGE_STATE_ZERO:
1430 case PGM_PAGE_STATE_BALLOONED:
1431 if (!paLSPages[iPage].fZero)
1432 {
1433 if (!paLSPages[iPage].fDirty)
1434 {
1435 paLSPages[iPage].fDirty = 1;
1436 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1437 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1438 }
1439 paLSPages[iPage].fZero = 1;
1440 paLSPages[iPage].fShared = 0;
1441#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1442 paLSPages[iPage].u32Crc = PGM_STATE_CRC32_ZERO_PAGE;
1443#endif
1444 }
1445 break;
1446
1447 case PGM_PAGE_STATE_SHARED:
1448 if (!paLSPages[iPage].fShared)
1449 {
1450 if (!paLSPages[iPage].fDirty)
1451 {
1452 paLSPages[iPage].fDirty = 1;
1453 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1454 if (paLSPages[iPage].fZero)
1455 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1456 pVM->pgm.s.LiveSave.Ram.cDirtyPages++;
1457 }
1458 paLSPages[iPage].fZero = 0;
1459 paLSPages[iPage].fShared = 1;
1460#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1461 pgmR3StateCalcCrc32ForRamPage(pVM, pCur, paLSPages, iPage);
1462#endif
1463 }
1464 break;
1465 }
1466 }
1467 else
1468 {
1469 /*
1470 * All other types => Ignore the page.
1471 */
1472 Assert(!paLSPages[iPage].fIgnore); /* skipped before switch */
1473 paLSPages[iPage].fIgnore = 1;
1474 if (paLSPages[iPage].fWriteMonitored)
1475 {
1476 /** @todo this doesn't hold water when we start monitoring MMIO2 and ROM shadow
1477 * pages! */
1478 if (RT_UNLIKELY(PGM_PAGE_GET_STATE(&pCur->aPages[iPage]) == PGM_PAGE_STATE_WRITE_MONITORED))
1479 {
1480 AssertMsgFailed(("%R[pgmpage]", &pCur->aPages[iPage])); /* shouldn't happen. */
1481 PGM_PAGE_SET_STATE(pVM, &pCur->aPages[iPage], PGM_PAGE_STATE_ALLOCATED);
1482 Assert(pVM->pgm.s.cMonitoredPages > 0);
1483 pVM->pgm.s.cMonitoredPages--;
1484 }
1485 if (PGM_PAGE_IS_WRITTEN_TO(&pCur->aPages[iPage]))
1486 {
1487 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, &pCur->aPages[iPage]);
1488 Assert(pVM->pgm.s.cWrittenToPages > 0);
1489 pVM->pgm.s.cWrittenToPages--;
1490 }
1491 pVM->pgm.s.LiveSave.Ram.cMonitoredPages--;
1492 }
1493
1494 /** @todo the counting doesn't quite work out here. fix later? */
1495 if (paLSPages[iPage].fDirty)
1496 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1497 else
1498 {
1499 pVM->pgm.s.LiveSave.Ram.cReadyPages--;
1500 if (paLSPages[iPage].fZero)
1501 pVM->pgm.s.LiveSave.Ram.cZeroPages--;
1502 }
1503 pVM->pgm.s.LiveSave.cIgnoredPages++;
1504 }
1505 } /* for each page in range */
1506
1507 if (GCPhysCur != 0)
1508 break; /* Yield + ramrange change */
1509 GCPhysCur = pCur->GCPhysLast;
1510 }
1511 } /* for each range */
1512 } while (pCur);
1513 pgmUnlock(pVM);
1514}
1515
1516
1517/**
1518 * Save quiescent RAM pages.
1519 *
1520 * @returns VBox status code.
1521 * @param pVM Pointer to the VM.
1522 * @param pSSM The SSM handle.
1523 * @param fLiveSave Whether it's a live save or not.
1524 * @param uPass The pass number.
1525 */
1526static int pgmR3SaveRamPages(PVM pVM, PSSMHANDLE pSSM, bool fLiveSave, uint32_t uPass)
1527{
1528 NOREF(fLiveSave);
1529
1530 /*
1531 * The RAM.
1532 */
1533 RTGCPHYS GCPhysLast = NIL_RTGCPHYS;
1534 RTGCPHYS GCPhysCur = 0;
1535 PPGMRAMRANGE pCur;
1536 bool fFTMDeltaSaveActive = FTMIsDeltaLoadSaveActive(pVM);
1537
1538 pgmLock(pVM);
1539 do
1540 {
1541 uint32_t const idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1542 for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1543 {
1544 if ( pCur->GCPhysLast > GCPhysCur
1545 && !PGM_RAM_RANGE_IS_AD_HOC(pCur))
1546 {
1547 PPGMLIVESAVERAMPAGE paLSPages = pCur->paLSPages;
1548 uint32_t cPages = pCur->cb >> PAGE_SHIFT;
1549 uint32_t iPage = GCPhysCur <= pCur->GCPhys ? 0 : (GCPhysCur - pCur->GCPhys) >> PAGE_SHIFT;
1550 GCPhysCur = 0;
1551 for (; iPage < cPages; iPage++)
1552 {
1553 /* Do yield first. */
1554 if ( uPass != SSM_PASS_FINAL
1555 && (iPage & 0x7ff) == 0x100
1556 && PDMR3CritSectYield(&pVM->pgm.s.CritSectX)
1557 && pVM->pgm.s.idRamRangesGen != idRamRangesGen)
1558 {
1559 GCPhysCur = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1560 break; /* restart */
1561 }
1562
1563 PPGMPAGE pCurPage = &pCur->aPages[iPage];
1564
1565 /*
1566 * Only save pages that haven't changed since last scan and are dirty.
1567 */
1568 if ( uPass != SSM_PASS_FINAL
1569 && paLSPages)
1570 {
1571 if (!paLSPages[iPage].fDirty)
1572 continue;
1573 if (paLSPages[iPage].fWriteMonitoredJustNow)
1574 continue;
1575 if (paLSPages[iPage].fIgnore)
1576 continue;
1577 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM) /* in case of recent remappings */
1578 continue;
1579 if ( PGM_PAGE_GET_STATE(pCurPage)
1580 != ( paLSPages[iPage].fZero
1581 ? PGM_PAGE_STATE_ZERO
1582 : paLSPages[iPage].fShared
1583 ? PGM_PAGE_STATE_SHARED
1584 : PGM_PAGE_STATE_WRITE_MONITORED))
1585 continue;
1586 if (PGM_PAGE_GET_WRITE_LOCKS(&pCur->aPages[iPage]) > 0)
1587 continue;
1588 }
1589 else
1590 {
1591 if ( paLSPages
1592 && !paLSPages[iPage].fDirty
1593 && !paLSPages[iPage].fIgnore)
1594 {
1595#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1596 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1597 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#1");
1598#endif
1599 continue;
1600 }
1601 if (PGM_PAGE_GET_TYPE(pCurPage) != PGMPAGETYPE_RAM)
1602 continue;
1603 }
1604
1605 /*
1606 * Do the saving outside the PGM critsect since SSM may block on I/O.
1607 */
1608 int rc;
1609 RTGCPHYS GCPhys = pCur->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
1610 bool fZero = PGM_PAGE_IS_ZERO(pCurPage);
1611 bool fBallooned = PGM_PAGE_IS_BALLOONED(pCurPage);
1612 bool fSkipped = false;
1613
1614 if (!fZero && !fBallooned)
1615 {
1616 /*
1617 * Copy the page and then save it outside the lock (since any
1618 * SSM call may block).
1619 */
1620 uint8_t abPage[PAGE_SIZE];
1621 PGMPAGEMAPLOCK PgMpLck;
1622 void const *pvPage;
1623 rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pCurPage, GCPhys, &pvPage, &PgMpLck);
1624 if (RT_SUCCESS(rc))
1625 {
1626 memcpy(abPage, pvPage, PAGE_SIZE);
1627#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1628 if (paLSPages)
1629 pgmR3StateVerifyCrc32ForPage(abPage, pCur, paLSPages, iPage, "save#3");
1630#endif
1631 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
1632 }
1633 pgmUnlock(pVM);
1634 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc GCPhys=%RGp\n", rc, GCPhys), rc);
1635
1636 /* Try save some memory when restoring. */
1637 if (!ASMMemIsZeroPage(pvPage))
1638 {
1639 if (fFTMDeltaSaveActive)
1640 {
1641 if ( PGM_PAGE_IS_WRITTEN_TO(pCurPage)
1642 || PGM_PAGE_IS_FT_DIRTY(pCurPage))
1643 {
1644 if (GCPhys == GCPhysLast + PAGE_SIZE)
1645 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1646 else
1647 {
1648 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1649 SSMR3PutGCPhys(pSSM, GCPhys);
1650 }
1651 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1652 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pCurPage);
1653 PGM_PAGE_CLEAR_FT_DIRTY(pCurPage);
1654 }
1655 /* else nothing changed, so skip it. */
1656 else
1657 fSkipped = true;
1658 }
1659 else
1660 {
1661 if (GCPhys == GCPhysLast + PAGE_SIZE)
1662 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW);
1663 else
1664 {
1665 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_RAW | PGM_STATE_REC_FLAG_ADDR);
1666 SSMR3PutGCPhys(pSSM, GCPhys);
1667 }
1668 rc = SSMR3PutMem(pSSM, abPage, PAGE_SIZE);
1669 }
1670 }
1671 else
1672 {
1673 if (GCPhys == GCPhysLast + PAGE_SIZE)
1674 rc = SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO);
1675 else
1676 {
1677 SSMR3PutU8(pSSM, PGM_STATE_REC_RAM_ZERO | PGM_STATE_REC_FLAG_ADDR);
1678 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1679 }
1680 }
1681 }
1682 else
1683 {
1684 /*
1685 * Dirty zero or ballooned page.
1686 */
1687#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1688 if (paLSPages)
1689 pgmR3StateVerifyCrc32ForRamPage(pVM, pCur, paLSPages, iPage, "save#2");
1690#endif
1691 pgmUnlock(pVM);
1692
1693 uint8_t u8RecType = fBallooned ? PGM_STATE_REC_RAM_BALLOONED : PGM_STATE_REC_RAM_ZERO;
1694 if (GCPhys == GCPhysLast + PAGE_SIZE)
1695 rc = SSMR3PutU8(pSSM, u8RecType);
1696 else
1697 {
1698 SSMR3PutU8(pSSM, u8RecType | PGM_STATE_REC_FLAG_ADDR);
1699 rc = SSMR3PutGCPhys(pSSM, GCPhys);
1700 }
1701 }
1702 if (RT_FAILURE(rc))
1703 return rc;
1704
1705 pgmLock(pVM);
1706 if (!fSkipped)
1707 GCPhysLast = GCPhys;
1708 if (paLSPages)
1709 {
1710 paLSPages[iPage].fDirty = 0;
1711 pVM->pgm.s.LiveSave.Ram.cReadyPages++;
1712 if (fZero)
1713 pVM->pgm.s.LiveSave.Ram.cZeroPages++;
1714 pVM->pgm.s.LiveSave.Ram.cDirtyPages--;
1715 pVM->pgm.s.LiveSave.cSavedPages++;
1716 }
1717 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1718 {
1719 GCPhysCur = GCPhys | PAGE_OFFSET_MASK;
1720 break; /* restart */
1721 }
1722
1723 } /* for each page in range */
1724
1725 if (GCPhysCur != 0)
1726 break; /* Yield + ramrange change */
1727 GCPhysCur = pCur->GCPhysLast;
1728 }
1729 } /* for each range */
1730 } while (pCur);
1731
1732 pgmUnlock(pVM);
1733
1734 return VINF_SUCCESS;
1735}
1736
1737
1738/**
1739 * Cleans up RAM pages after a live save.
1740 *
1741 * @param pVM Pointer to the VM.
1742 */
1743static void pgmR3DoneRamPages(PVM pVM)
1744{
1745 /*
1746 * Free the tracking arrays and disable write monitoring.
1747 *
1748 * Play nice with the PGM lock in case we're called while the VM is still
1749 * running. This means we have to delay the freeing since we wish to use
1750 * paLSPages as an indicator of which RAM ranges which we need to scan for
1751 * write monitored pages.
1752 */
1753 void *pvToFree = NULL;
1754 PPGMRAMRANGE pCur;
1755 uint32_t cMonitoredPages = 0;
1756 pgmLock(pVM);
1757 do
1758 {
1759 for (pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
1760 {
1761 if (pCur->paLSPages)
1762 {
1763 if (pvToFree)
1764 {
1765 uint32_t idRamRangesGen = pVM->pgm.s.idRamRangesGen;
1766 pgmUnlock(pVM);
1767 MMR3HeapFree(pvToFree);
1768 pvToFree = NULL;
1769 pgmLock(pVM);
1770 if (idRamRangesGen != pVM->pgm.s.idRamRangesGen)
1771 break; /* start over again. */
1772 }
1773
1774 pvToFree = pCur->paLSPages;
1775 pCur->paLSPages = NULL;
1776
1777 uint32_t iPage = pCur->cb >> PAGE_SHIFT;
1778 while (iPage--)
1779 {
1780 PPGMPAGE pPage = &pCur->aPages[iPage];
1781 PGM_PAGE_CLEAR_WRITTEN_TO(pVM, pPage);
1782 if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED)
1783 {
1784 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ALLOCATED);
1785 cMonitoredPages++;
1786 }
1787 }
1788 }
1789 }
1790 } while (pCur);
1791
1792 Assert(pVM->pgm.s.cMonitoredPages >= cMonitoredPages);
1793 if (pVM->pgm.s.cMonitoredPages < cMonitoredPages)
1794 pVM->pgm.s.cMonitoredPages = 0;
1795 else
1796 pVM->pgm.s.cMonitoredPages -= cMonitoredPages;
1797
1798 pgmUnlock(pVM);
1799
1800 MMR3HeapFree(pvToFree);
1801 pvToFree = NULL;
1802}
1803
1804
1805/**
1806 * Execute a live save pass.
1807 *
1808 * @returns VBox status code.
1809 *
1810 * @param pVM Pointer to the VM.
1811 * @param pSSM The SSM handle.
1812 */
1813static DECLCALLBACK(int) pgmR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1814{
1815 int rc;
1816
1817 /*
1818 * Save the MMIO2 and ROM range IDs in pass 0.
1819 */
1820 if (uPass == 0)
1821 {
1822 rc = pgmR3SaveRamConfig(pVM, pSSM);
1823 if (RT_FAILURE(rc))
1824 return rc;
1825 rc = pgmR3SaveRomRanges(pVM, pSSM);
1826 if (RT_FAILURE(rc))
1827 return rc;
1828 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
1829 if (RT_FAILURE(rc))
1830 return rc;
1831 }
1832 /*
1833 * Reset the page-per-second estimate to avoid inflation by the initial
1834 * load of zero pages. pgmR3LiveVote ASSUMES this is done at pass 7.
1835 */
1836 else if (uPass == 7)
1837 {
1838 pVM->pgm.s.LiveSave.cSavedPages = 0;
1839 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
1840 }
1841
1842 /*
1843 * Do the scanning.
1844 */
1845 pgmR3ScanRomPages(pVM);
1846 pgmR3ScanMmio2Pages(pVM, uPass);
1847 pgmR3ScanRamPages(pVM, false /*fFinalPass*/);
1848 pgmR3PoolClearAll(pVM, true /*fFlushRemTlb*/); /** @todo this could perhaps be optimized a bit. */
1849
1850 /*
1851 * Save the pages.
1852 */
1853 if (uPass == 0)
1854 rc = pgmR3SaveRomVirginPages( pVM, pSSM, true /*fLiveSave*/);
1855 else
1856 rc = VINF_SUCCESS;
1857 if (RT_SUCCESS(rc))
1858 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, true /*fLiveSave*/, false /*fFinalPass*/);
1859 if (RT_SUCCESS(rc))
1860 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, uPass);
1861 if (RT_SUCCESS(rc))
1862 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, uPass);
1863 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes care of it.) */
1864
1865 return rc;
1866}
1867
1868
1869/**
1870 * Votes on whether the live save phase is done or not.
1871 *
1872 * @returns VBox status code.
1873 *
1874 * @param pVM Pointer to the VM.
1875 * @param pSSM The SSM handle.
1876 * @param uPass The data pass.
1877 */
1878static DECLCALLBACK(int) pgmR3LiveVote(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1879{
1880 /*
1881 * Update and calculate parameters used in the decision making.
1882 */
1883 const uint32_t cHistoryEntries = RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory);
1884
1885 /* update history. */
1886 pgmLock(pVM);
1887 uint32_t const cWrittenToPages = pVM->pgm.s.cWrittenToPages;
1888 pgmUnlock(pVM);
1889 uint32_t const cDirtyNow = pVM->pgm.s.LiveSave.Rom.cDirtyPages
1890 + pVM->pgm.s.LiveSave.Mmio2.cDirtyPages
1891 + pVM->pgm.s.LiveSave.Ram.cDirtyPages
1892 + cWrittenToPages;
1893 uint32_t i = pVM->pgm.s.LiveSave.iDirtyPagesHistory;
1894 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = cDirtyNow;
1895 pVM->pgm.s.LiveSave.iDirtyPagesHistory = (i + 1) % cHistoryEntries;
1896
1897 /* calc shortterm average (4 passes). */
1898 AssertCompile(RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory) > 4);
1899 uint64_t cTotal = pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1900 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 1) % cHistoryEntries];
1901 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 2) % cHistoryEntries];
1902 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[(i + cHistoryEntries - 3) % cHistoryEntries];
1903 uint32_t const cDirtyPagesShort = cTotal / 4;
1904 pVM->pgm.s.LiveSave.cDirtyPagesShort = cDirtyPagesShort;
1905
1906 /* calc longterm average. */
1907 cTotal = 0;
1908 if (uPass < cHistoryEntries)
1909 for (i = 0; i < cHistoryEntries && i <= uPass; i++)
1910 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1911 else
1912 for (i = 0; i < cHistoryEntries; i++)
1913 cTotal += pVM->pgm.s.LiveSave.acDirtyPagesHistory[i];
1914 uint32_t const cDirtyPagesLong = cTotal / cHistoryEntries;
1915 pVM->pgm.s.LiveSave.cDirtyPagesLong = cDirtyPagesLong;
1916
1917 /* estimate the speed */
1918 uint64_t cNsElapsed = RTTimeNanoTS() - pVM->pgm.s.LiveSave.uSaveStartNS;
1919 uint32_t cPagesPerSecond = (uint32_t)( pVM->pgm.s.LiveSave.cSavedPages
1920 / ((long double)cNsElapsed / 1000000000.0) );
1921 pVM->pgm.s.LiveSave.cPagesPerSecond = cPagesPerSecond;
1922
1923 /*
1924 * Try make a decision.
1925 */
1926 if ( cDirtyPagesShort <= cDirtyPagesLong
1927 && ( cDirtyNow <= cDirtyPagesShort
1928 || cDirtyNow - cDirtyPagesShort < RT_MIN(cDirtyPagesShort / 8, 16)
1929 )
1930 )
1931 {
1932 if (uPass > 10)
1933 {
1934 uint32_t cMsLeftShort = (uint32_t)(cDirtyPagesShort / (long double)cPagesPerSecond * 1000.0);
1935 uint32_t cMsLeftLong = (uint32_t)(cDirtyPagesLong / (long double)cPagesPerSecond * 1000.0);
1936 uint32_t cMsMaxDowntime = SSMR3HandleMaxDowntime(pSSM);
1937 if (cMsMaxDowntime < 32)
1938 cMsMaxDowntime = 32;
1939 if ( ( cMsLeftLong <= cMsMaxDowntime
1940 && cMsLeftShort < cMsMaxDowntime)
1941 || cMsLeftShort < cMsMaxDowntime / 2
1942 )
1943 {
1944 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u|%ums cDirtyPagesLong=%u|%ums cMsMaxDowntime=%u\n",
1945 uPass, cDirtyPagesShort, cMsLeftShort, cDirtyPagesLong, cMsLeftLong, cMsMaxDowntime));
1946 return VINF_SUCCESS;
1947 }
1948 }
1949 else
1950 {
1951 if ( ( cDirtyPagesShort <= 128
1952 && cDirtyPagesLong <= 1024)
1953 || cDirtyPagesLong <= 256
1954 )
1955 {
1956 Log(("pgmR3LiveVote: VINF_SUCCESS - pass=%d cDirtyPagesShort=%u cDirtyPagesLong=%u\n", uPass, cDirtyPagesShort, cDirtyPagesLong));
1957 return VINF_SUCCESS;
1958 }
1959 }
1960 }
1961
1962 /*
1963 * Come up with a completion percentage. Currently this is a simple
1964 * dirty page (long term) vs. total pages ratio + some pass trickery.
1965 */
1966 unsigned uPctDirty = (unsigned)( (long double)cDirtyPagesLong
1967 / (pVM->pgm.s.cAllPages - pVM->pgm.s.LiveSave.cIgnoredPages - pVM->pgm.s.cZeroPages) );
1968 if (uPctDirty <= 100)
1969 SSMR3HandleReportLivePercent(pSSM, RT_MIN(100 - uPctDirty, uPass * 2));
1970 else
1971 AssertMsgFailed(("uPctDirty=%u cDirtyPagesLong=%#x cAllPages=%#x cIgnoredPages=%#x cZeroPages=%#x\n",
1972 uPctDirty, cDirtyPagesLong, pVM->pgm.s.cAllPages, pVM->pgm.s.LiveSave.cIgnoredPages, pVM->pgm.s.cZeroPages));
1973
1974 return VINF_SSM_VOTE_FOR_ANOTHER_PASS;
1975}
1976
1977
1978/**
1979 * Prepare for a live save operation.
1980 *
1981 * This will attempt to allocate and initialize the tracking structures. It
1982 * will also prepare for write monitoring of pages and initialize PGM::LiveSave.
1983 * pgmR3SaveDone will do the cleanups.
1984 *
1985 * @returns VBox status code.
1986 *
1987 * @param pVM Pointer to the VM.
1988 * @param pSSM The SSM handle.
1989 */
1990static DECLCALLBACK(int) pgmR3LivePrep(PVM pVM, PSSMHANDLE pSSM)
1991{
1992 /*
1993 * Indicate that we will be using the write monitoring.
1994 */
1995 pgmLock(pVM);
1996 /** @todo find a way of mediating this when more users are added. */
1997 if (pVM->pgm.s.fPhysWriteMonitoringEngaged)
1998 {
1999 pgmUnlock(pVM);
2000 AssertLogRelFailedReturn(VERR_PGM_WRITE_MONITOR_ENGAGED);
2001 }
2002 pVM->pgm.s.fPhysWriteMonitoringEngaged = true;
2003 pgmUnlock(pVM);
2004
2005 /*
2006 * Initialize the statistics.
2007 */
2008 pVM->pgm.s.LiveSave.Rom.cReadyPages = 0;
2009 pVM->pgm.s.LiveSave.Rom.cDirtyPages = 0;
2010 pVM->pgm.s.LiveSave.Mmio2.cReadyPages = 0;
2011 pVM->pgm.s.LiveSave.Mmio2.cDirtyPages = 0;
2012 pVM->pgm.s.LiveSave.Ram.cReadyPages = 0;
2013 pVM->pgm.s.LiveSave.Ram.cDirtyPages = 0;
2014 pVM->pgm.s.LiveSave.cIgnoredPages = 0;
2015 pVM->pgm.s.LiveSave.fActive = true;
2016 for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.LiveSave.acDirtyPagesHistory); i++)
2017 pVM->pgm.s.LiveSave.acDirtyPagesHistory[i] = UINT32_MAX / 2;
2018 pVM->pgm.s.LiveSave.iDirtyPagesHistory = 0;
2019 pVM->pgm.s.LiveSave.cSavedPages = 0;
2020 pVM->pgm.s.LiveSave.uSaveStartNS = RTTimeNanoTS();
2021 pVM->pgm.s.LiveSave.cPagesPerSecond = 8192;
2022
2023 /*
2024 * Per page type.
2025 */
2026 int rc = pgmR3PrepRomPages(pVM);
2027 if (RT_SUCCESS(rc))
2028 rc = pgmR3PrepMmio2Pages(pVM);
2029 if (RT_SUCCESS(rc))
2030 rc = pgmR3PrepRamPages(pVM);
2031
2032 NOREF(pSSM);
2033 return rc;
2034}
2035
2036
2037/**
2038 * Execute state save operation.
2039 *
2040 * @returns VBox status code.
2041 * @param pVM Pointer to the VM.
2042 * @param pSSM SSM operation handle.
2043 */
2044static DECLCALLBACK(int) pgmR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2045{
2046 int rc = VINF_SUCCESS;
2047 PPGM pPGM = &pVM->pgm.s;
2048
2049 /*
2050 * Lock PGM and set the no-more-writes indicator.
2051 */
2052 pgmLock(pVM);
2053 pVM->pgm.s.fNoMorePhysWrites = true;
2054
2055 /*
2056 * Save basic data (required / unaffected by relocation).
2057 */
2058 bool const fMappingsFixed = pVM->pgm.s.fMappingsFixed;
2059 pVM->pgm.s.fMappingsFixed |= pVM->pgm.s.fMappingsFixedRestored;
2060 SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2061 pVM->pgm.s.fMappingsFixed = fMappingsFixed;
2062
2063 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2064 rc = SSMR3PutStruct(pSSM, &pVM->aCpus[idCpu].pgm.s, &s_aPGMCpuFields[0]);
2065
2066 /*
2067 * Save the (remainder of the) memory.
2068 */
2069 if (RT_SUCCESS(rc))
2070 {
2071 if (pVM->pgm.s.LiveSave.fActive)
2072 {
2073 pgmR3ScanRomPages(pVM);
2074 pgmR3ScanMmio2Pages(pVM, SSM_PASS_FINAL);
2075 pgmR3ScanRamPages(pVM, true /*fFinalPass*/);
2076
2077 rc = pgmR3SaveShadowedRomPages( pVM, pSSM, true /*fLiveSave*/, true /*fFinalPass*/);
2078 if (RT_SUCCESS(rc))
2079 rc = pgmR3SaveMmio2Pages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2080 if (RT_SUCCESS(rc))
2081 rc = pgmR3SaveRamPages( pVM, pSSM, true /*fLiveSave*/, SSM_PASS_FINAL);
2082 }
2083 else
2084 {
2085 rc = pgmR3SaveRamConfig(pVM, pSSM);
2086 if (RT_SUCCESS(rc))
2087 rc = pgmR3SaveRomRanges(pVM, pSSM);
2088 if (RT_SUCCESS(rc))
2089 rc = pgmR3SaveMmio2Ranges(pVM, pSSM);
2090 if (RT_SUCCESS(rc))
2091 rc = pgmR3SaveRomVirginPages( pVM, pSSM, false /*fLiveSave*/);
2092 if (RT_SUCCESS(rc))
2093 rc = pgmR3SaveShadowedRomPages(pVM, pSSM, false /*fLiveSave*/, true /*fFinalPass*/);
2094 if (RT_SUCCESS(rc))
2095 rc = pgmR3SaveMmio2Pages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2096 if (RT_SUCCESS(rc))
2097 rc = pgmR3SaveRamPages( pVM, pSSM, false /*fLiveSave*/, SSM_PASS_FINAL);
2098 }
2099 SSMR3PutU8(pSSM, PGM_STATE_REC_END); /* (Ignore the rc, SSM takes of it.) */
2100 }
2101
2102 pgmUnlock(pVM);
2103 return rc;
2104}
2105
2106
2107/**
2108 * Cleans up after an save state operation.
2109 *
2110 * @returns VBox status code.
2111 * @param pVM Pointer to the VM.
2112 * @param pSSM SSM operation handle.
2113 */
2114static DECLCALLBACK(int) pgmR3SaveDone(PVM pVM, PSSMHANDLE pSSM)
2115{
2116 /*
2117 * Do per page type cleanups first.
2118 */
2119 if (pVM->pgm.s.LiveSave.fActive)
2120 {
2121 pgmR3DoneRomPages(pVM);
2122 pgmR3DoneMmio2Pages(pVM);
2123 pgmR3DoneRamPages(pVM);
2124 }
2125
2126 /*
2127 * Clear the live save indicator and disengage write monitoring.
2128 */
2129 pgmLock(pVM);
2130 pVM->pgm.s.LiveSave.fActive = false;
2131 /** @todo this is blindly assuming that we're the only user of write
2132 * monitoring. Fix this when more users are added. */
2133 pVM->pgm.s.fPhysWriteMonitoringEngaged = false;
2134 pgmUnlock(pVM);
2135
2136 NOREF(pSSM);
2137 return VINF_SUCCESS;
2138}
2139
2140
2141/**
2142 * Prepare state load operation.
2143 *
2144 * @returns VBox status code.
2145 * @param pVM Pointer to the VM.
2146 * @param pSSM SSM operation handle.
2147 */
2148static DECLCALLBACK(int) pgmR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2149{
2150 /*
2151 * Call the reset function to make sure all the memory is cleared.
2152 */
2153 PGMR3Reset(pVM);
2154 pVM->pgm.s.LiveSave.fActive = false;
2155 NOREF(pSSM);
2156 return VINF_SUCCESS;
2157}
2158
2159
2160/**
2161 * Load an ignored page.
2162 *
2163 * @returns VBox status code.
2164 * @param pSSM The saved state handle.
2165 */
2166static int pgmR3LoadPageToDevNullOld(PSSMHANDLE pSSM)
2167{
2168 uint8_t abPage[PAGE_SIZE];
2169 return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2170}
2171
2172
2173/**
2174 * Loads a page without any bits in the saved state, i.e. making sure it's
2175 * really zero.
2176 *
2177 * @returns VBox status code.
2178 * @param pVM Pointer to the VM.
2179 * @param uType The page type or PGMPAGETYPE_INVALID (old saved
2180 * state).
2181 * @param pPage The guest page tracking structure.
2182 * @param GCPhys The page address.
2183 * @param pRam The ram range (logging).
2184 */
2185static int pgmR3LoadPageZeroOld(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2186{
2187 if ( PGM_PAGE_GET_TYPE(pPage) != uType
2188 && uType != PGMPAGETYPE_INVALID)
2189 return VERR_SSM_UNEXPECTED_DATA;
2190
2191 /* I think this should be sufficient. */
2192 if ( !PGM_PAGE_IS_ZERO(pPage)
2193 && !PGM_PAGE_IS_BALLOONED(pPage))
2194 return VERR_SSM_UNEXPECTED_DATA;
2195
2196 NOREF(pVM);
2197 NOREF(GCPhys);
2198 NOREF(pRam);
2199 return VINF_SUCCESS;
2200}
2201
2202
2203/**
2204 * Loads a page from the saved state.
2205 *
2206 * @returns VBox status code.
2207 * @param pVM Pointer to the VM.
2208 * @param pSSM The SSM handle.
2209 * @param uType The page type or PGMPAGETYEP_INVALID (old saved
2210 * state).
2211 * @param pPage The guest page tracking structure.
2212 * @param GCPhys The page address.
2213 * @param pRam The ram range (logging).
2214 */
2215static int pgmR3LoadPageBitsOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2216{
2217 /*
2218 * Match up the type, dealing with MMIO2 aliases (dropped).
2219 */
2220 AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2221 || uType == PGMPAGETYPE_INVALID
2222 /* kudge for the expanded PXE bios (r67885) - @bugref{5687}: */
2223 || ( uType == PGMPAGETYPE_RAM
2224 && GCPhys >= 0xed000
2225 && GCPhys <= 0xeffff
2226 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM)
2227 ,
2228 ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2229 VERR_SSM_UNEXPECTED_DATA);
2230
2231 /*
2232 * Load the page.
2233 */
2234 PGMPAGEMAPLOCK PgMpLck;
2235 void *pvPage;
2236 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage, &PgMpLck);
2237 if (RT_SUCCESS(rc))
2238 {
2239 rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2240 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2241 }
2242
2243 return rc;
2244}
2245
2246
2247/**
2248 * Loads a page (counter part to pgmR3SavePage).
2249 *
2250 * @returns VBox status code, fully bitched errors.
2251 * @param pVM Pointer to the VM.
2252 * @param pSSM The SSM handle.
2253 * @param uType The page type.
2254 * @param pPage The page.
2255 * @param GCPhys The page address.
2256 * @param pRam The RAM range (for error messages).
2257 */
2258static int pgmR3LoadPageOld(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2259{
2260 uint8_t uState;
2261 int rc = SSMR3GetU8(pSSM, &uState);
2262 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2263 if (uState == 0 /* zero */)
2264 rc = pgmR3LoadPageZeroOld(pVM, uType, pPage, GCPhys, pRam);
2265 else if (uState == 1)
2266 rc = pgmR3LoadPageBitsOld(pVM, pSSM, uType, pPage, GCPhys, pRam);
2267 else
2268 rc = VERR_PGM_INVALID_SAVED_PAGE_STATE;
2269 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2270 pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2271 rc);
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/**
2277 * Loads a shadowed ROM page.
2278 *
2279 * @returns VBox status code, errors are fully bitched.
2280 * @param pVM Pointer to the VM.
2281 * @param pSSM The saved state handle.
2282 * @param pPage The page.
2283 * @param GCPhys The page address.
2284 * @param pRam The RAM range (for error messages).
2285 */
2286static int pgmR3LoadShadowedRomPageOld(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2287{
2288 /*
2289 * Load and set the protection first, then load the two pages, the first
2290 * one is the active the other is the passive.
2291 */
2292 PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2293 AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2294
2295 uint8_t uProt;
2296 int rc = SSMR3GetU8(pSSM, &uProt);
2297 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2298 PGMROMPROT enmProt = (PGMROMPROT)uProt;
2299 AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2300 && enmProt < PGMROMPROT_END,
2301 ("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2302 VERR_SSM_UNEXPECTED_DATA);
2303
2304 if (pRomPage->enmProt != enmProt)
2305 {
2306 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2307 AssertLogRelRCReturn(rc, rc);
2308 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2309 }
2310
2311 PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2312 PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2313 uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2314 uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2315
2316 /** @todo this isn't entirely correct as long as pgmPhysGCPhys2CCPtrInternal is
2317 * used down the line (will the 2nd page will be written to the first
2318 * one because of a false TLB hit since the TLB is using GCPhys and
2319 * doesn't check the HCPhys of the desired page). */
2320 rc = pgmR3LoadPageOld(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2321 if (RT_SUCCESS(rc))
2322 {
2323 *pPageActive = *pPage;
2324 rc = pgmR3LoadPageOld(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2325 }
2326 return rc;
2327}
2328
2329/**
2330 * Ram range flags and bits for older versions of the saved state.
2331 *
2332 * @returns VBox status code.
2333 *
2334 * @param pVM Pointer to the VM.
2335 * @param pSSM The SSM handle.
2336 * @param uVersion The saved state version.
2337 */
2338static int pgmR3LoadMemoryOld(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2339{
2340 PPGM pPGM = &pVM->pgm.s;
2341
2342 /*
2343 * Ram range flags and bits.
2344 */
2345 uint32_t i = 0;
2346 for (PPGMRAMRANGE pRam = pPGM->pRamRangesXR3; ; pRam = pRam->pNextR3, i++)
2347 {
2348 /* Check the sequence number / separator. */
2349 uint32_t u32Sep;
2350 int rc = SSMR3GetU32(pSSM, &u32Sep);
2351 if (RT_FAILURE(rc))
2352 return rc;
2353 if (u32Sep == ~0U)
2354 break;
2355 if (u32Sep != i)
2356 {
2357 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2358 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2359 }
2360 AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2361
2362 /* Get the range details. */
2363 RTGCPHYS GCPhys;
2364 SSMR3GetGCPhys(pSSM, &GCPhys);
2365 RTGCPHYS GCPhysLast;
2366 SSMR3GetGCPhys(pSSM, &GCPhysLast);
2367 RTGCPHYS cb;
2368 SSMR3GetGCPhys(pSSM, &cb);
2369 uint8_t fHaveBits;
2370 rc = SSMR3GetU8(pSSM, &fHaveBits);
2371 if (RT_FAILURE(rc))
2372 return rc;
2373 if (fHaveBits & ~1)
2374 {
2375 AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2376 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2377 }
2378 size_t cchDesc = 0;
2379 char szDesc[256];
2380 szDesc[0] = '\0';
2381 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2382 {
2383 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2384 if (RT_FAILURE(rc))
2385 return rc;
2386 /* Since we've modified the description strings in r45878, only compare
2387 them if the saved state is more recent. */
2388 if (uVersion != PGM_SAVED_STATE_VERSION_RR_DESC)
2389 cchDesc = strlen(szDesc);
2390 }
2391
2392 /*
2393 * Match it up with the current range.
2394 *
2395 * Note there is a hack for dealing with the high BIOS mapping
2396 * in the old saved state format, this means we might not have
2397 * a 1:1 match on success.
2398 */
2399 if ( ( GCPhys != pRam->GCPhys
2400 || GCPhysLast != pRam->GCPhysLast
2401 || cb != pRam->cb
2402 || ( cchDesc
2403 && strcmp(szDesc, pRam->pszDesc)) )
2404 /* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2405 && ( uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2406 || GCPhys != UINT32_C(0xfff80000)
2407 || GCPhysLast != UINT32_C(0xffffffff)
2408 || pRam->GCPhysLast != GCPhysLast
2409 || pRam->GCPhys < GCPhys
2410 || !fHaveBits)
2411 )
2412 {
2413 LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2414 "State : %RGp-%RGp %RGp bytes %s %s\n",
2415 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2416 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2417 /*
2418 * If we're loading a state for debugging purpose, don't make a fuss if
2419 * the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2420 */
2421 if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2422 || GCPhys < 8 * _1M)
2423 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2424 N_("RAM range mismatch; saved={%RGp-%RGp %RGp bytes %s %s} config={%RGp-%RGp %RGp bytes %s %s}"),
2425 GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc,
2426 pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc);
2427
2428 AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2429 continue;
2430 }
2431
2432 uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2433 if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2434 {
2435 /*
2436 * Load the pages one by one.
2437 */
2438 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2439 {
2440 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2441 PPGMPAGE pPage = &pRam->aPages[iPage];
2442 uint8_t uType;
2443 rc = SSMR3GetU8(pSSM, &uType);
2444 AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2445 if (uType == PGMPAGETYPE_ROM_SHADOW)
2446 rc = pgmR3LoadShadowedRomPageOld(pVM, pSSM, pPage, GCPhysPage, pRam);
2447 else
2448 rc = pgmR3LoadPageOld(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2449 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2450 }
2451 }
2452 else
2453 {
2454 /*
2455 * Old format.
2456 */
2457
2458 /* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2459 The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2460 uint32_t fFlags = 0;
2461 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2462 {
2463 uint16_t u16Flags;
2464 rc = SSMR3GetU16(pSSM, &u16Flags);
2465 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2466 fFlags |= u16Flags;
2467 }
2468
2469 /* Load the bits */
2470 if ( !fHaveBits
2471 && GCPhysLast < UINT32_C(0xe0000000))
2472 {
2473 /*
2474 * Dynamic chunks.
2475 */
2476 const uint32_t cPagesInChunk = (1*1024*1024) >> PAGE_SHIFT;
2477 AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2478 ("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2479 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2480
2481 for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2482 {
2483 uint8_t fPresent;
2484 rc = SSMR3GetU8(pSSM, &fPresent);
2485 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2486 AssertLogRelMsgReturn(fPresent == (uint8_t)true || fPresent == (uint8_t)false,
2487 ("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2488 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2489
2490 for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2491 {
2492 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2493 PPGMPAGE pPage = &pRam->aPages[iPage];
2494 if (fPresent)
2495 {
2496 if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2497 rc = pgmR3LoadPageToDevNullOld(pSSM);
2498 else
2499 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2500 }
2501 else
2502 rc = pgmR3LoadPageZeroOld(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2503 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2504 }
2505 }
2506 }
2507 else if (pRam->pvR3)
2508 {
2509 /*
2510 * MMIO2.
2511 */
2512 AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/,
2513 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2514 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2515 AssertLogRelMsgReturn(pRam->pvR3,
2516 ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2517 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2518
2519 rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2520 AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2521 }
2522 else if (GCPhysLast < UINT32_C(0xfff80000))
2523 {
2524 /*
2525 * PCI MMIO, no pages saved.
2526 */
2527 }
2528 else
2529 {
2530 /*
2531 * Load the 0xfff80000..0xffffffff BIOS range.
2532 * It starts with X reserved pages that we have to skip over since
2533 * the RAMRANGE create by the new code won't include those.
2534 */
2535 AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /*MM_RAM_FLAGS_MMIO2*/)
2536 && (fFlags & RT_BIT(0) /*MM_RAM_FLAGS_RESERVED*/),
2537 ("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2538 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2539 AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2540 ("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2541 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2542
2543 /* Skip wasted reserved pages before the ROM. */
2544 while (GCPhys < pRam->GCPhys)
2545 {
2546 rc = pgmR3LoadPageToDevNullOld(pSSM);
2547 GCPhys += PAGE_SIZE;
2548 }
2549
2550 /* Load the bios pages. */
2551 cPages = pRam->cb >> PAGE_SHIFT;
2552 for (uint32_t iPage = 0; iPage < cPages; iPage++)
2553 {
2554 RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2555 PPGMPAGE pPage = &pRam->aPages[iPage];
2556
2557 AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2558 ("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2559 VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2560 rc = pgmR3LoadPageBitsOld(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2561 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2562 }
2563 }
2564 }
2565 }
2566
2567 return VINF_SUCCESS;
2568}
2569
2570
2571/**
2572 * Worker for pgmR3Load and pgmR3LoadLocked.
2573 *
2574 * @returns VBox status code.
2575 *
2576 * @param pVM Pointer to the VM.
2577 * @param pSSM The SSM handle.
2578 * @param uVersion The PGM saved state unit version.
2579 * @param uPass The pass number.
2580 *
2581 * @todo This needs splitting up if more record types or code twists are
2582 * added...
2583 */
2584static int pgmR3LoadMemory(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2585{
2586 NOREF(uPass);
2587
2588 /*
2589 * Process page records until we hit the terminator.
2590 */
2591 RTGCPHYS GCPhys = NIL_RTGCPHYS;
2592 PPGMRAMRANGE pRamHint = NULL;
2593 uint8_t id = UINT8_MAX;
2594 uint32_t iPage = UINT32_MAX - 10;
2595 PPGMROMRANGE pRom = NULL;
2596 PPGMMMIO2RANGE pMmio2 = NULL;
2597
2598 /*
2599 * We batch up pages that should be freed instead of calling GMM for
2600 * each and every one of them. Note that we'll lose the pages in most
2601 * failure paths - this should probably be addressed one day.
2602 */
2603 uint32_t cPendingPages = 0;
2604 PGMMFREEPAGESREQ pReq;
2605 int rc = GMMR3FreePagesPrepare(pVM, &pReq, 128 /* batch size */, GMMACCOUNT_BASE);
2606 AssertLogRelRCReturn(rc, rc);
2607
2608 for (;;)
2609 {
2610 /*
2611 * Get the record type and flags.
2612 */
2613 uint8_t u8;
2614 rc = SSMR3GetU8(pSSM, &u8);
2615 if (RT_FAILURE(rc))
2616 return rc;
2617 if (u8 == PGM_STATE_REC_END)
2618 {
2619 /*
2620 * Finish off any pages pending freeing.
2621 */
2622 if (cPendingPages)
2623 {
2624 Log(("pgmR3LoadMemory: GMMR3FreePagesPerform pVM=%p cPendingPages=%u\n", pVM, cPendingPages));
2625 rc = GMMR3FreePagesPerform(pVM, pReq, cPendingPages);
2626 AssertLogRelRCReturn(rc, rc);
2627 }
2628 GMMR3FreePagesCleanup(pReq);
2629 return VINF_SUCCESS;
2630 }
2631 AssertLogRelMsgReturn((u8 & ~PGM_STATE_REC_FLAG_ADDR) <= PGM_STATE_REC_LAST, ("%#x\n", u8), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2632 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2633 {
2634 /*
2635 * RAM page.
2636 */
2637 case PGM_STATE_REC_RAM_ZERO:
2638 case PGM_STATE_REC_RAM_RAW:
2639 case PGM_STATE_REC_RAM_BALLOONED:
2640 {
2641 /*
2642 * Get the address and resolve it into a page descriptor.
2643 */
2644 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2645 GCPhys += PAGE_SIZE;
2646 else
2647 {
2648 rc = SSMR3GetGCPhys(pSSM, &GCPhys);
2649 if (RT_FAILURE(rc))
2650 return rc;
2651 }
2652 AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK), ("%RGp\n", GCPhys), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2653
2654 PPGMPAGE pPage;
2655 rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pPage, &pRamHint);
2656 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2657
2658 /*
2659 * Take action according to the record type.
2660 */
2661 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2662 {
2663 case PGM_STATE_REC_RAM_ZERO:
2664 {
2665 if (PGM_PAGE_IS_ZERO(pPage))
2666 break;
2667
2668 /* Ballooned pages must be unmarked (live snapshot and
2669 teleportation scenarios). */
2670 if (PGM_PAGE_IS_BALLOONED(pPage))
2671 {
2672 Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2673 if (uVersion == PGM_SAVED_STATE_VERSION_BALLOON_BROKEN)
2674 break;
2675 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_ZERO);
2676 break;
2677 }
2678
2679 AssertLogRelMsgReturn(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED, ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_UNEXPECTED_PAGE_STATE);
2680
2681 /* If this is a ROM page, we must clear it and not try to
2682 * free it. Ditto if the VM is using RamPreAlloc (see
2683 * @bugref{6318}). */
2684 if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM
2685 || PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM_SHADOW
2686 || pVM->pgm.s.fRamPreAlloc)
2687 {
2688 PGMPAGEMAPLOCK PgMpLck;
2689 void *pvDstPage;
2690 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2691 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2692
2693 ASMMemZeroPage(pvDstPage);
2694 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2695 }
2696 /* Free it only if it's not part of a previously
2697 allocated large page (no need to clear the page). */
2698 else if ( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2699 && PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2700 {
2701 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2702 AssertRCReturn(rc, rc);
2703 }
2704 /** @todo handle large pages (see @bugref{5545}) */
2705 break;
2706 }
2707
2708 case PGM_STATE_REC_RAM_BALLOONED:
2709 {
2710 Assert(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM);
2711 if (PGM_PAGE_IS_BALLOONED(pPage))
2712 break;
2713
2714 /* We don't map ballooned pages in our shadow page tables, let's
2715 just free it if allocated and mark as ballooned. See @bugref{5515}. */
2716 if (PGM_PAGE_IS_ALLOCATED(pPage))
2717 {
2718 /** @todo handle large pages + ballooning when it works. (see @bugref{5515},
2719 * @bugref{5545}). */
2720 AssertLogRelMsgReturn( PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE
2721 && PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE_DISABLED,
2722 ("GCPhys=%RGp %R[pgmpage]\n", GCPhys, pPage), VERR_PGM_LOAD_UNEXPECTED_PAGE_TYPE);
2723
2724 rc = pgmPhysFreePage(pVM, pReq, &cPendingPages, pPage, GCPhys);
2725 AssertRCReturn(rc, rc);
2726 }
2727 Assert(PGM_PAGE_IS_ZERO(pPage));
2728 PGM_PAGE_SET_STATE(pVM, pPage, PGM_PAGE_STATE_BALLOONED);
2729 break;
2730 }
2731
2732 case PGM_STATE_REC_RAM_RAW:
2733 {
2734 PGMPAGEMAPLOCK PgMpLck;
2735 void *pvDstPage;
2736 rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvDstPage, &PgMpLck);
2737 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp %R[pgmpage] rc=%Rrc\n", GCPhys, pPage, rc), rc);
2738 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2739 pgmPhysReleaseInternalPageMappingLock(pVM, &PgMpLck);
2740 if (RT_FAILURE(rc))
2741 return rc;
2742 break;
2743 }
2744
2745 default:
2746 AssertMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2747 }
2748 id = UINT8_MAX;
2749 break;
2750 }
2751
2752 /*
2753 * MMIO2 page.
2754 */
2755 case PGM_STATE_REC_MMIO2_RAW:
2756 case PGM_STATE_REC_MMIO2_ZERO:
2757 {
2758 /*
2759 * Get the ID + page number and resolved that into a MMIO2 page.
2760 */
2761 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2762 iPage++;
2763 else
2764 {
2765 SSMR3GetU8(pSSM, &id);
2766 rc = SSMR3GetU32(pSSM, &iPage);
2767 if (RT_FAILURE(rc))
2768 return rc;
2769 }
2770 if ( !pMmio2
2771 || pMmio2->idSavedState != id)
2772 {
2773 for (pMmio2 = pVM->pgm.s.pMmio2RangesR3; pMmio2; pMmio2 = pMmio2->pNextR3)
2774 if (pMmio2->idSavedState == id)
2775 break;
2776 AssertLogRelMsgReturn(pMmio2, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_MMIO2_RANGE_NOT_FOUND);
2777 }
2778 AssertLogRelMsgReturn(iPage < (pMmio2->RamRange.cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pMmio2->RamRange.cb, pMmio2->RamRange.pszDesc), VERR_PGM_SAVED_MMIO2_PAGE_NOT_FOUND);
2779 void *pvDstPage = (uint8_t *)pMmio2->RamRange.pvR3 + ((size_t)iPage << PAGE_SHIFT);
2780
2781 /*
2782 * Load the page bits.
2783 */
2784 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_MMIO2_ZERO)
2785 ASMMemZeroPage(pvDstPage);
2786 else
2787 {
2788 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2789 if (RT_FAILURE(rc))
2790 return rc;
2791 }
2792 GCPhys = NIL_RTGCPHYS;
2793 break;
2794 }
2795
2796 /*
2797 * ROM pages.
2798 */
2799 case PGM_STATE_REC_ROM_VIRGIN:
2800 case PGM_STATE_REC_ROM_SHW_RAW:
2801 case PGM_STATE_REC_ROM_SHW_ZERO:
2802 case PGM_STATE_REC_ROM_PROT:
2803 {
2804 /*
2805 * Get the ID + page number and resolved that into a ROM page descriptor.
2806 */
2807 if (!(u8 & PGM_STATE_REC_FLAG_ADDR))
2808 iPage++;
2809 else
2810 {
2811 SSMR3GetU8(pSSM, &id);
2812 rc = SSMR3GetU32(pSSM, &iPage);
2813 if (RT_FAILURE(rc))
2814 return rc;
2815 }
2816 if ( !pRom
2817 || pRom->idSavedState != id)
2818 {
2819 for (pRom = pVM->pgm.s.pRomRangesR3; pRom; pRom = pRom->pNextR3)
2820 if (pRom->idSavedState == id)
2821 break;
2822 AssertLogRelMsgReturn(pRom, ("id=%#u iPage=%#x\n", id, iPage), VERR_PGM_SAVED_ROM_RANGE_NOT_FOUND);
2823 }
2824 AssertLogRelMsgReturn(iPage < (pRom->cb >> PAGE_SHIFT), ("iPage=%#x cb=%RGp %s\n", iPage, pRom->cb, pRom->pszDesc), VERR_PGM_SAVED_ROM_PAGE_NOT_FOUND);
2825 PPGMROMPAGE pRomPage = &pRom->aPages[iPage];
2826 GCPhys = pRom->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2827
2828 /*
2829 * Get and set the protection.
2830 */
2831 uint8_t u8Prot;
2832 rc = SSMR3GetU8(pSSM, &u8Prot);
2833 if (RT_FAILURE(rc))
2834 return rc;
2835 PGMROMPROT enmProt = (PGMROMPROT)u8Prot;
2836 AssertLogRelMsgReturn(enmProt > PGMROMPROT_INVALID && enmProt < PGMROMPROT_END, ("GCPhys=%RGp enmProt=%d\n", GCPhys, enmProt), VERR_PGM_SAVED_ROM_PAGE_PROT);
2837
2838 if (enmProt != pRomPage->enmProt)
2839 {
2840 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2841 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2842 N_("Protection change of unshadowed ROM page: GCPhys=%RGp enmProt=%d %s"),
2843 GCPhys, enmProt, pRom->pszDesc);
2844 rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2845 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2846 AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_PGM_SAVED_ROM_PAGE_PROT);
2847 }
2848 if ((u8 & ~PGM_STATE_REC_FLAG_ADDR) == PGM_STATE_REC_ROM_PROT)
2849 break; /* done */
2850
2851 /*
2852 * Get the right page descriptor.
2853 */
2854 PPGMPAGE pRealPage;
2855 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2856 {
2857 case PGM_STATE_REC_ROM_VIRGIN:
2858 if (!PGMROMPROT_IS_ROM(enmProt))
2859 pRealPage = &pRomPage->Virgin;
2860 else
2861 pRealPage = NULL;
2862 break;
2863
2864 case PGM_STATE_REC_ROM_SHW_RAW:
2865 case PGM_STATE_REC_ROM_SHW_ZERO:
2866 if (RT_UNLIKELY(!(pRom->fFlags & PGMPHYS_ROM_FLAGS_SHADOWED)))
2867 return SSMR3SetCfgError(pSSM, RT_SRC_POS,
2868 N_("Shadowed / non-shadowed page type mismatch: GCPhys=%RGp enmProt=%d %s"),
2869 GCPhys, enmProt, pRom->pszDesc);
2870 if (PGMROMPROT_IS_ROM(enmProt))
2871 pRealPage = &pRomPage->Shadow;
2872 else
2873 pRealPage = NULL;
2874 break;
2875
2876 default: AssertLogRelFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE); /* shut up gcc */
2877 }
2878 if (!pRealPage)
2879 {
2880 rc = pgmPhysGetPageWithHintEx(pVM, GCPhys, &pRealPage, &pRamHint);
2881 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc %RGp\n", rc, GCPhys), rc);
2882 }
2883
2884 /*
2885 * Make it writable and map it (if necessary).
2886 */
2887 void *pvDstPage = NULL;
2888 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2889 {
2890 case PGM_STATE_REC_ROM_SHW_ZERO:
2891 if ( PGM_PAGE_IS_ZERO(pRealPage)
2892 || PGM_PAGE_IS_BALLOONED(pRealPage))
2893 break;
2894 /** @todo implement zero page replacing. */
2895 /* fall thru */
2896 case PGM_STATE_REC_ROM_VIRGIN:
2897 case PGM_STATE_REC_ROM_SHW_RAW:
2898 {
2899 rc = pgmPhysPageMakeWritableAndMap(pVM, pRealPage, GCPhys, &pvDstPage);
2900 AssertLogRelMsgRCReturn(rc, ("GCPhys=%RGp rc=%Rrc\n", GCPhys, rc), rc);
2901 break;
2902 }
2903 }
2904
2905 /*
2906 * Load the bits.
2907 */
2908 switch (u8 & ~PGM_STATE_REC_FLAG_ADDR)
2909 {
2910 case PGM_STATE_REC_ROM_SHW_ZERO:
2911 if (pvDstPage)
2912 ASMMemZeroPage(pvDstPage);
2913 break;
2914
2915 case PGM_STATE_REC_ROM_VIRGIN:
2916 case PGM_STATE_REC_ROM_SHW_RAW:
2917 rc = SSMR3GetMem(pSSM, pvDstPage, PAGE_SIZE);
2918 if (RT_FAILURE(rc))
2919 return rc;
2920 break;
2921 }
2922 GCPhys = NIL_RTGCPHYS;
2923 break;
2924 }
2925
2926 /*
2927 * Unknown type.
2928 */
2929 default:
2930 AssertLogRelMsgFailedReturn(("%#x\n", u8), VERR_PGM_SAVED_REC_TYPE);
2931 }
2932 } /* forever */
2933}
2934
2935
2936/**
2937 * Worker for pgmR3Load.
2938 *
2939 * @returns VBox status code.
2940 *
2941 * @param pVM Pointer to the VM.
2942 * @param pSSM The SSM handle.
2943 * @param uVersion The saved state version.
2944 */
2945static int pgmR3LoadFinalLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2946{
2947 PPGM pPGM = &pVM->pgm.s;
2948 int rc;
2949 uint32_t u32Sep;
2950
2951 /*
2952 * Load basic data (required / unaffected by relocation).
2953 */
2954 if (uVersion >= PGM_SAVED_STATE_VERSION_3_0_0)
2955 {
2956 if (uVersion > PGM_SAVED_STATE_VERSION_PRE_BALLOON)
2957 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2958 else
2959 rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFieldsPreBalloon[0]);
2960
2961 AssertLogRelRCReturn(rc, rc);
2962
2963 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2964 {
2965 if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
2966 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFieldsPrePae[0]);
2967 else
2968 rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2969 AssertLogRelRCReturn(rc, rc);
2970 }
2971 }
2972 else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
2973 {
2974 AssertRelease(pVM->cCpus == 1);
2975
2976 PGMOLD pgmOld;
2977 rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2978 AssertLogRelRCReturn(rc, rc);
2979
2980 pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2981 pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2982 pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2983
2984 pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2985 pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2986 pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2987 }
2988 else
2989 {
2990 AssertRelease(pVM->cCpus == 1);
2991
2992 SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2993 SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2994 SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2995
2996 uint32_t cbRamSizeIgnored;
2997 rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2998 if (RT_FAILURE(rc))
2999 return rc;
3000 SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
3001
3002 uint32_t u32 = 0;
3003 SSMR3GetUInt(pSSM, &u32);
3004 pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
3005 SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
3006 RTUINT uGuestMode;
3007 SSMR3GetUInt(pSSM, &uGuestMode);
3008 pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
3009
3010 /* check separator. */
3011 SSMR3GetU32(pSSM, &u32Sep);
3012 if (RT_FAILURE(rc))
3013 return rc;
3014 if (u32Sep != (uint32_t)~0)
3015 {
3016 AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
3017 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3018 }
3019 }
3020
3021 /*
3022 * Fix the A20 mask.
3023 */
3024 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3025 pVM->aCpus[i].pgm.s.GCPhysA20Mask = ~(RTGCPHYS)(!pVM->aCpus[i].pgm.s.fA20Enabled << 20);
3026
3027 /*
3028 * The guest mappings - skipped now, see re-fixation in the caller.
3029 */
3030 if (uVersion <= PGM_SAVED_STATE_VERSION_PRE_PAE)
3031 {
3032 for (uint32_t i = 0; ; i++)
3033 {
3034 rc = SSMR3GetU32(pSSM, &u32Sep); /* sequence number */
3035 if (RT_FAILURE(rc))
3036 return rc;
3037 if (u32Sep == ~0U)
3038 break;
3039 AssertMsgReturn(u32Sep == i, ("u32Sep=%#x i=%#x\n", u32Sep, i), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3040
3041 char szDesc[256];
3042 rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
3043 if (RT_FAILURE(rc))
3044 return rc;
3045 RTGCPTR GCPtrIgnore;
3046 SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* GCPtr */
3047 rc = SSMR3GetGCPtr(pSSM, &GCPtrIgnore); /* cPTs */
3048 if (RT_FAILURE(rc))
3049 return rc;
3050 }
3051 }
3052
3053 /*
3054 * Load the RAM contents.
3055 */
3056 if (uVersion > PGM_SAVED_STATE_VERSION_3_0_0)
3057 {
3058 if (!pVM->pgm.s.LiveSave.fActive)
3059 {
3060 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3061 {
3062 rc = pgmR3LoadRamConfig(pVM, pSSM);
3063 if (RT_FAILURE(rc))
3064 return rc;
3065 }
3066 rc = pgmR3LoadRomRanges(pVM, pSSM);
3067 if (RT_FAILURE(rc))
3068 return rc;
3069 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3070 if (RT_FAILURE(rc))
3071 return rc;
3072 }
3073
3074 rc = pgmR3LoadMemory(pVM, pSSM, uVersion, SSM_PASS_FINAL);
3075 }
3076 else
3077 rc = pgmR3LoadMemoryOld(pVM, pSSM, uVersion);
3078
3079 /* Refresh balloon accounting. */
3080 if (pVM->pgm.s.cBalloonedPages)
3081 {
3082 Log(("pgmR3LoadFinalLocked: pVM=%p cBalloonedPages=%#x\n", pVM, pVM->pgm.s.cBalloonedPages));
3083 rc = GMMR3BalloonedPages(pVM, GMMBALLOONACTION_INFLATE, pVM->pgm.s.cBalloonedPages);
3084 AssertRCReturn(rc, rc);
3085 }
3086 return rc;
3087}
3088
3089
3090/**
3091 * Execute state load operation.
3092 *
3093 * @returns VBox status code.
3094 * @param pVM Pointer to the VM.
3095 * @param pSSM SSM operation handle.
3096 * @param uVersion Data layout version.
3097 * @param uPass The data pass.
3098 */
3099static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3100{
3101 int rc;
3102
3103 /*
3104 * Validate version.
3105 */
3106 if ( ( uPass != SSM_PASS_FINAL
3107 && uVersion != PGM_SAVED_STATE_VERSION
3108 && uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3109 && uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3110 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3111 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3112 || ( uVersion != PGM_SAVED_STATE_VERSION
3113 && uVersion != PGM_SAVED_STATE_VERSION_PRE_PAE
3114 && uVersion != PGM_SAVED_STATE_VERSION_BALLOON_BROKEN
3115 && uVersion != PGM_SAVED_STATE_VERSION_PRE_BALLOON
3116 && uVersion != PGM_SAVED_STATE_VERSION_NO_RAM_CFG
3117 && uVersion != PGM_SAVED_STATE_VERSION_3_0_0
3118 && uVersion != PGM_SAVED_STATE_VERSION_2_2_2
3119 && uVersion != PGM_SAVED_STATE_VERSION_RR_DESC
3120 && uVersion != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3121 )
3122 {
3123 AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
3124 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3125 }
3126
3127 /*
3128 * Do the loading while owning the lock because a bunch of the functions
3129 * we're using requires this.
3130 */
3131 if (uPass != SSM_PASS_FINAL)
3132 {
3133 pgmLock(pVM);
3134 if (uPass != 0)
3135 rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3136 else
3137 {
3138 pVM->pgm.s.LiveSave.fActive = true;
3139 if (uVersion > PGM_SAVED_STATE_VERSION_NO_RAM_CFG)
3140 rc = pgmR3LoadRamConfig(pVM, pSSM);
3141 else
3142 rc = VINF_SUCCESS;
3143 if (RT_SUCCESS(rc))
3144 rc = pgmR3LoadRomRanges(pVM, pSSM);
3145 if (RT_SUCCESS(rc))
3146 rc = pgmR3LoadMmio2Ranges(pVM, pSSM);
3147 if (RT_SUCCESS(rc))
3148 rc = pgmR3LoadMemory(pVM, pSSM, uVersion, uPass);
3149 }
3150 pgmUnlock(pVM);
3151 }
3152 else
3153 {
3154 pgmLock(pVM);
3155 rc = pgmR3LoadFinalLocked(pVM, pSSM, uVersion);
3156 pVM->pgm.s.LiveSave.fActive = false;
3157 pgmUnlock(pVM);
3158 if (RT_SUCCESS(rc))
3159 {
3160 /*
3161 * We require a full resync now.
3162 */
3163 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3164 {
3165 PVMCPU pVCpu = &pVM->aCpus[i];
3166 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3167 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3168 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3169 /** @todo For guest PAE, we might get the wrong
3170 * aGCPhysGstPaePDs values now. We should used the
3171 * saved ones... Postponing this since it nothing new
3172 * and PAE/PDPTR needs some general readjusting, see
3173 * @bugref{5880}. */
3174 }
3175
3176 pgmR3HandlerPhysicalUpdateAll(pVM);
3177
3178 /*
3179 * Change the paging mode and restore PGMCPU::GCPhysCR3.
3180 * (The latter requires the CPUM state to be restored already.)
3181 */
3182 if (CPUMR3IsStateRestorePending(pVM))
3183 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3184 N_("PGM was unexpectedly restored before CPUM"));
3185
3186 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3187 {
3188 PVMCPU pVCpu = &pVM->aCpus[i];
3189
3190 rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3191 AssertLogRelRCReturn(rc, rc);
3192
3193 /* Update pVM->pgm.s.GCPhysCR3. */
3194 Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS || FTMIsDeltaLoadSaveActive(pVM));
3195 RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3196 if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3197 || pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3198 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3199 || pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3200 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3201 else
3202 GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3203 pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3204
3205 /* Update the PSE, NX flags and validity masks. */
3206 pVCpu->pgm.s.fGst32BitPageSizeExtension = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3207 PGMNotifyNxeChanged(pVCpu, CPUMIsGuestNXEnabled(pVCpu));
3208 }
3209
3210 /*
3211 * Try re-fixate the guest mappings.
3212 */
3213 pVM->pgm.s.fMappingsFixedRestored = false;
3214 if ( pVM->pgm.s.fMappingsFixed
3215 && pgmMapAreMappingsEnabled(pVM))
3216 {
3217 RTGCPTR GCPtrFixed = pVM->pgm.s.GCPtrMappingFixed;
3218 uint32_t cbFixed = pVM->pgm.s.cbMappingFixed;
3219 pVM->pgm.s.fMappingsFixed = false;
3220
3221 uint32_t cbRequired;
3222 int rc2 = PGMR3MappingsSize(pVM, &cbRequired); AssertRC(rc2);
3223 if ( RT_SUCCESS(rc2)
3224 && cbRequired > cbFixed)
3225 rc2 = VERR_OUT_OF_RANGE;
3226 if (RT_SUCCESS(rc2))
3227 rc2 = pgmR3MappingsFixInternal(pVM, GCPtrFixed, cbFixed);
3228 if (RT_FAILURE(rc2))
3229 {
3230 LogRel(("PGM: Unable to re-fixate the guest mappings at %RGv-%RGv: rc=%Rrc (cbRequired=%#x)\n",
3231 GCPtrFixed, GCPtrFixed + cbFixed, rc2, cbRequired));
3232 pVM->pgm.s.fMappingsFixed = false;
3233 pVM->pgm.s.fMappingsFixedRestored = true;
3234 pVM->pgm.s.GCPtrMappingFixed = GCPtrFixed;
3235 pVM->pgm.s.cbMappingFixed = cbFixed;
3236 }
3237 }
3238 else
3239 {
3240 /* We used to set fixed + disabled while we only use disabled now,
3241 so wipe the state to avoid any confusion. */
3242 pVM->pgm.s.fMappingsFixed = false;
3243 pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
3244 pVM->pgm.s.cbMappingFixed = 0;
3245 }
3246
3247 /*
3248 * If we have floating mappings, do a CR3 sync now to make sure the HMA
3249 * doesn't conflict with guest code / data and thereby cause trouble
3250 * when restoring other components like PATM.
3251 */
3252 if (pgmMapAreMappingsFloating(pVM))
3253 {
3254 PVMCPU pVCpu = &pVM->aCpus[0];
3255 rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), true);
3256 if (RT_FAILURE(rc))
3257 return SSMR3SetLoadError(pSSM, VERR_WRONG_ORDER, RT_SRC_POS,
3258 N_("PGMSyncCR3 failed unexpectedly with rc=%Rrc"), rc);
3259
3260 /* Make sure to re-sync before executing code. */
3261 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3262 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3263 pVCpu->pgm.s.fSyncFlags |= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3264 }
3265 }
3266 }
3267
3268 return rc;
3269}
3270
3271
3272/**
3273 * Registers the saved state callbacks with SSM.
3274 *
3275 * @returns VBox status code.
3276 * @param pVM Pointer to VM.
3277 * @param cbRam The RAM size.
3278 */
3279int pgmR3InitSavedState(PVM pVM, uint64_t cbRam)
3280{
3281 return SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
3282 pgmR3LivePrep, pgmR3LiveExec, pgmR3LiveVote,
3283 NULL, pgmR3SaveExec, pgmR3SaveDone,
3284 pgmR3LoadPrep, pgmR3Load, NULL);
3285}
3286
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