VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 84044

Last change on this file since 84044 was 83263, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Skeletal bits.
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File size: 12.4 KB
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1/* $Id: PDMDevMiscHlp.cpp 83263 2020-03-11 16:34:33Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/thread.h>
36
37
38#include "PDMInline.h"
39#include "dtrace/VBoxVMM.h"
40
41
42
43/** @name Ring-3 PIC Helpers
44 * @{
45 */
46
47/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
48static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
49{
50 PDMDEV_ASSERT_DEVINS(pDevIns);
51 PVM pVM = pDevIns->Internal.s.pVMR3;
52 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
53
54 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
55 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
56
57 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
58}
59
60
61/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
62static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
63{
64 PDMDEV_ASSERT_DEVINS(pDevIns);
65 PVM pVM = pDevIns->Internal.s.pVMR3;
66 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
67
68 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
69 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
70
71 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
72}
73
74
75/** @interface_method_impl{PDMPICHLP,pfnLock} */
76static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
77{
78 PDMDEV_ASSERT_DEVINS(pDevIns);
79 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
80}
81
82
83/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
84static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
85{
86 PDMDEV_ASSERT_DEVINS(pDevIns);
87 pdmUnlock(pDevIns->Internal.s.pVMR3);
88}
89
90
91/**
92 * PIC Device Helpers.
93 */
94const PDMPICHLP g_pdmR3DevPicHlp =
95{
96 PDM_PICHLP_VERSION,
97 pdmR3PicHlp_SetInterruptFF,
98 pdmR3PicHlp_ClearInterruptFF,
99 pdmR3PicHlp_Lock,
100 pdmR3PicHlp_Unlock,
101 PDM_PICHLP_VERSION /* the end */
102};
103
104/** @} */
105
106
107/** @name Ring-3 I/O APIC Helpers
108 * @{
109 */
110
111/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
112static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
113 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
114 uint8_t u8TriggerMode, uint32_t uTagSrc)
115{
116 PDMDEV_ASSERT_DEVINS(pDevIns);
117 PVM pVM = pDevIns->Internal.s.pVMR3;
118 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
119 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
120 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
121}
122
123
124/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
125static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
126{
127 PDMDEV_ASSERT_DEVINS(pDevIns);
128 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
129 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
130}
131
132
133/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
134static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
135{
136 PDMDEV_ASSERT_DEVINS(pDevIns);
137 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
138 pdmUnlock(pDevIns->Internal.s.pVMR3);
139}
140
141
142/**
143 * I/O APIC Device Helpers.
144 */
145const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
146{
147 PDM_IOAPICHLP_VERSION,
148 pdmR3IoApicHlp_ApicBusDeliver,
149 pdmR3IoApicHlp_Lock,
150 pdmR3IoApicHlp_Unlock,
151 PDM_IOAPICHLP_VERSION /* the end */
152};
153
154/** @} */
155
156
157
158
159/** @name Ring-3 PCI Bus Helpers
160 * @{
161 */
162
163/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
164static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
165{
166 PDMDEV_ASSERT_DEVINS(pDevIns);
167 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
168 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
169}
170
171
172/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
173static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
174{
175 PDMDEV_ASSERT_DEVINS(pDevIns);
176 Log4(("pdmR3PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
177 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
178}
179
180
181/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
182static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
183{
184 PDMDEV_ASSERT_DEVINS(pDevIns);
185 Log4(("pdmR3PciHlp_IoApicSendMsi: address=%p value=%x uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
186 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, GCPhys, uValue, uTagSrc);
187}
188
189
190/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
191static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
192{
193 PDMDEV_ASSERT_DEVINS(pDevIns);
194 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
195 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
196}
197
198
199/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
200static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
201{
202 PDMDEV_ASSERT_DEVINS(pDevIns);
203 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
204 pdmUnlock(pDevIns->Internal.s.pVMR3);
205}
206
207
208/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
209static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
210{
211 PDMDEV_ASSERT_DEVINS(pDevIns);
212 PVM pVM = pDevIns->Internal.s.pVMR3;
213 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
214 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
215 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
216 return pRetDevIns;
217}
218
219
220/**
221 * PCI Bus Device Helpers.
222 */
223const PDMPCIHLPR3 g_pdmR3DevPciHlp =
224{
225 PDM_PCIHLPR3_VERSION,
226 pdmR3PciHlp_IsaSetIrq,
227 pdmR3PciHlp_IoApicSetIrq,
228 pdmR3PciHlp_IoApicSendMsi,
229 pdmR3PciHlp_Lock,
230 pdmR3PciHlp_Unlock,
231 pdmR3PciHlp_GetBusByNo,
232 PDM_PCIHLPR3_VERSION, /* the end */
233};
234
235/** @} */
236
237
238/**
239 * IOMMU Device Helpers.
240 */
241const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
242{
243 PDM_IOMMUHLPR3_VERSION,
244 PDM_IOMMUHLPR3_VERSION /* the end */
245};
246
247
248/** @name Ring-3 HPET Helpers
249 * @{
250 */
251
252/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
253static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
254{
255 PDMDEV_ASSERT_DEVINS(pDevIns);
256 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
257
258 size_t i;
259 int rc = VINF_SUCCESS;
260 static const char * const s_apszDevsToNotify[] =
261 {
262 "i8254",
263 "mc146818"
264 };
265 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
266 {
267 PPDMIBASE pBase;
268 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
269 if (RT_SUCCESS(rc))
270 {
271 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
272 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
273 pPort->pfnModeChanged(pPort, fActivated);
274 }
275 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
276 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
277 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
278 else
279 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
280 }
281
282 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
283
284 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
285 return rc;
286}
287
288
289/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
290static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
291{
292 PDMDEV_ASSERT_DEVINS(pDevIns);
293 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
294 PVM pVM = pDevIns->Internal.s.pVMR3;
295
296 pdmLock(pVM);
297 uint32_t uTagSrc;
298 if (iLevel & PDM_IRQ_LEVEL_HIGH)
299 {
300 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
301 if (iLevel == PDM_IRQ_LEVEL_HIGH)
302 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
303 else
304 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
305 }
306 else
307 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
308
309 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
310
311 if (iLevel == PDM_IRQ_LEVEL_LOW)
312 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
313 pdmUnlock(pVM);
314 return 0;
315}
316
317
318/**
319 * HPET Device Helpers.
320 */
321const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
322{
323 PDM_HPETHLPR3_VERSION,
324 pdmR3HpetHlp_SetLegacyMode,
325 pdmR3HpetHlp_SetIrq,
326 PDM_HPETHLPR3_VERSION, /* the end */
327};
328
329/** @} */
330
331
332/** @name Ring-3 Raw PCI Device Helpers
333 * @{
334 */
335
336/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
337static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
338{
339 PDMDEV_ASSERT_DEVINS(pDevIns);
340 PVM pVM = pDevIns->Internal.s.pVMR3;
341 VM_ASSERT_EMT(pVM);
342
343 RTRCPTR pRCHelpers = NIL_RTRCPTR;
344 if (VM_IS_RAW_MODE_ENABLED(pVM))
345 {
346 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
347 AssertReleaseRC(rc);
348 AssertRelease(pRCHelpers);
349 }
350
351 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
352 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
353 return pRCHelpers;
354}
355
356
357/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
358static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
359{
360 PDMDEV_ASSERT_DEVINS(pDevIns);
361 PVM pVM = pDevIns->Internal.s.pVMR3;
362 VM_ASSERT_EMT(pVM);
363 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
364 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
365 AssertReleaseRC(rc);
366 AssertRelease(pR0Helpers);
367 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
368 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
369 return pR0Helpers;
370}
371
372
373/**
374 * Raw PCI Device Helpers.
375 */
376const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
377{
378 PDM_PCIRAWHLPR3_VERSION,
379 pdmR3PciRawHlp_GetRCHelpers,
380 pdmR3PciRawHlp_GetR0Helpers,
381 PDM_PCIRAWHLPR3_VERSION, /* the end */
382};
383
384/** @} */
385
386
387/* none yet */
388
389/**
390 * Firmware Device Helpers.
391 */
392const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
393{
394 PDM_FWHLPR3_VERSION,
395 PDM_FWHLPR3_VERSION
396};
397
398/**
399 * DMAC Device Helpers.
400 */
401const PDMDMACHLP g_pdmR3DevDmacHlp =
402{
403 PDM_DMACHLP_VERSION
404};
405
406
407
408
409/* none yet */
410
411/**
412 * RTC Device Helpers.
413 */
414const PDMRTCHLP g_pdmR3DevRtcHlp =
415{
416 PDM_RTCHLP_VERSION
417};
418
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