VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3IoPort.cpp@ 84044

Last change on this file since 84044 was 82968, checked in by vboxsync, 4 years ago

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[23]1/* $Id: IOMR3IoPort.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
[1]2/** @file
[81156]3 * IOM - Input / Output Monitor, I/O port related APIs.
[1]4 */
5
6/*
[82968]7 * Copyright (C) 2006-2020 Oracle Corporation
[1]8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
[5999]12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
[1]16 */
17
18
[57358]19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
[81383]22#define LOG_GROUP LOG_GROUP_IOM_IOPORT
[35346]23#include <VBox/vmm/iom.h>
[1]24#include <VBox/sup.h>
[35346]25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/vmm/dbgf.h>
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/pdmdev.h>
[1]30#include "IOMInternal.h"
[35346]31#include <VBox/vmm/vm.h>
[1]32
33#include <VBox/param.h>
34#include <iprt/assert.h>
35#include <iprt/string.h>
36#include <VBox/log.h>
37#include <VBox/err.h>
38
[37424]39#include "IOMInline.h"
[1]40
[37424]41
[80649]42#ifdef VBOX_WITH_STATISTICS
[1]43
44/**
[81156]45 * Register statistics for an I/O port entry.
[1]46 */
[81156]47void iomR3IoPortRegStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry)
[1]48{
[81797]49 bool const fDoRZ = pRegEntry->fRing0 || pRegEntry->fRawMode;
[81156]50 PIOMIOPORTSTATSENTRY pStats = &pVM->iom.s.paIoPortStats[pRegEntry->idxStats];
51 PCIOMIOPORTDESC pExtDesc = pRegEntry->paExtDescs;
52 unsigned uPort = pRegEntry->uPort;
53 unsigned const uFirstPort = uPort;
54 unsigned const uEndPort = uPort + pRegEntry->cPorts;
[1]55
[81156]56 /* Register a dummy statistics for the prefix. */
57 char szName[80];
58 size_t cchPrefix;
59 if (uFirstPort < uEndPort - 1)
[82378]60 cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/IoPorts/%04x-%04x", uFirstPort, uEndPort - 1);
[81156]61 else
[82378]62 cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/IoPorts/%04x", uPort);
[81156]63 const char *pszDesc = pRegEntry->pszDesc;
64 char *pszFreeDesc = NULL;
65 if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
66 pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
[82378]67 int rc = STAMR3Register(pVM, &pStats->Total, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName,
[81156]68 STAMUNIT_NONE, pRegEntry->pszDesc);
69 AssertRC(rc);
70 RTStrFree(pszFreeDesc);
[1]71
[81156]72 /* Register stats for each port under it */
73 do
[1]74 {
[81156]75 size_t cchBaseNm;
76 if (uFirstPort < uEndPort - 1)
77 cchBaseNm = cchPrefix + RTStrPrintf(&szName[cchPrefix], sizeof(szName) - cchPrefix, "/%04x-", uPort);
78 else
[55493]79 {
[81156]80 szName[cchPrefix] = '/';
81 cchBaseNm = cchPrefix + 1;
[55493]82 }
[1]83
[81156]84# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchBaseNm], a_sz, sizeof(a_sz));
85 const char * const pszInDesc = pExtDesc ? pExtDesc->pszIn : NULL;
86 const char * const pszOutDesc = pExtDesc ? pExtDesc->pszOut : NULL;
[1]87
[81156]88 /* register the statistics counters. */
89 SET_NM_SUFFIX("In-R3");
90 rc = STAMR3Register(pVM, &pStats->InR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
91 SET_NM_SUFFIX("Out-R3");
92 rc = STAMR3Register(pVM, &pStats->OutR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
[81797]93 if (fDoRZ)
94 {
95 SET_NM_SUFFIX("In-RZ");
96 rc = STAMR3Register(pVM, &pStats->InRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
97 SET_NM_SUFFIX("Out-RZ");
98 rc = STAMR3Register(pVM, &pStats->OutRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
99 SET_NM_SUFFIX("In-RZtoR3");
100 rc = STAMR3Register(pVM, &pStats->InRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
101 SET_NM_SUFFIX("Out-RZtoR3");
102 rc = STAMR3Register(pVM, &pStats->OutRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
103 }
[1]104
[81156]105 /* Profiling */
106 SET_NM_SUFFIX("In-R3-Prof");
107 rc = STAMR3Register(pVM, &pStats->ProfInR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
108 SET_NM_SUFFIX("Out-R3-Prof");
109 rc = STAMR3Register(pVM, &pStats->ProfOutR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
[81797]110 if (fDoRZ)
111 {
112 SET_NM_SUFFIX("In-RZ-Prof");
113 rc = STAMR3Register(pVM, &pStats->ProfInRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
114 SET_NM_SUFFIX("Out-RZ-Prof");
115 rc = STAMR3Register(pVM, &pStats->ProfOutRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
116 }
[1]117
[81156]118 pStats++;
119 uPort++;
120 if (pExtDesc)
121 pExtDesc = pszInDesc || pszOutDesc ? pExtDesc + 1 : NULL;
122 } while (uPort < uEndPort);
[80649]123}
124
125
126/**
[81156]127 * Deregister statistics for an I/O port entry.
[7726]128 */
[81156]129static void iomR3IoPortDeregStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry, unsigned uPort)
[7726]130{
[81156]131 char szPrefix[80];
132 size_t cchPrefix;
133 if (pRegEntry->cPorts > 1)
[82378]134 cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/IoPorts/%04x-%04x", uPort, uPort + pRegEntry->cPorts - 1);
[81156]135 else
[82378]136 cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/IoPorts/%04x", uPort);
[81156]137 STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
[7726]138}
139
[81156]140#endif /* VBOX_WITH_STATISTICS */
[7726]141
[1]142
143/**
[81156]144 * @callback_method_impl{FNIOMIOPORTNEWIN,
145 * Dummy Port I/O Handler for IN operations.}
[1]146 */
[81156]147static DECLCALLBACK(VBOXSTRICTRC)
148iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
[1]149{
[81156]150 NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
151 switch (cb)
[45305]152 {
[81156]153 case 1: *pu32 = 0xff; break;
154 case 2: *pu32 = 0xffff; break;
155 case 4: *pu32 = UINT32_C(0xffffffff); break;
156 default:
157 AssertReleaseMsgFailed(("cb=%d\n", cb));
158 return VERR_IOM_IOPORT_IPE_2;
[45305]159 }
[81156]160 return VINF_SUCCESS;
[1]161}
162
163
164/**
[81156]165 * @callback_method_impl{FNIOMIOPORTNEWINSTRING,
166 * Dummy Port I/O Handler for string IN operations.}
[1]167 */
[81156]168static DECLCALLBACK(VBOXSTRICTRC)
169iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst, uint32_t *pcTransfer, unsigned cb)
[1]170{
[81156]171 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
172 return VINF_SUCCESS;
[1]173}
174
175
176/**
[81156]177 * @callback_method_impl{FNIOMIOPORTNEWOUT,
178 * Dummy Port I/O Handler for OUT operations.}
[1]179 */
[81156]180static DECLCALLBACK(VBOXSTRICTRC)
181iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
[1]182{
[81156]183 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
184 return VINF_SUCCESS;
[1]185}
[80091]186
[1]187
188/**
[81156]189 * @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
190 * Dummy Port I/O Handler for string OUT operations.}
[1]191 */
[81156]192static DECLCALLBACK(VBOXSTRICTRC)
193iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc, uint32_t *pcTransfer, unsigned cb)
[1]194{
[81156]195 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
[1]196 return VINF_SUCCESS;
197}
198
[80641]199
[81156]200
[80641]201/**
202 * Worker for PDMDEVHLPR3::pfnIoPortCreateEx.
203 */
204VMMR3_INT_DECL(int) IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
[80960]205 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
206 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
[80679]207 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
[80641]208{
209 /*
210 * Validate input.
211 */
212 AssertPtrReturn(phIoPorts, VERR_INVALID_POINTER);
213 *phIoPorts = UINT32_MAX;
214 VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
215 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
216
217 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
218
[81162]219 AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%#x\n", cPorts), VERR_OUT_OF_RANGE);
[81136]220 AssertReturn(!(fFlags & ~IOM_IOPORT_F_VALID_MASK), VERR_INVALID_FLAGS);
[80641]221
222 AssertReturn(pfnOut || pfnIn || pfnOutStr || pfnInStr, VERR_INVALID_PARAMETER);
223 AssertPtrNullReturn(pfnOut, VERR_INVALID_POINTER);
224 AssertPtrNullReturn(pfnIn, VERR_INVALID_POINTER);
225 AssertPtrNullReturn(pfnOutStr, VERR_INVALID_POINTER);
226 AssertPtrNullReturn(pfnInStr, VERR_INVALID_POINTER);
227 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
228 AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
229 AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
[80679]230 if (paExtDescs)
231 {
232 AssertPtrReturn(paExtDescs, VERR_INVALID_POINTER);
233 for (size_t i = 0;; i++)
234 {
235 const char *pszIn = paExtDescs[i].pszIn;
236 const char *pszOut = paExtDescs[i].pszIn;
237 if (!pszIn && !pszOut)
238 break;
239 AssertReturn(i < _8K, VERR_OUT_OF_RANGE);
240 AssertReturn(!pszIn || strlen(pszIn) < 128, VERR_INVALID_POINTER);
241 AssertReturn(!pszOut || strlen(pszOut) < 128, VERR_INVALID_POINTER);
242 }
243 }
[80641]244
245 /*
246 * Ensure that we've got table space for it.
247 */
248#ifndef VBOX_WITH_STATISTICS
249 uint16_t const idxStats = UINT16_MAX;
250#else
251 uint32_t const idxStats = pVM->iom.s.cIoPortStats;
252 uint32_t const cNewIoPortStats = idxStats + cPorts;
253 AssertReturn(cNewIoPortStats <= _64K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
254 if (cNewIoPortStats > pVM->iom.s.cIoPortStatsAllocation)
255 {
256 int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORT_STATS, cNewIoPortStats, NULL);
257 AssertLogRelRCReturn(rc, rc);
258 AssertReturn(idxStats == pVM->iom.s.cIoPortStats, VERR_IOM_IOPORT_IPE_1);
259 AssertReturn(cNewIoPortStats <= pVM->iom.s.cIoPortStatsAllocation, VERR_IOM_IOPORT_IPE_2);
260 }
261#endif
262
263 uint32_t idx = pVM->iom.s.cIoPortRegs;
264 if (idx >= pVM->iom.s.cIoPortAlloc)
265 {
266 int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORTS, pVM->iom.s.cIoPortAlloc + 1, NULL);
267 AssertLogRelRCReturn(rc, rc);
268 AssertReturn(idx == pVM->iom.s.cIoPortRegs, VERR_IOM_IOPORT_IPE_1);
269 AssertReturn(idx < pVM->iom.s.cIoPortAlloc, VERR_IOM_IOPORT_IPE_2);
270 }
271
272 /*
273 * Enter it.
274 */
275 pVM->iom.s.paIoPortRegs[idx].pvUser = pvUser;
276 pVM->iom.s.paIoPortRegs[idx].pDevIns = pDevIns;
[80960]277 pVM->iom.s.paIoPortRegs[idx].pfnOutCallback = pfnOut ? pfnOut : iomR3IOPortDummyNewOut;
278 pVM->iom.s.paIoPortRegs[idx].pfnInCallback = pfnIn ? pfnIn : iomR3IOPortDummyNewIn;
279 pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
280 pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback = pfnInStr ? pfnInStr : iomR3IOPortDummyNewInStr;
[80641]281 pVM->iom.s.paIoPortRegs[idx].pszDesc = pszDesc;
[80679]282 pVM->iom.s.paIoPortRegs[idx].paExtDescs = paExtDescs;
[80641]283 pVM->iom.s.paIoPortRegs[idx].pPciDev = pPciDev;
284 pVM->iom.s.paIoPortRegs[idx].iPciRegion = iPciRegion;
285 pVM->iom.s.paIoPortRegs[idx].cPorts = cPorts;
286 pVM->iom.s.paIoPortRegs[idx].uPort = UINT16_MAX;
287 pVM->iom.s.paIoPortRegs[idx].idxStats = (uint16_t)idxStats;
288 pVM->iom.s.paIoPortRegs[idx].fMapped = false;
[81136]289 pVM->iom.s.paIoPortRegs[idx].fFlags = (uint8_t)fFlags;
[80641]290 pVM->iom.s.paIoPortRegs[idx].idxSelf = idx;
291
292 pVM->iom.s.cIoPortRegs = idx + 1;
[81461]293#ifdef VBOX_WITH_STATISTICS
294 pVM->iom.s.cIoPortStats = cNewIoPortStats;
295#endif
[80641]296 *phIoPorts = idx;
[82277]297 LogFlow(("IOMR3IoPortCreate: idx=%#x cPorts=%u %s\n", idx, cPorts, pszDesc));
[80641]298 return VINF_SUCCESS;
299}
300
301
302/**
303 * Worker for PDMDEVHLPR3::pfnIoPortMap.
304 */
305VMMR3_INT_DECL(int) IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT uPort)
306{
307 /*
308 * Validate input and state.
309 */
310 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
311 AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
312 PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
313 AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
314
315 RTIOPORT const cPorts = pRegEntry->cPorts;
316 AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%s\n", cPorts), VERR_IOM_IOPORT_IPE_1);
317 AssertReturn((uint32_t)uPort + cPorts <= _64K, VERR_OUT_OF_RANGE);
318 RTIOPORT const uLastPort = uPort + cPorts - 1;
[82277]319 LogFlow(("IOMR3IoPortMap: hIoPorts=%#RX64 %RTiop..%RTiop (%u ports)\n", hIoPorts, uPort, uLastPort, cPorts));
[80641]320
321 /*
322 * Do the mapping.
323 */
324 int rc = VINF_SUCCESS;
325 IOM_LOCK_EXCL(pVM);
326
327 if (!pRegEntry->fMapped)
328 {
329 uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
330 Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
331
332 PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
333 PIOMIOPORTLOOKUPENTRY pEntry;
334 if (cEntries > 0)
335 {
336 uint32_t iFirst = 0;
337 uint32_t iEnd = cEntries;
338 uint32_t i = cEntries / 2;
339 for (;;)
340 {
341 pEntry = &paEntries[i];
342 if (pEntry->uLastPort < uPort)
343 {
344 i += 1;
345 if (i < iEnd)
346 iFirst = i;
347 else
348 {
349 /* Insert after the entry we just considered: */
350 pEntry += 1;
[80960]351 if (i < cEntries)
352 memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
[80641]353 break;
354 }
355 }
356 else if (pEntry->uFirstPort > uLastPort)
357 {
358 if (i > iFirst)
359 iEnd = i;
360 else
361 {
362 /* Insert at the entry we just considered: */
[80960]363 if (i < cEntries)
364 memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
[80641]365 break;
366 }
367 }
368 else
369 {
370 /* Oops! We've got a conflict. */
[81162]371 AssertLogRelMsgFailed(("%x..%x (%s) conflicts with existing mapping %x..%x (%s)\n",
[80641]372 uPort, uLastPort, pRegEntry->pszDesc,
373 pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
374 IOM_UNLOCK_EXCL(pVM);
375 return VERR_IOM_IOPORT_RANGE_CONFLICT;
376 }
377
378 i = iFirst + (iEnd - iFirst) / 2;
379 }
380 }
381 else
382 pEntry = paEntries;
383
384 /*
385 * Fill in the entry and bump the table size.
386 */
387 pEntry->idx = hIoPorts;
388 pEntry->uFirstPort = uPort;
389 pEntry->uLastPort = uLastPort;
390 pVM->iom.s.cIoPortLookupEntries = cEntries + 1;
391
392 pRegEntry->uPort = uPort;
393 pRegEntry->fMapped = true;
394
[80649]395#ifdef VBOX_WITH_STATISTICS
396 /* Don't register stats here when we're creating the VM as the
397 statistics table may still be reallocated. */
398 if (pVM->enmVMState >= VMSTATE_CREATED)
399 iomR3IoPortRegStats(pVM, pRegEntry);
400#endif
401
[80641]402#ifdef VBOX_STRICT
403 /*
404 * Assert table sanity.
405 */
406 AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
407 AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
408
409 RTIOPORT uPortPrev = paEntries[0].uLastPort;
410 for (size_t i = 1; i <= cEntries; i++)
411 {
412 AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
413 AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
414 AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
[82277]415 AssertMsg(paEntries[i].uLastPort - paEntries[i].uFirstPort + 1 == pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts,
416 ("%u: %#x %#x..%#x -> %u, expected %u\n", i, uPortPrev, paEntries[i].uFirstPort, paEntries[i].uLastPort,
417 paEntries[i].uLastPort - paEntries[i].uFirstPort + 1, pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts));
[80641]418 uPortPrev = paEntries[i].uLastPort;
419 }
420#endif
421 }
422 else
423 {
424 AssertFailed();
425 rc = VERR_IOM_IOPORTS_ALREADY_MAPPED;
426 }
427
428 IOM_UNLOCK_EXCL(pVM);
429 return rc;
430}
431
432
433/**
434 * Worker for PDMDEVHLPR3::pfnIoPortUnmap.
435 */
436VMMR3_INT_DECL(int) IOMR3IoPortUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
437{
438 /*
439 * Validate input and state.
440 */
441 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
442 AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
443 PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
444 AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
445
446 /*
447 * Do the mapping.
448 */
449 int rc;
450 IOM_LOCK_EXCL(pVM);
451
452 if (pRegEntry->fMapped)
453 {
454 RTIOPORT const uPort = pRegEntry->uPort;
455 RTIOPORT const uLastPort = uPort + pRegEntry->cPorts - 1;
456 uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
457 Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
458 Assert(cEntries > 0);
[82277]459 LogFlow(("IOMR3IoPortUnmap: hIoPorts=%#RX64 %RTiop..%RTiop (%u ports)\n", hIoPorts, uPort, uLastPort, pRegEntry->cPorts));
[80641]460
461 PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
462 uint32_t iFirst = 0;
463 uint32_t iEnd = cEntries;
464 uint32_t i = cEntries / 2;
465 for (;;)
466 {
467 PIOMIOPORTLOOKUPENTRY pEntry = &paEntries[i];
468 if (pEntry->uLastPort < uPort)
469 {
470 i += 1;
471 if (i < iEnd)
472 iFirst = i;
473 else
474 {
475 rc = VERR_IOM_IOPORT_IPE_1;
[81162]476 AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
[80641]477 }
478 }
479 else if (pEntry->uFirstPort > uLastPort)
480 {
481 if (i > iFirst)
482 iEnd = i;
483 else
484 {
485 rc = VERR_IOM_IOPORT_IPE_1;
[81162]486 AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
[80641]487 }
488 }
489 else if (pEntry->idx == hIoPorts)
490 {
491 Assert(pEntry->uFirstPort == uPort);
492 Assert(pEntry->uLastPort == uLastPort);
[80649]493#ifdef VBOX_WITH_STATISTICS
494 iomR3IoPortDeregStats(pVM, pRegEntry, uPort);
495#endif
[80641]496 if (i + 1 < cEntries)
497 memmove(pEntry, pEntry + 1, sizeof(*pEntry) * (cEntries - i - 1));
498 pVM->iom.s.cIoPortLookupEntries = cEntries - 1;
499 pRegEntry->uPort = UINT16_MAX;
500 pRegEntry->fMapped = false;
501 rc = VINF_SUCCESS;
502 break;
503 }
504 else
505 {
[81162]506 AssertLogRelMsgFailed(("Lookig for %x..%x (%s), found %x..%x (%s) instead!\n",
[80641]507 uPort, uLastPort, pRegEntry->pszDesc,
508 pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
509 rc = VERR_IOM_IOPORT_IPE_1;
510 break;
511 }
512
513 i = iFirst + (iEnd - iFirst) / 2;
514 }
515
516#ifdef VBOX_STRICT
517 /*
518 * Assert table sanity.
519 */
520 AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
521 AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
522
523 RTIOPORT uPortPrev = paEntries[0].uLastPort;
[80960]524 for (i = 1; i < cEntries - 1; i++)
[80641]525 {
526 AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
527 AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
528 AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
[82277]529 AssertMsg(paEntries[i].uLastPort - paEntries[i].uFirstPort + 1 == pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts,
530 ("%u: %#x %#x..%#x -> %u, expected %u\n", i, uPortPrev, paEntries[i].uFirstPort, paEntries[i].uLastPort,
531 paEntries[i].uLastPort - paEntries[i].uFirstPort + 1, pVM->iom.s.paIoPortRegs[paEntries[i].idx].cPorts));
[80641]532 uPortPrev = paEntries[i].uLastPort;
533 }
534#endif
535 }
536 else
537 {
538 AssertFailed();
539 rc = VERR_IOM_IOPORTS_NOT_MAPPED;
540 }
541
542 IOM_UNLOCK_EXCL(pVM);
543 return rc;
544}
545
546
[80649]547/**
[81375]548 * Validates @a hIoPorts, making sure it belongs to @a pDevIns.
549 *
550 * @returns VBox status code.
551 * @param pVM The cross context VM structure.
552 * @param pDevIns The device which allegedly owns @a hIoPorts.
553 * @param hIoPorts The handle to validate.
554 */
555VMMR3_INT_DECL(int) IOMR3IoPortValidateHandle(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
556{
557 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
558 AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc), VERR_IOM_INVALID_IOPORT_HANDLE);
559 PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
560 AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
561 return VINF_SUCCESS;
562}
563
564
565/**
[81564]566 * Gets the mapping address of I/O ports @a hIoPorts.
567 *
568 * @returns Mapping address if mapped, UINT32_MAX if not mapped or invalid
569 * input.
570 * @param pVM The cross context VM structure.
571 * @param pDevIns The device which allegedly owns @a hRegion.
572 * @param hIoPorts The handle to I/O port region.
573 */
574VMMR3_INT_DECL(uint32_t) IOMR3IoPortGetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
575{
576 AssertPtrReturn(pDevIns, UINT32_MAX);
[81702]577 AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc), UINT32_MAX);
[81564]578 IOMIOPORTENTRYR3 volatile * const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
579 AssertReturn(pRegEntry->pDevIns == pDevIns, UINT32_MAX);
580 for (uint32_t iTry = 0; ; iTry++)
581 {
582 bool fMapped = pRegEntry->fMapped;
583 RTIOPORT uPort = pRegEntry->uPort;
584 if ( ( ASMAtomicReadBool(&pRegEntry->fMapped) == fMapped
585 && uPort == pRegEntry->uPort)
586 || iTry > 1024)
587 return fMapped ? uPort : UINT32_MAX;
588 ASMNopPause();
589 }
590}
591
592
593/**
[1]594 * Display all registered I/O port ranges.
595 *
[58122]596 * @param pVM The cross context VM structure.
[1]597 * @param pHlp The info helpers.
598 * @param pszArgs Arguments, ignored.
599 */
[81156]600DECLCALLBACK(void) iomR3IoPortInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
[1]601{
[82311]602 RT_NOREF(pszArgs);
603
[81056]604 /* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
605 pHlp->pfnPrintf(pHlp,
606 "I/O port registrations: %u (%u allocated)\n"
607 " ## Ctx Ports Mapping PCI Description\n",
608 pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc);
609 PIOMIOPORTENTRYR3 paRegs = pVM->iom.s.paIoPortRegs;
610 for (uint32_t i = 0; i < pVM->iom.s.cIoPortRegs; i++)
611 {
612 const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
613 : paRegs[i].fRawMode ? "+C " : " ";
614 if (paRegs[i].fMapped && paRegs[i].pPciDev)
615 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
616 paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1,
617 paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
618 else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
619 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
620 paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1, paRegs[i].pszDesc);
621 else if (paRegs[i].pPciDev)
622 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
623 paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
624 else
625 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped %s\n",
626 paRegs[i].idxSelf, pszRing, paRegs[i].cPorts, paRegs[i].pszDesc);
627 }
[1]628}
629
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