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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 96407

Last change on this file since 96407 was 96407, checked in by vboxsync, 22 months ago
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1	/* $Id: HM.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
29	*
30	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
31	* extensions.
32	*
33	* {summary of what HM does}
34	*
35	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
36	* however that was cumbersome to write and parse for such a central component,
37	* so it was shortened to HM when refactoring the code in the 4.3 development
38	* cycle.
39	*
40	* {add sections with more details}
41	*
42	* @sa @ref grp_hm
43	*/
44
45
46	/*********************************************************************************************************************************
47	* Header Files *
48	*********************************************************************************************************************************/
49	#define LOG_GROUP LOG_GROUP_HM
50	#define VMCPU_INCL_CPUM_GST_CTX
51	#include <VBox/vmm/cpum.h>
52	#include <VBox/vmm/stam.h>
53	#include <VBox/vmm/em.h>
54	#include <VBox/vmm/pdmapi.h>
55	#include <VBox/vmm/pgm.h>
56	#include <VBox/vmm/ssm.h>
57	#include <VBox/vmm/gim.h>
58	#include <VBox/vmm/gcm.h>
59	#include <VBox/vmm/trpm.h>
60	#include <VBox/vmm/dbgf.h>
61	#include <VBox/vmm/iom.h>
62	#include <VBox/vmm/iem.h>
63	#include <VBox/vmm/selm.h>
64	#include <VBox/vmm/nem.h>
65	#include <VBox/vmm/hm_vmx.h>
66	#include <VBox/vmm/hm_svm.h>
67	#include "HMInternal.h"
68	#include <VBox/vmm/vmcc.h>
69	#include <VBox/err.h>
70	#include <VBox/param.h>
71
72	#include <iprt/assert.h>
73	#include <VBox/log.h>
74	#include <iprt/asm.h>
75	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
76	# include <iprt/asm-amd64-x86.h>
77	#endif
78	#include <iprt/env.h>
79	#include <iprt/thread.h>
80
81
82	/*********************************************************************************************************************************
83	* Defined Constants And Macros *
84	*********************************************************************************************************************************/
85	/** @def HMVMX_REPORT_FEAT
86	* Reports VT-x feature to the release log.
87	*
88	* @param a_uAllowed1 Mask of allowed-1 feature bits.
89	* @param a_uAllowed0 Mask of allowed-0 feature bits.
90	* @param a_StrDesc The description string to report.
91	* @param a_Featflag Mask of the feature to report.
92	*/
93	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
94	do { \
95	if ((a_uAllowed1) & (a_Featflag)) \
96	{ \
97	if ((a_uAllowed0) & (a_Featflag)) \
98	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
99	else \
100	LogRel(("HM: " a_StrDesc "\n")); \
101	} \
102	else \
103	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
104	} while (0)
105
106	/** @def HMVMX_REPORT_ALLOWED_FEAT
107	* Reports an allowed VT-x feature to the release log.
108	*
109	* @param a_uAllowed1 Mask of allowed-1 feature bits.
110	* @param a_StrDesc The description string to report.
111	* @param a_FeatFlag Mask of the feature to report.
112	*/
113	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
114	do { \
115	if ((a_uAllowed1) & (a_FeatFlag)) \
116	LogRel(("HM: " a_StrDesc "\n")); \
117	else \
118	LogRel(("HM: " a_StrDesc " not supported\n")); \
119	} while (0)
120
121	/** @def HMVMX_REPORT_MSR_CAP
122	* Reports MSR feature capability.
123	*
124	* @param a_MsrCaps Mask of MSR feature bits.
125	* @param a_StrDesc The description string to report.
126	* @param a_fCap Mask of the feature to report.
127	*/
128	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
129	do { \
130	if ((a_MsrCaps) & (a_fCap)) \
131	LogRel(("HM: " a_StrDesc "\n")); \
132	} while (0)
133
134	/** @def HMVMX_LOGREL_FEAT
135	* Dumps a feature flag from a bitmap of features to the release log.
136	*
137	* @param a_fVal The value of all the features.
138	* @param a_fMask The specific bitmask of the feature.
139	*/
140	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
141	do { \
142	if ((a_fVal) & (a_fMask)) \
143	LogRel(("HM: %s\n", #a_fMask)); \
144	} while (0)
145
146
147	/*********************************************************************************************************************************
148	* Internal Functions *
149	*********************************************************************************************************************************/
150	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
151	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
152	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
153	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
154	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
155	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static int hmR3InitFinalizeR3(PVM pVM);
157	static int hmR3InitFinalizeR0(PVM pVM);
158	static int hmR3InitFinalizeR0Intel(PVM pVM);
159	static int hmR3InitFinalizeR0Amd(PVM pVM);
160	static int hmR3TermCPU(PVM pVM);
161
162
163	#ifdef VBOX_WITH_STATISTICS
164	/**
165	* Returns the name of the hardware exception.
166	*
167	* @returns The name of the hardware exception.
168	* @param uVector The exception vector.
169	*/
170	static const char *hmR3GetXcptName(uint8_t uVector)
171	{
172	switch (uVector)
173	{
174	case X86_XCPT_DE: return "#DE";
175	case X86_XCPT_DB: return "#DB";
176	case X86_XCPT_NMI: return "#NMI";
177	case X86_XCPT_BP: return "#BP";
178	case X86_XCPT_OF: return "#OF";
179	case X86_XCPT_BR: return "#BR";
180	case X86_XCPT_UD: return "#UD";
181	case X86_XCPT_NM: return "#NM";
182	case X86_XCPT_DF: return "#DF";
183	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
184	case X86_XCPT_TS: return "#TS";
185	case X86_XCPT_NP: return "#NP";
186	case X86_XCPT_SS: return "#SS";
187	case X86_XCPT_GP: return "#GP";
188	case X86_XCPT_PF: return "#PF";
189	case X86_XCPT_MF: return "#MF";
190	case X86_XCPT_AC: return "#AC";
191	case X86_XCPT_MC: return "#MC";
192	case X86_XCPT_XF: return "#XF";
193	case X86_XCPT_VE: return "#VE";
194	case X86_XCPT_CP: return "#CP";
195	case X86_XCPT_VC: return "#VC";
196	case X86_XCPT_SX: return "#SX";
197	}
198	return "Reserved";
199	}
200	#endif /* VBOX_WITH_STATISTICS */
201
202
203	/**
204	* Initializes the HM.
205	*
206	* This is the very first component to really do init after CFGM so that we can
207	* establish the predominant execution engine for the VM prior to initializing
208	* other modules. It takes care of NEM initialization if needed (HM disabled or
209	* not available in HW).
210	*
211	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
212	* hypervisor API via NEM, and then back on raw-mode if that isn't available
213	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
214	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
215	* X, OS/2 and others).
216	*
217	* Note that a lot of the set up work is done in ring-0 and thus postponed till
218	* the ring-3 and ring-0 callback to HMR3InitCompleted.
219	*
220	* @returns VBox status code.
221	* @param pVM The cross context VM structure.
222	*
223	* @remarks Be careful with what we call here, since most of the VMM components
224	* are uninitialized.
225	*/
226	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
227	{
228	LogFlowFunc(("\n"));
229
230	/*
231	* Assert alignment and sizes.
232	*/
233	AssertCompileMemberAlignment(VM, hm.s, 32);
234	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
235
236	/*
237	* Register the saved state data unit.
238	*/
239	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
240	NULL, NULL, NULL,
241	NULL, hmR3Save, NULL,
242	NULL, hmR3Load, NULL);
243	if (RT_FAILURE(rc))
244	return rc;
245
246	/*
247	* Read configuration.
248	*/
249	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
250
251	/*
252	* Validate the HM settings.
253	*/
254	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
255	"HMForced" /* implied 'true' these days */
256	"\|UseNEMInstead"
257	"\|FallbackToNEM"
258	"\|FallbackToIEM"
259	"\|EnableNestedPaging"
260	"\|EnableUX"
261	"\|EnableLargePages"
262	"\|EnableVPID"
263	"\|IBPBOnVMExit"
264	"\|IBPBOnVMEntry"
265	"\|SpecCtrlByHost"
266	"\|L1DFlushOnSched"
267	"\|L1DFlushOnVMEntry"
268	"\|MDSClearOnSched"
269	"\|MDSClearOnVMEntry"
270	"\|TPRPatchingEnabled"
271	"\|64bitEnabled"
272	"\|Exclusive"
273	"\|MaxResumeLoops"
274	"\|VmxPleGap"
275	"\|VmxPleWindow"
276	"\|VmxLbr"
277	"\|UseVmxPreemptTimer"
278	"\|SvmPauseFilter"
279	"\|SvmPauseFilterThreshold"
280	"\|SvmVirtVmsaveVmload"
281	"\|SvmVGif"
282	"\|LovelyMesaDrvWorkaround"
283	"\|MissingOS2TlbFlushWorkaround",
284	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
285	if (RT_FAILURE(rc))
286	return rc;
287
288	/** @cfgm{/HM/HMForced, bool, false}
289	* Forces hardware virtualization, no falling back on raw-mode. HM must be
290	* enabled, i.e. /HMEnabled must be true. */
291	bool const fHMForced = true;
292	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
293	AssertRelease(pVM->fHMEnabled);
294	#else
295	AssertRelease(!pVM->fHMEnabled);
296	#endif
297
298	/** @cfgm{/HM/UseNEMInstead, bool, true}
299	* Don't use HM, use NEM instead. */
300	bool fUseNEMInstead = false;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
302	AssertRCReturn(rc, rc);
303	if (fUseNEMInstead && pVM->fHMEnabled)
304	{
305	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
306	pVM->fHMEnabled = false;
307	}
308
309	/** @cfgm{/HM/FallbackToNEM, bool, true}
310	* Enables fallback on NEM. */
311	bool fFallbackToNEM = true;
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
316	* Enables fallback on NEM. */
317	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
318	bool fFallbackToIEM = false;
319	#else
320	bool fFallbackToIEM = true;
321	#endif
322	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
323	AssertRCReturn(rc, rc);
324
325	/** @cfgm{/HM/EnableNestedPaging, bool, false}
326	* Enables nested paging (aka extended page tables). */
327	bool fAllowNestedPaging = false;
328	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
329	AssertRCReturn(rc, rc);
330
331	/** @cfgm{/HM/EnableUX, bool, true}
332	* Enables the VT-x unrestricted execution feature. */
333	bool fAllowUnrestricted = true;
334	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/EnableLargePages, bool, false}
338	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
339	* page table walking and maybe better TLB hit rate in some cases. */
340	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
341	AssertRCReturn(rc, rc);
342
343	/** @cfgm{/HM/EnableVPID, bool, false}
344	* Enables the VT-x VPID feature. */
345	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
346	AssertRCReturn(rc, rc);
347
348	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
349	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
350	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
351	AssertRCReturn(rc, rc);
352
353	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
354	* Enables AMD64 cpu features.
355	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
356	* already have the support. */
357	#ifdef VBOX_WITH_64_BITS_GUESTS
358	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
359	AssertLogRelRCReturn(rc, rc);
360	#else
361	pVM->hm.s.fAllow64BitGuestsCfg = false;
362	#endif
363
364	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
365	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
366	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
367	* latest PAUSE instruction to be start of a new PAUSE loop.
368	*/
369	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
373	* The pause-filter exiting window in TSC ticks. When the number of ticks
374	* between the current PAUSE instruction and first PAUSE of a loop exceeds
375	* VmxPleWindow, a VM-exit is triggered.
376	*
377	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
378	*/
379	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
380	AssertRCReturn(rc, rc);
381
382	/** @cfgm{/HM/VmxLbr, bool, false}
383	* Whether to enable LBR for the guest. This is disabled by default as it's only
384	* useful while debugging and enabling it causes a noticeable performance hit. */
385	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
386	AssertRCReturn(rc, rc);
387
388	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
389	* A counter that is decrement each time a PAUSE instruction is executed by the
390	* guest. When the counter is 0, a \#VMEXIT is triggered.
391	*
392	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
393	*/
394	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
398	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
399	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
400	* PauseFilter count is reset to its initial value. However, if PAUSE is
401	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
402	* be triggered.
403	*
404	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
405	* activated.
406	*/
407	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
408	AssertRCReturn(rc, rc);
409
410	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
411	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
412	* available. */
413	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
414	AssertRCReturn(rc, rc);
415
416	/** @cfgm{/HM/SvmVGif, bool, true}
417	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
418	* if it's available. */
419	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
420	AssertRCReturn(rc, rc);
421
422	/** @cfgm{/HM/SvmLbrVirt, bool, false}
423	* Whether to make use of the LBR virtualization feature of the CPU if it's
424	* available. This is disabled by default as it's only useful while debugging
425	* and enabling it causes a small hit to performance. */
426	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
427	AssertRCReturn(rc, rc);
428
429	/** @cfgm{/HM/Exclusive, bool}
430	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
431	* global init for each host CPU. If false, we do local init each time we wish
432	* to execute guest code.
433	*
434	* On Windows, default is false due to the higher risk of conflicts with other
435	* hypervisors.
436	*
437	* On Mac OS X, this setting is ignored since the code does not handle local
438	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
439	*/
440	#if defined(RT_OS_DARWIN)
441	pVM->hm.s.fGlobalInit = true;
442	#else
443	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
444	# if defined(RT_OS_WINDOWS)
445	false
446	# else
447	true
448	# endif
449	);
450	AssertLogRelRCReturn(rc, rc);
451	#endif
452
453	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
454	* The number of times to resume guest execution before we forcibly return to
455	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
456	* determines the default value. */
457	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
458	AssertLogRelRCReturn(rc, rc);
459
460	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
461	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
462	* available. */
463	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
464	AssertLogRelRCReturn(rc, rc);
465
466	/** @cfgm{/HM/IBPBOnVMExit, bool}
467	* Costly paranoia setting. */
468	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
469	AssertLogRelRCReturn(rc, rc);
470
471	/** @cfgm{/HM/IBPBOnVMEntry, bool}
472	* Costly paranoia setting. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
474	AssertLogRelRCReturn(rc, rc);
475
476	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
477	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
478	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
479	AssertLogRelRCReturn(rc, rc);
480
481	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
482	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
483	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
484	AssertLogRelRCReturn(rc, rc);
485
486	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
487	if (pVM->hm.s.fL1dFlushOnVmEntry)
488	pVM->hm.s.fL1dFlushOnSched = false;
489
490	/** @cfgm{/HM/SpecCtrlByHost, bool}
491	* Another expensive paranoia setting. */
492	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
493	AssertLogRelRCReturn(rc, rc);
494
495	/** @cfgm{/HM/MDSClearOnSched, bool, true}
496	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
497	* ignored on CPUs that aren't affected. */
498	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
499	AssertLogRelRCReturn(rc, rc);
500
501	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
502	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
503	* ignored on CPUs that aren't affected. */
504	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
505	AssertLogRelRCReturn(rc, rc);
506
507	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
508	if (pVM->hm.s.fMdsClearOnVmEntry)
509	pVM->hm.s.fMdsClearOnSched = false;
510
511	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
512	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
513	* the hypervisor it is running under. */
514	bool fMesaWorkaround;
515	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
516	AssertLogRelRCReturn(rc, rc);
517	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
518	{
519	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
520	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
521	}
522
523	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
524	* Workaround OS/2 not flushing the TLB after page directory and page table
525	* modifications when returning to protected mode from a real mode call
526	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
527	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
528	AssertLogRelRCReturn(rc, rc);
529
530	/*
531	* Check if VT-x or AMD-v support according to the users wishes.
532	*/
533	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
534	* VERR_SVM_IN_USE. */
535	if (pVM->fHMEnabled)
536	{
537	uint32_t fCaps;
538	rc = SUPR3QueryVTCaps(&fCaps);
539	if (RT_SUCCESS(rc))
540	{
541	if (fCaps & SUPVTCAPS_AMD_V)
542	{
543	pVM->hm.s.svm.fSupported = true;
544	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
545	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
546	}
547	else if (fCaps & SUPVTCAPS_VT_X)
548	{
549	const char *pszWhy;
550	rc = SUPR3QueryVTxSupported(&pszWhy);
551	if (RT_SUCCESS(rc))
552	{
553	pVM->hm.s.vmx.fSupported = true;
554	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
555	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
556	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
557	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
558	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
559	}
560	else
561	{
562	/*
563	* Before failing, try fallback to NEM if we're allowed to do that.
564	*/
565	pVM->fHMEnabled = false;
566	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
567	if (fFallbackToNEM)
568	{
569	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
570	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
571
572	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
573	if ( RT_SUCCESS(rc2)
574	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
575	rc = VINF_SUCCESS;
576	}
577	if (RT_FAILURE(rc))
578	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
579	}
580	}
581	else
582	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
583	VERR_INTERNAL_ERROR_5);
584
585	/*
586	* Disable nested paging and unrestricted guest execution now if they're
587	* configured so that CPUM can make decisions based on our configuration.
588	*/
589	if ( fAllowNestedPaging
590	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
591	{
592	pVM->hm.s.fNestedPagingCfg = true;
593	if (fCaps & SUPVTCAPS_VT_X)
594	{
595	if ( fAllowUnrestricted
596	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
597	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
598	else
599	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
600	}
601	}
602	else
603	Assert(!pVM->hm.s.fNestedPagingCfg);
604	}
605	else
606	{
607	const char *pszMsg;
608	switch (rc)
609	{
610	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
611	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
612	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
613	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
614	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
615	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
616	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
617	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
618	default:
619	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
620	}
621
622	/*
623	* Before failing, try fallback to NEM if we're allowed to do that.
624	*/
625	pVM->fHMEnabled = false;
626	if (fFallbackToNEM)
627	{
628	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
629	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
630	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
631	if ( RT_SUCCESS(rc2)
632	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
633	{
634	rc = VINF_SUCCESS;
635
636	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
637	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
638	}
639	}
640
641	/*
642	* Then try fall back on IEM if NEM isn't available and we're allowed to.
643	*/
644	if (RT_FAILURE(rc))
645	{
646	if ( fFallbackToIEM
647	&& (!fFallbackToNEM \|\| rc == VERR_NEM_NOT_AVAILABLE \|\| rc == VERR_SUP_DRIVERLESS))
648	{
649	LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
650	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
651	#ifdef VBOX_WITH_PGM_NEM_MODE
652	PGMR3EnableNemMode(pVM);
653	#endif
654	}
655	else
656	return VM_SET_ERROR(pVM, rc, pszMsg);
657	}
658	}
659	}
660	else
661	{
662	/*
663	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
664	*/
665	rc = VERR_NEM_NOT_AVAILABLE;
666	if (fUseNEMInstead)
667	{
668	rc = NEMR3Init(pVM, false /fFallback/, true);
669	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
670	if (RT_SUCCESS(rc))
671	{
672	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
673	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
674	}
675	else if (!fFallbackToIEM \|\| rc != VERR_NEM_NOT_AVAILABLE)
676	return rc;
677	}
678
679	if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
680	{
681	LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
682	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
683	#ifdef VBOX_WITH_PGM_NEM_MODE
684	PGMR3EnableNemMode(pVM);
685	#endif
686	}
687
688	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
689	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
690	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
691	}
692
693	if (pVM->fHMEnabled)
694	{
695	/*
696	* Register info handlers now that HM is used for sure.
697	*/
698	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
699	AssertRCReturn(rc, rc);
700
701	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
702	DBGFINFO_FLAGS_ALL_EMTS);
703	AssertRCReturn(rc, rc);
704
705	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
706	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
707	AssertRCReturn(rc, rc);
708
709	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
710	AssertRCReturn(rc, rc);
711	}
712
713	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
714	return VINF_SUCCESS;
715	}
716
717
718	/**
719	* Initializes HM components after ring-3 phase has been fully initialized.
720	*
721	* @returns VBox status code.
722	* @param pVM The cross context VM structure.
723	*/
724	static int hmR3InitFinalizeR3(PVM pVM)
725	{
726	LogFlowFunc(("\n"));
727
728	if (!HMIsEnabled(pVM))
729	return VINF_SUCCESS;
730
731	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
732	{
733	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
734	pVCpu->hm.s.fActive = false;
735	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
736	pVCpu->hm.s.fGCMTrapXcptDE = GCMShouldTrapXcptDE(pVCpu); /* Is safe to call now since GCMR3Init() has completed. */
737	}
738
739	#if defined(RT_ARCH_AMD64) \|\|defined(RT_ARCH_X86)
740	/*
741	* Check if L1D flush is needed/possible.
742	*/
743	if ( !g_CpumHostFeatures.s.fFlushCmd
744	\|\| g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
745	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
746	\|\| g_CpumHostFeatures.s.fArchVmmNeedNotFlushL1d
747	\|\| g_CpumHostFeatures.s.fArchRdclNo)
748	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
749
750	/*
751	* Check if MDS flush is needed/possible.
752	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
753	*/
754	if ( !g_CpumHostFeatures.s.fMdsClear
755	\|\| g_CpumHostFeatures.s.fArchMdsNo)
756	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
757	else if ( ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
758	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
759	\|\| ( g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
760	&& g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
761	{
762	if (!pVM->hm.s.fMdsClearOnSched)
763	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
764	pVM->hm.s.fMdsClearOnVmEntry = false;
765	}
766	else if ( g_CpumHostFeatures.s.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
767	\|\| g_CpumHostFeatures.s.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
768	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
769	#endif
770
771	/*
772	* Statistics.
773	*/
774	#ifdef VBOX_WITH_STATISTICS
775	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
776	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
777	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
778	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
779	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
780	#endif
781
782	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
783	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
784	#else
785	bool const fCpuSupportsVmx = false;
786	#endif
787	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
788	{
789	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
790	PHMCPU pHmCpu = &pVCpu->hm.s;
791	int rc;
792
793	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
794	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
795	AssertRC(rc); \
796	} while (0)
797	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
798	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
799
800	#ifdef VBOX_WITH_STATISTICS
801
802	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
803	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
804	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
805	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
806	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
807	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
808	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
809	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
810	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
811	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
812	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
813	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
814	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
815	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
816	# ifdef HM_PROFILE_EXIT_DISPATCH
817	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
818	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
819	# endif
820	#endif
821	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
822
823	#ifdef VBOX_WITH_STATISTICS
824	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
825	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
826	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
827	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
828	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
829	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
830	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
831	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
832	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
833	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
834	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
835	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
836	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
837	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
838	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
839	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
840	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
841	#endif
842	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
843	if (fCpuSupportsVmx)
844	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
845	#ifdef VBOX_WITH_STATISTICS
846	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
847	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
848	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
849	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
850	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
851	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
852	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
853	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
854	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
855	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
856	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
857	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
858	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
859	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
860	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
861	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
862	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
863	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
864	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
865	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
866	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
867	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
868	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
869	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
870	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
871	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
872	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
873	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
874	#endif
875	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
876	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
877	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
878	#ifdef VBOX_WITH_STATISTICS
879	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
880	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
881	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
882
883	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
884	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
885	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
886	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
887	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
888	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
889	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
890	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
891	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
892	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
893	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
894	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
895	#endif
896	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
897	#ifdef VBOX_WITH_STATISTICS
898	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
899
900	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
901	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
902	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
903	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
904	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
905	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
906
907	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
908	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
909	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
910	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
911	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
912	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
913	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
914	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
915	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
916	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
917	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
918	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
919	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
920	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
921	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
922
923	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
924	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
925	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
926
927	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
928	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
929	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
930
931	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
932	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
933	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
934	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
935
936	if (fCpuSupportsVmx)
937	{
938	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
939	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
940	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
941	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
942	}
943
944	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
945	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
946	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
947
948	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
949	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
950	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
951
952	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
953	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
954	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
955	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
956	#endif
957	if (fCpuSupportsVmx)
958	{
959	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
960	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
961	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
962	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
963	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
964	}
965	#ifdef VBOX_WITH_STATISTICS
966	/*
967	* Guest Exit reason stats.
968	*/
969	if (fCpuSupportsVmx)
970	{
971	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
972	{
973	const char *pszExitName = HMGetVmxExitName(j);
974	if (pszExitName)
975	{
976	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
977	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
978	AssertRCReturn(rc, rc);
979	}
980	}
981	}
982	else
983	{
984	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
985	{
986	const char *pszExitName = HMGetSvmExitName(j);
987	if (pszExitName)
988	{
989	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
990	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
991	AssertRC(rc);
992	}
993	}
994	}
995	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
996
997	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
998	/*
999	* Nested-guest VM-exit reason stats.
1000	*/
1001	if (fCpuSupportsVmx)
1002	{
1003	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1004	{
1005	const char *pszExitName = HMGetVmxExitName(j);
1006	if (pszExitName)
1007	{
1008	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1009	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
1010	AssertRC(rc);
1011	}
1012	}
1013	}
1014	else
1015	{
1016	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1017	{
1018	const char *pszExitName = HMGetSvmExitName(j);
1019	if (pszExitName)
1020	{
1021	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1022	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
1023	AssertRC(rc);
1024	}
1025	}
1026	}
1027	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
1028	#endif
1029
1030	/*
1031	* Injected interrupts stats.
1032	*/
1033	char szDesc[64];
1034	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1035	{
1036	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1037	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1038	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1039	AssertRC(rc);
1040	}
1041
1042	/*
1043	* Injected exception stats.
1044	*/
1045	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1046	{
1047	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1048	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1049	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1050	AssertRC(rc);
1051	}
1052
1053	#endif /* VBOX_WITH_STATISTICS */
1054	#undef HM_REG_COUNTER
1055	#undef HM_REG_PROFILE
1056	#undef HM_REG_STAT
1057	}
1058
1059	return VINF_SUCCESS;
1060	}
1061
1062
1063	/**
1064	* Called when a init phase has completed.
1065	*
1066	* @returns VBox status code.
1067	* @param pVM The cross context VM structure.
1068	* @param enmWhat The phase that completed.
1069	*/
1070	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1071	{
1072	switch (enmWhat)
1073	{
1074	case VMINITCOMPLETED_RING3:
1075	return hmR3InitFinalizeR3(pVM);
1076	case VMINITCOMPLETED_RING0:
1077	return hmR3InitFinalizeR0(pVM);
1078	default:
1079	return VINF_SUCCESS;
1080	}
1081	}
1082
1083
1084	/**
1085	* Turns off normal raw mode features.
1086	*
1087	* @param pVM The cross context VM structure.
1088	*/
1089	static void hmR3DisableRawMode(PVM pVM)
1090	{
1091	/** @todo r=bird: HM shouldn't be doing this crap. */
1092	/* Reinit the paging mode to force the new shadow mode. */
1093	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1094	{
1095	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1096	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1097	}
1098	}
1099
1100
1101	/**
1102	* Initialize VT-x or AMD-V.
1103	*
1104	* @returns VBox status code.
1105	* @param pVM The cross context VM structure.
1106	*/
1107	static int hmR3InitFinalizeR0(PVM pVM)
1108	{
1109	int rc;
1110
1111	if (!HMIsEnabled(pVM))
1112	return VINF_SUCCESS;
1113
1114	/*
1115	* Hack to allow users to work around broken BIOSes that incorrectly set
1116	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1117	*/
1118	if ( !pVM->hm.s.vmx.fSupported
1119	&& !pVM->hm.s.svm.fSupported
1120	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1121	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1122	{
1123	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1124	pVM->hm.s.svm.fSupported = true;
1125	pVM->hm.s.svm.fIgnoreInUseError = true;
1126	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1127	}
1128
1129	/*
1130	* Report ring-0 init errors.
1131	*/
1132	if ( !pVM->hm.s.vmx.fSupported
1133	&& !pVM->hm.s.svm.fSupported)
1134	{
1135	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1136	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1137	switch (pVM->hm.s.ForR3.rcInit)
1138	{
1139	case VERR_VMX_IN_VMX_ROOT_MODE:
1140	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1141	case VERR_VMX_NO_VMX:
1142	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1143	case VERR_VMX_MSR_VMX_DISABLED:
1144	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1145	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1146	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1147	case VERR_VMX_MSR_LOCKING_FAILED:
1148	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1149	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1150	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1151	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1152	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1153
1154	case VERR_SVM_IN_USE:
1155	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1156	case VERR_SVM_NO_SVM:
1157	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1158	case VERR_SVM_DISABLED:
1159	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1160	}
1161	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1162	}
1163
1164	/*
1165	* Enable VT-x or AMD-V on all host CPUs.
1166	*/
1167	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1168	if (RT_FAILURE(rc))
1169	{
1170	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1171	HMR3CheckError(pVM, rc);
1172	return rc;
1173	}
1174
1175	/*
1176	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1177	* (Main should have taken care of this already)
1178	*/
1179	if (!PDMHasIoApic(pVM))
1180	{
1181	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1182	pVM->hm.s.fTprPatchingAllowed = false;
1183	}
1184
1185	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1186	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1187	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1188
1189	/*
1190	* Do the vendor specific initialization
1191	*
1192	* Note! We disable release log buffering here since we're doing relatively
1193	* lot of logging and doesn't want to hit the disk with each LogRel
1194	* statement.
1195	*/
1196	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1197	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1198	if (pVM->hm.s.vmx.fSupported)
1199	rc = hmR3InitFinalizeR0Intel(pVM);
1200	else
1201	rc = hmR3InitFinalizeR0Amd(pVM);
1202	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1203	: "HM: VT-x/AMD-V init method: Local\n"));
1204	RTLogRelSetBuffering(fOldBuffered);
1205	pVM->hm.s.fInitialized = true;
1206
1207	return rc;
1208	}
1209
1210
1211	/**
1212	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1213	*/
1214	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1215	{
1216	NOREF(pVM);
1217	NOREF(pvAllocation);
1218	NOREF(GCPhysAllocation);
1219	}
1220
1221
1222	/**
1223	* Returns a description of the VMCS (and associated regions') memory type given the
1224	* IA32_VMX_BASIC MSR.
1225	*
1226	* @returns The descriptive memory type.
1227	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1228	*/
1229	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1230	{
1231	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1232	switch (uMemType)
1233	{
1234	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1235	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1236	}
1237	return "Unknown";
1238	}
1239
1240
1241	/**
1242	* Returns a single-line description of all the activity-states supported by the CPU
1243	* given the IA32_VMX_MISC MSR.
1244	*
1245	* @returns All supported activity states.
1246	* @param uMsrMisc IA32_VMX_MISC MSR value.
1247	*/
1248	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1249	{
1250	static const char * const s_apszActStates[] =
1251	{
1252	"",
1253	" ( HLT )",
1254	" ( SHUTDOWN )",
1255	" ( HLT SHUTDOWN )",
1256	" ( SIPI_WAIT )",
1257	" ( HLT SIPI_WAIT )",
1258	" ( SHUTDOWN SIPI_WAIT )",
1259	" ( HLT SHUTDOWN SIPI_WAIT )"
1260	};
1261	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1262	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1263	return s_apszActStates[idxActStates];
1264	}
1265
1266
1267	/**
1268	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1269	*
1270	* @param fFeatMsr The feature control MSR value.
1271	*/
1272	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1273	{
1274	uint64_t const val = fFeatMsr;
1275	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1276	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1277	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1278	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1279	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1280	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1281	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1282	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1283	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1284	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1285	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1286	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1287	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1288	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1289	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1290	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1291	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1292	}
1293
1294
1295	/**
1296	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1297	*
1298	* @param uBasicMsr The VMX basic MSR value.
1299	*/
1300	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1301	{
1302	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1303	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1304	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1305	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1306	"< 4 GB" : "None"));
1307	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1308	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1309	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1310	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1311	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1312	}
1313
1314
1315	/**
1316	* Reports MSR_IA32_PINBASED_CTLS to the log.
1317	*
1318	* @param pVmxMsr Pointer to the VMX MSR.
1319	*/
1320	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1321	{
1322	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1323	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1324	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1330	}
1331
1332
1333	/**
1334	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1335	*
1336	* @param pVmxMsr Pointer to the VMX MSR.
1337	*/
1338	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1339	{
1340	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1341	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1342	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1355	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1357	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1358	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1359	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1365	}
1366
1367
1368	/**
1369	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1370	*
1371	* @param pVmxMsr Pointer to the VMX MSR.
1372	*/
1373	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1374	{
1375	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1376	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1377	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1389	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1405	}
1406
1407
1408	/**
1409	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1410	*
1411	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1412	*/
1413	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1414	{
1415	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1416	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1417	}
1418
1419
1420	/**
1421	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1422	*
1423	* @param pVmxMsr Pointer to the VMX MSR.
1424	*/
1425	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1426	{
1427	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1428	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1429	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1432	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1433	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1434	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1435	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1436	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1437	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1438	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1439	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1440	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1441	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1442	}
1443
1444
1445	/**
1446	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1447	*
1448	* @param pVmxMsr Pointer to the VMX MSR.
1449	*/
1450	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1451	{
1452	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1453	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1454	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1455	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1456	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1457	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1458	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1459	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1460	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1461	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1462	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1463	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1464	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1465	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1466	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1467	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1468	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1469	}
1470
1471
1472	/**
1473	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1474	*
1475	* @param fCaps The VMX EPT/VPID capability MSR value.
1476	*/
1477	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1478	{
1479	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1480	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1481	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1482	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1483	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1484	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1485	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1486	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1487	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1488	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1489	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1490	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1491	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1492	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1493	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1494	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1495	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1496	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1497	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1498	}
1499
1500
1501	/**
1502	* Reports MSR_IA32_VMX_MISC MSR to the log.
1503	*
1504	* @param pVM Pointer to the VM.
1505	* @param fMisc The VMX misc. MSR value.
1506	*/
1507	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1508	{
1509	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1510	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1511	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1512	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1513	else
1514	{
1515	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1516	pVM->hm.s.vmx.cPreemptTimerShift));
1517	}
1518	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1519	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1520	hmR3VmxGetActivityStateAllDesc(fMisc)));
1521	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1522	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1523	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1524	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1525	VMX_MISC_MAX_MSRS(fMisc)));
1526	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1527	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1528	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1529	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1530	}
1531
1532
1533	/**
1534	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1535	*
1536	* @param uVmcsEnum The VMX VMCS enum MSR value.
1537	*/
1538	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1539	{
1540	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1541	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1542	}
1543
1544
1545	/**
1546	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1547	*
1548	* @param uVmFunc The VMX VMFUNC MSR value.
1549	*/
1550	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1551	{
1552	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1553	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1554	}
1555
1556
1557	/**
1558	* Reports VMX CR0, CR4 fixed MSRs.
1559	*
1560	* @param pMsrs Pointer to the VMX MSRs.
1561	*/
1562	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1563	{
1564	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1565	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1566	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1567	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1568	}
1569
1570
1571	/**
1572	* Finish VT-x initialization (after ring-0 init).
1573	*
1574	* @returns VBox status code.
1575	* @param pVM The cross context VM structure.
1576	*/
1577	static int hmR3InitFinalizeR0Intel(PVM pVM)
1578	{
1579	int rc;
1580
1581	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1582	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1583
1584	LogRel(("HM: Using VT-x implementation 3.0\n"));
1585	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1586	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1587	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1588	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1589
1590	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1591	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1592
1593	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1594	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1595	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1596	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1597	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1598	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1599
1600	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1601	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1602
1603	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1604	{
1605	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1606	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1607	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1608	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1609	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1610	}
1611
1612	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1613	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1614	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1615	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1616	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1617	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1618	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1619
1620	#ifdef TODO_9217_VMCSINFO
1621	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1622	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1623	{
1624	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1625	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1626	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1627	}
1628	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1629	if (pVM->cpum.ro.GuestFeatures.fVmx)
1630	{
1631	LogRel(("HM: Nested-guest:\n"));
1632	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1633	{
1634	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1635	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1636	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1637	}
1638	}
1639	#endif
1640	#endif /* TODO_9217_VMCSINFO */
1641
1642	/*
1643	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1644	*/
1645	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1646	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1647	VERR_HM_IPE_1);
1648	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1649	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1650	&& pVM->hm.s.fNestedPagingCfg),
1651	VERR_HM_IPE_1);
1652
1653	/*
1654	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1655	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1656	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1657	*/
1658	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1659	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1660	{
1661	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1662	LogRel(("HM: Disabled RDTSCP\n"));
1663	}
1664
1665	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1666	{
1667	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1668	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1669	if (RT_SUCCESS(rc))
1670	{
1671	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1672	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1673	esp. Figure 20-5.*/
1674	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1675	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1676
1677	/* Bit set to 0 means software interrupts are redirected to the
1678	8086 program interrupt handler rather than switching to
1679	protected-mode handler. */
1680	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1681
1682	/* Allow all port IO, so that port IO instructions do not cause
1683	exceptions and would instead cause a VM-exit (based on VT-x's
1684	IO bitmap which we currently configure to always cause an exit). */
1685	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1686	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1687
1688	/*
1689	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1690	* page table used in real and protected mode without paging with EPT.
1691	*/
1692	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1693	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1694	{
1695	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1696	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1697	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1698	\| X86_PDE4M_G;
1699	}
1700
1701	/* We convert it here every time as PCI regions could be reconfigured. */
1702	if (PDMVmmDevHeapIsEnabled(pVM))
1703	{
1704	RTGCPHYS GCPhys;
1705	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1706	AssertRCReturn(rc, rc);
1707	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1708
1709	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1710	AssertRCReturn(rc, rc);
1711	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1712	}
1713	}
1714	else
1715	{
1716	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1717	pVM->hm.s.vmx.pRealModeTSS = NULL;
1718	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1719	return VMSetError(pVM, rc, RT_SRC_POS,
1720	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1721	}
1722	}
1723
1724	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1725	: "HM: Guest support: 32-bit only\n"));
1726
1727	/*
1728	* Call ring-0 to set up the VM.
1729	*/
1730	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1731	if (rc != VINF_SUCCESS)
1732	{
1733	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1734	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1735	{
1736	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1737	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1738	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1739	}
1740	HMR3CheckError(pVM, rc);
1741	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1742	}
1743
1744	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1745	LogRel(("HM: Enabled VMX\n"));
1746	pVM->hm.s.vmx.fEnabled = true;
1747
1748	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1749
1750	/*
1751	* Log configuration details.
1752	*/
1753	if (pVM->hm.s.fNestedPagingCfg)
1754	{
1755	LogRel(("HM: Enabled nested paging\n"));
1756	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1757	LogRel(("HM: EPT flush type = Single context\n"));
1758	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1759	LogRel(("HM: EPT flush type = All contexts\n"));
1760	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1761	LogRel(("HM: EPT flush type = Not supported\n"));
1762	else
1763	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1764
1765	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1766	LogRel(("HM: Enabled unrestricted guest execution\n"));
1767
1768	if (pVM->hm.s.fLargePages)
1769	{
1770	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1771	PGMSetLargePageUsage(pVM, true);
1772	LogRel(("HM: Enabled large page support\n"));
1773	}
1774	}
1775	else
1776	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1777
1778	if (pVM->hm.s.ForR3.vmx.fVpid)
1779	{
1780	LogRel(("HM: Enabled VPID\n"));
1781	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1782	LogRel(("HM: VPID flush type = Individual addresses\n"));
1783	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1784	LogRel(("HM: VPID flush type = Single context\n"));
1785	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1786	LogRel(("HM: VPID flush type = All contexts\n"));
1787	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1788	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1789	else
1790	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1791	}
1792	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1793	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1794
1795	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1796	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1797	else
1798	LogRel(("HM: Disabled VMX-preemption timer\n"));
1799
1800	if (pVM->hm.s.fVirtApicRegs)
1801	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1802
1803	if (pVM->hm.s.fPostedIntrs)
1804	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1805
1806	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1807	{
1808	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1809	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1810	}
1811
1812	return VINF_SUCCESS;
1813	}
1814
1815
1816	/**
1817	* Finish AMD-V initialization (after ring-0 init).
1818	*
1819	* @returns VBox status code.
1820	* @param pVM The cross context VM structure.
1821	*/
1822	static int hmR3InitFinalizeR0Amd(PVM pVM)
1823	{
1824	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1825
1826	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1827
1828	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1829	uint32_t u32Family;
1830	uint32_t u32Model;
1831	uint32_t u32Stepping;
1832	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1833	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1834	#endif
1835	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1836	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1837	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1838	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1839	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1840
1841	/*
1842	* Enumerate AMD-V features.
1843	*/
1844	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1845	{
1846	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1847	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1848	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1849	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1850	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1851	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1852	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1853	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1854	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1855	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1856	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1857	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1858	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1859	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1860	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1861	HMSVM_REPORT_FEATURE("SSSCHECK", X86_CPUID_SVM_FEATURE_EDX_SSSCHECK),
1862	HMSVM_REPORT_FEATURE("SPEC_CTRL", X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL),
1863	HMSVM_REPORT_FEATURE("HOST_MCE_OVERRIDE", X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE),
1864	HMSVM_REPORT_FEATURE("TLBICTL", X86_CPUID_SVM_FEATURE_EDX_TLBICTL),
1865	#undef HMSVM_REPORT_FEATURE
1866	};
1867
1868	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1869	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1870	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1871	{
1872	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1873	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1874	}
1875	if (fSvmFeatures)
1876	for (unsigned iBit = 0; iBit < 32; iBit++)
1877	if (RT_BIT_32(iBit) & fSvmFeatures)
1878	LogRel(("HM: Reserved bit %u\n", iBit));
1879
1880	/*
1881	* Nested paging is determined in HMR3Init, verify the sanity of that.
1882	*/
1883	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1884	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1885	VERR_HM_IPE_1);
1886
1887	#if 0
1888	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1889	* here. */
1890	if (RTR0IsPostIpiSupport())
1891	pVM->hm.s.fPostedIntrs = true;
1892	#endif
1893
1894	/*
1895	* Determine whether we need to intercept #UD in SVM mode for emulating
1896	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1897	* when executed in long-mode. This is only really applicable when
1898	* non-default CPU profiles are in effect, i.e. guest vendor differs
1899	* from the host one.
1900	*/
1901	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1902	switch (CPUMGetGuestCpuVendor(pVM))
1903	{
1904	case CPUMCPUVENDOR_INTEL:
1905	case CPUMCPUVENDOR_VIA: /?/
1906	case CPUMCPUVENDOR_SHANGHAI: /?/
1907	switch (CPUMGetHostCpuVendor(pVM))
1908	{
1909	case CPUMCPUVENDOR_AMD:
1910	case CPUMCPUVENDOR_HYGON:
1911	if (pVM->hm.s.fAllow64BitGuestsCfg)
1912	{
1913	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1914	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1915	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1916	}
1917	break;
1918	default: break;
1919	}
1920	default: break;
1921	}
1922
1923	/*
1924	* Call ring-0 to set up the VM.
1925	*/
1926	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1927	if (rc != VINF_SUCCESS)
1928	{
1929	AssertMsgFailed(("%Rrc\n", rc));
1930	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1931	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1932	}
1933
1934	LogRel(("HM: Enabled SVM\n"));
1935	pVM->hm.s.svm.fEnabled = true;
1936
1937	if (pVM->hm.s.fNestedPagingCfg)
1938	{
1939	LogRel(("HM: Enabled nested paging\n"));
1940
1941	/*
1942	* Enable large pages (2 MB) if applicable.
1943	*/
1944	if (pVM->hm.s.fLargePages)
1945	{
1946	PGMSetLargePageUsage(pVM, true);
1947	LogRel(("HM: Enabled large page support\n"));
1948	}
1949	}
1950
1951	if (pVM->hm.s.fVirtApicRegs)
1952	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1953
1954	if (pVM->hm.s.fPostedIntrs)
1955	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1956
1957	hmR3DisableRawMode(pVM);
1958
1959	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1960	: "HM: Disabled TPR patching\n"));
1961
1962	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1963	: "HM: Guest support: 32-bit only\n"));
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/**
1969	* Applies relocations to data and code managed by this
1970	* component. This function will be called at init and
1971	* whenever the VMM need to relocate it self inside the GC.
1972	*
1973	* @param pVM The cross context VM structure.
1974	*/
1975	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1976	{
1977	/* Fetch the current paging mode during the relocate callback during state loading. */
1978	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1979	{
1980	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1981	{
1982	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1983	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1984	}
1985	}
1986	}
1987
1988
1989	/**
1990	* Terminates the HM.
1991	*
1992	* Termination means cleaning up and freeing all resources,
1993	* the VM itself is, at this point, powered off or suspended.
1994	*
1995	* @returns VBox status code.
1996	* @param pVM The cross context VM structure.
1997	*/
1998	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1999	{
2000	if (pVM->hm.s.vmx.pRealModeTSS)
2001	{
2002	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2003	pVM->hm.s.vmx.pRealModeTSS = 0;
2004	}
2005	hmR3TermCPU(pVM);
2006	return 0;
2007	}
2008
2009
2010	/**
2011	* Terminates the per-VCPU HM.
2012	*
2013	* @returns VBox status code.
2014	* @param pVM The cross context VM structure.
2015	*/
2016	static int hmR3TermCPU(PVM pVM)
2017	{
2018	RT_NOREF(pVM);
2019	return VINF_SUCCESS;
2020	}
2021
2022
2023	/**
2024	* Resets a virtual CPU.
2025	*
2026	* Used by HMR3Reset and CPU hot plugging.
2027	*
2028	* @param pVCpu The cross context virtual CPU structure to reset.
2029	*/
2030	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2031	{
2032	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2033	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2034	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2035
2036	pVCpu->hm.s.fActive = false;
2037	pVCpu->hm.s.Event.fPending = false;
2038	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2039	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2040	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2041	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2042	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2043	#endif
2044	}
2045
2046
2047	/**
2048	* The VM is being reset.
2049	*
2050	* For the HM component this means that any GDT/LDT/TSS monitors
2051	* needs to be removed.
2052	*
2053	* @param pVM The cross context VM structure.
2054	*/
2055	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2056	{
2057	LogFlow(("HMR3Reset:\n"));
2058
2059	if (HMIsEnabled(pVM))
2060	hmR3DisableRawMode(pVM);
2061
2062	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2063	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2064
2065	/* Clear all patch information. */
2066	pVM->hm.s.pGuestPatchMem = 0;
2067	pVM->hm.s.pFreeGuestPatchMem = 0;
2068	pVM->hm.s.cbGuestPatchMem = 0;
2069	pVM->hm.s.cPatches = 0;
2070	pVM->hm.s.PatchTree = 0;
2071	pVM->hm.s.fTprPatchingActive = false;
2072	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2073	}
2074
2075
2076	/**
2077	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2078	*
2079	* @returns VBox strict status code.
2080	* @param pVM The cross context VM structure.
2081	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2082	* @param pvUser Unused.
2083	*/
2084	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2085	{
2086	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2087
2088	/* Only execute the handler on the VCPU the original patch request was issued. */
2089	if (pVCpu->idCpu != idCpu)
2090	return VINF_SUCCESS;
2091
2092	Log(("hmR3RemovePatches\n"));
2093	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2094	{
2095	uint8_t abInstr[15];
2096	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2097	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2098	int rc;
2099
2100	#ifdef LOG_ENABLED
2101	char szOutput[256];
2102	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2103	szOutput, sizeof(szOutput), NULL);
2104	if (RT_SUCCESS(rc))
2105	Log(("Patched instr: %s\n", szOutput));
2106	#endif
2107
2108	/* Check if the instruction is still the same. */
2109	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2110	if (rc != VINF_SUCCESS)
2111	{
2112	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2113	continue; /* swapped out or otherwise removed; skip it. */
2114	}
2115
2116	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2117	{
2118	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2119	continue; /* skip it. */
2120	}
2121
2122	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2123	AssertRC(rc);
2124
2125	#ifdef LOG_ENABLED
2126	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2127	szOutput, sizeof(szOutput), NULL);
2128	if (RT_SUCCESS(rc))
2129	Log(("Original instr: %s\n", szOutput));
2130	#endif
2131	}
2132	pVM->hm.s.cPatches = 0;
2133	pVM->hm.s.PatchTree = 0;
2134	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2135	pVM->hm.s.fTprPatchingActive = false;
2136	return VINF_SUCCESS;
2137	}
2138
2139
2140	/**
2141	* Worker for enabling patching in a VT-x/AMD-V guest.
2142	*
2143	* @returns VBox status code.
2144	* @param pVM The cross context VM structure.
2145	* @param idCpu VCPU to execute hmR3RemovePatches on.
2146	* @param pPatchMem Patch memory range.
2147	* @param cbPatchMem Size of the memory range.
2148	*/
2149	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2150	{
2151	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2152	AssertRC(rc);
2153
2154	pVM->hm.s.pGuestPatchMem = pPatchMem;
2155	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2156	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2157	return VINF_SUCCESS;
2158	}
2159
2160
2161	/**
2162	* Enable patching in a VT-x/AMD-V guest
2163	*
2164	* @returns VBox status code.
2165	* @param pVM The cross context VM structure.
2166	* @param pPatchMem Patch memory range.
2167	* @param cbPatchMem Size of the memory range.
2168	*/
2169	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2170	{
2171	VM_ASSERT_EMT(pVM);
2172	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2173	if (pVM->cCpus > 1)
2174	{
2175	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2176	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2177	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2178	AssertRC(rc);
2179	return rc;
2180	}
2181	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2182	}
2183
2184
2185	/**
2186	* Disable patching in a VT-x/AMD-V guest.
2187	*
2188	* @returns VBox status code.
2189	* @param pVM The cross context VM structure.
2190	* @param pPatchMem Patch memory range.
2191	* @param cbPatchMem Size of the memory range.
2192	*/
2193	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2194	{
2195	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2196	RT_NOREF2(pPatchMem, cbPatchMem);
2197
2198	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2199	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2200
2201	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2202	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2203	(void *)(uintptr_t)VMMGetCpuId(pVM));
2204	AssertRC(rc);
2205
2206	pVM->hm.s.pGuestPatchMem = 0;
2207	pVM->hm.s.pFreeGuestPatchMem = 0;
2208	pVM->hm.s.cbGuestPatchMem = 0;
2209	pVM->hm.s.fTprPatchingActive = false;
2210	return VINF_SUCCESS;
2211	}
2212
2213
2214	/**
2215	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2216	*
2217	* @returns VBox strict status code.
2218	* @param pVM The cross context VM structure.
2219	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2220	* @param pvUser User specified CPU context.
2221	*
2222	*/
2223	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2224	{
2225	/*
2226	* Only execute the handler on the VCPU the original patch request was
2227	* issued. (The other CPU(s) might not yet have switched to protected
2228	* mode, nor have the correct memory context.)
2229	*/
2230	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2231	if (pVCpu->idCpu != idCpu)
2232	return VINF_SUCCESS;
2233
2234	/*
2235	* We're racing other VCPUs here, so don't try patch the instruction twice
2236	* and make sure there is still room for our patch record.
2237	*/
2238	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2239	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2240	if (pPatch)
2241	{
2242	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2243	return VINF_SUCCESS;
2244	}
2245	uint32_t const idx = pVM->hm.s.cPatches;
2246	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2247	{
2248	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2249	return VINF_SUCCESS;
2250	}
2251	pPatch = &pVM->hm.s.aPatches[idx];
2252
2253	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2254
2255	/*
2256	* Disassembler the instruction and get cracking.
2257	*/
2258	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2259	DISCPUSTATE Dis;
2260	uint32_t cbOp;
2261	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2262	AssertRC(rc);
2263	if ( rc == VINF_SUCCESS
2264	&& Dis.pCurInstr->uOpcode == OP_MOV
2265	&& cbOp >= 3)
2266	{
2267	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2268
2269	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2270	AssertRC(rc);
2271
2272	pPatch->cbOp = cbOp;
2273
2274	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2275	{
2276	/* write. */
2277	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2278	{
2279	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2280	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2281	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2282	}
2283	else
2284	{
2285	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2286	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2287	pPatch->uSrcOperand = Dis.Param2.uValue;
2288	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2289	}
2290	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2291	AssertRC(rc);
2292
2293	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2294	pPatch->cbNewOp = sizeof(s_abVMMCall);
2295	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2296	}
2297	else
2298	{
2299	/*
2300	* TPR Read.
2301	*
2302	* Found:
2303	* mov eax, dword [fffe0080] (5 bytes)
2304	* Check if next instruction is:
2305	* shr eax, 4
2306	*/
2307	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2308
2309	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2310	uint8_t const cbOpMmio = cbOp;
2311	uint64_t const uSavedRip = pCtx->rip;
2312
2313	pCtx->rip += cbOp;
2314	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2315	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2316	pCtx->rip = uSavedRip;
2317
2318	if ( rc == VINF_SUCCESS
2319	&& Dis.pCurInstr->uOpcode == OP_SHR
2320	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2321	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2322	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2323	&& Dis.Param2.uValue == 4
2324	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2325	{
2326	uint8_t abInstr[15];
2327
2328	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2329	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2330	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2331	AssertRC(rc);
2332
2333	pPatch->cbOp = cbOpMmio + cbOp;
2334
2335	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2336	abInstr[0] = 0xf0;
2337	abInstr[1] = 0x0f;
2338	abInstr[2] = 0x20;
2339	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2340	for (unsigned i = 4; i < pPatch->cbOp; i++)
2341	abInstr[i] = 0x90; /* nop */
2342
2343	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2344	AssertRC(rc);
2345
2346	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2347	pPatch->cbNewOp = pPatch->cbOp;
2348	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2349
2350	Log(("Acceptable read/shr candidate!\n"));
2351	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2352	}
2353	else
2354	{
2355	pPatch->enmType = HMTPRINSTR_READ;
2356	pPatch->uDstOperand = idxMmioReg;
2357
2358	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2359	AssertRC(rc);
2360
2361	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2362	pPatch->cbNewOp = sizeof(s_abVMMCall);
2363	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2364	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2365	}
2366	}
2367
2368	pPatch->Core.Key = pCtx->eip;
2369	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2370	AssertRC(rc);
2371
2372	pVM->hm.s.cPatches++;
2373	return VINF_SUCCESS;
2374	}
2375
2376	/*
2377	* Save invalid patch, so we will not try again.
2378	*/
2379	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2380	pPatch->Core.Key = pCtx->eip;
2381	pPatch->enmType = HMTPRINSTR_INVALID;
2382	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2383	AssertRC(rc);
2384	pVM->hm.s.cPatches++;
2385	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2386	return VINF_SUCCESS;
2387	}
2388
2389
2390	/**
2391	* Callback to patch a TPR instruction (jump to generated code).
2392	*
2393	* @returns VBox strict status code.
2394	* @param pVM The cross context VM structure.
2395	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2396	* @param pvUser User specified CPU context.
2397	*
2398	*/
2399	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2400	{
2401	/*
2402	* Only execute the handler on the VCPU the original patch request was
2403	* issued. (The other CPU(s) might not yet have switched to protected
2404	* mode, nor have the correct memory context.)
2405	*/
2406	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2407	if (pVCpu->idCpu != idCpu)
2408	return VINF_SUCCESS;
2409
2410	/*
2411	* We're racing other VCPUs here, so don't try patch the instruction twice
2412	* and make sure there is still room for our patch record.
2413	*/
2414	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2415	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2416	if (pPatch)
2417	{
2418	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2419	return VINF_SUCCESS;
2420	}
2421	uint32_t const idx = pVM->hm.s.cPatches;
2422	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2423	{
2424	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2425	return VINF_SUCCESS;
2426	}
2427	pPatch = &pVM->hm.s.aPatches[idx];
2428
2429	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2430	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2431
2432	/*
2433	* Disassemble the instruction and get cracking.
2434	*/
2435	DISCPUSTATE Dis;
2436	uint32_t cbOp;
2437	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2438	AssertRC(rc);
2439	if ( rc == VINF_SUCCESS
2440	&& Dis.pCurInstr->uOpcode == OP_MOV
2441	&& cbOp >= 5)
2442	{
2443	uint8_t aPatch[64];
2444	uint32_t off = 0;
2445
2446	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2447	AssertRC(rc);
2448
2449	pPatch->cbOp = cbOp;
2450	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2451
2452	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2453	{
2454	/*
2455	* TPR write:
2456	*
2457	* push ECX [51]
2458	* push EDX [52]
2459	* push EAX [50]
2460	* xor EDX,EDX [31 D2]
2461	* mov EAX,EAX [89 C0]
2462	* or
2463	* mov EAX,0000000CCh [B8 CC 00 00 00]
2464	* mov ECX,0C0000082h [B9 82 00 00 C0]
2465	* wrmsr [0F 30]
2466	* pop EAX [58]
2467	* pop EDX [5A]
2468	* pop ECX [59]
2469	* jmp return_address [E9 return_address]
2470	*/
2471	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2472
2473	aPatch[off++] = 0x51; /* push ecx */
2474	aPatch[off++] = 0x52; /* push edx */
2475	if (!fUsesEax)
2476	aPatch[off++] = 0x50; /* push eax */
2477	aPatch[off++] = 0x31; /* xor edx, edx */
2478	aPatch[off++] = 0xd2;
2479	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2480	{
2481	if (!fUsesEax)
2482	{
2483	aPatch[off++] = 0x89; /* mov eax, src_reg */
2484	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2485	}
2486	}
2487	else
2488	{
2489	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2490	aPatch[off++] = 0xb8; /* mov eax, immediate */
2491	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2492	off += sizeof(uint32_t);
2493	}
2494	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2495	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2496	off += sizeof(uint32_t);
2497
2498	aPatch[off++] = 0x0f; /* wrmsr */
2499	aPatch[off++] = 0x30;
2500	if (!fUsesEax)
2501	aPatch[off++] = 0x58; /* pop eax */
2502	aPatch[off++] = 0x5a; /* pop edx */
2503	aPatch[off++] = 0x59; /* pop ecx */
2504	}
2505	else
2506	{
2507	/*
2508	* TPR read:
2509	*
2510	* push ECX [51]
2511	* push EDX [52]
2512	* push EAX [50]
2513	* mov ECX,0C0000082h [B9 82 00 00 C0]
2514	* rdmsr [0F 32]
2515	* mov EAX,EAX [89 C0]
2516	* pop EAX [58]
2517	* pop EDX [5A]
2518	* pop ECX [59]
2519	* jmp return_address [E9 return_address]
2520	*/
2521	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2522
2523	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2524	aPatch[off++] = 0x51; /* push ecx */
2525	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2526	aPatch[off++] = 0x52; /* push edx */
2527	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2528	aPatch[off++] = 0x50; /* push eax */
2529
2530	aPatch[off++] = 0x31; /* xor edx, edx */
2531	aPatch[off++] = 0xd2;
2532
2533	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2534	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2535	off += sizeof(uint32_t);
2536
2537	aPatch[off++] = 0x0f; /* rdmsr */
2538	aPatch[off++] = 0x32;
2539
2540	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2541	{
2542	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2543	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2544	}
2545
2546	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2547	aPatch[off++] = 0x58; /* pop eax */
2548	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2549	aPatch[off++] = 0x5a; /* pop edx */
2550	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2551	aPatch[off++] = 0x59; /* pop ecx */
2552	}
2553	aPatch[off++] = 0xe9; /* jmp return_address */
2554	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2555	off += sizeof(RTRCUINTPTR);
2556
2557	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2558	{
2559	/* Write new code to the patch buffer. */
2560	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2561	AssertRC(rc);
2562
2563	#ifdef LOG_ENABLED
2564	uint32_t cbCurInstr;
2565	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2566	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2567	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2568	{
2569	char szOutput[256];
2570	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2571	szOutput, sizeof(szOutput), &cbCurInstr);
2572	if (RT_SUCCESS(rc))
2573	Log(("Patch instr %s\n", szOutput));
2574	else
2575	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2576	}
2577	#endif
2578
2579	pPatch->aNewOpcode[0] = 0xE9;
2580	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2581
2582	/* Overwrite the TPR instruction with a jump. */
2583	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2584	AssertRC(rc);
2585
2586	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2587
2588	pVM->hm.s.pFreeGuestPatchMem += off;
2589	pPatch->cbNewOp = 5;
2590
2591	pPatch->Core.Key = pCtx->eip;
2592	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2593	AssertRC(rc);
2594
2595	pVM->hm.s.cPatches++;
2596	pVM->hm.s.fTprPatchingActive = true;
2597	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2598	return VINF_SUCCESS;
2599	}
2600
2601	Log(("Ran out of space in our patch buffer!\n"));
2602	}
2603	else
2604	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2605
2606
2607	/*
2608	* Save invalid patch, so we will not try again.
2609	*/
2610	pPatch = &pVM->hm.s.aPatches[idx];
2611	pPatch->Core.Key = pCtx->eip;
2612	pPatch->enmType = HMTPRINSTR_INVALID;
2613	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2614	AssertRC(rc);
2615	pVM->hm.s.cPatches++;
2616	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2617	return VINF_SUCCESS;
2618	}
2619
2620
2621	/**
2622	* Attempt to patch TPR mmio instructions.
2623	*
2624	* @returns VBox status code.
2625	* @param pVM The cross context VM structure.
2626	* @param pVCpu The cross context virtual CPU structure.
2627	*/
2628	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2629	{
2630	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2631	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2632	(void *)(uintptr_t)pVCpu->idCpu);
2633	AssertRC(rc);
2634	return rc;
2635	}
2636
2637
2638	/**
2639	* Checks if we need to reschedule due to VMM device heap changes.
2640	*
2641	* @returns true if a reschedule is required, otherwise false.
2642	* @param pVM The cross context VM structure.
2643	* @param pCtx VM execution context.
2644	*/
2645	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2646	{
2647	/*
2648	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2649	* when the unrestricted guest execution feature is missing (VT-x only).
2650	*/
2651	if ( pVM->hm.s.vmx.fEnabled
2652	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2653	&& CPUMIsGuestInRealModeEx(pCtx)
2654	&& !PDMVmmDevHeapIsEnabled(pVM))
2655	return true;
2656
2657	return false;
2658	}
2659
2660
2661	/**
2662	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2663	* event settings changes.
2664	*
2665	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2666	* function is just updating the VM globals.
2667	*
2668	* @param pVM The VM cross context VM structure.
2669	* @thread EMT(0)
2670	*/
2671	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2672	{
2673	/* Interrupts. */
2674	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2675	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2676
2677	/* CPU Exceptions. */
2678	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2679	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2680	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2681	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2682
2683	/* Common VM exits. */
2684	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2685	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2686	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2687	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2688
2689	/* Vendor specific VM exits. */
2690	if (HMR3IsVmxEnabled(pVM->pUVM))
2691	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2692	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2693	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2694	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2695	else
2696	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2697	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2698	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2699	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2700
2701	/* Done. */
2702	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2703	}
2704
2705
2706	/**
2707	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2708	*
2709	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2710	* per CPU settings.
2711	*
2712	* @param pVM The VM cross context VM structure.
2713	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2714	*/
2715	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2716	{
2717	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2718	}
2719
2720
2721	/**
2722	* Checks if we are currently using hardware acceleration.
2723	*
2724	* @returns true if hardware acceleration is being used, otherwise false.
2725	* @param pVCpu The cross context virtual CPU structure.
2726	*/
2727	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2728	{
2729	return pVCpu->hm.s.fActive;
2730	}
2731
2732
2733	/**
2734	* External interface for querying whether hardware acceleration is enabled.
2735	*
2736	* @returns true if VT-x or AMD-V is being used, otherwise false.
2737	* @param pUVM The user mode VM handle.
2738	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2739	*/
2740	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2741	{
2742	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2743	PVM pVM = pUVM->pVM;
2744	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2745	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2746	}
2747
2748
2749	/**
2750	* External interface for querying whether VT-x is being used.
2751	*
2752	* @returns true if VT-x is being used, otherwise false.
2753	* @param pUVM The user mode VM handle.
2754	* @sa HMR3IsSvmEnabled, HMIsEnabled
2755	*/
2756	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2757	{
2758	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2759	PVM pVM = pUVM->pVM;
2760	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2761	return pVM->hm.s.vmx.fEnabled
2762	&& pVM->hm.s.vmx.fSupported
2763	&& pVM->fHMEnabled;
2764	}
2765
2766
2767	/**
2768	* External interface for querying whether AMD-V is being used.
2769	*
2770	* @returns true if VT-x is being used, otherwise false.
2771	* @param pUVM The user mode VM handle.
2772	* @sa HMR3IsVmxEnabled, HMIsEnabled
2773	*/
2774	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2775	{
2776	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2777	PVM pVM = pUVM->pVM;
2778	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2779	return pVM->hm.s.svm.fEnabled
2780	&& pVM->hm.s.svm.fSupported
2781	&& pVM->fHMEnabled;
2782	}
2783
2784
2785	/**
2786	* Checks if we are currently using nested paging.
2787	*
2788	* @returns true if nested paging is being used, otherwise false.
2789	* @param pUVM The user mode VM handle.
2790	*/
2791	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2792	{
2793	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2794	PVM pVM = pUVM->pVM;
2795	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2796	return pVM->hm.s.fNestedPagingCfg;
2797	}
2798
2799
2800	/**
2801	* Checks if virtualized APIC registers are enabled.
2802	*
2803	* When enabled this feature allows the hardware to access most of the
2804	* APIC registers in the virtual-APIC page without causing VM-exits. See
2805	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2806	*
2807	* @returns true if virtualized APIC registers is enabled, otherwise
2808	* false.
2809	* @param pUVM The user mode VM handle.
2810	*/
2811	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2812	{
2813	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2814	PVM pVM = pUVM->pVM;
2815	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2816	return pVM->hm.s.fVirtApicRegs;
2817	}
2818
2819
2820	/**
2821	* Checks if APIC posted-interrupt processing is enabled.
2822	*
2823	* This returns whether we can deliver interrupts to the guest without
2824	* leaving guest-context by updating APIC state from host-context.
2825	*
2826	* @returns true if APIC posted-interrupt processing is enabled,
2827	* otherwise false.
2828	* @param pUVM The user mode VM handle.
2829	*/
2830	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2831	{
2832	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2833	PVM pVM = pUVM->pVM;
2834	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2835	return pVM->hm.s.fPostedIntrs;
2836	}
2837
2838
2839	/**
2840	* Checks if we are currently using VPID in VT-x mode.
2841	*
2842	* @returns true if VPID is being used, otherwise false.
2843	* @param pUVM The user mode VM handle.
2844	*/
2845	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2846	{
2847	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2848	PVM pVM = pUVM->pVM;
2849	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2850	return pVM->hm.s.ForR3.vmx.fVpid;
2851	}
2852
2853
2854	/**
2855	* Checks if we are currently using VT-x unrestricted execution,
2856	* aka UX.
2857	*
2858	* @returns true if UX is being used, otherwise false.
2859	* @param pUVM The user mode VM handle.
2860	*/
2861	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2862	{
2863	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2864	PVM pVM = pUVM->pVM;
2865	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2866	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2867	\|\| pVM->hm.s.svm.fSupported;
2868	}
2869
2870
2871	/**
2872	* Checks if the VMX-preemption timer is being used.
2873	*
2874	* @returns true if the VMX-preemption timer is being used, otherwise false.
2875	* @param pVM The cross context VM structure.
2876	*/
2877	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2878	{
2879	return HMIsEnabled(pVM)
2880	&& pVM->hm.s.vmx.fEnabled
2881	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2882	}
2883
2884
2885	#ifdef TODO_9217_VMCSINFO
2886	/**
2887	* Helper for HMR3CheckError to log VMCS controls to the release log.
2888	*
2889	* @param idCpu The Virtual CPU ID.
2890	* @param pVmcsInfo The VMCS info. object.
2891	*/
2892	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2893	{
2894	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2895	{
2896	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2897	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2902	}
2903	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2904	{
2905	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2928	}
2929	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2930	{
2931	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2959	}
2960	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2961	{
2962	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2975	}
2976	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2977	{
2978	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2993	}
2994	}
2995	#endif
2996
2997
2998	/**
2999	* Check fatal VT-x/AMD-V error and produce some meaningful
3000	* log release message.
3001	*
3002	* @param pVM The cross context VM structure.
3003	* @param iStatusCode VBox status code.
3004	*/
3005	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3006	{
3007	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3008	{
3009	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3010	* might be getting inaccurate values for non-guru'ing EMTs. */
3011	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3012	#ifdef TODO_9217_VMCSINFO
3013	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3014	#endif
3015	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3016	switch (iStatusCode)
3017	{
3018	case VERR_VMX_INVALID_VMCS_PTR:
3019	{
3020	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3021	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3022	#ifdef TODO_9217_VMCSINFO
3023	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3024	pVmcsInfo->HCPhysVmcs));
3025	#endif
3026	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3027	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3028	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3029	break;
3030	}
3031
3032	case VERR_VMX_UNABLE_TO_START_VM:
3033	{
3034	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3035	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3036	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3037	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3038
3039	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3040	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3041	{
3042	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3043	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3044	}
3045	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3046	{
3047	#ifdef TODO_9217_VMCSINFO
3048	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3049	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3050	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3051	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3052	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3053	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3054	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3055	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3056	#endif
3057	}
3058	/** @todo Log VM-entry event injection control fields
3059	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3060	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3061	break;
3062	}
3063
3064	case VERR_VMX_INVALID_GUEST_STATE:
3065	{
3066	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3067	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3068	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3069	#ifdef TODO_9217_VMCSINFO
3070	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3071	#endif
3072	break;
3073	}
3074
3075	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3076	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3077	case VERR_VMX_INVALID_VMXON_PTR:
3078	case VERR_VMX_UNEXPECTED_EXIT:
3079	case VERR_VMX_INVALID_VMCS_FIELD:
3080	case VERR_SVM_UNKNOWN_EXIT:
3081	case VERR_SVM_UNEXPECTED_EXIT:
3082	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3083	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3084	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3085	break;
3086	}
3087	}
3088
3089	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3090	{
3091	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3092	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3093	}
3094	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3095	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3096	}
3097
3098
3099	/**
3100	* Execute state save operation.
3101	*
3102	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3103	* is because we always save the VM state from ring-3 and thus most HM state
3104	* will be re-synced dynamically at runtime and don't need to be part of the VM
3105	* saved state.
3106	*
3107	* @returns VBox status code.
3108	* @param pVM The cross context VM structure.
3109	* @param pSSM SSM operation handle.
3110	*/
3111	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3112	{
3113	Log(("hmR3Save:\n"));
3114
3115	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3116	{
3117	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3118	Assert(!pVCpu->hm.s.Event.fPending);
3119	if (pVM->cpum.ro.GuestFeatures.fSvm)
3120	{
3121	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3122	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3123	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3124	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3125	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3126	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3127	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3128	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3129	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3130	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3131	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3132	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3133	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3134	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3135	}
3136	}
3137
3138	/* Save the guest patch data. */
3139	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3140	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3141	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3142
3143	/* Store all the guest patch records too. */
3144	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3145	if (RT_FAILURE(rc))
3146	return rc;
3147
3148	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3149	{
3150	AssertCompileSize(HMTPRINSTR, 4);
3151	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3152	SSMR3PutU32(pSSM, pPatch->Core.Key);
3153	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3154	SSMR3PutU32(pSSM, pPatch->cbOp);
3155	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3156	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3157	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3158	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3159	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3160	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3161	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3162	if (RT_FAILURE(rc))
3163	return rc;
3164	}
3165
3166	return VINF_SUCCESS;
3167	}
3168
3169
3170	/**
3171	* Execute state load operation.
3172	*
3173	* @returns VBox status code.
3174	* @param pVM The cross context VM structure.
3175	* @param pSSM SSM operation handle.
3176	* @param uVersion Data layout version.
3177	* @param uPass The data pass.
3178	*/
3179	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3180	{
3181	int rc;
3182
3183	LogFlowFunc(("uVersion=%u\n", uVersion));
3184	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3185
3186	/*
3187	* Validate version.
3188	*/
3189	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3190	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3191	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3192	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3193	{
3194	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3195	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3196	}
3197
3198	/*
3199	* Load per-VCPU state.
3200	*/
3201	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3202	{
3203	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3204	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3205	{
3206	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3207	if (pVM->cpum.ro.GuestFeatures.fSvm)
3208	{
3209	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3210	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3211	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3212	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3213	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3214	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3215	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3216	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3217	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3218	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3219	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3220	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3221	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3222	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3223	AssertRCReturn(rc, rc);
3224	}
3225	}
3226	else
3227	{
3228	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3229	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3230	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3231	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3232
3233	/* VMX fWasInRealMode related data. */
3234	uint32_t uDummy;
3235	SSMR3GetU32(pSSM, &uDummy);
3236	SSMR3GetU32(pSSM, &uDummy);
3237	rc = SSMR3GetU32(pSSM, &uDummy);
3238	AssertRCReturn(rc, rc);
3239	}
3240	}
3241
3242	/*
3243	* Load TPR patching data.
3244	*/
3245	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3246	{
3247	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3248	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3249	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3250
3251	/* Fetch all TPR patch records. */
3252	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3253	AssertRCReturn(rc, rc);
3254	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3255	{
3256	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3257	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3258	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3259	SSMR3GetU32(pSSM, &pPatch->cbOp);
3260	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3261	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3262	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3263
3264	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3265	pVM->hm.s.fTprPatchingActive = true;
3266	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3267
3268	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3269	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3270	SSMR3GetU32(pSSM, &pPatch->cFaults);
3271	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3272	AssertRCReturn(rc, rc);
3273
3274	LogFlow(("hmR3Load: patch %d\n", i));
3275	LogFlow(("Key = %x\n", pPatch->Core.Key));
3276	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3277	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3278	LogFlow(("type = %d\n", pPatch->enmType));
3279	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3280	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3281	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3282	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3283
3284	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3285	AssertRCReturn(rc, rc);
3286	}
3287	}
3288
3289	return VINF_SUCCESS;
3290	}
3291
3292
3293	/**
3294	* Displays HM info.
3295	*
3296	* @param pVM The cross context VM structure.
3297	* @param pHlp The info helper functions.
3298	* @param pszArgs Arguments, ignored.
3299	*/
3300	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3301	{
3302	NOREF(pszArgs);
3303	PVMCPU pVCpu = VMMGetCpu(pVM);
3304	if (!pVCpu)
3305	pVCpu = pVM->apCpusR3[0];
3306
3307	if (HMIsEnabled(pVM))
3308	{
3309	if (pVM->hm.s.vmx.fSupported)
3310	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3311	else
3312	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3313	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3314	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3315	if (pVM->hm.s.vmx.fSupported)
3316	{
3317	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3318	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3319	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3320
3321	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3322	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3323	if (fRealOnV86Active)
3324	{
3325	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3326	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3327	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3328	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3329	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3330	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3331	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3332	}
3333	}
3334	}
3335	else
3336	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3337	}
3338
3339
3340	/**
3341	* Displays the HM Last-Branch-Record info. for the guest.
3342	*
3343	* @param pVM The cross context VM structure.
3344	* @param pHlp The info helper functions.
3345	* @param pszArgs Arguments, ignored.
3346	*/
3347	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3348	{
3349	NOREF(pszArgs);
3350	PVMCPU pVCpu = VMMGetCpu(pVM);
3351	if (!pVCpu)
3352	pVCpu = pVM->apCpusR3[0];
3353
3354	if (!HMIsEnabled(pVM))
3355	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3356	else if (HMIsVmxActive(pVM))
3357	{
3358	if (pVM->hm.s.vmx.fLbrCfg)
3359	{
3360	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3361	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3362
3363	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3364	* 0xf should cover everything we support thus far. Fix if necessary
3365	* later. */
3366	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3367	if (idxTopOfStack > cLbrStack)
3368	{
3369	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3370	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3371	return;
3372	}
3373
3374	/*
3375	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3376	*/
3377	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3378	uint32_t idxCurrent = idxTopOfStack;
3379	Assert(idxTopOfStack < cLbrStack);
3380	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3381	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3382	for (;;)
3383	{
3384	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3385	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3386	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3387	else
3388	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3389
3390	idxCurrent = (idxCurrent - 1) % cLbrStack;
3391	if (idxCurrent == idxTopOfStack)
3392	break;
3393	}
3394	}
3395	else
3396	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3397	}
3398	else
3399	{
3400	Assert(HMIsSvmActive(pVM));
3401	/** @todo SVM: LBRs (get them from VMCB if possible). */
3402	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3403	}
3404	}
3405
3406
3407	/**
3408	* Displays the HM pending event.
3409	*
3410	* @param pVM The cross context VM structure.
3411	* @param pHlp The info helper functions.
3412	* @param pszArgs Arguments, ignored.
3413	*/
3414	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3415	{
3416	NOREF(pszArgs);
3417	PVMCPU pVCpu = VMMGetCpu(pVM);
3418	if (!pVCpu)
3419	pVCpu = pVM->apCpusR3[0];
3420
3421	if (HMIsEnabled(pVM))
3422	{
3423	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3424	if (pVCpu->hm.s.Event.fPending)
3425	{
3426	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3427	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3428	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3429	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3430	}
3431	}
3432	else
3433	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3434	}
3435
3436
3437	/**
3438	* Displays the SVM nested-guest VMCB cache.
3439	*
3440	* @param pVM The cross context VM structure.
3441	* @param pHlp The info helper functions.
3442	* @param pszArgs Arguments, ignored.
3443	*/
3444	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3445	{
3446	NOREF(pszArgs);
3447	PVMCPU pVCpu = VMMGetCpu(pVM);
3448	if (!pVCpu)
3449	pVCpu = pVM->apCpusR3[0];
3450
3451	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3452	if ( fSvmEnabled
3453	&& pVM->cpum.ro.GuestFeatures.fSvm)
3454	{
3455	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3456	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3457	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3458	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3459	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3460	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3461	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3462	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3463	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3464	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3465	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3466	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3467	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3468	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3469	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3470	}
3471	else
3472	{
3473	if (!fSvmEnabled)
3474	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3475	else
3476	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3477	}
3478	}
3479

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