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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 84044

Last change on this file since 84044 was 83105, checked in by vboxsync, 4 years ago
VMM/HM: LogRel nit.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 154.3 KB

Line
1	/* $Id: HM.cpp 83105 2020-02-18 03:48:08Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#include <VBox/vmm/hm_vmx.h>
56	#include <VBox/vmm/hm_svm.h>
57	#include "HMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/err.h>
60	#include <VBox/param.h>
61
62	#include <iprt/assert.h>
63	#include <VBox/log.h>
64	#include <iprt/asm.h>
65	#include <iprt/asm-amd64-x86.h>
66	#include <iprt/env.h>
67	#include <iprt/thread.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73	/** @def HMVMX_REPORT_FEAT
74	* Reports VT-x feature to the release log.
75	*
76	* @param a_uAllowed1 Mask of allowed-1 feature bits.
77	* @param a_uAllowed0 Mask of allowed-0 feature bits.
78	* @param a_StrDesc The description string to report.
79	* @param a_Featflag Mask of the feature to report.
80	*/
81	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
82	do { \
83	if ((a_uAllowed1) & (a_Featflag)) \
84	{ \
85	if ((a_uAllowed0) & (a_Featflag)) \
86	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
87	else \
88	LogRel(("HM: " a_StrDesc "\n")); \
89	} \
90	else \
91	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
92	} while (0)
93
94	/** @def HMVMX_REPORT_ALLOWED_FEAT
95	* Reports an allowed VT-x feature to the release log.
96	*
97	* @param a_uAllowed1 Mask of allowed-1 feature bits.
98	* @param a_StrDesc The description string to report.
99	* @param a_FeatFlag Mask of the feature to report.
100	*/
101	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
102	do { \
103	if ((a_uAllowed1) & (a_FeatFlag)) \
104	LogRel(("HM: " a_StrDesc "\n")); \
105	else \
106	LogRel(("HM: " a_StrDesc " not supported\n")); \
107	} while (0)
108
109	/** @def HMVMX_REPORT_MSR_CAP
110	* Reports MSR feature capability.
111	*
112	* @param a_MsrCaps Mask of MSR feature bits.
113	* @param a_StrDesc The description string to report.
114	* @param a_fCap Mask of the feature to report.
115	*/
116	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
117	do { \
118	if ((a_MsrCaps) & (a_fCap)) \
119	LogRel(("HM: " a_StrDesc "\n")); \
120	} while (0)
121
122	/** @def HMVMX_LOGREL_FEAT
123	* Dumps a feature flag from a bitmap of features to the release log.
124	*
125	* @param a_fVal The value of all the features.
126	* @param a_fMask The specific bitmask of the feature.
127	*/
128	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
129	do { \
130	if ((a_fVal) & (a_fMask)) \
131	LogRel(("HM: %s\n", #a_fMask)); \
132	} while (0)
133
134
135	/*********************************************************************************************************************************
136	* Internal Functions *
137	*********************************************************************************************************************************/
138	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
139	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static int hmR3InitFinalizeR3(PVM pVM);
145	static int hmR3InitFinalizeR0(PVM pVM);
146	static int hmR3InitFinalizeR0Intel(PVM pVM);
147	static int hmR3InitFinalizeR0Amd(PVM pVM);
148	static int hmR3TermCPU(PVM pVM);
149
150
151	#ifdef VBOX_WITH_STATISTICS
152	/**
153	* Returns the name of the hardware exception.
154	*
155	* @returns The name of the hardware exception.
156	* @param uVector The exception vector.
157	*/
158	static const char *hmR3GetXcptName(uint8_t uVector)
159	{
160	switch (uVector)
161	{
162	case X86_XCPT_DE: return "#DE";
163	case X86_XCPT_DB: return "#DB";
164	case X86_XCPT_NMI: return "#NMI";
165	case X86_XCPT_BP: return "#BP";
166	case X86_XCPT_OF: return "#OF";
167	case X86_XCPT_BR: return "#BR";
168	case X86_XCPT_UD: return "#UD";
169	case X86_XCPT_NM: return "#NM";
170	case X86_XCPT_DF: return "#DF";
171	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
172	case X86_XCPT_TS: return "#TS";
173	case X86_XCPT_NP: return "#NP";
174	case X86_XCPT_SS: return "#SS";
175	case X86_XCPT_GP: return "#GP";
176	case X86_XCPT_PF: return "#PF";
177	case X86_XCPT_MF: return "#MF";
178	case X86_XCPT_AC: return "#AC";
179	case X86_XCPT_MC: return "#MC";
180	case X86_XCPT_XF: return "#XF";
181	case X86_XCPT_VE: return "#VE";
182	case X86_XCPT_CP: return "#CP";
183	case X86_XCPT_VC: return "#VC";
184	case X86_XCPT_SX: return "#SX";
185	}
186	return "Reserved";
187	}
188	#endif /* VBOX_WITH_STATISTICS */
189
190
191	/**
192	* Initializes the HM.
193	*
194	* This is the very first component to really do init after CFGM so that we can
195	* establish the predominant execution engine for the VM prior to initializing
196	* other modules. It takes care of NEM initialization if needed (HM disabled or
197	* not available in HW).
198	*
199	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
200	* hypervisor API via NEM, and then back on raw-mode if that isn't available
201	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
202	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
203	* X, OS/2 and others).
204	*
205	* Note that a lot of the set up work is done in ring-0 and thus postponed till
206	* the ring-3 and ring-0 callback to HMR3InitCompleted.
207	*
208	* @returns VBox status code.
209	* @param pVM The cross context VM structure.
210	*
211	* @remarks Be careful with what we call here, since most of the VMM components
212	* are uninitialized.
213	*/
214	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
215	{
216	LogFlowFunc(("\n"));
217
218	/*
219	* Assert alignment and sizes.
220	*/
221	AssertCompileMemberAlignment(VM, hm.s, 32);
222	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
223
224	/*
225	* Register the saved state data unit.
226	*/
227	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
228	NULL, NULL, NULL,
229	NULL, hmR3Save, NULL,
230	NULL, hmR3Load, NULL);
231	if (RT_FAILURE(rc))
232	return rc;
233
234	/*
235	* Register info handlers.
236	*/
237	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
238	AssertRCReturn(rc, rc);
239
240	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
241	DBGFINFO_FLAGS_ALL_EMTS);
242	AssertRCReturn(rc, rc);
243
244	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
245	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
246	AssertRCReturn(rc, rc);
247
248	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
249	AssertRCReturn(rc, rc);
250
251	/*
252	* Read configuration.
253	*/
254	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
255
256	/*
257	* Validate the HM settings.
258	*/
259	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
260	"HMForced" /* implied 'true' these days */
261	"\|UseNEMInstead"
262	"\|FallbackToNEM"
263	"\|EnableNestedPaging"
264	"\|EnableUX"
265	"\|EnableLargePages"
266	"\|EnableVPID"
267	"\|IBPBOnVMExit"
268	"\|IBPBOnVMEntry"
269	"\|SpecCtrlByHost"
270	"\|L1DFlushOnSched"
271	"\|L1DFlushOnVMEntry"
272	"\|MDSClearOnSched"
273	"\|MDSClearOnVMEntry"
274	"\|TPRPatchingEnabled"
275	"\|64bitEnabled"
276	"\|Exclusive"
277	"\|MaxResumeLoops"
278	"\|VmxPleGap"
279	"\|VmxPleWindow"
280	"\|VmxLbr"
281	"\|UseVmxPreemptTimer"
282	"\|SvmPauseFilter"
283	"\|SvmPauseFilterThreshold"
284	"\|SvmVirtVmsaveVmload"
285	"\|SvmVGif"
286	"\|LovelyMesaDrvWorkaround",
287	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
288	if (RT_FAILURE(rc))
289	return rc;
290
291	/** @cfgm{/HM/HMForced, bool, false}
292	* Forces hardware virtualization, no falling back on raw-mode. HM must be
293	* enabled, i.e. /HMEnabled must be true. */
294	bool fHMForced;
295	AssertRelease(pVM->fHMEnabled);
296	fHMForced = true;
297
298	/** @cfgm{/HM/UseNEMInstead, bool, true}
299	* Don't use HM, use NEM instead. */
300	bool fUseNEMInstead = false;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
302	AssertRCReturn(rc, rc);
303	if (fUseNEMInstead && pVM->fHMEnabled)
304	{
305	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
306	pVM->fHMEnabled = false;
307	}
308
309	/** @cfgm{/HM/FallbackToNEM, bool, true}
310	* Enables fallback on NEM. */
311	bool fFallbackToNEM = true;
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/EnableNestedPaging, bool, false}
316	* Enables nested paging (aka extended page tables). */
317	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
318	AssertRCReturn(rc, rc);
319
320	/** @cfgm{/HM/EnableUX, bool, true}
321	* Enables the VT-x unrestricted execution feature. */
322	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
323	AssertRCReturn(rc, rc);
324
325	/** @cfgm{/HM/EnableLargePages, bool, false}
326	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
327	* page table walking and maybe better TLB hit rate in some cases. */
328	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
329	AssertRCReturn(rc, rc);
330
331	/** @cfgm{/HM/EnableVPID, bool, false}
332	* Enables the VT-x VPID feature. */
333	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
334	AssertRCReturn(rc, rc);
335
336	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
337	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
338	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
339	AssertRCReturn(rc, rc);
340
341	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
342	* Enables AMD64 cpu features.
343	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
344	* already have the support. */
345	#ifdef VBOX_WITH_64_BITS_GUESTS
346	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
347	AssertLogRelRCReturn(rc, rc);
348	#else
349	pVM->hm.s.fAllow64BitGuests = false;
350	#endif
351
352	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
353	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
354	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
355	* latest PAUSE instruction to be start of a new PAUSE loop.
356	*/
357	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
358	AssertRCReturn(rc, rc);
359
360	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
361	* The pause-filter exiting window in TSC ticks. When the number of ticks
362	* between the current PAUSE instruction and first PAUSE of a loop exceeds
363	* VmxPleWindow, a VM-exit is triggered.
364	*
365	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
366	*/
367	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
368	AssertRCReturn(rc, rc);
369
370	/** @cfgm{/HM/VmxLbr, bool, false}
371	* Whether to enable LBR for the guest. This is disabled by default as it's only
372	* useful while debugging and enabling it causes a noticeable performance hit. */
373	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbr, false);
374	AssertRCReturn(rc, rc);
375
376	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
377	* A counter that is decrement each time a PAUSE instruction is executed by the
378	* guest. When the counter is 0, a \#VMEXIT is triggered.
379	*
380	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
381	*/
382	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
383	AssertRCReturn(rc, rc);
384
385	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
386	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
387	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
388	* PauseFilter count is reset to its initial value. However, if PAUSE is
389	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
390	* be triggered.
391	*
392	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
393	* activated.
394	*/
395	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
396	AssertRCReturn(rc, rc);
397
398	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
399	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
400	* available. */
401	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
402	AssertRCReturn(rc, rc);
403
404	/** @cfgm{/HM/SvmVGif, bool, true}
405	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
406	* if it's available. */
407	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
408	AssertRCReturn(rc, rc);
409
410	/** @cfgm{/HM/SvmLbrVirt, bool, false}
411	* Whether to make use of the LBR virtualization feature of the CPU if it's
412	* available. This is disabled by default as it's only useful while debugging
413	* and enabling it causes a small hit to performance. */
414	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
415	AssertRCReturn(rc, rc);
416
417	/** @cfgm{/HM/Exclusive, bool}
418	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
419	* global init for each host CPU. If false, we do local init each time we wish
420	* to execute guest code.
421	*
422	* On Windows, default is false due to the higher risk of conflicts with other
423	* hypervisors.
424	*
425	* On Mac OS X, this setting is ignored since the code does not handle local
426	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
427	*/
428	#if defined(RT_OS_DARWIN)
429	pVM->hm.s.fGlobalInit = true;
430	#else
431	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
432	# if defined(RT_OS_WINDOWS)
433	false
434	# else
435	true
436	# endif
437	);
438	AssertLogRelRCReturn(rc, rc);
439	#endif
440
441	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
442	* The number of times to resume guest execution before we forcibly return to
443	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
444	* determines the default value. */
445	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
446	AssertLogRelRCReturn(rc, rc);
447
448	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
449	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
450	* available. */
451	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
452	AssertLogRelRCReturn(rc, rc);
453
454	/** @cfgm{/HM/IBPBOnVMExit, bool}
455	* Costly paranoia setting. */
456	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
457	AssertLogRelRCReturn(rc, rc);
458
459	/** @cfgm{/HM/IBPBOnVMEntry, bool}
460	* Costly paranoia setting. */
461	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
462	AssertLogRelRCReturn(rc, rc);
463
464	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
465	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
466	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
467	AssertLogRelRCReturn(rc, rc);
468
469	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
470	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
471	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
472	AssertLogRelRCReturn(rc, rc);
473
474	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
475	if (pVM->hm.s.fL1dFlushOnVmEntry)
476	pVM->hm.s.fL1dFlushOnSched = false;
477
478	/** @cfgm{/HM/SpecCtrlByHost, bool}
479	* Another expensive paranoia setting. */
480	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
481	AssertLogRelRCReturn(rc, rc);
482
483	/** @cfgm{/HM/MDSClearOnSched, bool, true}
484	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
485	* ignored on CPUs that aren't affected. */
486	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
487	AssertLogRelRCReturn(rc, rc);
488
489	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
490	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
491	* ignored on CPUs that aren't affected. */
492	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
493	AssertLogRelRCReturn(rc, rc);
494
495	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
496	if (pVM->hm.s.fMdsClearOnVmEntry)
497	pVM->hm.s.fMdsClearOnSched = false;
498
499	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
500	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
501	* the hypervisor it is running under. */
502	bool f;
503	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
504	AssertLogRelRCReturn(rc, rc);
505	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
506	{
507	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
508	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
509	}
510
511	/*
512	* Check if VT-x or AMD-v support according to the users wishes.
513	*/
514	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
515	* VERR_SVM_IN_USE. */
516	if (pVM->fHMEnabled)
517	{
518	uint32_t fCaps;
519	rc = SUPR3QueryVTCaps(&fCaps);
520	if (RT_SUCCESS(rc))
521	{
522	if (fCaps & SUPVTCAPS_AMD_V)
523	{
524	pVM->hm.s.svm.fSupported = true;
525	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
526	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
527	}
528	else if (fCaps & SUPVTCAPS_VT_X)
529	{
530	const char *pszWhy;
531	rc = SUPR3QueryVTxSupported(&pszWhy);
532	if (RT_SUCCESS(rc))
533	{
534	pVM->hm.s.vmx.fSupported = true;
535	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
536	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
537	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
538	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
539	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
540	}
541	else
542	{
543	/*
544	* Before failing, try fallback to NEM if we're allowed to do that.
545	*/
546	pVM->fHMEnabled = false;
547	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
548	if (fFallbackToNEM)
549	{
550	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
551	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
552
553	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
554	if ( RT_SUCCESS(rc2)
555	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
556	rc = VINF_SUCCESS;
557	}
558	if (RT_FAILURE(rc))
559	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
560	}
561	}
562	else
563	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
564	VERR_INTERNAL_ERROR_5);
565
566	/*
567	* Disable nested paging and unrestricted guest execution now if they're
568	* configured so that CPUM can make decisions based on our configuration.
569	*/
570	Assert(!pVM->hm.s.fNestedPaging);
571	if (pVM->hm.s.fAllowNestedPaging)
572	{
573	if (fCaps & SUPVTCAPS_NESTED_PAGING)
574	pVM->hm.s.fNestedPaging = true;
575	else
576	pVM->hm.s.fAllowNestedPaging = false;
577	}
578
579	if (fCaps & SUPVTCAPS_VT_X)
580	{
581	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
582	if (pVM->hm.s.vmx.fAllowUnrestricted)
583	{
584	if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
585	&& pVM->hm.s.fNestedPaging)
586	pVM->hm.s.vmx.fUnrestrictedGuest = true;
587	else
588	pVM->hm.s.vmx.fAllowUnrestricted = false;
589	}
590	}
591	}
592	else
593	{
594	const char *pszMsg;
595	switch (rc)
596	{
597	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
598	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
599	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
600	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
601	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
602	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
603	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
604	default:
605	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
606	}
607
608	/*
609	* Before failing, try fallback to NEM if we're allowed to do that.
610	*/
611	pVM->fHMEnabled = false;
612	if (fFallbackToNEM)
613	{
614	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
615	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
616	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
617	if ( RT_SUCCESS(rc2)
618	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
619	rc = VINF_SUCCESS;
620	}
621	if (RT_FAILURE(rc))
622	return VM_SET_ERROR(pVM, rc, pszMsg);
623	}
624	}
625	else
626	{
627	/*
628	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
629	*/
630	if (fUseNEMInstead)
631	{
632	rc = NEMR3Init(pVM, false /fFallback/, true);
633	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
634	if (RT_FAILURE(rc))
635	return rc;
636	}
637	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
638	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
639	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
640	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
641	}
642
643	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
644	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
645	return VINF_SUCCESS;
646	}
647
648
649	/**
650	* Initializes HM components after ring-3 phase has been fully initialized.
651	*
652	* @returns VBox status code.
653	* @param pVM The cross context VM structure.
654	*/
655	static int hmR3InitFinalizeR3(PVM pVM)
656	{
657	LogFlowFunc(("\n"));
658
659	if (!HMIsEnabled(pVM))
660	return VINF_SUCCESS;
661
662	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
663	{
664	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
665	pVCpu->hm.s.fActive = false;
666	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
667	}
668
669	#ifdef VBOX_WITH_STATISTICS
670	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
671	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
672	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
673	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
674	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
675	#endif
676
677	/*
678	* Statistics.
679	*/
680	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
681	{
682	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
683	PHMCPU pHmCpu = &pVCpu->hm.s;
684	int rc;
685
686	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
687	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
688	AssertRC(rc); \
689	} while (0)
690	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
691	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
692
693	#ifdef VBOX_WITH_STATISTICS
694
695	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
696	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
697	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
698	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
699	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
700	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
701	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
702	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
703	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
704	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
705	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
706	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
707	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
708	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
709	# ifdef HM_PROFILE_EXIT_DISPATCH
710	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
711	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
712	# endif
713	#endif
714	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
715
716	#ifdef VBOX_WITH_STATISTICS
717	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
718	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
719	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
720	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
721	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
722	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
723	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
724	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
725	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
726	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
727	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
728	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
729	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
730	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
731	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
732	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
733	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
734	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
735	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
736	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
737	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
738	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
739	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
740	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
741	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
742	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
743	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
744	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
745	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
746	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
747	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
748	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
749	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
750	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
751	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
752	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
753	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
754	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
755	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
756	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
757	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
758	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
759	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
760	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
761	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
762	#endif
763	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
764	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
765	#ifdef VBOX_WITH_STATISTICS
766	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
767	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
768	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
769	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
770
771	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
772	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
773	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
774	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
775	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
776	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
777	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
778	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
779	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
780	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
781	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
782	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
783	#endif
784	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
785	#ifdef VBOX_WITH_STATISTICS
786	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
787
788	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
789	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
790	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
791	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
792	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
793	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
794
795	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
796	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
797	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
798	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
799	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
800	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
801	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
802	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
803	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
804	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
805	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
806	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
807	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
808	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
809	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
810
811	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
812	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
813	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
814
815	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
816	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
817	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
818
819	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
820	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
821	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
822	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
823
824	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
825	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
826	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
827
828	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
829	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
830	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
831
832	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
833	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
834	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
835	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
836
837	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
838
839	/*
840	* Guest Exit reason stats.
841	*/
842	pHmCpu->paStatExitReason = NULL;
843	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
844	(void **)&pHmCpu->paStatExitReason);
845	AssertRCReturn(rc, rc);
846
847	if (fCpuSupportsVmx)
848	{
849	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
850	{
851	const char *pszExitName = HMGetVmxExitName(j);
852	if (pszExitName)
853	{
854	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
855	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
856	AssertRCReturn(rc, rc);
857	}
858	}
859	}
860	else
861	{
862	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
863	{
864	const char *pszExitName = HMGetSvmExitName(j);
865	if (pszExitName)
866	{
867	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
868	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
869	AssertRC(rc);
870	}
871	}
872	}
873	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
874
875	pHmCpu->paStatExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatExitReason);
876	Assert(pHmCpu->paStatExitReasonR0 != NIL_RTR0PTR);
877
878	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
879	/*
880	* Nested-guest VM-exit reason stats.
881	*/
882	pHmCpu->paStatNestedExitReason = NULL;
883	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
884	(void **)&pHmCpu->paStatNestedExitReason);
885	AssertRCReturn(rc, rc);
886	if (fCpuSupportsVmx)
887	{
888	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
889	{
890	const char *pszExitName = HMGetVmxExitName(j);
891	if (pszExitName)
892	{
893	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
894	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
895	AssertRC(rc);
896	}
897	}
898	}
899	else
900	{
901	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
902	{
903	const char *pszExitName = HMGetSvmExitName(j);
904	if (pszExitName)
905	{
906	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
907	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
908	AssertRC(rc);
909	}
910	}
911	}
912	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
913	pHmCpu->paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatNestedExitReason);
914	Assert(pHmCpu->paStatNestedExitReasonR0 != NIL_RTR0PTR);
915	#endif
916
917	/*
918	* Injected interrupts stats.
919	*/
920	{
921	uint32_t const cInterrupts = 0xff + 1;
922	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cInterrupts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedIrqs);
923	AssertRCReturn(rc, rc);
924	pHmCpu->paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedIrqs);
925	Assert(pHmCpu->paStatInjectedIrqsR0 != NIL_RTR0PTR);
926	for (unsigned j = 0; j < cInterrupts; j++)
927	{
928	char aszIntrName[64];
929	RTStrPrintf(&aszIntrName[0], sizeof(aszIntrName), "Interrupt %u", j);
930	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
931	STAMUNIT_OCCURENCES, aszIntrName,
932	"/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
933	AssertRC(rc);
934	}
935	}
936
937	/*
938	* Injected exception stats.
939	*/
940	{
941	uint32_t const cXcpts = X86_XCPT_LAST + 1;
942	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cXcpts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedXcpts);
943	AssertRCReturn(rc, rc);
944	pHmCpu->paStatInjectedXcptsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedXcpts);
945	Assert(pHmCpu->paStatInjectedXcptsR0 != NIL_RTR0PTR);
946	for (unsigned j = 0; j < cXcpts; j++)
947	{
948	char aszXcptName[64];
949	RTStrPrintf(&aszXcptName[0], sizeof(aszXcptName), "%s exception", hmR3GetXcptName(j));
950	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
951	STAMUNIT_OCCURENCES, aszXcptName,
952	"/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
953	AssertRC(rc);
954	}
955	}
956
957	#endif /* VBOX_WITH_STATISTICS */
958	#undef HM_REG_COUNTER
959	#undef HM_REG_PROFILE
960	#undef HM_REG_STAT
961	}
962
963	return VINF_SUCCESS;
964	}
965
966
967	/**
968	* Called when a init phase has completed.
969	*
970	* @returns VBox status code.
971	* @param pVM The cross context VM structure.
972	* @param enmWhat The phase that completed.
973	*/
974	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
975	{
976	switch (enmWhat)
977	{
978	case VMINITCOMPLETED_RING3:
979	return hmR3InitFinalizeR3(pVM);
980	case VMINITCOMPLETED_RING0:
981	return hmR3InitFinalizeR0(pVM);
982	default:
983	return VINF_SUCCESS;
984	}
985	}
986
987
988	/**
989	* Turns off normal raw mode features.
990	*
991	* @param pVM The cross context VM structure.
992	*/
993	static void hmR3DisableRawMode(PVM pVM)
994	{
995	/** @todo r=bird: HM shouldn't be doing this crap. */
996	/* Reinit the paging mode to force the new shadow mode. */
997	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
998	{
999	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1000	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1001	}
1002	}
1003
1004
1005	/**
1006	* Initialize VT-x or AMD-V.
1007	*
1008	* @returns VBox status code.
1009	* @param pVM The cross context VM structure.
1010	*/
1011	static int hmR3InitFinalizeR0(PVM pVM)
1012	{
1013	int rc;
1014
1015	if (!HMIsEnabled(pVM))
1016	return VINF_SUCCESS;
1017
1018	/*
1019	* Hack to allow users to work around broken BIOSes that incorrectly set
1020	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1021	*/
1022	if ( !pVM->hm.s.vmx.fSupported
1023	&& !pVM->hm.s.svm.fSupported
1024	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1025	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1026	{
1027	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1028	pVM->hm.s.svm.fSupported = true;
1029	pVM->hm.s.svm.fIgnoreInUseError = true;
1030	pVM->hm.s.rcInit = VINF_SUCCESS;
1031	}
1032
1033	/*
1034	* Report ring-0 init errors.
1035	*/
1036	if ( !pVM->hm.s.vmx.fSupported
1037	&& !pVM->hm.s.svm.fSupported)
1038	{
1039	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1040	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1041	switch (pVM->hm.s.rcInit)
1042	{
1043	case VERR_VMX_IN_VMX_ROOT_MODE:
1044	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1045	case VERR_VMX_NO_VMX:
1046	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1047	case VERR_VMX_MSR_VMX_DISABLED:
1048	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1049	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1050	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1051	case VERR_VMX_MSR_LOCKING_FAILED:
1052	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1053	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1054	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1055	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1056	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1057
1058	case VERR_SVM_IN_USE:
1059	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1060	case VERR_SVM_NO_SVM:
1061	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1062	case VERR_SVM_DISABLED:
1063	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1064	}
1065	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1066	}
1067
1068	/*
1069	* Enable VT-x or AMD-V on all host CPUs.
1070	*/
1071	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1072	if (RT_FAILURE(rc))
1073	{
1074	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1075	HMR3CheckError(pVM, rc);
1076	return rc;
1077	}
1078
1079	/*
1080	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1081	* (Main should have taken care of this already)
1082	*/
1083	if (!PDMHasIoApic(pVM))
1084	{
1085	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1086	pVM->hm.s.fTprPatchingAllowed = false;
1087	}
1088
1089	/*
1090	* Check if L1D flush is needed/possible.
1091	*/
1092	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1093	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1094	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1095	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1096	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1097	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1098
1099	/*
1100	* Check if MDS flush is needed/possible.
1101	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1102	*/
1103	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1104	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1105	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1106	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1107	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1108	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1109	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1110	{
1111	if (!pVM->hm.s.fMdsClearOnSched)
1112	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1113	pVM->hm.s.fMdsClearOnVmEntry = false;
1114	}
1115	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1116	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1117	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1118
1119	/*
1120	* Sync options.
1121	*/
1122	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1123	* That will require a little bit of work, of course. */
1124	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1125	{
1126	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1127	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1128	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1129	if (pVM->cpum.ro.HostFeatures.fIbpb)
1130	{
1131	if (pVM->hm.s.fIbpbOnVmExit)
1132	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1133	if (pVM->hm.s.fIbpbOnVmEntry)
1134	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1135	}
1136	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1137	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1138	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1139	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1140	if (idCpu == 0)
1141	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1142	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1143	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1144	}
1145
1146	/*
1147	* Do the vendor specific initialization
1148	*
1149	* Note! We disable release log buffering here since we're doing relatively
1150	* lot of logging and doesn't want to hit the disk with each LogRel
1151	* statement.
1152	*/
1153	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1154	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1155	if (pVM->hm.s.vmx.fSupported)
1156	rc = hmR3InitFinalizeR0Intel(pVM);
1157	else
1158	rc = hmR3InitFinalizeR0Amd(pVM);
1159	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1160	: "HM: VT-x/AMD-V init method: Local\n"));
1161	RTLogRelSetBuffering(fOldBuffered);
1162	pVM->hm.s.fInitialized = true;
1163
1164	return rc;
1165	}
1166
1167
1168	/**
1169	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1170	*/
1171	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1172	{
1173	NOREF(pVM);
1174	NOREF(pvAllocation);
1175	NOREF(GCPhysAllocation);
1176	}
1177
1178
1179	/**
1180	* Returns a description of the VMCS (and associated regions') memory type given the
1181	* IA32_VMX_BASIC MSR.
1182	*
1183	* @returns The descriptive memory type.
1184	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1185	*/
1186	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1187	{
1188	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1189	switch (uMemType)
1190	{
1191	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1192	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1193	}
1194	return "Unknown";
1195	}
1196
1197
1198	/**
1199	* Returns a single-line description of all the activity-states supported by the CPU
1200	* given the IA32_VMX_MISC MSR.
1201	*
1202	* @returns All supported activity states.
1203	* @param uMsrMisc IA32_VMX_MISC MSR value.
1204	*/
1205	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1206	{
1207	static const char * const s_apszActStates[] =
1208	{
1209	"",
1210	" ( HLT )",
1211	" ( SHUTDOWN )",
1212	" ( HLT SHUTDOWN )",
1213	" ( SIPI_WAIT )",
1214	" ( HLT SIPI_WAIT )",
1215	" ( SHUTDOWN SIPI_WAIT )",
1216	" ( HLT SHUTDOWN SIPI_WAIT )"
1217	};
1218	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1219	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1220	return s_apszActStates[idxActStates];
1221	}
1222
1223
1224	/**
1225	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1226	*
1227	* @param fFeatMsr The feature control MSR value.
1228	*/
1229	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1230	{
1231	uint64_t const val = fFeatMsr;
1232	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1233	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1234	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1235	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1236	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1237	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1238	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1239	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1240	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1241	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1242	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1243	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1244	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1245	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1246	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1247	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1248	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1249	}
1250
1251
1252	/**
1253	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1254	*
1255	* @param uBasicMsr The VMX basic MSR value.
1256	*/
1257	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1258	{
1259	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1260	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1261	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1262	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1263	"< 4 GB" : "None"));
1264	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1265	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1266	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1267	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1268	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1269	}
1270
1271
1272	/**
1273	* Reports MSR_IA32_PINBASED_CTLS to the log.
1274	*
1275	* @param pVmxMsr Pointer to the VMX MSR.
1276	*/
1277	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1278	{
1279	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1280	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1281	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1282	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1283	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1284	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1285	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1286	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1287	}
1288
1289
1290	/**
1291	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1292	*
1293	* @param pVmxMsr Pointer to the VMX MSR.
1294	*/
1295	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1296	{
1297	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1298	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1299	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1321	}
1322
1323
1324	/**
1325	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1326	*
1327	* @param pVmxMsr Pointer to the VMX MSR.
1328	*/
1329	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1330	{
1331	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1332	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1333	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1355	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1357	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1358	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1359	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1361	}
1362
1363
1364	/**
1365	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1366	*
1367	* @param pVmxMsr Pointer to the VMX MSR.
1368	*/
1369	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1370	{
1371	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1372	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1373	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1384	}
1385
1386
1387	/**
1388	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1389	*
1390	* @param pVmxMsr Pointer to the VMX MSR.
1391	*/
1392	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1393	{
1394	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1395	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1396	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1409	}
1410
1411
1412	/**
1413	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1414	*
1415	* @param fCaps The VMX EPT/VPID capability MSR value.
1416	*/
1417	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1418	{
1419	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1420	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1421	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1424	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1425	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "SSS", MSR_IA32_VMX_EPT_VPID_CAP_SSS);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1434	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1435	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1436	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1437	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1438	}
1439
1440
1441	/**
1442	* Reports MSR_IA32_VMX_MISC MSR to the log.
1443	*
1444	* @param pVM Pointer to the VM.
1445	* @param fMisc The VMX misc. MSR value.
1446	*/
1447	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1448	{
1449	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1450	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1451	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1452	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1453	else
1454	{
1455	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1456	pVM->hm.s.vmx.cPreemptTimerShift));
1457	}
1458	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1459	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1460	hmR3VmxGetActivityStateAllDesc(fMisc)));
1461	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1462	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1463	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1464	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1465	VMX_MISC_MAX_MSRS(fMisc)));
1466	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1467	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1468	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1469	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1470	}
1471
1472
1473	/**
1474	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1475	*
1476	* @param uVmcsEnum The VMX VMCS enum MSR value.
1477	*/
1478	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1479	{
1480	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1481	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1482	}
1483
1484
1485	/**
1486	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1487	*
1488	* @param uVmFunc The VMX VMFUNC MSR value.
1489	*/
1490	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1491	{
1492	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1493	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1494	}
1495
1496
1497	/**
1498	* Reports VMX CR0, CR4 fixed MSRs.
1499	*
1500	* @param pMsrs Pointer to the VMX MSRs.
1501	*/
1502	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1503	{
1504	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1505	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1506	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1507	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1508	}
1509
1510
1511	/**
1512	* Finish VT-x initialization (after ring-0 init).
1513	*
1514	* @returns VBox status code.
1515	* @param pVM The cross context VM structure.
1516	*/
1517	static int hmR3InitFinalizeR0Intel(PVM pVM)
1518	{
1519	int rc;
1520
1521	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1522	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1523
1524	LogRel(("HM: Using VT-x implementation 3.0\n"));
1525	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1526	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1527	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1528	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1529
1530	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1531	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1532
1533	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1534	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1535	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1536	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1537
1538	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1539	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1540
1541	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1542	{
1543	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1544	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1545	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1546	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1547	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1548	}
1549
1550	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1551	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1552	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1553	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1554	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1555	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1556	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1557
1558	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1559	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1560	{
1561	PCVMXVMCSINFO pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1562	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1563	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1564	}
1565	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1566	if (pVM->cpum.ro.GuestFeatures.fVmx)
1567	{
1568	LogRel(("HM: Nested-guest:\n"));
1569	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1570	{
1571	PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1572	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1573	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1574	}
1575	}
1576	#endif
1577
1578	/*
1579	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1580	*/
1581	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1582	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1583	VERR_HM_IPE_1);
1584	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1585	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1586	&& pVM->hm.s.fNestedPaging),
1587	VERR_HM_IPE_1);
1588
1589	/*
1590	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1591	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1592	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1593	*/
1594	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1595	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1596	{
1597	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1598	LogRel(("HM: Disabled RDTSCP\n"));
1599	}
1600
1601	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1602	{
1603	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1604	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1605	if (RT_SUCCESS(rc))
1606	{
1607	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1608	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1609	esp. Figure 20-5.*/
1610	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1611	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1612
1613	/* Bit set to 0 means software interrupts are redirected to the
1614	8086 program interrupt handler rather than switching to
1615	protected-mode handler. */
1616	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1617
1618	/* Allow all port IO, so that port IO instructions do not cause
1619	exceptions and would instead cause a VM-exit (based on VT-x's
1620	IO bitmap which we currently configure to always cause an exit). */
1621	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1622	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1623
1624	/*
1625	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1626	* page table used in real and protected mode without paging with EPT.
1627	*/
1628	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1629	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1630	{
1631	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1632	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1633	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1634	\| X86_PDE4M_G;
1635	}
1636
1637	/* We convert it here every time as PCI regions could be reconfigured. */
1638	if (PDMVmmDevHeapIsEnabled(pVM))
1639	{
1640	RTGCPHYS GCPhys;
1641	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1642	AssertRCReturn(rc, rc);
1643	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1644
1645	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1646	AssertRCReturn(rc, rc);
1647	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1648	}
1649	}
1650	else
1651	{
1652	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1653	pVM->hm.s.vmx.pRealModeTSS = NULL;
1654	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1655	return VMSetError(pVM, rc, RT_SRC_POS,
1656	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1657	}
1658	}
1659
1660	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1661	: "HM: Guest support: 32-bit only\n"));
1662
1663	/*
1664	* Call ring-0 to set up the VM.
1665	*/
1666	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1667	if (rc != VINF_SUCCESS)
1668	{
1669	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1670	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1671	{
1672	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1673	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1674	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1675	}
1676	HMR3CheckError(pVM, rc);
1677	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1678	}
1679
1680	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1681	LogRel(("HM: Enabled VMX\n"));
1682	pVM->hm.s.vmx.fEnabled = true;
1683
1684	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1685
1686	/*
1687	* Change the CPU features.
1688	*/
1689	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1690	if (pVM->hm.s.fAllow64BitGuests)
1691	{
1692	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1693	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1694	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1695	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1696	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1697	}
1698	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1699	(we reuse the host EFER in the switcher). */
1700	/** @todo this needs to be fixed properly!! */
1701	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1702	{
1703	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1704	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1705	else
1706	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1707	}
1708
1709	/*
1710	* Log configuration details.
1711	*/
1712	if (pVM->hm.s.fNestedPaging)
1713	{
1714	LogRel(("HM: Enabled nested paging\n"));
1715	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1716	LogRel(("HM: EPT flush type = Single context\n"));
1717	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1718	LogRel(("HM: EPT flush type = All contexts\n"));
1719	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1720	LogRel(("HM: EPT flush type = Not supported\n"));
1721	else
1722	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1723
1724	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1725	LogRel(("HM: Enabled unrestricted guest execution\n"));
1726
1727	if (pVM->hm.s.fLargePages)
1728	{
1729	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1730	PGMSetLargePageUsage(pVM, true);
1731	LogRel(("HM: Enabled large page support\n"));
1732	}
1733	}
1734	else
1735	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1736
1737	if (pVM->hm.s.vmx.fVpid)
1738	{
1739	LogRel(("HM: Enabled VPID\n"));
1740	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1741	LogRel(("HM: VPID flush type = Individual addresses\n"));
1742	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1743	LogRel(("HM: VPID flush type = Single context\n"));
1744	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1745	LogRel(("HM: VPID flush type = All contexts\n"));
1746	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1747	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1748	else
1749	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1750	}
1751	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1752	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1753
1754	if (pVM->hm.s.vmx.fUsePreemptTimer)
1755	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1756	else
1757	LogRel(("HM: Disabled VMX-preemption timer\n"));
1758
1759	if (pVM->hm.s.fVirtApicRegs)
1760	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1761
1762	if (pVM->hm.s.fPostedIntrs)
1763	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1764
1765	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1766	{
1767	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1768	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1769	}
1770
1771	return VINF_SUCCESS;
1772	}
1773
1774
1775	/**
1776	* Finish AMD-V initialization (after ring-0 init).
1777	*
1778	* @returns VBox status code.
1779	* @param pVM The cross context VM structure.
1780	*/
1781	static int hmR3InitFinalizeR0Amd(PVM pVM)
1782	{
1783	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1784
1785	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1786
1787	uint32_t u32Family;
1788	uint32_t u32Model;
1789	uint32_t u32Stepping;
1790	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1791	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1792	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1793	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1794	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1795	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1796	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1797
1798	/*
1799	* Enumerate AMD-V features.
1800	*/
1801	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1802	{
1803	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1804	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1805	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1806	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1807	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1808	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1809	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1810	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1811	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1812	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1813	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1814	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1815	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1816	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1817	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1818	#undef HMSVM_REPORT_FEATURE
1819	};
1820
1821	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1822	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1823	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1824	{
1825	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1826	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1827	}
1828	if (fSvmFeatures)
1829	for (unsigned iBit = 0; iBit < 32; iBit++)
1830	if (RT_BIT_32(iBit) & fSvmFeatures)
1831	LogRel(("HM: Reserved bit %u\n", iBit));
1832
1833	/*
1834	* Nested paging is determined in HMR3Init, verify the sanity of that.
1835	*/
1836	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1837	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1838	VERR_HM_IPE_1);
1839
1840	#if 0
1841	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1842	* here. */
1843	if (RTR0IsPostIpiSupport())
1844	pVM->hm.s.fPostedIntrs = true;
1845	#endif
1846
1847	/*
1848	* Call ring-0 to set up the VM.
1849	*/
1850	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1851	if (rc != VINF_SUCCESS)
1852	{
1853	AssertMsgFailed(("%Rrc\n", rc));
1854	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1855	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1856	}
1857
1858	LogRel(("HM: Enabled SVM\n"));
1859	pVM->hm.s.svm.fEnabled = true;
1860
1861	if (pVM->hm.s.fNestedPaging)
1862	{
1863	LogRel(("HM: Enabled nested paging\n"));
1864
1865	/*
1866	* Enable large pages (2 MB) if applicable.
1867	*/
1868	if (pVM->hm.s.fLargePages)
1869	{
1870	PGMSetLargePageUsage(pVM, true);
1871	LogRel(("HM: Enabled large page support\n"));
1872	}
1873	}
1874
1875	if (pVM->hm.s.fVirtApicRegs)
1876	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1877
1878	if (pVM->hm.s.fPostedIntrs)
1879	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1880
1881	hmR3DisableRawMode(pVM);
1882
1883	/*
1884	* Change the CPU features.
1885	*/
1886	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1887	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1888	if (pVM->hm.s.fAllow64BitGuests)
1889	{
1890	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1891	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1892	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1893	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1894	}
1895	/* Turn on NXE if PAE has been enabled. */
1896	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1897	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1898
1899	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1900	: "HM: Disabled TPR patching\n"));
1901
1902	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1903	: "HM: Guest support: 32-bit only\n"));
1904	return VINF_SUCCESS;
1905	}
1906
1907
1908	/**
1909	* Applies relocations to data and code managed by this
1910	* component. This function will be called at init and
1911	* whenever the VMM need to relocate it self inside the GC.
1912	*
1913	* @param pVM The cross context VM structure.
1914	*/
1915	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1916	{
1917	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1918
1919	/* Fetch the current paging mode during the relocate callback during state loading. */
1920	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1921	{
1922	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1923	{
1924	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1925	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1926	}
1927	}
1928	}
1929
1930
1931	/**
1932	* Terminates the HM.
1933	*
1934	* Termination means cleaning up and freeing all resources,
1935	* the VM itself is, at this point, powered off or suspended.
1936	*
1937	* @returns VBox status code.
1938	* @param pVM The cross context VM structure.
1939	*/
1940	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1941	{
1942	if (pVM->hm.s.vmx.pRealModeTSS)
1943	{
1944	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1945	pVM->hm.s.vmx.pRealModeTSS = 0;
1946	}
1947	hmR3TermCPU(pVM);
1948	return 0;
1949	}
1950
1951
1952	/**
1953	* Terminates the per-VCPU HM.
1954	*
1955	* @returns VBox status code.
1956	* @param pVM The cross context VM structure.
1957	*/
1958	static int hmR3TermCPU(PVM pVM)
1959	{
1960	#ifdef VBOX_WITH_STATISTICS
1961	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1962	{
1963	PVMCPU pVCpu = pVM->apCpusR3[idCpu]; NOREF(pVCpu);
1964	if (pVCpu->hm.s.paStatExitReason)
1965	{
1966	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1967	pVCpu->hm.s.paStatExitReason = NULL;
1968	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1969	}
1970	if (pVCpu->hm.s.paStatInjectedIrqs)
1971	{
1972	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1973	pVCpu->hm.s.paStatInjectedIrqs = NULL;
1974	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1975	}
1976	if (pVCpu->hm.s.paStatInjectedXcpts)
1977	{
1978	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedXcpts);
1979	pVCpu->hm.s.paStatInjectedXcpts = NULL;
1980	pVCpu->hm.s.paStatInjectedXcptsR0 = NIL_RTR0PTR;
1981	}
1982	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1983	if (pVCpu->hm.s.paStatNestedExitReason)
1984	{
1985	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
1986	pVCpu->hm.s.paStatNestedExitReason = NULL;
1987	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
1988	}
1989	# endif
1990	}
1991	#else
1992	RT_NOREF(pVM);
1993	#endif
1994	return VINF_SUCCESS;
1995	}
1996
1997
1998	/**
1999	* Resets a virtual CPU.
2000	*
2001	* Used by HMR3Reset and CPU hot plugging.
2002	*
2003	* @param pVCpu The cross context virtual CPU structure to reset.
2004	*/
2005	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2006	{
2007	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2008	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2009	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2010
2011	pVCpu->hm.s.fActive = false;
2012	pVCpu->hm.s.Event.fPending = false;
2013	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2014	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
2015	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2016	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2017	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2018	{
2019	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
2020	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2021	}
2022	#endif
2023	}
2024
2025
2026	/**
2027	* The VM is being reset.
2028	*
2029	* For the HM component this means that any GDT/LDT/TSS monitors
2030	* needs to be removed.
2031	*
2032	* @param pVM The cross context VM structure.
2033	*/
2034	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2035	{
2036	LogFlow(("HMR3Reset:\n"));
2037
2038	if (HMIsEnabled(pVM))
2039	hmR3DisableRawMode(pVM);
2040
2041	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2042	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2043
2044	/* Clear all patch information. */
2045	pVM->hm.s.pGuestPatchMem = 0;
2046	pVM->hm.s.pFreeGuestPatchMem = 0;
2047	pVM->hm.s.cbGuestPatchMem = 0;
2048	pVM->hm.s.cPatches = 0;
2049	pVM->hm.s.PatchTree = 0;
2050	pVM->hm.s.fTPRPatchingActive = false;
2051	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2052	}
2053
2054
2055	/**
2056	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2057	*
2058	* @returns VBox strict status code.
2059	* @param pVM The cross context VM structure.
2060	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2061	* @param pvUser Unused.
2062	*/
2063	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2064	{
2065	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2066
2067	/* Only execute the handler on the VCPU the original patch request was issued. */
2068	if (pVCpu->idCpu != idCpu)
2069	return VINF_SUCCESS;
2070
2071	Log(("hmR3RemovePatches\n"));
2072	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2073	{
2074	uint8_t abInstr[15];
2075	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2076	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2077	int rc;
2078
2079	#ifdef LOG_ENABLED
2080	char szOutput[256];
2081	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2082	szOutput, sizeof(szOutput), NULL);
2083	if (RT_SUCCESS(rc))
2084	Log(("Patched instr: %s\n", szOutput));
2085	#endif
2086
2087	/* Check if the instruction is still the same. */
2088	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2089	if (rc != VINF_SUCCESS)
2090	{
2091	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2092	continue; /* swapped out or otherwise removed; skip it. */
2093	}
2094
2095	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2096	{
2097	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2098	continue; /* skip it. */
2099	}
2100
2101	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2102	AssertRC(rc);
2103
2104	#ifdef LOG_ENABLED
2105	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2106	szOutput, sizeof(szOutput), NULL);
2107	if (RT_SUCCESS(rc))
2108	Log(("Original instr: %s\n", szOutput));
2109	#endif
2110	}
2111	pVM->hm.s.cPatches = 0;
2112	pVM->hm.s.PatchTree = 0;
2113	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2114	pVM->hm.s.fTPRPatchingActive = false;
2115	return VINF_SUCCESS;
2116	}
2117
2118
2119	/**
2120	* Worker for enabling patching in a VT-x/AMD-V guest.
2121	*
2122	* @returns VBox status code.
2123	* @param pVM The cross context VM structure.
2124	* @param idCpu VCPU to execute hmR3RemovePatches on.
2125	* @param pPatchMem Patch memory range.
2126	* @param cbPatchMem Size of the memory range.
2127	*/
2128	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2129	{
2130	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2131	AssertRC(rc);
2132
2133	pVM->hm.s.pGuestPatchMem = pPatchMem;
2134	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2135	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2136	return VINF_SUCCESS;
2137	}
2138
2139
2140	/**
2141	* Enable patching in a VT-x/AMD-V guest
2142	*
2143	* @returns VBox status code.
2144	* @param pVM The cross context VM structure.
2145	* @param pPatchMem Patch memory range.
2146	* @param cbPatchMem Size of the memory range.
2147	*/
2148	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2149	{
2150	VM_ASSERT_EMT(pVM);
2151	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2152	if (pVM->cCpus > 1)
2153	{
2154	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2155	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2156	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2157	AssertRC(rc);
2158	return rc;
2159	}
2160	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2161	}
2162
2163
2164	/**
2165	* Disable patching in a VT-x/AMD-V guest.
2166	*
2167	* @returns VBox status code.
2168	* @param pVM The cross context VM structure.
2169	* @param pPatchMem Patch memory range.
2170	* @param cbPatchMem Size of the memory range.
2171	*/
2172	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2173	{
2174	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2175	RT_NOREF2(pPatchMem, cbPatchMem);
2176
2177	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2178	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2179
2180	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2181	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2182	(void *)(uintptr_t)VMMGetCpuId(pVM));
2183	AssertRC(rc);
2184
2185	pVM->hm.s.pGuestPatchMem = 0;
2186	pVM->hm.s.pFreeGuestPatchMem = 0;
2187	pVM->hm.s.cbGuestPatchMem = 0;
2188	pVM->hm.s.fTPRPatchingActive = false;
2189	return VINF_SUCCESS;
2190	}
2191
2192
2193	/**
2194	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2195	*
2196	* @returns VBox strict status code.
2197	* @param pVM The cross context VM structure.
2198	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2199	* @param pvUser User specified CPU context.
2200	*
2201	*/
2202	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2203	{
2204	/*
2205	* Only execute the handler on the VCPU the original patch request was
2206	* issued. (The other CPU(s) might not yet have switched to protected
2207	* mode, nor have the correct memory context.)
2208	*/
2209	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2210	if (pVCpu->idCpu != idCpu)
2211	return VINF_SUCCESS;
2212
2213	/*
2214	* We're racing other VCPUs here, so don't try patch the instruction twice
2215	* and make sure there is still room for our patch record.
2216	*/
2217	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2218	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2219	if (pPatch)
2220	{
2221	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2222	return VINF_SUCCESS;
2223	}
2224	uint32_t const idx = pVM->hm.s.cPatches;
2225	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2226	{
2227	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2228	return VINF_SUCCESS;
2229	}
2230	pPatch = &pVM->hm.s.aPatches[idx];
2231
2232	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2233
2234	/*
2235	* Disassembler the instruction and get cracking.
2236	*/
2237	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2238	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2239	uint32_t cbOp;
2240	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2241	AssertRC(rc);
2242	if ( rc == VINF_SUCCESS
2243	&& pDis->pCurInstr->uOpcode == OP_MOV
2244	&& cbOp >= 3)
2245	{
2246	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2247
2248	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2249	AssertRC(rc);
2250
2251	pPatch->cbOp = cbOp;
2252
2253	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2254	{
2255	/* write. */
2256	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2257	{
2258	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2259	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2260	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2261	}
2262	else
2263	{
2264	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2265	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2266	pPatch->uSrcOperand = pDis->Param2.uValue;
2267	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2268	}
2269	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2270	AssertRC(rc);
2271
2272	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2273	pPatch->cbNewOp = sizeof(s_abVMMCall);
2274	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2275	}
2276	else
2277	{
2278	/*
2279	* TPR Read.
2280	*
2281	* Found:
2282	* mov eax, dword [fffe0080] (5 bytes)
2283	* Check if next instruction is:
2284	* shr eax, 4
2285	*/
2286	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2287
2288	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2289	uint8_t const cbOpMmio = cbOp;
2290	uint64_t const uSavedRip = pCtx->rip;
2291
2292	pCtx->rip += cbOp;
2293	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2294	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2295	pCtx->rip = uSavedRip;
2296
2297	if ( rc == VINF_SUCCESS
2298	&& pDis->pCurInstr->uOpcode == OP_SHR
2299	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2300	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2301	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2302	&& pDis->Param2.uValue == 4
2303	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2304	{
2305	uint8_t abInstr[15];
2306
2307	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2308	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2309	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2310	AssertRC(rc);
2311
2312	pPatch->cbOp = cbOpMmio + cbOp;
2313
2314	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2315	abInstr[0] = 0xf0;
2316	abInstr[1] = 0x0f;
2317	abInstr[2] = 0x20;
2318	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2319	for (unsigned i = 4; i < pPatch->cbOp; i++)
2320	abInstr[i] = 0x90; /* nop */
2321
2322	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2323	AssertRC(rc);
2324
2325	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2326	pPatch->cbNewOp = pPatch->cbOp;
2327	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2328
2329	Log(("Acceptable read/shr candidate!\n"));
2330	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2331	}
2332	else
2333	{
2334	pPatch->enmType = HMTPRINSTR_READ;
2335	pPatch->uDstOperand = idxMmioReg;
2336
2337	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2338	AssertRC(rc);
2339
2340	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2341	pPatch->cbNewOp = sizeof(s_abVMMCall);
2342	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2343	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2344	}
2345	}
2346
2347	pPatch->Core.Key = pCtx->eip;
2348	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2349	AssertRC(rc);
2350
2351	pVM->hm.s.cPatches++;
2352	return VINF_SUCCESS;
2353	}
2354
2355	/*
2356	* Save invalid patch, so we will not try again.
2357	*/
2358	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2359	pPatch->Core.Key = pCtx->eip;
2360	pPatch->enmType = HMTPRINSTR_INVALID;
2361	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2362	AssertRC(rc);
2363	pVM->hm.s.cPatches++;
2364	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2365	return VINF_SUCCESS;
2366	}
2367
2368
2369	/**
2370	* Callback to patch a TPR instruction (jump to generated code).
2371	*
2372	* @returns VBox strict status code.
2373	* @param pVM The cross context VM structure.
2374	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2375	* @param pvUser User specified CPU context.
2376	*
2377	*/
2378	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2379	{
2380	/*
2381	* Only execute the handler on the VCPU the original patch request was
2382	* issued. (The other CPU(s) might not yet have switched to protected
2383	* mode, nor have the correct memory context.)
2384	*/
2385	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2386	if (pVCpu->idCpu != idCpu)
2387	return VINF_SUCCESS;
2388
2389	/*
2390	* We're racing other VCPUs here, so don't try patch the instruction twice
2391	* and make sure there is still room for our patch record.
2392	*/
2393	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2394	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2395	if (pPatch)
2396	{
2397	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2398	return VINF_SUCCESS;
2399	}
2400	uint32_t const idx = pVM->hm.s.cPatches;
2401	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2402	{
2403	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2404	return VINF_SUCCESS;
2405	}
2406	pPatch = &pVM->hm.s.aPatches[idx];
2407
2408	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2409	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2410
2411	/*
2412	* Disassemble the instruction and get cracking.
2413	*/
2414	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2415	uint32_t cbOp;
2416	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2417	AssertRC(rc);
2418	if ( rc == VINF_SUCCESS
2419	&& pDis->pCurInstr->uOpcode == OP_MOV
2420	&& cbOp >= 5)
2421	{
2422	uint8_t aPatch[64];
2423	uint32_t off = 0;
2424
2425	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2426	AssertRC(rc);
2427
2428	pPatch->cbOp = cbOp;
2429	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2430
2431	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2432	{
2433	/*
2434	* TPR write:
2435	*
2436	* push ECX [51]
2437	* push EDX [52]
2438	* push EAX [50]
2439	* xor EDX,EDX [31 D2]
2440	* mov EAX,EAX [89 C0]
2441	* or
2442	* mov EAX,0000000CCh [B8 CC 00 00 00]
2443	* mov ECX,0C0000082h [B9 82 00 00 C0]
2444	* wrmsr [0F 30]
2445	* pop EAX [58]
2446	* pop EDX [5A]
2447	* pop ECX [59]
2448	* jmp return_address [E9 return_address]
2449	*/
2450	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2451
2452	aPatch[off++] = 0x51; /* push ecx */
2453	aPatch[off++] = 0x52; /* push edx */
2454	if (!fUsesEax)
2455	aPatch[off++] = 0x50; /* push eax */
2456	aPatch[off++] = 0x31; /* xor edx, edx */
2457	aPatch[off++] = 0xd2;
2458	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2459	{
2460	if (!fUsesEax)
2461	{
2462	aPatch[off++] = 0x89; /* mov eax, src_reg */
2463	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2464	}
2465	}
2466	else
2467	{
2468	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2469	aPatch[off++] = 0xb8; /* mov eax, immediate */
2470	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2471	off += sizeof(uint32_t);
2472	}
2473	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2474	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2475	off += sizeof(uint32_t);
2476
2477	aPatch[off++] = 0x0f; /* wrmsr */
2478	aPatch[off++] = 0x30;
2479	if (!fUsesEax)
2480	aPatch[off++] = 0x58; /* pop eax */
2481	aPatch[off++] = 0x5a; /* pop edx */
2482	aPatch[off++] = 0x59; /* pop ecx */
2483	}
2484	else
2485	{
2486	/*
2487	* TPR read:
2488	*
2489	* push ECX [51]
2490	* push EDX [52]
2491	* push EAX [50]
2492	* mov ECX,0C0000082h [B9 82 00 00 C0]
2493	* rdmsr [0F 32]
2494	* mov EAX,EAX [89 C0]
2495	* pop EAX [58]
2496	* pop EDX [5A]
2497	* pop ECX [59]
2498	* jmp return_address [E9 return_address]
2499	*/
2500	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2501
2502	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2503	aPatch[off++] = 0x51; /* push ecx */
2504	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2505	aPatch[off++] = 0x52; /* push edx */
2506	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2507	aPatch[off++] = 0x50; /* push eax */
2508
2509	aPatch[off++] = 0x31; /* xor edx, edx */
2510	aPatch[off++] = 0xd2;
2511
2512	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2513	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2514	off += sizeof(uint32_t);
2515
2516	aPatch[off++] = 0x0f; /* rdmsr */
2517	aPatch[off++] = 0x32;
2518
2519	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2520	{
2521	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2522	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2523	}
2524
2525	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2526	aPatch[off++] = 0x58; /* pop eax */
2527	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2528	aPatch[off++] = 0x5a; /* pop edx */
2529	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2530	aPatch[off++] = 0x59; /* pop ecx */
2531	}
2532	aPatch[off++] = 0xe9; /* jmp return_address */
2533	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2534	off += sizeof(RTRCUINTPTR);
2535
2536	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2537	{
2538	/* Write new code to the patch buffer. */
2539	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2540	AssertRC(rc);
2541
2542	#ifdef LOG_ENABLED
2543	uint32_t cbCurInstr;
2544	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2545	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2546	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2547	{
2548	char szOutput[256];
2549	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2550	szOutput, sizeof(szOutput), &cbCurInstr);
2551	if (RT_SUCCESS(rc))
2552	Log(("Patch instr %s\n", szOutput));
2553	else
2554	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2555	}
2556	#endif
2557
2558	pPatch->aNewOpcode[0] = 0xE9;
2559	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2560
2561	/* Overwrite the TPR instruction with a jump. */
2562	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2563	AssertRC(rc);
2564
2565	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2566
2567	pVM->hm.s.pFreeGuestPatchMem += off;
2568	pPatch->cbNewOp = 5;
2569
2570	pPatch->Core.Key = pCtx->eip;
2571	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2572	AssertRC(rc);
2573
2574	pVM->hm.s.cPatches++;
2575	pVM->hm.s.fTPRPatchingActive = true;
2576	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2577	return VINF_SUCCESS;
2578	}
2579
2580	Log(("Ran out of space in our patch buffer!\n"));
2581	}
2582	else
2583	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2584
2585
2586	/*
2587	* Save invalid patch, so we will not try again.
2588	*/
2589	pPatch = &pVM->hm.s.aPatches[idx];
2590	pPatch->Core.Key = pCtx->eip;
2591	pPatch->enmType = HMTPRINSTR_INVALID;
2592	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2593	AssertRC(rc);
2594	pVM->hm.s.cPatches++;
2595	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2596	return VINF_SUCCESS;
2597	}
2598
2599
2600	/**
2601	* Attempt to patch TPR mmio instructions.
2602	*
2603	* @returns VBox status code.
2604	* @param pVM The cross context VM structure.
2605	* @param pVCpu The cross context virtual CPU structure.
2606	*/
2607	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2608	{
2609	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2610	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2611	(void *)(uintptr_t)pVCpu->idCpu);
2612	AssertRC(rc);
2613	return rc;
2614	}
2615
2616
2617	/**
2618	* Checks if we need to reschedule due to VMM device heap changes.
2619	*
2620	* @returns true if a reschedule is required, otherwise false.
2621	* @param pVM The cross context VM structure.
2622	* @param pCtx VM execution context.
2623	*/
2624	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2625	{
2626	/*
2627	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2628	* when the unrestricted guest execution feature is missing (VT-x only).
2629	*/
2630	if ( pVM->hm.s.vmx.fEnabled
2631	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2632	&& CPUMIsGuestInRealModeEx(pCtx)
2633	&& !PDMVmmDevHeapIsEnabled(pVM))
2634	return true;
2635
2636	return false;
2637	}
2638
2639
2640	/**
2641	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2642	* event settings changes.
2643	*
2644	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2645	* function is just updating the VM globals.
2646	*
2647	* @param pVM The VM cross context VM structure.
2648	* @thread EMT(0)
2649	*/
2650	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2651	{
2652	/* Interrupts. */
2653	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2654	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2655
2656	/* CPU Exceptions. */
2657	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2658	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2659	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2660	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2661
2662	/* Common VM exits. */
2663	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2664	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2665	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2666	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2667
2668	/* Vendor specific VM exits. */
2669	if (HMR3IsVmxEnabled(pVM->pUVM))
2670	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2671	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2672	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2673	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2674	else
2675	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2676	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2677	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2678	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2679
2680	/* Done. */
2681	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2682	}
2683
2684
2685	/**
2686	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2687	*
2688	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2689	* per CPU settings.
2690	*
2691	* @param pVM The VM cross context VM structure.
2692	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2693	*/
2694	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2695	{
2696	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2697	}
2698
2699
2700	/**
2701	* Checks if we are currently using hardware acceleration.
2702	*
2703	* @returns true if hardware acceleration is being used, otherwise false.
2704	* @param pVCpu The cross context virtual CPU structure.
2705	*/
2706	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2707	{
2708	return pVCpu->hm.s.fActive;
2709	}
2710
2711
2712	/**
2713	* External interface for querying whether hardware acceleration is enabled.
2714	*
2715	* @returns true if VT-x or AMD-V is being used, otherwise false.
2716	* @param pUVM The user mode VM handle.
2717	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2718	*/
2719	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2720	{
2721	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2722	PVM pVM = pUVM->pVM;
2723	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2724	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2725	}
2726
2727
2728	/**
2729	* External interface for querying whether VT-x is being used.
2730	*
2731	* @returns true if VT-x is being used, otherwise false.
2732	* @param pUVM The user mode VM handle.
2733	* @sa HMR3IsSvmEnabled, HMIsEnabled
2734	*/
2735	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2736	{
2737	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2738	PVM pVM = pUVM->pVM;
2739	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2740	return pVM->hm.s.vmx.fEnabled
2741	&& pVM->hm.s.vmx.fSupported
2742	&& pVM->fHMEnabled;
2743	}
2744
2745
2746	/**
2747	* External interface for querying whether AMD-V is being used.
2748	*
2749	* @returns true if VT-x is being used, otherwise false.
2750	* @param pUVM The user mode VM handle.
2751	* @sa HMR3IsVmxEnabled, HMIsEnabled
2752	*/
2753	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2754	{
2755	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2756	PVM pVM = pUVM->pVM;
2757	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2758	return pVM->hm.s.svm.fEnabled
2759	&& pVM->hm.s.svm.fSupported
2760	&& pVM->fHMEnabled;
2761	}
2762
2763
2764	/**
2765	* Checks if we are currently using nested paging.
2766	*
2767	* @returns true if nested paging is being used, otherwise false.
2768	* @param pUVM The user mode VM handle.
2769	*/
2770	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2771	{
2772	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2773	PVM pVM = pUVM->pVM;
2774	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2775	return pVM->hm.s.fNestedPaging;
2776	}
2777
2778
2779	/**
2780	* Checks if virtualized APIC registers is enabled.
2781	*
2782	* When enabled this feature allows the hardware to access most of the
2783	* APIC registers in the virtual-APIC page without causing VM-exits. See
2784	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2785	*
2786	* @returns true if virtualized APIC registers is enabled, otherwise
2787	* false.
2788	* @param pUVM The user mode VM handle.
2789	*/
2790	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2791	{
2792	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2793	PVM pVM = pUVM->pVM;
2794	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2795	return pVM->hm.s.fVirtApicRegs;
2796	}
2797
2798
2799	/**
2800	* Checks if APIC posted-interrupt processing is enabled.
2801	*
2802	* This returns whether we can deliver interrupts to the guest without
2803	* leaving guest-context by updating APIC state from host-context.
2804	*
2805	* @returns true if APIC posted-interrupt processing is enabled,
2806	* otherwise false.
2807	* @param pUVM The user mode VM handle.
2808	*/
2809	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2810	{
2811	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2812	PVM pVM = pUVM->pVM;
2813	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2814	return pVM->hm.s.fPostedIntrs;
2815	}
2816
2817
2818	/**
2819	* Checks if we are currently using VPID in VT-x mode.
2820	*
2821	* @returns true if VPID is being used, otherwise false.
2822	* @param pUVM The user mode VM handle.
2823	*/
2824	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2825	{
2826	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2827	PVM pVM = pUVM->pVM;
2828	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2829	return pVM->hm.s.vmx.fVpid;
2830	}
2831
2832
2833	/**
2834	* Checks if we are currently using VT-x unrestricted execution,
2835	* aka UX.
2836	*
2837	* @returns true if UX is being used, otherwise false.
2838	* @param pUVM The user mode VM handle.
2839	*/
2840	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2841	{
2842	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2843	PVM pVM = pUVM->pVM;
2844	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2845	return pVM->hm.s.vmx.fUnrestrictedGuest
2846	\|\| pVM->hm.s.svm.fSupported;
2847	}
2848
2849
2850	/**
2851	* Checks if the VMX-preemption timer is being used.
2852	*
2853	* @returns true if the VMX-preemption timer is being used, otherwise false.
2854	* @param pVM The cross context VM structure.
2855	*/
2856	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2857	{
2858	return HMIsEnabled(pVM)
2859	&& pVM->hm.s.vmx.fEnabled
2860	&& pVM->hm.s.vmx.fUsePreemptTimer;
2861	}
2862
2863
2864	/**
2865	* Helper for HMR3CheckError to log VMCS controls to the release log.
2866	*
2867	* @param idCpu The Virtual CPU ID.
2868	* @param pVmcsInfo The VMCS info. object.
2869	*/
2870	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2871	{
2872	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2873	{
2874	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2875	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2876	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2877	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2878	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2880	}
2881	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2882	{
2883	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2894	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2895	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2896	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2897	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2905	}
2906	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2907	{
2908	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2936	}
2937	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2938	{
2939	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2950	}
2951	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2952	{
2953	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2966	}
2967	}
2968
2969
2970	/**
2971	* Check fatal VT-x/AMD-V error and produce some meaningful
2972	* log release message.
2973	*
2974	* @param pVM The cross context VM structure.
2975	* @param iStatusCode VBox status code.
2976	*/
2977	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2978	{
2979	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2980	{
2981	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2982	* might be getting inaccurate values for non-guru'ing EMTs. */
2983	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2984	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
2985	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
2986	switch (iStatusCode)
2987	{
2988	case VERR_VMX_INVALID_VMCS_PTR:
2989	{
2990	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2991	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2992	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2993	pVmcsInfo->HCPhysVmcs));
2994	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2995	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2996	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2997	break;
2998	}
2999
3000	case VERR_VMX_UNABLE_TO_START_VM:
3001	{
3002	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3003	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3004	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3005	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3006
3007	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3008	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3009	{
3010	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3011	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3012	}
3013	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3014	{
3015	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3016	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3017	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3018	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3019	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3020	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3021	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3022	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3023	}
3024	/** @todo Log VM-entry event injection control fields
3025	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3026	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3027	break;
3028	}
3029
3030	case VERR_VMX_INVALID_GUEST_STATE:
3031	{
3032	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3033	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3034	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3035	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3036	break;
3037	}
3038
3039	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3040	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3041	case VERR_VMX_INVALID_VMXON_PTR:
3042	case VERR_VMX_UNEXPECTED_EXIT:
3043	case VERR_VMX_INVALID_VMCS_FIELD:
3044	case VERR_SVM_UNKNOWN_EXIT:
3045	case VERR_SVM_UNEXPECTED_EXIT:
3046	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3047	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3048	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3049	break;
3050	}
3051	}
3052
3053	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3054	{
3055	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3056	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3057	}
3058	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3059	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3060	}
3061
3062
3063	/**
3064	* Execute state save operation.
3065	*
3066	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3067	* is because we always save the VM state from ring-3 and thus most HM state
3068	* will be re-synced dynamically at runtime and don't need to be part of the VM
3069	* saved state.
3070	*
3071	* @returns VBox status code.
3072	* @param pVM The cross context VM structure.
3073	* @param pSSM SSM operation handle.
3074	*/
3075	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3076	{
3077	Log(("hmR3Save:\n"));
3078
3079	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3080	{
3081	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3082	Assert(!pVCpu->hm.s.Event.fPending);
3083	if (pVM->cpum.ro.GuestFeatures.fSvm)
3084	{
3085	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3086	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3087	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3088	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3089	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3090	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3091	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3092	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3093	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3094	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3095	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3096	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3097	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3098	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3099	}
3100	}
3101
3102	/* Save the guest patch data. */
3103	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3104	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3105	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3106
3107	/* Store all the guest patch records too. */
3108	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3109	if (RT_FAILURE(rc))
3110	return rc;
3111
3112	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3113	{
3114	AssertCompileSize(HMTPRINSTR, 4);
3115	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3116	SSMR3PutU32(pSSM, pPatch->Core.Key);
3117	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3118	SSMR3PutU32(pSSM, pPatch->cbOp);
3119	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3120	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3121	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3122	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3123	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3124	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3125	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3126	if (RT_FAILURE(rc))
3127	return rc;
3128	}
3129
3130	return VINF_SUCCESS;
3131	}
3132
3133
3134	/**
3135	* Execute state load operation.
3136	*
3137	* @returns VBox status code.
3138	* @param pVM The cross context VM structure.
3139	* @param pSSM SSM operation handle.
3140	* @param uVersion Data layout version.
3141	* @param uPass The data pass.
3142	*/
3143	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3144	{
3145	int rc;
3146
3147	LogFlowFunc(("uVersion=%u\n", uVersion));
3148	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3149
3150	/*
3151	* Validate version.
3152	*/
3153	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3154	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3155	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3156	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3157	{
3158	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3159	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3160	}
3161
3162	/*
3163	* Load per-VCPU state.
3164	*/
3165	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3166	{
3167	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3168	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3169	{
3170	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3171	if (pVM->cpum.ro.GuestFeatures.fSvm)
3172	{
3173	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3174	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3175	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3176	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3177	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3178	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3179	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3180	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3181	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3182	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3183	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3184	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3185	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3186	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3187	AssertRCReturn(rc, rc);
3188	}
3189	}
3190	else
3191	{
3192	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3193	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3194	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3195	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3196
3197	/* VMX fWasInRealMode related data. */
3198	uint32_t uDummy;
3199	SSMR3GetU32(pSSM, &uDummy);
3200	SSMR3GetU32(pSSM, &uDummy);
3201	rc = SSMR3GetU32(pSSM, &uDummy);
3202	AssertRCReturn(rc, rc);
3203	}
3204	}
3205
3206	/*
3207	* Load TPR patching data.
3208	*/
3209	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3210	{
3211	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3212	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3213	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3214
3215	/* Fetch all TPR patch records. */
3216	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3217	AssertRCReturn(rc, rc);
3218	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3219	{
3220	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3221	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3222	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3223	SSMR3GetU32(pSSM, &pPatch->cbOp);
3224	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3225	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3226	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3227
3228	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3229	pVM->hm.s.fTPRPatchingActive = true;
3230	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3231
3232	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3233	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3234	SSMR3GetU32(pSSM, &pPatch->cFaults);
3235	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3236	AssertRCReturn(rc, rc);
3237
3238	LogFlow(("hmR3Load: patch %d\n", i));
3239	LogFlow(("Key = %x\n", pPatch->Core.Key));
3240	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3241	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3242	LogFlow(("type = %d\n", pPatch->enmType));
3243	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3244	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3245	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3246	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3247
3248	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3249	AssertRCReturn(rc, rc);
3250	}
3251	}
3252
3253	return VINF_SUCCESS;
3254	}
3255
3256
3257	/**
3258	* Displays HM info.
3259	*
3260	* @param pVM The cross context VM structure.
3261	* @param pHlp The info helper functions.
3262	* @param pszArgs Arguments, ignored.
3263	*/
3264	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3265	{
3266	NOREF(pszArgs);
3267	PVMCPU pVCpu = VMMGetCpu(pVM);
3268	if (!pVCpu)
3269	pVCpu = pVM->apCpusR3[0];
3270
3271	if (HMIsEnabled(pVM))
3272	{
3273	if (pVM->hm.s.vmx.fSupported)
3274	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3275	else
3276	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3277	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3278	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3279	if (pVM->hm.s.vmx.fSupported)
3280	{
3281	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3282	bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3283	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3284
3285	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3286	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3287	if (fRealOnV86Active)
3288	{
3289	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3290	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3291	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3292	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3293	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3294	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3295	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3296	}
3297	}
3298	}
3299	else
3300	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3301	}
3302
3303
3304	/**
3305	* Displays the HM Last-Branch-Record info. for the guest.
3306	*
3307	* @param pVM The cross context VM structure.
3308	* @param pHlp The info helper functions.
3309	* @param pszArgs Arguments, ignored.
3310	*/
3311	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3312	{
3313	NOREF(pszArgs);
3314	PVMCPU pVCpu = VMMGetCpu(pVM);
3315	if (!pVCpu)
3316	pVCpu = pVM->apCpusR3[0];
3317
3318	if (!HMIsEnabled(pVM))
3319	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3320
3321	if (HMIsVmxActive(pVM))
3322	{
3323	if (pVM->hm.s.vmx.fLbr)
3324	{
3325	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3326	uint32_t const cLbrStack = pVM->hm.s.vmx.idLbrFromIpMsrLast - pVM->hm.s.vmx.idLbrFromIpMsrFirst + 1;
3327
3328	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3329	* 0xf should cover everything we support thus far. Fix if necessary
3330	* later. */
3331	uint32_t const idxTopOfStack = pVmcsInfo->u64LbrTosMsr & 0xf;
3332	if (idxTopOfStack > cLbrStack)
3333	{
3334	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3335	idxTopOfStack, pVmcsInfo->u64LbrTosMsr, cLbrStack);
3336	return;
3337	}
3338
3339	/*
3340	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3341	*/
3342	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3343	uint32_t idxCurrent = idxTopOfStack;
3344	Assert(idxTopOfStack < cLbrStack);
3345	Assert(RT_ELEMENTS(pVmcsInfo->au64LbrFromIpMsr) <= cLbrStack);
3346	Assert(RT_ELEMENTS(pVmcsInfo->au64LbrToIpMsr) <= cLbrStack);
3347	for (;;)
3348	{
3349	if (pVM->hm.s.vmx.idLbrToIpMsrFirst)
3350	{
3351	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3352	pVmcsInfo->au64LbrFromIpMsr[idxCurrent], pVmcsInfo->au64LbrToIpMsr[idxCurrent]);
3353	}
3354	else
3355	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfo->au64LbrFromIpMsr[idxCurrent]);
3356
3357	idxCurrent = (idxCurrent - 1) % cLbrStack;
3358	if (idxCurrent == idxTopOfStack)
3359	break;
3360	}
3361	}
3362	else
3363	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3364	}
3365	else
3366	{
3367	Assert(HMIsSvmActive(pVM));
3368	/** @todo SVM: LBRs (get them from VMCB if possible). */
3369	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented in VM debugger yet\n");
3370	}
3371	}
3372
3373
3374	/**
3375	* Displays the HM pending event.
3376	*
3377	* @param pVM The cross context VM structure.
3378	* @param pHlp The info helper functions.
3379	* @param pszArgs Arguments, ignored.
3380	*/
3381	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3382	{
3383	NOREF(pszArgs);
3384	PVMCPU pVCpu = VMMGetCpu(pVM);
3385	if (!pVCpu)
3386	pVCpu = pVM->apCpusR3[0];
3387
3388	if (HMIsEnabled(pVM))
3389	{
3390	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3391	if (pVCpu->hm.s.Event.fPending)
3392	{
3393	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3394	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3395	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3396	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3397	}
3398	}
3399	else
3400	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3401	}
3402
3403
3404	/**
3405	* Displays the SVM nested-guest VMCB cache.
3406	*
3407	* @param pVM The cross context VM structure.
3408	* @param pHlp The info helper functions.
3409	* @param pszArgs Arguments, ignored.
3410	*/
3411	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3412	{
3413	NOREF(pszArgs);
3414	PVMCPU pVCpu = VMMGetCpu(pVM);
3415	if (!pVCpu)
3416	pVCpu = pVM->apCpusR3[0];
3417
3418	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3419	if ( fSvmEnabled
3420	&& pVM->cpum.ro.GuestFeatures.fSvm)
3421	{
3422	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3423	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3424	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3425	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3426	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3427	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3428	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3429	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3430	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3431	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3432	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3433	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3434	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3435	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3436	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3437	}
3438	else
3439	{
3440	if (!fSvmEnabled)
3441	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3442	else
3443	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3444	}
3445	}
3446

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