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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 76553

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1/* $Id: HM.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/pdmapi.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/ssm.h>
48#include <VBox/vmm/gim.h>
49#include <VBox/vmm/trpm.h>
50#include <VBox/vmm/dbgf.h>
51#include <VBox/vmm/iom.h>
52#include <VBox/vmm/iem.h>
53#include <VBox/vmm/patm.h>
54#include <VBox/vmm/csam.h>
55#include <VBox/vmm/selm.h>
56#include <VBox/vmm/nem.h>
57#ifdef VBOX_WITH_REM
58# include <VBox/vmm/rem.h>
59#endif
60#include <VBox/vmm/hm_vmx.h>
61#include <VBox/vmm/hm_svm.h>
62#include "HMInternal.h"
63#include <VBox/vmm/vm.h>
64#include <VBox/vmm/uvm.h>
65#include <VBox/err.h>
66#include <VBox/param.h>
67
68#include <iprt/assert.h>
69#include <VBox/log.h>
70#include <iprt/asm.h>
71#include <iprt/asm-amd64-x86.h>
72#include <iprt/env.h>
73#include <iprt/thread.h>
74
75
76/*********************************************************************************************************************************
77* Global Variables *
78*********************************************************************************************************************************/
79#define EXIT_REASON(def, val, str) #def " - " #val " - " str
80#define EXIT_REASON_NIL() NULL
81/** Exit reason descriptions for VT-x, used to describe statistics and exit
82 * history. */
83static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
84{
85 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
86 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
87 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
88 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
89 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
90 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
91 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
92 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
93 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
94 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
95 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
96 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
97 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
98 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
99 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
100 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
101 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
102 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
103 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
104 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
105 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
106 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
107 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
108 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
109 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
110 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
111 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
112 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
113 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
114 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
115 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
116 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
117 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
118 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
119 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
122 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
123 EXIT_REASON_NIL(),
124 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
125 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
126 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
127 EXIT_REASON_NIL(),
128 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
129 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
130 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
131 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
132 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
133 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
134 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
135 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
136 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
137 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
138 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
139 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
140 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
141 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
142 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
143 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
144 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
145 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
146 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
147 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
148 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
149 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
150};
151/** Array index of the last valid VT-x exit reason. */
152#define MAX_EXITREASON_VTX 64
153
154/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
155 * statistics and exit history.
156 *
157 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
158 * this array doesn't contain the entire set of exit reasons, we
159 * handle them via hmSvmGetSpecialExitReasonDesc(). */
160static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
161{
162 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
163 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
164 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
165 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
166 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
167 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
168 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
169 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
170 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
171 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
172 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
173 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
174 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
175 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
176 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
177 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
190 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
191 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
192 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
193 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
194 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
195 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
196 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
197 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
198 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
199 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
200 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
201 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
202 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
203 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
204 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
205 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
206 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
207 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
208 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
209 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
222 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
223 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
224 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
225 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
226 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
227 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
228 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
229 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
230 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
231 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
232 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
233 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
234 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
235 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
236 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
237 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
238 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
239 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
240 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
241 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
242 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
243 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
244 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
245 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
246 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
247 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
248 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
249 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
250 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
251 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
252 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
253 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
254 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
255 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
256 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
257 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
258 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
259 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
260 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
261 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
262 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
263 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
264 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
265 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
266 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
267 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
268 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
269 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
270 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
271 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
272 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
273 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
274 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
275 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
276 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
277 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
278 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
279 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
280 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
281 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
282 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
283 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
284 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
285 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
286 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
287 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
288 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
289 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
290 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
291 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
292 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
293 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
294 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
295 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
296 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
297 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
298 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
299 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
300 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
301 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
302 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
303 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
304};
305/** Array index of the last valid AMD-V exit reason. */
306#define MAX_EXITREASON_AMDV 141
307
308/** Special exit reasons not covered in the array above. */
309#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
310#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
311#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
312
313/**
314 * Gets the SVM exit reason if it's one of the reasons not present in the @c
315 * g_apszSvmExitReasons array.
316 *
317 * @returns The exit reason or NULL if unknown.
318 * @param uExit The exit.
319 */
320DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
321{
322 switch (uExit)
323 {
324 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
325 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
326 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
327 }
328 return EXIT_REASON_NIL();
329}
330#undef EXIT_REASON_NIL
331#undef EXIT_REASON
332
333/** @def HMVMX_REPORT_FEAT
334 * Reports VT-x feature to the release log.
335 *
336 * @param a_uAllowed1 Mask of allowed-1 feature bits.
337 * @param a_uAllowed0 Mask of allowed-0 feature bits.
338 * @param a_StrDesc The description string to report.
339 * @param a_Featflag Mask of the feature to report.
340 */
341#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
342 do { \
343 if ((a_uAllowed1) & (a_Featflag)) \
344 { \
345 if ((a_uAllowed0) & (a_Featflag)) \
346 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
347 else \
348 LogRel(("HM: " a_StrDesc "\n")); \
349 } \
350 else \
351 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
352 } while (0)
353
354/** @def HMVMX_REPORT_ALLOWED_FEAT
355 * Reports an allowed VT-x feature to the release log.
356 *
357 * @param a_uAllowed1 Mask of allowed-1 feature bits.
358 * @param a_StrDesc The description string to report.
359 * @param a_FeatFlag Mask of the feature to report.
360 */
361#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
362 do { \
363 if ((a_uAllowed1) & (a_FeatFlag)) \
364 LogRel(("HM: " a_StrDesc "\n")); \
365 else \
366 LogRel(("HM: " a_StrDesc " not supported\n")); \
367 } while (0)
368
369/** @def HMVMX_REPORT_MSR_CAP
370 * Reports MSR feature capability.
371 *
372 * @param a_MsrCaps Mask of MSR feature bits.
373 * @param a_StrDesc The description string to report.
374 * @param a_fCap Mask of the feature to report.
375 */
376#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
377 do { \
378 if ((a_MsrCaps) & (a_fCap)) \
379 LogRel(("HM: " a_StrDesc "\n")); \
380 } while (0)
381
382/** @def HMVMX_LOGREL_FEAT
383 * Dumps a feature flag from a bitmap of features to the release log.
384 *
385 * @param a_fVal The value of all the features.
386 * @param a_fMask The specific bitmask of the feature.
387 */
388#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
389 do { \
390 if ((a_fVal) & (a_fMask)) \
391 LogRel(("HM: %s\n", #a_fMask)); \
392 } while (0)
393
394
395/*********************************************************************************************************************************
396* Internal Functions *
397*********************************************************************************************************************************/
398static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
399static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
400static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
401static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
402static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
403static int hmR3InitFinalizeR3(PVM pVM);
404static int hmR3InitFinalizeR0(PVM pVM);
405static int hmR3InitFinalizeR0Intel(PVM pVM);
406static int hmR3InitFinalizeR0Amd(PVM pVM);
407static int hmR3TermCPU(PVM pVM);
408
409
410
411/**
412 * Initializes the HM.
413 *
414 * This is the very first component to really do init after CFGM so that we can
415 * establish the predominant execution engine for the VM prior to initializing
416 * other modules. It takes care of NEM initialization if needed (HM disabled or
417 * not available in HW).
418 *
419 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
420 * hypervisor API via NEM, and then back on raw-mode if that isn't available
421 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
422 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
423 * X, OS/2 and others).
424 *
425 * Note that a lot of the set up work is done in ring-0 and thus postponed till
426 * the ring-3 and ring-0 callback to HMR3InitCompleted.
427 *
428 * @returns VBox status code.
429 * @param pVM The cross context VM structure.
430 *
431 * @remarks Be careful with what we call here, since most of the VMM components
432 * are uninitialized.
433 */
434VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
435{
436 LogFlow(("HMR3Init\n"));
437
438 /*
439 * Assert alignment and sizes.
440 */
441 AssertCompileMemberAlignment(VM, hm.s, 32);
442 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
443
444 /*
445 * Register the saved state data unit.
446 */
447 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
448 NULL, NULL, NULL,
449 NULL, hmR3Save, NULL,
450 NULL, hmR3Load, NULL);
451 if (RT_FAILURE(rc))
452 return rc;
453
454 /*
455 * Register info handlers.
456 */
457 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
458 AssertRCReturn(rc, rc);
459
460 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
461 DBGFINFO_FLAGS_ALL_EMTS);
462 AssertRCReturn(rc, rc);
463
464 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
465 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
466 AssertRCReturn(rc, rc);
467
468 /*
469 * Read configuration.
470 */
471 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
472
473 /*
474 * Validate the HM settings.
475 */
476 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
477 "HMForced"
478 "|UseNEMInstead"
479 "|FallbackToNEM"
480 "|EnableNestedPaging"
481 "|EnableUX"
482 "|EnableLargePages"
483 "|EnableVPID"
484 "|IBPBOnVMExit"
485 "|IBPBOnVMEntry"
486 "|SpecCtrlByHost"
487 "|TPRPatchingEnabled"
488 "|64bitEnabled"
489 "|Exclusive"
490 "|MaxResumeLoops"
491 "|VmxPleGap"
492 "|VmxPleWindow"
493 "|UseVmxPreemptTimer"
494 "|SvmPauseFilter"
495 "|SvmPauseFilterThreshold"
496 "|SvmVirtVmsaveVmload"
497 "|SvmVGif"
498 "|LovelyMesaDrvWorkaround",
499 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
500 if (RT_FAILURE(rc))
501 return rc;
502
503 /** @cfgm{/HM/HMForced, bool, false}
504 * Forces hardware virtualization, no falling back on raw-mode. HM must be
505 * enabled, i.e. /HMEnabled must be true. */
506 bool fHMForced;
507#ifdef VBOX_WITH_RAW_MODE
508 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
509 AssertRCReturn(rc, rc);
510 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
511 VERR_INVALID_PARAMETER);
512# if defined(RT_OS_DARWIN)
513 if (pVM->fHMEnabled)
514 fHMForced = true;
515# endif
516 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
517 VERR_INVALID_PARAMETER);
518 if (pVM->cCpus > 1)
519 fHMForced = true;
520#else /* !VBOX_WITH_RAW_MODE */
521 AssertRelease(pVM->fHMEnabled);
522 fHMForced = true;
523#endif /* !VBOX_WITH_RAW_MODE */
524
525 /** @cfgm{/HM/UseNEMInstead, bool, true}
526 * Don't use HM, use NEM instead. */
527 bool fUseNEMInstead = false;
528 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
529 AssertRCReturn(rc, rc);
530 if (fUseNEMInstead && pVM->fHMEnabled)
531 {
532 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
533 pVM->fHMEnabled = false;
534 }
535
536 /** @cfgm{/HM/FallbackToNEM, bool, true}
537 * Enables fallback on NEM. */
538 bool fFallbackToNEM = true;
539 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
540 AssertRCReturn(rc, rc);
541
542 /** @cfgm{/HM/EnableNestedPaging, bool, false}
543 * Enables nested paging (aka extended page tables). */
544 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
545 AssertRCReturn(rc, rc);
546
547 /** @cfgm{/HM/EnableUX, bool, true}
548 * Enables the VT-x unrestricted execution feature. */
549 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
550 AssertRCReturn(rc, rc);
551
552 /** @cfgm{/HM/EnableLargePages, bool, false}
553 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
554 * page table walking and maybe better TLB hit rate in some cases. */
555 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
556 AssertRCReturn(rc, rc);
557
558 /** @cfgm{/HM/EnableVPID, bool, false}
559 * Enables the VT-x VPID feature. */
560 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
561 AssertRCReturn(rc, rc);
562
563 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
564 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
565 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
566 AssertRCReturn(rc, rc);
567
568 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
569 * Enables AMD64 cpu features.
570 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
571 * already have the support. */
572#ifdef VBOX_ENABLE_64_BITS_GUESTS
573 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
574 AssertLogRelRCReturn(rc, rc);
575#else
576 pVM->hm.s.fAllow64BitGuests = false;
577#endif
578
579 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
580 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
581 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
582 * latest PAUSE instruction to be start of a new PAUSE loop.
583 */
584 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
585 AssertRCReturn(rc, rc);
586
587 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
588 * The pause-filter exiting window in TSC ticks. When the number of ticks
589 * between the current PAUSE instruction and first PAUSE of a loop exceeds
590 * VmxPleWindow, a VM-exit is triggered.
591 *
592 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
593 */
594 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
595 AssertRCReturn(rc, rc);
596
597 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
598 * A counter that is decrement each time a PAUSE instruction is executed by the
599 * guest. When the counter is 0, a \#VMEXIT is triggered.
600 *
601 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
602 */
603 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
604 AssertRCReturn(rc, rc);
605
606 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
607 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
608 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
609 * PauseFilter count is reset to its initial value. However, if PAUSE is
610 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
611 * be triggered.
612 *
613 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
614 * activated.
615 */
616 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
617 AssertRCReturn(rc, rc);
618
619 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
620 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
621 * available. */
622 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
623 AssertRCReturn(rc, rc);
624
625 /** @cfgm{/HM/SvmVGif, bool, true}
626 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
627 * if it's available. */
628 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
629 AssertRCReturn(rc, rc);
630
631 /** @cfgm{/HM/Exclusive, bool}
632 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
633 * global init for each host CPU. If false, we do local init each time we wish
634 * to execute guest code.
635 *
636 * On Windows, default is false due to the higher risk of conflicts with other
637 * hypervisors.
638 *
639 * On Mac OS X, this setting is ignored since the code does not handle local
640 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
641 */
642#if defined(RT_OS_DARWIN)
643 pVM->hm.s.fGlobalInit = true;
644#else
645 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
646# if defined(RT_OS_WINDOWS)
647 false
648# else
649 true
650# endif
651 );
652 AssertLogRelRCReturn(rc, rc);
653#endif
654
655 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
656 * The number of times to resume guest execution before we forcibly return to
657 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
658 * determines the default value. */
659 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
660 AssertLogRelRCReturn(rc, rc);
661
662 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
663 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
664 * available. */
665 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
666 AssertLogRelRCReturn(rc, rc);
667
668 /** @cfgm{/HM/IBPBOnVMExit, bool}
669 * Costly paranoia setting. */
670 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
671 AssertLogRelRCReturn(rc, rc);
672
673 /** @cfgm{/HM/IBPBOnVMEntry, bool}
674 * Costly paranoia setting. */
675 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
676 AssertLogRelRCReturn(rc, rc);
677
678 /** @cfgm{/HM/SpecCtrlByHost, bool}
679 * Another expensive paranoia setting. */
680 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
681 AssertLogRelRCReturn(rc, rc);
682
683 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
684 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
685 * the hypervisor it is running under. */
686 bool f;
687 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
688 AssertLogRelRCReturn(rc, rc);
689 for (VMCPUID i = 0; i < pVM->cCpus; i++)
690 pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
691
692 /*
693 * Check if VT-x or AMD-v support according to the users wishes.
694 */
695 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
696 * VERR_SVM_IN_USE. */
697 if (pVM->fHMEnabled)
698 {
699 uint32_t fCaps;
700 rc = SUPR3QueryVTCaps(&fCaps);
701 if (RT_SUCCESS(rc))
702 {
703 if (fCaps & SUPVTCAPS_AMD_V)
704 {
705 pVM->hm.s.svm.fSupported = true;
706 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
707 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
708 }
709 else if (fCaps & SUPVTCAPS_VT_X)
710 {
711 const char *pszWhy;
712 rc = SUPR3QueryVTxSupported(&pszWhy);
713 if (RT_SUCCESS(rc))
714 {
715 pVM->hm.s.vmx.fSupported = true;
716 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
717 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
718 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
719 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
720 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
721 }
722 else
723 {
724 /*
725 * Before failing, try fallback to NEM if we're allowed to do that.
726 */
727 pVM->fHMEnabled = false;
728 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
729 if (fFallbackToNEM)
730 {
731 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
732 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
733
734 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
735 if ( RT_SUCCESS(rc2)
736 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
737 rc = VINF_SUCCESS;
738 }
739 if (RT_FAILURE(rc))
740 {
741 if (fHMForced)
742 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
743
744 /* Fall back to raw-mode. */
745 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
746 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
747 }
748 }
749 }
750 else
751 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
752 VERR_INTERNAL_ERROR_5);
753
754 /*
755 * Do we require a little bit or raw-mode for 64-bit guest execution?
756 */
757 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
758 && pVM->fHMEnabled
759 && pVM->hm.s.fAllow64BitGuests;
760
761 /*
762 * Disable nested paging and unrestricted guest execution now if they're
763 * configured so that CPUM can make decisions based on our configuration.
764 */
765 Assert(!pVM->hm.s.fNestedPaging);
766 if (pVM->hm.s.fAllowNestedPaging)
767 {
768 if (fCaps & SUPVTCAPS_NESTED_PAGING)
769 pVM->hm.s.fNestedPaging = true;
770 else
771 pVM->hm.s.fAllowNestedPaging = false;
772 }
773
774 if (fCaps & SUPVTCAPS_VT_X)
775 {
776 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
777 if (pVM->hm.s.vmx.fAllowUnrestricted)
778 {
779 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
780 && pVM->hm.s.fNestedPaging)
781 pVM->hm.s.vmx.fUnrestrictedGuest = true;
782 else
783 pVM->hm.s.vmx.fAllowUnrestricted = false;
784 }
785 }
786 }
787 else
788 {
789 const char *pszMsg;
790 switch (rc)
791 {
792 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
793 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
794 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
795 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
796 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
797 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
798 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
799 default:
800 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
801 }
802
803 /*
804 * Before failing, try fallback to NEM if we're allowed to do that.
805 */
806 pVM->fHMEnabled = false;
807 if (fFallbackToNEM)
808 {
809 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
810 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
811 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
812 if ( RT_SUCCESS(rc2)
813 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
814 rc = VINF_SUCCESS;
815 }
816 if (RT_FAILURE(rc))
817 {
818 if (fHMForced)
819 return VM_SET_ERROR(pVM, rc, pszMsg);
820
821 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
822 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
823 }
824 }
825 }
826 else
827 {
828 /*
829 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
830 */
831 if (!fUseNEMInstead)
832 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
833 else
834 {
835 rc = NEMR3Init(pVM, false /*fFallback*/, true);
836 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
837 if (RT_FAILURE(rc))
838 return rc;
839 }
840 }
841
842 return VINF_SUCCESS;
843}
844
845
846/**
847 * Initializes HM components after ring-3 phase has been fully initialized.
848 *
849 * @returns VBox status code.
850 * @param pVM The cross context VM structure.
851 */
852static int hmR3InitFinalizeR3(PVM pVM)
853{
854 LogFlow(("HMR3InitCPU\n"));
855
856 if (!HMIsEnabled(pVM))
857 return VINF_SUCCESS;
858
859 for (VMCPUID i = 0; i < pVM->cCpus; i++)
860 {
861 PVMCPU pVCpu = &pVM->aCpus[i];
862 pVCpu->hm.s.fActive = false;
863 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
864 }
865
866#ifdef VBOX_WITH_STATISTICS
867 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
868 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
869 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
870 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
871 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
872#endif
873
874 /*
875 * Statistics.
876 */
877 for (VMCPUID i = 0; i < pVM->cCpus; i++)
878 {
879 PVMCPU pVCpu = &pVM->aCpus[i];
880 int rc;
881
882#ifdef VBOX_WITH_STATISTICS
883 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
884 "Profiling of RTMpPokeCpu.",
885 "/PROF/CPU%d/HM/Poke", i);
886 AssertRC(rc);
887 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
888 "Profiling of poke wait.",
889 "/PROF/CPU%d/HM/PokeWait", i);
890 AssertRC(rc);
891 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
892 "Profiling of poke wait when RTMpPokeCpu fails.",
893 "/PROF/CPU%d/HM/PokeWaitFailed", i);
894 AssertRC(rc);
895 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
896 "Profiling of entry until entering GC.",
897 "/PROF/CPU%d/HM/Entry", i);
898 AssertRC(rc);
899 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
900 "Profiling of pre-exit processing after returning from GC.",
901 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
902 AssertRC(rc);
903 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
904 "Profiling of exit handling (longjmps not included!)",
905 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
906 AssertRC(rc);
907
908 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
909 "I/O.",
910 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
911 AssertRC(rc);
912 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
913 "MOV CRx.",
914 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
915 AssertRC(rc);
916 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
917 "Exceptions, NMIs.",
918 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
919 AssertRC(rc);
920
921 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
922 "Profiling of importing guest state from hardware after VM-exit.",
923 "/PROF/CPU%d/HM/ImportGuestState", i);
924 AssertRC(rc);
925 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
926 "Profiling of exporting guest state to hardware before VM-entry.",
927 "/PROF/CPU%d/HM/ExportGuestState", i);
928 AssertRC(rc);
929 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
930 "Profiling of CPUMR0LoadGuestFPU.",
931 "/PROF/CPU%d/HM/LoadGuestFpuState", i);
932 AssertRC(rc);
933 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
934 "Profiling of execution of guest-code in hardware.",
935 "/PROF/CPU%d/HM/InGC", i);
936 AssertRC(rc);
937
938# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
939 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
940 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
941 "/PROF/CPU%d/HM/Switcher3264", i);
942 AssertRC(rc);
943# endif
944
945# ifdef HM_PROFILE_EXIT_DISPATCH
946 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
947 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
948 "/PROF/CPU%d/HM/ExitDispatch", i);
949 AssertRC(rc);
950# endif
951
952#endif
953# define HM_REG_COUNTER(a, b, desc) \
954 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
955 AssertRC(rc);
956
957#ifdef VBOX_WITH_STATISTICS
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
990 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
991 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
992 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
993 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
994 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
995 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
996 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
1000 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
1006#endif
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
1008#ifdef VBOX_WITH_STATISTICS
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
1010 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
1012 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
1014
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
1018 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
1019 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
1021 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
1022 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
1024#endif
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
1026#ifdef VBOX_WITH_STATISTICS
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
1028
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
1031 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
1033
1034 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1035 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1036 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1038 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1039 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1040 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1041 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1042 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1043 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1044 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1045 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1046 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1047 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1048
1049 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1050 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1051 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1052
1053 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1054 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1055 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1056
1057 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
1058 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
1059 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
1060
1061 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1062 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1063 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector limit.");
1064 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1065 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1066 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1067 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1068
1069#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1070 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1071 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1072#endif
1073
1074#undef HM_REG_COUNTER
1075
1076 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVmxExitReasons[0]
1077 : &g_apszSvmExitReasons[0];
1078
1079 /*
1080 * Guest Exit reason stats.
1081 */
1082 pVCpu->hm.s.paStatExitReason = NULL;
1083 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1084 (void **)&pVCpu->hm.s.paStatExitReason);
1085 AssertRCReturn(rc, rc);
1086 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1087 {
1088 if (papszDesc[j])
1089 {
1090 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1091 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1092 AssertRCReturn(rc, rc);
1093 }
1094 }
1095 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1096 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1097 AssertRCReturn(rc, rc);
1098 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1099# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1100 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1101# else
1102 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1103# endif
1104
1105#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1106 /*
1107 * Nested-guest Exit reason stats.
1108 */
1109 pVCpu->hm.s.paStatNestedExitReason = NULL;
1110 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1111 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1112 AssertRCReturn(rc, rc);
1113 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1114 {
1115 if (papszDesc[j])
1116 {
1117 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1118 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1119 AssertRC(rc);
1120 }
1121 }
1122 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1123 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1124 AssertRCReturn(rc, rc);
1125 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1126# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1127 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1128# else
1129 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1130# endif
1131#endif
1132
1133 /*
1134 * Injected events stats.
1135 */
1136 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1137 AssertRCReturn(rc, rc);
1138 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1139# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1140 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1141# else
1142 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1143# endif
1144 for (unsigned j = 0; j < 255; j++)
1145 {
1146 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1147 "Injected event.",
1148 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1149 }
1150
1151#endif /* VBOX_WITH_STATISTICS */
1152 }
1153
1154#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1155 /*
1156 * Magic marker for searching in crash dumps.
1157 */
1158 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1159 {
1160 PVMCPU pVCpu = &pVM->aCpus[i];
1161
1162 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1163 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1164 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
1165 }
1166#endif
1167
1168 return VINF_SUCCESS;
1169}
1170
1171
1172/**
1173 * Called when a init phase has completed.
1174 *
1175 * @returns VBox status code.
1176 * @param pVM The cross context VM structure.
1177 * @param enmWhat The phase that completed.
1178 */
1179VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1180{
1181 switch (enmWhat)
1182 {
1183 case VMINITCOMPLETED_RING3:
1184 return hmR3InitFinalizeR3(pVM);
1185 case VMINITCOMPLETED_RING0:
1186 return hmR3InitFinalizeR0(pVM);
1187 default:
1188 return VINF_SUCCESS;
1189 }
1190}
1191
1192
1193/**
1194 * Turns off normal raw mode features.
1195 *
1196 * @param pVM The cross context VM structure.
1197 */
1198static void hmR3DisableRawMode(PVM pVM)
1199{
1200/** @todo r=bird: HM shouldn't be doing this crap. */
1201 /* Reinit the paging mode to force the new shadow mode. */
1202 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1203 {
1204 PVMCPU pVCpu = &pVM->aCpus[i];
1205 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1206 }
1207}
1208
1209
1210/**
1211 * Initialize VT-x or AMD-V.
1212 *
1213 * @returns VBox status code.
1214 * @param pVM The cross context VM structure.
1215 */
1216static int hmR3InitFinalizeR0(PVM pVM)
1217{
1218 int rc;
1219
1220 if (!HMIsEnabled(pVM))
1221 return VINF_SUCCESS;
1222
1223 /*
1224 * Hack to allow users to work around broken BIOSes that incorrectly set
1225 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1226 */
1227 if ( !pVM->hm.s.vmx.fSupported
1228 && !pVM->hm.s.svm.fSupported
1229 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1230 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1231 {
1232 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1233 pVM->hm.s.svm.fSupported = true;
1234 pVM->hm.s.svm.fIgnoreInUseError = true;
1235 pVM->hm.s.rcInit = VINF_SUCCESS;
1236 }
1237
1238 /*
1239 * Report ring-0 init errors.
1240 */
1241 if ( !pVM->hm.s.vmx.fSupported
1242 && !pVM->hm.s.svm.fSupported)
1243 {
1244 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1245 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1246 switch (pVM->hm.s.rcInit)
1247 {
1248 case VERR_VMX_IN_VMX_ROOT_MODE:
1249 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1250 case VERR_VMX_NO_VMX:
1251 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1252 case VERR_VMX_MSR_VMX_DISABLED:
1253 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1254 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1255 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1256 case VERR_VMX_MSR_LOCKING_FAILED:
1257 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1258 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1259 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1260 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1261 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1262
1263 case VERR_SVM_IN_USE:
1264 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1265 case VERR_SVM_NO_SVM:
1266 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1267 case VERR_SVM_DISABLED:
1268 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1269 }
1270 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1271 }
1272
1273 /*
1274 * Enable VT-x or AMD-V on all host CPUs.
1275 */
1276 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1277 if (RT_FAILURE(rc))
1278 {
1279 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1280 HMR3CheckError(pVM, rc);
1281 return rc;
1282 }
1283
1284 /*
1285 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1286 * (Main should have taken care of this already)
1287 */
1288 if (!PDMHasIoApic(pVM))
1289 {
1290 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1291 pVM->hm.s.fTprPatchingAllowed = false;
1292 }
1293
1294 /*
1295 * Sync options.
1296 */
1297 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1298 * That will require a little bit of work, of course. */
1299 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1300 {
1301 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1302 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1303 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1304 if (pVM->cpum.ro.HostFeatures.fIbpb)
1305 {
1306 if (pVM->hm.s.fIbpbOnVmExit)
1307 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1308 if (pVM->hm.s.fIbpbOnVmEntry)
1309 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1310 }
1311 if (iCpu == 0)
1312 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1313 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1314 }
1315
1316 /*
1317 * Do the vendor specific initialization
1318 *
1319 * Note! We disable release log buffering here since we're doing relatively
1320 * lot of logging and doesn't want to hit the disk with each LogRel
1321 * statement.
1322 */
1323 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1324 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1325 if (pVM->hm.s.vmx.fSupported)
1326 rc = hmR3InitFinalizeR0Intel(pVM);
1327 else
1328 rc = hmR3InitFinalizeR0Amd(pVM);
1329 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1330 RTLogRelSetBuffering(fOldBuffered);
1331 pVM->hm.s.fInitialized = true;
1332
1333 return rc;
1334}
1335
1336
1337/**
1338 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1339 */
1340static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1341{
1342 NOREF(pVM);
1343 NOREF(pvAllocation);
1344 NOREF(GCPhysAllocation);
1345}
1346
1347
1348/**
1349 * Returns a description of the VMCS (and associated regions') memory type given the
1350 * IA32_VMX_BASIC MSR.
1351 *
1352 * @returns The descriptive memory type.
1353 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1354 */
1355static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1356{
1357 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1358 switch (uMemType)
1359 {
1360 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1361 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1362 }
1363 return "Unknown";
1364}
1365
1366
1367/**
1368 * Returns a single-line description of all the activity-states supported by the CPU
1369 * given the IA32_VMX_MISC MSR.
1370 *
1371 * @returns All supported activity states.
1372 * @param uMsrMisc IA32_VMX_MISC MSR value.
1373 */
1374static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1375{
1376 static const char * const s_apszActStates[] =
1377 {
1378 "",
1379 " ( HLT )",
1380 " ( SHUTDOWN )",
1381 " ( HLT SHUTDOWN )",
1382 " ( SIPI_WAIT )",
1383 " ( HLT SIPI_WAIT )",
1384 " ( SHUTDOWN SIPI_WAIT )",
1385 " ( HLT SHUTDOWN SIPI_WAIT )"
1386 };
1387 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1388 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1389 return s_apszActStates[idxActStates];
1390}
1391
1392
1393/**
1394 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1395 *
1396 * @param fFeatMsr The feature control MSR value.
1397 */
1398static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1399{
1400 uint64_t const val = fFeatMsr;
1401 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1402 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1403 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1404 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1405 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1406 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1407 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1408 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1409 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1410 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1411 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1412 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1413 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1414 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1415 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1416 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1417 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1418}
1419
1420
1421/**
1422 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1423 *
1424 * @param uBasicMsr The VMX basic MSR value.
1425 */
1426static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1427{
1428 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1429 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1430 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1431 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1432 "< 4 GB" : "None"));
1433 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1434 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1435 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1436 LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1437}
1438
1439
1440/**
1441 * Reports MSR_IA32_PINBASED_CTLS to the log.
1442 *
1443 * @param pVmxMsr Pointer to the VMX MSR.
1444 */
1445static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1446{
1447 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1448 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1449 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1450 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1451 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1452 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1453 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1454 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1455}
1456
1457
1458/**
1459 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1460 *
1461 * @param pVmxMsr Pointer to the VMX MSR.
1462 */
1463static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1464{
1465 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1466 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1467 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1468 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1469 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1470 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1471 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1472 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1473 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1474 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1475 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1476 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1477 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1478 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1479 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1480 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1481 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1482 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1483 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1484 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1485 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1486 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1487 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1488 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1489}
1490
1491
1492/**
1493 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1494 *
1495 * @param pVmxMsr Pointer to the VMX MSR.
1496 */
1497static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1498{
1499 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1500 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1501 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1502 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1503 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1504 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1505 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1506 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1507 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1508 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1509 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1510 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1511 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1512 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1513 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1514 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1515 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1516 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1517 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1518 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1519 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1520 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1521 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_FROM_PT", VMX_PROC_CTLS2_CONCEAL_FROM_PT);
1522 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1523 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1524}
1525
1526
1527/**
1528 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1529 *
1530 * @param pVmxMsr Pointer to the VMX MSR.
1531 */
1532static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1533{
1534 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1535 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1536 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1537 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1538 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1539 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1540 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1541 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1542 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1543 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1544}
1545
1546
1547/**
1548 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1549 *
1550 * @param pVmxMsr Pointer to the VMX MSR.
1551 */
1552static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1553{
1554 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1555 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1556 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1557 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1558 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1559 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1560 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1561 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1562 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1563 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1564 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1565 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1566}
1567
1568
1569/**
1570 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1571 *
1572 * @param fCaps The VMX EPT/VPID capability MSR value.
1573 */
1574static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1575{
1576 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1577 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1578 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1579 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1580 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1581 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1582 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1583 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1584 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1585 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1586 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1587 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1588 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1589 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1590 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1591 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1592}
1593
1594
1595/**
1596 * Reports MSR_IA32_VMX_MISC MSR to the log.
1597 *
1598 * @param pVM Pointer to the VM.
1599 * @param fMisc The VMX misc. MSR value.
1600 */
1601static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1602{
1603 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1604 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1605 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1606 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1607 else
1608 {
1609 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1610 pVM->hm.s.vmx.cPreemptTimerShift));
1611 }
1612 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1613 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1614 hmR3VmxGetActivityStateAllDesc(fMisc)));
1615 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1616 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1617 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1618 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1619 VMX_MISC_MAX_MSRS(fMisc)));
1620 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1621 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1622 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1623 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1624}
1625
1626
1627/**
1628 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1629 *
1630 * @param uVmcsEnum The VMX VMCS enum MSR value.
1631 */
1632static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1633{
1634 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1635 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1636}
1637
1638
1639/**
1640 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1641 *
1642 * @param uVmFunc The VMX VMFUNC MSR value.
1643 */
1644static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1645{
1646 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1647 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1648}
1649
1650
1651/**
1652 * Reports VMX CR0, CR4 fixed MSRs.
1653 *
1654 * @param pMsrs Pointer to the VMX MSRs.
1655 */
1656static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1657{
1658 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1659 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1660 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1661 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1662}
1663
1664
1665/**
1666 * Finish VT-x initialization (after ring-0 init).
1667 *
1668 * @returns VBox status code.
1669 * @param pVM The cross context VM structure.
1670 */
1671static int hmR3InitFinalizeR0Intel(PVM pVM)
1672{
1673 int rc;
1674
1675 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1676 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1677
1678 LogRel(("HM: Using VT-x implementation 2.0\n"));
1679 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1680 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1681 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1682 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1683
1684 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1685 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1686
1687 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1688 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1689 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1690 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1691
1692 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1693 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1694
1695 if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1696 {
1697 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1698 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1699 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1700 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1701 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1702 }
1703
1704 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1705 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1706 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1707 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1708 if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1709 hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1710 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1711
1712 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1713 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1714 {
1715 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1716 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1717 }
1718
1719 /*
1720 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1721 */
1722 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1723 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1724 VERR_HM_IPE_1);
1725 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1726 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1727 && pVM->hm.s.fNestedPaging),
1728 VERR_HM_IPE_1);
1729
1730 /*
1731 * Enable VPID if configured and supported.
1732 */
1733 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1734 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1735
1736#if 0
1737 /*
1738 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1739 */
1740 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1741 && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1742 pVM->hm.s.fVirtApicRegs = true;
1743
1744 /*
1745 * Enable posted-interrupt processing if supported.
1746 */
1747 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1748 * here. */
1749 if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1750 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1751 pVM->hm.s.fPostedIntrs = true;
1752#endif
1753
1754 /*
1755 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1756 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1757 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1758 */
1759 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1760 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1761 {
1762 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1763 LogRel(("HM: Disabled RDTSCP\n"));
1764 }
1765
1766 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1767 {
1768 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1769 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1770 if (RT_SUCCESS(rc))
1771 {
1772 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1773 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1774 esp. Figure 20-5.*/
1775 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1776 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1777
1778 /* Bit set to 0 means software interrupts are redirected to the
1779 8086 program interrupt handler rather than switching to
1780 protected-mode handler. */
1781 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1782
1783 /* Allow all port IO, so that port IO instructions do not cause
1784 exceptions and would instead cause a VM-exit (based on VT-x's
1785 IO bitmap which we currently configure to always cause an exit). */
1786 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1787 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1788
1789 /*
1790 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1791 * page table used in real and protected mode without paging with EPT.
1792 */
1793 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1794 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1795 {
1796 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1797 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1798 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1799 | X86_PDE4M_G;
1800 }
1801
1802 /* We convert it here every time as PCI regions could be reconfigured. */
1803 if (PDMVmmDevHeapIsEnabled(pVM))
1804 {
1805 RTGCPHYS GCPhys;
1806 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1807 AssertRCReturn(rc, rc);
1808 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1809
1810 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1811 AssertRCReturn(rc, rc);
1812 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1813 }
1814 }
1815 else
1816 {
1817 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1818 pVM->hm.s.vmx.pRealModeTSS = NULL;
1819 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1820 return VMSetError(pVM, rc, RT_SRC_POS,
1821 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1822 }
1823 }
1824
1825 LogRel((pVM->hm.s.fAllow64BitGuests
1826 ? "HM: Guest support: 32-bit and 64-bit\n"
1827 : "HM: Guest support: 32-bit only\n"));
1828
1829 /*
1830 * Call ring-0 to set up the VM.
1831 */
1832 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1833 if (rc != VINF_SUCCESS)
1834 {
1835 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1836 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1837 {
1838 PVMCPU pVCpu = &pVM->aCpus[i];
1839 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1840 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1841 }
1842 HMR3CheckError(pVM, rc);
1843 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1844 }
1845
1846 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1847 LogRel(("HM: Enabled VMX\n"));
1848 pVM->hm.s.vmx.fEnabled = true;
1849
1850 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1851
1852 /*
1853 * Change the CPU features.
1854 */
1855 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1856 if (pVM->hm.s.fAllow64BitGuests)
1857 {
1858 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1859 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1860 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1861 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1862 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1863 }
1864 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1865 (we reuse the host EFER in the switcher). */
1866 /** @todo this needs to be fixed properly!! */
1867 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1868 {
1869 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1870 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1871 else
1872 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1873 }
1874
1875 /*
1876 * Log configuration details.
1877 */
1878 if (pVM->hm.s.fNestedPaging)
1879 {
1880 LogRel(("HM: Enabled nested paging\n"));
1881 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1882 LogRel(("HM: EPT flush type = Single context\n"));
1883 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1884 LogRel(("HM: EPT flush type = All contexts\n"));
1885 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1886 LogRel(("HM: EPT flush type = Not supported\n"));
1887 else
1888 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1889
1890 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1891 LogRel(("HM: Enabled unrestricted guest execution\n"));
1892
1893#if HC_ARCH_BITS == 64
1894 if (pVM->hm.s.fLargePages)
1895 {
1896 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1897 PGMSetLargePageUsage(pVM, true);
1898 LogRel(("HM: Enabled large page support\n"));
1899 }
1900#endif
1901 }
1902 else
1903 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1904
1905 if (pVM->hm.s.fVirtApicRegs)
1906 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1907
1908 if (pVM->hm.s.fPostedIntrs)
1909 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1910
1911 if (pVM->hm.s.vmx.fVpid)
1912 {
1913 LogRel(("HM: Enabled VPID\n"));
1914 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1915 LogRel(("HM: VPID flush type = Individual addresses\n"));
1916 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1917 LogRel(("HM: VPID flush type = Single context\n"));
1918 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1919 LogRel(("HM: VPID flush type = All contexts\n"));
1920 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1921 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1922 else
1923 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1924 }
1925 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1926 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1927
1928 if (pVM->hm.s.vmx.fUsePreemptTimer)
1929 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1930 else
1931 LogRel(("HM: Disabled VMX-preemption timer\n"));
1932
1933 return VINF_SUCCESS;
1934}
1935
1936
1937/**
1938 * Finish AMD-V initialization (after ring-0 init).
1939 *
1940 * @returns VBox status code.
1941 * @param pVM The cross context VM structure.
1942 */
1943static int hmR3InitFinalizeR0Amd(PVM pVM)
1944{
1945 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1946
1947 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1948
1949 uint32_t u32Family;
1950 uint32_t u32Model;
1951 uint32_t u32Stepping;
1952 if (HMSvmIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1953 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1954 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1955 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1956 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1957 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1958 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1959
1960 /*
1961 * Enumerate AMD-V features.
1962 */
1963 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1964 {
1965#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1966 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1967 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1968 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1969 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1970 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1971 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1972 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1973 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1974 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1975 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1976 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1977 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1978 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1979#undef HMSVM_REPORT_FEATURE
1980 };
1981
1982 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1983 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1984 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1985 {
1986 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1987 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1988 }
1989 if (fSvmFeatures)
1990 for (unsigned iBit = 0; iBit < 32; iBit++)
1991 if (RT_BIT_32(iBit) & fSvmFeatures)
1992 LogRel(("HM: Reserved bit %u\n", iBit));
1993
1994 /*
1995 * Nested paging is determined in HMR3Init, verify the sanity of that.
1996 */
1997 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1998 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1999 VERR_HM_IPE_1);
2000
2001#if 0
2002 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
2003 * here. */
2004 if (RTR0IsPostIpiSupport())
2005 pVM->hm.s.fPostedIntrs = true;
2006#endif
2007
2008 /*
2009 * Call ring-0 to set up the VM.
2010 */
2011 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
2012 if (rc != VINF_SUCCESS)
2013 {
2014 AssertMsgFailed(("%Rrc\n", rc));
2015 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
2016 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
2017 }
2018
2019 LogRel(("HM: Enabled SVM\n"));
2020 pVM->hm.s.svm.fEnabled = true;
2021
2022 if (pVM->hm.s.fNestedPaging)
2023 {
2024 LogRel(("HM: Enabled nested paging\n"));
2025
2026 /*
2027 * Enable large pages (2 MB) if applicable.
2028 */
2029#if HC_ARCH_BITS == 64
2030 if (pVM->hm.s.fLargePages)
2031 {
2032 PGMSetLargePageUsage(pVM, true);
2033 LogRel(("HM: Enabled large page support\n"));
2034 }
2035#endif
2036 }
2037
2038 if (pVM->hm.s.fVirtApicRegs)
2039 LogRel(("HM: Enabled APIC-register virtualization support\n"));
2040
2041 if (pVM->hm.s.fPostedIntrs)
2042 LogRel(("HM: Enabled posted-interrupt processing support\n"));
2043
2044 hmR3DisableRawMode(pVM);
2045
2046 /*
2047 * Change the CPU features.
2048 */
2049 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
2050 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
2051 if (pVM->hm.s.fAllow64BitGuests)
2052 {
2053 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
2054 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
2055 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2056 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
2057 }
2058 /* Turn on NXE if PAE has been enabled. */
2059 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
2060 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2061
2062 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
2063
2064 LogRel((pVM->hm.s.fAllow64BitGuests
2065 ? "HM: Guest support: 32-bit and 64-bit\n"
2066 : "HM: Guest support: 32-bit only\n"));
2067
2068 return VINF_SUCCESS;
2069}
2070
2071
2072/**
2073 * Applies relocations to data and code managed by this
2074 * component. This function will be called at init and
2075 * whenever the VMM need to relocate it self inside the GC.
2076 *
2077 * @param pVM The cross context VM structure.
2078 */
2079VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2080{
2081 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
2082
2083 /* Fetch the current paging mode during the relocate callback during state loading. */
2084 if (VMR3GetState(pVM) == VMSTATE_LOADING)
2085 {
2086 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2087 {
2088 PVMCPU pVCpu = &pVM->aCpus[i];
2089 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2090 }
2091 }
2092#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
2093 if (HMIsEnabled(pVM))
2094 {
2095 switch (PGMGetHostMode(pVM))
2096 {
2097 case PGMMODE_32_BIT:
2098 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
2099 break;
2100
2101 case PGMMODE_PAE:
2102 case PGMMODE_PAE_NX:
2103 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
2104 break;
2105
2106 default:
2107 AssertFailed();
2108 break;
2109 }
2110 }
2111#endif
2112 return;
2113}
2114
2115
2116/**
2117 * Terminates the HM.
2118 *
2119 * Termination means cleaning up and freeing all resources,
2120 * the VM itself is, at this point, powered off or suspended.
2121 *
2122 * @returns VBox status code.
2123 * @param pVM The cross context VM structure.
2124 */
2125VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2126{
2127 if (pVM->hm.s.vmx.pRealModeTSS)
2128 {
2129 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2130 pVM->hm.s.vmx.pRealModeTSS = 0;
2131 }
2132 hmR3TermCPU(pVM);
2133 return 0;
2134}
2135
2136
2137/**
2138 * Terminates the per-VCPU HM.
2139 *
2140 * @returns VBox status code.
2141 * @param pVM The cross context VM structure.
2142 */
2143static int hmR3TermCPU(PVM pVM)
2144{
2145 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2146 {
2147 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2148
2149#ifdef VBOX_WITH_STATISTICS
2150 if (pVCpu->hm.s.paStatExitReason)
2151 {
2152 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2153 pVCpu->hm.s.paStatExitReason = NULL;
2154 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2155 }
2156 if (pVCpu->hm.s.paStatInjectedIrqs)
2157 {
2158 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2159 pVCpu->hm.s.paStatInjectedIrqs = NULL;
2160 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2161 }
2162#endif
2163
2164#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2165 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
2166 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
2167 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
2168#endif
2169 }
2170 return 0;
2171}
2172
2173
2174/**
2175 * Resets a virtual CPU.
2176 *
2177 * Used by HMR3Reset and CPU hot plugging.
2178 *
2179 * @param pVCpu The cross context virtual CPU structure to reset.
2180 */
2181VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2182{
2183 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2184 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2185 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2186
2187 pVCpu->hm.s.fActive = false;
2188 pVCpu->hm.s.Event.fPending = false;
2189 pVCpu->hm.s.vmx.fWasInRealMode = true;
2190 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2191 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2192
2193 /* Reset the contents of the read cache. */
2194 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2195 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2196 pCache->Read.aFieldVal[j] = 0;
2197
2198#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2199 /* Magic marker for searching in crash dumps. */
2200 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2201 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2202#endif
2203}
2204
2205
2206/**
2207 * The VM is being reset.
2208 *
2209 * For the HM component this means that any GDT/LDT/TSS monitors
2210 * needs to be removed.
2211 *
2212 * @param pVM The cross context VM structure.
2213 */
2214VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2215{
2216 LogFlow(("HMR3Reset:\n"));
2217
2218 if (HMIsEnabled(pVM))
2219 hmR3DisableRawMode(pVM);
2220
2221 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2222 {
2223 PVMCPU pVCpu = &pVM->aCpus[i];
2224
2225 HMR3ResetCpu(pVCpu);
2226 }
2227
2228 /* Clear all patch information. */
2229 pVM->hm.s.pGuestPatchMem = 0;
2230 pVM->hm.s.pFreeGuestPatchMem = 0;
2231 pVM->hm.s.cbGuestPatchMem = 0;
2232 pVM->hm.s.cPatches = 0;
2233 pVM->hm.s.PatchTree = 0;
2234 pVM->hm.s.fTPRPatchingActive = false;
2235 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2236}
2237
2238
2239/**
2240 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2241 *
2242 * @returns VBox strict status code.
2243 * @param pVM The cross context VM structure.
2244 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2245 * @param pvUser Unused.
2246 */
2247static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2248{
2249 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2250
2251 /* Only execute the handler on the VCPU the original patch request was issued. */
2252 if (pVCpu->idCpu != idCpu)
2253 return VINF_SUCCESS;
2254
2255 Log(("hmR3RemovePatches\n"));
2256 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2257 {
2258 uint8_t abInstr[15];
2259 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2260 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2261 int rc;
2262
2263#ifdef LOG_ENABLED
2264 char szOutput[256];
2265 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2266 szOutput, sizeof(szOutput), NULL);
2267 if (RT_SUCCESS(rc))
2268 Log(("Patched instr: %s\n", szOutput));
2269#endif
2270
2271 /* Check if the instruction is still the same. */
2272 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2273 if (rc != VINF_SUCCESS)
2274 {
2275 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2276 continue; /* swapped out or otherwise removed; skip it. */
2277 }
2278
2279 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2280 {
2281 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2282 continue; /* skip it. */
2283 }
2284
2285 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2286 AssertRC(rc);
2287
2288#ifdef LOG_ENABLED
2289 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2290 szOutput, sizeof(szOutput), NULL);
2291 if (RT_SUCCESS(rc))
2292 Log(("Original instr: %s\n", szOutput));
2293#endif
2294 }
2295 pVM->hm.s.cPatches = 0;
2296 pVM->hm.s.PatchTree = 0;
2297 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2298 pVM->hm.s.fTPRPatchingActive = false;
2299 return VINF_SUCCESS;
2300}
2301
2302
2303/**
2304 * Worker for enabling patching in a VT-x/AMD-V guest.
2305 *
2306 * @returns VBox status code.
2307 * @param pVM The cross context VM structure.
2308 * @param idCpu VCPU to execute hmR3RemovePatches on.
2309 * @param pPatchMem Patch memory range.
2310 * @param cbPatchMem Size of the memory range.
2311 */
2312static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2313{
2314 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2315 AssertRC(rc);
2316
2317 pVM->hm.s.pGuestPatchMem = pPatchMem;
2318 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2319 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2320 return VINF_SUCCESS;
2321}
2322
2323
2324/**
2325 * Enable patching in a VT-x/AMD-V guest
2326 *
2327 * @returns VBox status code.
2328 * @param pVM The cross context VM structure.
2329 * @param pPatchMem Patch memory range.
2330 * @param cbPatchMem Size of the memory range.
2331 */
2332VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2333{
2334 VM_ASSERT_EMT(pVM);
2335 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2336 if (pVM->cCpus > 1)
2337 {
2338 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2339 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2340 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2341 AssertRC(rc);
2342 return rc;
2343 }
2344 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2345}
2346
2347
2348/**
2349 * Disable patching in a VT-x/AMD-V guest.
2350 *
2351 * @returns VBox status code.
2352 * @param pVM The cross context VM structure.
2353 * @param pPatchMem Patch memory range.
2354 * @param cbPatchMem Size of the memory range.
2355 */
2356VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2357{
2358 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2359 RT_NOREF2(pPatchMem, cbPatchMem);
2360
2361 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2362 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2363
2364 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2365 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2366 (void *)(uintptr_t)VMMGetCpuId(pVM));
2367 AssertRC(rc);
2368
2369 pVM->hm.s.pGuestPatchMem = 0;
2370 pVM->hm.s.pFreeGuestPatchMem = 0;
2371 pVM->hm.s.cbGuestPatchMem = 0;
2372 pVM->hm.s.fTPRPatchingActive = false;
2373 return VINF_SUCCESS;
2374}
2375
2376
2377/**
2378 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2379 *
2380 * @returns VBox strict status code.
2381 * @param pVM The cross context VM structure.
2382 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2383 * @param pvUser User specified CPU context.
2384 *
2385 */
2386static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2387{
2388 /*
2389 * Only execute the handler on the VCPU the original patch request was
2390 * issued. (The other CPU(s) might not yet have switched to protected
2391 * mode, nor have the correct memory context.)
2392 */
2393 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2394 if (pVCpu->idCpu != idCpu)
2395 return VINF_SUCCESS;
2396
2397 /*
2398 * We're racing other VCPUs here, so don't try patch the instruction twice
2399 * and make sure there is still room for our patch record.
2400 */
2401 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2402 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2403 if (pPatch)
2404 {
2405 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2406 return VINF_SUCCESS;
2407 }
2408 uint32_t const idx = pVM->hm.s.cPatches;
2409 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2410 {
2411 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2412 return VINF_SUCCESS;
2413 }
2414 pPatch = &pVM->hm.s.aPatches[idx];
2415
2416 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2417
2418 /*
2419 * Disassembler the instruction and get cracking.
2420 */
2421 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2422 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2423 uint32_t cbOp;
2424 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2425 AssertRC(rc);
2426 if ( rc == VINF_SUCCESS
2427 && pDis->pCurInstr->uOpcode == OP_MOV
2428 && cbOp >= 3)
2429 {
2430 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2431
2432 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2433 AssertRC(rc);
2434
2435 pPatch->cbOp = cbOp;
2436
2437 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2438 {
2439 /* write. */
2440 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2441 {
2442 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2443 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2444 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2445 }
2446 else
2447 {
2448 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2449 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2450 pPatch->uSrcOperand = pDis->Param2.uValue;
2451 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2452 }
2453 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2454 AssertRC(rc);
2455
2456 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2457 pPatch->cbNewOp = sizeof(s_abVMMCall);
2458 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2459 }
2460 else
2461 {
2462 /*
2463 * TPR Read.
2464 *
2465 * Found:
2466 * mov eax, dword [fffe0080] (5 bytes)
2467 * Check if next instruction is:
2468 * shr eax, 4
2469 */
2470 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2471
2472 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2473 uint8_t const cbOpMmio = cbOp;
2474 uint64_t const uSavedRip = pCtx->rip;
2475
2476 pCtx->rip += cbOp;
2477 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2478 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2479 pCtx->rip = uSavedRip;
2480
2481 if ( rc == VINF_SUCCESS
2482 && pDis->pCurInstr->uOpcode == OP_SHR
2483 && pDis->Param1.fUse == DISUSE_REG_GEN32
2484 && pDis->Param1.Base.idxGenReg == idxMmioReg
2485 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2486 && pDis->Param2.uValue == 4
2487 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2488 {
2489 uint8_t abInstr[15];
2490
2491 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2492 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2493 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2494 AssertRC(rc);
2495
2496 pPatch->cbOp = cbOpMmio + cbOp;
2497
2498 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2499 abInstr[0] = 0xf0;
2500 abInstr[1] = 0x0f;
2501 abInstr[2] = 0x20;
2502 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2503 for (unsigned i = 4; i < pPatch->cbOp; i++)
2504 abInstr[i] = 0x90; /* nop */
2505
2506 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2507 AssertRC(rc);
2508
2509 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2510 pPatch->cbNewOp = pPatch->cbOp;
2511 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2512
2513 Log(("Acceptable read/shr candidate!\n"));
2514 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2515 }
2516 else
2517 {
2518 pPatch->enmType = HMTPRINSTR_READ;
2519 pPatch->uDstOperand = idxMmioReg;
2520
2521 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2522 AssertRC(rc);
2523
2524 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2525 pPatch->cbNewOp = sizeof(s_abVMMCall);
2526 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2527 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2528 }
2529 }
2530
2531 pPatch->Core.Key = pCtx->eip;
2532 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2533 AssertRC(rc);
2534
2535 pVM->hm.s.cPatches++;
2536 return VINF_SUCCESS;
2537 }
2538
2539 /*
2540 * Save invalid patch, so we will not try again.
2541 */
2542 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2543 pPatch->Core.Key = pCtx->eip;
2544 pPatch->enmType = HMTPRINSTR_INVALID;
2545 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2546 AssertRC(rc);
2547 pVM->hm.s.cPatches++;
2548 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2549 return VINF_SUCCESS;
2550}
2551
2552
2553/**
2554 * Callback to patch a TPR instruction (jump to generated code).
2555 *
2556 * @returns VBox strict status code.
2557 * @param pVM The cross context VM structure.
2558 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2559 * @param pvUser User specified CPU context.
2560 *
2561 */
2562static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2563{
2564 /*
2565 * Only execute the handler on the VCPU the original patch request was
2566 * issued. (The other CPU(s) might not yet have switched to protected
2567 * mode, nor have the correct memory context.)
2568 */
2569 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2570 if (pVCpu->idCpu != idCpu)
2571 return VINF_SUCCESS;
2572
2573 /*
2574 * We're racing other VCPUs here, so don't try patch the instruction twice
2575 * and make sure there is still room for our patch record.
2576 */
2577 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2578 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2579 if (pPatch)
2580 {
2581 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2582 return VINF_SUCCESS;
2583 }
2584 uint32_t const idx = pVM->hm.s.cPatches;
2585 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2586 {
2587 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2588 return VINF_SUCCESS;
2589 }
2590 pPatch = &pVM->hm.s.aPatches[idx];
2591
2592 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2593 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2594
2595 /*
2596 * Disassemble the instruction and get cracking.
2597 */
2598 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2599 uint32_t cbOp;
2600 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2601 AssertRC(rc);
2602 if ( rc == VINF_SUCCESS
2603 && pDis->pCurInstr->uOpcode == OP_MOV
2604 && cbOp >= 5)
2605 {
2606 uint8_t aPatch[64];
2607 uint32_t off = 0;
2608
2609 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2610 AssertRC(rc);
2611
2612 pPatch->cbOp = cbOp;
2613 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2614
2615 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2616 {
2617 /*
2618 * TPR write:
2619 *
2620 * push ECX [51]
2621 * push EDX [52]
2622 * push EAX [50]
2623 * xor EDX,EDX [31 D2]
2624 * mov EAX,EAX [89 C0]
2625 * or
2626 * mov EAX,0000000CCh [B8 CC 00 00 00]
2627 * mov ECX,0C0000082h [B9 82 00 00 C0]
2628 * wrmsr [0F 30]
2629 * pop EAX [58]
2630 * pop EDX [5A]
2631 * pop ECX [59]
2632 * jmp return_address [E9 return_address]
2633 */
2634 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2635
2636 aPatch[off++] = 0x51; /* push ecx */
2637 aPatch[off++] = 0x52; /* push edx */
2638 if (!fUsesEax)
2639 aPatch[off++] = 0x50; /* push eax */
2640 aPatch[off++] = 0x31; /* xor edx, edx */
2641 aPatch[off++] = 0xd2;
2642 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2643 {
2644 if (!fUsesEax)
2645 {
2646 aPatch[off++] = 0x89; /* mov eax, src_reg */
2647 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2648 }
2649 }
2650 else
2651 {
2652 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2653 aPatch[off++] = 0xb8; /* mov eax, immediate */
2654 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2655 off += sizeof(uint32_t);
2656 }
2657 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2658 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2659 off += sizeof(uint32_t);
2660
2661 aPatch[off++] = 0x0f; /* wrmsr */
2662 aPatch[off++] = 0x30;
2663 if (!fUsesEax)
2664 aPatch[off++] = 0x58; /* pop eax */
2665 aPatch[off++] = 0x5a; /* pop edx */
2666 aPatch[off++] = 0x59; /* pop ecx */
2667 }
2668 else
2669 {
2670 /*
2671 * TPR read:
2672 *
2673 * push ECX [51]
2674 * push EDX [52]
2675 * push EAX [50]
2676 * mov ECX,0C0000082h [B9 82 00 00 C0]
2677 * rdmsr [0F 32]
2678 * mov EAX,EAX [89 C0]
2679 * pop EAX [58]
2680 * pop EDX [5A]
2681 * pop ECX [59]
2682 * jmp return_address [E9 return_address]
2683 */
2684 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2685
2686 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2687 aPatch[off++] = 0x51; /* push ecx */
2688 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2689 aPatch[off++] = 0x52; /* push edx */
2690 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2691 aPatch[off++] = 0x50; /* push eax */
2692
2693 aPatch[off++] = 0x31; /* xor edx, edx */
2694 aPatch[off++] = 0xd2;
2695
2696 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2697 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2698 off += sizeof(uint32_t);
2699
2700 aPatch[off++] = 0x0f; /* rdmsr */
2701 aPatch[off++] = 0x32;
2702
2703 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2704 {
2705 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2706 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2707 }
2708
2709 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2710 aPatch[off++] = 0x58; /* pop eax */
2711 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2712 aPatch[off++] = 0x5a; /* pop edx */
2713 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2714 aPatch[off++] = 0x59; /* pop ecx */
2715 }
2716 aPatch[off++] = 0xe9; /* jmp return_address */
2717 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2718 off += sizeof(RTRCUINTPTR);
2719
2720 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2721 {
2722 /* Write new code to the patch buffer. */
2723 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2724 AssertRC(rc);
2725
2726#ifdef LOG_ENABLED
2727 uint32_t cbCurInstr;
2728 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2729 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2730 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2731 {
2732 char szOutput[256];
2733 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2734 szOutput, sizeof(szOutput), &cbCurInstr);
2735 if (RT_SUCCESS(rc))
2736 Log(("Patch instr %s\n", szOutput));
2737 else
2738 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2739 }
2740#endif
2741
2742 pPatch->aNewOpcode[0] = 0xE9;
2743 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2744
2745 /* Overwrite the TPR instruction with a jump. */
2746 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2747 AssertRC(rc);
2748
2749 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2750
2751 pVM->hm.s.pFreeGuestPatchMem += off;
2752 pPatch->cbNewOp = 5;
2753
2754 pPatch->Core.Key = pCtx->eip;
2755 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2756 AssertRC(rc);
2757
2758 pVM->hm.s.cPatches++;
2759 pVM->hm.s.fTPRPatchingActive = true;
2760 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2761 return VINF_SUCCESS;
2762 }
2763
2764 Log(("Ran out of space in our patch buffer!\n"));
2765 }
2766 else
2767 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2768
2769
2770 /*
2771 * Save invalid patch, so we will not try again.
2772 */
2773 pPatch = &pVM->hm.s.aPatches[idx];
2774 pPatch->Core.Key = pCtx->eip;
2775 pPatch->enmType = HMTPRINSTR_INVALID;
2776 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2777 AssertRC(rc);
2778 pVM->hm.s.cPatches++;
2779 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2780 return VINF_SUCCESS;
2781}
2782
2783
2784/**
2785 * Attempt to patch TPR mmio instructions.
2786 *
2787 * @returns VBox status code.
2788 * @param pVM The cross context VM structure.
2789 * @param pVCpu The cross context virtual CPU structure.
2790 */
2791VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2792{
2793 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2794 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2795 (void *)(uintptr_t)pVCpu->idCpu);
2796 AssertRC(rc);
2797 return rc;
2798}
2799
2800
2801/**
2802 * Checks if we need to reschedule due to VMM device heap changes.
2803 *
2804 * @returns true if a reschedule is required, otherwise false.
2805 * @param pVM The cross context VM structure.
2806 * @param pCtx VM execution context.
2807 */
2808VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2809{
2810 /*
2811 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2812 * when the unrestricted guest execution feature is missing (VT-x only).
2813 */
2814 if ( pVM->hm.s.vmx.fEnabled
2815 && !pVM->hm.s.vmx.fUnrestrictedGuest
2816 && CPUMIsGuestInRealModeEx(pCtx)
2817 && !PDMVmmDevHeapIsEnabled(pVM))
2818 return true;
2819
2820 return false;
2821}
2822
2823
2824/**
2825 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2826 * event settings changes.
2827 *
2828 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2829 * function is just updating the VM globals.
2830 *
2831 * @param pVM The VM cross context VM structure.
2832 * @thread EMT(0)
2833 */
2834VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2835{
2836 /* Interrupts. */
2837 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2838 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2839
2840 /* CPU Exceptions. */
2841 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2842 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2843 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2844 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2845
2846 /* Common VM exits. */
2847 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2848 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2849 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2850 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2851
2852 /* Vendor specific VM exits. */
2853 if (HMR3IsVmxEnabled(pVM->pUVM))
2854 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2855 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2856 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2857 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2858 else
2859 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2860 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2861 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2862 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2863
2864 /* Done. */
2865 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2866}
2867
2868
2869/**
2870 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2871 *
2872 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2873 * per CPU settings.
2874 *
2875 * @param pVM The VM cross context VM structure.
2876 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2877 */
2878VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2879{
2880 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2881}
2882
2883
2884/**
2885 * Checks if we are currently using hardware acceleration.
2886 *
2887 * @returns true if hardware acceleration is being used, otherwise false.
2888 * @param pVCpu The cross context virtual CPU structure.
2889 */
2890VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2891{
2892 return pVCpu->hm.s.fActive;
2893}
2894
2895
2896/**
2897 * External interface for querying whether hardware acceleration is enabled.
2898 *
2899 * @returns true if VT-x or AMD-V is being used, otherwise false.
2900 * @param pUVM The user mode VM handle.
2901 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2902 */
2903VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2904{
2905 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2906 PVM pVM = pUVM->pVM;
2907 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2908 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2909}
2910
2911
2912/**
2913 * External interface for querying whether VT-x is being used.
2914 *
2915 * @returns true if VT-x is being used, otherwise false.
2916 * @param pUVM The user mode VM handle.
2917 * @sa HMR3IsSvmEnabled, HMIsEnabled
2918 */
2919VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2920{
2921 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2922 PVM pVM = pUVM->pVM;
2923 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2924 return pVM->hm.s.vmx.fEnabled
2925 && pVM->hm.s.vmx.fSupported
2926 && pVM->fHMEnabled;
2927}
2928
2929
2930/**
2931 * External interface for querying whether AMD-V is being used.
2932 *
2933 * @returns true if VT-x is being used, otherwise false.
2934 * @param pUVM The user mode VM handle.
2935 * @sa HMR3IsVmxEnabled, HMIsEnabled
2936 */
2937VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2938{
2939 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2940 PVM pVM = pUVM->pVM;
2941 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2942 return pVM->hm.s.svm.fEnabled
2943 && pVM->hm.s.svm.fSupported
2944 && pVM->fHMEnabled;
2945}
2946
2947
2948/**
2949 * Checks if we are currently using nested paging.
2950 *
2951 * @returns true if nested paging is being used, otherwise false.
2952 * @param pUVM The user mode VM handle.
2953 */
2954VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2955{
2956 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2957 PVM pVM = pUVM->pVM;
2958 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2959 return pVM->hm.s.fNestedPaging;
2960}
2961
2962
2963/**
2964 * Checks if virtualized APIC registers is enabled.
2965 *
2966 * When enabled this feature allows the hardware to access most of the
2967 * APIC registers in the virtual-APIC page without causing VM-exits. See
2968 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2969 *
2970 * @returns true if virtualized APIC registers is enabled, otherwise
2971 * false.
2972 * @param pUVM The user mode VM handle.
2973 */
2974VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2975{
2976 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2977 PVM pVM = pUVM->pVM;
2978 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2979 return pVM->hm.s.fVirtApicRegs;
2980}
2981
2982
2983/**
2984 * Checks if APIC posted-interrupt processing is enabled.
2985 *
2986 * This returns whether we can deliver interrupts to the guest without
2987 * leaving guest-context by updating APIC state from host-context.
2988 *
2989 * @returns true if APIC posted-interrupt processing is enabled,
2990 * otherwise false.
2991 * @param pUVM The user mode VM handle.
2992 */
2993VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2994{
2995 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2996 PVM pVM = pUVM->pVM;
2997 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2998 return pVM->hm.s.fPostedIntrs;
2999}
3000
3001
3002/**
3003 * Checks if we are currently using VPID in VT-x mode.
3004 *
3005 * @returns true if VPID is being used, otherwise false.
3006 * @param pUVM The user mode VM handle.
3007 */
3008VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3009{
3010 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3011 PVM pVM = pUVM->pVM;
3012 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3013 return pVM->hm.s.vmx.fVpid;
3014}
3015
3016
3017/**
3018 * Checks if we are currently using VT-x unrestricted execution,
3019 * aka UX.
3020 *
3021 * @returns true if UX is being used, otherwise false.
3022 * @param pUVM The user mode VM handle.
3023 */
3024VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3025{
3026 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3027 PVM pVM = pUVM->pVM;
3028 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3029 return pVM->hm.s.vmx.fUnrestrictedGuest
3030 || pVM->hm.s.svm.fSupported;
3031}
3032
3033
3034/**
3035 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3036 *
3037 * @returns true if an internal event is pending, otherwise false.
3038 * @param pVCpu The cross context virtual CPU structure.
3039 */
3040VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3041{
3042 return HMIsEnabled(pVCpu->pVMR3)
3043 && pVCpu->hm.s.Event.fPending;
3044}
3045
3046
3047/**
3048 * Checks if the VMX-preemption timer is being used.
3049 *
3050 * @returns true if the VMX-preemption timer is being used, otherwise false.
3051 * @param pVM The cross context VM structure.
3052 */
3053VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3054{
3055 return HMIsEnabled(pVM)
3056 && pVM->hm.s.vmx.fEnabled
3057 && pVM->hm.s.vmx.fUsePreemptTimer;
3058}
3059
3060
3061/**
3062 * Check fatal VT-x/AMD-V error and produce some meaningful
3063 * log release message.
3064 *
3065 * @param pVM The cross context VM structure.
3066 * @param iStatusCode VBox status code.
3067 */
3068VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3069{
3070 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3071 {
3072 PVMCPU pVCpu = &pVM->aCpus[i];
3073 switch (iStatusCode)
3074 {
3075 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3076 * might be getting inaccurate values for non-guru'ing EMTs. */
3077 case VERR_VMX_INVALID_VMCS_FIELD:
3078 break;
3079
3080 case VERR_VMX_INVALID_VMCS_PTR:
3081 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3082 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VmcsPhys,
3083 pVCpu->hm.s.vmx.HCPhysVmcs));
3084 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3085 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3086 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3087 break;
3088
3089 case VERR_VMX_UNABLE_TO_START_VM:
3090 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3091 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3092 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3093
3094 if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3095 || pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3096 {
3097 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3098 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3099 }
3100 else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3101 {
3102 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3103 {
3104 uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
3105 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
3106 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
3107 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
3108 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
3109 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
3110 }
3111 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3112 {
3113 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
3114 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
3115 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
3116 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
3117 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
3118 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
3119 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
3120 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
3121 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
3122 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
3123 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
3124 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
3125 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
3126 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
3127 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
3128 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
3129 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
3130 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
3131 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
3132 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
3133 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
3134 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
3135 }
3136 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3137 {
3138 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
3139 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
3140 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
3141 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
3142 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
3143 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
3144 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
3145 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
3146 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
3147 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
3148 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
3149 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
3150 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
3151 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
3152 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
3153 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
3154 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
3155 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
3156 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
3157 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
3158 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_FROM_PT );
3159 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
3160 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
3161 }
3162 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3163 {
3164 uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
3165 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3166 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3167 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3168 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3169 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3170 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3171 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3172 }
3173 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3174 {
3175 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
3176 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3177 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3178 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3179 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3180 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3181 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3182 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3183 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3184 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3185 }
3186 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3187 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3188 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3189 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3190 }
3191 /** @todo Log VM-entry event injection control fields
3192 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3193 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3194 break;
3195
3196 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3197 case VERR_VMX_INVALID_VMXON_PTR:
3198 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3199 case VERR_VMX_INVALID_GUEST_STATE:
3200 case VERR_VMX_UNEXPECTED_EXIT:
3201 case VERR_SVM_UNKNOWN_EXIT:
3202 case VERR_SVM_UNEXPECTED_EXIT:
3203 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3204 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3205 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3206 break;
3207 }
3208 }
3209
3210 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3211 {
3212 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3213 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3214 }
3215 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3216 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3217}
3218
3219
3220/**
3221 * Execute state save operation.
3222 *
3223 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3224 * is because we always save the VM state from ring-3 and thus most HM state
3225 * will be re-synced dynamically at runtime and don't need to be part of the VM
3226 * saved state.
3227 *
3228 * @returns VBox status code.
3229 * @param pVM The cross context VM structure.
3230 * @param pSSM SSM operation handle.
3231 */
3232static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3233{
3234 int rc;
3235
3236 Log(("hmR3Save:\n"));
3237
3238 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3239 {
3240 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3241 if (pVM->cpum.ro.GuestFeatures.fSvm)
3242 {
3243 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3244 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3245 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3246 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3247 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3248 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3249 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3250 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3251 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3252 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3253 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3254 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3255 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3256 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3257 AssertRCReturn(rc, rc);
3258 }
3259 }
3260
3261 /* Save the guest patch data. */
3262 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3263 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3264 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3265
3266 /* Store all the guest patch records too. */
3267 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3268 AssertRCReturn(rc, rc);
3269
3270 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3271 {
3272 AssertCompileSize(HMTPRINSTR, 4);
3273 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3274 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3275 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3276 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3277 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3278 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3279 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3280 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3281 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3282 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3283 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3284 AssertRCReturn(rc, rc);
3285 }
3286
3287 return VINF_SUCCESS;
3288}
3289
3290
3291/**
3292 * Execute state load operation.
3293 *
3294 * @returns VBox status code.
3295 * @param pVM The cross context VM structure.
3296 * @param pSSM SSM operation handle.
3297 * @param uVersion Data layout version.
3298 * @param uPass The data pass.
3299 */
3300static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3301{
3302 int rc;
3303
3304 LogFlowFunc(("uVersion=%u\n", uVersion));
3305 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3306
3307 /*
3308 * Validate version.
3309 */
3310 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3311 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3312 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3313 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3314 {
3315 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3316 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3317 }
3318
3319 /*
3320 * Load per-VCPU state.
3321 */
3322 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3323 {
3324 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3325 {
3326 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3327 if (pVM->cpum.ro.GuestFeatures.fSvm)
3328 {
3329 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3330 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3331 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3332 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3333 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3334 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3335 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3336 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3337 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3338 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3339 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3340 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3341 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3342 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3343 AssertRCReturn(rc, rc);
3344 }
3345 }
3346 else
3347 {
3348 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3349 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3350 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3351 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3352
3353 /* VMX fWasInRealMode related data. */
3354 uint32_t uDummy;
3355 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3356 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3357 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3358 AssertRCReturn(rc, rc);
3359 }
3360 }
3361
3362 /*
3363 * Load TPR patching data.
3364 */
3365 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3366 {
3367 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3368 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3369 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3370
3371 /* Fetch all TPR patch records. */
3372 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3373 AssertRCReturn(rc, rc);
3374 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3375 {
3376 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3377 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3378 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3379 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3380 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3381 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3382 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3383
3384 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3385 pVM->hm.s.fTPRPatchingActive = true;
3386 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3387
3388 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3389 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3390 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3391 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3392 AssertRCReturn(rc, rc);
3393
3394 LogFlow(("hmR3Load: patch %d\n", i));
3395 LogFlow(("Key = %x\n", pPatch->Core.Key));
3396 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3397 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3398 LogFlow(("type = %d\n", pPatch->enmType));
3399 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3400 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3401 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3402 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3403
3404 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3405 AssertRCReturn(rc, rc);
3406 }
3407 }
3408
3409 return VINF_SUCCESS;
3410}
3411
3412
3413/**
3414 * Gets the name of a VT-x exit code.
3415 *
3416 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3417 * @param uExit The VT-x exit to name.
3418 */
3419VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
3420{
3421 if (uExit < RT_ELEMENTS(g_apszVmxExitReasons))
3422 return g_apszVmxExitReasons[uExit];
3423 return NULL;
3424}
3425
3426
3427/**
3428 * Gets the name of an AMD-V exit code.
3429 *
3430 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3431 * @param uExit The AMD-V exit to name.
3432 */
3433VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
3434{
3435 if (uExit < RT_ELEMENTS(g_apszSvmExitReasons))
3436 return g_apszSvmExitReasons[uExit];
3437 return hmSvmGetSpecialExitReasonDesc(uExit);
3438}
3439
3440
3441/**
3442 * Displays HM info.
3443 *
3444 * @param pVM The cross context VM structure.
3445 * @param pHlp The info helper functions.
3446 * @param pszArgs Arguments, ignored.
3447 */
3448static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3449{
3450 NOREF(pszArgs);
3451 PVMCPU pVCpu = VMMGetCpu(pVM);
3452 if (!pVCpu)
3453 pVCpu = &pVM->aCpus[0];
3454
3455 if (HMIsEnabled(pVM))
3456 {
3457 if (pVM->hm.s.vmx.fSupported)
3458 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3459 else
3460 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3461 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3462 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3463 }
3464 else
3465 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3466}
3467
3468
3469/**
3470 * Displays the HM pending event.
3471 *
3472 * @param pVM The cross context VM structure.
3473 * @param pHlp The info helper functions.
3474 * @param pszArgs Arguments, ignored.
3475 */
3476static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3477{
3478 NOREF(pszArgs);
3479 PVMCPU pVCpu = VMMGetCpu(pVM);
3480 if (!pVCpu)
3481 pVCpu = &pVM->aCpus[0];
3482
3483 if (HMIsEnabled(pVM))
3484 {
3485 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3486 if (pVCpu->hm.s.Event.fPending)
3487 {
3488 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3489 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3490 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3491 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3492 }
3493 }
3494 else
3495 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3496}
3497
3498
3499/**
3500 * Displays the SVM nested-guest VMCB cache.
3501 *
3502 * @param pVM The cross context VM structure.
3503 * @param pHlp The info helper functions.
3504 * @param pszArgs Arguments, ignored.
3505 */
3506static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3507{
3508 NOREF(pszArgs);
3509 PVMCPU pVCpu = VMMGetCpu(pVM);
3510 if (!pVCpu)
3511 pVCpu = &pVM->aCpus[0];
3512
3513 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3514 if ( fSvmEnabled
3515 && pVM->cpum.ro.GuestFeatures.fSvm)
3516 {
3517 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3518 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3519 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3520 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3521 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3522 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3523 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3524 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3525 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3526 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3527 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3528 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3529 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3530 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3531 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3532 }
3533 else
3534 {
3535 if (!fSvmEnabled)
3536 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3537 else
3538 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3539 }
3540}
3541
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