VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 96860

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1/* $Id: DBGFDisas.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DBGF
33#include <VBox/vmm/dbgf.h>
34#include <VBox/vmm/selm.h>
35#include <VBox/vmm/mm.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/pgm.h>
38#include <VBox/vmm/cpum.h>
39#include "DBGFInternal.h"
40#include <VBox/dis.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43#include <VBox/vmm/vm.h>
44#include <VBox/vmm/uvm.h>
45
46#include <VBox/log.h>
47#include <iprt/assert.h>
48#include <iprt/string.h>
49#include <iprt/alloca.h>
50#include <iprt/ctype.h>
51
52
53/*********************************************************************************************************************************
54* Structures and Typedefs *
55*********************************************************************************************************************************/
56/**
57 * Structure used when disassembling and instructions in DBGF.
58 * This is used so the reader function can get the stuff it needs.
59 */
60typedef struct
61{
62 /** The core structure. */
63 DISCPUSTATE Cpu;
64 /** The cross context VM structure. */
65 PVM pVM;
66 /** The cross context virtual CPU structure. */
67 PVMCPU pVCpu;
68 /** The address space for resolving symbol. */
69 RTDBGAS hDbgAs;
70 /** Pointer to the first byte in the segment. */
71 RTGCUINTPTR GCPtrSegBase;
72 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
73 RTGCUINTPTR GCPtrSegEnd;
74 /** The size of the segment minus 1. */
75 RTGCUINTPTR cbSegLimit;
76 /** The guest paging mode. */
77 PGMMODE enmMode;
78 /** Pointer to the current page - R3 Ptr. */
79 void const *pvPageR3;
80 /** Pointer to the current page - GC Ptr. */
81 RTGCPTR GCPtrPage;
82 /** Pointer to the next instruction (relative to GCPtrSegBase). */
83 RTGCUINTPTR GCPtrNext;
84 /** The lock information that PGMPhysReleasePageMappingLock needs. */
85 PGMPAGEMAPLOCK PageMapLock;
86 /** Whether the PageMapLock is valid or not. */
87 bool fLocked;
88 /** 64 bits mode or not. */
89 bool f64Bits;
90} DBGFDISASSTATE, *PDBGFDISASSTATE;
91
92
93/*********************************************************************************************************************************
94* Internal Functions *
95*********************************************************************************************************************************/
96static FNDISREADBYTES dbgfR3DisasInstrRead;
97
98
99
100/**
101 * Calls the disassembler with the proper reader functions and such for disa
102 *
103 * @returns VBox status code.
104 * @param pVM The cross context VM structure.
105 * @param pVCpu The cross context virtual CPU structure.
106 * @param pSelInfo The selector info.
107 * @param enmMode The guest paging mode.
108 * @param fFlags DBGF_DISAS_FLAGS_XXX.
109 * @param GCPtr The GC pointer (selector offset).
110 * @param pState The disas CPU state.
111 */
112static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
113 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
114{
115 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
116 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
117 pState->cbSegLimit = pSelInfo->cbLimit;
118 pState->enmMode = enmMode;
119 pState->GCPtrPage = 0;
120 pState->pvPageR3 = NULL;
121 pState->hDbgAs = DBGF_AS_GLOBAL;
122 pState->pVM = pVM;
123 pState->pVCpu = pVCpu;
124 pState->fLocked = false;
125 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
126
127 DISCPUMODE enmCpuMode;
128 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
129 {
130 default:
131 AssertFailed();
132 RT_FALL_THRU();
133 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
134 enmCpuMode = pState->f64Bits
135 ? DISCPUMODE_64BIT
136 : pSelInfo->u.Raw.Gen.u1DefBig
137 ? DISCPUMODE_32BIT
138 : DISCPUMODE_16BIT;
139 break;
140 case DBGF_DISAS_FLAGS_16BIT_MODE:
141 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
142 enmCpuMode = DISCPUMODE_16BIT;
143 break;
144 case DBGF_DISAS_FLAGS_32BIT_MODE:
145 enmCpuMode = DISCPUMODE_32BIT;
146 break;
147 case DBGF_DISAS_FLAGS_64BIT_MODE:
148 enmCpuMode = DISCPUMODE_64BIT;
149 break;
150 }
151
152 uint32_t cbInstr;
153 int rc = DISInstrWithReader(GCPtr,
154 enmCpuMode,
155 dbgfR3DisasInstrRead,
156 &pState->Cpu,
157 &pState->Cpu,
158 &cbInstr);
159 if (RT_SUCCESS(rc))
160 {
161 pState->GCPtrNext = GCPtr + cbInstr;
162 return VINF_SUCCESS;
163 }
164
165 /* cleanup */
166 if (pState->fLocked)
167 {
168 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
169 pState->fLocked = false;
170 }
171 return rc;
172}
173
174
175#if 0
176/**
177 * Calls the disassembler for disassembling the next instruction.
178 *
179 * @returns VBox status code.
180 * @param pState The disas CPU state.
181 */
182static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
183{
184 uint32_t cbInstr;
185 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
186 if (RT_SUCCESS(rc))
187 {
188 pState->GCPtrNext = GCPtr + cbInstr;
189 return VINF_SUCCESS;
190 }
191 return rc;
192}
193#endif
194
195
196/**
197 * Done with the disassembler state, free associated resources.
198 *
199 * @param pState The disas CPU state ++.
200 */
201static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
202{
203 if (pState->fLocked)
204 {
205 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
206 pState->fLocked = false;
207 }
208}
209
210
211/**
212 * @callback_method_impl{FNDISREADBYTES}
213 *
214 * @remarks The source is relative to the base address indicated by
215 * DBGFDISASSTATE::GCPtrSegBase.
216 */
217static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
218{
219 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
220 for (;;)
221 {
222 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
223
224 /*
225 * Need to update the page translation?
226 */
227 if ( !pState->pvPageR3
228 || (GCPtr >> GUEST_PAGE_SHIFT) != (pState->GCPtrPage >> GUEST_PAGE_SHIFT))
229 {
230 int rc = VINF_SUCCESS;
231
232 /* translate the address */
233 pState->GCPtrPage = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
234 if (pState->fLocked)
235 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
236 if (pState->enmMode <= PGMMODE_PROTECTED)
237 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
238 else
239 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
240 if (RT_SUCCESS(rc))
241 pState->fLocked = true;
242 else
243 {
244 pState->fLocked = false;
245 pState->pvPageR3 = NULL;
246 return rc;
247 }
248 }
249
250 /*
251 * Check the segment limit.
252 */
253 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
254 return VERR_OUT_OF_SELECTOR_BOUNDS;
255
256 /*
257 * Calc how much we can read, maxing out the read.
258 */
259 uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
260 if (!pState->f64Bits)
261 {
262 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
263 if (cb > cbSeg && cbSeg)
264 cb = cbSeg;
265 }
266 if (cb > cbMaxRead)
267 cb = cbMaxRead;
268
269 /*
270 * Read and advance,
271 */
272 memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
273 offInstr += (uint8_t)cb;
274 if (cb >= cbMinRead)
275 {
276 pDis->cbCachedInstr = offInstr;
277 return VINF_SUCCESS;
278 }
279 cbMaxRead -= (uint8_t)cb;
280 cbMinRead -= (uint8_t)cb;
281 }
282}
283
284
285/**
286 * @callback_method_impl{FNDISGETSYMBOL}
287 */
288static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
289 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
290{
291 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
292 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
293
294 /*
295 * Address conversion
296 */
297 DBGFADDRESS Addr;
298 int rc;
299 /* Start with CS. */
300 if ( DIS_FMT_SEL_IS_REG(u32Sel)
301 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
302 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
303 rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
304 /* In long mode everything but FS and GS is easy. */
305 else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
306 && DIS_FMT_SEL_IS_REG(u32Sel)
307 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
308 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
309 {
310 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
311 rc = VINF_SUCCESS;
312 }
313 /* Here's a quick hack to catch patch manager SS relative access. */
314 else if ( DIS_FMT_SEL_IS_REG(u32Sel)
315 && DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
316 && pSelInfo->GCPtrBase == 0
317 && pSelInfo->cbLimit >= UINT32_MAX)
318 {
319 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
320 rc = VINF_SUCCESS;
321 }
322 else
323 {
324 /** @todo implement a generic solution here. */
325 rc = VERR_SYMBOL_NOT_FOUND;
326 }
327
328 /*
329 * If we got an address, try resolve it into a symbol.
330 */
331 if (RT_SUCCESS(rc))
332 {
333 RTDBGSYMBOL Sym;
334 RTGCINTPTR off;
335 rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr,
336 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL | RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
337 &off, &Sym, NULL /*phMod*/);
338 if (RT_SUCCESS(rc))
339 {
340 /*
341 * Return the symbol and offset.
342 */
343 size_t cchName = strlen(Sym.szName);
344 if (cchName >= cchBuf)
345 cchName = cchBuf - 1;
346 memcpy(pszBuf, Sym.szName, cchName);
347 pszBuf[cchName] = '\0';
348
349 *poff = off;
350 }
351 }
352 return rc;
353}
354
355
356/**
357 * Disassembles the one instruction according to the specified flags and
358 * address, internal worker executing on the EMT of the specified virtual CPU.
359 *
360 * @returns VBox status code.
361 * @param pVM The cross context VM structure.
362 * @param pVCpu The cross context virtual CPU structure.
363 * @param Sel The code selector. This used to determine the 32/16 bit ness and
364 * calculation of the actual instruction address.
365 * @param pGCPtr Pointer to the variable holding the code address
366 * relative to the base of Sel.
367 * @param fFlags Flags controlling where to start and how to format.
368 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
369 * @param pszOutput Output buffer.
370 * @param cbOutput Size of the output buffer.
371 * @param pcbInstr Where to return the size of the instruction.
372 * @param pDisState Where to store the disassembler state into.
373 */
374static DECLCALLBACK(int)
375dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
376 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr, PDBGFDISSTATE pDisState)
377{
378 VMCPU_ASSERT_EMT(pVCpu);
379 RTGCPTR GCPtr = *pGCPtr;
380 int rc;
381
382 /*
383 * Get the Sel and GCPtr if fFlags requests that.
384 */
385 PCCPUMCTXCORE pCtxCore = NULL;
386 PCCPUMSELREG pSRegCS = NULL;
387 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
388 {
389 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
390 Sel = pCtxCore->cs.Sel;
391 pSRegCS = &pCtxCore->cs;
392 GCPtr = pCtxCore->rip;
393 }
394 /*
395 * Check if the selector matches the guest CS, use the hidden
396 * registers from that if they are valid. Saves time and effort.
397 */
398 else
399 {
400 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
401 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
402 pSRegCS = &pCtxCore->cs;
403 else
404 pCtxCore = NULL;
405 }
406
407 /*
408 * Read the selector info - assume no stale selectors and nasty stuff like that.
409 *
410 * Note! We CANNOT load invalid hidden selector registers since that would
411 * mean that log/debug statements or the debug will influence the
412 * guest state and make things behave differently.
413 */
414 DBGFSELINFO SelInfo;
415 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
416 bool fRealModeAddress = false;
417
418 if ( pSRegCS
419 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
420 {
421 SelInfo.Sel = Sel;
422 SelInfo.SelGate = 0;
423 SelInfo.GCPtrBase = pSRegCS->u64Base;
424 SelInfo.cbLimit = pSRegCS->u32Limit;
425 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
426 ? DBGFSELINFO_FLAGS_LONG_MODE
427 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
428 ? DBGFSELINFO_FLAGS_PROT_MODE
429 : DBGFSELINFO_FLAGS_REAL_MODE;
430
431 SelInfo.u.Raw.au32[0] = 0;
432 SelInfo.u.Raw.au32[1] = 0;
433 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
434 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
435 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
436 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
437 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
438 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
439 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
440 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
441 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
442 }
443 else if (Sel == DBGF_SEL_FLAT)
444 {
445 SelInfo.Sel = Sel;
446 SelInfo.SelGate = 0;
447 SelInfo.GCPtrBase = 0;
448 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
449 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
450 ? DBGFSELINFO_FLAGS_LONG_MODE
451 : enmMode != PGMMODE_REAL
452 ? DBGFSELINFO_FLAGS_PROT_MODE
453 : DBGFSELINFO_FLAGS_REAL_MODE;
454 SelInfo.u.Raw.au32[0] = 0;
455 SelInfo.u.Raw.au32[1] = 0;
456 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
457 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
458
459 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
460 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
461 {
462 /* Assume the current CS defines the execution mode. */
463 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
464 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
465 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
466 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
467 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
468 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
469 }
470 else
471 {
472 pSRegCS = NULL;
473 SelInfo.u.Raw.Gen.u1Present = 1;
474 SelInfo.u.Raw.Gen.u1Granularity = 1;
475 SelInfo.u.Raw.Gen.u1DefBig = 1;
476 SelInfo.u.Raw.Gen.u1DescType = 1;
477 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
478 }
479 }
480 else if ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
481 || enmMode == PGMMODE_REAL
482 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE)
483 { /* V86 mode or real mode - real mode addressing */
484 SelInfo.Sel = Sel;
485 SelInfo.SelGate = 0;
486 SelInfo.GCPtrBase = Sel * 16;
487 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
488 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
489 SelInfo.u.Raw.au32[0] = 0;
490 SelInfo.u.Raw.au32[1] = 0;
491 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
492 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
493 SelInfo.u.Raw.Gen.u1Present = 1;
494 SelInfo.u.Raw.Gen.u1Granularity = 1;
495 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
496 SelInfo.u.Raw.Gen.u1DescType = 1;
497 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
498 fRealModeAddress = true;
499 }
500 else
501 {
502 rc = SELMR3GetSelectorInfo(pVCpu, Sel, &SelInfo);
503 if (RT_FAILURE(rc))
504 {
505 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
506 return rc;
507 }
508 }
509
510 /*
511 * Disassemble it.
512 */
513 DBGFDISASSTATE State;
514 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
515 if (RT_FAILURE(rc))
516 {
517 if (State.Cpu.cbCachedInstr)
518 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
519 else
520 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
521 return rc;
522 }
523
524 /*
525 * Format it.
526 */
527 char szBuf[512];
528 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
529 DIS_FMT_FLAGS_RELATIVE_BRANCH,
530 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
531 &SelInfo);
532
533 /*
534 * Print it to the user specified buffer.
535 */
536 size_t cch;
537 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
538 {
539 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
540 cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
541 else if (fRealModeAddress)
542 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
543 else if (Sel == DBGF_SEL_FLAT)
544 {
545 if (enmMode >= PGMMODE_AMD64)
546 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
547 else
548 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
549 }
550 else
551 {
552 if (enmMode >= PGMMODE_AMD64)
553 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
554 else
555 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
556 }
557 }
558 else
559 {
560 uint32_t cbInstr = State.Cpu.cbInstr;
561 uint8_t const *pabInstr = State.Cpu.abInstr;
562 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
563 cch = RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
564 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
565 szBuf);
566 else if (fRealModeAddress)
567 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
568 Sel, (unsigned)GCPtr,
569 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
570 szBuf);
571 else if (Sel == DBGF_SEL_FLAT)
572 {
573 if (enmMode >= PGMMODE_AMD64)
574 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
575 GCPtr,
576 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
577 szBuf);
578 else
579 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
580 (uint32_t)GCPtr,
581 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
582 szBuf);
583 }
584 else
585 {
586 if (enmMode >= PGMMODE_AMD64)
587 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
588 Sel, GCPtr,
589 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
590 szBuf);
591 else
592 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
593 Sel, (uint32_t)GCPtr,
594 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
595 szBuf);
596 }
597 }
598
599 if (pcbInstr)
600 *pcbInstr = State.Cpu.cbInstr;
601
602 if (pDisState)
603 {
604 pDisState->pCurInstr = State.Cpu.pCurInstr;
605 pDisState->cbInstr = State.Cpu.cbInstr;
606 pDisState->Param1 = State.Cpu.Param1;
607 pDisState->Param2 = State.Cpu.Param2;
608 pDisState->Param3 = State.Cpu.Param3;
609 pDisState->Param4 = State.Cpu.Param4;
610 }
611
612 dbgfR3DisasInstrDone(&State);
613 return VINF_SUCCESS;
614}
615
616
617/**
618 * Disassembles the one instruction according to the specified flags and address
619 * returning part of the disassembler state.
620 *
621 * @returns VBox status code.
622 * @param pUVM The user mode VM handle.
623 * @param idCpu The ID of virtual CPU.
624 * @param pAddr The code address.
625 * @param fFlags Flags controlling where to start and how to format.
626 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
627 * @param pszOutput Output buffer. This will always be properly
628 * terminated if @a cbOutput is greater than zero.
629 * @param cbOutput Size of the output buffer.
630 * @param pDisState The disassembler state to fill in.
631 *
632 * @remarks May have to switch to the EMT of the virtual CPU in order to do
633 * address conversion.
634 */
635DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
636 char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
637{
638 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
639 *pszOutput = '\0';
640 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
641 PVM pVM = pUVM->pVM;
642 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
643 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
644 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
645 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
646
647 /*
648 * Optimize the common case where we're called on the EMT of idCpu since
649 * we're using this all the time when logging.
650 */
651 int rc;
652 PVMCPU pVCpu = VMMGetCpu(pVM);
653 if ( pVCpu
654 && pVCpu->idCpu == idCpu)
655 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
656 else
657 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
658 pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
659 return rc;
660}
661
662/**
663 * Disassembles the one instruction according to the specified flags and address.
664 *
665 * @returns VBox status code.
666 * @param pUVM The user mode VM handle.
667 * @param idCpu The ID of virtual CPU.
668 * @param Sel The code selector. This used to determine the 32/16 bit ness and
669 * calculation of the actual instruction address.
670 * @param GCPtr The code address relative to the base of Sel.
671 * @param fFlags Flags controlling where to start and how to format.
672 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
673 * @param pszOutput Output buffer. This will always be properly
674 * terminated if @a cbOutput is greater than zero.
675 * @param cbOutput Size of the output buffer.
676 * @param pcbInstr Where to return the size of the instruction.
677 *
678 * @remarks May have to switch to the EMT of the virtual CPU in order to do
679 * address conversion.
680 */
681VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
682 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
683{
684 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
685 *pszOutput = '\0';
686 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
687 PVM pVM = pUVM->pVM;
688 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
689 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
690 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
691 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
692
693 /*
694 * Optimize the common case where we're called on the EMT of idCpu since
695 * we're using this all the time when logging.
696 */
697 int rc;
698 PVMCPU pVCpu = VMMGetCpu(pVM);
699 if ( pVCpu
700 && pVCpu->idCpu == idCpu)
701 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
702 else
703 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
704 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
705 return rc;
706}
707
708
709/**
710 * Disassembles the current guest context instruction.
711 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
712 *
713 * @returns VBox status code.
714 * @param pVCpu The cross context virtual CPU structure.
715 * @param pszOutput Output buffer. This will always be properly
716 * terminated if @a cbOutput is greater than zero.
717 * @param cbOutput Size of the output buffer.
718 * @thread EMT(pVCpu)
719 */
720VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
721{
722 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
723 *pszOutput = '\0';
724 Assert(VMCPU_IS_EMT(pVCpu));
725
726 RTGCPTR GCPtr = 0;
727 return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
728 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE
729 | DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
730 pszOutput, cbOutput, NULL, NULL);
731}
732
733
734/**
735 * Disassembles the current guest context instruction and writes it to the log.
736 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
737 *
738 * @returns VBox status code.
739 * @param pVCpu The cross context virtual CPU structure.
740 * @param pszPrefix Short prefix string to the disassembly string. (optional)
741 * @thread EMT(pVCpu)
742 */
743VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
744{
745 char szBuf[256];
746 szBuf[0] = '\0';
747 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
748 if (RT_FAILURE(rc))
749 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
750 if (pszPrefix && *pszPrefix)
751 {
752 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
753 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
754 else
755 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
756 }
757 else
758 RTLogPrintf("%s\n", szBuf);
759 return rc;
760}
761
762
763
764/**
765 * Disassembles the specified guest context instruction and writes it to the log.
766 * Addresses will be attempted resolved to symbols.
767 *
768 * @returns VBox status code.
769 * @param pVCpu The cross context virtual CPU structure of the calling
770 * EMT.
771 * @param Sel The code selector. This used to determine the 32/16
772 * bit-ness and calculation of the actual instruction
773 * address.
774 * @param GCPtr The code address relative to the base of Sel.
775 * @param pszPrefix Short prefix string to the disassembly string.
776 * (optional)
777 * @thread EMT(pVCpu)
778 */
779VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
780{
781 Assert(VMCPU_IS_EMT(pVCpu));
782
783 char szBuf[256];
784 RTGCPTR GCPtrTmp = GCPtr;
785 int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
786 &szBuf[0], sizeof(szBuf), NULL, NULL);
787 if (RT_FAILURE(rc))
788 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
789 if (pszPrefix && *pszPrefix)
790 {
791 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
792 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
793 else
794 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
795 }
796 else
797 RTLogPrintf("%s\n", szBuf);
798 return rc;
799}
800
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