VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 80007

Last change on this file since 80007 was 80007, checked in by vboxsync, 5 years ago

VMM: Kicking out raw-mode (work in progress). bugref:9517
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1/* $Id: DBGFDisas.cpp 80007 2019-07-26 13:57:38Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/cpum.h>
29#include "DBGFInternal.h"
30#include <VBox/dis.h>
31#include <VBox/err.h>
32#include <VBox/param.h>
33#include <VBox/vmm/vm.h>
34#include <VBox/vmm/uvm.h>
35
36#include <VBox/log.h>
37#include <iprt/assert.h>
38#include <iprt/string.h>
39#include <iprt/alloca.h>
40#include <iprt/ctype.h>
41
42
43/*********************************************************************************************************************************
44* Structures and Typedefs *
45*********************************************************************************************************************************/
46/**
47 * Structure used when disassembling and instructions in DBGF.
48 * This is used so the reader function can get the stuff it needs.
49 */
50typedef struct
51{
52 /** The core structure. */
53 DISCPUSTATE Cpu;
54 /** The cross context VM structure. */
55 PVM pVM;
56 /** The cross context virtual CPU structure. */
57 PVMCPU pVCpu;
58 /** The address space for resolving symbol. */
59 RTDBGAS hDbgAs;
60 /** Pointer to the first byte in the segment. */
61 RTGCUINTPTR GCPtrSegBase;
62 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
63 RTGCUINTPTR GCPtrSegEnd;
64 /** The size of the segment minus 1. */
65 RTGCUINTPTR cbSegLimit;
66 /** The guest paging mode. */
67 PGMMODE enmMode;
68 /** Pointer to the current page - R3 Ptr. */
69 void const *pvPageR3;
70 /** Pointer to the current page - GC Ptr. */
71 RTGCPTR GCPtrPage;
72 /** Pointer to the next instruction (relative to GCPtrSegBase). */
73 RTGCUINTPTR GCPtrNext;
74 /** The lock information that PGMPhysReleasePageMappingLock needs. */
75 PGMPAGEMAPLOCK PageMapLock;
76 /** Whether the PageMapLock is valid or not. */
77 bool fLocked;
78 /** 64 bits mode or not. */
79 bool f64Bits;
80 /** Read original unpatched bytes from the patch manager. */
81 bool fUnpatchedBytes;
82 /** Set when fUnpatchedBytes is active and we encounter patched bytes. */
83 bool fPatchedInstr;
84} DBGFDISASSTATE, *PDBGFDISASSTATE;
85
86
87/*********************************************************************************************************************************
88* Internal Functions *
89*********************************************************************************************************************************/
90static FNDISREADBYTES dbgfR3DisasInstrRead;
91
92
93
94/**
95 * Calls the disassembler with the proper reader functions and such for disa
96 *
97 * @returns VBox status code.
98 * @param pVM The cross context VM structure.
99 * @param pVCpu The cross context virtual CPU structure.
100 * @param pSelInfo The selector info.
101 * @param enmMode The guest paging mode.
102 * @param fFlags DBGF_DISAS_FLAGS_XXX.
103 * @param GCPtr The GC pointer (selector offset).
104 * @param pState The disas CPU state.
105 */
106static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
107 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
108{
109 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
110 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
111 pState->cbSegLimit = pSelInfo->cbLimit;
112 pState->enmMode = enmMode;
113 pState->GCPtrPage = 0;
114 pState->pvPageR3 = NULL;
115 pState->hDbgAs = VM_IS_RAW_MODE_ENABLED(pVM)
116 ? DBGF_AS_RC_AND_GC_GLOBAL
117 : DBGF_AS_GLOBAL;
118 pState->pVM = pVM;
119 pState->pVCpu = pVCpu;
120 pState->fLocked = false;
121 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
122#ifdef VBOX_WITH_RAW_MODE
123 pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
124 pState->fPatchedInstr = false;
125#endif
126
127 DISCPUMODE enmCpuMode;
128 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
129 {
130 default:
131 AssertFailed();
132 RT_FALL_THRU();
133 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
134 enmCpuMode = pState->f64Bits
135 ? DISCPUMODE_64BIT
136 : pSelInfo->u.Raw.Gen.u1DefBig
137 ? DISCPUMODE_32BIT
138 : DISCPUMODE_16BIT;
139 break;
140 case DBGF_DISAS_FLAGS_16BIT_MODE:
141 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
142 enmCpuMode = DISCPUMODE_16BIT;
143 break;
144 case DBGF_DISAS_FLAGS_32BIT_MODE:
145 enmCpuMode = DISCPUMODE_32BIT;
146 break;
147 case DBGF_DISAS_FLAGS_64BIT_MODE:
148 enmCpuMode = DISCPUMODE_64BIT;
149 break;
150 }
151
152 uint32_t cbInstr;
153 int rc = DISInstrWithReader(GCPtr,
154 enmCpuMode,
155 dbgfR3DisasInstrRead,
156 &pState->Cpu,
157 &pState->Cpu,
158 &cbInstr);
159 if (RT_SUCCESS(rc))
160 {
161 pState->GCPtrNext = GCPtr + cbInstr;
162 return VINF_SUCCESS;
163 }
164
165 /* cleanup */
166 if (pState->fLocked)
167 {
168 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
169 pState->fLocked = false;
170 }
171 return rc;
172}
173
174
175#if 0
176/**
177 * Calls the disassembler for disassembling the next instruction.
178 *
179 * @returns VBox status code.
180 * @param pState The disas CPU state.
181 */
182static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
183{
184 uint32_t cbInstr;
185 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
186 if (RT_SUCCESS(rc))
187 {
188 pState->GCPtrNext = GCPtr + cbInstr;
189 return VINF_SUCCESS;
190 }
191 return rc;
192}
193#endif
194
195
196/**
197 * Done with the disassembler state, free associated resources.
198 *
199 * @param pState The disas CPU state ++.
200 */
201static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
202{
203 if (pState->fLocked)
204 {
205 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
206 pState->fLocked = false;
207 }
208}
209
210
211/**
212 * @callback_method_impl{FNDISREADBYTES}
213 *
214 * @remarks The source is relative to the base address indicated by
215 * DBGFDISASSTATE::GCPtrSegBase.
216 */
217static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
218{
219 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
220 for (;;)
221 {
222 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
223
224 /*
225 * Need to update the page translation?
226 */
227 if ( !pState->pvPageR3
228 || (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
229 {
230 int rc = VINF_SUCCESS;
231
232 /* translate the address */
233 pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
234 if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
235 && MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
236 {
237 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
238 if (!pState->pvPageR3)
239 rc = VERR_INVALID_POINTER;
240 }
241 else
242 {
243 if (pState->fLocked)
244 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
245
246 if (pState->enmMode <= PGMMODE_PROTECTED)
247 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
248 else
249 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
250 pState->fLocked = RT_SUCCESS_NP(rc);
251 }
252 if (RT_FAILURE(rc))
253 {
254 pState->pvPageR3 = NULL;
255 return rc;
256 }
257 }
258
259 /*
260 * Check the segment limit.
261 */
262 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
263 return VERR_OUT_OF_SELECTOR_BOUNDS;
264
265 /*
266 * Calc how much we can read, maxing out the read.
267 */
268 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
269 if (!pState->f64Bits)
270 {
271 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
272 if (cb > cbSeg && cbSeg)
273 cb = cbSeg;
274 }
275 if (cb > cbMaxRead)
276 cb = cbMaxRead;
277
278#ifdef VBOX_WITH_RAW_MODE
279 /*
280 * Read original bytes from PATM if asked to do so.
281 */
282 if (pState->fUnpatchedBytes)
283 {
284 size_t cbRead = cb;
285 int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
286 if (RT_SUCCESS(rc))
287 {
288 pState->fPatchedInstr = true;
289 if (cbRead >= cbMinRead)
290 {
291 pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
292 return rc;
293 }
294
295 cbMinRead -= (uint8_t)cbRead;
296 cbMaxRead -= (uint8_t)cbRead;
297 cb -= (uint8_t)cbRead;
298 offInstr += (uint8_t)cbRead;
299 GCPtr += cbRead;
300 if (!cb)
301 continue;
302 }
303 }
304#endif /* VBOX_WITH_RAW_MODE */
305
306 /*
307 * Read and advance,
308 */
309 memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
310 offInstr += (uint8_t)cb;
311 if (cb >= cbMinRead)
312 {
313 pDis->cbCachedInstr = offInstr;
314 return VINF_SUCCESS;
315 }
316 cbMaxRead -= (uint8_t)cb;
317 cbMinRead -= (uint8_t)cb;
318 }
319}
320
321
322/**
323 * @callback_method_impl{FNDISGETSYMBOL}
324 */
325static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
326 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
327{
328 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
329 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
330
331 /*
332 * Address conversion
333 */
334 DBGFADDRESS Addr;
335 int rc;
336 /* Start with CS. */
337 if ( DIS_FMT_SEL_IS_REG(u32Sel)
338 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
339 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
340 rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
341 /* In long mode everything but FS and GS is easy. */
342 else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
343 && DIS_FMT_SEL_IS_REG(u32Sel)
344 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
345 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
346 {
347 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
348 rc = VINF_SUCCESS;
349 }
350 /* Here's a quick hack to catch patch manager SS relative access. */
351 else if ( DIS_FMT_SEL_IS_REG(u32Sel)
352 && DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
353 && pSelInfo->GCPtrBase == 0
354 && pSelInfo->cbLimit >= UINT32_MAX
355#ifdef VBOX_WITH_RAW_MODE
356 && PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr)
357#endif
358 )
359 {
360 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
361 rc = VINF_SUCCESS;
362 }
363 else
364 {
365 /** @todo implement a generic solution here. */
366 rc = VERR_SYMBOL_NOT_FOUND;
367 }
368
369 /*
370 * If we got an address, try resolve it into a symbol.
371 */
372 if (RT_SUCCESS(rc))
373 {
374 RTDBGSYMBOL Sym;
375 RTGCINTPTR off;
376 rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr,
377 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL | RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
378 &off, &Sym, NULL /*phMod*/);
379 if (RT_SUCCESS(rc))
380 {
381 /*
382 * Return the symbol and offset.
383 */
384 size_t cchName = strlen(Sym.szName);
385 if (cchName >= cchBuf)
386 cchName = cchBuf - 1;
387 memcpy(pszBuf, Sym.szName, cchName);
388 pszBuf[cchName] = '\0';
389
390 *poff = off;
391 }
392 }
393 return rc;
394}
395
396
397/**
398 * Disassembles the one instruction according to the specified flags and
399 * address, internal worker executing on the EMT of the specified virtual CPU.
400 *
401 * @returns VBox status code.
402 * @param pVM The cross context VM structure.
403 * @param pVCpu The cross context virtual CPU structure.
404 * @param Sel The code selector. This used to determine the 32/16 bit ness and
405 * calculation of the actual instruction address.
406 * @param pGCPtr Pointer to the variable holding the code address
407 * relative to the base of Sel.
408 * @param fFlags Flags controlling where to start and how to format.
409 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
410 * @param pszOutput Output buffer.
411 * @param cbOutput Size of the output buffer.
412 * @param pcbInstr Where to return the size of the instruction.
413 * @param pDisState Where to store the disassembler state into.
414 */
415static DECLCALLBACK(int)
416dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
417 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr, PDBGFDISSTATE pDisState)
418{
419 VMCPU_ASSERT_EMT(pVCpu);
420 RTGCPTR GCPtr = *pGCPtr;
421 int rc;
422
423 /*
424 * Get the Sel and GCPtr if fFlags requests that.
425 */
426 PCCPUMCTXCORE pCtxCore = NULL;
427 PCCPUMSELREG pSRegCS = NULL;
428 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
429 {
430 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
431 Sel = pCtxCore->cs.Sel;
432 pSRegCS = &pCtxCore->cs;
433 GCPtr = pCtxCore->rip;
434 }
435 else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
436 {
437 fFlags |= DBGF_DISAS_FLAGS_HYPER;
438 pCtxCore = CPUMGetHyperCtxCore(pVCpu);
439 Sel = pCtxCore->cs.Sel;
440 GCPtr = pCtxCore->rip;
441 }
442 /*
443 * Check if the selector matches the guest CS, use the hidden
444 * registers from that if they are valid. Saves time and effort.
445 */
446 else
447 {
448 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
449 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
450 pSRegCS = &pCtxCore->cs;
451 else
452 pCtxCore = NULL;
453 }
454
455 /*
456 * Read the selector info - assume no stale selectors and nasty stuff like that.
457 *
458 * Note! We CANNOT load invalid hidden selector registers since that would
459 * mean that log/debug statements or the debug will influence the
460 * guest state and make things behave differently.
461 */
462 DBGFSELINFO SelInfo;
463 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
464 bool fRealModeAddress = false;
465
466 if ( pSRegCS
467 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
468 {
469 SelInfo.Sel = Sel;
470 SelInfo.SelGate = 0;
471 SelInfo.GCPtrBase = pSRegCS->u64Base;
472 SelInfo.cbLimit = pSRegCS->u32Limit;
473 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
474 ? DBGFSELINFO_FLAGS_LONG_MODE
475 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
476 ? DBGFSELINFO_FLAGS_PROT_MODE
477 : DBGFSELINFO_FLAGS_REAL_MODE;
478
479 SelInfo.u.Raw.au32[0] = 0;
480 SelInfo.u.Raw.au32[1] = 0;
481 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
482 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
483 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
484 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
485 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
486 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
487 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
488 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
489 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
490 }
491 else if (Sel == DBGF_SEL_FLAT)
492 {
493 SelInfo.Sel = Sel;
494 SelInfo.SelGate = 0;
495 SelInfo.GCPtrBase = 0;
496 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
497 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
498 ? DBGFSELINFO_FLAGS_LONG_MODE
499 : enmMode != PGMMODE_REAL
500 ? DBGFSELINFO_FLAGS_PROT_MODE
501 : DBGFSELINFO_FLAGS_REAL_MODE;
502 SelInfo.u.Raw.au32[0] = 0;
503 SelInfo.u.Raw.au32[1] = 0;
504 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
505 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
506
507 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
508 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
509 {
510 /* Assume the current CS defines the execution mode. */
511 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
512 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
513 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
514 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
515 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
516 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
517 }
518 else
519 {
520 pSRegCS = NULL;
521 SelInfo.u.Raw.Gen.u1Present = 1;
522 SelInfo.u.Raw.Gen.u1Granularity = 1;
523 SelInfo.u.Raw.Gen.u1DefBig = 1;
524 SelInfo.u.Raw.Gen.u1DescType = 1;
525 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
526 }
527 }
528 else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
529 && ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
530 || enmMode == PGMMODE_REAL
531 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
532 )
533 )
534 { /* V86 mode or real mode - real mode addressing */
535 SelInfo.Sel = Sel;
536 SelInfo.SelGate = 0;
537 SelInfo.GCPtrBase = Sel * 16;
538 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
539 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
540 SelInfo.u.Raw.au32[0] = 0;
541 SelInfo.u.Raw.au32[1] = 0;
542 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
543 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
544 SelInfo.u.Raw.Gen.u1Present = 1;
545 SelInfo.u.Raw.Gen.u1Granularity = 1;
546 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
547 SelInfo.u.Raw.Gen.u1DescType = 1;
548 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
549 fRealModeAddress = true;
550 }
551 else
552 {
553 if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
554 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
555 else
556 rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
557 if (RT_FAILURE(rc))
558 {
559 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
560 return rc;
561 }
562 }
563
564 /*
565 * Disassemble it.
566 */
567 DBGFDISASSTATE State;
568 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
569 if (RT_FAILURE(rc))
570 {
571 if (State.Cpu.cbCachedInstr)
572 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
573 else
574 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
575 return rc;
576 }
577
578 /*
579 * Format it.
580 */
581 char szBuf[512];
582 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
583 DIS_FMT_FLAGS_RELATIVE_BRANCH,
584 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
585 &SelInfo);
586
587#ifdef VBOX_WITH_RAW_MODE
588 /*
589 * Patched instruction annotations.
590 */
591 char szPatchAnnotations[256];
592 szPatchAnnotations[0] = '\0';
593 if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
594 PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
595#endif
596
597 /*
598 * Print it to the user specified buffer.
599 */
600 size_t cch;
601 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
602 {
603 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
604 cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
605 else if (fRealModeAddress)
606 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
607 else if (Sel == DBGF_SEL_FLAT)
608 {
609 if (enmMode >= PGMMODE_AMD64)
610 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
611 else
612 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
613 }
614 else
615 {
616 if (enmMode >= PGMMODE_AMD64)
617 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
618 else
619 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
620 }
621 }
622 else
623 {
624 uint32_t cbInstr = State.Cpu.cbInstr;
625 uint8_t const *pabInstr = State.Cpu.abInstr;
626 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
627 cch = RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
628 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
629 szBuf);
630 else if (fRealModeAddress)
631 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
632 Sel, (unsigned)GCPtr,
633 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
634 szBuf);
635 else if (Sel == DBGF_SEL_FLAT)
636 {
637 if (enmMode >= PGMMODE_AMD64)
638 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
639 GCPtr,
640 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
641 szBuf);
642 else
643 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
644 (uint32_t)GCPtr,
645 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
646 szBuf);
647 }
648 else
649 {
650 if (enmMode >= PGMMODE_AMD64)
651 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
652 Sel, GCPtr,
653 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
654 szBuf);
655 else
656 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
657 Sel, (uint32_t)GCPtr,
658 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
659 szBuf);
660 }
661 }
662
663#ifdef VBOX_WITH_RAW_MODE
664 if (szPatchAnnotations[0] && cch + 1 < cbOutput)
665 RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
666#endif
667
668 if (pcbInstr)
669 *pcbInstr = State.Cpu.cbInstr;
670
671 if (pDisState)
672 {
673 pDisState->pCurInstr = State.Cpu.pCurInstr;
674 pDisState->cbInstr = State.Cpu.cbInstr;
675 pDisState->Param1 = State.Cpu.Param1;
676 pDisState->Param2 = State.Cpu.Param2;
677 pDisState->Param3 = State.Cpu.Param3;
678 pDisState->Param4 = State.Cpu.Param4;
679 }
680
681 dbgfR3DisasInstrDone(&State);
682 return VINF_SUCCESS;
683}
684
685
686/**
687 * Disassembles the one instruction according to the specified flags and address
688 * returning part of the disassembler state.
689 *
690 * @returns VBox status code.
691 * @param pUVM The user mode VM handle.
692 * @param idCpu The ID of virtual CPU.
693 * @param pAddr The code address.
694 * @param fFlags Flags controlling where to start and how to format.
695 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
696 * @param pszOutput Output buffer. This will always be properly
697 * terminated if @a cbOutput is greater than zero.
698 * @param cbOutput Size of the output buffer.
699 * @param pDisState The disassembler state to fill in.
700 *
701 * @remarks May have to switch to the EMT of the virtual CPU in order to do
702 * address conversion.
703 */
704DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
705 char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
706{
707 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
708 *pszOutput = '\0';
709 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
710 PVM pVM = pUVM->pVM;
711 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
712 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
713 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
714 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
715
716 /*
717 * Optimize the common case where we're called on the EMT of idCpu since
718 * we're using this all the time when logging.
719 */
720 int rc;
721 PVMCPU pVCpu = VMMGetCpu(pVM);
722 if ( pVCpu
723 && pVCpu->idCpu == idCpu)
724 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
725 else
726 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
727 pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
728 return rc;
729}
730
731/**
732 * Disassembles the one instruction according to the specified flags and address.
733 *
734 * @returns VBox status code.
735 * @param pUVM The user mode VM handle.
736 * @param idCpu The ID of virtual CPU.
737 * @param Sel The code selector. This used to determine the 32/16 bit ness and
738 * calculation of the actual instruction address.
739 * @param GCPtr The code address relative to the base of Sel.
740 * @param fFlags Flags controlling where to start and how to format.
741 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
742 * @param pszOutput Output buffer. This will always be properly
743 * terminated if @a cbOutput is greater than zero.
744 * @param cbOutput Size of the output buffer.
745 * @param pcbInstr Where to return the size of the instruction.
746 *
747 * @remarks May have to switch to the EMT of the virtual CPU in order to do
748 * address conversion.
749 */
750VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
751 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
752{
753 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
754 *pszOutput = '\0';
755 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
756 PVM pVM = pUVM->pVM;
757 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
758 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
759 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
760 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
761
762 /*
763 * Optimize the common case where we're called on the EMT of idCpu since
764 * we're using this all the time when logging.
765 */
766 int rc;
767 PVMCPU pVCpu = VMMGetCpu(pVM);
768 if ( pVCpu
769 && pVCpu->idCpu == idCpu)
770 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
771 else
772 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
773 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
774 return rc;
775}
776
777
778/**
779 * Disassembles the current guest context instruction.
780 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
781 *
782 * @returns VBox status code.
783 * @param pVCpu The cross context virtual CPU structure.
784 * @param pszOutput Output buffer. This will always be properly
785 * terminated if @a cbOutput is greater than zero.
786 * @param cbOutput Size of the output buffer.
787 * @thread EMT(pVCpu)
788 */
789VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
790{
791 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
792 *pszOutput = '\0';
793 Assert(VMCPU_IS_EMT(pVCpu));
794
795 RTGCPTR GCPtr = 0;
796 return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
797 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE
798 | DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
799 pszOutput, cbOutput, NULL, NULL);
800}
801
802
803/**
804 * Disassembles the current guest context instruction and writes it to the log.
805 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
806 *
807 * @returns VBox status code.
808 * @param pVCpu The cross context virtual CPU structure.
809 * @param pszPrefix Short prefix string to the disassembly string. (optional)
810 * @thread EMT(pVCpu)
811 */
812VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
813{
814 char szBuf[256];
815 szBuf[0] = '\0';
816 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
817 if (RT_FAILURE(rc))
818 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
819 if (pszPrefix && *pszPrefix)
820 {
821 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
822 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
823 else
824 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
825 }
826 else
827 RTLogPrintf("%s\n", szBuf);
828 return rc;
829}
830
831
832
833/**
834 * Disassembles the specified guest context instruction and writes it to the log.
835 * Addresses will be attempted resolved to symbols.
836 *
837 * @returns VBox status code.
838 * @param pVCpu The cross context virtual CPU structure of the calling
839 * EMT.
840 * @param Sel The code selector. This used to determine the 32/16
841 * bit-ness and calculation of the actual instruction
842 * address.
843 * @param GCPtr The code address relative to the base of Sel.
844 * @param pszPrefix Short prefix string to the disassembly string.
845 * (optional)
846 * @thread EMT(pVCpu)
847 */
848VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
849{
850 Assert(VMCPU_IS_EMT(pVCpu));
851
852 char szBuf[256];
853 RTGCPTR GCPtrTmp = GCPtr;
854 int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
855 &szBuf[0], sizeof(szBuf), NULL, NULL);
856 if (RT_FAILURE(rc))
857 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
858 if (pszPrefix && *pszPrefix)
859 {
860 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
861 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
862 else
863 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
864 }
865 else
866 RTLogPrintf("%s\n", szBuf);
867 return rc;
868}
869
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