VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 74795

Last change on this file since 74795 was 73360, checked in by vboxsync, 6 years ago

VMM,REM,DBGC: Use RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED.
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1/* $Id: DBGFDisas.cpp 73360 2018-07-25 18:51:12Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/cpum.h>
29#ifdef VBOX_WITH_RAW_MODE
30# include <VBox/vmm/patm.h>
31#endif
32#include "DBGFInternal.h"
33#include <VBox/dis.h>
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38
39#include <VBox/log.h>
40#include <iprt/assert.h>
41#include <iprt/string.h>
42#include <iprt/alloca.h>
43#include <iprt/ctype.h>
44
45
46/*********************************************************************************************************************************
47* Structures and Typedefs *
48*********************************************************************************************************************************/
49/**
50 * Structure used when disassembling and instructions in DBGF.
51 * This is used so the reader function can get the stuff it needs.
52 */
53typedef struct
54{
55 /** The core structure. */
56 DISCPUSTATE Cpu;
57 /** The cross context VM structure. */
58 PVM pVM;
59 /** The cross context virtual CPU structure. */
60 PVMCPU pVCpu;
61 /** The address space for resolving symbol. */
62 RTDBGAS hDbgAs;
63 /** Pointer to the first byte in the segment. */
64 RTGCUINTPTR GCPtrSegBase;
65 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
66 RTGCUINTPTR GCPtrSegEnd;
67 /** The size of the segment minus 1. */
68 RTGCUINTPTR cbSegLimit;
69 /** The guest paging mode. */
70 PGMMODE enmMode;
71 /** Pointer to the current page - R3 Ptr. */
72 void const *pvPageR3;
73 /** Pointer to the current page - GC Ptr. */
74 RTGCPTR GCPtrPage;
75 /** Pointer to the next instruction (relative to GCPtrSegBase). */
76 RTGCUINTPTR GCPtrNext;
77 /** The lock information that PGMPhysReleasePageMappingLock needs. */
78 PGMPAGEMAPLOCK PageMapLock;
79 /** Whether the PageMapLock is valid or not. */
80 bool fLocked;
81 /** 64 bits mode or not. */
82 bool f64Bits;
83 /** Read original unpatched bytes from the patch manager. */
84 bool fUnpatchedBytes;
85 /** Set when fUnpatchedBytes is active and we encounter patched bytes. */
86 bool fPatchedInstr;
87} DBGFDISASSTATE, *PDBGFDISASSTATE;
88
89
90/*********************************************************************************************************************************
91* Internal Functions *
92*********************************************************************************************************************************/
93static FNDISREADBYTES dbgfR3DisasInstrRead;
94
95
96
97/**
98 * Calls the disassembler with the proper reader functions and such for disa
99 *
100 * @returns VBox status code.
101 * @param pVM The cross context VM structure.
102 * @param pVCpu The cross context virtual CPU structure.
103 * @param pSelInfo The selector info.
104 * @param enmMode The guest paging mode.
105 * @param fFlags DBGF_DISAS_FLAGS_XXX.
106 * @param GCPtr The GC pointer (selector offset).
107 * @param pState The disas CPU state.
108 */
109static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
110 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
111{
112 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
113 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
114 pState->cbSegLimit = pSelInfo->cbLimit;
115 pState->enmMode = enmMode;
116 pState->GCPtrPage = 0;
117 pState->pvPageR3 = NULL;
118 pState->hDbgAs = VM_IS_RAW_MODE_ENABLED(pVM)
119 ? DBGF_AS_RC_AND_GC_GLOBAL
120 : DBGF_AS_GLOBAL;
121 pState->pVM = pVM;
122 pState->pVCpu = pVCpu;
123 pState->fLocked = false;
124 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
125#ifdef VBOX_WITH_RAW_MODE
126 pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
127 pState->fPatchedInstr = false;
128#endif
129
130 DISCPUMODE enmCpuMode;
131 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
132 {
133 default:
134 AssertFailed();
135 RT_FALL_THRU();
136 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
137 enmCpuMode = pState->f64Bits
138 ? DISCPUMODE_64BIT
139 : pSelInfo->u.Raw.Gen.u1DefBig
140 ? DISCPUMODE_32BIT
141 : DISCPUMODE_16BIT;
142 break;
143 case DBGF_DISAS_FLAGS_16BIT_MODE:
144 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
145 enmCpuMode = DISCPUMODE_16BIT;
146 break;
147 case DBGF_DISAS_FLAGS_32BIT_MODE:
148 enmCpuMode = DISCPUMODE_32BIT;
149 break;
150 case DBGF_DISAS_FLAGS_64BIT_MODE:
151 enmCpuMode = DISCPUMODE_64BIT;
152 break;
153 }
154
155 uint32_t cbInstr;
156 int rc = DISInstrWithReader(GCPtr,
157 enmCpuMode,
158 dbgfR3DisasInstrRead,
159 &pState->Cpu,
160 &pState->Cpu,
161 &cbInstr);
162 if (RT_SUCCESS(rc))
163 {
164 pState->GCPtrNext = GCPtr + cbInstr;
165 return VINF_SUCCESS;
166 }
167
168 /* cleanup */
169 if (pState->fLocked)
170 {
171 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
172 pState->fLocked = false;
173 }
174 return rc;
175}
176
177
178#if 0
179/**
180 * Calls the disassembler for disassembling the next instruction.
181 *
182 * @returns VBox status code.
183 * @param pState The disas CPU state.
184 */
185static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
186{
187 uint32_t cbInstr;
188 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
189 if (RT_SUCCESS(rc))
190 {
191 pState->GCPtrNext = GCPtr + cbInstr;
192 return VINF_SUCCESS;
193 }
194 return rc;
195}
196#endif
197
198
199/**
200 * Done with the disassembler state, free associated resources.
201 *
202 * @param pState The disas CPU state ++.
203 */
204static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
205{
206 if (pState->fLocked)
207 {
208 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
209 pState->fLocked = false;
210 }
211}
212
213
214/**
215 * @callback_method_impl{FNDISREADBYTES}
216 *
217 * @remarks The source is relative to the base address indicated by
218 * DBGFDISASSTATE::GCPtrSegBase.
219 */
220static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
221{
222 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
223 for (;;)
224 {
225 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
226
227 /*
228 * Need to update the page translation?
229 */
230 if ( !pState->pvPageR3
231 || (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
232 {
233 int rc = VINF_SUCCESS;
234
235 /* translate the address */
236 pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
237 if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
238 && MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
239 {
240 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
241 if (!pState->pvPageR3)
242 rc = VERR_INVALID_POINTER;
243 }
244 else
245 {
246 if (pState->fLocked)
247 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
248
249 if (pState->enmMode <= PGMMODE_PROTECTED)
250 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
251 else
252 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
253 pState->fLocked = RT_SUCCESS_NP(rc);
254 }
255 if (RT_FAILURE(rc))
256 {
257 pState->pvPageR3 = NULL;
258 return rc;
259 }
260 }
261
262 /*
263 * Check the segment limit.
264 */
265 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
266 return VERR_OUT_OF_SELECTOR_BOUNDS;
267
268 /*
269 * Calc how much we can read, maxing out the read.
270 */
271 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
272 if (!pState->f64Bits)
273 {
274 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
275 if (cb > cbSeg && cbSeg)
276 cb = cbSeg;
277 }
278 if (cb > cbMaxRead)
279 cb = cbMaxRead;
280
281#ifdef VBOX_WITH_RAW_MODE
282 /*
283 * Read original bytes from PATM if asked to do so.
284 */
285 if (pState->fUnpatchedBytes)
286 {
287 size_t cbRead = cb;
288 int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
289 if (RT_SUCCESS(rc))
290 {
291 pState->fPatchedInstr = true;
292 if (cbRead >= cbMinRead)
293 {
294 pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
295 return rc;
296 }
297
298 cbMinRead -= (uint8_t)cbRead;
299 cbMaxRead -= (uint8_t)cbRead;
300 cb -= (uint8_t)cbRead;
301 offInstr += (uint8_t)cbRead;
302 GCPtr += cbRead;
303 if (!cb)
304 continue;
305 }
306 }
307#endif /* VBOX_WITH_RAW_MODE */
308
309 /*
310 * Read and advance,
311 */
312 memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
313 offInstr += (uint8_t)cb;
314 if (cb >= cbMinRead)
315 {
316 pDis->cbCachedInstr = offInstr;
317 return VINF_SUCCESS;
318 }
319 cbMaxRead -= (uint8_t)cb;
320 cbMinRead -= (uint8_t)cb;
321 }
322}
323
324
325/**
326 * @callback_method_impl{FNDISGETSYMBOL}
327 */
328static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
329 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
330{
331 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
332 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
333
334 /*
335 * Address conversion
336 */
337 DBGFADDRESS Addr;
338 int rc;
339 /* Start with CS. */
340 if ( DIS_FMT_SEL_IS_REG(u32Sel)
341 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
342 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
343 rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
344 /* In long mode everything but FS and GS is easy. */
345 else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
346 && DIS_FMT_SEL_IS_REG(u32Sel)
347 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
348 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
349 {
350 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
351 rc = VINF_SUCCESS;
352 }
353 /* Here's a quick hack to catch patch manager SS relative access. */
354 else if ( DIS_FMT_SEL_IS_REG(u32Sel)
355 && DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
356 && pSelInfo->GCPtrBase == 0
357 && pSelInfo->cbLimit >= UINT32_MAX
358#ifdef VBOX_WITH_RAW_MODE
359 && PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr)
360#endif
361 )
362 {
363 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
364 rc = VINF_SUCCESS;
365 }
366 else
367 {
368 /** @todo implement a generic solution here. */
369 rc = VERR_SYMBOL_NOT_FOUND;
370 }
371
372 /*
373 * If we got an address, try resolve it into a symbol.
374 */
375 if (RT_SUCCESS(rc))
376 {
377 RTDBGSYMBOL Sym;
378 RTGCINTPTR off;
379 rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr,
380 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL | RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
381 &off, &Sym, NULL /*phMod*/);
382 if (RT_SUCCESS(rc))
383 {
384 /*
385 * Return the symbol and offset.
386 */
387 size_t cchName = strlen(Sym.szName);
388 if (cchName >= cchBuf)
389 cchName = cchBuf - 1;
390 memcpy(pszBuf, Sym.szName, cchName);
391 pszBuf[cchName] = '\0';
392
393 *poff = off;
394 }
395 }
396 return rc;
397}
398
399
400/**
401 * Disassembles the one instruction according to the specified flags and
402 * address, internal worker executing on the EMT of the specified virtual CPU.
403 *
404 * @returns VBox status code.
405 * @param pVM The cross context VM structure.
406 * @param pVCpu The cross context virtual CPU structure.
407 * @param Sel The code selector. This used to determine the 32/16 bit ness and
408 * calculation of the actual instruction address.
409 * @param pGCPtr Pointer to the variable holding the code address
410 * relative to the base of Sel.
411 * @param fFlags Flags controlling where to start and how to format.
412 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
413 * @param pszOutput Output buffer.
414 * @param cbOutput Size of the output buffer.
415 * @param pcbInstr Where to return the size of the instruction.
416 * @param pDisState Where to store the disassembler state into.
417 */
418static DECLCALLBACK(int)
419dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
420 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr, PDBGFDISSTATE pDisState)
421{
422 VMCPU_ASSERT_EMT(pVCpu);
423 RTGCPTR GCPtr = *pGCPtr;
424 int rc;
425
426 /*
427 * Get the Sel and GCPtr if fFlags requests that.
428 */
429 PCCPUMCTXCORE pCtxCore = NULL;
430 PCCPUMSELREG pSRegCS = NULL;
431 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
432 {
433 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
434 Sel = pCtxCore->cs.Sel;
435 pSRegCS = &pCtxCore->cs;
436 GCPtr = pCtxCore->rip;
437 }
438 else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
439 {
440 fFlags |= DBGF_DISAS_FLAGS_HYPER;
441 pCtxCore = CPUMGetHyperCtxCore(pVCpu);
442 Sel = pCtxCore->cs.Sel;
443 GCPtr = pCtxCore->rip;
444 }
445 /*
446 * Check if the selector matches the guest CS, use the hidden
447 * registers from that if they are valid. Saves time and effort.
448 */
449 else
450 {
451 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
452 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
453 pSRegCS = &pCtxCore->cs;
454 else
455 pCtxCore = NULL;
456 }
457
458 /*
459 * Read the selector info - assume no stale selectors and nasty stuff like that.
460 *
461 * Note! We CANNOT load invalid hidden selector registers since that would
462 * mean that log/debug statements or the debug will influence the
463 * guest state and make things behave differently.
464 */
465 DBGFSELINFO SelInfo;
466 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
467 bool fRealModeAddress = false;
468
469 if ( pSRegCS
470 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
471 {
472 SelInfo.Sel = Sel;
473 SelInfo.SelGate = 0;
474 SelInfo.GCPtrBase = pSRegCS->u64Base;
475 SelInfo.cbLimit = pSRegCS->u32Limit;
476 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
477 ? DBGFSELINFO_FLAGS_LONG_MODE
478 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
479 ? DBGFSELINFO_FLAGS_PROT_MODE
480 : DBGFSELINFO_FLAGS_REAL_MODE;
481
482 SelInfo.u.Raw.au32[0] = 0;
483 SelInfo.u.Raw.au32[1] = 0;
484 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
485 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
486 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
487 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
488 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
489 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
490 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
491 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
492 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
493 }
494 else if (Sel == DBGF_SEL_FLAT)
495 {
496 SelInfo.Sel = Sel;
497 SelInfo.SelGate = 0;
498 SelInfo.GCPtrBase = 0;
499 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
500 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
501 ? DBGFSELINFO_FLAGS_LONG_MODE
502 : enmMode != PGMMODE_REAL
503 ? DBGFSELINFO_FLAGS_PROT_MODE
504 : DBGFSELINFO_FLAGS_REAL_MODE;
505 SelInfo.u.Raw.au32[0] = 0;
506 SelInfo.u.Raw.au32[1] = 0;
507 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
508 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
509
510 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
511 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
512 {
513 /* Assume the current CS defines the execution mode. */
514 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
515 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
516 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
517 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
518 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
519 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
520 }
521 else
522 {
523 pSRegCS = NULL;
524 SelInfo.u.Raw.Gen.u1Present = 1;
525 SelInfo.u.Raw.Gen.u1Granularity = 1;
526 SelInfo.u.Raw.Gen.u1DefBig = 1;
527 SelInfo.u.Raw.Gen.u1DescType = 1;
528 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
529 }
530 }
531 else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
532 && ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
533 || enmMode == PGMMODE_REAL
534 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
535 )
536 )
537 { /* V86 mode or real mode - real mode addressing */
538 SelInfo.Sel = Sel;
539 SelInfo.SelGate = 0;
540 SelInfo.GCPtrBase = Sel * 16;
541 SelInfo.cbLimit = ~(RTGCUINTPTR)0;
542 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
543 SelInfo.u.Raw.au32[0] = 0;
544 SelInfo.u.Raw.au32[1] = 0;
545 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
546 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
547 SelInfo.u.Raw.Gen.u1Present = 1;
548 SelInfo.u.Raw.Gen.u1Granularity = 1;
549 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
550 SelInfo.u.Raw.Gen.u1DescType = 1;
551 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
552 fRealModeAddress = true;
553 }
554 else
555 {
556 if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
557 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
558 else
559 rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
560 if (RT_FAILURE(rc))
561 {
562 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
563 return rc;
564 }
565 }
566
567 /*
568 * Disassemble it.
569 */
570 DBGFDISASSTATE State;
571 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
572 if (RT_FAILURE(rc))
573 {
574 if (State.Cpu.cbCachedInstr)
575 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
576 else
577 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
578 return rc;
579 }
580
581 /*
582 * Format it.
583 */
584 char szBuf[512];
585 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
586 DIS_FMT_FLAGS_RELATIVE_BRANCH,
587 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
588 &SelInfo);
589
590#ifdef VBOX_WITH_RAW_MODE
591 /*
592 * Patched instruction annotations.
593 */
594 char szPatchAnnotations[256];
595 szPatchAnnotations[0] = '\0';
596 if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
597 PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
598#endif
599
600 /*
601 * Print it to the user specified buffer.
602 */
603 size_t cch;
604 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
605 {
606 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
607 cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
608 else if (fRealModeAddress)
609 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
610 else if (Sel == DBGF_SEL_FLAT)
611 {
612 if (enmMode >= PGMMODE_AMD64)
613 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
614 else
615 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
616 }
617 else
618 {
619 if (enmMode >= PGMMODE_AMD64)
620 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
621 else
622 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
623 }
624 }
625 else
626 {
627 uint32_t cbInstr = State.Cpu.cbInstr;
628 uint8_t const *pabInstr = State.Cpu.abInstr;
629 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
630 cch = RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
631 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
632 szBuf);
633 else if (fRealModeAddress)
634 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
635 Sel, (unsigned)GCPtr,
636 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
637 szBuf);
638 else if (Sel == DBGF_SEL_FLAT)
639 {
640 if (enmMode >= PGMMODE_AMD64)
641 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
642 GCPtr,
643 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
644 szBuf);
645 else
646 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
647 (uint32_t)GCPtr,
648 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
649 szBuf);
650 }
651 else
652 {
653 if (enmMode >= PGMMODE_AMD64)
654 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
655 Sel, GCPtr,
656 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
657 szBuf);
658 else
659 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
660 Sel, (uint32_t)GCPtr,
661 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
662 szBuf);
663 }
664 }
665
666#ifdef VBOX_WITH_RAW_MODE
667 if (szPatchAnnotations[0] && cch + 1 < cbOutput)
668 RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
669#endif
670
671 if (pcbInstr)
672 *pcbInstr = State.Cpu.cbInstr;
673
674 if (pDisState)
675 {
676 pDisState->pCurInstr = State.Cpu.pCurInstr;
677 pDisState->cbInstr = State.Cpu.cbInstr;
678 pDisState->Param1 = State.Cpu.Param1;
679 pDisState->Param2 = State.Cpu.Param2;
680 pDisState->Param3 = State.Cpu.Param3;
681 pDisState->Param4 = State.Cpu.Param4;
682 }
683
684 dbgfR3DisasInstrDone(&State);
685 return VINF_SUCCESS;
686}
687
688
689/**
690 * Disassembles the one instruction according to the specified flags and address
691 * returning part of the disassembler state.
692 *
693 * @returns VBox status code.
694 * @param pUVM The user mode VM handle.
695 * @param idCpu The ID of virtual CPU.
696 * @param pAddr The code address.
697 * @param fFlags Flags controlling where to start and how to format.
698 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
699 * @param pszOutput Output buffer. This will always be properly
700 * terminated if @a cbOutput is greater than zero.
701 * @param cbOutput Size of the output buffer.
702 * @param pDisState The disassembler state to fill in.
703 *
704 * @remarks May have to switch to the EMT of the virtual CPU in order to do
705 * address conversion.
706 */
707DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
708 char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
709{
710 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
711 *pszOutput = '\0';
712 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
713 PVM pVM = pUVM->pVM;
714 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
715 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
716 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
717 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
718
719 /*
720 * Optimize the common case where we're called on the EMT of idCpu since
721 * we're using this all the time when logging.
722 */
723 int rc;
724 PVMCPU pVCpu = VMMGetCpu(pVM);
725 if ( pVCpu
726 && pVCpu->idCpu == idCpu)
727 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
728 else
729 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
730 pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
731 return rc;
732}
733
734/**
735 * Disassembles the one instruction according to the specified flags and address.
736 *
737 * @returns VBox status code.
738 * @param pUVM The user mode VM handle.
739 * @param idCpu The ID of virtual CPU.
740 * @param Sel The code selector. This used to determine the 32/16 bit ness and
741 * calculation of the actual instruction address.
742 * @param GCPtr The code address relative to the base of Sel.
743 * @param fFlags Flags controlling where to start and how to format.
744 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
745 * @param pszOutput Output buffer. This will always be properly
746 * terminated if @a cbOutput is greater than zero.
747 * @param cbOutput Size of the output buffer.
748 * @param pcbInstr Where to return the size of the instruction.
749 *
750 * @remarks May have to switch to the EMT of the virtual CPU in order to do
751 * address conversion.
752 */
753VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
754 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
755{
756 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
757 *pszOutput = '\0';
758 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
759 PVM pVM = pUVM->pVM;
760 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
761 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
762 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
763 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
764
765 /*
766 * Optimize the common case where we're called on the EMT of idCpu since
767 * we're using this all the time when logging.
768 */
769 int rc;
770 PVMCPU pVCpu = VMMGetCpu(pVM);
771 if ( pVCpu
772 && pVCpu->idCpu == idCpu)
773 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
774 else
775 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
776 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
777 return rc;
778}
779
780
781/**
782 * Disassembles the current guest context instruction.
783 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
784 *
785 * @returns VBox status code.
786 * @param pVCpu The cross context virtual CPU structure.
787 * @param pszOutput Output buffer. This will always be properly
788 * terminated if @a cbOutput is greater than zero.
789 * @param cbOutput Size of the output buffer.
790 * @thread EMT(pVCpu)
791 */
792VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
793{
794 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
795 *pszOutput = '\0';
796 Assert(VMCPU_IS_EMT(pVCpu));
797
798 RTGCPTR GCPtr = 0;
799 return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
800 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE
801 | DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
802 pszOutput, cbOutput, NULL, NULL);
803}
804
805
806/**
807 * Disassembles the current guest context instruction and writes it to the log.
808 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
809 *
810 * @returns VBox status code.
811 * @param pVCpu The cross context virtual CPU structure.
812 * @param pszPrefix Short prefix string to the disassembly string. (optional)
813 * @thread EMT(pVCpu)
814 */
815VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
816{
817 char szBuf[256];
818 szBuf[0] = '\0';
819 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
820 if (RT_FAILURE(rc))
821 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
822 if (pszPrefix && *pszPrefix)
823 {
824 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
825 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
826 else
827 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
828 }
829 else
830 RTLogPrintf("%s\n", szBuf);
831 return rc;
832}
833
834
835
836/**
837 * Disassembles the specified guest context instruction and writes it to the log.
838 * Addresses will be attempted resolved to symbols.
839 *
840 * @returns VBox status code.
841 * @param pVCpu The cross context virtual CPU structure of the calling
842 * EMT.
843 * @param Sel The code selector. This used to determine the 32/16
844 * bit-ness and calculation of the actual instruction
845 * address.
846 * @param GCPtr The code address relative to the base of Sel.
847 * @param pszPrefix Short prefix string to the disassembly string.
848 * (optional)
849 * @thread EMT(pVCpu)
850 */
851VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
852{
853 Assert(VMCPU_IS_EMT(pVCpu));
854
855 char szBuf[256];
856 RTGCPTR GCPtrTmp = GCPtr;
857 int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
858 &szBuf[0], sizeof(szBuf), NULL, NULL);
859 if (RT_FAILURE(rc))
860 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
861 if (pszPrefix && *pszPrefix)
862 {
863 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
864 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
865 else
866 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
867 }
868 else
869 RTLogPrintf("%s\n", szBuf);
870 return rc;
871}
872
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