VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 84044

Last change on this file since 84044 was 83092, checked in by vboxsync, 4 years ago

VMM/CPUM: bugref:9630: Ignore writes to MSR_IA32_TSX_CTRL.
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1/* $Id: CPUMR3Db.cpp 83092 2020-02-17 09:35:20Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include "CPUMInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/vmm/mm.h>
27
28#include <VBox/err.h>
29#include <iprt/asm-amd64-x86.h>
30#include <iprt/mem.h>
31#include <iprt/string.h>
32
33
34/*********************************************************************************************************************************
35* Structures and Typedefs *
36*********************************************************************************************************************************/
37typedef struct CPUMDBENTRY
38{
39 /** The CPU name. */
40 const char *pszName;
41 /** The full CPU name. */
42 const char *pszFullName;
43 /** The CPU vendor (CPUMCPUVENDOR). */
44 uint8_t enmVendor;
45 /** The CPU family. */
46 uint8_t uFamily;
47 /** The CPU model. */
48 uint8_t uModel;
49 /** The CPU stepping. */
50 uint8_t uStepping;
51 /** The microarchitecture. */
52 CPUMMICROARCH enmMicroarch;
53 /** Scalable bus frequency used for reporting other frequencies. */
54 uint64_t uScalableBusFreq;
55 /** Flags - CPUDB_F_XXX. */
56 uint32_t fFlags;
57 /** The maximum physical address with of the CPU. This should correspond to
58 * the value in CPUID leaf 0x80000008 when present. */
59 uint8_t cMaxPhysAddrWidth;
60 /** The MXCSR mask. */
61 uint32_t fMxCsrMask;
62 /** Pointer to an array of CPUID leaves. */
63 PCCPUMCPUIDLEAF paCpuIdLeaves;
64 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65 uint32_t cCpuIdLeaves;
66 /** The method used to deal with unknown CPUID leaves. */
67 CPUMUNKNOWNCPUID enmUnknownCpuId;
68 /** The default unknown CPUID value. */
69 CPUMCPUID DefUnknownCpuId;
70
71 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72 * the RDMSR and WRMSR instructions. */
73 uint32_t fMsrMask;
74
75 /** The number of ranges in the table pointed to b paMsrRanges. */
76 uint32_t cMsrRanges;
77 /** MSR ranges for this CPU. */
78 PCCPUMMSRRANGE paMsrRanges;
79} CPUMDBENTRY;
80
81
82/*********************************************************************************************************************************
83* Defined Constants And Macros *
84*********************************************************************************************************************************/
85/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86 * @{ */
87/** Should execute all in IEM.
88 * @todo Implement this - currently done in Main... */
89#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90/** @} */
91
92
93/** @def NULL_ALONE
94 * For eliminating an unnecessary data dependency in standalone builds (for
95 * VBoxSVC). */
96/** @def ZERO_ALONE
97 * For eliminating an unnecessary data size dependency in standalone builds (for
98 * VBoxSVC). */
99#ifndef CPUM_DB_STANDALONE
100# define NULL_ALONE(a_aTable) a_aTable
101# define ZERO_ALONE(a_cTable) a_cTable
102#else
103# define NULL_ALONE(a_aTable) NULL
104# define ZERO_ALONE(a_cTable) 0
105#endif
106
107
108/** @name Short macros for the MSR range entries.
109 *
110 * These are rather cryptic, but this is to reduce the attack on the right
111 * margin.
112 *
113 * @{ */
114/** Alias one MSR onto another (a_uTarget). */
115#define MAL(a_uMsr, a_szName, a_uTarget) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117/** Functions handles everything. */
118#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120/** Functions handles everything, with GP mask. */
121#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123/** Function handlers, read-only. */
124#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126/** Function handlers, ignore all writes. */
127#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129/** Function handlers, with value. */
130#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132/** Function handlers, with write ignore mask. */
133#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135/** Function handlers, extended version. */
136#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138/** Function handlers, with CPUMCPU storage variable. */
139#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** Read-only fixed value. */
147#define MVO(a_uMsr, a_szName, a_uValue) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149/** Read-only fixed value, ignores all writes. */
150#define MVI(a_uMsr, a_szName, a_uValue) \
151 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152/** Read fixed value, ignore writes outside GP mask. */
153#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155/** Read fixed value, extended version with both GP and ignore masks. */
156#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158/** The short form, no CPUM backing. */
159#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163/** Range: Functions handles everything. */
164#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166/** Range: Read fixed value, read-only. */
167#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169/** Range: Read fixed value, ignore writes. */
170#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172/** Range: The short form, no CPUM backing. */
173#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177/** Internal form used by the macros. */
178#ifdef VBOX_WITH_STATISTICS
179# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181 { 0 }, { 0 }, { 0 }, { 0 } }
182#else
183# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185#endif
186/** @} */
187
188#ifndef CPUM_DB_STANDALONE
189
190#include "cpus/Intel_Core_i7_6700K.h"
191#include "cpus/Intel_Core_i7_5600U.h"
192#include "cpus/Intel_Core_i7_3960X.h"
193#include "cpus/Intel_Core_i5_3570.h"
194#include "cpus/Intel_Core_i7_2635QM.h"
195#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200#include "cpus/Intel_Pentium_4_3_00GHz.h"
201#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202#include "cpus/Intel_Atom_330_1_60GHz.h"
203#include "cpus/Intel_80486.h"
204#include "cpus/Intel_80386.h"
205#include "cpus/Intel_80286.h"
206#include "cpus/Intel_80186.h"
207#include "cpus/Intel_8086.h"
208
209#include "cpus/AMD_FX_8150_Eight_Core.h"
210#include "cpus/AMD_Phenom_II_X6_1100T.h"
211#include "cpus/Quad_Core_AMD_Opteron_2384.h"
212#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
213#include "cpus/AMD_Athlon_64_3200.h"
214
215#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
216
217#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
218
219#include "cpus/Hygon_C86_7185_32_core.h"
220
221
222/**
223 * The database entries.
224 *
225 * 1. The first entry is special. It is the fallback for unknown
226 * processors. Thus, it better be pretty representative.
227 *
228 * 2. The first entry for a CPU vendor is likewise important as it is
229 * the default entry for that vendor.
230 *
231 * Generally we put the most recent CPUs first, since these tend to have the
232 * most complicated and backwards compatible list of MSRs.
233 */
234static CPUMDBENTRY const * const g_apCpumDbEntries[] =
235{
236#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
237 &g_Entry_Intel_Core_i7_6700K,
238#endif
239#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
240 &g_Entry_Intel_Core_i7_5600U,
241#endif
242#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
243 &g_Entry_Intel_Core_i5_3570,
244#endif
245#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
246 &g_Entry_Intel_Core_i7_3960X,
247#endif
248#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
249 &g_Entry_Intel_Core_i7_2635QM,
250#endif
251#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
252 &g_Entry_Intel_Pentium_N3530_2_16GHz,
253#endif
254#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
255 &g_Entry_Intel_Atom_330_1_60GHz,
256#endif
257#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
258 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
259#endif
260#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
261 &g_Entry_Intel_Xeon_X5482_3_20GHz,
262#endif
263#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
264 &g_Entry_Intel_Core2_X6800_2_93GHz,
265#endif
266#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
267 &g_Entry_Intel_Core2_T7600_2_33GHz,
268#endif
269#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
270 &g_Entry_Intel_Core_Duo_T2600_2_16GHz,
271#endif
272#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
273 &g_Entry_Intel_Pentium_4_3_00GHz,
274#endif
275#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
276 &g_Entry_Intel_Pentium_4_3_00GHz,
277#endif
278/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
279#ifdef VBOX_CPUDB_Intel_80486_h
280 &g_Entry_Intel_80486,
281#endif
282#ifdef VBOX_CPUDB_Intel_80386_h
283 &g_Entry_Intel_80386,
284#endif
285#ifdef VBOX_CPUDB_Intel_80286_h
286 &g_Entry_Intel_80286,
287#endif
288#ifdef VBOX_CPUDB_Intel_80186_h
289 &g_Entry_Intel_80186,
290#endif
291#ifdef VBOX_CPUDB_Intel_8086_h
292 &g_Entry_Intel_8086,
293#endif
294
295#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
296 &g_Entry_AMD_FX_8150_Eight_Core,
297#endif
298#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
299 &g_Entry_AMD_Phenom_II_X6_1100T,
300#endif
301#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
302 &g_Entry_Quad_Core_AMD_Opteron_2384,
303#endif
304#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
305 &g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
306#endif
307#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
308 &g_Entry_AMD_Athlon_64_3200,
309#endif
310
311#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
312 &g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
313#endif
314
315#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
316 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
317#endif
318
319#ifdef VBOX_CPUDB_NEC_V20_h
320 &g_Entry_NEC_V20,
321#endif
322
323#ifdef VBOX_CPUDB_Hygon_C86_7185_32_core_h
324 &g_Entry_Hygon_C86_7185_32_core,
325#endif
326};
327
328
329
330/**
331 * Binary search used by cpumR3MsrRangesInsert and has some special properties
332 * wrt to mismatches.
333 *
334 * @returns Insert location.
335 * @param paMsrRanges The MSR ranges to search.
336 * @param cMsrRanges The number of MSR ranges.
337 * @param uMsr What to search for.
338 */
339static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
340{
341 if (!cMsrRanges)
342 return 0;
343
344 uint32_t iStart = 0;
345 uint32_t iLast = cMsrRanges - 1;
346 for (;;)
347 {
348 uint32_t i = iStart + (iLast - iStart + 1) / 2;
349 if ( uMsr >= paMsrRanges[i].uFirst
350 && uMsr <= paMsrRanges[i].uLast)
351 return i;
352 if (uMsr < paMsrRanges[i].uFirst)
353 {
354 if (i <= iStart)
355 return i;
356 iLast = i - 1;
357 }
358 else
359 {
360 if (i >= iLast)
361 {
362 if (i < cMsrRanges)
363 i++;
364 return i;
365 }
366 iStart = i + 1;
367 }
368 }
369}
370
371
372/**
373 * Ensures that there is space for at least @a cNewRanges in the table,
374 * reallocating the table if necessary.
375 *
376 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
377 * @a *ppaMsrRanges is freed and set to NULL.
378 * @param pVM The cross context VM structure. If NULL,
379 * use the process heap, otherwise the VM's hyper heap.
380 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
381 * @param cMsrRanges The current number of ranges.
382 * @param cNewRanges The number of ranges to be added.
383 */
384static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
385{
386 uint32_t cMsrRangesAllocated;
387 if (!pVM)
388 cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
389 else
390 {
391 /*
392 * We're using the hyper heap now, but when the range array was copied over to it from
393 * the host-context heap, we only copy the exact size and not the ensured size.
394 * See @bugref{7270}.
395 */
396 cMsrRangesAllocated = cMsrRanges;
397 }
398 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
399 {
400 void *pvNew;
401 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
402 if (pVM)
403 {
404 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
405 Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
406
407 size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
408 size_t cbNew = cNew * sizeof(**ppaMsrRanges);
409 int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
410 if (RT_FAILURE(rc))
411 {
412 *ppaMsrRanges = NULL;
413 pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
414 LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
415 return NULL;
416 }
417 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
418 }
419 else
420 {
421 pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
422 if (!pvNew)
423 {
424 RTMemFree(*ppaMsrRanges);
425 *ppaMsrRanges = NULL;
426 return NULL;
427 }
428 }
429 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
430 }
431
432 if (pVM)
433 {
434 /* Update the R0 pointer. */
435 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
436 pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
437 }
438
439 return *ppaMsrRanges;
440}
441
442
443/**
444 * Inserts a new MSR range in into an sorted MSR range array.
445 *
446 * If the new MSR range overlaps existing ranges, the existing ones will be
447 * adjusted/removed to fit in the new one.
448 *
449 * @returns VBox status code.
450 * @retval VINF_SUCCESS
451 * @retval VERR_NO_MEMORY
452 *
453 * @param pVM The cross context VM structure. If NULL,
454 * use the process heap, otherwise the VM's hyper heap.
455 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
456 * Must be NULL if using the hyper heap.
457 * @param pcMsrRanges The variable holding number of ranges. Must be NULL
458 * if using the hyper heap.
459 * @param pNewRange The new range.
460 */
461int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
462{
463 Assert(pNewRange->uLast >= pNewRange->uFirst);
464 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
465 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
466
467 /*
468 * Validate and use the VM's MSR ranges array if we are using the hyper heap.
469 */
470 if (pVM)
471 {
472 AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
473 AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
474
475 ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
476 pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
477 }
478 else
479 {
480 AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
481 AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
482 }
483
484 uint32_t cMsrRanges = *pcMsrRanges;
485 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
486
487 /*
488 * Optimize the linear insertion case where we add new entries at the end.
489 */
490 if ( cMsrRanges > 0
491 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
492 {
493 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
494 if (!paMsrRanges)
495 return VERR_NO_MEMORY;
496 paMsrRanges[cMsrRanges] = *pNewRange;
497 *pcMsrRanges += 1;
498 }
499 else
500 {
501 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
502 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
503 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
504
505 /*
506 * Adding an entirely new entry?
507 */
508 if ( i >= cMsrRanges
509 || pNewRange->uLast < paMsrRanges[i].uFirst)
510 {
511 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
512 if (!paMsrRanges)
513 return VERR_NO_MEMORY;
514 if (i < cMsrRanges)
515 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
516 paMsrRanges[i] = *pNewRange;
517 *pcMsrRanges += 1;
518 }
519 /*
520 * Replace existing entry?
521 */
522 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
523 && pNewRange->uLast == paMsrRanges[i].uLast)
524 paMsrRanges[i] = *pNewRange;
525 /*
526 * Splitting an existing entry?
527 */
528 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
529 && pNewRange->uLast < paMsrRanges[i].uLast)
530 {
531 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
532 if (!paMsrRanges)
533 return VERR_NO_MEMORY;
534 if (i < cMsrRanges)
535 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
536 paMsrRanges[i + 1] = *pNewRange;
537 paMsrRanges[i + 2] = paMsrRanges[i];
538 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
539 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
540 *pcMsrRanges += 2;
541 }
542 /*
543 * Complicated scenarios that can affect more than one range.
544 *
545 * The current code does not optimize memmove calls when replacing
546 * one or more existing ranges, because it's tedious to deal with and
547 * not expected to be a frequent usage scenario.
548 */
549 else
550 {
551 /* Adjust start of first match? */
552 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
553 && pNewRange->uLast < paMsrRanges[i].uLast)
554 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
555 else
556 {
557 /* Adjust end of first match? */
558 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
559 {
560 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
561 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
562 i++;
563 }
564 /* Replace the whole first match (lazy bird). */
565 else
566 {
567 if (i + 1 < cMsrRanges)
568 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
569 cMsrRanges = *pcMsrRanges -= 1;
570 }
571
572 /* Do the new range affect more ranges? */
573 while ( i < cMsrRanges
574 && pNewRange->uLast >= paMsrRanges[i].uFirst)
575 {
576 if (pNewRange->uLast < paMsrRanges[i].uLast)
577 {
578 /* Adjust the start of it, then we're done. */
579 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
580 break;
581 }
582
583 /* Remove it entirely. */
584 if (i + 1 < cMsrRanges)
585 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
586 cMsrRanges = *pcMsrRanges -= 1;
587 }
588 }
589
590 /* Now, perform a normal insertion. */
591 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
592 if (!paMsrRanges)
593 return VERR_NO_MEMORY;
594 if (i < cMsrRanges)
595 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
596 paMsrRanges[i] = *pNewRange;
597 *pcMsrRanges += 1;
598 }
599 }
600
601 return VINF_SUCCESS;
602}
603
604
605/**
606 * Reconciles CPUID info with MSRs (selected ones).
607 *
608 * @returns VBox status code.
609 * @param pVM The cross context VM structure.
610 */
611int cpumR3MsrReconcileWithCpuId(PVM pVM)
612{
613 PCCPUMMSRRANGE papToAdd[10];
614 uint32_t cToAdd = 0;
615
616 /*
617 * The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
618 */
619 if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
620 {
621 static CPUMMSRRANGE const s_FlushCmd =
622 {
623 /*.uFirst =*/ MSR_IA32_FLUSH_CMD,
624 /*.uLast =*/ MSR_IA32_FLUSH_CMD,
625 /*.enmRdFn =*/ kCpumMsrRdFn_WriteOnly,
626 /*.enmWrFn =*/ kCpumMsrWrFn_Ia32FlushCmd,
627 /*.offCpumCpu =*/ UINT16_MAX,
628 /*.fReserved =*/ 0,
629 /*.uValue =*/ 0,
630 /*.fWrIgnMask =*/ 0,
631 /*.fWrGpMask =*/ ~MSR_IA32_FLUSH_CMD_F_L1D,
632 /*.szName = */ "IA32_FLUSH_CMD"
633 };
634 papToAdd[cToAdd++] = &s_FlushCmd;
635 }
636
637 /*
638 * The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
639 * documented in relation to such.
640 */
641 if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
642 {
643 static CPUMMSRRANGE const s_ArchCaps =
644 {
645 /*.uFirst =*/ MSR_IA32_ARCH_CAPABILITIES,
646 /*.uLast =*/ MSR_IA32_ARCH_CAPABILITIES,
647 /*.enmRdFn =*/ kCpumMsrRdFn_Ia32ArchCapabilities,
648 /*.enmWrFn =*/ kCpumMsrWrFn_ReadOnly,
649 /*.offCpumCpu =*/ UINT16_MAX,
650 /*.fReserved =*/ 0,
651 /*.uValue =*/ 0,
652 /*.fWrIgnMask =*/ 0,
653 /*.fWrGpMask =*/ UINT64_MAX,
654 /*.szName = */ "IA32_ARCH_CAPABILITIES"
655 };
656 papToAdd[cToAdd++] = &s_ArchCaps;
657 }
658
659 /*
660 * Do the adding.
661 */
662 for (uint32_t i = 0; i < cToAdd; i++)
663 {
664 PCCPUMMSRRANGE pRange = papToAdd[i];
665 LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
666 int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
667 pRange);
668 if (RT_FAILURE(rc))
669 return rc;
670 }
671 return VINF_SUCCESS;
672}
673
674
675/**
676 * Worker for cpumR3MsrApplyFudge that applies one table.
677 *
678 * @returns VBox status code.
679 * @param pVM The cross context VM structure.
680 * @param paRanges Array of MSRs to fudge.
681 * @param cRanges Number of MSRs in the array.
682 */
683static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
684{
685 for (uint32_t i = 0; i < cRanges; i++)
686 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
687 {
688 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
689 int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
690 &paRanges[i]);
691 if (RT_FAILURE(rc))
692 return rc;
693 }
694 return VINF_SUCCESS;
695}
696
697
698/**
699 * Fudges the MSRs that guest are known to access in some odd cases.
700 *
701 * A typical example is a VM that has been moved between different hosts where
702 * for instance the cpu vendor differs.
703 *
704 * Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
705 * Atom Silvermont), where features reported thru CPUID aren't present in the
706 * MSRs (e.g. AMD64_TSC_AUX).
707 *
708 *
709 * @returns VBox status code.
710 * @param pVM The cross context VM structure.
711 */
712int cpumR3MsrApplyFudge(PVM pVM)
713{
714 /*
715 * Basic.
716 */
717 static CPUMMSRRANGE const s_aFudgeMsrs[] =
718 {
719 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
720 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
721 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
722 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
723 MVI(0x0000008b, "BIOS_SIGN", 0),
724 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
725 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
726 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
727 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
728 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
729 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
730 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
731 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
732 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
733 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
734 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
735 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
736 };
737 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
738 AssertLogRelRCReturn(rc, rc);
739
740 /*
741 * XP might mistake opterons and other newer CPUs for P4s.
742 */
743 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
744 {
745 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
746 {
747 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
748 };
749 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
750 AssertLogRelRCReturn(rc, rc);
751 }
752
753 if (pVM->cpum.s.GuestFeatures.fRdTscP)
754 {
755 static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
756 {
757 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
758 };
759 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
760 AssertLogRelRCReturn(rc, rc);
761 }
762
763 /*
764 * Windows 10 incorrectly writes to MSR_IA32_TSX_CTRL without checking
765 * CPUID.ARCH_CAP(EAX=7h,ECX=0):EDX[bit 29] or the MSR feature bits in
766 * MSR_IA32_ARCH_CAPABILITIES[bit 7], see @bugref{9630}.
767 * Ignore writes to this MSR and return 0 on reads.
768 */
769 if (pVM->cpum.s.GuestFeatures.fArchCap)
770 {
771 static CPUMMSRRANGE const s_aTsxCtrl[] =
772 {
773 MVI(MSR_IA32_TSX_CTRL, "IA32_TSX_CTRL", 0),
774 };
775 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aTsxCtrl[0], RT_ELEMENTS(s_aTsxCtrl));
776 AssertLogRelRCReturn(rc, rc);
777 }
778
779 return rc;
780}
781
782
783/**
784 * Do we consider @a enmConsider a better match for @a enmTarget than
785 * @a enmFound?
786 *
787 * Only called when @a enmConsider isn't exactly what we're looking for.
788 *
789 * @returns true/false.
790 * @param enmConsider The new microarch to consider.
791 * @param enmTarget The target microarch.
792 * @param enmFound The best microarch match we've found thus far.
793 */
794DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
795{
796 Assert(enmConsider != enmTarget);
797
798 /*
799 * If we've got an march match, don't bother with enmConsider.
800 */
801 if (enmFound == enmTarget)
802 return false;
803
804 /*
805 * Found is below: Pick 'consider' if it's closer to the target or above it.
806 */
807 if (enmFound < enmTarget)
808 return enmConsider > enmFound;
809
810 /*
811 * Found is above: Pick 'consider' if it's also above (paranoia: or equal)
812 * and but closer to the target.
813 */
814 return enmConsider >= enmTarget && enmConsider < enmFound;
815}
816
817
818/**
819 * Do we consider @a enmConsider a better match for @a enmTarget than
820 * @a enmFound?
821 *
822 * Only called for intel family 06h CPUs.
823 *
824 * @returns true/false.
825 * @param enmConsider The new microarch to consider.
826 * @param enmTarget The target microarch.
827 * @param enmFound The best microarch match we've found thus far.
828 */
829static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
830{
831 /* Check intel family 06h claims. */
832 AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
833 false);
834 AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
835 false);
836
837 /* Put matches out of the way. */
838 if (enmConsider == enmTarget)
839 return true;
840 if (enmFound == enmTarget)
841 return false;
842
843 /* If found isn't a family 06h march, whatever we're considering must be a better choice. */
844 if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
845 || enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
846 return true;
847
848 /*
849 * The family 06h stuff is split into three categories:
850 * - Common P6 heritage
851 * - Core
852 * - Atom
853 *
854 * Determin which of the three arguments are Atom marchs, because that's
855 * all we need to make the right choice.
856 */
857 bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
858 bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
859 bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
860
861 /*
862 * Want atom:
863 */
864 if (fTargetAtom)
865 {
866 /* Pick the atom if we've got one of each.*/
867 if (fConsiderAtom != fFoundAtom)
868 return fConsiderAtom;
869 /* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
870 Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
871 if (!fConsiderAtom)
872 {
873 if (enmConsider > enmFound)
874 return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
875 return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
876 }
877 /* else: same category, default comparison rules. */
878 Assert(fConsiderAtom && fFoundAtom);
879 }
880 /*
881 * Want non-atom:
882 */
883 /* Pick the non-atom if we've got one of each. */
884 else if (fConsiderAtom != fFoundAtom)
885 return fFoundAtom;
886 /* If we've only got atoms under consideration, pick the older one just to pick something. */
887 else if (fConsiderAtom)
888 return enmConsider < enmFound;
889 else
890 Assert(!fConsiderAtom && !fFoundAtom);
891
892 /*
893 * Same basic category. Do same compare as caller.
894 */
895 return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
896}
897
898
899int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
900{
901 CPUMDBENTRY const *pEntry = NULL;
902 int rc;
903
904 if (!strcmp(pszName, "host"))
905 {
906 /*
907 * Create a CPU database entry for the host CPU. This means getting
908 * the CPUID bits from the real CPU and grabbing the closest matching
909 * database entry for MSRs.
910 */
911 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
912 if (RT_FAILURE(rc))
913 return rc;
914 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
915 if (RT_FAILURE(rc))
916 return rc;
917 pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
918
919 /* Lookup database entry for MSRs. */
920 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
921 pInfo->paCpuIdLeavesR3[0].uEbx,
922 pInfo->paCpuIdLeavesR3[0].uEcx,
923 pInfo->paCpuIdLeavesR3[0].uEdx);
924 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
925 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
926 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
927 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
928 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
929
930 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
931 {
932 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
933 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
934 {
935 /* Match against Family, Microarch, model and stepping. Except
936 for family, always match the closer with preference given to
937 the later/older ones. */
938 if (pCur->uFamily == uFamily)
939 {
940 if (pCur->enmMicroarch == enmMicroarch)
941 {
942 if (pCur->uModel == uModel)
943 {
944 if (pCur->uStepping == uStepping)
945 {
946 /* Perfect match. */
947 pEntry = pCur;
948 break;
949 }
950
951 if ( !pEntry
952 || pEntry->uModel != uModel
953 || pEntry->enmMicroarch != enmMicroarch
954 || pEntry->uFamily != uFamily)
955 pEntry = pCur;
956 else if ( pCur->uStepping >= uStepping
957 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
958 : pCur->uStepping > pEntry->uStepping)
959 pEntry = pCur;
960 }
961 else if ( !pEntry
962 || pEntry->enmMicroarch != enmMicroarch
963 || pEntry->uFamily != uFamily)
964 pEntry = pCur;
965 else if ( pCur->uModel >= uModel
966 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
967 : pCur->uModel > pEntry->uModel)
968 pEntry = pCur;
969 }
970 else if ( !pEntry
971 || pEntry->uFamily != uFamily)
972 pEntry = pCur;
973 /* Special march matching rules applies to intel family 06h. */
974 else if ( enmVendor == CPUMCPUVENDOR_INTEL
975 && uFamily == 6
976 ? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
977 : cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
978 pEntry = pCur;
979 }
980 /* We don't do closeness matching on family, we use the first
981 entry for the CPU vendor instead. (P4 workaround.) */
982 else if (!pEntry)
983 pEntry = pCur;
984 }
985 }
986
987 if (pEntry)
988 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
989 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
990 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
991 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
992 else
993 {
994 pEntry = g_apCpumDbEntries[0];
995 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
996 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
997 pEntry->pszName));
998 }
999 }
1000 else
1001 {
1002 /*
1003 * We're supposed to be emulating a specific CPU that is included in
1004 * our CPU database. The CPUID tables needs to be copied onto the
1005 * heap so the caller can modify them and so they can be freed like
1006 * in the host case above.
1007 */
1008 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
1009 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
1010 {
1011 pEntry = g_apCpumDbEntries[i];
1012 break;
1013 }
1014 if (!pEntry)
1015 {
1016 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
1017 return VERR_CPUM_DB_CPU_NOT_FOUND;
1018 }
1019
1020 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1021 if (pEntry->cCpuIdLeaves)
1022 {
1023 /* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1024 size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1025 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1026 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1027 cbExtra);
1028 if (!pInfo->paCpuIdLeavesR3)
1029 return VERR_NO_MEMORY;
1030 }
1031 else
1032 pInfo->paCpuIdLeavesR3 = NULL;
1033
1034 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1035 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1036 pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1037
1038 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1039 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1040 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1041 }
1042
1043 pInfo->fMsrMask = pEntry->fMsrMask;
1044 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1045 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1046 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1047 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1048
1049 /*
1050 * Copy the MSR range.
1051 */
1052 uint32_t cMsrs = 0;
1053 PCPUMMSRRANGE paMsrs = NULL;
1054
1055 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1056 uint32_t cLeft = pEntry->cMsrRanges;
1057 while (cLeft-- > 0)
1058 {
1059 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1060 if (RT_FAILURE(rc))
1061 {
1062 Assert(!paMsrs); /* The above function frees this. */
1063 RTMemFree(pInfo->paCpuIdLeavesR3);
1064 pInfo->paCpuIdLeavesR3 = NULL;
1065 return rc;
1066 }
1067 pCurMsr++;
1068 }
1069
1070 pInfo->paMsrRangesR3 = paMsrs;
1071 pInfo->cMsrRanges = cMsrs;
1072 return VINF_SUCCESS;
1073}
1074
1075
1076/**
1077 * Insert an MSR range into the VM.
1078 *
1079 * If the new MSR range overlaps existing ranges, the existing ones will be
1080 * adjusted/removed to fit in the new one.
1081 *
1082 * @returns VBox status code.
1083 * @param pVM The cross context VM structure.
1084 * @param pNewRange Pointer to the MSR range being inserted.
1085 */
1086VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1087{
1088 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1089 AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1090
1091 return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges */, NULL /* pcMsrRanges */, pNewRange);
1092}
1093
1094
1095/**
1096 * Register statistics for the MSRs.
1097 *
1098 * This must not be called before the MSRs have been finalized and moved to the
1099 * hyper heap.
1100 *
1101 * @returns VBox status code.
1102 * @param pVM The cross context VM structure.
1103 */
1104int cpumR3MsrRegStats(PVM pVM)
1105{
1106 /*
1107 * Global statistics.
1108 */
1109 PCPUM pCpum = &pVM->cpum.s;
1110 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1111 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1112 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1113 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1114 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1115 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1116 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1117 STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1118 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1119 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1120 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1121 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1122 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1123 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1124
1125
1126# ifdef VBOX_WITH_STATISTICS
1127 /*
1128 * Per range.
1129 */
1130 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1131 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1132 for (uint32_t i = 0; i < cRanges; i++)
1133 {
1134 char szName[160];
1135 ssize_t cchName;
1136
1137 if (paRanges[i].uFirst == paRanges[i].uLast)
1138 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1139 paRanges[i].uFirst, paRanges[i].szName);
1140 else
1141 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1142 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1143
1144 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1145 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1146
1147 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1148 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1149
1150 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1151 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1152
1153 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1154 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1155 }
1156# endif /* VBOX_WITH_STATISTICS */
1157
1158 return VINF_SUCCESS;
1159}
1160
1161#endif /* !CPUM_DB_STANDALONE */
1162
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