VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 85354

Last change on this file since 85354 was 85354, checked in by vboxsync, 4 years ago

VMM/CPUM: Add profile for Ryzen 7 1800X (first gen Zen)
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 45.8 KB
Line 
1/* $Id: CPUMR3Db.cpp 85354 2020-07-15 16:55:28Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include "CPUMInternal.h"
25#include <VBox/vmm/vm.h>
26#include <VBox/vmm/mm.h>
27
28#include <VBox/err.h>
29#include <iprt/asm-amd64-x86.h>
30#include <iprt/mem.h>
31#include <iprt/string.h>
32
33
34/*********************************************************************************************************************************
35* Structures and Typedefs *
36*********************************************************************************************************************************/
37typedef struct CPUMDBENTRY
38{
39 /** The CPU name. */
40 const char *pszName;
41 /** The full CPU name. */
42 const char *pszFullName;
43 /** The CPU vendor (CPUMCPUVENDOR). */
44 uint8_t enmVendor;
45 /** The CPU family. */
46 uint8_t uFamily;
47 /** The CPU model. */
48 uint8_t uModel;
49 /** The CPU stepping. */
50 uint8_t uStepping;
51 /** The microarchitecture. */
52 CPUMMICROARCH enmMicroarch;
53 /** Scalable bus frequency used for reporting other frequencies. */
54 uint64_t uScalableBusFreq;
55 /** Flags - CPUDB_F_XXX. */
56 uint32_t fFlags;
57 /** The maximum physical address with of the CPU. This should correspond to
58 * the value in CPUID leaf 0x80000008 when present. */
59 uint8_t cMaxPhysAddrWidth;
60 /** The MXCSR mask. */
61 uint32_t fMxCsrMask;
62 /** Pointer to an array of CPUID leaves. */
63 PCCPUMCPUIDLEAF paCpuIdLeaves;
64 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
65 uint32_t cCpuIdLeaves;
66 /** The method used to deal with unknown CPUID leaves. */
67 CPUMUNKNOWNCPUID enmUnknownCpuId;
68 /** The default unknown CPUID value. */
69 CPUMCPUID DefUnknownCpuId;
70
71 /** MSR mask. Several microarchitectures ignore the higher bits of ECX in
72 * the RDMSR and WRMSR instructions. */
73 uint32_t fMsrMask;
74
75 /** The number of ranges in the table pointed to b paMsrRanges. */
76 uint32_t cMsrRanges;
77 /** MSR ranges for this CPU. */
78 PCCPUMMSRRANGE paMsrRanges;
79} CPUMDBENTRY;
80
81
82/*********************************************************************************************************************************
83* Defined Constants And Macros *
84*********************************************************************************************************************************/
85/** @name CPUDB_F_XXX - CPUDBENTRY::fFlags
86 * @{ */
87/** Should execute all in IEM.
88 * @todo Implement this - currently done in Main... */
89#define CPUDB_F_EXECUTE_ALL_IN_IEM RT_BIT_32(0)
90/** @} */
91
92
93/** @def NULL_ALONE
94 * For eliminating an unnecessary data dependency in standalone builds (for
95 * VBoxSVC). */
96/** @def ZERO_ALONE
97 * For eliminating an unnecessary data size dependency in standalone builds (for
98 * VBoxSVC). */
99#ifndef CPUM_DB_STANDALONE
100# define NULL_ALONE(a_aTable) a_aTable
101# define ZERO_ALONE(a_cTable) a_cTable
102#else
103# define NULL_ALONE(a_aTable) NULL
104# define ZERO_ALONE(a_cTable) 0
105#endif
106
107
108/** @name Short macros for the MSR range entries.
109 *
110 * These are rather cryptic, but this is to reduce the attack on the right
111 * margin.
112 *
113 * @{ */
114/** Alias one MSR onto another (a_uTarget). */
115#define MAL(a_uMsr, a_szName, a_uTarget) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
117/** Functions handles everything. */
118#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
120/** Functions handles everything, with GP mask. */
121#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
123/** Function handlers, read-only. */
124#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
126/** Function handlers, ignore all writes. */
127#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
129/** Function handlers, with value. */
130#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
131 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
132/** Function handlers, with write ignore mask. */
133#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
134 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
135/** Function handlers, extended version. */
136#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
137 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
138/** Function handlers, with CPUMCPU storage variable. */
139#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
140 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
141 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
142/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
143#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
144 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
145 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** Read-only fixed value. */
147#define MVO(a_uMsr, a_szName, a_uValue) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
149/** Read-only fixed value, ignores all writes. */
150#define MVI(a_uMsr, a_szName, a_uValue) \
151 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
152/** Read fixed value, ignore writes outside GP mask. */
153#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
154 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
155/** Read fixed value, extended version with both GP and ignore masks. */
156#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
157 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
158/** The short form, no CPUM backing. */
159#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
160 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
161 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
162
163/** Range: Functions handles everything. */
164#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
165 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
166/** Range: Read fixed value, read-only. */
167#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
168 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
169/** Range: Read fixed value, ignore writes. */
170#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
171 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
172/** Range: The short form, no CPUM backing. */
173#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
174 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
175 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
176
177/** Internal form used by the macros. */
178#ifdef VBOX_WITH_STATISTICS
179# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
180 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
181 { 0 }, { 0 }, { 0 }, { 0 } }
182#else
183# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
184 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
185#endif
186/** @} */
187
188#ifndef CPUM_DB_STANDALONE
189
190#include "cpus/Intel_Core_i7_6700K.h"
191#include "cpus/Intel_Core_i7_5600U.h"
192#include "cpus/Intel_Core_i7_3960X.h"
193#include "cpus/Intel_Core_i5_3570.h"
194#include "cpus/Intel_Core_i7_2635QM.h"
195#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
196#include "cpus/Intel_Core2_X6800_2_93GHz.h"
197#include "cpus/Intel_Core2_T7600_2_33GHz.h"
198#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
199#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
200#include "cpus/Intel_Pentium_4_3_00GHz.h"
201#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
202#include "cpus/Intel_Atom_330_1_60GHz.h"
203#include "cpus/Intel_80486.h"
204#include "cpus/Intel_80386.h"
205#include "cpus/Intel_80286.h"
206#include "cpus/Intel_80186.h"
207#include "cpus/Intel_8086.h"
208
209#include "cpus/AMD_Ryzen_7_1800X_Eight_Core.h"
210#include "cpus/AMD_FX_8150_Eight_Core.h"
211#include "cpus/AMD_Phenom_II_X6_1100T.h"
212#include "cpus/Quad_Core_AMD_Opteron_2384.h"
213#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
214#include "cpus/AMD_Athlon_64_3200.h"
215
216#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
217
218#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
219
220#include "cpus/Hygon_C86_7185_32_core.h"
221
222
223/**
224 * The database entries.
225 *
226 * 1. The first entry is special. It is the fallback for unknown
227 * processors. Thus, it better be pretty representative.
228 *
229 * 2. The first entry for a CPU vendor is likewise important as it is
230 * the default entry for that vendor.
231 *
232 * Generally we put the most recent CPUs first, since these tend to have the
233 * most complicated and backwards compatible list of MSRs.
234 */
235static CPUMDBENTRY const * const g_apCpumDbEntries[] =
236{
237#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
238 &g_Entry_Intel_Core_i7_6700K,
239#endif
240#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
241 &g_Entry_Intel_Core_i7_5600U,
242#endif
243#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
244 &g_Entry_Intel_Core_i5_3570,
245#endif
246#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
247 &g_Entry_Intel_Core_i7_3960X,
248#endif
249#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
250 &g_Entry_Intel_Core_i7_2635QM,
251#endif
252#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
253 &g_Entry_Intel_Pentium_N3530_2_16GHz,
254#endif
255#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
256 &g_Entry_Intel_Atom_330_1_60GHz,
257#endif
258#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
259 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
260#endif
261#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
262 &g_Entry_Intel_Xeon_X5482_3_20GHz,
263#endif
264#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
265 &g_Entry_Intel_Core2_X6800_2_93GHz,
266#endif
267#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
268 &g_Entry_Intel_Core2_T7600_2_33GHz,
269#endif
270#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
271 &g_Entry_Intel_Core_Duo_T2600_2_16GHz,
272#endif
273#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
274 &g_Entry_Intel_Pentium_4_3_00GHz,
275#endif
276#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
277 &g_Entry_Intel_Pentium_4_3_00GHz,
278#endif
279/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
280#ifdef VBOX_CPUDB_Intel_80486_h
281 &g_Entry_Intel_80486,
282#endif
283#ifdef VBOX_CPUDB_Intel_80386_h
284 &g_Entry_Intel_80386,
285#endif
286#ifdef VBOX_CPUDB_Intel_80286_h
287 &g_Entry_Intel_80286,
288#endif
289#ifdef VBOX_CPUDB_Intel_80186_h
290 &g_Entry_Intel_80186,
291#endif
292#ifdef VBOX_CPUDB_Intel_8086_h
293 &g_Entry_Intel_8086,
294#endif
295
296#ifdef VBOX_CPUDB_AMD_Ryzen_7_1800X_Eight_Core_h
297 &g_Entry_AMD_Ryzen_7_1800X_Eight_Core,
298#endif
299#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
300 &g_Entry_AMD_FX_8150_Eight_Core,
301#endif
302#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
303 &g_Entry_AMD_Phenom_II_X6_1100T,
304#endif
305#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
306 &g_Entry_Quad_Core_AMD_Opteron_2384,
307#endif
308#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
309 &g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
310#endif
311#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
312 &g_Entry_AMD_Athlon_64_3200,
313#endif
314
315#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
316 &g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
317#endif
318
319#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
320 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
321#endif
322
323#ifdef VBOX_CPUDB_NEC_V20_h
324 &g_Entry_NEC_V20,
325#endif
326
327#ifdef VBOX_CPUDB_Hygon_C86_7185_32_core_h
328 &g_Entry_Hygon_C86_7185_32_core,
329#endif
330};
331
332
333
334/**
335 * Binary search used by cpumR3MsrRangesInsert and has some special properties
336 * wrt to mismatches.
337 *
338 * @returns Insert location.
339 * @param paMsrRanges The MSR ranges to search.
340 * @param cMsrRanges The number of MSR ranges.
341 * @param uMsr What to search for.
342 */
343static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
344{
345 if (!cMsrRanges)
346 return 0;
347
348 uint32_t iStart = 0;
349 uint32_t iLast = cMsrRanges - 1;
350 for (;;)
351 {
352 uint32_t i = iStart + (iLast - iStart + 1) / 2;
353 if ( uMsr >= paMsrRanges[i].uFirst
354 && uMsr <= paMsrRanges[i].uLast)
355 return i;
356 if (uMsr < paMsrRanges[i].uFirst)
357 {
358 if (i <= iStart)
359 return i;
360 iLast = i - 1;
361 }
362 else
363 {
364 if (i >= iLast)
365 {
366 if (i < cMsrRanges)
367 i++;
368 return i;
369 }
370 iStart = i + 1;
371 }
372 }
373}
374
375
376/**
377 * Ensures that there is space for at least @a cNewRanges in the table,
378 * reallocating the table if necessary.
379 *
380 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
381 * @a *ppaMsrRanges is freed and set to NULL.
382 * @param pVM The cross context VM structure. If NULL,
383 * use the process heap, otherwise the VM's hyper heap.
384 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
385 * @param cMsrRanges The current number of ranges.
386 * @param cNewRanges The number of ranges to be added.
387 */
388static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
389{
390 uint32_t cMsrRangesAllocated;
391 if (!pVM)
392 cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
393 else
394 {
395 /*
396 * We're using the hyper heap now, but when the range array was copied over to it from
397 * the host-context heap, we only copy the exact size and not the ensured size.
398 * See @bugref{7270}.
399 */
400 cMsrRangesAllocated = cMsrRanges;
401 }
402 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
403 {
404 void *pvNew;
405 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
406 if (pVM)
407 {
408 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
409 Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
410
411 size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
412 size_t cbNew = cNew * sizeof(**ppaMsrRanges);
413 int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
414 if (RT_FAILURE(rc))
415 {
416 *ppaMsrRanges = NULL;
417 pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
418 LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
419 return NULL;
420 }
421 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
422 }
423 else
424 {
425 pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
426 if (!pvNew)
427 {
428 RTMemFree(*ppaMsrRanges);
429 *ppaMsrRanges = NULL;
430 return NULL;
431 }
432 }
433 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
434 }
435
436 if (pVM)
437 {
438 /* Update the R0 pointer. */
439 Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
440 pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
441 }
442
443 return *ppaMsrRanges;
444}
445
446
447/**
448 * Inserts a new MSR range in into an sorted MSR range array.
449 *
450 * If the new MSR range overlaps existing ranges, the existing ones will be
451 * adjusted/removed to fit in the new one.
452 *
453 * @returns VBox status code.
454 * @retval VINF_SUCCESS
455 * @retval VERR_NO_MEMORY
456 *
457 * @param pVM The cross context VM structure. If NULL,
458 * use the process heap, otherwise the VM's hyper heap.
459 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
460 * Must be NULL if using the hyper heap.
461 * @param pcMsrRanges The variable holding number of ranges. Must be NULL
462 * if using the hyper heap.
463 * @param pNewRange The new range.
464 */
465int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
466{
467 Assert(pNewRange->uLast >= pNewRange->uFirst);
468 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
469 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
470
471 /*
472 * Validate and use the VM's MSR ranges array if we are using the hyper heap.
473 */
474 if (pVM)
475 {
476 AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
477 AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
478
479 ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
480 pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
481 }
482 else
483 {
484 AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
485 AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
486 }
487
488 uint32_t cMsrRanges = *pcMsrRanges;
489 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
490
491 /*
492 * Optimize the linear insertion case where we add new entries at the end.
493 */
494 if ( cMsrRanges > 0
495 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
496 {
497 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
498 if (!paMsrRanges)
499 return VERR_NO_MEMORY;
500 paMsrRanges[cMsrRanges] = *pNewRange;
501 *pcMsrRanges += 1;
502 }
503 else
504 {
505 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
506 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
507 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
508
509 /*
510 * Adding an entirely new entry?
511 */
512 if ( i >= cMsrRanges
513 || pNewRange->uLast < paMsrRanges[i].uFirst)
514 {
515 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
516 if (!paMsrRanges)
517 return VERR_NO_MEMORY;
518 if (i < cMsrRanges)
519 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
520 paMsrRanges[i] = *pNewRange;
521 *pcMsrRanges += 1;
522 }
523 /*
524 * Replace existing entry?
525 */
526 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
527 && pNewRange->uLast == paMsrRanges[i].uLast)
528 paMsrRanges[i] = *pNewRange;
529 /*
530 * Splitting an existing entry?
531 */
532 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
533 && pNewRange->uLast < paMsrRanges[i].uLast)
534 {
535 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
536 if (!paMsrRanges)
537 return VERR_NO_MEMORY;
538 if (i < cMsrRanges)
539 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
540 paMsrRanges[i + 1] = *pNewRange;
541 paMsrRanges[i + 2] = paMsrRanges[i];
542 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
543 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
544 *pcMsrRanges += 2;
545 }
546 /*
547 * Complicated scenarios that can affect more than one range.
548 *
549 * The current code does not optimize memmove calls when replacing
550 * one or more existing ranges, because it's tedious to deal with and
551 * not expected to be a frequent usage scenario.
552 */
553 else
554 {
555 /* Adjust start of first match? */
556 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
557 && pNewRange->uLast < paMsrRanges[i].uLast)
558 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
559 else
560 {
561 /* Adjust end of first match? */
562 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
563 {
564 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
565 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
566 i++;
567 }
568 /* Replace the whole first match (lazy bird). */
569 else
570 {
571 if (i + 1 < cMsrRanges)
572 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
573 cMsrRanges = *pcMsrRanges -= 1;
574 }
575
576 /* Do the new range affect more ranges? */
577 while ( i < cMsrRanges
578 && pNewRange->uLast >= paMsrRanges[i].uFirst)
579 {
580 if (pNewRange->uLast < paMsrRanges[i].uLast)
581 {
582 /* Adjust the start of it, then we're done. */
583 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
584 break;
585 }
586
587 /* Remove it entirely. */
588 if (i + 1 < cMsrRanges)
589 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
590 cMsrRanges = *pcMsrRanges -= 1;
591 }
592 }
593
594 /* Now, perform a normal insertion. */
595 paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
596 if (!paMsrRanges)
597 return VERR_NO_MEMORY;
598 if (i < cMsrRanges)
599 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
600 paMsrRanges[i] = *pNewRange;
601 *pcMsrRanges += 1;
602 }
603 }
604
605 return VINF_SUCCESS;
606}
607
608
609/**
610 * Reconciles CPUID info with MSRs (selected ones).
611 *
612 * @returns VBox status code.
613 * @param pVM The cross context VM structure.
614 */
615int cpumR3MsrReconcileWithCpuId(PVM pVM)
616{
617 PCCPUMMSRRANGE papToAdd[10];
618 uint32_t cToAdd = 0;
619
620 /*
621 * The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
622 */
623 if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
624 {
625 static CPUMMSRRANGE const s_FlushCmd =
626 {
627 /*.uFirst =*/ MSR_IA32_FLUSH_CMD,
628 /*.uLast =*/ MSR_IA32_FLUSH_CMD,
629 /*.enmRdFn =*/ kCpumMsrRdFn_WriteOnly,
630 /*.enmWrFn =*/ kCpumMsrWrFn_Ia32FlushCmd,
631 /*.offCpumCpu =*/ UINT16_MAX,
632 /*.fReserved =*/ 0,
633 /*.uValue =*/ 0,
634 /*.fWrIgnMask =*/ 0,
635 /*.fWrGpMask =*/ ~MSR_IA32_FLUSH_CMD_F_L1D,
636 /*.szName = */ "IA32_FLUSH_CMD"
637 };
638 papToAdd[cToAdd++] = &s_FlushCmd;
639 }
640
641 /*
642 * The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
643 * documented in relation to such.
644 */
645 if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
646 {
647 static CPUMMSRRANGE const s_ArchCaps =
648 {
649 /*.uFirst =*/ MSR_IA32_ARCH_CAPABILITIES,
650 /*.uLast =*/ MSR_IA32_ARCH_CAPABILITIES,
651 /*.enmRdFn =*/ kCpumMsrRdFn_Ia32ArchCapabilities,
652 /*.enmWrFn =*/ kCpumMsrWrFn_ReadOnly,
653 /*.offCpumCpu =*/ UINT16_MAX,
654 /*.fReserved =*/ 0,
655 /*.uValue =*/ 0,
656 /*.fWrIgnMask =*/ 0,
657 /*.fWrGpMask =*/ UINT64_MAX,
658 /*.szName = */ "IA32_ARCH_CAPABILITIES"
659 };
660 papToAdd[cToAdd++] = &s_ArchCaps;
661 }
662
663 /*
664 * Do the adding.
665 */
666 for (uint32_t i = 0; i < cToAdd; i++)
667 {
668 PCCPUMMSRRANGE pRange = papToAdd[i];
669 LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
670 int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
671 pRange);
672 if (RT_FAILURE(rc))
673 return rc;
674 }
675 return VINF_SUCCESS;
676}
677
678
679/**
680 * Worker for cpumR3MsrApplyFudge that applies one table.
681 *
682 * @returns VBox status code.
683 * @param pVM The cross context VM structure.
684 * @param paRanges Array of MSRs to fudge.
685 * @param cRanges Number of MSRs in the array.
686 */
687static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
688{
689 for (uint32_t i = 0; i < cRanges; i++)
690 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
691 {
692 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
693 int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
694 &paRanges[i]);
695 if (RT_FAILURE(rc))
696 return rc;
697 }
698 return VINF_SUCCESS;
699}
700
701
702/**
703 * Fudges the MSRs that guest are known to access in some odd cases.
704 *
705 * A typical example is a VM that has been moved between different hosts where
706 * for instance the cpu vendor differs.
707 *
708 * Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
709 * Atom Silvermont), where features reported thru CPUID aren't present in the
710 * MSRs (e.g. AMD64_TSC_AUX).
711 *
712 *
713 * @returns VBox status code.
714 * @param pVM The cross context VM structure.
715 */
716int cpumR3MsrApplyFudge(PVM pVM)
717{
718 /*
719 * Basic.
720 */
721 static CPUMMSRRANGE const s_aFudgeMsrs[] =
722 {
723 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
724 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
725 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
726 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
727 MVI(0x0000008b, "BIOS_SIGN", 0),
728 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
729 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
730 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
731 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
732 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
733 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
734 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
735 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
736 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
737 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
738 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
739 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
740 };
741 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
742 AssertLogRelRCReturn(rc, rc);
743
744 /*
745 * XP might mistake opterons and other newer CPUs for P4s.
746 */
747 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
748 {
749 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
750 {
751 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
752 };
753 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
754 AssertLogRelRCReturn(rc, rc);
755 }
756
757 if (pVM->cpum.s.GuestFeatures.fRdTscP)
758 {
759 static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
760 {
761 MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
762 };
763 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
764 AssertLogRelRCReturn(rc, rc);
765 }
766
767 /*
768 * Windows 10 incorrectly writes to MSR_IA32_TSX_CTRL without checking
769 * CPUID.ARCH_CAP(EAX=7h,ECX=0):EDX[bit 29] or the MSR feature bits in
770 * MSR_IA32_ARCH_CAPABILITIES[bit 7], see @bugref{9630}.
771 * Ignore writes to this MSR and return 0 on reads.
772 */
773 if (pVM->cpum.s.GuestFeatures.fArchCap)
774 {
775 static CPUMMSRRANGE const s_aTsxCtrl[] =
776 {
777 MVI(MSR_IA32_TSX_CTRL, "IA32_TSX_CTRL", 0),
778 };
779 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aTsxCtrl[0], RT_ELEMENTS(s_aTsxCtrl));
780 AssertLogRelRCReturn(rc, rc);
781 }
782
783 return rc;
784}
785
786
787/**
788 * Do we consider @a enmConsider a better match for @a enmTarget than
789 * @a enmFound?
790 *
791 * Only called when @a enmConsider isn't exactly what we're looking for.
792 *
793 * @returns true/false.
794 * @param enmConsider The new microarch to consider.
795 * @param enmTarget The target microarch.
796 * @param enmFound The best microarch match we've found thus far.
797 */
798DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
799{
800 Assert(enmConsider != enmTarget);
801
802 /*
803 * If we've got an march match, don't bother with enmConsider.
804 */
805 if (enmFound == enmTarget)
806 return false;
807
808 /*
809 * Found is below: Pick 'consider' if it's closer to the target or above it.
810 */
811 if (enmFound < enmTarget)
812 return enmConsider > enmFound;
813
814 /*
815 * Found is above: Pick 'consider' if it's also above (paranoia: or equal)
816 * and but closer to the target.
817 */
818 return enmConsider >= enmTarget && enmConsider < enmFound;
819}
820
821
822/**
823 * Do we consider @a enmConsider a better match for @a enmTarget than
824 * @a enmFound?
825 *
826 * Only called for intel family 06h CPUs.
827 *
828 * @returns true/false.
829 * @param enmConsider The new microarch to consider.
830 * @param enmTarget The target microarch.
831 * @param enmFound The best microarch match we've found thus far.
832 */
833static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
834{
835 /* Check intel family 06h claims. */
836 AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
837 false);
838 AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
839 false);
840
841 /* Put matches out of the way. */
842 if (enmConsider == enmTarget)
843 return true;
844 if (enmFound == enmTarget)
845 return false;
846
847 /* If found isn't a family 06h march, whatever we're considering must be a better choice. */
848 if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
849 || enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
850 return true;
851
852 /*
853 * The family 06h stuff is split into three categories:
854 * - Common P6 heritage
855 * - Core
856 * - Atom
857 *
858 * Determin which of the three arguments are Atom marchs, because that's
859 * all we need to make the right choice.
860 */
861 bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
862 bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
863 bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
864
865 /*
866 * Want atom:
867 */
868 if (fTargetAtom)
869 {
870 /* Pick the atom if we've got one of each.*/
871 if (fConsiderAtom != fFoundAtom)
872 return fConsiderAtom;
873 /* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
874 Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
875 if (!fConsiderAtom)
876 {
877 if (enmConsider > enmFound)
878 return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
879 return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
880 }
881 /* else: same category, default comparison rules. */
882 Assert(fConsiderAtom && fFoundAtom);
883 }
884 /*
885 * Want non-atom:
886 */
887 /* Pick the non-atom if we've got one of each. */
888 else if (fConsiderAtom != fFoundAtom)
889 return fFoundAtom;
890 /* If we've only got atoms under consideration, pick the older one just to pick something. */
891 else if (fConsiderAtom)
892 return enmConsider < enmFound;
893 else
894 Assert(!fConsiderAtom && !fFoundAtom);
895
896 /*
897 * Same basic category. Do same compare as caller.
898 */
899 return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
900}
901
902
903int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
904{
905 CPUMDBENTRY const *pEntry = NULL;
906 int rc;
907
908 if (!strcmp(pszName, "host"))
909 {
910 /*
911 * Create a CPU database entry for the host CPU. This means getting
912 * the CPUID bits from the real CPU and grabbing the closest matching
913 * database entry for MSRs.
914 */
915 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
916 if (RT_FAILURE(rc))
917 return rc;
918 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
919 if (RT_FAILURE(rc))
920 return rc;
921 pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
922
923 /* Lookup database entry for MSRs. */
924 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
925 pInfo->paCpuIdLeavesR3[0].uEbx,
926 pInfo->paCpuIdLeavesR3[0].uEcx,
927 pInfo->paCpuIdLeavesR3[0].uEdx);
928 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
929 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
930 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
931 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
932 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
933
934 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
935 {
936 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
937 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
938 {
939 /* Match against Family, Microarch, model and stepping. Except
940 for family, always match the closer with preference given to
941 the later/older ones. */
942 if (pCur->uFamily == uFamily)
943 {
944 if (pCur->enmMicroarch == enmMicroarch)
945 {
946 if (pCur->uModel == uModel)
947 {
948 if (pCur->uStepping == uStepping)
949 {
950 /* Perfect match. */
951 pEntry = pCur;
952 break;
953 }
954
955 if ( !pEntry
956 || pEntry->uModel != uModel
957 || pEntry->enmMicroarch != enmMicroarch
958 || pEntry->uFamily != uFamily)
959 pEntry = pCur;
960 else if ( pCur->uStepping >= uStepping
961 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
962 : pCur->uStepping > pEntry->uStepping)
963 pEntry = pCur;
964 }
965 else if ( !pEntry
966 || pEntry->enmMicroarch != enmMicroarch
967 || pEntry->uFamily != uFamily)
968 pEntry = pCur;
969 else if ( pCur->uModel >= uModel
970 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
971 : pCur->uModel > pEntry->uModel)
972 pEntry = pCur;
973 }
974 else if ( !pEntry
975 || pEntry->uFamily != uFamily)
976 pEntry = pCur;
977 /* Special march matching rules applies to intel family 06h. */
978 else if ( enmVendor == CPUMCPUVENDOR_INTEL
979 && uFamily == 6
980 ? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
981 : cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
982 pEntry = pCur;
983 }
984 /* We don't do closeness matching on family, we use the first
985 entry for the CPU vendor instead. (P4 workaround.) */
986 else if (!pEntry)
987 pEntry = pCur;
988 }
989 }
990
991 if (pEntry)
992 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
993 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
994 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
995 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
996 else
997 {
998 pEntry = g_apCpumDbEntries[0];
999 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
1000 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
1001 pEntry->pszName));
1002 }
1003 }
1004 else
1005 {
1006 /*
1007 * We're supposed to be emulating a specific CPU that is included in
1008 * our CPU database. The CPUID tables needs to be copied onto the
1009 * heap so the caller can modify them and so they can be freed like
1010 * in the host case above.
1011 */
1012 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
1013 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
1014 {
1015 pEntry = g_apCpumDbEntries[i];
1016 break;
1017 }
1018 if (!pEntry)
1019 {
1020 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
1021 return VERR_CPUM_DB_CPU_NOT_FOUND;
1022 }
1023
1024 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1025 if (pEntry->cCpuIdLeaves)
1026 {
1027 /* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1028 size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1029 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1030 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1031 cbExtra);
1032 if (!pInfo->paCpuIdLeavesR3)
1033 return VERR_NO_MEMORY;
1034 }
1035 else
1036 pInfo->paCpuIdLeavesR3 = NULL;
1037
1038 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1039 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1040 pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1041
1042 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1043 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1044 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1045 }
1046
1047 pInfo->fMsrMask = pEntry->fMsrMask;
1048 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1049 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1050 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1051 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1052
1053 /*
1054 * Copy the MSR range.
1055 */
1056 uint32_t cMsrs = 0;
1057 PCPUMMSRRANGE paMsrs = NULL;
1058
1059 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1060 uint32_t cLeft = pEntry->cMsrRanges;
1061 while (cLeft-- > 0)
1062 {
1063 rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1064 if (RT_FAILURE(rc))
1065 {
1066 Assert(!paMsrs); /* The above function frees this. */
1067 RTMemFree(pInfo->paCpuIdLeavesR3);
1068 pInfo->paCpuIdLeavesR3 = NULL;
1069 return rc;
1070 }
1071 pCurMsr++;
1072 }
1073
1074 pInfo->paMsrRangesR3 = paMsrs;
1075 pInfo->cMsrRanges = cMsrs;
1076 return VINF_SUCCESS;
1077}
1078
1079
1080/**
1081 * Insert an MSR range into the VM.
1082 *
1083 * If the new MSR range overlaps existing ranges, the existing ones will be
1084 * adjusted/removed to fit in the new one.
1085 *
1086 * @returns VBox status code.
1087 * @param pVM The cross context VM structure.
1088 * @param pNewRange Pointer to the MSR range being inserted.
1089 */
1090VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1091{
1092 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1093 AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1094
1095 return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges */, NULL /* pcMsrRanges */, pNewRange);
1096}
1097
1098
1099/**
1100 * Register statistics for the MSRs.
1101 *
1102 * This must not be called before the MSRs have been finalized and moved to the
1103 * hyper heap.
1104 *
1105 * @returns VBox status code.
1106 * @param pVM The cross context VM structure.
1107 */
1108int cpumR3MsrRegStats(PVM pVM)
1109{
1110 /*
1111 * Global statistics.
1112 */
1113 PCPUM pCpum = &pVM->cpum.s;
1114 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1115 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1116 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1117 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1118 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1119 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1120 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1121 STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1122 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1123 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1124 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1125 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1126 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1127 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1128
1129
1130# ifdef VBOX_WITH_STATISTICS
1131 /*
1132 * Per range.
1133 */
1134 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1135 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1136 for (uint32_t i = 0; i < cRanges; i++)
1137 {
1138 char szName[160];
1139 ssize_t cchName;
1140
1141 if (paRanges[i].uFirst == paRanges[i].uLast)
1142 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1143 paRanges[i].uFirst, paRanges[i].szName);
1144 else
1145 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1146 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1147
1148 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1149 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1150
1151 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1152 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1153
1154 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1155 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1156
1157 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1158 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1159 }
1160# endif /* VBOX_WITH_STATISTICS */
1161
1162 return VINF_SUCCESS;
1163}
1164
1165#endif /* !CPUM_DB_STANDALONE */
1166
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use