VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 51234

Last change on this file since 51234 was 50656, checked in by vboxsync, 10 years ago

Added an example of the initial SandyBridge silicone.
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1/* $Id: CPUMR3Db.cpp 50656 2014-02-28 20:04:22Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include "CPUMInternal.h"
24#include <VBox/vmm/vm.h>
25
26#include <VBox/err.h>
27#include <iprt/asm-amd64-x86.h>
28#include <iprt/mem.h>
29#include <iprt/string.h>
30
31
32/*******************************************************************************
33* Structures and Typedefs *
34*******************************************************************************/
35typedef struct CPUMDBENTRY
36{
37 /** The CPU name. */
38 const char *pszName;
39 /** The full CPU name. */
40 const char *pszFullName;
41 /** The CPU vendor (CPUMCPUVENDOR). */
42 uint8_t enmVendor;
43 /** The CPU family. */
44 uint8_t uFamily;
45 /** The CPU model. */
46 uint8_t uModel;
47 /** The CPU stepping. */
48 uint8_t uStepping;
49 /** The microarchitecture. */
50 CPUMMICROARCH enmMicroarch;
51 /** Scalable bus frequency used for reporting other frequencies. */
52 uint64_t uScalableBusFreq;
53 /** Flags (TBD). */
54 uint32_t fFlags;
55 /** The maximum physical address with of the CPU. This should correspond to
56 * the value in CPUID leaf 0x80000008 when present. */
57 uint8_t cMaxPhysAddrWidth;
58 /** Pointer to an array of CPUID leaves. */
59 PCCPUMCPUIDLEAF paCpuIdLeaves;
60 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
61 uint32_t cCpuIdLeaves;
62 /** The method used to deal with unknown CPUID leaves. */
63 CPUMUKNOWNCPUID enmUnknownCpuId;
64 /** The default unknown CPUID value. */
65 CPUMCPUID DefUnknownCpuId;
66
67 /** MSR mask. Several microarchitectures ignore higher bits of the */
68 uint32_t fMsrMask;
69
70 /** The number of ranges in the table pointed to b paMsrRanges. */
71 uint32_t cMsrRanges;
72 /** MSR ranges for this CPU. */
73 PCCPUMMSRRANGE paMsrRanges;
74} CPUMDBENTRY;
75
76
77/*******************************************************************************
78* Defined Constants And Macros *
79*******************************************************************************/
80
81/** @def NULL_ALONE
82 * For eliminating an unnecessary data dependency in standalone builds (for
83 * VBoxSVC). */
84/** @def ZERO_ALONE
85 * For eliminating an unnecessary data size dependency in standalone builds (for
86 * VBoxSVC). */
87#ifndef CPUM_DB_STANDALONE
88# define NULL_ALONE(a_aTable) a_aTable
89# define ZERO_ALONE(a_cTable) a_cTable
90#else
91# define NULL_ALONE(a_aTable) NULL
92# define ZERO_ALONE(a_cTable) 0
93#endif
94
95
96/** @name Short macros for the MSR range entries.
97 *
98 * These are rather cryptic, but this is to reduce the attack on the right
99 * margin.
100 *
101 * @{ */
102/** Alias one MSR onto another (a_uTarget). */
103#define MAL(a_uMsr, a_szName, a_uTarget) \
104 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
105/** Functions handles everything. */
106#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
107 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
108/** Functions handles everything, with GP mask. */
109#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
110 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
111/** Function handlers, read-only. */
112#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
113 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
114/** Function handlers, ignore all writes. */
115#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
117/** Function handlers, with value. */
118#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
120/** Function handlers, with write ignore mask. */
121#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
123/** Function handlers, extended version. */
124#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
126/** Function handlers, with CPUMCPU storage variable. */
127#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
129 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
130/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
131#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
132 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
133 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
134/** Read-only fixed value. */
135#define MVO(a_uMsr, a_szName, a_uValue) \
136 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
137/** Read-only fixed value, ignores all writes. */
138#define MVI(a_uMsr, a_szName, a_uValue) \
139 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
140/** Read fixed value, ignore writes outside GP mask. */
141#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
142 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
143/** Read fixed value, extended version with both GP and ignore masks. */
144#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
145 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** The short form, no CPUM backing. */
147#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
149 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
150
151/** Range: Functions handles everything. */
152#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
153 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
154/** Range: Read fixed value, read-only. */
155#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
156 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
157/** Range: Read fixed value, ignore writes. */
158#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
159 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
160/** Range: The short form, no CPUM backing. */
161#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
162 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
163 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
164
165/** Internal form used by the macros. */
166#ifdef VBOX_WITH_STATISTICS
167# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
168 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
169 { 0 }, { 0 }, { 0 }, { 0 } }
170#else
171# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
172 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
173#endif
174/** @} */
175
176
177#include "cpus/Intel_Core_i7_3960X.h"
178#include "cpus/Intel_Core_i5_3570.h"
179#include "cpus/Intel_Core_i7_2635QM.h"
180#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
181#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
182#include "cpus/Intel_Pentium_4_3_00GHz.h"
183
184#include "cpus/AMD_FX_8150_Eight_Core.h"
185#include "cpus/AMD_Phenom_II_X6_1100T.h"
186#include "cpus/Quad_Core_AMD_Opteron_2384.h"
187#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
188#include "cpus/AMD_Athlon_64_3200.h"
189
190#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
191
192
193
194/**
195 * The database entries.
196 *
197 * 1. The first entry is special. It is the fallback for unknown
198 * processors. Thus, it better be pretty representative.
199 *
200 * 2. The first entry for a CPU vendor is likewise important as it is
201 * the default entry for that vendor.
202 *
203 * Generally we put the most recent CPUs first, since these tend to have the
204 * most complicated and backwards compatible list of MSRs.
205 */
206static CPUMDBENTRY const * const g_apCpumDbEntries[] =
207{
208#ifdef VBOX_CPUDB_Intel_Core_i5_3570
209 &g_Entry_Intel_Core_i5_3570,
210#endif
211#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
212 &g_Entry_Intel_Core_i7_3960X,
213#endif
214#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM
215 &g_Entry_Intel_Core_i7_2635QM,
216#endif
217#ifdef Intel_Pentium_M_processor_2_00GHz
218 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
219#endif
220#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
221 &g_Entry_Intel_Xeon_X5482_3_20GHz,
222#endif
223#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
224 &g_Entry_Intel_Pentium_4_3_00GHz,
225#endif
226
227#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
228 &g_Entry_AMD_FX_8150_Eight_Core,
229#endif
230#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
231 &g_Entry_AMD_Phenom_II_X6_1100T,
232#endif
233#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
234 &g_Entry_Quad_Core_AMD_Opteron_2384,
235#endif
236#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
237 &g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
238#endif
239#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
240 &g_Entry_AMD_Athlon_64_3200,
241#endif
242
243#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
244 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
245#endif
246};
247
248
249#ifndef CPUM_DB_STANDALONE
250
251/**
252 * Binary search used by cpumR3MsrRangesInsert and has some special properties
253 * wrt to mismatches.
254 *
255 * @returns Insert location.
256 * @param paMsrRanges The MSR ranges to search.
257 * @param cMsrRanges The number of MSR ranges.
258 * @param uMsr What to search for.
259 */
260static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
261{
262 if (!cMsrRanges)
263 return 0;
264
265 uint32_t iStart = 0;
266 uint32_t iLast = cMsrRanges - 1;
267 for (;;)
268 {
269 uint32_t i = iStart + (iLast - iStart + 1) / 2;
270 if ( uMsr >= paMsrRanges[i].uFirst
271 && uMsr <= paMsrRanges[i].uLast)
272 return i;
273 if (uMsr < paMsrRanges[i].uFirst)
274 {
275 if (i <= iStart)
276 return i;
277 iLast = i - 1;
278 }
279 else
280 {
281 if (i >= iLast)
282 {
283 if (i < cMsrRanges)
284 i++;
285 return i;
286 }
287 iStart = i + 1;
288 }
289 }
290}
291
292
293/**
294 * Ensures that there is space for at least @a cNewRanges in the table,
295 * reallocating the table if necessary.
296 *
297 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
298 * @a *ppaMsrRanges is freed and set to NULL.
299 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
300 * @param cMsrRanges The current number of ranges.
301 * @param cNewRanges The number of ranges to be added.
302 */
303static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
304{
305 uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
306 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
307 {
308 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
309 void *pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
310 if (!pvNew)
311 {
312 RTMemFree(*ppaMsrRanges);
313 *ppaMsrRanges = NULL;
314 return NULL;
315 }
316 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
317 }
318 return *ppaMsrRanges;
319}
320
321
322/**
323 * Inserts a new MSR range in into an sorted MSR range array.
324 *
325 * If the new MSR range overlaps existing ranges, the existing ones will be
326 * adjusted/removed to fit in the new one.
327 *
328 * @returns VBox status code.
329 * @retval VINF_SUCCESS
330 * @retval VERR_NO_MEMORY
331 *
332 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
333 * @param pcMsrRanges The variable holding number of ranges.
334 * @param pNewRange The new range.
335 */
336int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
337{
338 uint32_t cMsrRanges = *pcMsrRanges;
339 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
340
341 Assert(pNewRange->uLast >= pNewRange->uFirst);
342 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
343 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
344
345 /*
346 * Optimize the linear insertion case where we add new entries at the end.
347 */
348 if ( cMsrRanges > 0
349 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
350 {
351 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
352 if (!paMsrRanges)
353 return VERR_NO_MEMORY;
354 paMsrRanges[cMsrRanges] = *pNewRange;
355 *pcMsrRanges += 1;
356 }
357 else
358 {
359 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
360 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
361 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
362
363 /*
364 * Adding an entirely new entry?
365 */
366 if ( i >= cMsrRanges
367 || pNewRange->uLast < paMsrRanges[i].uFirst)
368 {
369 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
370 if (!paMsrRanges)
371 return VERR_NO_MEMORY;
372 if (i < cMsrRanges)
373 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
374 paMsrRanges[i] = *pNewRange;
375 *pcMsrRanges += 1;
376 }
377 /*
378 * Replace existing entry?
379 */
380 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
381 && pNewRange->uLast == paMsrRanges[i].uLast)
382 paMsrRanges[i] = *pNewRange;
383 /*
384 * Splitting an existing entry?
385 */
386 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
387 && pNewRange->uLast < paMsrRanges[i].uLast)
388 {
389 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
390 if (!paMsrRanges)
391 return VERR_NO_MEMORY;
392 if (i < cMsrRanges)
393 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
394 paMsrRanges[i + 1] = *pNewRange;
395 paMsrRanges[i + 2] = paMsrRanges[i];
396 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
397 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
398 *pcMsrRanges += 2;
399 }
400 /*
401 * Complicated scenarios that can affect more than one range.
402 *
403 * The current code does not optimize memmove calls when replacing
404 * one or more existing ranges, because it's tedious to deal with and
405 * not expected to be a frequent usage scenario.
406 */
407 else
408 {
409 /* Adjust start of first match? */
410 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
411 && pNewRange->uLast < paMsrRanges[i].uLast)
412 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
413 else
414 {
415 /* Adjust end of first match? */
416 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
417 {
418 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
419 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
420 i++;
421 }
422 /* Replace the whole first match (lazy bird). */
423 else
424 {
425 if (i + 1 < cMsrRanges)
426 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
427 cMsrRanges = *pcMsrRanges -= 1;
428 }
429
430 /* Do the new range affect more ranges? */
431 while ( i < cMsrRanges
432 && pNewRange->uLast >= paMsrRanges[i].uFirst)
433 {
434 if (pNewRange->uLast < paMsrRanges[i].uLast)
435 {
436 /* Adjust the start of it, then we're done. */
437 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
438 break;
439 }
440
441 /* Remove it entirely. */
442 if (i + 1 < cMsrRanges)
443 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
444 cMsrRanges = *pcMsrRanges -= 1;
445 }
446 }
447
448 /* Now, perform a normal insertion. */
449 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
450 if (!paMsrRanges)
451 return VERR_NO_MEMORY;
452 if (i < cMsrRanges)
453 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
454 paMsrRanges[i] = *pNewRange;
455 *pcMsrRanges += 1;
456 }
457 }
458
459 return VINF_SUCCESS;
460}
461
462
463/**
464 * Worker for cpumR3MsrApplyFudge that applies one table.
465 *
466 * @returns VBox status code.
467 * @param pVM Pointer to the cross context VM structure.
468 * @param paRanges Array of MSRs to fudge.
469 * @param cRanges Number of MSRs in the array.
470 */
471static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
472{
473 for (uint32_t i = 0; i < cRanges; i++)
474 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
475 {
476 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
477 int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
478 &paRanges[i]);
479 if (RT_FAILURE(rc))
480 return rc;
481 }
482 return VINF_SUCCESS;
483}
484
485
486/**
487 * Fudges the MSRs that guest are known to access in some odd cases.
488 *
489 * A typical example is a VM that has been moved between different hosts where
490 * for instance the cpu vendor differs.
491 *
492 * @returns VBox status code.
493 * @param pVM Pointer to the cross context VM structure.
494 */
495int cpumR3MsrApplyFudge(PVM pVM)
496{
497 /*
498 * Basic.
499 */
500 static CPUMMSRRANGE const s_aFudgeMsrs[] =
501 {
502 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
503 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
504 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
505 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
506 MVI(0x0000008b, "BIOS_SIGN", 0),
507 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
508 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
509 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
510 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
511 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
512 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
513 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
514 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
515 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
516 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
517 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
518 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
519 };
520 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
521 AssertLogRelRCReturn(rc, rc);
522
523 /*
524 * XP might mistake opterons and other newer CPUs for P4s.
525 */
526 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
527 {
528 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
529 {
530 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
531 };
532 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
533 AssertLogRelRCReturn(rc, rc);
534 }
535
536 return rc;
537}
538
539
540int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
541{
542 CPUMDBENTRY const *pEntry = NULL;
543 int rc;
544
545 if (!strcmp(pszName, "host"))
546 {
547 /*
548 * Create a CPU database entry for the host CPU. This means getting
549 * the CPUID bits from the real CPU and grabbing the closest matching
550 * database entry for MSRs.
551 */
552 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
553 if (RT_FAILURE(rc))
554 return rc;
555 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
556 if (RT_FAILURE(rc))
557 return rc;
558
559 /* Lookup database entry for MSRs. */
560 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
561 pInfo->paCpuIdLeavesR3[0].uEbx,
562 pInfo->paCpuIdLeavesR3[0].uEcx,
563 pInfo->paCpuIdLeavesR3[0].uEdx);
564 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
565 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
566 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
567 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
568 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
569
570 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
571 {
572 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
573 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
574 {
575 /* Match against Family, Microarch, model and stepping. Except
576 for family, always match the closer with preference given to
577 the later/older ones. */
578 if (pCur->uFamily == uFamily)
579 {
580 if (pCur->enmMicroarch == enmMicroarch)
581 {
582 if (pCur->uModel == uModel)
583 {
584 if (pCur->uStepping == uStepping)
585 {
586 /* Perfect match. */
587 pEntry = pCur;
588 break;
589 }
590
591 if ( !pEntry
592 || pEntry->uModel != uModel
593 || pEntry->enmMicroarch != enmMicroarch
594 || pEntry->uFamily != uFamily)
595 pEntry = pCur;
596 else if ( pCur->uStepping >= uStepping
597 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
598 : pCur->uStepping > pEntry->uStepping)
599 pEntry = pCur;
600 }
601 else if ( !pEntry
602 || pEntry->enmMicroarch != enmMicroarch
603 || pEntry->uFamily != uFamily)
604 pEntry = pCur;
605 else if ( pCur->uModel >= uModel
606 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
607 : pCur->uModel > pEntry->uModel)
608 pEntry = pCur;
609 }
610 else if ( !pEntry
611 || pEntry->uFamily != uFamily)
612 pEntry = pCur;
613 else if ( pCur->enmMicroarch >= enmMicroarch
614 ? pCur->enmMicroarch < pEntry->enmMicroarch || pEntry->enmMicroarch < enmMicroarch
615 : pCur->enmMicroarch > pEntry->enmMicroarch)
616 pEntry = pCur;
617 }
618 /* We don't do closeness matching on family, we use the first
619 entry for the CPU vendor instead. (P4 workaround.) */
620 else if (!pEntry)
621 pEntry = pCur;
622 }
623 }
624
625 if (pEntry)
626 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
627 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
628 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
629 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
630 else
631 {
632 pEntry = g_apCpumDbEntries[0];
633 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
634 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
635 pEntry->pszName));
636 }
637 }
638 else
639 {
640 /*
641 * We're supposed to be emulating a specific CPU that is included in
642 * our CPU database. The CPUID tables needs to be copied onto the
643 * heap so the caller can modify them and so they can be freed like
644 * in the host case above.
645 */
646 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
647 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
648 {
649 pEntry = g_apCpumDbEntries[i];
650 break;
651 }
652 if (!pEntry)
653 {
654 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
655 return VERR_CPUM_DB_CPU_NOT_FOUND;
656 }
657
658 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
659 if (pEntry->cCpuIdLeaves)
660 {
661 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
662 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
663 if (!pInfo->paCpuIdLeavesR3)
664 return VERR_NO_MEMORY;
665 }
666 else
667 pInfo->paCpuIdLeavesR3 = NULL;
668
669 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
670 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
671
672 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
673 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
674 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
675 }
676
677 pInfo->fMsrMask = pEntry->fMsrMask;
678 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
679 pInfo->uPadding = 0;
680 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
681 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
682 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
683 pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
684 pInfo->paMsrRangesRC = NIL_RTRCPTR;
685
686 /*
687 * Copy the MSR range.
688 */
689 uint32_t cMsrs = 0;
690 PCPUMMSRRANGE paMsrs = NULL;
691
692 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
693 uint32_t cLeft = pEntry->cMsrRanges;
694 while (cLeft-- > 0)
695 {
696 rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
697 if (RT_FAILURE(rc))
698 {
699 Assert(!paMsrs); /* The above function frees this. */
700 RTMemFree(pInfo->paCpuIdLeavesR3);
701 pInfo->paCpuIdLeavesR3 = NULL;
702 return rc;
703 }
704 pCurMsr++;
705 }
706
707 pInfo->paMsrRangesR3 = paMsrs;
708 pInfo->cMsrRanges = cMsrs;
709 return VINF_SUCCESS;
710}
711
712
713/**
714 * Register statistics for the MSRs.
715 *
716 * This must not be called before the MSRs have been finalized and moved to the
717 * hyper heap.
718 *
719 * @returns VBox status code.
720 * @param pVM Pointer to the cross context VM structure.
721 */
722int cpumR3MsrRegStats(PVM pVM)
723{
724 /*
725 * Global statistics.
726 */
727 PCPUM pCpum = &pVM->cpum.s;
728 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
729 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
730 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
731 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
732 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
733 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
734 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
735 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
736 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
737 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
738 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
739 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
740 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
741 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
742
743
744# ifdef VBOX_WITH_STATISTICS
745 /*
746 * Per range.
747 */
748 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
749 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
750 for (uint32_t i = 0; i < cRanges; i++)
751 {
752 char szName[160];
753 ssize_t cchName;
754
755 if (paRanges[i].uFirst == paRanges[i].uLast)
756 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
757 paRanges[i].uFirst, paRanges[i].szName);
758 else
759 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
760 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
761
762 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
763 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
764
765 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
766 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
767
768 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
769 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
770
771 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
772 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
773 }
774# endif /* VBOX_WITH_STATISTICS */
775
776 return VINF_SUCCESS;
777}
778
779#endif /* !CPUM_DB_STANDALONE */
780
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