VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 50653

Last change on this file since 50653 was 50653, checked in by vboxsync, 10 years ago

Added a more recent K8 CPU to the CPU database.
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1/* $Id: CPUMR3Db.cpp 50653 2014-02-28 15:44:55Z vboxsync $ */
2/** @file
3 * CPUM - CPU database part.
4 */
5
6/*
7 * Copyright (C) 2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include "CPUMInternal.h"
24#include <VBox/vmm/vm.h>
25
26#include <VBox/err.h>
27#include <iprt/asm-amd64-x86.h>
28#include <iprt/mem.h>
29#include <iprt/string.h>
30
31
32/*******************************************************************************
33* Structures and Typedefs *
34*******************************************************************************/
35typedef struct CPUMDBENTRY
36{
37 /** The CPU name. */
38 const char *pszName;
39 /** The full CPU name. */
40 const char *pszFullName;
41 /** The CPU vendor (CPUMCPUVENDOR). */
42 uint8_t enmVendor;
43 /** The CPU family. */
44 uint8_t uFamily;
45 /** The CPU model. */
46 uint8_t uModel;
47 /** The CPU stepping. */
48 uint8_t uStepping;
49 /** The microarchitecture. */
50 CPUMMICROARCH enmMicroarch;
51 /** Scalable bus frequency used for reporting other frequencies. */
52 uint64_t uScalableBusFreq;
53 /** Flags (TBD). */
54 uint32_t fFlags;
55 /** The maximum physical address with of the CPU. This should correspond to
56 * the value in CPUID leaf 0x80000008 when present. */
57 uint8_t cMaxPhysAddrWidth;
58 /** Pointer to an array of CPUID leaves. */
59 PCCPUMCPUIDLEAF paCpuIdLeaves;
60 /** The number of CPUID leaves in the array paCpuIdLeaves points to. */
61 uint32_t cCpuIdLeaves;
62 /** The method used to deal with unknown CPUID leaves. */
63 CPUMUKNOWNCPUID enmUnknownCpuId;
64 /** The default unknown CPUID value. */
65 CPUMCPUID DefUnknownCpuId;
66
67 /** MSR mask. Several microarchitectures ignore higher bits of the */
68 uint32_t fMsrMask;
69
70 /** The number of ranges in the table pointed to b paMsrRanges. */
71 uint32_t cMsrRanges;
72 /** MSR ranges for this CPU. */
73 PCCPUMMSRRANGE paMsrRanges;
74} CPUMDBENTRY;
75
76
77/*******************************************************************************
78* Defined Constants And Macros *
79*******************************************************************************/
80
81/** @def NULL_ALONE
82 * For eliminating an unnecessary data dependency in standalone builds (for
83 * VBoxSVC). */
84/** @def ZERO_ALONE
85 * For eliminating an unnecessary data size dependency in standalone builds (for
86 * VBoxSVC). */
87#ifndef CPUM_DB_STANDALONE
88# define NULL_ALONE(a_aTable) a_aTable
89# define ZERO_ALONE(a_cTable) a_cTable
90#else
91# define NULL_ALONE(a_aTable) NULL
92# define ZERO_ALONE(a_cTable) 0
93#endif
94
95
96/** @name Short macros for the MSR range entries.
97 *
98 * These are rather cryptic, but this is to reduce the attack on the right
99 * margin.
100 *
101 * @{ */
102/** Alias one MSR onto another (a_uTarget). */
103#define MAL(a_uMsr, a_szName, a_uTarget) \
104 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
105/** Functions handles everything. */
106#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
107 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
108/** Functions handles everything, with GP mask. */
109#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
110 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
111/** Function handlers, read-only. */
112#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
113 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
114/** Function handlers, ignore all writes. */
115#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
116 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
117/** Function handlers, with value. */
118#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
119 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
120/** Function handlers, with write ignore mask. */
121#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
122 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
123/** Function handlers, extended version. */
124#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
125 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
126/** Function handlers, with CPUMCPU storage variable. */
127#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
128 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
129 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
130/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
131#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
132 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
133 RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
134/** Read-only fixed value. */
135#define MVO(a_uMsr, a_szName, a_uValue) \
136 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
137/** Read-only fixed value, ignores all writes. */
138#define MVI(a_uMsr, a_szName, a_uValue) \
139 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
140/** Read fixed value, ignore writes outside GP mask. */
141#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
142 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
143/** Read fixed value, extended version with both GP and ignore masks. */
144#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
145 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
146/** The short form, no CPUM backing. */
147#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
148 RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
149 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
150
151/** Range: Functions handles everything. */
152#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
153 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
154/** Range: Read fixed value, read-only. */
155#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
156 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
157/** Range: Read fixed value, ignore writes. */
158#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
159 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
160/** Range: The short form, no CPUM backing. */
161#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
162 RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
163 a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
164
165/** Internal form used by the macros. */
166#ifdef VBOX_WITH_STATISTICS
167# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
168 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
169 { 0 }, { 0 }, { 0 }, { 0 } }
170#else
171# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
172 { a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
173#endif
174/** @} */
175
176
177#include "cpus/Intel_Core_i7_3960X.h"
178#include "cpus/Intel_Core_i5_3570.h"
179#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
180#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
181#include "cpus/Intel_Pentium_4_3_00GHz.h"
182
183#include "cpus/AMD_FX_8150_Eight_Core.h"
184#include "cpus/AMD_Phenom_II_X6_1100T.h"
185#include "cpus/Quad_Core_AMD_Opteron_2384.h"
186#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
187#include "cpus/AMD_Athlon_64_3200.h"
188
189#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
190
191
192
193/**
194 * The database entries.
195 *
196 * 1. The first entry is special. It is the fallback for unknown
197 * processors. Thus, it better be pretty representative.
198 *
199 * 2. The first entry for a CPU vendor is likewise important as it is
200 * the default entry for that vendor.
201 *
202 * Generally we put the most recent CPUs first, since these tend to have the
203 * most complicated and backwards compatible list of MSRs.
204 */
205static CPUMDBENTRY const * const g_apCpumDbEntries[] =
206{
207#ifdef VBOX_CPUDB_Intel_Core_i5_3570
208 &g_Entry_Intel_Core_i5_3570,
209#endif
210#ifdef VBOX_CPUDB_Intel_Core_i7_3960X
211 &g_Entry_Intel_Core_i7_3960X,
212#endif
213#ifdef Intel_Pentium_M_processor_2_00GHz
214 &g_Entry_Intel_Pentium_M_processor_2_00GHz,
215#endif
216#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz
217 &g_Entry_Intel_Xeon_X5482_3_20GHz,
218#endif
219#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz
220 &g_Entry_Intel_Pentium_4_3_00GHz,
221#endif
222
223#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core
224 &g_Entry_AMD_FX_8150_Eight_Core,
225#endif
226#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T
227 &g_Entry_AMD_Phenom_II_X6_1100T,
228#endif
229#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384
230 &g_Entry_Quad_Core_AMD_Opteron_2384,
231#endif
232#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200
233 &g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
234#endif
235#ifdef VBOX_CPUDB_AMD_Athlon_64_3200
236 &g_Entry_AMD_Athlon_64_3200,
237#endif
238
239#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz
240 &g_Entry_VIA_QuadCore_L4700_1_2_GHz,
241#endif
242};
243
244
245#ifndef CPUM_DB_STANDALONE
246
247/**
248 * Binary search used by cpumR3MsrRangesInsert and has some special properties
249 * wrt to mismatches.
250 *
251 * @returns Insert location.
252 * @param paMsrRanges The MSR ranges to search.
253 * @param cMsrRanges The number of MSR ranges.
254 * @param uMsr What to search for.
255 */
256static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
257{
258 if (!cMsrRanges)
259 return 0;
260
261 uint32_t iStart = 0;
262 uint32_t iLast = cMsrRanges - 1;
263 for (;;)
264 {
265 uint32_t i = iStart + (iLast - iStart + 1) / 2;
266 if ( uMsr >= paMsrRanges[i].uFirst
267 && uMsr <= paMsrRanges[i].uLast)
268 return i;
269 if (uMsr < paMsrRanges[i].uFirst)
270 {
271 if (i <= iStart)
272 return i;
273 iLast = i - 1;
274 }
275 else
276 {
277 if (i >= iLast)
278 {
279 if (i < cMsrRanges)
280 i++;
281 return i;
282 }
283 iStart = i + 1;
284 }
285 }
286}
287
288
289/**
290 * Ensures that there is space for at least @a cNewRanges in the table,
291 * reallocating the table if necessary.
292 *
293 * @returns Pointer to the MSR ranges on success, NULL on failure. On failure
294 * @a *ppaMsrRanges is freed and set to NULL.
295 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
296 * @param cMsrRanges The current number of ranges.
297 * @param cNewRanges The number of ranges to be added.
298 */
299static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
300{
301 uint32_t cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
302 if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
303 {
304 uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
305 void *pvNew = RTMemRealloc(*ppaMsrRanges, cNew * sizeof(**ppaMsrRanges));
306 if (!pvNew)
307 {
308 RTMemFree(*ppaMsrRanges);
309 *ppaMsrRanges = NULL;
310 return NULL;
311 }
312 *ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
313 }
314 return *ppaMsrRanges;
315}
316
317
318/**
319 * Inserts a new MSR range in into an sorted MSR range array.
320 *
321 * If the new MSR range overlaps existing ranges, the existing ones will be
322 * adjusted/removed to fit in the new one.
323 *
324 * @returns VBox status code.
325 * @retval VINF_SUCCESS
326 * @retval VERR_NO_MEMORY
327 *
328 * @param ppaMsrRanges The variable pointing to the ranges (input/output).
329 * @param pcMsrRanges The variable holding number of ranges.
330 * @param pNewRange The new range.
331 */
332int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange)
333{
334 uint32_t cMsrRanges = *pcMsrRanges;
335 PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
336
337 Assert(pNewRange->uLast >= pNewRange->uFirst);
338 Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
339 Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
340
341 /*
342 * Optimize the linear insertion case where we add new entries at the end.
343 */
344 if ( cMsrRanges > 0
345 && paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
346 {
347 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
348 if (!paMsrRanges)
349 return VERR_NO_MEMORY;
350 paMsrRanges[cMsrRanges] = *pNewRange;
351 *pcMsrRanges += 1;
352 }
353 else
354 {
355 uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
356 Assert(i == cMsrRanges || pNewRange->uFirst <= paMsrRanges[i].uLast);
357 Assert(i == 0 || pNewRange->uFirst > paMsrRanges[i - 1].uLast);
358
359 /*
360 * Adding an entirely new entry?
361 */
362 if ( i >= cMsrRanges
363 || pNewRange->uLast < paMsrRanges[i].uFirst)
364 {
365 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
366 if (!paMsrRanges)
367 return VERR_NO_MEMORY;
368 if (i < cMsrRanges)
369 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
370 paMsrRanges[i] = *pNewRange;
371 *pcMsrRanges += 1;
372 }
373 /*
374 * Replace existing entry?
375 */
376 else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
377 && pNewRange->uLast == paMsrRanges[i].uLast)
378 paMsrRanges[i] = *pNewRange;
379 /*
380 * Splitting an existing entry?
381 */
382 else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
383 && pNewRange->uLast < paMsrRanges[i].uLast)
384 {
385 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 2);
386 if (!paMsrRanges)
387 return VERR_NO_MEMORY;
388 if (i < cMsrRanges)
389 memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
390 paMsrRanges[i + 1] = *pNewRange;
391 paMsrRanges[i + 2] = paMsrRanges[i];
392 paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
393 paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
394 *pcMsrRanges += 2;
395 }
396 /*
397 * Complicated scenarios that can affect more than one range.
398 *
399 * The current code does not optimize memmove calls when replacing
400 * one or more existing ranges, because it's tedious to deal with and
401 * not expected to be a frequent usage scenario.
402 */
403 else
404 {
405 /* Adjust start of first match? */
406 if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
407 && pNewRange->uLast < paMsrRanges[i].uLast)
408 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
409 else
410 {
411 /* Adjust end of first match? */
412 if (pNewRange->uFirst > paMsrRanges[i].uFirst)
413 {
414 Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
415 paMsrRanges[i].uLast = pNewRange->uFirst - 1;
416 i++;
417 }
418 /* Replace the whole first match (lazy bird). */
419 else
420 {
421 if (i + 1 < cMsrRanges)
422 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
423 cMsrRanges = *pcMsrRanges -= 1;
424 }
425
426 /* Do the new range affect more ranges? */
427 while ( i < cMsrRanges
428 && pNewRange->uLast >= paMsrRanges[i].uFirst)
429 {
430 if (pNewRange->uLast < paMsrRanges[i].uLast)
431 {
432 /* Adjust the start of it, then we're done. */
433 paMsrRanges[i].uFirst = pNewRange->uLast + 1;
434 break;
435 }
436
437 /* Remove it entirely. */
438 if (i + 1 < cMsrRanges)
439 memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
440 cMsrRanges = *pcMsrRanges -= 1;
441 }
442 }
443
444 /* Now, perform a normal insertion. */
445 paMsrRanges = cpumR3MsrRangesEnsureSpace(ppaMsrRanges, cMsrRanges, 1);
446 if (!paMsrRanges)
447 return VERR_NO_MEMORY;
448 if (i < cMsrRanges)
449 memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
450 paMsrRanges[i] = *pNewRange;
451 *pcMsrRanges += 1;
452 }
453 }
454
455 return VINF_SUCCESS;
456}
457
458
459/**
460 * Worker for cpumR3MsrApplyFudge that applies one table.
461 *
462 * @returns VBox status code.
463 * @param pVM Pointer to the cross context VM structure.
464 * @param paRanges Array of MSRs to fudge.
465 * @param cRanges Number of MSRs in the array.
466 */
467static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
468{
469 for (uint32_t i = 0; i < cRanges; i++)
470 if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
471 {
472 LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
473 int rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
474 &paRanges[i]);
475 if (RT_FAILURE(rc))
476 return rc;
477 }
478 return VINF_SUCCESS;
479}
480
481
482/**
483 * Fudges the MSRs that guest are known to access in some odd cases.
484 *
485 * A typical example is a VM that has been moved between different hosts where
486 * for instance the cpu vendor differs.
487 *
488 * @returns VBox status code.
489 * @param pVM Pointer to the cross context VM structure.
490 */
491int cpumR3MsrApplyFudge(PVM pVM)
492{
493 /*
494 * Basic.
495 */
496 static CPUMMSRRANGE const s_aFudgeMsrs[] =
497 {
498 MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
499 MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
500 MVO(0x00000017, "IA32_PLATFORM_ID", 0),
501 MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
502 MVI(0x0000008b, "BIOS_SIGN", 0),
503 MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
504 MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
505 MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
506 MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
507 MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
508 MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
509 MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
510 MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
511 MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
512 MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
513 MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
514 MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
515 };
516 int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
517 AssertLogRelRCReturn(rc, rc);
518
519 /*
520 * XP might mistake opterons and other newer CPUs for P4s.
521 */
522 if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
523 {
524 static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
525 {
526 MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
527 };
528 rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
529 AssertLogRelRCReturn(rc, rc);
530 }
531
532 return rc;
533}
534
535
536int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
537{
538 CPUMDBENTRY const *pEntry = NULL;
539 int rc;
540
541 if (!strcmp(pszName, "host"))
542 {
543 /*
544 * Create a CPU database entry for the host CPU. This means getting
545 * the CPUID bits from the real CPU and grabbing the closest matching
546 * database entry for MSRs.
547 */
548 rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
549 if (RT_FAILURE(rc))
550 return rc;
551 rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
552 if (RT_FAILURE(rc))
553 return rc;
554
555 /* Lookup database entry for MSRs. */
556 CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
557 pInfo->paCpuIdLeavesR3[0].uEbx,
558 pInfo->paCpuIdLeavesR3[0].uEcx,
559 pInfo->paCpuIdLeavesR3[0].uEdx);
560 uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
561 uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
562 uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
563 uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
564 CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
565
566 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
567 {
568 CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
569 if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
570 {
571 /* Match against Family, Microarch, model and stepping. Except
572 for family, always match the closer with preference given to
573 the later/older ones. */
574 if (pCur->uFamily == uFamily)
575 {
576 if (pCur->enmMicroarch == enmMicroarch)
577 {
578 if (pCur->uModel == uModel)
579 {
580 if (pCur->uStepping == uStepping)
581 {
582 /* Perfect match. */
583 pEntry = pCur;
584 break;
585 }
586
587 if ( !pEntry
588 || pEntry->uModel != uModel
589 || pEntry->enmMicroarch != enmMicroarch
590 || pEntry->uFamily != uFamily)
591 pEntry = pCur;
592 else if ( pCur->uStepping >= uStepping
593 ? pCur->uStepping < pEntry->uStepping || pEntry->uStepping < uStepping
594 : pCur->uStepping > pEntry->uStepping)
595 pEntry = pCur;
596 }
597 else if ( !pEntry
598 || pEntry->enmMicroarch != enmMicroarch
599 || pEntry->uFamily != uFamily)
600 pEntry = pCur;
601 else if ( pCur->uModel >= uModel
602 ? pCur->uModel < pEntry->uModel || pEntry->uModel < uModel
603 : pCur->uModel > pEntry->uModel)
604 pEntry = pCur;
605 }
606 else if ( !pEntry
607 || pEntry->uFamily != uFamily)
608 pEntry = pCur;
609 else if ( pCur->enmMicroarch >= enmMicroarch
610 ? pCur->enmMicroarch < pEntry->enmMicroarch || pEntry->enmMicroarch < enmMicroarch
611 : pCur->enmMicroarch > pEntry->enmMicroarch)
612 pEntry = pCur;
613 }
614 /* We don't do closeness matching on family, we use the first
615 entry for the CPU vendor instead. (P4 workaround.) */
616 else if (!pEntry)
617 pEntry = pCur;
618 }
619 }
620
621 if (pEntry)
622 LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
623 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
624 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
625 pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
626 else
627 {
628 pEntry = g_apCpumDbEntries[0];
629 LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'.\n",
630 CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
631 pEntry->pszName));
632 }
633 }
634 else
635 {
636 /*
637 * We're supposed to be emulating a specific CPU that is included in
638 * our CPU database. The CPUID tables needs to be copied onto the
639 * heap so the caller can modify them and so they can be freed like
640 * in the host case above.
641 */
642 for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
643 if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
644 {
645 pEntry = g_apCpumDbEntries[i];
646 break;
647 }
648 if (!pEntry)
649 {
650 LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
651 return VERR_CPUM_DB_CPU_NOT_FOUND;
652 }
653
654 pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
655 if (pEntry->cCpuIdLeaves)
656 {
657 pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDup(pEntry->paCpuIdLeaves,
658 sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves);
659 if (!pInfo->paCpuIdLeavesR3)
660 return VERR_NO_MEMORY;
661 }
662 else
663 pInfo->paCpuIdLeavesR3 = NULL;
664
665 pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
666 pInfo->DefCpuId = pEntry->DefUnknownCpuId;
667
668 LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s).\n",
669 pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
670 pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
671 }
672
673 pInfo->fMsrMask = pEntry->fMsrMask;
674 pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
675 pInfo->uPadding = 0;
676 pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
677 pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
678 pInfo->paMsrRangesR0 = NIL_RTR0PTR;
679 pInfo->paCpuIdLeavesRC = NIL_RTRCPTR;
680 pInfo->paMsrRangesRC = NIL_RTRCPTR;
681
682 /*
683 * Copy the MSR range.
684 */
685 uint32_t cMsrs = 0;
686 PCPUMMSRRANGE paMsrs = NULL;
687
688 PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
689 uint32_t cLeft = pEntry->cMsrRanges;
690 while (cLeft-- > 0)
691 {
692 rc = cpumR3MsrRangesInsert(&paMsrs, &cMsrs, pCurMsr);
693 if (RT_FAILURE(rc))
694 {
695 Assert(!paMsrs); /* The above function frees this. */
696 RTMemFree(pInfo->paCpuIdLeavesR3);
697 pInfo->paCpuIdLeavesR3 = NULL;
698 return rc;
699 }
700 pCurMsr++;
701 }
702
703 pInfo->paMsrRangesR3 = paMsrs;
704 pInfo->cMsrRanges = cMsrs;
705 return VINF_SUCCESS;
706}
707
708
709/**
710 * Register statistics for the MSRs.
711 *
712 * This must not be called before the MSRs have been finalized and moved to the
713 * hyper heap.
714 *
715 * @returns VBox status code.
716 * @param pVM Pointer to the cross context VM structure.
717 */
718int cpumR3MsrRegStats(PVM pVM)
719{
720 /*
721 * Global statistics.
722 */
723 PCPUM pCpum = &pVM->cpum.s;
724 STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
725 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
726 STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
727 STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
728 STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
729 STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
730 STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
731 STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
732 STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
733 STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
734 STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
735 STAMUNIT_OCCURENCES, "Writing of ignored bits.");
736 STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
737 STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
738
739
740# ifdef VBOX_WITH_STATISTICS
741 /*
742 * Per range.
743 */
744 PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
745 uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
746 for (uint32_t i = 0; i < cRanges; i++)
747 {
748 char szName[160];
749 ssize_t cchName;
750
751 if (paRanges[i].uFirst == paRanges[i].uLast)
752 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
753 paRanges[i].uFirst, paRanges[i].szName);
754 else
755 cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
756 paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
757
758 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
759 STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
760
761 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
762 STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
763
764 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
765 STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
766
767 RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
768 STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
769 }
770# endif /* VBOX_WITH_STATISTICS */
771
772 return VINF_SUCCESS;
773}
774
775#endif /* !CPUM_DB_STANDALONE */
776
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