VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp@ 50653

Last change on this file since 50653 was 50607, checked in by vboxsync, 10 years ago

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1/* $Id: CPUMR3CpuId.cpp 50607 2014-02-26 14:06:40Z vboxsync $ */
2/** @file
3 * CPUM - CPU ID part.
4 */
5
6/*
7 * Copyright (C) 2013-2014 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_CPUM
22#include <VBox/vmm/cpum.h>
23#include "CPUMInternal.h"
24#include <VBox/vmm/vm.h>
25
26#include <VBox/err.h>
27#include <iprt/asm-amd64-x86.h>
28#include <iprt/ctype.h>
29#include <iprt/mem.h>
30#include <iprt/string.h>
31
32
33/*******************************************************************************
34* Global Variables *
35*******************************************************************************/
36/**
37 * The intel pentium family.
38 */
39static const CPUMMICROARCH g_aenmIntelFamily06[] =
40{
41 /* [ 0(0x00)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro A-step (says sandpile.org). */
42 /* [ 1(0x01)] = */ kCpumMicroarch_Intel_P6, /* Pentium Pro */
43 /* [ 2(0x02)] = */ kCpumMicroarch_Intel_Unknown,
44 /* [ 3(0x03)] = */ kCpumMicroarch_Intel_P6_II, /* PII Klamath */
45 /* [ 4(0x04)] = */ kCpumMicroarch_Intel_Unknown,
46 /* [ 5(0x05)] = */ kCpumMicroarch_Intel_P6_II, /* PII Deschutes */
47 /* [ 6(0x06)] = */ kCpumMicroarch_Intel_P6_II, /* Celeron Mendocino. */
48 /* [ 7(0x07)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Katmai. */
49 /* [ 8(0x08)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Coppermine (includes Celeron). */
50 /* [ 9(0x09)] = */ kCpumMicroarch_Intel_P6_M_Banias, /* Pentium/Celeron M Banias. */
51 /* [10(0x0a)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Xeon */
52 /* [11(0x0b)] = */ kCpumMicroarch_Intel_P6_III, /* PIII Tualatin (includes Celeron). */
53 /* [12(0x0c)] = */ kCpumMicroarch_Intel_Unknown,
54 /* [13(0x0d)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Pentium/Celeron M Dothan. */
55 /* [14(0x0e)] = */ kCpumMicroarch_Intel_Core_Yonah, /* Core Yonah (Enhanced Pentium M). */
56 /* [15(0x0f)] = */ kCpumMicroarch_Intel_Core2_Merom, /* Merom */
57 /* [16(0x10)] = */ kCpumMicroarch_Intel_Unknown,
58 /* [17(0x11)] = */ kCpumMicroarch_Intel_Unknown,
59 /* [18(0x12)] = */ kCpumMicroarch_Intel_Unknown,
60 /* [19(0x13)] = */ kCpumMicroarch_Intel_Unknown,
61 /* [20(0x14)] = */ kCpumMicroarch_Intel_Unknown,
62 /* [21(0x15)] = */ kCpumMicroarch_Intel_P6_M_Dothan, /* Tolapai - System-on-a-chip. */
63 /* [22(0x16)] = */ kCpumMicroarch_Intel_Core2_Merom,
64 /* [23(0x17)] = */ kCpumMicroarch_Intel_Core2_Penryn,
65 /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
66 /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
67 /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
68 /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
69 /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
70 /* [29(0x1d)] = */ kCpumMicroarch_Intel_Core2_Penryn,
71 /* [30(0x1e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Clarksfield, Lynnfield, Jasper Forest. */
72 /* [31(0x1f)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Only listed by sandpile.org. 2 cores ABD/HVD, whatever that means. */
73 /* [32(0x20)] = */ kCpumMicroarch_Intel_Unknown,
74 /* [33(0x21)] = */ kCpumMicroarch_Intel_Unknown,
75 /* [34(0x22)] = */ kCpumMicroarch_Intel_Unknown,
76 /* [35(0x23)] = */ kCpumMicroarch_Intel_Unknown,
77 /* [36(0x24)] = */ kCpumMicroarch_Intel_Unknown,
78 /* [37(0x25)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Arrandale, Clarksdale. */
79 /* [38(0x26)] = */ kCpumMicroarch_Intel_Atom_Lincroft,
80 /* [39(0x27)] = */ kCpumMicroarch_Intel_Atom_Saltwell,
81 /* [40(0x28)] = */ kCpumMicroarch_Intel_Unknown,
82 /* [41(0x29)] = */ kCpumMicroarch_Intel_Unknown,
83 /* [42(0x2a)] = */ kCpumMicroarch_Intel_Core7_SandyBridge,
84 /* [43(0x2b)] = */ kCpumMicroarch_Intel_Unknown,
85 /* [44(0x2c)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Gulftown, Westmere-EP. */
86 /* [45(0x2d)] = */ kCpumMicroarch_Intel_Core7_SandyBridge, /* SandyBridge-E, SandyBridge-EN, SandyBridge-EP. */
87 /* [46(0x2e)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Beckton (Xeon). */
88 /* [47(0x2f)] = */ kCpumMicroarch_Intel_Core7_Westmere, /* Westmere-EX. */
89 /* [48(0x30)] = */ kCpumMicroarch_Intel_Unknown,
90 /* [49(0x31)] = */ kCpumMicroarch_Intel_Unknown,
91 /* [50(0x32)] = */ kCpumMicroarch_Intel_Unknown,
92 /* [51(0x33)] = */ kCpumMicroarch_Intel_Unknown,
93 /* [52(0x34)] = */ kCpumMicroarch_Intel_Unknown,
94 /* [53(0x35)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* ?? */
95 /* [54(0x36)] = */ kCpumMicroarch_Intel_Atom_Saltwell, /* Cedarview, ++ */
96 /* [55(0x37)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
97 /* [56(0x38)] = */ kCpumMicroarch_Intel_Unknown,
98 /* [57(0x39)] = */ kCpumMicroarch_Intel_Unknown,
99 /* [58(0x3a)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
100 /* [59(0x3b)] = */ kCpumMicroarch_Intel_Unknown,
101 /* [60(0x3c)] = */ kCpumMicroarch_Intel_Core7_Haswell,
102 /* [61(0x3d)] = */ kCpumMicroarch_Intel_Core7_Broadwell,
103 /* [62(0x3e)] = */ kCpumMicroarch_Intel_Core7_IvyBridge,
104 /* [63(0x3f)] = */ kCpumMicroarch_Intel_Core7_Haswell,
105 /* [64(0x40)] = */ kCpumMicroarch_Intel_Unknown,
106 /* [65(0x41)] = */ kCpumMicroarch_Intel_Unknown,
107 /* [66(0x42)] = */ kCpumMicroarch_Intel_Unknown,
108 /* [67(0x43)] = */ kCpumMicroarch_Intel_Unknown,
109 /* [68(0x44)] = */ kCpumMicroarch_Intel_Unknown,
110 /* [69(0x45)] = */ kCpumMicroarch_Intel_Core7_Haswell,
111 /* [70(0x46)] = */ kCpumMicroarch_Intel_Core7_Haswell,
112 /* [71(0x47)] = */ kCpumMicroarch_Intel_Unknown,
113 /* [72(0x48)] = */ kCpumMicroarch_Intel_Unknown,
114 /* [73(0x49)] = */ kCpumMicroarch_Intel_Unknown,
115 /* [74(0x4a)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
116 /* [75(0x4b)] = */ kCpumMicroarch_Intel_Unknown,
117 /* [76(0x4c)] = */ kCpumMicroarch_Intel_Unknown,
118 /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
119 /* [78(0x4e)] = */ kCpumMicroarch_Intel_Unknown,
120 /* [79(0x4f)] = */ kCpumMicroarch_Intel_Unknown,
121};
122
123
124
125/**
126 * Figures out the (sub-)micro architecture given a bit of CPUID info.
127 *
128 * @returns Micro architecture.
129 * @param enmVendor The CPU vendor .
130 * @param bFamily The CPU family.
131 * @param bModel The CPU model.
132 * @param bStepping The CPU stepping.
133 */
134VMMR3DECL(CPUMMICROARCH) CPUMR3CpuIdDetermineMicroarchEx(CPUMCPUVENDOR enmVendor, uint8_t bFamily,
135 uint8_t bModel, uint8_t bStepping)
136{
137 if (enmVendor == CPUMCPUVENDOR_AMD)
138 {
139 switch (bFamily)
140 {
141 case 0x02: return kCpumMicroarch_AMD_Am286; /* Not really kosher... */
142 case 0x03: return kCpumMicroarch_AMD_Am386;
143 case 0x23: return kCpumMicroarch_AMD_Am386; /* SX*/
144 case 0x04: return bModel < 14 ? kCpumMicroarch_AMD_Am486 : kCpumMicroarch_AMD_Am486Enh;
145 case 0x05: return bModel < 6 ? kCpumMicroarch_AMD_K5 : kCpumMicroarch_AMD_K6; /* Genode LX is 0x0a, lump it with K6. */
146 case 0x06:
147 switch (bModel)
148 {
149 case 0: kCpumMicroarch_AMD_K7_Palomino;
150 case 1: kCpumMicroarch_AMD_K7_Palomino;
151 case 2: kCpumMicroarch_AMD_K7_Palomino;
152 case 3: kCpumMicroarch_AMD_K7_Spitfire;
153 case 4: kCpumMicroarch_AMD_K7_Thunderbird;
154 case 6: kCpumMicroarch_AMD_K7_Palomino;
155 case 7: kCpumMicroarch_AMD_K7_Morgan;
156 case 8: kCpumMicroarch_AMD_K7_Thoroughbred;
157 case 10: kCpumMicroarch_AMD_K7_Barton; /* Thorton too. */
158 }
159 return kCpumMicroarch_AMD_K7_Unknown;
160 case 0x0f:
161 /*
162 * This family is a friggin mess. Trying my best to make some
163 * sense out of it. Too much happened in the 0x0f family to
164 * lump it all together as K8 (130nm->90nm->65nm, AMD-V, ++).
165 *
166 * Emperical CPUID.01h.EAX evidence from revision guides, wikipedia,
167 * cpu-world.com, and other places:
168 * - 130nm:
169 * - ClawHammer: F7A/SH-CG, F5A/-CG, F4A/-CG, F50/-B0, F48/-C0, F58/-C0,
170 * - SledgeHammer: F50/SH-B0, F48/-C0, F58/-C0, F4A/-CG, F5A/-CG, F7A/-CG, F51/-B3
171 * - Newcastle: FC0/DH-CG (errum #180: FE0/DH-CG), FF0/DH-CG
172 * - Dublin: FC0/-CG, FF0/-CG, F82/CH-CG, F4A/-CG, F48/SH-C0,
173 * - Odessa: FC0/DH-CG (errum #180: FE0/DH-CG)
174 * - Paris: FF0/DH-CG, FC0/DH-CG (errum #180: FE0/DH-CG),
175 * - 90nm:
176 * - Winchester: 10FF0/DH-D0, 20FF0/DH-E3.
177 * - Oakville: 10FC0/DH-D0.
178 * - Georgetown: 10FC0/DH-D0.
179 * - Sonora: 10FC0/DH-D0.
180 * - Venus: 20F71/SH-E4
181 * - Troy: 20F51/SH-E4
182 * - Athens: 20F51/SH-E4
183 * - San Diego: 20F71/SH-E4.
184 * - Lancaster: 20F42/SH-E5
185 * - Newark: 20F42/SH-E5.
186 * - Albany: 20FC2/DH-E6.
187 * - Roma: 20FC2/DH-E6.
188 * - Venice: 20FF0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6.
189 * - Palermo: 10FC0/DH-D0, 20FF0/DH-E3, 20FC0/DH-E3, 20FC2/DH-E6, 20FF2/DH-E6
190 * - 90nm introducing Dual core:
191 * - Denmark: 20F30/JH-E1, 20F32/JH-E6
192 * - Italy: 20F10/JH-E1, 20F12/JH-E6
193 * - Egypt: 20F10/JH-E1, 20F12/JH-E6
194 * - Toledo: 20F32/JH-E6, 30F72/DH-E6 (single code variant).
195 * - Manchester: 20FB1/BH-E4, 30FF2/BH-E4.
196 * - 90nm 2nd gen opteron ++, AMD-V introduced (might be missing in some cheeper models):
197 * - Santa Ana: 40F32/JH-F2, /-F3
198 * - Santa Rosa: 40F12/JH-F2, 40F13/JH-F3
199 * - Windsor: 40F32/JH-F2, 40F33/JH-F3, C0F13/JH-F3, 40FB2/BH-F2, ??20FB1/BH-E4??.
200 * - Manila: 50FF2/DH-F2, 40FF2/DH-F2
201 * - Orleans: 40FF2/DH-F2, 50FF2/DH-F2, 50FF3/DH-F3.
202 * - Keene: 40FC2/DH-F2.
203 * - Richmond: 40FC2/DH-F2
204 * - Taylor: 40F82/BH-F2
205 * - Trinidad: 40F82/BH-F2
206 *
207 * - 65nm:
208 * - Brisbane: 60FB1/BH-G1, 60FB2/BH-G2.
209 * - Tyler: 60F81/BH-G1, 60F82/BH-G2.
210 * - Sparta: 70FF1/DH-G1, 70FF2/DH-G2.
211 * - Lima: 70FF1/DH-G1, 70FF2/DH-G2.
212 * - Sherman: /-G1, 70FC2/DH-G2.
213 * - Huron: 70FF2/DH-G2.
214 */
215 if (bModel < 0x10)
216 return kCpumMicroarch_AMD_K8_130nm;
217 if (bModel >= 0x60 && bModel < 0x80)
218 return kCpumMicroarch_AMD_K8_65nm;
219 if (bModel >= 0x40)
220 return kCpumMicroarch_AMD_K8_90nm_AMDV;
221 switch (bModel)
222 {
223 case 0x21:
224 case 0x23:
225 case 0x2b:
226 case 0x2f:
227 case 0x37:
228 case 0x3f:
229 return kCpumMicroarch_AMD_K8_90nm_DualCore;
230 }
231 return kCpumMicroarch_AMD_K8_90nm;
232 case 0x10:
233 return kCpumMicroarch_AMD_K10;
234 case 0x11:
235 return kCpumMicroarch_AMD_K10_Lion;
236 case 0x12:
237 return kCpumMicroarch_AMD_K10_Llano;
238 case 0x14:
239 return kCpumMicroarch_AMD_Bobcat;
240 case 0x15:
241 switch (bModel)
242 {
243 case 0x00: return kCpumMicroarch_AMD_15h_Bulldozer; /* Any? prerelease? */
244 case 0x01: return kCpumMicroarch_AMD_15h_Bulldozer; /* Opteron 4200, FX-81xx. */
245 case 0x02: return kCpumMicroarch_AMD_15h_Piledriver; /* Opteron 4300, FX-83xx. */
246 case 0x10: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-5800K for e.g. */
247 case 0x11: /* ?? */
248 case 0x12: /* ?? */
249 case 0x13: return kCpumMicroarch_AMD_15h_Piledriver; /* A10-6800K for e.g. */
250 }
251 return kCpumMicroarch_AMD_15h_Unknown;
252 case 0x16:
253 return kCpumMicroarch_AMD_Jaguar;
254
255 }
256 return kCpumMicroarch_AMD_Unknown;
257 }
258
259 if (enmVendor == CPUMCPUVENDOR_INTEL)
260 {
261 switch (bFamily)
262 {
263 case 3:
264 return kCpumMicroarch_Intel_80386;
265 case 4:
266 return kCpumMicroarch_Intel_80486;
267 case 5:
268 return kCpumMicroarch_Intel_P5;
269 case 6:
270 if (bModel < RT_ELEMENTS(g_aenmIntelFamily06))
271 return g_aenmIntelFamily06[bModel];
272 return kCpumMicroarch_Intel_Atom_Unknown;
273 case 15:
274 switch (bModel)
275 {
276 case 0: return kCpumMicroarch_Intel_NB_Willamette;
277 case 1: return kCpumMicroarch_Intel_NB_Willamette;
278 case 2: return kCpumMicroarch_Intel_NB_Northwood;
279 case 3: return kCpumMicroarch_Intel_NB_Prescott;
280 case 4: return kCpumMicroarch_Intel_NB_Prescott2M; /* ?? */
281 case 5: return kCpumMicroarch_Intel_NB_Unknown; /*??*/
282 case 6: return kCpumMicroarch_Intel_NB_CedarMill;
283 case 7: return kCpumMicroarch_Intel_NB_Gallatin;
284 default: return kCpumMicroarch_Intel_NB_Unknown;
285 }
286 break;
287 /* The following are not kosher but kind of follow intuitively from 6, 5 & 4. */
288 case 1:
289 return kCpumMicroarch_Intel_8086;
290 case 2:
291 return kCpumMicroarch_Intel_80286;
292 }
293 return kCpumMicroarch_Intel_Unknown;
294 }
295
296 if (enmVendor == CPUMCPUVENDOR_VIA)
297 {
298 switch (bFamily)
299 {
300 case 5:
301 switch (bModel)
302 {
303 case 1: return kCpumMicroarch_Centaur_C6;
304 case 4: return kCpumMicroarch_Centaur_C6;
305 case 8: return kCpumMicroarch_Centaur_C2;
306 case 9: return kCpumMicroarch_Centaur_C3;
307 }
308 break;
309
310 case 6:
311 switch (bModel)
312 {
313 case 5: return kCpumMicroarch_VIA_C3_M2;
314 case 6: return kCpumMicroarch_VIA_C3_C5A;
315 case 7: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5B : kCpumMicroarch_VIA_C3_C5C;
316 case 8: return kCpumMicroarch_VIA_C3_C5N;
317 case 9: return bStepping < 8 ? kCpumMicroarch_VIA_C3_C5XL : kCpumMicroarch_VIA_C3_C5P;
318 case 10: return kCpumMicroarch_VIA_C7_C5J;
319 case 15: return kCpumMicroarch_VIA_Isaiah;
320 }
321 break;
322 }
323 return kCpumMicroarch_VIA_Unknown;
324 }
325
326 if (enmVendor == CPUMCPUVENDOR_CYRIX)
327 {
328 switch (bFamily)
329 {
330 case 4:
331 switch (bModel)
332 {
333 case 9: return kCpumMicroarch_Cyrix_5x86;
334 }
335 break;
336
337 case 5:
338 switch (bModel)
339 {
340 case 2: return kCpumMicroarch_Cyrix_M1;
341 case 4: return kCpumMicroarch_Cyrix_MediaGX;
342 case 5: return kCpumMicroarch_Cyrix_MediaGXm;
343 }
344 break;
345
346 case 6:
347 switch (bModel)
348 {
349 case 0: return kCpumMicroarch_Cyrix_M2;
350 }
351 break;
352
353 }
354 return kCpumMicroarch_Cyrix_Unknown;
355 }
356
357 return kCpumMicroarch_Unknown;
358}
359
360
361/**
362 * Translates a microarchitecture enum value to the corresponding string
363 * constant.
364 *
365 * @returns Read-only string constant (omits "kCpumMicroarch_" prefix). Returns
366 * NULL if the value is invalid.
367 *
368 * @param enmMicroarch The enum value to convert.
369 */
370VMMR3DECL(const char *) CPUMR3MicroarchName(CPUMMICROARCH enmMicroarch)
371{
372 switch (enmMicroarch)
373 {
374#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("kCpumMicroarch_") - 1)
375 CASE_RET_STR(kCpumMicroarch_Intel_8086);
376 CASE_RET_STR(kCpumMicroarch_Intel_80186);
377 CASE_RET_STR(kCpumMicroarch_Intel_80286);
378 CASE_RET_STR(kCpumMicroarch_Intel_80386);
379 CASE_RET_STR(kCpumMicroarch_Intel_80486);
380 CASE_RET_STR(kCpumMicroarch_Intel_P5);
381
382 CASE_RET_STR(kCpumMicroarch_Intel_P6);
383 CASE_RET_STR(kCpumMicroarch_Intel_P6_II);
384 CASE_RET_STR(kCpumMicroarch_Intel_P6_III);
385
386 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Banias);
387 CASE_RET_STR(kCpumMicroarch_Intel_P6_M_Dothan);
388 CASE_RET_STR(kCpumMicroarch_Intel_Core_Yonah);
389
390 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Merom);
391 CASE_RET_STR(kCpumMicroarch_Intel_Core2_Penryn);
392
393 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Nehalem);
394 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Westmere);
395 CASE_RET_STR(kCpumMicroarch_Intel_Core7_SandyBridge);
396 CASE_RET_STR(kCpumMicroarch_Intel_Core7_IvyBridge);
397 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Haswell);
398 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Broadwell);
399 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Skylake);
400 CASE_RET_STR(kCpumMicroarch_Intel_Core7_Cannonlake);
401
402 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Bonnell);
403 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Lincroft);
404 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Saltwell);
405 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Silvermont);
406 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Airmount);
407 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Goldmont);
408 CASE_RET_STR(kCpumMicroarch_Intel_Atom_Unknown);
409
410 CASE_RET_STR(kCpumMicroarch_Intel_NB_Willamette);
411 CASE_RET_STR(kCpumMicroarch_Intel_NB_Northwood);
412 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott);
413 CASE_RET_STR(kCpumMicroarch_Intel_NB_Prescott2M);
414 CASE_RET_STR(kCpumMicroarch_Intel_NB_CedarMill);
415 CASE_RET_STR(kCpumMicroarch_Intel_NB_Gallatin);
416 CASE_RET_STR(kCpumMicroarch_Intel_NB_Unknown);
417
418 CASE_RET_STR(kCpumMicroarch_Intel_Unknown);
419
420 CASE_RET_STR(kCpumMicroarch_AMD_Am286);
421 CASE_RET_STR(kCpumMicroarch_AMD_Am386);
422 CASE_RET_STR(kCpumMicroarch_AMD_Am486);
423 CASE_RET_STR(kCpumMicroarch_AMD_Am486Enh);
424 CASE_RET_STR(kCpumMicroarch_AMD_K5);
425 CASE_RET_STR(kCpumMicroarch_AMD_K6);
426
427 CASE_RET_STR(kCpumMicroarch_AMD_K7_Palomino);
428 CASE_RET_STR(kCpumMicroarch_AMD_K7_Spitfire);
429 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thunderbird);
430 CASE_RET_STR(kCpumMicroarch_AMD_K7_Morgan);
431 CASE_RET_STR(kCpumMicroarch_AMD_K7_Thoroughbred);
432 CASE_RET_STR(kCpumMicroarch_AMD_K7_Barton);
433 CASE_RET_STR(kCpumMicroarch_AMD_K7_Unknown);
434
435 CASE_RET_STR(kCpumMicroarch_AMD_K8_130nm);
436 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm);
437 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_DualCore);
438 CASE_RET_STR(kCpumMicroarch_AMD_K8_90nm_AMDV);
439 CASE_RET_STR(kCpumMicroarch_AMD_K8_65nm);
440
441 CASE_RET_STR(kCpumMicroarch_AMD_K10);
442 CASE_RET_STR(kCpumMicroarch_AMD_K10_Lion);
443 CASE_RET_STR(kCpumMicroarch_AMD_K10_Llano);
444 CASE_RET_STR(kCpumMicroarch_AMD_Bobcat);
445 CASE_RET_STR(kCpumMicroarch_AMD_Jaguar);
446
447 CASE_RET_STR(kCpumMicroarch_AMD_15h_Bulldozer);
448 CASE_RET_STR(kCpumMicroarch_AMD_15h_Piledriver);
449 CASE_RET_STR(kCpumMicroarch_AMD_15h_Steamroller);
450 CASE_RET_STR(kCpumMicroarch_AMD_15h_Excavator);
451 CASE_RET_STR(kCpumMicroarch_AMD_15h_Unknown);
452
453 CASE_RET_STR(kCpumMicroarch_AMD_16h_First);
454
455 CASE_RET_STR(kCpumMicroarch_AMD_Unknown);
456
457 CASE_RET_STR(kCpumMicroarch_Centaur_C6);
458 CASE_RET_STR(kCpumMicroarch_Centaur_C2);
459 CASE_RET_STR(kCpumMicroarch_Centaur_C3);
460 CASE_RET_STR(kCpumMicroarch_VIA_C3_M2);
461 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5A);
462 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5B);
463 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5C);
464 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5N);
465 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5XL);
466 CASE_RET_STR(kCpumMicroarch_VIA_C3_C5P);
467 CASE_RET_STR(kCpumMicroarch_VIA_C7_C5J);
468 CASE_RET_STR(kCpumMicroarch_VIA_Isaiah);
469 CASE_RET_STR(kCpumMicroarch_VIA_Unknown);
470
471 CASE_RET_STR(kCpumMicroarch_Cyrix_5x86);
472 CASE_RET_STR(kCpumMicroarch_Cyrix_M1);
473 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGX);
474 CASE_RET_STR(kCpumMicroarch_Cyrix_MediaGXm);
475 CASE_RET_STR(kCpumMicroarch_Cyrix_M2);
476 CASE_RET_STR(kCpumMicroarch_Cyrix_Unknown);
477
478 CASE_RET_STR(kCpumMicroarch_Unknown);
479
480#undef CASE_RET_STR
481 case kCpumMicroarch_Invalid:
482 case kCpumMicroarch_Intel_End:
483 case kCpumMicroarch_Intel_Core7_End:
484 case kCpumMicroarch_Intel_Atom_End:
485 case kCpumMicroarch_Intel_P6_Core_Atom_End:
486 case kCpumMicroarch_Intel_NB_End:
487 case kCpumMicroarch_AMD_K7_End:
488 case kCpumMicroarch_AMD_K8_End:
489 case kCpumMicroarch_AMD_15h_End:
490 case kCpumMicroarch_AMD_16h_End:
491 case kCpumMicroarch_AMD_End:
492 case kCpumMicroarch_VIA_End:
493 case kCpumMicroarch_Cyrix_End:
494 case kCpumMicroarch_32BitHack:
495 break;
496 /* no default! */
497 }
498
499 return NULL;
500}
501
502
503
504/**
505 * Gets a matching leaf in the CPUID leaf array.
506 *
507 * @returns Pointer to the matching leaf, or NULL if not found.
508 * @param paLeaves The CPUID leaves to search. This is sorted.
509 * @param cLeaves The number of leaves in the array.
510 * @param uLeaf The leaf to locate.
511 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
512 */
513PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf)
514{
515 /* Lazy bird does linear lookup here since this is only used for the
516 occational CPUID overrides. */
517 for (uint32_t i = 0; i < cLeaves; i++)
518 if ( paLeaves[i].uLeaf == uLeaf
519 && paLeaves[i].uSubLeaf == (uSubLeaf & paLeaves[i].fSubLeafMask))
520 return &paLeaves[i];
521 return NULL;
522}
523
524
525/**
526 * Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
527 *
528 * @returns true if found, false it not.
529 * @param paLeaves The CPUID leaves to search. This is sorted.
530 * @param cLeaves The number of leaves in the array.
531 * @param uLeaf The leaf to locate.
532 * @param uSubLeaf The subleaf to locate. Pass 0 if no subleaves.
533 * @param pLegacy The legacy output leaf.
534 */
535bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf, PCPUMCPUID pLeagcy)
536{
537 PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(paLeaves, cLeaves, uLeaf, uSubLeaf);
538 if (pLeaf)
539 {
540 pLeagcy->eax = pLeaf->uEax;
541 pLeagcy->ebx = pLeaf->uEbx;
542 pLeagcy->ecx = pLeaf->uEcx;
543 pLeagcy->edx = pLeaf->uEdx;
544 return true;
545 }
546 return false;
547}
548
549
550/**
551 * Ensures that the CPUID leaf array can hold one more leaf.
552 *
553 * @returns Pointer to the CPUID leaf array (*ppaLeaves) on success. NULL on
554 * failure.
555 * @param ppaLeaves Pointer to the variable holding the array
556 * pointer (input/output).
557 * @param cLeaves The current array size.
558 */
559static PCPUMCPUIDLEAF cpumR3CpuIdEnsureSpace(PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves)
560{
561 uint32_t cAllocated = RT_ALIGN(cLeaves, 16);
562 if (cLeaves + 1 > cAllocated)
563 {
564 void *pvNew = RTMemRealloc(*ppaLeaves, (cAllocated + 16) * sizeof(**ppaLeaves));
565 if (!pvNew)
566 {
567 RTMemFree(*ppaLeaves);
568 *ppaLeaves = NULL;
569 return NULL;
570 }
571 *ppaLeaves = (PCPUMCPUIDLEAF)pvNew;
572 }
573 return *ppaLeaves;
574}
575
576
577/**
578 * Append a CPUID leaf or sub-leaf.
579 *
580 * ASSUMES linear insertion order, so we'll won't need to do any searching or
581 * replace anything. Use cpumR3CpuIdInsert for those cases.
582 *
583 * @returns VINF_SUCCESS or VERR_NO_MEMORY. On error, *ppaLeaves is freed, so
584 * the caller need do no more work.
585 * @param ppaLeaves Pointer to the the pointer to the array of sorted
586 * CPUID leaves and sub-leaves.
587 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
588 * @param uLeaf The leaf we're adding.
589 * @param uSubLeaf The sub-leaf number.
590 * @param fSubLeafMask The sub-leaf mask.
591 * @param uEax The EAX value.
592 * @param uEbx The EBX value.
593 * @param uEcx The ECX value.
594 * @param uEdx The EDX value.
595 * @param fFlags The flags.
596 */
597static int cpumR3CollectCpuIdInfoAddOne(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves,
598 uint32_t uLeaf, uint32_t uSubLeaf, uint32_t fSubLeafMask,
599 uint32_t uEax, uint32_t uEbx, uint32_t uEcx, uint32_t uEdx, uint32_t fFlags)
600{
601 if (!cpumR3CpuIdEnsureSpace(ppaLeaves, *pcLeaves))
602 return VERR_NO_MEMORY;
603
604 PCPUMCPUIDLEAF pNew = &(*ppaLeaves)[*pcLeaves];
605 Assert( *pcLeaves == 0
606 || pNew[-1].uLeaf < uLeaf
607 || (pNew[-1].uLeaf == uLeaf && pNew[-1].uSubLeaf < uSubLeaf) );
608
609 pNew->uLeaf = uLeaf;
610 pNew->uSubLeaf = uSubLeaf;
611 pNew->fSubLeafMask = fSubLeafMask;
612 pNew->uEax = uEax;
613 pNew->uEbx = uEbx;
614 pNew->uEcx = uEcx;
615 pNew->uEdx = uEdx;
616 pNew->fFlags = fFlags;
617
618 *pcLeaves += 1;
619 return VINF_SUCCESS;
620}
621
622
623/**
624 * Inserts a CPU ID leaf, replacing any existing ones.
625 *
626 * When inserting a simple leaf where we already got a series of subleaves with
627 * the same leaf number (eax), the simple leaf will replace the whole series.
628 *
629 * This ASSUMES that the leave array is still on the normal heap and has only
630 * been allocated/reallocated by the cpumR3CpuIdEnsureSpace function.
631 *
632 * @returns VBox status code.
633 * @param ppaLeaves Pointer to the the pointer to the array of sorted
634 * CPUID leaves and sub-leaves.
635 * @param pcLeaves Where we keep the leaf count for *ppaLeaves.
636 * @param pNewLeaf Pointer to the data of the new leaf we're about to
637 * insert.
638 */
639int cpumR3CpuIdInsert(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
640{
641 PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
642 uint32_t cLeaves = *pcLeaves;
643
644 /*
645 * Validate the new leaf a little.
646 */
647 AssertReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED), VERR_INVALID_FLAGS);
648 AssertReturn(pNewLeaf->fSubLeafMask != 0 || pNewLeaf->uSubLeaf == 0, VERR_INVALID_PARAMETER);
649 AssertReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1), VERR_INVALID_PARAMETER);
650 AssertReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf, VERR_INVALID_PARAMETER);
651
652
653 /*
654 * Find insertion point. The lazy bird uses the same excuse as in
655 * cpumR3CpuIdGetLeaf().
656 */
657 uint32_t i = 0;
658 while ( i < cLeaves
659 && paLeaves[i].uLeaf < pNewLeaf->uLeaf)
660 i++;
661 if ( i < cLeaves
662 && paLeaves[i].uLeaf == pNewLeaf->uLeaf)
663 {
664 if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
665 {
666 /*
667 * The subleaf mask differs, replace all existing leaves with the
668 * same leaf number.
669 */
670 uint32_t c = 1;
671 while ( i + c < cLeaves
672 && paLeaves[i + c].uSubLeaf == pNewLeaf->uLeaf)
673 c++;
674 if (c > 1 && i + c < cLeaves)
675 {
676 memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
677 *pcLeaves = cLeaves -= c - 1;
678 }
679
680 paLeaves[i] = *pNewLeaf;
681 return VINF_SUCCESS;
682 }
683
684 /* Find subleaf insertion point. */
685 while ( i < cLeaves
686 && paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf)
687 i++;
688
689 /*
690 * If we've got an exactly matching leaf, replace it.
691 */
692 if ( paLeaves[i].uLeaf == pNewLeaf->uLeaf
693 && paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
694 {
695 paLeaves[i] = *pNewLeaf;
696 return VINF_SUCCESS;
697 }
698 }
699
700 /*
701 * Adding a new leaf at 'i'.
702 */
703 paLeaves = cpumR3CpuIdEnsureSpace(ppaLeaves, cLeaves);
704 if (!paLeaves)
705 return VERR_NO_MEMORY;
706
707 if (i < cLeaves)
708 memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
709 *pcLeaves += 1;
710 paLeaves[i] = *pNewLeaf;
711 return VINF_SUCCESS;
712}
713
714
715/**
716 * Removes a range of CPUID leaves.
717 *
718 * This will not reallocate the array.
719 *
720 * @param paLeaves The array of sorted CPUID leaves and sub-leaves.
721 * @param pcLeaves Where we keep the leaf count for @a paLeaves.
722 * @param uFirst The first leaf.
723 * @param uLast The last leaf.
724 */
725void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
726{
727 uint32_t cLeaves = *pcLeaves;
728
729 Assert(uFirst <= uLast);
730
731 /*
732 * Find the first one.
733 */
734 uint32_t iFirst = 0;
735 while ( iFirst < cLeaves
736 && paLeaves[iFirst].uLeaf < uFirst)
737 iFirst++;
738
739 /*
740 * Find the end (last + 1).
741 */
742 uint32_t iEnd = iFirst;
743 while ( iEnd < cLeaves
744 && paLeaves[iEnd].uLeaf <= uLast)
745 iEnd++;
746
747 /*
748 * Adjust the array if anything needs removing.
749 */
750 if (iFirst < iEnd)
751 {
752 if (iEnd < cLeaves)
753 memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
754 *pcLeaves = cLeaves -= (iEnd - iFirst);
755 }
756}
757
758
759
760/**
761 * Checks if ECX make a difference when reading a given CPUID leaf.
762 *
763 * @returns @c true if it does, @c false if it doesn't.
764 * @param uLeaf The leaf we're reading.
765 * @param pcSubLeaves Number of sub-leaves accessible via ECX.
766 * @param pfFinalEcxUnchanged Whether ECX is passed thru when going beyond the
767 * final sub-leaf.
768 */
769static bool cpumR3IsEcxRelevantForCpuIdLeaf(uint32_t uLeaf, uint32_t *pcSubLeaves, bool *pfFinalEcxUnchanged)
770{
771 *pfFinalEcxUnchanged = false;
772
773 uint32_t auCur[4];
774 uint32_t auPrev[4];
775 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &auPrev[0], &auPrev[1], &auPrev[2], &auPrev[3]);
776
777 /* Look for sub-leaves. */
778 uint32_t uSubLeaf = 1;
779 for (;;)
780 {
781 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
782 if (memcmp(auCur, auPrev, sizeof(auCur)))
783 break;
784
785 /* Advance / give up. */
786 uSubLeaf++;
787 if (uSubLeaf >= 64)
788 {
789 *pcSubLeaves = 1;
790 return false;
791 }
792 }
793
794 /* Count sub-leaves. */
795 uint32_t cRepeats = 0;
796 uSubLeaf = 0;
797 for (;;)
798 {
799 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
800
801 /* Figuring out when to stop isn't entirely straight forward as we need
802 to cover undocumented behavior up to a point and implementation shortcuts. */
803
804 /* 1. Look for zero values. */
805 if ( auCur[0] == 0
806 && auCur[1] == 0
807 && (auCur[2] == 0 || auCur[2] == uSubLeaf)
808 && (auCur[3] == 0 || uLeaf == 0xb /* edx is fixed */) )
809 break;
810
811 /* 2. Look for more than 4 repeating value sets. */
812 if ( auCur[0] == auPrev[0]
813 && auCur[1] == auPrev[1]
814 && ( auCur[2] == auPrev[2]
815 || ( auCur[2] == uSubLeaf
816 && auPrev[2] == uSubLeaf - 1) )
817 && auCur[3] == auPrev[3])
818 {
819 cRepeats++;
820 if (cRepeats > 4)
821 break;
822 }
823 else
824 cRepeats = 0;
825
826 /* 3. Leaf 0xb level type 0 check. */
827 if ( uLeaf == 0xb
828 && (auCur[3] & 0xff00) == 0
829 && (auPrev[3] & 0xff00) == 0)
830 break;
831
832 /* 99. Give up. */
833 if (uSubLeaf >= 128)
834 {
835#ifndef IN_VBOX_CPU_REPORT
836 /* Ok, limit it according to the documentation if possible just to
837 avoid annoying users with these detection issues. */
838 uint32_t cDocLimit = UINT32_MAX;
839 if (uLeaf == 0x4)
840 cDocLimit = 4;
841 else if (uLeaf == 0x7)
842 cDocLimit = 1;
843 else if (uLeaf == 0xf)
844 cDocLimit = 2;
845 if (cDocLimit != UINT32_MAX)
846 {
847 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf;
848 *pcSubLeaves = cDocLimit + 3;
849 return true;
850 }
851#endif
852 *pcSubLeaves = UINT32_MAX;
853 return true;
854 }
855
856 /* Advance. */
857 uSubLeaf++;
858 memcpy(auPrev, auCur, sizeof(auCur));
859 }
860
861 /* Standard exit. */
862 *pfFinalEcxUnchanged = auCur[2] == uSubLeaf;
863 *pcSubLeaves = uSubLeaf + 1 - cRepeats;
864 return true;
865}
866
867
868/**
869 * Collects CPUID leaves and sub-leaves, returning a sorted array of them.
870 *
871 * @returns VBox status code.
872 * @param ppaLeaves Where to return the array pointer on success.
873 * Use RTMemFree to release.
874 * @param pcLeaves Where to return the size of the array on
875 * success.
876 */
877VMMR3DECL(int) CPUMR3CpuIdCollectLeaves(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
878{
879 *ppaLeaves = NULL;
880 *pcLeaves = 0;
881
882 /*
883 * Try out various candidates. This must be sorted!
884 */
885 static struct { uint32_t uMsr; bool fSpecial; } const s_aCandidates[] =
886 {
887 { UINT32_C(0x00000000), false },
888 { UINT32_C(0x10000000), false },
889 { UINT32_C(0x20000000), false },
890 { UINT32_C(0x30000000), false },
891 { UINT32_C(0x40000000), false },
892 { UINT32_C(0x50000000), false },
893 { UINT32_C(0x60000000), false },
894 { UINT32_C(0x70000000), false },
895 { UINT32_C(0x80000000), false },
896 { UINT32_C(0x80860000), false },
897 { UINT32_C(0x8ffffffe), true },
898 { UINT32_C(0x8fffffff), true },
899 { UINT32_C(0x90000000), false },
900 { UINT32_C(0xa0000000), false },
901 { UINT32_C(0xb0000000), false },
902 { UINT32_C(0xc0000000), false },
903 { UINT32_C(0xd0000000), false },
904 { UINT32_C(0xe0000000), false },
905 { UINT32_C(0xf0000000), false },
906 };
907
908 for (uint32_t iOuter = 0; iOuter < RT_ELEMENTS(s_aCandidates); iOuter++)
909 {
910 uint32_t uLeaf = s_aCandidates[iOuter].uMsr;
911 uint32_t uEax, uEbx, uEcx, uEdx;
912 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
913
914 /*
915 * Does EAX look like a typical leaf count value?
916 */
917 if ( uEax > uLeaf
918 && uEax - uLeaf < UINT32_C(0xff)) /* Adjust 0xff limit when exceeded by real HW. */
919 {
920 /* Yes, dump them. */
921 uint32_t cLeaves = uEax - uLeaf + 1;
922 while (cLeaves-- > 0)
923 {
924 /* Check three times here to reduce the chance of CPU migration
925 resulting in false positives with things like the APIC ID. */
926 uint32_t cSubLeaves;
927 bool fFinalEcxUnchanged;
928 if ( cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
929 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged)
930 && cpumR3IsEcxRelevantForCpuIdLeaf(uLeaf, &cSubLeaves, &fFinalEcxUnchanged))
931 {
932 if (cSubLeaves > 16)
933 {
934 /* This shouldn't happen. But in case it does, file all
935 relevant details in the release log. */
936 LogRel(("CPUM: VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES! uLeaf=%#x cSubLeaves=%#x\n", uLeaf, cSubLeaves));
937 LogRel(("------------------ dump of problematic subleaves ------------------\n"));
938 for (uint32_t uSubLeaf = 0; uSubLeaf < 128; uSubLeaf++)
939 {
940 uint32_t auTmp[4];
941 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &auTmp[0], &auTmp[1], &auTmp[2], &auTmp[3]);
942 LogRel(("CPUM: %#010x, %#010x => %#010x %#010x %#010x %#010x\n",
943 uLeaf, uSubLeaf, auTmp[0], auTmp[1], auTmp[2], auTmp[3]));
944 }
945 LogRel(("----------------- dump of what we've found so far -----------------\n"));
946 for (uint32_t i = 0 ; i < *pcLeaves; i++)
947 LogRel(("CPUM: %#010x, %#010x/%#010x => %#010x %#010x %#010x %#010x\n",
948 (*ppaLeaves)[i].uLeaf, (*ppaLeaves)[i].uSubLeaf, (*ppaLeaves)[i].fSubLeafMask,
949 (*ppaLeaves)[i].uEax, (*ppaLeaves)[i].uEbx, (*ppaLeaves)[i].uEcx, (*ppaLeaves)[i].uEdx));
950 LogRel(("\nPlease create a defect on virtualbox.org and attach this log file!\n\n"));
951 return VERR_CPUM_TOO_MANY_CPUID_SUBLEAVES;
952 }
953
954 for (uint32_t uSubLeaf = 0; uSubLeaf < cSubLeaves; uSubLeaf++)
955 {
956 ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &uEax, &uEbx, &uEcx, &uEdx);
957 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
958 uLeaf, uSubLeaf, UINT32_MAX, uEax, uEbx, uEcx, uEdx,
959 uSubLeaf + 1 == cSubLeaves && fFinalEcxUnchanged
960 ? CPUMCPUIDLEAF_F_SUBLEAVES_ECX_UNCHANGED : 0);
961 if (RT_FAILURE(rc))
962 return rc;
963 }
964 }
965 else
966 {
967 ASMCpuIdExSlow(uLeaf, 0, 0, 0, &uEax, &uEbx, &uEcx, &uEdx);
968 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
969 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
970 if (RT_FAILURE(rc))
971 return rc;
972 }
973
974 /* next */
975 uLeaf++;
976 }
977 }
978 /*
979 * Special CPUIDs needs special handling as they don't follow the
980 * leaf count principle used above.
981 */
982 else if (s_aCandidates[iOuter].fSpecial)
983 {
984 bool fKeep = false;
985 if (uLeaf == 0x8ffffffe && uEax == UINT32_C(0x00494544))
986 fKeep = true;
987 else if ( uLeaf == 0x8fffffff
988 && RT_C_IS_PRINT(RT_BYTE1(uEax))
989 && RT_C_IS_PRINT(RT_BYTE2(uEax))
990 && RT_C_IS_PRINT(RT_BYTE3(uEax))
991 && RT_C_IS_PRINT(RT_BYTE4(uEax))
992 && RT_C_IS_PRINT(RT_BYTE1(uEbx))
993 && RT_C_IS_PRINT(RT_BYTE2(uEbx))
994 && RT_C_IS_PRINT(RT_BYTE3(uEbx))
995 && RT_C_IS_PRINT(RT_BYTE4(uEbx))
996 && RT_C_IS_PRINT(RT_BYTE1(uEcx))
997 && RT_C_IS_PRINT(RT_BYTE2(uEcx))
998 && RT_C_IS_PRINT(RT_BYTE3(uEcx))
999 && RT_C_IS_PRINT(RT_BYTE4(uEcx))
1000 && RT_C_IS_PRINT(RT_BYTE1(uEdx))
1001 && RT_C_IS_PRINT(RT_BYTE2(uEdx))
1002 && RT_C_IS_PRINT(RT_BYTE3(uEdx))
1003 && RT_C_IS_PRINT(RT_BYTE4(uEdx)) )
1004 fKeep = true;
1005 if (fKeep)
1006 {
1007 int rc = cpumR3CollectCpuIdInfoAddOne(ppaLeaves, pcLeaves,
1008 uLeaf, 0, 0, uEax, uEbx, uEcx, uEdx, 0);
1009 if (RT_FAILURE(rc))
1010 return rc;
1011 }
1012 }
1013 }
1014
1015 return VINF_SUCCESS;
1016}
1017
1018
1019/**
1020 * Determines the method the CPU uses to handle unknown CPUID leaves.
1021 *
1022 * @returns VBox status code.
1023 * @param penmUnknownMethod Where to return the method.
1024 * @param pDefUnknown Where to return default unknown values. This
1025 * will be set, even if the resulting method
1026 * doesn't actually needs it.
1027 */
1028VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
1029{
1030 uint32_t uLastStd = ASMCpuId_EAX(0);
1031 uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
1032 if (!ASMIsValidExtRange(uLastExt))
1033 uLastExt = 0x80000000;
1034
1035 uint32_t auChecks[] =
1036 {
1037 uLastStd + 1,
1038 uLastStd + 5,
1039 uLastStd + 8,
1040 uLastStd + 32,
1041 uLastStd + 251,
1042 uLastExt + 1,
1043 uLastExt + 8,
1044 uLastExt + 15,
1045 uLastExt + 63,
1046 uLastExt + 255,
1047 0x7fbbffcc,
1048 0x833f7872,
1049 0xefff2353,
1050 0x35779456,
1051 0x1ef6d33e,
1052 };
1053
1054 static const uint32_t s_auValues[] =
1055 {
1056 0xa95d2156,
1057 0x00000001,
1058 0x00000002,
1059 0x00000008,
1060 0x00000000,
1061 0x55773399,
1062 0x93401769,
1063 0x12039587,
1064 };
1065
1066 /*
1067 * Simple method, all zeros.
1068 */
1069 *penmUnknownMethod = CPUMUKNOWNCPUID_DEFAULTS;
1070 pDefUnknown->eax = 0;
1071 pDefUnknown->ebx = 0;
1072 pDefUnknown->ecx = 0;
1073 pDefUnknown->edx = 0;
1074
1075 /*
1076 * Intel has been observed returning the last standard leaf.
1077 */
1078 uint32_t auLast[4];
1079 ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
1080
1081 uint32_t cChecks = RT_ELEMENTS(auChecks);
1082 while (cChecks > 0)
1083 {
1084 uint32_t auCur[4];
1085 ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1086 if (memcmp(auCur, auLast, sizeof(auCur)))
1087 break;
1088 cChecks--;
1089 }
1090 if (cChecks == 0)
1091 {
1092 /* Now, what happens when the input changes? Esp. ECX. */
1093 uint32_t cTotal = 0;
1094 uint32_t cSame = 0;
1095 uint32_t cLastWithEcx = 0;
1096 uint32_t cNeither = 0;
1097 uint32_t cValues = RT_ELEMENTS(s_auValues);
1098 while (cValues > 0)
1099 {
1100 uint32_t uValue = s_auValues[cValues - 1];
1101 uint32_t auLastWithEcx[4];
1102 ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
1103 &auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
1104
1105 cChecks = RT_ELEMENTS(auChecks);
1106 while (cChecks > 0)
1107 {
1108 uint32_t auCur[4];
1109 ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1110 if (!memcmp(auCur, auLast, sizeof(auCur)))
1111 {
1112 cSame++;
1113 if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1114 cLastWithEcx++;
1115 }
1116 else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
1117 cLastWithEcx++;
1118 else
1119 cNeither++;
1120 cTotal++;
1121 cChecks--;
1122 }
1123 cValues--;
1124 }
1125
1126 Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
1127 if (cSame == cTotal)
1128 *penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1129 else if (cLastWithEcx == cTotal)
1130 *penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
1131 else
1132 *penmUnknownMethod = CPUMUKNOWNCPUID_LAST_STD_LEAF;
1133 pDefUnknown->eax = auLast[0];
1134 pDefUnknown->ebx = auLast[1];
1135 pDefUnknown->ecx = auLast[2];
1136 pDefUnknown->edx = auLast[3];
1137 return VINF_SUCCESS;
1138 }
1139
1140 /*
1141 * Unchanged register values?
1142 */
1143 cChecks = RT_ELEMENTS(auChecks);
1144 while (cChecks > 0)
1145 {
1146 uint32_t const uLeaf = auChecks[cChecks - 1];
1147 uint32_t cValues = RT_ELEMENTS(s_auValues);
1148 while (cValues > 0)
1149 {
1150 uint32_t uValue = s_auValues[cValues - 1];
1151 uint32_t auCur[4];
1152 ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
1153 if ( auCur[0] != uLeaf
1154 || auCur[1] != uValue
1155 || auCur[2] != uValue
1156 || auCur[3] != uValue)
1157 break;
1158 cValues--;
1159 }
1160 if (cValues != 0)
1161 break;
1162 cChecks--;
1163 }
1164 if (cChecks == 0)
1165 {
1166 *penmUnknownMethod = CPUMUKNOWNCPUID_PASSTHRU;
1167 return VINF_SUCCESS;
1168 }
1169
1170 /*
1171 * Just go with the simple method.
1172 */
1173 return VINF_SUCCESS;
1174}
1175
1176
1177/**
1178 * Translates a unknow CPUID leaf method into the constant name (sans prefix).
1179 *
1180 * @returns Read only name string.
1181 * @param enmUnknownMethod The method to translate.
1182 */
1183VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUKNOWNCPUID enmUnknownMethod)
1184{
1185 switch (enmUnknownMethod)
1186 {
1187 case CPUMUKNOWNCPUID_DEFAULTS: return "DEFAULTS";
1188 case CPUMUKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
1189 case CPUMUKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
1190 case CPUMUKNOWNCPUID_PASSTHRU: return "PASSTHRU";
1191
1192 case CPUMUKNOWNCPUID_INVALID:
1193 case CPUMUKNOWNCPUID_END:
1194 case CPUMUKNOWNCPUID_32BIT_HACK:
1195 break;
1196 }
1197 return "Invalid-unknown-CPUID-method";
1198}
1199
1200
1201/**
1202 * Detect the CPU vendor give n the
1203 *
1204 * @returns The vendor.
1205 * @param uEAX EAX from CPUID(0).
1206 * @param uEBX EBX from CPUID(0).
1207 * @param uECX ECX from CPUID(0).
1208 * @param uEDX EDX from CPUID(0).
1209 */
1210VMMR3DECL(CPUMCPUVENDOR) CPUMR3CpuIdDetectVendorEx(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
1211{
1212 if (ASMIsValidStdRange(uEAX))
1213 {
1214 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
1215 return CPUMCPUVENDOR_AMD;
1216
1217 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
1218 return CPUMCPUVENDOR_INTEL;
1219
1220 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
1221 return CPUMCPUVENDOR_VIA;
1222
1223 if ( uEBX == UINT32_C(0x69727943) /* CyrixInstead */
1224 && uECX == UINT32_C(0x64616574)
1225 && uEDX == UINT32_C(0x736E4978))
1226 return CPUMCPUVENDOR_CYRIX;
1227
1228 /* "Geode by NSC", example: family 5, model 9. */
1229
1230 /** @todo detect the other buggers... */
1231 }
1232
1233 return CPUMCPUVENDOR_UNKNOWN;
1234}
1235
1236
1237/**
1238 * Translates a CPU vendor enum value into the corresponding string constant.
1239 *
1240 * The named can be prefixed with 'CPUMCPUVENDOR_' to construct a valid enum
1241 * value name. This can be useful when generating code.
1242 *
1243 * @returns Read only name string.
1244 * @param enmVendor The CPU vendor value.
1245 */
1246VMMR3DECL(const char *) CPUMR3CpuVendorName(CPUMCPUVENDOR enmVendor)
1247{
1248 switch (enmVendor)
1249 {
1250 case CPUMCPUVENDOR_INTEL: return "INTEL";
1251 case CPUMCPUVENDOR_AMD: return "AMD";
1252 case CPUMCPUVENDOR_VIA: return "VIA";
1253 case CPUMCPUVENDOR_CYRIX: return "CYRIX";
1254 case CPUMCPUVENDOR_UNKNOWN: return "UNKNOWN";
1255
1256 case CPUMCPUVENDOR_INVALID:
1257 case CPUMCPUVENDOR_32BIT_HACK:
1258 break;
1259 }
1260 return "Invalid-cpu-vendor";
1261}
1262
1263
1264static PCCPUMCPUIDLEAF cpumR3CpuIdFindLeaf(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf)
1265{
1266 /* Could do binary search, doing linear now because I'm lazy. */
1267 PCCPUMCPUIDLEAF pLeaf = paLeaves;
1268 while (cLeaves-- > 0)
1269 {
1270 if (pLeaf->uLeaf == uLeaf)
1271 return pLeaf;
1272 pLeaf++;
1273 }
1274 return NULL;
1275}
1276
1277
1278int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures)
1279{
1280 RT_ZERO(*pFeatures);
1281 if (cLeaves >= 2)
1282 {
1283 AssertLogRelReturn(paLeaves[0].uLeaf == 0, VERR_CPUM_IPE_1);
1284 AssertLogRelReturn(paLeaves[1].uLeaf == 1, VERR_CPUM_IPE_1);
1285
1286 pFeatures->enmCpuVendor = CPUMR3CpuIdDetectVendorEx(paLeaves[0].uEax,
1287 paLeaves[0].uEbx,
1288 paLeaves[0].uEcx,
1289 paLeaves[0].uEdx);
1290 pFeatures->uFamily = ASMGetCpuFamily(paLeaves[1].uEax);
1291 pFeatures->uModel = ASMGetCpuModel(paLeaves[1].uEax, pFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL);
1292 pFeatures->uStepping = ASMGetCpuStepping(paLeaves[1].uEax);
1293 pFeatures->enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx((CPUMCPUVENDOR)pFeatures->enmCpuVendor,
1294 pFeatures->uFamily,
1295 pFeatures->uModel,
1296 pFeatures->uStepping);
1297
1298 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000008);
1299 if (pLeaf)
1300 pFeatures->cMaxPhysAddrWidth = pLeaf->uEax & 0xff;
1301 else if (paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36)
1302 pFeatures->cMaxPhysAddrWidth = 36;
1303 else
1304 pFeatures->cMaxPhysAddrWidth = 32;
1305
1306 /* Standard features. */
1307 pFeatures->fMsr = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_MSR);
1308 pFeatures->fApic = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_APIC);
1309 pFeatures->fX2Apic = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_X2APIC);
1310 pFeatures->fPse = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE);
1311 pFeatures->fPse36 = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PSE36);
1312 pFeatures->fPae = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAE);
1313 pFeatures->fPat = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_PAT);
1314 pFeatures->fFxSaveRstor = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_FXSR);
1315 pFeatures->fSysEnter = RT_BOOL(paLeaves[1].uEdx & X86_CPUID_FEATURE_EDX_SEP);
1316 pFeatures->fHypervisorPresent = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_HVP);
1317 pFeatures->fMonitorMWait = RT_BOOL(paLeaves[1].uEcx & X86_CPUID_FEATURE_ECX_MONITOR);
1318
1319 /* Extended features. */
1320 PCCPUMCPUIDLEAF const pExtLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 0x80000001);
1321 if (pExtLeaf)
1322 {
1323 pFeatures->fLongMode = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1324 pFeatures->fSysCall = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_SYSCALL);
1325 pFeatures->fNoExecute = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX);
1326 pFeatures->fLahfSahf = RT_BOOL(pExtLeaf->uEcx & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1327 pFeatures->fRdTscP = RT_BOOL(pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1328 }
1329
1330 if ( pExtLeaf
1331 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD)
1332 {
1333 /* AMD features. */
1334 pFeatures->fMsr |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_MSR);
1335 pFeatures->fApic |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_APIC);
1336 pFeatures->fPse |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE);
1337 pFeatures->fPse36 |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PSE36);
1338 pFeatures->fPae |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAE);
1339 pFeatures->fPat |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_PAT);
1340 pFeatures->fFxSaveRstor |= RT_BOOL(pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FXSR);
1341 }
1342
1343 /*
1344 * Quirks.
1345 */
1346 pFeatures->fLeakyFxSR = pExtLeaf
1347 && (pExtLeaf->uEdx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1348 && pFeatures->enmCpuVendor == CPUMCPUVENDOR_AMD
1349 && pFeatures->uFamily >= 6 /* K7 and up */;
1350 }
1351 else
1352 AssertLogRelReturn(cLeaves == 0, VERR_CPUM_IPE_1);
1353 return VINF_SUCCESS;
1354}
1355
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