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CPUMR3CpuId.cpp

Last change on this file was 103752, checked in by vboxsync, 2 months ago
VMM/CPUMR3CpuId: Enable XSAVE for IEM, it is fully supported, enables us to run bs3-cpu-instr-3 with IEM on arm64, bugref:10614
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 295.4 KB

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1	/* $Id: CPUMR3CpuId.cpp 103752 2024-03-11 08:12:36Z vboxsync $ */
2	/** @file
3	* CPUM - CPU ID part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_CPUM
33	#include <VBox/vmm/cpum.h>
34	#include <VBox/vmm/dbgf.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/nem.h>
37	#include <VBox/vmm/ssm.h>
38	#include "CPUMInternal.h"
39	#include <VBox/vmm/vmcc.h>
40	#include <VBox/sup.h>
41
42	#include <VBox/err.h>
43	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
44	# include <iprt/asm-amd64-x86.h>
45	#endif
46	#include <iprt/ctype.h>
47	#include <iprt/mem.h>
48	#include <iprt/string.h>
49	#include <iprt/x86-helpers.h>
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** For sanity and avoid wasting hyper heap on buggy config / saved state. */
56	#define CPUM_CPUID_MAX_LEAVES 2048
57
58
59	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
60	/**
61	* Determins the host CPU MXCSR mask.
62	*
63	* @returns MXCSR mask.
64	*/
65	VMMR3DECL(uint32_t) CPUMR3DeterminHostMxCsrMask(void)
66	{
67	if ( ASMHasCpuId()
68	&& RTX86IsValidStdRange(ASMCpuId_EAX(0))
69	&& ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_FXSR)
70	{
71	uint8_t volatile abBuf[sizeof(X86FXSTATE) + 64];
72	PX86FXSTATE pState = (PX86FXSTATE)&abBuf[64 - ((uintptr_t)&abBuf[0] & 63)];
73	RT_ZERO(*pState);
74	ASMFxSave(pState);
75	if (pState->MXCSR_MASK == 0)
76	return 0xffbf;
77	return pState->MXCSR_MASK;
78	}
79	return 0;
80	}
81	#endif
82
83
84
85	#ifndef IN_VBOX_CPU_REPORT
86	/**
87	* Gets a matching leaf in the CPUID leaf array, converted to a CPUMCPUID.
88	*
89	* @returns true if found, false it not.
90	* @param paLeaves The CPUID leaves to search. This is sorted.
91	* @param cLeaves The number of leaves in the array.
92	* @param uLeaf The leaf to locate.
93	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
94	* @param pLegacy The legacy output leaf.
95	*/
96	static bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
97	PCPUMCPUID pLegacy)
98	{
99	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, uLeaf, uSubLeaf);
100	if (pLeaf)
101	{
102	pLegacy->uEax = pLeaf->uEax;
103	pLegacy->uEbx = pLeaf->uEbx;
104	pLegacy->uEcx = pLeaf->uEcx;
105	pLegacy->uEdx = pLeaf->uEdx;
106	return true;
107	}
108	return false;
109	}
110	#endif /* IN_VBOX_CPU_REPORT */
111
112
113	/**
114	* Inserts a CPU ID leaf, replacing any existing ones.
115	*
116	* When inserting a simple leaf where we already got a series of sub-leaves with
117	* the same leaf number (eax), the simple leaf will replace the whole series.
118	*
119	* When pVM is NULL, this ASSUMES that the leaves array is still on the normal
120	* host-context heap and has only been allocated/reallocated by the
121	* cpumCpuIdEnsureSpace function.
122	*
123	* @returns VBox status code.
124	* @param pVM The cross context VM structure. If NULL, use
125	* the process heap, otherwise the VM's hyper heap.
126	* @param ppaLeaves Pointer to the pointer to the array of sorted
127	* CPUID leaves and sub-leaves. Must be NULL if using
128	* the hyper heap.
129	* @param pcLeaves Where we keep the leaf count for *ppaLeaves. Must
130	* be NULL if using the hyper heap.
131	* @param pNewLeaf Pointer to the data of the new leaf we're about to
132	* insert.
133	*/
134	static int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf)
135	{
136	/*
137	* Validate input parameters if we are using the hyper heap and use the VM's CPUID arrays.
138	*/
139	if (pVM)
140	{
141	AssertReturn(!ppaLeaves, VERR_INVALID_PARAMETER);
142	AssertReturn(!pcLeaves, VERR_INVALID_PARAMETER);
143	AssertReturn(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3 == pVM->cpum.s.GuestInfo.aCpuIdLeaves, VERR_INVALID_PARAMETER);
144
145	ppaLeaves = &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
146	pcLeaves = &pVM->cpum.s.GuestInfo.cCpuIdLeaves;
147	}
148
149	PCPUMCPUIDLEAF paLeaves = *ppaLeaves;
150	uint32_t cLeaves = *pcLeaves;
151
152	/*
153	* Validate the new leaf a little.
154	*/
155	AssertLogRelMsgReturn(!(pNewLeaf->fFlags & ~CPUMCPUIDLEAF_F_VALID_MASK),
156	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fFlags),
157	VERR_INVALID_FLAGS);
158	AssertLogRelMsgReturn(pNewLeaf->fSubLeafMask != 0 \|\| pNewLeaf->uSubLeaf == 0,
159	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
160	VERR_INVALID_PARAMETER);
161	AssertLogRelMsgReturn(RT_IS_POWER_OF_TWO(pNewLeaf->fSubLeafMask + 1),
162	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
163	VERR_INVALID_PARAMETER);
164	AssertLogRelMsgReturn((pNewLeaf->fSubLeafMask & pNewLeaf->uSubLeaf) == pNewLeaf->uSubLeaf,
165	("%#x/%#x: %#x", pNewLeaf->uLeaf, pNewLeaf->uSubLeaf, pNewLeaf->fSubLeafMask),
166	VERR_INVALID_PARAMETER);
167
168	/*
169	* Find insertion point. The lazy bird uses the same excuse as in
170	* cpumCpuIdGetLeaf(), but optimizes for linear insertion (saved state).
171	*/
172	uint32_t i;
173	if ( cLeaves > 0
174	&& paLeaves[cLeaves - 1].uLeaf < pNewLeaf->uLeaf)
175	{
176	/* Add at end. */
177	i = cLeaves;
178	}
179	else if ( cLeaves > 0
180	&& paLeaves[cLeaves - 1].uLeaf == pNewLeaf->uLeaf)
181	{
182	/* Either replacing the last leaf or dealing with sub-leaves. Spool
183	back to the first sub-leaf to pretend we did the linear search. */
184	i = cLeaves - 1;
185	while ( i > 0
186	&& paLeaves[i - 1].uLeaf == pNewLeaf->uLeaf)
187	i--;
188	}
189	else
190	{
191	/* Linear search from the start. */
192	i = 0;
193	while ( i < cLeaves
194	&& paLeaves[i].uLeaf < pNewLeaf->uLeaf)
195	i++;
196	}
197	if ( i < cLeaves
198	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
199	{
200	if (paLeaves[i].fSubLeafMask != pNewLeaf->fSubLeafMask)
201	{
202	/*
203	* The sub-leaf mask differs, replace all existing leaves with the
204	* same leaf number.
205	*/
206	uint32_t c = 1;
207	while ( i + c < cLeaves
208	&& paLeaves[i + c].uLeaf == pNewLeaf->uLeaf)
209	c++;
210	if (c > 1 && i + c < cLeaves)
211	{
212	memmove(&paLeaves[i + c], &paLeaves[i + 1], (cLeaves - i - c) * sizeof(paLeaves[0]));
213	*pcLeaves = cLeaves -= c - 1;
214	}
215
216	paLeaves[i] = *pNewLeaf;
217	#ifdef VBOX_STRICT
218	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
219	#endif
220	return VINF_SUCCESS;
221	}
222
223	/* Find sub-leaf insertion point. */
224	while ( i < cLeaves
225	&& paLeaves[i].uSubLeaf < pNewLeaf->uSubLeaf
226	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf)
227	i++;
228
229	/*
230	* If we've got an exactly matching leaf, replace it.
231	*/
232	if ( i < cLeaves
233	&& paLeaves[i].uLeaf == pNewLeaf->uLeaf
234	&& paLeaves[i].uSubLeaf == pNewLeaf->uSubLeaf)
235	{
236	paLeaves[i] = *pNewLeaf;
237	#ifdef VBOX_STRICT
238	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
239	#endif
240	return VINF_SUCCESS;
241	}
242	}
243
244	/*
245	* Adding a new leaf at 'i'.
246	*/
247	AssertLogRelReturn(cLeaves < CPUM_CPUID_MAX_LEAVES, VERR_TOO_MANY_CPUID_LEAVES);
248	paLeaves = cpumCpuIdEnsureSpace(pVM, ppaLeaves, cLeaves);
249	if (!paLeaves)
250	return VERR_NO_MEMORY;
251
252	if (i < cLeaves)
253	memmove(&paLeaves[i + 1], &paLeaves[i], (cLeaves - i) * sizeof(paLeaves[0]));
254	*pcLeaves += 1;
255	paLeaves[i] = *pNewLeaf;
256
257	#ifdef VBOX_STRICT
258	cpumCpuIdAssertOrder(ppaLeaves, pcLeaves);
259	#endif
260	return VINF_SUCCESS;
261	}
262
263
264	#ifndef IN_VBOX_CPU_REPORT
265	/**
266	* Removes a range of CPUID leaves.
267	*
268	* This will not reallocate the array.
269	*
270	* @param paLeaves The array of sorted CPUID leaves and sub-leaves.
271	* @param pcLeaves Where we keep the leaf count for @a paLeaves.
272	* @param uFirst The first leaf.
273	* @param uLast The last leaf.
274	*/
275	static void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast)
276	{
277	uint32_t cLeaves = *pcLeaves;
278
279	Assert(uFirst <= uLast);
280
281	/*
282	* Find the first one.
283	*/
284	uint32_t iFirst = 0;
285	while ( iFirst < cLeaves
286	&& paLeaves[iFirst].uLeaf < uFirst)
287	iFirst++;
288
289	/*
290	* Find the end (last + 1).
291	*/
292	uint32_t iEnd = iFirst;
293	while ( iEnd < cLeaves
294	&& paLeaves[iEnd].uLeaf <= uLast)
295	iEnd++;
296
297	/*
298	* Adjust the array if anything needs removing.
299	*/
300	if (iFirst < iEnd)
301	{
302	if (iEnd < cLeaves)
303	memmove(&paLeaves[iFirst], &paLeaves[iEnd], (cLeaves - iEnd) * sizeof(paLeaves[0]));
304	*pcLeaves = cLeaves -= (iEnd - iFirst);
305	}
306
307	# ifdef VBOX_STRICT
308	cpumCpuIdAssertOrder(paLeaves, *pcLeaves);
309	# endif
310	}
311	#endif /* IN_VBOX_CPU_REPORT */
312
313
314	/**
315	* Gets a CPU ID leaf.
316	*
317	* @returns VBox status code.
318	* @param pVM The cross context VM structure.
319	* @param pLeaf Where to store the found leaf.
320	* @param uLeaf The leaf to locate.
321	* @param uSubLeaf The subleaf to locate. Pass 0 if no sub-leaves.
322	*/
323	VMMR3DECL(int) CPUMR3CpuIdGetLeaf(PVM pVM, PCPUMCPUIDLEAF pLeaf, uint32_t uLeaf, uint32_t uSubLeaf)
324	{
325	PCPUMCPUIDLEAF pcLeaf = cpumCpuIdGetLeafInt(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
326	uLeaf, uSubLeaf);
327	if (pcLeaf)
328	{
329	memcpy(pLeaf, pcLeaf, sizeof(*pLeaf));
330	return VINF_SUCCESS;
331	}
332
333	return VERR_NOT_FOUND;
334	}
335
336
337	/**
338	* Gets all the leaves.
339	*
340	* This only works after the CPUID leaves have been initialized. The interface
341	* is intended for NEM and configuring CPUID leaves for the native hypervisor.
342	*
343	* @returns Pointer to the array of leaves. NULL on failure.
344	* @param pVM The cross context VM structure.
345	* @param pcLeaves Where to return the number of leaves.
346	*/
347	VMMR3_INT_DECL(PCCPUMCPUIDLEAF) CPUMR3CpuIdGetPtr(PVM pVM, uint32_t *pcLeaves)
348	{
349	*pcLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
350	return pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
351	}
352
353
354	/**
355	* Inserts a CPU ID leaf, replacing any existing ones.
356	*
357	* @returns VBox status code.
358	* @param pVM The cross context VM structure.
359	* @param pNewLeaf Pointer to the leaf being inserted.
360	*/
361	VMMR3DECL(int) CPUMR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF pNewLeaf)
362	{
363	/*
364	* Validate parameters.
365	*/
366	AssertReturn(pVM, VERR_INVALID_PARAMETER);
367	AssertReturn(pNewLeaf, VERR_INVALID_PARAMETER);
368
369	/*
370	* Disallow replacing CPU ID leaves that this API currently cannot manage.
371	* These leaves have dependencies on saved-states, see PATMCpuidReplacement().
372	* If you want to modify these leaves, use CPUMSetGuestCpuIdFeature().
373	*/
374	if ( pNewLeaf->uLeaf == UINT32_C(0x00000000) /* Standard */
375	\|\| pNewLeaf->uLeaf == UINT32_C(0x00000001)
376	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000000) /* Extended */
377	\|\| pNewLeaf->uLeaf == UINT32_C(0x80000001)
378	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000000) /* Centaur */
379	\|\| pNewLeaf->uLeaf == UINT32_C(0xc0000001) )
380	{
381	return VERR_NOT_SUPPORTED;
382	}
383
384	return cpumR3CpuIdInsert(pVM, NULL /* ppaLeaves /, NULL / pcLeaves */, pNewLeaf);
385	}
386
387
388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
389	/**
390	* Determines the method the CPU uses to handle unknown CPUID leaves.
391	*
392	* @returns VBox status code.
393	* @param penmUnknownMethod Where to return the method.
394	* @param pDefUnknown Where to return default unknown values. This
395	* will be set, even if the resulting method
396	* doesn't actually needs it.
397	*/
398	VMMR3DECL(int) CPUMR3CpuIdDetectUnknownLeafMethod(PCPUMUNKNOWNCPUID penmUnknownMethod, PCPUMCPUID pDefUnknown)
399	{
400	uint32_t uLastStd = ASMCpuId_EAX(0);
401	uint32_t uLastExt = ASMCpuId_EAX(0x80000000);
402	if (!RTX86IsValidExtRange(uLastExt))
403	uLastExt = 0x80000000;
404
405	uint32_t auChecks[] =
406	{
407	uLastStd + 1,
408	uLastStd + 5,
409	uLastStd + 8,
410	uLastStd + 32,
411	uLastStd + 251,
412	uLastExt + 1,
413	uLastExt + 8,
414	uLastExt + 15,
415	uLastExt + 63,
416	uLastExt + 255,
417	0x7fbbffcc,
418	0x833f7872,
419	0xefff2353,
420	0x35779456,
421	0x1ef6d33e,
422	};
423
424	static const uint32_t s_auValues[] =
425	{
426	0xa95d2156,
427	0x00000001,
428	0x00000002,
429	0x00000008,
430	0x00000000,
431	0x55773399,
432	0x93401769,
433	0x12039587,
434	};
435
436	/*
437	* Simple method, all zeros.
438	*/
439	*penmUnknownMethod = CPUMUNKNOWNCPUID_DEFAULTS;
440	pDefUnknown->uEax = 0;
441	pDefUnknown->uEbx = 0;
442	pDefUnknown->uEcx = 0;
443	pDefUnknown->uEdx = 0;
444
445	/*
446	* Intel has been observed returning the last standard leaf.
447	*/
448	uint32_t auLast[4];
449	ASMCpuIdExSlow(uLastStd, 0, 0, 0, &auLast[0], &auLast[1], &auLast[2], &auLast[3]);
450
451	uint32_t cChecks = RT_ELEMENTS(auChecks);
452	while (cChecks > 0)
453	{
454	uint32_t auCur[4];
455	ASMCpuIdExSlow(auChecks[cChecks - 1], 0, 0, 0, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
456	if (memcmp(auCur, auLast, sizeof(auCur)))
457	break;
458	cChecks--;
459	}
460	if (cChecks == 0)
461	{
462	/* Now, what happens when the input changes? Esp. ECX. */
463	uint32_t cTotal = 0;
464	uint32_t cSame = 0;
465	uint32_t cLastWithEcx = 0;
466	uint32_t cNeither = 0;
467	uint32_t cValues = RT_ELEMENTS(s_auValues);
468	while (cValues > 0)
469	{
470	uint32_t uValue = s_auValues[cValues - 1];
471	uint32_t auLastWithEcx[4];
472	ASMCpuIdExSlow(uLastStd, uValue, uValue, uValue,
473	&auLastWithEcx[0], &auLastWithEcx[1], &auLastWithEcx[2], &auLastWithEcx[3]);
474
475	cChecks = RT_ELEMENTS(auChecks);
476	while (cChecks > 0)
477	{
478	uint32_t auCur[4];
479	ASMCpuIdExSlow(auChecks[cChecks - 1], uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
480	if (!memcmp(auCur, auLast, sizeof(auCur)))
481	{
482	cSame++;
483	if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
484	cLastWithEcx++;
485	}
486	else if (!memcmp(auCur, auLastWithEcx, sizeof(auCur)))
487	cLastWithEcx++;
488	else
489	cNeither++;
490	cTotal++;
491	cChecks--;
492	}
493	cValues--;
494	}
495
496	Log(("CPUM: cNeither=%d cSame=%d cLastWithEcx=%d cTotal=%d\n", cNeither, cSame, cLastWithEcx, cTotal));
497	if (cSame == cTotal)
498	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
499	else if (cLastWithEcx == cTotal)
500	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX;
501	else
502	*penmUnknownMethod = CPUMUNKNOWNCPUID_LAST_STD_LEAF;
503	pDefUnknown->uEax = auLast[0];
504	pDefUnknown->uEbx = auLast[1];
505	pDefUnknown->uEcx = auLast[2];
506	pDefUnknown->uEdx = auLast[3];
507	return VINF_SUCCESS;
508	}
509
510	/*
511	* Unchanged register values?
512	*/
513	cChecks = RT_ELEMENTS(auChecks);
514	while (cChecks > 0)
515	{
516	uint32_t const uLeaf = auChecks[cChecks - 1];
517	uint32_t cValues = RT_ELEMENTS(s_auValues);
518	while (cValues > 0)
519	{
520	uint32_t uValue = s_auValues[cValues - 1];
521	uint32_t auCur[4];
522	ASMCpuIdExSlow(uLeaf, uValue, uValue, uValue, &auCur[0], &auCur[1], &auCur[2], &auCur[3]);
523	if ( auCur[0] != uLeaf
524	\|\| auCur[1] != uValue
525	\|\| auCur[2] != uValue
526	\|\| auCur[3] != uValue)
527	break;
528	cValues--;
529	}
530	if (cValues != 0)
531	break;
532	cChecks--;
533	}
534	if (cChecks == 0)
535	{
536	*penmUnknownMethod = CPUMUNKNOWNCPUID_PASSTHRU;
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Just go with the simple method.
542	*/
543	return VINF_SUCCESS;
544	}
545	#endif /* RT_ARCH_X86 \|\| RT_ARCH_AMD64 */
546
547
548	/**
549	* Translates a unknow CPUID leaf method into the constant name (sans prefix).
550	*
551	* @returns Read only name string.
552	* @param enmUnknownMethod The method to translate.
553	*/
554	VMMR3DECL(const char *) CPUMR3CpuIdUnknownLeafMethodName(CPUMUNKNOWNCPUID enmUnknownMethod)
555	{
556	switch (enmUnknownMethod)
557	{
558	case CPUMUNKNOWNCPUID_DEFAULTS: return "DEFAULTS";
559	case CPUMUNKNOWNCPUID_LAST_STD_LEAF: return "LAST_STD_LEAF";
560	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX: return "LAST_STD_LEAF_WITH_ECX";
561	case CPUMUNKNOWNCPUID_PASSTHRU: return "PASSTHRU";
562
563	case CPUMUNKNOWNCPUID_INVALID:
564	case CPUMUNKNOWNCPUID_END:
565	case CPUMUNKNOWNCPUID_32BIT_HACK:
566	break;
567	}
568	return "Invalid-unknown-CPUID-method";
569	}
570
571
572	/*
573	*
574	* Init related code.
575	* Init related code.
576	* Init related code.
577	*
578	*
579	*/
580	#ifndef IN_VBOX_CPU_REPORT
581
582
583	/**
584	* Gets an exactly matching leaf + sub-leaf in the CPUID leaf array.
585	*
586	* This ignores the fSubLeafMask.
587	*
588	* @returns Pointer to the matching leaf, or NULL if not found.
589	* @param pCpum The CPUM instance data.
590	* @param uLeaf The leaf to locate.
591	* @param uSubLeaf The subleaf to locate.
592	*/
593	static PCPUMCPUIDLEAF cpumR3CpuIdGetExactLeaf(PCPUM pCpum, uint32_t uLeaf, uint32_t uSubLeaf)
594	{
595	uint64_t uNeedle = RT_MAKE_U64(uSubLeaf, uLeaf);
596	PCPUMCPUIDLEAF paLeaves = pCpum->GuestInfo.paCpuIdLeavesR3;
597	uint32_t iEnd = pCpum->GuestInfo.cCpuIdLeaves;
598	if (iEnd)
599	{
600	uint32_t iBegin = 0;
601	for (;;)
602	{
603	uint32_t const i = (iEnd - iBegin) / 2 + iBegin;
604	uint64_t const uCur = RT_MAKE_U64(paLeaves[i].uSubLeaf, paLeaves[i].uLeaf);
605	if (uNeedle < uCur)
606	{
607	if (i > iBegin)
608	iEnd = i;
609	else
610	break;
611	}
612	else if (uNeedle > uCur)
613	{
614	if (i + 1 < iEnd)
615	iBegin = i + 1;
616	else
617	break;
618	}
619	else
620	return &paLeaves[i];
621	}
622	}
623	return NULL;
624	}
625
626
627	/**
628	* Loads MSR range overrides.
629	*
630	* This must be called before the MSR ranges are moved from the normal heap to
631	* the hyper heap!
632	*
633	* @returns VBox status code (VMSetError called).
634	* @param pVM The cross context VM structure.
635	* @param pMsrNode The CFGM node with the MSR overrides.
636	*/
637	static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
638	{
639	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
640	{
641	/*
642	* Assemble a valid MSR range.
643	*/
644	CPUMMSRRANGE MsrRange;
645	MsrRange.offCpumCpu = 0;
646	MsrRange.fReserved = 0;
647
648	int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
649	if (RT_FAILURE(rc))
650	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
651
652	rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
653	if (RT_FAILURE(rc))
654	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
655	MsrRange.szName, rc);
656
657	rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
658	if (RT_FAILURE(rc))
659	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
660	MsrRange.szName, rc);
661
662	char szType[32];
663	rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
664	if (RT_FAILURE(rc))
665	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
666	MsrRange.szName, rc);
667	if (!RTStrICmp(szType, "FixedValue"))
668	{
669	MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
670	MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
671
672	rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
673	if (RT_FAILURE(rc))
674	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
675	MsrRange.szName, rc);
676
677	rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
678	if (RT_FAILURE(rc))
679	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
680	MsrRange.szName, rc);
681
682	rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
683	if (RT_FAILURE(rc))
684	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
685	MsrRange.szName, rc);
686	}
687	else
688	return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
689	"Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
690
691	/*
692	* Insert the range into the table (replaces/splits/shrinks existing
693	* MSR ranges).
694	*/
695	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
696	&MsrRange);
697	if (RT_FAILURE(rc))
698	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
699	}
700
701	return VINF_SUCCESS;
702	}
703
704
705	/**
706	* Loads CPUID leaf overrides.
707	*
708	* This must be called before the CPUID leaves are moved from the normal
709	* heap to the hyper heap!
710	*
711	* @returns VBox status code (VMSetError called).
712	* @param pVM The cross context VM structure.
713	* @param pParentNode The CFGM node with the CPUID leaves.
714	* @param pszLabel How to label the overrides we're loading.
715	*/
716	static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
717	{
718	for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
719	{
720	/*
721	* Get the leaf and subleaf numbers.
722	*/
723	char szName[128];
724	int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
725	if (RT_FAILURE(rc))
726	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
727
728	/* The leaf number is either specified directly or thru the node name. */
729	uint32_t uLeaf;
730	rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
731	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
732	{
733	rc = RTStrToUInt32Full(szName, 16, &uLeaf);
734	if (rc != VINF_SUCCESS)
735	return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
736	"Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
737	}
738	else if (RT_FAILURE(rc))
739	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
740	pszLabel, szName, rc);
741
742	uint32_t uSubLeaf;
743	rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
744	if (RT_FAILURE(rc))
745	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
746	pszLabel, szName, rc);
747
748	uint32_t fSubLeafMask;
749	rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
750	if (RT_FAILURE(rc))
751	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
752	pszLabel, szName, rc);
753
754	/*
755	* Look up the specified leaf, since the output register values
756	* defaults to any existing values. This allows overriding a single
757	* register, without needing to know the other values.
758	*/
759	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, uLeaf, uSubLeaf);
760	CPUMCPUIDLEAF Leaf;
761	if (pLeaf)
762	Leaf = *pLeaf;
763	else
764	RT_ZERO(Leaf);
765	Leaf.uLeaf = uLeaf;
766	Leaf.uSubLeaf = uSubLeaf;
767	Leaf.fSubLeafMask = fSubLeafMask;
768
769	rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
770	if (RT_FAILURE(rc))
771	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
772	pszLabel, szName, rc);
773	rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
774	if (RT_FAILURE(rc))
775	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
776	pszLabel, szName, rc);
777	rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
778	if (RT_FAILURE(rc))
779	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
780	pszLabel, szName, rc);
781	rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
782	if (RT_FAILURE(rc))
783	return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
784	pszLabel, szName, rc);
785
786	/*
787	* Insert the leaf into the table (replaces existing ones).
788	*/
789	rc = cpumR3CpuIdInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves,
790	&Leaf);
791	if (RT_FAILURE(rc))
792	return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
793	}
794
795	return VINF_SUCCESS;
796	}
797
798
799
800	/**
801	* Fetches overrides for a CPUID leaf.
802	*
803	* @returns VBox status code.
804	* @param pLeaf The leaf to load the overrides into.
805	* @param pCfgNode The CFGM node containing the overrides
806	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
807	* @param iLeaf The CPUID leaf number.
808	*/
809	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
810	{
811	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
812	if (pLeafNode)
813	{
814	uint32_t u32;
815	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
816	if (RT_SUCCESS(rc))
817	pLeaf->uEax = u32;
818	else
819	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
820
821	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
822	if (RT_SUCCESS(rc))
823	pLeaf->uEbx = u32;
824	else
825	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
826
827	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
828	if (RT_SUCCESS(rc))
829	pLeaf->uEcx = u32;
830	else
831	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
832
833	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
834	if (RT_SUCCESS(rc))
835	pLeaf->uEdx = u32;
836	else
837	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
838
839	}
840	return VINF_SUCCESS;
841	}
842
843
844	/**
845	* Load the overrides for a set of CPUID leaves.
846	*
847	* @returns VBox status code.
848	* @param paLeaves The leaf array.
849	* @param cLeaves The number of leaves.
850	* @param uStart The start leaf number.
851	* @param pCfgNode The CFGM node containing the overrides
852	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
853	*/
854	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
855	{
856	for (uint32_t i = 0; i < cLeaves; i++)
857	{
858	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
859	if (RT_FAILURE(rc))
860	return rc;
861	}
862
863	return VINF_SUCCESS;
864	}
865
866
867	/**
868	* Installs the CPUID leaves and explods the data into structures like
869	* GuestFeatures and CPUMCTX::aoffXState.
870	*
871	* @returns VBox status code.
872	* @param pVM The cross context VM structure.
873	* @param pCpum The CPUM part of @a VM.
874	* @param paLeaves The leaves. These will be copied (but not freed).
875	* @param cLeaves The number of leaves.
876	* @param pMsrs The MSRs.
877	*/
878	static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCpum, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
879	{
880	# ifdef VBOX_STRICT
881	cpumCpuIdAssertOrder(paLeaves, cLeaves);
882	# endif
883
884	/*
885	* Install the CPUID information.
886	*/
887	AssertLogRelMsgReturn(cLeaves <= RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves),
888	("cLeaves=%u - max %u\n", cLeaves, RT_ELEMENTS(pVM->cpum.s.GuestInfo.aCpuIdLeaves)),
889	VERR_CPUM_IPE_1); /** @todo better status! */
890	if (paLeaves != pCpum->GuestInfo.aCpuIdLeaves)
891	memcpy(pCpum->GuestInfo.aCpuIdLeaves, paLeaves, cLeaves * sizeof(paLeaves[0]));
892	pCpum->GuestInfo.paCpuIdLeavesR3 = pCpum->GuestInfo.aCpuIdLeaves;
893	pCpum->GuestInfo.cCpuIdLeaves = cLeaves;
894
895	/*
896	* Update the default CPUID leaf if necessary.
897	*/
898	switch (pCpum->GuestInfo.enmUnknownCpuIdMethod)
899	{
900	case CPUMUNKNOWNCPUID_LAST_STD_LEAF:
901	case CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX:
902	{
903	/* We don't use CPUID(0).eax here because of the NT hack that only
904	changes that value without actually removing any leaves. */
905	uint32_t i = 0;
906	if ( pCpum->GuestInfo.cCpuIdLeaves > 0
907	&& pCpum->GuestInfo.paCpuIdLeavesR3[0].uLeaf <= UINT32_C(0xff))
908	{
909	while ( i + 1 < pCpum->GuestInfo.cCpuIdLeaves
910	&& pCpum->GuestInfo.paCpuIdLeavesR3[i + 1].uLeaf <= UINT32_C(0xff))
911	i++;
912	pCpum->GuestInfo.DefCpuId.uEax = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEax;
913	pCpum->GuestInfo.DefCpuId.uEbx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEbx;
914	pCpum->GuestInfo.DefCpuId.uEcx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEcx;
915	pCpum->GuestInfo.DefCpuId.uEdx = pCpum->GuestInfo.paCpuIdLeavesR3[i].uEdx;
916	}
917	break;
918	}
919	default:
920	break;
921	}
922
923	/*
924	* Explode the guest CPU features.
925	*/
926	int rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, pMsrs,
927	&pCpum->GuestFeatures);
928	AssertLogRelRCReturn(rc, rc);
929
930	/*
931	* Adjust the scalable bus frequency according to the CPUID information
932	* we're now using.
933	*/
934	if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
935	pCpum->GuestInfo.uScalableBusFreq = pCpum->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
936	? UINT64_C(100000000) /* 100MHz */
937	: UINT64_C(133333333); /* 133MHz */
938
939	/*
940	* Populate the legacy arrays. Currently used for everything, later only
941	* for patch manager.
942	*/
943	struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
944	{
945	{ pCpum->aGuestCpuIdPatmStd, RT_ELEMENTS(pCpum->aGuestCpuIdPatmStd), 0x00000000 },
946	{ pCpum->aGuestCpuIdPatmExt, RT_ELEMENTS(pCpum->aGuestCpuIdPatmExt), 0x80000000 },
947	{ pCpum->aGuestCpuIdPatmCentaur, RT_ELEMENTS(pCpum->aGuestCpuIdPatmCentaur), 0xc0000000 },
948	};
949	for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
950	{
951	uint32_t cLeft = aOldRanges[i].cCpuIds;
952	uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
953	PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
954	while (cLeft-- > 0)
955	{
956	uLeaf--;
957	pLegacyLeaf--;
958
959	PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, 0 /* uSubLeaf */);
960	if (pLeaf)
961	{
962	pLegacyLeaf->uEax = pLeaf->uEax;
963	pLegacyLeaf->uEbx = pLeaf->uEbx;
964	pLegacyLeaf->uEcx = pLeaf->uEcx;
965	pLegacyLeaf->uEdx = pLeaf->uEdx;
966	}
967	else
968	*pLegacyLeaf = pCpum->GuestInfo.DefCpuId;
969	}
970	}
971
972	/*
973	* Configure XSAVE offsets according to the CPUID info and set the feature flags.
974	*/
975	PVMCPU pVCpu0 = pVM->apCpusR3[0];
976	AssertCompile(sizeof(pVCpu0->cpum.s.Guest.abXState) == CPUM_MAX_XSAVE_AREA_SIZE);
977	memset(&pVCpu0->cpum.s.Guest.aoffXState[0], 0xff, sizeof(pVCpu0->cpum.s.Guest.aoffXState));
978	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_X87_BIT] = 0;
979	pVCpu0->cpum.s.Guest.aoffXState[XSAVE_C_SSE_BIT] = 0;
980	for (uint32_t iComponent = XSAVE_C_SSE_BIT + 1; iComponent < 63; iComponent++)
981	if (pCpum->fXStateGuestMask & RT_BIT_64(iComponent))
982	{
983	PCPUMCPUIDLEAF pSubLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0xd, iComponent);
984	AssertLogRelMsgReturn(pSubLeaf, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
985	AssertLogRelMsgReturn(pSubLeaf->fSubLeafMask >= iComponent, ("iComponent=%#x\n", iComponent), VERR_CPUM_IPE_1);
986	AssertLogRelMsgReturn( pSubLeaf->uEax > 0
987	&& pSubLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
988	&& pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState
989	&& pSubLeaf->uEbx <= pCpum->GuestFeatures.cbMaxExtendedState
990	&& pSubLeaf->uEbx + pSubLeaf->uEax <= pCpum->GuestFeatures.cbMaxExtendedState,
991	("iComponent=%#x eax=%#x ebx=%#x cbMax=%#x\n", iComponent, pSubLeaf->uEax, pSubLeaf->uEbx,
992	pCpum->GuestFeatures.cbMaxExtendedState),
993	VERR_CPUM_IPE_1);
994	pVCpu0->cpum.s.Guest.aoffXState[iComponent] = pSubLeaf->uEbx;
995	}
996
997	/* Copy the CPU #0 data to the other CPUs. */
998	for (VMCPUID idCpu = 1; idCpu < pVM->cCpus; idCpu++)
999	{
1000	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1001	memcpy(&pVCpu->cpum.s.Guest.aoffXState[0], &pVCpu0->cpum.s.Guest.aoffXState[0], sizeof(pVCpu0->cpum.s.Guest.aoffXState));
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/** @name Instruction Set Extension Options
1009	* @{ */
1010	/** Configuration option type (extended boolean, really). */
1011	typedef uint8_t CPUMISAEXTCFG;
1012	/** Always disable the extension. */
1013	#define CPUMISAEXTCFG_DISABLED false
1014	/** Enable the extension if it's supported by the host CPU. */
1015	#define CPUMISAEXTCFG_ENABLED_SUPPORTED true
1016	/** Enable the extension if it's supported by the host CPU, but don't let
1017	* the portable CPUID feature disable it. */
1018	#define CPUMISAEXTCFG_ENABLED_PORTABLE UINT8_C(127)
1019	/** Always enable the extension. */
1020	#define CPUMISAEXTCFG_ENABLED_ALWAYS UINT8_C(255)
1021	/** @} */
1022
1023	/**
1024	* CPUID Configuration (from CFGM).
1025	*
1026	* @remarks The members aren't document since we would only be duplicating the
1027	* \@cfgm entries in cpumR3CpuIdReadConfig.
1028	*/
1029	typedef struct CPUMCPUIDCONFIG
1030	{
1031	bool fNt4LeafLimit;
1032	bool fInvariantTsc;
1033	bool fInvariantApic;
1034	bool fForceVme;
1035	bool fNestedHWVirt;
1036
1037	CPUMISAEXTCFG enmCmpXchg16b;
1038	CPUMISAEXTCFG enmMonitor;
1039	CPUMISAEXTCFG enmMWaitExtensions;
1040	CPUMISAEXTCFG enmSse41;
1041	CPUMISAEXTCFG enmSse42;
1042	CPUMISAEXTCFG enmAvx;
1043	CPUMISAEXTCFG enmAvx2;
1044	CPUMISAEXTCFG enmXSave;
1045	CPUMISAEXTCFG enmAesNi;
1046	CPUMISAEXTCFG enmPClMul;
1047	CPUMISAEXTCFG enmPopCnt;
1048	CPUMISAEXTCFG enmMovBe;
1049	CPUMISAEXTCFG enmRdRand;
1050	CPUMISAEXTCFG enmRdSeed;
1051	CPUMISAEXTCFG enmSha;
1052	CPUMISAEXTCFG enmAdx;
1053	CPUMISAEXTCFG enmCLFlushOpt;
1054	CPUMISAEXTCFG enmFsGsBase;
1055	CPUMISAEXTCFG enmPcid;
1056	CPUMISAEXTCFG enmInvpcid;
1057	CPUMISAEXTCFG enmFlushCmdMsr;
1058	CPUMISAEXTCFG enmMdsClear;
1059	CPUMISAEXTCFG enmArchCapMsr;
1060
1061	CPUMISAEXTCFG enmAbm;
1062	CPUMISAEXTCFG enmSse4A;
1063	CPUMISAEXTCFG enmMisAlnSse;
1064	CPUMISAEXTCFG enm3dNowPrf;
1065	CPUMISAEXTCFG enmAmdExtMmx;
1066
1067	uint32_t uMaxStdLeaf;
1068	uint32_t uMaxExtLeaf;
1069	uint32_t uMaxCentaurLeaf;
1070	uint32_t uMaxIntelFamilyModelStep;
1071	char szCpuName[128];
1072	} CPUMCPUIDCONFIG;
1073	/** Pointer to CPUID config (from CFGM). */
1074	typedef CPUMCPUIDCONFIG *PCPUMCPUIDCONFIG;
1075
1076
1077	/**
1078	* Mini CPU selection support for making Mac OS X happy.
1079	*
1080	* Executes the /CPUM/MaxIntelFamilyModelStep config.
1081	*
1082	* @param pCpum The CPUM instance data.
1083	* @param pConfig The CPUID configuration we've read from CFGM.
1084	*/
1085	static void cpumR3CpuIdLimitIntelFamModStep(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1086	{
1087	if (pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1088	{
1089	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1090	uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(RTX86GetCpuStepping(pStdFeatureLeaf->uEax),
1091	RTX86GetCpuModelIntel(pStdFeatureLeaf->uEax),
1092	RTX86GetCpuFamily(pStdFeatureLeaf->uEax),
1093	0);
1094	uint32_t uMaxIntelFamilyModelStep = pConfig->uMaxIntelFamilyModelStep;
1095	if (pConfig->uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1096	{
1097	uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1098	uNew \|= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1099	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1100	uNew \|= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1101	uNew \|= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1102	if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1103	uNew \|= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1104	LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1105	pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1106	pStdFeatureLeaf->uEax = uNew;
1107	}
1108	}
1109	}
1110
1111
1112
1113	/**
1114	* Limit it the number of entries, zapping the remainder.
1115	*
1116	* The limits are masking off stuff about power saving and similar, this
1117	* is perhaps a bit crudely done as there is probably some relatively harmless
1118	* info too in these leaves (like words about having a constant TSC).
1119	*
1120	* @param pCpum The CPUM instance data.
1121	* @param pConfig The CPUID configuration we've read from CFGM.
1122	*/
1123	static void cpumR3CpuIdLimitLeaves(PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1124	{
1125	/*
1126	* Standard leaves.
1127	*/
1128	uint32_t uSubLeaf = 0;
1129	PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0, uSubLeaf);
1130	if (pCurLeaf)
1131	{
1132	uint32_t uLimit = pCurLeaf->uEax;
1133	if (uLimit <= UINT32_C(0x000fffff))
1134	{
1135	if (uLimit > pConfig->uMaxStdLeaf)
1136	{
1137	pCurLeaf->uEax = uLimit = pConfig->uMaxStdLeaf;
1138	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1139	uLimit + 1, UINT32_C(0x000fffff));
1140	}
1141
1142	/* NT4 hack, no zapping of extra leaves here. */
1143	if (pConfig->fNt4LeafLimit && uLimit > 3)
1144	pCurLeaf->uEax = uLimit = 3;
1145
1146	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x00000000), ++uSubLeaf)) != NULL)
1147	pCurLeaf->uEax = uLimit;
1148	}
1149	else
1150	{
1151	LogRel(("CPUID: Invalid standard range: %#x\n", uLimit));
1152	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1153	UINT32_C(0x00000000), UINT32_C(0x0fffffff));
1154	}
1155	}
1156
1157	/*
1158	* Extended leaves.
1159	*/
1160	uSubLeaf = 0;
1161	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), uSubLeaf);
1162	if (pCurLeaf)
1163	{
1164	uint32_t uLimit = pCurLeaf->uEax;
1165	if ( uLimit >= UINT32_C(0x80000000)
1166	&& uLimit <= UINT32_C(0x800fffff))
1167	{
1168	if (uLimit > pConfig->uMaxExtLeaf)
1169	{
1170	pCurLeaf->uEax = uLimit = pConfig->uMaxExtLeaf;
1171	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1172	uLimit + 1, UINT32_C(0x800fffff));
1173	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000000), ++uSubLeaf)) != NULL)
1174	pCurLeaf->uEax = uLimit;
1175	}
1176	}
1177	else
1178	{
1179	LogRel(("CPUID: Invalid extended range: %#x\n", uLimit));
1180	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1181	UINT32_C(0x80000000), UINT32_C(0x8ffffffd));
1182	}
1183	}
1184
1185	/*
1186	* Centaur leaves (VIA).
1187	*/
1188	uSubLeaf = 0;
1189	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), uSubLeaf);
1190	if (pCurLeaf)
1191	{
1192	uint32_t uLimit = pCurLeaf->uEax;
1193	if ( uLimit >= UINT32_C(0xc0000000)
1194	&& uLimit <= UINT32_C(0xc00fffff))
1195	{
1196	if (uLimit > pConfig->uMaxCentaurLeaf)
1197	{
1198	pCurLeaf->uEax = uLimit = pConfig->uMaxCentaurLeaf;
1199	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1200	uLimit + 1, UINT32_C(0xcfffffff));
1201	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000000), ++uSubLeaf)) != NULL)
1202	pCurLeaf->uEax = uLimit;
1203	}
1204	}
1205	else
1206	{
1207	LogRel(("CPUID: Invalid centaur range: %#x\n", uLimit));
1208	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
1209	UINT32_C(0xc0000000), UINT32_C(0xcfffffff));
1210	}
1211	}
1212	}
1213
1214
1215	/**
1216	* Clears a CPUID leaf and all sub-leaves (to zero).
1217	*
1218	* @param pCpum The CPUM instance data.
1219	* @param uLeaf The leaf to clear.
1220	*/
1221	static void cpumR3CpuIdZeroLeaf(PCPUM pCpum, uint32_t uLeaf)
1222	{
1223	uint32_t uSubLeaf = 0;
1224	PCPUMCPUIDLEAF pCurLeaf;
1225	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, uLeaf, uSubLeaf)) != NULL)
1226	{
1227	pCurLeaf->uEax = 0;
1228	pCurLeaf->uEbx = 0;
1229	pCurLeaf->uEcx = 0;
1230	pCurLeaf->uEdx = 0;
1231	uSubLeaf++;
1232	}
1233	}
1234
1235
1236	/**
1237	* Used by cpumR3CpuIdSanitize to ensure that we don't have any sub-leaves for
1238	* the given leaf.
1239	*
1240	* @returns pLeaf.
1241	* @param pCpum The CPUM instance data.
1242	* @param pLeaf The leaf to ensure is alone with it's EAX input value.
1243	*/
1244	static PCPUMCPUIDLEAF cpumR3CpuIdMakeSingleLeaf(PCPUM pCpum, PCPUMCPUIDLEAF pLeaf)
1245	{
1246	Assert((uintptr_t)(pLeaf - pCpum->GuestInfo.paCpuIdLeavesR3) < pCpum->GuestInfo.cCpuIdLeaves);
1247	if (pLeaf->fSubLeafMask != 0)
1248	{
1249	/*
1250	* Figure out how many sub-leaves in need of removal (we'll keep the first).
1251	* Log everything while we're at it.
1252	*/
1253	LogRel(("CPUM:\n"
1254	"CPUM: Unexpected CPUID sub-leaves for leaf %#x; fSubLeafMask=%#x\n", pLeaf->uLeaf, pLeaf->fSubLeafMask));
1255	PCPUMCPUIDLEAF pLast = &pCpum->GuestInfo.paCpuIdLeavesR3[pCpum->GuestInfo.cCpuIdLeaves - 1];
1256	PCPUMCPUIDLEAF pSubLeaf = pLeaf;
1257	for (;;)
1258	{
1259	LogRel(("CPUM: %08x/%08x: %08x %08x %08x %08x; flags=%#x mask=%#x\n",
1260	pSubLeaf->uLeaf, pSubLeaf->uSubLeaf,
1261	pSubLeaf->uEax, pSubLeaf->uEbx, pSubLeaf->uEcx, pSubLeaf->uEdx,
1262	pSubLeaf->fFlags, pSubLeaf->fSubLeafMask));
1263	if (pSubLeaf == pLast \|\| pSubLeaf[1].uLeaf != pLeaf->uLeaf)
1264	break;
1265	pSubLeaf++;
1266	}
1267	LogRel(("CPUM:\n"));
1268
1269	/*
1270	* Remove the offending sub-leaves.
1271	*/
1272	if (pSubLeaf != pLeaf)
1273	{
1274	if (pSubLeaf != pLast)
1275	memmove(pLeaf + 1, pSubLeaf + 1, (uintptr_t)pLast - (uintptr_t)pSubLeaf);
1276	pCpum->GuestInfo.cCpuIdLeaves -= (uint32_t)(pSubLeaf - pLeaf);
1277	}
1278
1279	/*
1280	* Convert the first sub-leaf into a single leaf.
1281	*/
1282	pLeaf->uSubLeaf = 0;
1283	pLeaf->fSubLeafMask = 0;
1284	}
1285	return pLeaf;
1286	}
1287
1288
1289	/**
1290	* Sanitizes and adjust the CPUID leaves.
1291	*
1292	* Drop features that aren't virtualized (or virtualizable). Adjust information
1293	* and capabilities to fit the virtualized hardware. Remove information the
1294	* guest shouldn't have (because it's wrong in the virtual world or because it
1295	* gives away host details) or that we don't have documentation for and no idea
1296	* what means.
1297	*
1298	* @returns VBox status code.
1299	* @param pVM The cross context VM structure (for cCpus).
1300	* @param pCpum The CPUM instance data.
1301	* @param pConfig The CPUID configuration we've read from CFGM.
1302	*/
1303	static int cpumR3CpuIdSanitize(PVM pVM, PCPUM pCpum, PCPUMCPUIDCONFIG pConfig)
1304	{
1305	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1306	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1307	{ \
1308	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1309	(a_pLeafReg) &= ~(uint32_t)(fMask); \
1310	}
1311	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1312	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1313	{ \
1314	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1315	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1316	}
1317	#define PORTABLE_DISABLE_FEATURE_BIT_CFG(Lvl, a_pLeafReg, FeatNm, fBitMask, enmConfig) \
1318	if ( pCpum->u8PortableCpuIdLevel >= (Lvl) \
1319	&& ((a_pLeafReg) & (fBitMask)) \
1320	&& (enmConfig) != CPUMISAEXTCFG_ENABLED_PORTABLE ) \
1321	{ \
1322	LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1323	(a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1324	}
1325	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1326
1327	/* The CPUID entries we start with here isn't necessarily the ones of the host, so we
1328	must consult HostFeatures when processing CPUMISAEXTCFG variables. */
1329	PCCPUMFEATURES pHstFeat = &pCpum->HostFeatures;
1330	#define PASSTHRU_FEATURE(enmConfig, fHostFeature, fConst) \
1331	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) ? (fConst) : 0)
1332	#define PASSTHRU_FEATURE_EX(enmConfig, fHostFeature, fAndExpr, fConst) \
1333	((enmConfig) && ((enmConfig) == CPUMISAEXTCFG_ENABLED_ALWAYS \|\| (fHostFeature)) && (fAndExpr) ? (fConst) : 0)
1334	#define PASSTHRU_FEATURE_TODO(enmConfig, fConst) ((enmConfig) ? (fConst) : 0)
1335
1336	/* Cpuid 1:
1337	* EAX: CPU model, family and stepping.
1338	*
1339	* ECX + EDX: Supported features. Only report features we can support.
1340	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1341	* options may require adjusting (i.e. stripping what was enabled).
1342	*
1343	* EBX: Branding, CLFLUSH line size, logical processors per package and
1344	* initial APIC ID.
1345	*/
1346	PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0); /* Note! Must refetch when used later. */
1347	AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1348	pStdFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pStdFeatureLeaf);
1349
1350	pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1351	\| X86_CPUID_FEATURE_EDX_VME
1352	\| X86_CPUID_FEATURE_EDX_DE
1353	\| X86_CPUID_FEATURE_EDX_PSE
1354	\| X86_CPUID_FEATURE_EDX_TSC
1355	\| X86_CPUID_FEATURE_EDX_MSR
1356	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1357	\| X86_CPUID_FEATURE_EDX_MCE
1358	\| X86_CPUID_FEATURE_EDX_CX8
1359	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1360	//\| RT_BIT_32(10) - not defined
1361	\| X86_CPUID_FEATURE_EDX_SEP
1362	\| X86_CPUID_FEATURE_EDX_MTRR
1363	\| X86_CPUID_FEATURE_EDX_PGE
1364	\| X86_CPUID_FEATURE_EDX_MCA
1365	\| X86_CPUID_FEATURE_EDX_CMOV
1366	\| X86_CPUID_FEATURE_EDX_PAT /* 16 */
1367	\| X86_CPUID_FEATURE_EDX_PSE36
1368	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1369	\| X86_CPUID_FEATURE_EDX_CLFSH
1370	//\| RT_BIT_32(20) - not defined
1371	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
1372	//\| X86_CPUID_FEATURE_EDX_ACPI - not supported (not DevAcpi, right?).
1373	\| X86_CPUID_FEATURE_EDX_MMX
1374	\| X86_CPUID_FEATURE_EDX_FXSR
1375	\| X86_CPUID_FEATURE_EDX_SSE
1376	\| X86_CPUID_FEATURE_EDX_SSE2
1377	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1378	\| X86_CPUID_FEATURE_EDX_HTT
1379	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1380	//\| RT_BIT_32(30) - not defined
1381	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1382	;
1383	pStdFeatureLeaf->uEcx &= X86_CPUID_FEATURE_ECX_SSE3
1384	\| PASSTHRU_FEATURE_TODO(pConfig->enmPClMul, X86_CPUID_FEATURE_ECX_PCLMUL)
1385	//\| X86_CPUID_FEATURE_ECX_DTES64 - not implemented yet.
1386	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1387	\| PASSTHRU_FEATURE_EX(pConfig->enmMonitor, pHstFeat->fMonitorMWait, pVM->cCpus == 1, X86_CPUID_FEATURE_ECX_MONITOR)
1388	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1389	\| (pConfig->fNestedHWVirt ? X86_CPUID_FEATURE_ECX_VMX : 0)
1390	//\| X86_CPUID_FEATURE_ECX_SMX - not virtualized yet.
1391	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1392	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1393	\| X86_CPUID_FEATURE_ECX_SSSE3
1394	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1395	//\| X86_CPUID_FEATURE_ECX_FMA - not implemented yet.
1396	\| PASSTHRU_FEATURE(pConfig->enmCmpXchg16b, pHstFeat->fCmpXchg16b, X86_CPUID_FEATURE_ECX_CX16)
1397	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1398	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1399	//\| X86_CPUID_FEATURE_ECX_PDCM - not implemented yet.
1400	\| PASSTHRU_FEATURE(pConfig->enmPcid, pHstFeat->fPcid, X86_CPUID_FEATURE_ECX_PCID)
1401	//\| X86_CPUID_FEATURE_ECX_DCA - not implemented yet.
1402	\| PASSTHRU_FEATURE(pConfig->enmSse41, pHstFeat->fSse41, X86_CPUID_FEATURE_ECX_SSE4_1)
1403	\| PASSTHRU_FEATURE(pConfig->enmSse42, pHstFeat->fSse42, X86_CPUID_FEATURE_ECX_SSE4_2)
1404	//\| X86_CPUID_FEATURE_ECX_X2APIC - turned on later by the device if enabled.
1405	\| PASSTHRU_FEATURE(pConfig->enmMovBe, pHstFeat->fMovBe, X86_CPUID_FEATURE_ECX_MOVBE)
1406	\| PASSTHRU_FEATURE(pConfig->enmPopCnt, pHstFeat->fPopCnt, X86_CPUID_FEATURE_ECX_POPCNT)
1407	//\| X86_CPUID_FEATURE_ECX_TSCDEADL - not implemented yet.
1408	\| PASSTHRU_FEATURE_TODO(pConfig->enmAesNi, X86_CPUID_FEATURE_ECX_AES)
1409	\| PASSTHRU_FEATURE(pConfig->enmXSave, pHstFeat->fXSaveRstor, X86_CPUID_FEATURE_ECX_XSAVE)
1410	//\| X86_CPUID_FEATURE_ECX_OSXSAVE - mirrors CR4.OSXSAVE state, set dynamically.
1411	\| PASSTHRU_FEATURE(pConfig->enmAvx, pHstFeat->fAvx, X86_CPUID_FEATURE_ECX_AVX)
1412	//\| X86_CPUID_FEATURE_ECX_F16C - not implemented yet.
1413	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdRand, X86_CPUID_FEATURE_ECX_RDRAND)
1414	//\| X86_CPUID_FEATURE_ECX_HVP - Set explicitly later.
1415	;
1416
1417	/* Mask out PCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1418	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1419	&& (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_PCID))
1420	{
1421	pStdFeatureLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_PCID;
1422	LogRel(("CPUM: Disabled PCID without FSGSBASE to workaround buggy guests\n"));
1423	}
1424
1425	if (pCpum->u8PortableCpuIdLevel > 0)
1426	{
1427	PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1428	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1429	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCID, X86_CPUID_FEATURE_ECX_PCID, pConfig->enmPcid);
1430	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1, pConfig->enmSse41);
1431	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2, pConfig->enmSse42);
1432	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, MOVBE, X86_CPUID_FEATURE_ECX_MOVBE, pConfig->enmMovBe);
1433	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, AES, X86_CPUID_FEATURE_ECX_AES);
1434	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, VMX, X86_CPUID_FEATURE_ECX_VMX);
1435	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, PCLMUL, X86_CPUID_FEATURE_ECX_PCLMUL, pConfig->enmPClMul);
1436	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, POPCNT, X86_CPUID_FEATURE_ECX_POPCNT, pConfig->enmPopCnt);
1437	PORTABLE_DISABLE_FEATURE_BIT( 1, pStdFeatureLeaf->uEcx, F16C, X86_CPUID_FEATURE_ECX_F16C);
1438	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, XSAVE, X86_CPUID_FEATURE_ECX_XSAVE, pConfig->enmXSave);
1439	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, AVX, X86_CPUID_FEATURE_ECX_AVX, pConfig->enmAvx);
1440	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, RDRAND, X86_CPUID_FEATURE_ECX_RDRAND, pConfig->enmRdRand);
1441	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16, pConfig->enmCmpXchg16b);
1442	PORTABLE_DISABLE_FEATURE_BIT( 2, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1443	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1444	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1445	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1446	PORTABLE_DISABLE_FEATURE_BIT( 3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1447
1448	Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP ///??
1449	\| X86_CPUID_FEATURE_EDX_PSN
1450	\| X86_CPUID_FEATURE_EDX_DS
1451	\| X86_CPUID_FEATURE_EDX_ACPI
1452	\| X86_CPUID_FEATURE_EDX_SS
1453	\| X86_CPUID_FEATURE_EDX_TM
1454	\| X86_CPUID_FEATURE_EDX_PBE
1455	)));
1456	Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_DTES64
1457	\| X86_CPUID_FEATURE_ECX_CPLDS
1458	\| X86_CPUID_FEATURE_ECX_AES
1459	\| X86_CPUID_FEATURE_ECX_VMX
1460	\| X86_CPUID_FEATURE_ECX_SMX
1461	\| X86_CPUID_FEATURE_ECX_EST
1462	\| X86_CPUID_FEATURE_ECX_TM2
1463	\| X86_CPUID_FEATURE_ECX_CNTXID
1464	\| X86_CPUID_FEATURE_ECX_FMA
1465	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
1466	\| X86_CPUID_FEATURE_ECX_PDCM
1467	\| X86_CPUID_FEATURE_ECX_DCA
1468	\| X86_CPUID_FEATURE_ECX_OSXSAVE
1469	)));
1470	}
1471
1472	/* Set up APIC ID for CPU 0, configure multi core/threaded smp. */
1473	pStdFeatureLeaf->uEbx &= UINT32_C(0x0000ffff); /* (APIC-ID := 0 and #LogCpus := 0) */
1474
1475	/* The HTT bit is architectural and does not directly indicate hyper-threading or multiple cores;
1476	* it was set even on single-core/non-HT Northwood P4s for example. The HTT bit only means that the
1477	* information in EBX[23:16] (max number of addressable logical processor IDs) is valid.
1478	*/
1479	#ifdef VBOX_WITH_MULTI_CORE
1480	if (pVM->cCpus > 1)
1481	pStdFeatureLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_HTT; /* Force if emulating a multi-core CPU. */
1482	#endif
1483	if (pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_HTT)
1484	{
1485	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU
1486	core times the number of CPU cores per processor */
1487	#ifdef VBOX_WITH_MULTI_CORE
1488	pStdFeatureLeaf->uEbx \|= pVM->cCpus <= 0xff ? (pVM->cCpus << 16) : UINT32_C(0x00ff0000);
1489	#else
1490	/* Single logical processor in a package. */
1491	pStdFeatureLeaf->uEbx \|= (1 << 16);
1492	#endif
1493	}
1494
1495	uint32_t uMicrocodeRev;
1496	int rc = SUPR3QueryMicrocodeRev(&uMicrocodeRev);
1497	if (RT_SUCCESS(rc))
1498	{
1499	LogRel(("CPUM: Microcode revision 0x%08X\n", uMicrocodeRev));
1500	}
1501	else
1502	{
1503	uMicrocodeRev = 0;
1504	LogRel(("CPUM: Failed to query microcode revision. rc=%Rrc\n", rc));
1505	}
1506
1507	/* Mask out the VME capability on certain CPUs, unless overridden by fForceVme.
1508	* VME bug was fixed in AGESA 1.0.0.6, microcode patch level 8001126.
1509	*/
1510	if ( ( pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_AMD_Zen_Ryzen
1511	/** @todo The following ASSUMES that Hygon uses the same version numbering
1512	* as AMD and that they shipped buggy firmware. */
1513	\|\| pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Hygon_Dhyana)
1514	&& uMicrocodeRev < 0x8001126
1515	&& !pConfig->fForceVme)
1516	{
1517	/** @todo The above is a very coarse test but at the moment we don't know any better (see @bugref{8852}). */
1518	LogRel(("CPUM: Zen VME workaround engaged\n"));
1519	pStdFeatureLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_VME;
1520	}
1521
1522	/* Force standard feature bits. */
1523	if (pConfig->enmPClMul == CPUMISAEXTCFG_ENABLED_ALWAYS)
1524	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_PCLMUL;
1525	if (pConfig->enmMonitor == CPUMISAEXTCFG_ENABLED_ALWAYS)
1526	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MONITOR;
1527	if (pConfig->enmCmpXchg16b == CPUMISAEXTCFG_ENABLED_ALWAYS)
1528	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_CX16;
1529	if (pConfig->enmSse41 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1530	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_1;
1531	if (pConfig->enmSse42 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1532	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_SSE4_2;
1533	if (pConfig->enmMovBe == CPUMISAEXTCFG_ENABLED_ALWAYS)
1534	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_MOVBE;
1535	if (pConfig->enmPopCnt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1536	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_POPCNT;
1537	if (pConfig->enmAesNi == CPUMISAEXTCFG_ENABLED_ALWAYS)
1538	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AES;
1539	if (pConfig->enmXSave == CPUMISAEXTCFG_ENABLED_ALWAYS)
1540	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_XSAVE;
1541	if (pConfig->enmAvx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1542	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_AVX;
1543	if (pConfig->enmRdRand == CPUMISAEXTCFG_ENABLED_ALWAYS)
1544	pStdFeatureLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_RDRAND;
1545
1546	pStdFeatureLeaf = NULL; /* Must refetch! */
1547
1548	/* Cpuid 0x80000001: (Similar, but in no way identical to 0x00000001.)
1549	* AMD:
1550	* EAX: CPU model, family and stepping.
1551	*
1552	* ECX + EDX: Supported features. Only report features we can support.
1553	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1554	* options may require adjusting (i.e. stripping what was enabled).
1555	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
1556	*
1557	* EBX: Branding ID and package type (or reserved).
1558	*
1559	* Intel and probably most others:
1560	* EAX: 0
1561	* EBX: 0
1562	* ECX + EDX: Subset of AMD features, mainly for AMD64 support.
1563	*/
1564	PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
1565	if (pExtFeatureLeaf)
1566	{
1567	pExtFeatureLeaf = cpumR3CpuIdMakeSingleLeaf(pCpum, pExtFeatureLeaf);
1568
1569	pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1570	\| X86_CPUID_AMD_FEATURE_EDX_VME
1571	\| X86_CPUID_AMD_FEATURE_EDX_DE
1572	\| X86_CPUID_AMD_FEATURE_EDX_PSE
1573	\| X86_CPUID_AMD_FEATURE_EDX_TSC
1574	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1575	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - turned on when necessary
1576	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1577	\| X86_CPUID_AMD_FEATURE_EDX_CX8
1578	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1579	//\| RT_BIT_32(10) - reserved
1580	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1581	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
1582	\| X86_CPUID_AMD_FEATURE_EDX_PGE
1583	\| X86_CPUID_AMD_FEATURE_EDX_MCA
1584	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
1585	\| X86_CPUID_AMD_FEATURE_EDX_PAT
1586	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
1587	//\| RT_BIT_32(18) - reserved
1588	//\| RT_BIT_32(19) - reserved
1589	\| X86_CPUID_EXT_FEATURE_EDX_NX
1590	//\| RT_BIT_32(21) - reserved
1591	\| PASSTHRU_FEATURE(pConfig->enmAmdExtMmx, pHstFeat->fAmdMmxExts, X86_CPUID_AMD_FEATURE_EDX_AXMMX)
1592	\| X86_CPUID_AMD_FEATURE_EDX_MMX
1593	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
1594	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
1595	//\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1596	\| X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1597	//\| RT_BIT_32(28) - reserved
1598	//\| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1599	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1600	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
1601	;
1602	pExtFeatureLeaf->uEcx &= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1603	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL - set below if applicable.
1604	\| (pConfig->fNestedHWVirt ? X86_CPUID_AMD_FEATURE_ECX_SVM : 0)
1605	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1606	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
1607	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1608	\| PASSTHRU_FEATURE(pConfig->enmAbm, pHstFeat->fAbm, X86_CPUID_AMD_FEATURE_ECX_ABM)
1609	\| PASSTHRU_FEATURE_TODO(pConfig->enmSse4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A)
1610	\| PASSTHRU_FEATURE_TODO(pConfig->enmMisAlnSse, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE)
1611	\| PASSTHRU_FEATURE(pConfig->enm3dNowPrf, pHstFeat->f3DNowPrefetch, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF)
1612	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1613	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
1614	//\| X86_CPUID_AMD_FEATURE_ECX_XOP
1615	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1616	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
1617	//\| RT_BIT_32(14) - reserved
1618	//\| X86_CPUID_AMD_FEATURE_ECX_LWP - not supported
1619	//\| X86_CPUID_AMD_FEATURE_ECX_FMA4 - not yet virtualized.
1620	//\| RT_BIT_32(17) - reserved
1621	//\| RT_BIT_32(18) - reserved
1622	//\| X86_CPUID_AMD_FEATURE_ECX_NODEID - not yet virtualized.
1623	//\| RT_BIT_32(20) - reserved
1624	//\| X86_CPUID_AMD_FEATURE_ECX_TBM - not yet virtualized.
1625	//\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT - not yet virtualized.
1626	//\| RT_BIT_32(23) - reserved
1627	//\| RT_BIT_32(24) - reserved
1628	//\| RT_BIT_32(25) - reserved
1629	//\| RT_BIT_32(26) - reserved
1630	//\| RT_BIT_32(27) - reserved
1631	//\| RT_BIT_32(28) - reserved
1632	//\| RT_BIT_32(29) - reserved
1633	//\| RT_BIT_32(30) - reserved
1634	//\| RT_BIT_32(31) - reserved
1635	;
1636	#ifdef VBOX_WITH_MULTI_CORE
1637	if ( pVM->cCpus > 1
1638	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
1639	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
1640	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL; /* CmpLegacy */
1641	#endif
1642
1643	if (pCpum->u8PortableCpuIdLevel > 0)
1644	{
1645	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1646	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, SVM, X86_CPUID_AMD_FEATURE_ECX_SVM);
1647	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, ABM, X86_CPUID_AMD_FEATURE_ECX_ABM, pConfig->enmAbm);
1648	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, SSE4A, X86_CPUID_AMD_FEATURE_ECX_SSE4A, pConfig->enmSse4A);
1649	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, MISALNSSE, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE, pConfig->enmMisAlnSse);
1650	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEcx, 3DNOWPRF, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF, pConfig->enm3dNowPrf);
1651	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, XOP, X86_CPUID_AMD_FEATURE_ECX_XOP);
1652	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, TBM, X86_CPUID_AMD_FEATURE_ECX_TBM);
1653	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEcx, FMA4, X86_CPUID_AMD_FEATURE_ECX_FMA4);
1654	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pExtFeatureLeaf->uEdx, AXMMX, X86_CPUID_AMD_FEATURE_EDX_AXMMX, pConfig->enmAmdExtMmx);
1655	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1656	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1657	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1658	PORTABLE_DISABLE_FEATURE_BIT( 1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1659	PORTABLE_DISABLE_FEATURE_BIT( 2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1660	PORTABLE_DISABLE_FEATURE_BIT( 3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1661
1662	Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_SVM
1663	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1664	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
1665	\| X86_CPUID_AMD_FEATURE_ECX_IBS
1666	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1667	\| X86_CPUID_AMD_FEATURE_ECX_WDT
1668	\| X86_CPUID_AMD_FEATURE_ECX_LWP
1669	\| X86_CPUID_AMD_FEATURE_ECX_NODEID
1670	\| X86_CPUID_AMD_FEATURE_ECX_TOPOEXT
1671	\| UINT32_C(0xff964000)
1672	)));
1673	Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1674	\| X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1675	\| RT_BIT(18)
1676	\| RT_BIT(19)
1677	\| RT_BIT(21)
1678	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1679	\| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1680	\| RT_BIT(28)
1681	)));
1682	}
1683
1684	/* Force extended feature bits. */
1685	if (pConfig->enmAbm == CPUMISAEXTCFG_ENABLED_ALWAYS)
1686	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_ABM;
1687	if (pConfig->enmSse4A == CPUMISAEXTCFG_ENABLED_ALWAYS)
1688	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_SSE4A;
1689	if (pConfig->enmMisAlnSse == CPUMISAEXTCFG_ENABLED_ALWAYS)
1690	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_MISALNSSE;
1691	if (pConfig->enm3dNowPrf == CPUMISAEXTCFG_ENABLED_ALWAYS)
1692	pExtFeatureLeaf->uEcx \|= X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF;
1693	if (pConfig->enmAmdExtMmx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1694	pExtFeatureLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_AXMMX;
1695	}
1696	pExtFeatureLeaf = NULL; /* Must refetch! */
1697
1698
1699	/* Cpuid 2:
1700	* Intel: (Nondeterministic) Cache and TLB information
1701	* AMD: Reserved
1702	* VIA: Reserved
1703	* Safe to expose.
1704	*/
1705	uint32_t uSubLeaf = 0;
1706	PCPUMCPUIDLEAF pCurLeaf;
1707	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 2, uSubLeaf)) != NULL)
1708	{
1709	if ((pCurLeaf->uEax & 0xff) > 1)
1710	{
1711	LogRel(("CpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1712	pCurLeaf->uEax &= UINT32_C(0xffffff01);
1713	}
1714	uSubLeaf++;
1715	}
1716
1717	/* Cpuid 3:
1718	* Intel: EAX, EBX - reserved (transmeta uses these)
1719	* ECX, EDX - Processor Serial Number if available, otherwise reserved
1720	* AMD: Reserved
1721	* VIA: Reserved
1722	* Safe to expose
1723	*/
1724	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1725	if (!(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN))
1726	{
1727	uSubLeaf = 0;
1728	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 3, uSubLeaf)) != NULL)
1729	{
1730	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1731	if (pCpum->u8PortableCpuIdLevel > 0)
1732	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1733	uSubLeaf++;
1734	}
1735	}
1736
1737	/* Cpuid 4 + ECX:
1738	* Intel: Deterministic Cache Parameters Leaf.
1739	* AMD: Reserved
1740	* VIA: Reserved
1741	* Safe to expose, except for EAX:
1742	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1743	* Bits 31-26: Maximum number of processor cores in this physical package**
1744	* Note: These SMP values are constant regardless of ECX
1745	*/
1746	uSubLeaf = 0;
1747	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 4, uSubLeaf)) != NULL)
1748	{
1749	pCurLeaf->uEax &= UINT32_C(0x00003fff); /* Clear the #maxcores, #threads-sharing-cache (both are #-1).*/
1750	#ifdef VBOX_WITH_MULTI_CORE
1751	if ( pVM->cCpus > 1
1752	&& pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1753	{
1754	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1755	/* One logical processor with possibly multiple cores. */
1756	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1757	pCurLeaf->uEax \|= pVM->cCpus <= 0x40 ? ((pVM->cCpus - 1) << 26) : UINT32_C(0xfc000000); /* 6 bits only -> 64 cores! */
1758	}
1759	#endif
1760	uSubLeaf++;
1761	}
1762
1763	/* Cpuid 5: Monitor/mwait Leaf
1764	* Intel: ECX, EDX - reserved
1765	* EAX, EBX - Smallest and largest monitor line size
1766	* AMD: EDX - reserved
1767	* EAX, EBX - Smallest and largest monitor line size
1768	* ECX - extensions (ignored for now)
1769	* VIA: Reserved
1770	* Safe to expose
1771	*/
1772	uSubLeaf = 0;
1773	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 5, uSubLeaf)) != NULL)
1774	{
1775	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
1776	if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1777	pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1778
1779	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1780	if (pConfig->enmMWaitExtensions)
1781	{
1782	pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1783	/** @todo for now we just expose host's MWAIT C-states, although conceptually
1784	it shall be part of our power management virtualization model */
1785	#if 0
1786	/* MWAIT sub C-states */
1787	pCurLeaf->uEdx =
1788	(0 << 0) /* 0 in C0 */ \|
1789	(2 << 4) /* 2 in C1 */ \|
1790	(2 << 8) /* 2 in C2 */ \|
1791	(2 << 12) /* 2 in C3 */ \|
1792	(0 << 16) /* 0 in C4 */
1793	;
1794	#endif
1795	}
1796	else
1797	pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1798	uSubLeaf++;
1799	}
1800
1801	/* Cpuid 6: Digital Thermal Sensor and Power Management Paramenters.
1802	* Intel: Various thermal and power management related stuff.
1803	* AMD: EBX, EDX - reserved.
1804	* EAX - Bit two is ARAT, indicating that APIC timers run at a constant
1805	* rate regardless of processor P-states. Same as Intel.
1806	* ECX - Bit zero is EffFreq, indicating MSR_0000_00e7 and MSR_0000_00e8
1807	* present. Same as Intel.
1808	* VIA: ??
1809	*
1810	* We clear everything except for the ARAT bit which is important for Windows 11.
1811	*/
1812	uSubLeaf = 0;
1813	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 6, uSubLeaf)) != NULL)
1814	{
1815	pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1816	pCurLeaf->uEax &= 0
1817	\| X86_CPUID_POWER_EAX_ARAT
1818	;
1819
1820	/* Since we emulate the APIC timers, we can normally set the ARAT bit
1821	* regardless of whether the host CPU sets it or not. Intel sets the ARAT
1822	* bit circa since the Westmere generation, AMD probably only since Zen.
1823	* See @bugref{10567}.
1824	*/
1825	if (pConfig->fInvariantApic)
1826	pCurLeaf->uEax \|= X86_CPUID_POWER_EAX_ARAT;
1827
1828	uSubLeaf++;
1829	}
1830
1831	/* Cpuid 7 + ECX: Structured Extended Feature Flags Enumeration
1832	* EAX: Number of sub leaves.
1833	* EBX+ECX+EDX: Feature flags
1834	*
1835	* We only have documentation for one sub-leaf, so clear all other (no need
1836	* to remove them as such, just set them to zero).
1837	*
1838	* Note! When enabling new features the Synthetic CPU and Portable CPUID
1839	* options may require adjusting (i.e. stripping what was enabled).
1840	*/
1841	uSubLeaf = 0;
1842	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, uSubLeaf)) != NULL)
1843	{
1844	switch (uSubLeaf)
1845	{
1846	case 0:
1847	{
1848	pCurLeaf->uEax = 0; /* Max ECX input is 0. */
1849	pCurLeaf->uEbx &= 0
1850	\| PASSTHRU_FEATURE(pConfig->enmFsGsBase, pHstFeat->fFsGsBase, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE)
1851	//\| X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT(1)
1852	//\| X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT(2)
1853	\| X86_CPUID_STEXT_FEATURE_EBX_BMI1
1854	//\| X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT(4)
1855	\| PASSTHRU_FEATURE(pConfig->enmAvx2, pHstFeat->fAvx2, X86_CPUID_STEXT_FEATURE_EBX_AVX2)
1856	\| X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY
1857	//\| X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT(7)
1858	\| X86_CPUID_STEXT_FEATURE_EBX_BMI2
1859	//\| X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT(9)
1860	\| PASSTHRU_FEATURE(pConfig->enmInvpcid, pHstFeat->fInvpcid, X86_CPUID_STEXT_FEATURE_EBX_INVPCID)
1861	//\| X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT(11)
1862	//\| X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT(12)
1863	\| X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS
1864	//\| X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT(14)
1865	//\| X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT(15)
1866	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT(16)
1867	//\| RT_BIT(17) - reserved
1868	\| PASSTHRU_FEATURE_TODO(pConfig->enmRdSeed, X86_CPUID_STEXT_FEATURE_EBX_RDSEED)
1869	\| PASSTHRU_FEATURE(pConfig->enmAdx, pHstFeat->fAdx, X86_CPUID_STEXT_FEATURE_EBX_ADX)
1870	//\| X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT(20)
1871	//\| RT_BIT(21) - reserved
1872	//\| RT_BIT(22) - reserved
1873	\| PASSTHRU_FEATURE(pConfig->enmCLFlushOpt, pHstFeat->fClFlushOpt, X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
1874	//\| RT_BIT(24) - reserved
1875	//\| X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT(25)
1876	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT(26)
1877	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT(27)
1878	//\| X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT(28)
1879	\| PASSTHRU_FEATURE(pConfig->enmSha, pHstFeat->fSha, X86_CPUID_STEXT_FEATURE_EBX_SHA)
1880	//\| RT_BIT(30) - reserved
1881	//\| RT_BIT(31) - reserved
1882	;
1883	pCurLeaf->uEcx &= 0
1884	//\| X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 - we do not do vector functions yet.
1885	;
1886	pCurLeaf->uEdx &= 0
1887	\| PASSTHRU_FEATURE(pConfig->enmMdsClear, pHstFeat->fMdsClear, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1888	//\| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT(26)
1889	//\| X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT(27)
1890	\| PASSTHRU_FEATURE(pConfig->enmFlushCmdMsr, pHstFeat->fFlushCmd, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1891	\| PASSTHRU_FEATURE(pConfig->enmArchCapMsr, pHstFeat->fArchCap, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP)
1892	;
1893
1894	/* Mask out INVPCID unless FSGSBASE is exposed due to a bug in Windows 10 SMP guests, see @bugref{9089#c15}. */
1895	if ( !pVM->cpum.s.GuestFeatures.fFsGsBase
1896	&& (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_INVPCID))
1897	{
1898	pCurLeaf->uEbx &= ~X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1899	LogRel(("CPUM: Disabled INVPCID without FSGSBASE to work around buggy guests\n"));
1900	}
1901
1902	if (pCpum->u8PortableCpuIdLevel > 0)
1903	{
1904	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, FSGSBASE, X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE, pConfig->enmFsGsBase);
1905	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SGX, X86_CPUID_STEXT_FEATURE_EBX_SGX);
1906	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, AVX2, X86_CPUID_STEXT_FEATURE_EBX_AVX2, pConfig->enmAvx2);
1907	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMEP, X86_CPUID_STEXT_FEATURE_EBX_SMEP);
1908	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, BMI2, X86_CPUID_STEXT_FEATURE_EBX_BMI2);
1909	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, INVPCID, X86_CPUID_STEXT_FEATURE_EBX_INVPCID, pConfig->enmInvpcid);
1910	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512F, X86_CPUID_STEXT_FEATURE_EBX_AVX512F);
1911	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, RDSEED, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmRdSeed);
1912	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, ADX, X86_CPUID_STEXT_FEATURE_EBX_ADX, pConfig->enmAdx);
1913	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, CLFLUSHOPT, X86_CPUID_STEXT_FEATURE_EBX_RDSEED, pConfig->enmCLFlushOpt);
1914	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512PF, X86_CPUID_STEXT_FEATURE_EBX_AVX512PF);
1915	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512ER, X86_CPUID_STEXT_FEATURE_EBX_AVX512ER);
1916	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, AVX512CD, X86_CPUID_STEXT_FEATURE_EBX_AVX512CD);
1917	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEbx, SMAP, X86_CPUID_STEXT_FEATURE_EBX_SMAP);
1918	PORTABLE_DISABLE_FEATURE_BIT_CFG(1, pCurLeaf->uEbx, SHA, X86_CPUID_STEXT_FEATURE_EBX_SHA, pConfig->enmSha);
1919	PORTABLE_DISABLE_FEATURE_BIT( 1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
1920	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD, X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
1921	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR, X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
1922	PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP, X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
1923	}
1924
1925	/* Dependencies. */
1926	if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
1927	pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1928
1929	/* Force standard feature bits. */
1930	if (pConfig->enmFsGsBase == CPUMISAEXTCFG_ENABLED_ALWAYS)
1931	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE;
1932	if (pConfig->enmAvx2 == CPUMISAEXTCFG_ENABLED_ALWAYS)
1933	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_AVX2;
1934	if (pConfig->enmRdSeed == CPUMISAEXTCFG_ENABLED_ALWAYS)
1935	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_RDSEED;
1936	if (pConfig->enmAdx == CPUMISAEXTCFG_ENABLED_ALWAYS)
1937	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_ADX;
1938	if (pConfig->enmCLFlushOpt == CPUMISAEXTCFG_ENABLED_ALWAYS)
1939	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT;
1940	if (pConfig->enmSha == CPUMISAEXTCFG_ENABLED_ALWAYS)
1941	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_SHA;
1942	if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
1943	pCurLeaf->uEbx \|= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
1944	if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1945	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
1946	if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
1947	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
1948	if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
1949	pCurLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
1950	break;
1951	}
1952
1953	default:
1954	/* Invalid index, all values are zero. */
1955	pCurLeaf->uEax = 0;
1956	pCurLeaf->uEbx = 0;
1957	pCurLeaf->uEcx = 0;
1958	pCurLeaf->uEdx = 0;
1959	break;
1960	}
1961	uSubLeaf++;
1962	}
1963
1964	/* Cpuid 8: Marked as reserved by Intel and AMD.
1965	* We zero this since we don't know what it may have been used for.
1966	*/
1967	cpumR3CpuIdZeroLeaf(pCpum, 8);
1968
1969	/* Cpuid 9: Direct Cache Access (DCA) Parameters
1970	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1971	* EBX, ECX, EDX - reserved.
1972	* AMD: Reserved
1973	* VIA: ??
1974	*
1975	* We zero this.
1976	*/
1977	cpumR3CpuIdZeroLeaf(pCpum, 9);
1978
1979	/* Cpuid 0xa: Architectural Performance Monitor Features
1980	* Intel: EAX - Value of PLATFORM_DCA_CAP bits.
1981	* EBX, ECX, EDX - reserved.
1982	* AMD: Reserved
1983	* VIA: ??
1984	*
1985	* We zero this, for now at least.
1986	*/
1987	cpumR3CpuIdZeroLeaf(pCpum, 10);
1988
1989	/* Cpuid 0xb+ECX: x2APIC Features / Processor Topology.
1990	* Intel: EAX - APCI ID shift right for next level.
1991	* EBX - Factory configured cores/threads at this level.
1992	* ECX - Level number (same as input) and level type (1,2,0).
1993	* EDX - Extended initial APIC ID.
1994	* AMD: Reserved
1995	* VIA: ??
1996	*/
1997	uSubLeaf = 0;
1998	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 11, uSubLeaf)) != NULL)
1999	{
2000	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2001	{
2002	uint8_t bLevelType = RT_BYTE2(pCurLeaf->uEcx);
2003	if (bLevelType == 1)
2004	{
2005	/* Thread level - we don't do threads at the moment. */
2006	pCurLeaf->uEax = 0; /** @todo is this correct? Real CPUs never do 0 here, I think... */
2007	pCurLeaf->uEbx = 1;
2008	}
2009	else if (bLevelType == 2)
2010	{
2011	/* Core level. */
2012	pCurLeaf->uEax = 1; /** @todo real CPUs are supposed to be in the 4-6 range, not 1. Our APIC ID assignments are a little special... */
2013	#ifdef VBOX_WITH_MULTI_CORE
2014	while (RT_BIT_32(pCurLeaf->uEax) < pVM->cCpus)
2015	pCurLeaf->uEax++;
2016	#endif
2017	pCurLeaf->uEbx = pVM->cCpus;
2018	}
2019	else
2020	{
2021	AssertLogRelMsg(bLevelType == 0, ("bLevelType=%#x uSubLeaf=%#x\n", bLevelType, uSubLeaf));
2022	pCurLeaf->uEax = 0;
2023	pCurLeaf->uEbx = 0;
2024	pCurLeaf->uEcx = 0;
2025	}
2026	pCurLeaf->uEcx = (pCurLeaf->uEcx & UINT32_C(0xffffff00)) \| (uSubLeaf & 0xff);
2027	pCurLeaf->uEdx = 0; /* APIC ID is filled in by CPUMGetGuestCpuId() at runtime. Init for EMT(0) as usual. */
2028	}
2029	else
2030	{
2031	pCurLeaf->uEax = 0;
2032	pCurLeaf->uEbx = 0;
2033	pCurLeaf->uEcx = 0;
2034	pCurLeaf->uEdx = 0;
2035	}
2036	uSubLeaf++;
2037	}
2038
2039	/* Cpuid 0xc: Marked as reserved by Intel and AMD.
2040	* We zero this since we don't know what it may have been used for.
2041	*/
2042	cpumR3CpuIdZeroLeaf(pCpum, 12);
2043
2044	/* Cpuid 0xd + ECX: Processor Extended State Enumeration
2045	* ECX=0: EAX - Valid bits in XCR0[31:0].
2046	* EBX - Maximum state size as per current XCR0 value.
2047	* ECX - Maximum state size for all supported features.
2048	* EDX - Valid bits in XCR0[63:32].
2049	* ECX=1: EAX - Various X-features.
2050	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
2051	* ECX - Valid bits in IA32_XSS[31:0].
2052	* EDX - Valid bits in IA32_XSS[63:32].
2053	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
2054	* if the bit invalid all four registers are set to zero.
2055	* EAX - The state size for this feature.
2056	* EBX - The state byte offset of this feature.
2057	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
2058	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
2059	*
2060	* Clear them all as we don't currently implement extended CPU state.
2061	*/
2062	/* Figure out the supported XCR0/XSS mask component and make sure CPUID[1].ECX[27] = CR4.OSXSAVE. */
2063	uint64_t fGuestXcr0Mask = 0;
2064	pStdFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 1, 0);
2065	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
2066	{
2067	fGuestXcr0Mask = XSAVE_C_X87 \| XSAVE_C_SSE;
2068	if (pStdFeatureLeaf && (pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_AVX))
2069	fGuestXcr0Mask \|= XSAVE_C_YMM;
2070	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 7, 0);
2071	if (pCurLeaf && (pCurLeaf->uEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX512F))
2072	fGuestXcr0Mask \|= XSAVE_C_ZMM_16HI \| XSAVE_C_ZMM_HI256 \| XSAVE_C_OPMASK;
2073	fGuestXcr0Mask &= pCpum->fXStateHostMask;
2074
2075	pStdFeatureLeaf->fFlags \|= CPUMCPUIDLEAF_F_CONTAINS_OSXSAVE;
2076	}
2077	pStdFeatureLeaf = NULL;
2078	pCpum->fXStateGuestMask = fGuestXcr0Mask;
2079
2080	/* Work the sub-leaves. */
2081	uint32_t cbXSaveMaxActual = CPUM_MIN_XSAVE_AREA_SIZE;
2082	uint32_t cbXSaveMaxReport = CPUM_MIN_XSAVE_AREA_SIZE;
2083	for (uSubLeaf = 0; uSubLeaf < 63; uSubLeaf++)
2084	{
2085	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, uSubLeaf);
2086	if (pCurLeaf)
2087	{
2088	if (fGuestXcr0Mask)
2089	{
2090	switch (uSubLeaf)
2091	{
2092	case 0:
2093	pCurLeaf->uEax &= RT_LO_U32(fGuestXcr0Mask);
2094	pCurLeaf->uEdx &= RT_HI_U32(fGuestXcr0Mask);
2095	AssertLogRelMsgReturn((pCurLeaf->uEax & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2096	("CPUID(0xd/0).EAX missing mandatory X87 or SSE bits: %#RX32", pCurLeaf->uEax),
2097	VERR_CPUM_IPE_1);
2098	cbXSaveMaxActual = pCurLeaf->uEcx;
2099	AssertLogRelMsgReturn(cbXSaveMaxActual <= CPUM_MAX_XSAVE_AREA_SIZE && cbXSaveMaxActual >= CPUM_MIN_XSAVE_AREA_SIZE,
2100	("%#x max=%#x\n", cbXSaveMaxActual, CPUM_MAX_XSAVE_AREA_SIZE), VERR_CPUM_IPE_2);
2101	AssertLogRelMsgReturn(pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE && pCurLeaf->uEbx <= cbXSaveMaxActual,
2102	("ebx=%#x cbXSaveMaxActual=%#x\n", pCurLeaf->uEbx, cbXSaveMaxActual),
2103	VERR_CPUM_IPE_2);
2104	continue;
2105	case 1:
2106	pCurLeaf->uEax &= 0;
2107	pCurLeaf->uEcx &= 0;
2108	pCurLeaf->uEdx &= 0;
2109	/** @todo what about checking ebx? */
2110	continue;
2111	default:
2112	if (fGuestXcr0Mask & RT_BIT_64(uSubLeaf))
2113	{
2114	AssertLogRelMsgReturn( pCurLeaf->uEax <= cbXSaveMaxActual
2115	&& pCurLeaf->uEax > 0
2116	&& pCurLeaf->uEbx < cbXSaveMaxActual
2117	&& pCurLeaf->uEbx >= CPUM_MIN_XSAVE_AREA_SIZE
2118	&& pCurLeaf->uEbx + pCurLeaf->uEax <= cbXSaveMaxActual,
2119	("%#x: eax=%#x ebx=%#x cbMax=%#x\n",
2120	uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, cbXSaveMaxActual),
2121	VERR_CPUM_IPE_2);
2122	AssertLogRel(!(pCurLeaf->uEcx & 1));
2123	pCurLeaf->uEcx = 0; /* Bit 0 should be zero (XCR0), the reset are reserved... */
2124	pCurLeaf->uEdx = 0; /* it's reserved... */
2125	if (pCurLeaf->uEbx + pCurLeaf->uEax > cbXSaveMaxReport)
2126	cbXSaveMaxReport = pCurLeaf->uEbx + pCurLeaf->uEax;
2127	continue;
2128	}
2129	break;
2130	}
2131	}
2132
2133	/* Clear the leaf. */
2134	pCurLeaf->uEax = 0;
2135	pCurLeaf->uEbx = 0;
2136	pCurLeaf->uEcx = 0;
2137	pCurLeaf->uEdx = 0;
2138	}
2139	}
2140
2141	/* Update the max and current feature sizes to shut up annoying Linux kernels. */
2142	if (cbXSaveMaxReport != cbXSaveMaxActual && fGuestXcr0Mask)
2143	{
2144	pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 13, 0);
2145	if (pCurLeaf)
2146	{
2147	LogRel(("CPUM: Changing leaf 13[0]: EBX=%#RX32 -> %#RX32, ECX=%#RX32 -> %#RX32\n",
2148	pCurLeaf->uEbx, cbXSaveMaxReport, pCurLeaf->uEcx, cbXSaveMaxReport));
2149	pCurLeaf->uEbx = cbXSaveMaxReport;
2150	pCurLeaf->uEcx = cbXSaveMaxReport;
2151	}
2152	}
2153
2154	/* Cpuid 0xe: Marked as reserved by Intel and AMD.
2155	* We zero this since we don't know what it may have been used for.
2156	*/
2157	cpumR3CpuIdZeroLeaf(pCpum, 14);
2158
2159	/* Cpuid 0xf + ECX: Platform quality of service monitoring (PQM),
2160	* also known as Intel Resource Director Technology (RDT) Monitoring
2161	* We zero this as we don't currently virtualize PQM.
2162	*/
2163	cpumR3CpuIdZeroLeaf(pCpum, 15);
2164
2165	/* Cpuid 0x10 + ECX: Platform quality of service enforcement (PQE),
2166	* also known as Intel Resource Director Technology (RDT) Allocation
2167	* We zero this as we don't currently virtualize PQE.
2168	*/
2169	cpumR3CpuIdZeroLeaf(pCpum, 16);
2170
2171	/* Cpuid 0x11: Marked as reserved by Intel and AMD.
2172	* We zero this since we don't know what it may have been used for.
2173	*/
2174	cpumR3CpuIdZeroLeaf(pCpum, 17);
2175
2176	/* Cpuid 0x12 + ECX: SGX resource enumeration.
2177	* We zero this as we don't currently virtualize this.
2178	*/
2179	cpumR3CpuIdZeroLeaf(pCpum, 18);
2180
2181	/* Cpuid 0x13: Marked as reserved by Intel and AMD.
2182	* We zero this since we don't know what it may have been used for.
2183	*/
2184	cpumR3CpuIdZeroLeaf(pCpum, 19);
2185
2186	/* Cpuid 0x14 + ECX: Processor Trace (PT) capability enumeration.
2187	* We zero this as we don't currently virtualize this.
2188	*/
2189	cpumR3CpuIdZeroLeaf(pCpum, 20);
2190
2191	/* Cpuid 0x15: Timestamp Counter / Core Crystal Clock info.
2192	* Intel: uTscFrequency = uCoreCrystalClockFrequency * EBX / EAX.
2193	* EAX - denominator (unsigned).
2194	* EBX - numerator (unsigned).
2195	* ECX, EDX - reserved.
2196	* AMD: Reserved / undefined / not implemented.
2197	* VIA: Reserved / undefined / not implemented.
2198	* We zero this as we don't currently virtualize this.
2199	*/
2200	cpumR3CpuIdZeroLeaf(pCpum, 21);
2201
2202	/* Cpuid 0x16: Processor frequency info
2203	* Intel: EAX - Core base frequency in MHz.
2204	* EBX - Core maximum frequency in MHz.
2205	* ECX - Bus (reference) frequency in MHz.
2206	* EDX - Reserved.
2207	* AMD: Reserved / undefined / not implemented.
2208	* VIA: Reserved / undefined / not implemented.
2209	* We zero this as we don't currently virtualize this.
2210	*/
2211	cpumR3CpuIdZeroLeaf(pCpum, 22);
2212
2213	/* Cpuid 0x17..0x10000000: Unknown.
2214	* We don't know these and what they mean, so remove them. */
2215	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2216	UINT32_C(0x00000017), UINT32_C(0x0fffffff));
2217
2218
2219	/* CpuId 0x40000000..0x4fffffff: Reserved for hypervisor/emulator.
2220	* We remove all these as we're a hypervisor and must provide our own.
2221	*/
2222	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2223	UINT32_C(0x40000000), UINT32_C(0x4fffffff));
2224
2225
2226	/* Cpuid 0x80000000 is harmless. */
2227
2228	/* Cpuid 0x80000001 is handled with cpuid 1 way up above. */
2229
2230	/* Cpuid 0x80000002...0x80000004 contains the processor name and is considered harmless. */
2231
2232	/* Cpuid 0x80000005 & 0x80000006 contain information about L1, L2 & L3 cache and TLB identifiers.
2233	* Safe to pass on to the guest.
2234	*
2235	* AMD: 0x80000005 L1 cache information
2236	* 0x80000006 L2/L3 cache information
2237	* Intel: 0x80000005 reserved
2238	* 0x80000006 L2 cache information
2239	* VIA: 0x80000005 TLB and L1 cache information
2240	* 0x80000006 L2 cache information
2241	*/
2242
2243	uSubLeaf = 0;
2244	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000006), uSubLeaf)) != NULL)
2245	{
2246	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2247	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2248	{
2249	/*
2250	* Some AMD CPUs (e.g. Ryzen 7940HS) report zero L3 cache line size here and refer
2251	* to CPUID Fn8000_001D. This triggers division by zero in Linux if the
2252	* TopologyExtensions aka TOPOEXT bit in Fn8000_0001_ECX is not set, or if the kernel
2253	* is old enough (e.g. Linux 3.13) that it does not know about the topology extension
2254	* CPUID leaves.
2255	* We put a non-zero value in the cache line size here, if possible the actual value
2256	* gleaned from Fn8000_001D, or worst case a made-up valid number.
2257	*/
2258	PCPUMCPUIDLEAF pTopoLeaf;
2259	uint32_t uTopoSubLeaf;
2260	uint32_t uCacheLineSize;
2261
2262	if ((pCurLeaf->uEdx & 0xff) == 0)
2263	{
2264	uTopoSubLeaf = 0;
2265
2266	uCacheLineSize = 64; /* Use 64-byte line size as a fallback. */
2267
2268	/* Find L3 cache information. Have to check the cache level in EAX. */
2269	while ((pTopoLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uTopoSubLeaf)) != NULL)
2270	{
2271	if (((pTopoLeaf->uEax >> 5) & 0x07) == 3) {
2272	uCacheLineSize = (pTopoLeaf->uEbx & 0xfff) + 1;
2273	/* Fn8000_0006 can't report power of two line sizes greater than 128. */
2274	if (uCacheLineSize > 128)
2275	uCacheLineSize = 128;
2276
2277	break;
2278	}
2279	uTopoSubLeaf++;
2280	}
2281
2282	Assert(uCacheLineSize < 256);
2283	pCurLeaf->uEdx \|= uCacheLineSize;
2284	LogRel(("CPUM: AMD L3 cache line size in CPUID leaf 0x80000006 was zero, adjusting to %u\n", uCacheLineSize));
2285	}
2286	}
2287	uSubLeaf++;
2288	}
2289
2290	/* Cpuid 0x80000007: Advanced Power Management Information.
2291	* AMD: EAX: Processor feedback capabilities.
2292	* EBX: RAS capabilites.
2293	* ECX: Advanced power monitoring interface.
2294	* EDX: Enhanced power management capabilities.
2295	* Intel: EAX, EBX, ECX - reserved.
2296	* EDX - Invariant TSC indicator supported (bit 8), the rest is reserved.
2297	* VIA: Reserved
2298	* We let the guest see EDX_TSCINVAR (and later maybe EDX_EFRO). Actually, we should set EDX_TSCINVAR.
2299	*/
2300	uSubLeaf = 0;
2301	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000007), uSubLeaf)) != NULL)
2302	{
2303	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
2304	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2305	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2306	{
2307	/*
2308	* Older 64-bit linux kernels blindly assume that the AMD performance counters work
2309	* if X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR is set, see @bugref{7243#c85}. Exposing this
2310	* bit is now configurable.
2311	*/
2312	pCurLeaf->uEdx &= 0
2313	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
2314	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
2315	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
2316	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
2317	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
2318	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
2319	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
2320	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
2321	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
2322	//\| X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT(9)
2323	//\| X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT(10)
2324	//\| X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT(11)
2325	//\| X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT(12)
2326	\| 0;
2327	}
2328	else
2329	pCurLeaf->uEdx &= X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2330	if (!pConfig->fInvariantTsc)
2331	pCurLeaf->uEdx &= ~X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR;
2332	uSubLeaf++;
2333	}
2334
2335	/* Cpuid 0x80000008:
2336	* AMD: EAX: Long Mode Size Identifiers
2337	* EBX: Extended Feature Identifiers
2338	* ECX: Number of cores + APICIdCoreIdSize
2339	* EDX: RDPRU Register Identifier Range
2340	* Intel: EAX: Virtual/Physical address Size
2341	* EBX, ECX, EDX - reserved
2342	* VIA: EAX: Virtual/Physical address Size
2343	* EBX, ECX, EDX - reserved
2344	*
2345	* We only expose the virtual+pysical address size to the guest atm.
2346	* On AMD we set the core count, but not the apic id stuff as we're
2347	* currently not doing the apic id assignments in a compatible manner.
2348	*/
2349	uSubLeaf = 0;
2350	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000008), uSubLeaf)) != NULL)
2351	{
2352	pCurLeaf->uEax &= UINT32_C(0x0000ffff); /* Virtual & physical address sizes only. */
2353	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2354	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2355	{
2356	/* Expose XSaveErPtr aka RstrFpErrPtrs to guest. */
2357	pCurLeaf->uEbx &= X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR; /* reserved - [12] == IBPB */
2358	}
2359	else
2360	pCurLeaf->uEbx = 0; /* reserved */
2361
2362	pCurLeaf->uEdx = 0; /* reserved */
2363
2364	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu).
2365	* Set core count to 0, indicating 1 core. Adjust if we're in multi core mode on AMD. */
2366	pCurLeaf->uEcx = 0;
2367	#ifdef VBOX_WITH_MULTI_CORE
2368	if ( pVM->cCpus > 1
2369	&& ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2370	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
2371	pCurLeaf->uEcx \|= (pVM->cCpus - 1) & UINT32_C(0xff);
2372	#endif
2373	uSubLeaf++;
2374	}
2375
2376	/* Cpuid 0x80000009: Reserved
2377	* We zero this since we don't know what it may have been used for.
2378	*/
2379	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x80000009));
2380
2381	/* Cpuid 0x8000000a: SVM information on AMD, invalid on Intel.
2382	* AMD: EAX - SVM revision.
2383	* EBX - Number of ASIDs.
2384	* ECX - Reserved.
2385	* EDX - SVM Feature identification.
2386	*/
2387	if ( pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2388	\|\| pCpum->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
2389	{
2390	pExtFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x80000001), 0);
2391	if ( pExtFeatureLeaf
2392	&& (pExtFeatureLeaf->uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM))
2393	{
2394	PCPUMCPUIDLEAF pSvmFeatureLeaf = cpumR3CpuIdGetExactLeaf(pCpum, 0x8000000a, 0);
2395	if (pSvmFeatureLeaf)
2396	{
2397	pSvmFeatureLeaf->uEax = 0x1;
2398	pSvmFeatureLeaf->uEbx = 0x8000; /** @todo figure out virtual NASID. */
2399	pSvmFeatureLeaf->uEcx = 0;
2400	pSvmFeatureLeaf->uEdx &= ( X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE /** @todo Support other SVM features */
2401	\| X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID
2402	\| X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS);
2403	}
2404	else
2405	{
2406	/* Should never happen. */
2407	LogRel(("CPUM: Warning! Expected CPUID leaf 0x8000000a not present! SVM features not exposed to the guest\n"));
2408	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2409	}
2410	}
2411	else
2412	{
2413	/* If SVM is not supported, this is reserved, zero out. */
2414	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2415	}
2416	}
2417	else
2418	{
2419	/* Cpuid 0x8000000a: Reserved on Intel.
2420	* We zero this since we don't know what it may have been used for.
2421	*/
2422	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000000a));
2423	}
2424
2425	/* Cpuid 0x8000000b thru 0x80000018: Reserved
2426	* We clear these as we don't know what purpose they might have. */
2427	for (uint32_t uLeaf = UINT32_C(0x8000000b); uLeaf <= UINT32_C(0x80000018); uLeaf++)
2428	cpumR3CpuIdZeroLeaf(pCpum, uLeaf);
2429
2430	/* Cpuid 0x80000019: TLB configuration
2431	* Seems to be harmless, pass them thru as is. */
2432
2433	/* Cpuid 0x8000001a: Peformance optimization identifiers.
2434	* Strip anything we don't know what is or addresses feature we don't implement. */
2435	uSubLeaf = 0;
2436	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001a), uSubLeaf)) != NULL)
2437	{
2438	pCurLeaf->uEax &= RT_BIT_32(0) /* FP128 - use 1x128-bit instead of 2x64-bit. */
2439	\| RT_BIT_32(1) /* MOVU - Prefere unaligned MOV over MOVL + MOVH. */
2440	//\| RT_BIT_32(2) /* FP256 - use 1x256-bit instead of 2x128-bit. */
2441	;
2442	pCurLeaf->uEbx = 0; /* reserved */
2443	pCurLeaf->uEcx = 0; /* reserved */
2444	pCurLeaf->uEdx = 0; /* reserved */
2445	uSubLeaf++;
2446	}
2447
2448	/* Cpuid 0x8000001b: Instruct based sampling (IBS) information.
2449	* Clear this as we don't currently virtualize this feature. */
2450	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001b));
2451
2452	/* Cpuid 0x8000001c: Lightweight profiling (LWP) information.
2453	* Clear this as we don't currently virtualize this feature. */
2454	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0x8000001c));
2455
2456	/* Cpuid 0x8000001d+ECX: Get cache configuration descriptors.
2457	* We need to sanitize the cores per cache (EAX[25:14]).
2458	*
2459	* This is very much the same as Intel's CPUID(4) leaf, except EAX[31:26]
2460	* and EDX[2] are reserved here, and EAX[14:25] is documented having a
2461	* slightly different meaning.
2462	*/
2463	uSubLeaf = 0;
2464	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001d), uSubLeaf)) != NULL)
2465	{
2466	#ifdef VBOX_WITH_MULTI_CORE
2467	uint32_t cCores = ((pCurLeaf->uEax >> 14) & 0xfff) + 1;
2468	if (cCores > pVM->cCpus)
2469	cCores = pVM->cCpus;
2470	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2471	pCurLeaf->uEax \|= ((cCores - 1) & 0xfff) << 14;
2472	#else
2473	pCurLeaf->uEax &= UINT32_C(0x00003fff);
2474	#endif
2475	uSubLeaf++;
2476	}
2477
2478	/* Cpuid 0x8000001e: Get APIC / unit / node information.
2479	* If AMD, we configure it for our layout (on EMT(0)). In the multi-core
2480	* setup, we have one compute unit with all the cores in it. Single node.
2481	*/
2482	uSubLeaf = 0;
2483	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0x8000001e), uSubLeaf)) != NULL)
2484	{
2485	pCurLeaf->uEax = 0; /* Extended APIC ID = EMT(0).idApic (== 0). */
2486	if (pCurLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC_ID)
2487	{
2488	#ifdef VBOX_WITH_MULTI_CORE
2489	pCurLeaf->uEbx = pVM->cCpus < 0x100
2490	? (pVM->cCpus - 1) << 8 : UINT32_C(0x0000ff00); /* Compute unit ID 0, core per unit. */
2491	#else
2492	pCurLeaf->uEbx = 0; /* Compute unit ID 0, 1 core per unit. */
2493	#endif
2494	pCurLeaf->uEcx = 0; /* Node ID 0, 1 node per CPU. */
2495	}
2496	else
2497	{
2498	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_AMD);
2499	Assert(pCpum->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_HYGON);
2500	pCurLeaf->uEbx = 0; /* Reserved. */
2501	pCurLeaf->uEcx = 0; /* Reserved. */
2502	}
2503	pCurLeaf->uEdx = 0; /* Reserved. */
2504	uSubLeaf++;
2505	}
2506
2507	/* Cpuid 0x8000001f...0x8ffffffd: Unknown.
2508	* We don't know these and what they mean, so remove them. */
2509	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2510	UINT32_C(0x8000001f), UINT32_C(0x8ffffffd));
2511
2512	/* Cpuid 0x8ffffffe: Mystery AMD K6 leaf.
2513	* Just pass it thru for now. */
2514
2515	/* Cpuid 0x8fffffff: Mystery hammer time leaf!
2516	* Just pass it thru for now. */
2517
2518	/* Cpuid 0xc0000000: Centaur stuff.
2519	* Harmless, pass it thru. */
2520
2521	/* Cpuid 0xc0000001: Centaur features.
2522	* VIA: EAX - Family, model, stepping.
2523	* EDX - Centaur extended feature flags. Nothing interesting, except may
2524	* FEMMS (bit 5), but VIA marks it as 'reserved', so never mind.
2525	* EBX, ECX - reserved.
2526	* We keep EAX but strips the rest.
2527	*/
2528	uSubLeaf = 0;
2529	while ((pCurLeaf = cpumR3CpuIdGetExactLeaf(pCpum, UINT32_C(0xc0000001), uSubLeaf)) != NULL)
2530	{
2531	pCurLeaf->uEbx = 0;
2532	pCurLeaf->uEcx = 0;
2533	pCurLeaf->uEdx = 0; /* Bits 0 thru 9 are documented on sandpil.org, but we don't want them, except maybe 5 (FEMMS). */
2534	uSubLeaf++;
2535	}
2536
2537	/* Cpuid 0xc0000002: Old Centaur Current Performance Data.
2538	* We only have fixed stale values, but should be harmless. */
2539
2540	/* Cpuid 0xc0000003: Reserved.
2541	* We zero this since we don't know what it may have been used for.
2542	*/
2543	cpumR3CpuIdZeroLeaf(pCpum, UINT32_C(0xc0000003));
2544
2545	/* Cpuid 0xc0000004: Centaur Performance Info.
2546	* We only have fixed stale values, but should be harmless. */
2547
2548
2549	/* Cpuid 0xc0000005...0xcfffffff: Unknown.
2550	* We don't know these and what they mean, so remove them. */
2551	cpumR3CpuIdRemoveRange(pCpum->GuestInfo.paCpuIdLeavesR3, &pCpum->GuestInfo.cCpuIdLeaves,
2552	UINT32_C(0xc0000005), UINT32_C(0xcfffffff));
2553
2554	return VINF_SUCCESS;
2555	#undef PORTABLE_DISABLE_FEATURE_BIT
2556	#undef PORTABLE_CLEAR_BITS_WHEN
2557	}
2558
2559
2560	/**
2561	* Reads a value in /CPUM/IsaExts/ node.
2562	*
2563	* @returns VBox status code (error message raised).
2564	* @param pVM The cross context VM structure. (For errors.)
2565	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2566	* @param pszValueName The value / extension name.
2567	* @param penmValue Where to return the choice.
2568	* @param enmDefault The default choice.
2569	*/
2570	static int cpumR3CpuIdReadIsaExtCfg(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2571	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2572	{
2573	/*
2574	* Try integer encoding first.
2575	*/
2576	uint64_t uValue;
2577	int rc = CFGMR3QueryInteger(pIsaExts, pszValueName, &uValue);
2578	if (RT_SUCCESS(rc))
2579	switch (uValue)
2580	{
2581	case 0: *penmValue = CPUMISAEXTCFG_DISABLED; break;
2582	case 1: *penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED; break;
2583	case 2: *penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS; break;
2584	case 9: *penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE; break;
2585	default:
2586	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2587	"Invalid config value for '/CPUM/IsaExts/%s': %llu (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2588	pszValueName, uValue);
2589	}
2590	/*
2591	* If missing, use default.
2592	*/
2593	else if (rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT)
2594	*penmValue = enmDefault;
2595	else
2596	{
2597	if (rc == VERR_CFGM_NOT_INTEGER)
2598	{
2599	/*
2600	* Not an integer, try read it as a string.
2601	*/
2602	char szValue[32];
2603	rc = CFGMR3QueryString(pIsaExts, pszValueName, szValue, sizeof(szValue));
2604	if (RT_SUCCESS(rc))
2605	{
2606	RTStrToLower(szValue);
2607	size_t cchValue = strlen(szValue);
2608	#define EQ(a_str) (cchValue == sizeof(a_str) - 1U && memcmp(szValue, a_str, sizeof(a_str) - 1))
2609	if ( EQ("disabled") \|\| EQ("disable") \|\| EQ("off") \|\| EQ("no"))
2610	*penmValue = CPUMISAEXTCFG_DISABLED;
2611	else if (EQ("enabled") \|\| EQ("enable") \|\| EQ("on") \|\| EQ("yes"))
2612	*penmValue = CPUMISAEXTCFG_ENABLED_SUPPORTED;
2613	else if (EQ("forced") \|\| EQ("force") \|\| EQ("always"))
2614	*penmValue = CPUMISAEXTCFG_ENABLED_ALWAYS;
2615	else if (EQ("portable"))
2616	*penmValue = CPUMISAEXTCFG_ENABLED_PORTABLE;
2617	else if (EQ("default") \|\| EQ("def"))
2618	*penmValue = enmDefault;
2619	else
2620	return VMSetError(pVM, VERR_CPUM_INVALID_CONFIG_VALUE, RT_SRC_POS,
2621	"Invalid config value for '/CPUM/IsaExts/%s': '%s' (expected 0/'disabled', 1/'enabled', 2/'portable', or 9/'forced')",
2622	pszValueName, uValue);
2623	#undef EQ
2624	}
2625	}
2626	if (RT_FAILURE(rc))
2627	return VMSetError(pVM, rc, RT_SRC_POS, "Error reading config value '/CPUM/IsaExts/%s': %Rrc", pszValueName, rc);
2628	}
2629	return VINF_SUCCESS;
2630	}
2631
2632
2633	/**
2634	* Reads a value in /CPUM/IsaExts/ node, forcing it to DISABLED if wanted.
2635	*
2636	* @returns VBox status code (error message raised).
2637	* @param pVM The cross context VM structure. (For errors.)
2638	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2639	* @param pszValueName The value / extension name.
2640	* @param penmValue Where to return the choice.
2641	* @param enmDefault The default choice.
2642	* @param fAllowed Allowed choice. Applied both to the result and to
2643	* the default value.
2644	*/
2645	static int cpumR3CpuIdReadIsaExtCfgEx(PVM pVM, PCFGMNODE pIsaExts, const char *pszValueName,
2646	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault, bool fAllowed)
2647	{
2648	int rc;
2649	if (fAllowed)
2650	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2651	else
2652	{
2653	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, false /enmDefault/);
2654	if (RT_SUCCESS(rc) && *penmValue == CPUMISAEXTCFG_ENABLED_ALWAYS)
2655	LogRel(("CPUM: Ignoring forced '%s'\n", pszValueName));
2656	*penmValue = CPUMISAEXTCFG_DISABLED;
2657	}
2658	return rc;
2659	}
2660
2661
2662	/**
2663	* Reads a value in /CPUM/IsaExts/ node that used to be located in /CPUM/.
2664	*
2665	* @returns VBox status code (error message raised).
2666	* @param pVM The cross context VM structure. (For errors.)
2667	* @param pIsaExts The /CPUM/IsaExts node (can be NULL).
2668	* @param pCpumCfg The /CPUM node (can be NULL).
2669	* @param pszValueName The value / extension name.
2670	* @param penmValue Where to return the choice.
2671	* @param enmDefault The default choice.
2672	*/
2673	static int cpumR3CpuIdReadIsaExtCfgLegacy(PVM pVM, PCFGMNODE pIsaExts, PCFGMNODE pCpumCfg, const char *pszValueName,
2674	CPUMISAEXTCFG *penmValue, CPUMISAEXTCFG enmDefault)
2675	{
2676	if (CFGMR3Exists(pCpumCfg, pszValueName))
2677	{
2678	if (!CFGMR3Exists(pIsaExts, pszValueName))
2679	LogRel(("Warning: /CPUM/%s is deprecated, use /CPUM/IsaExts/%s instead.\n", pszValueName, pszValueName));
2680	else
2681	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS,
2682	"Duplicate config values '/CPUM/%s' and '/CPUM/IsaExts/%s' - please remove the former!",
2683	pszValueName, pszValueName);
2684
2685	bool fLegacy;
2686	int rc = CFGMR3QueryBoolDef(pCpumCfg, pszValueName, &fLegacy, enmDefault != CPUMISAEXTCFG_DISABLED);
2687	if (RT_SUCCESS(rc))
2688	{
2689	*penmValue = fLegacy;
2690	return VINF_SUCCESS;
2691	}
2692	return VMSetError(pVM, VERR_DUPLICATE, RT_SRC_POS, "Error querying '/CPUM/%s': %Rrc", pszValueName, rc);
2693	}
2694
2695	return cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, pszValueName, penmValue, enmDefault);
2696	}
2697
2698
2699	static int cpumR3CpuIdReadConfig(PVM pVM, PCPUMCPUIDCONFIG pConfig, PCFGMNODE pCpumCfg, bool fNestedPagingAndFullGuestExec)
2700	{
2701	int rc;
2702
2703	/** @cfgm{/CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
2704	* When non-zero CPUID features that could cause portability issues will be
2705	* stripped. The higher the value the more features gets stripped. Higher
2706	* values should only be used when older CPUs are involved since it may
2707	* harm performance and maybe also cause problems with specific guests. */
2708	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pVM->cpum.s.u8PortableCpuIdLevel, 0);
2709	AssertLogRelRCReturn(rc, rc);
2710
2711	/** @cfgm{/CPUM/GuestCpuName, string}
2712	* The name of the CPU we're to emulate. The default is the host CPU.
2713	* Note! CPUs other than "host" one is currently unsupported. */
2714	rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", pConfig->szCpuName, sizeof(pConfig->szCpuName), "host");
2715	AssertLogRelRCReturn(rc, rc);
2716
2717	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
2718	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
2719	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
2720	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
2721	*/
2722	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &pConfig->fNt4LeafLimit, false);
2723	AssertLogRelRCReturn(rc, rc);
2724
2725	/** @cfgm{/CPUM/InvariantTsc, boolean, true}
2726	* Pass-through the invariant TSC flag in 0x80000007 if available on the host
2727	* CPU. On AMD CPUs, users may wish to suppress it to avoid trouble from older
2728	* 64-bit linux guests which assume the presence of AMD performance counters
2729	* that we do not virtualize.
2730	*/
2731	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantTsc", &pConfig->fInvariantTsc, true);
2732	AssertLogRelRCReturn(rc, rc);
2733
2734	/** @cfgm{/CPUM/InvariantApic, boolean, true}
2735	* Set the Always Running APIC Timer (ARAT) flag in lea if true; otherwise
2736	* pass through the host setting. The Windows 10/11 HAL won't use APIC timers
2737	* unless the ARAT bit is set. Note that both Intel and AMD set this bit.
2738	*/
2739	rc = CFGMR3QueryBoolDef(pCpumCfg, "InvariantApic", &pConfig->fInvariantApic, true);
2740	AssertLogRelRCReturn(rc, rc);
2741
2742	/** @cfgm{/CPUM/ForceVme, boolean, false}
2743	* Always expose the VME (Virtual-8086 Mode Extensions) capability if true.
2744	* By default the flag is passed thru as is from the host CPU, except
2745	* on AMD Ryzen CPUs where it's masked to avoid trouble with XP/Server 2003
2746	* guests and DOS boxes in general.
2747	*/
2748	rc = CFGMR3QueryBoolDef(pCpumCfg, "ForceVme", &pConfig->fForceVme, false);
2749	AssertLogRelRCReturn(rc, rc);
2750
2751	/** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
2752	* Restrict the reported CPU family+model+stepping of intel CPUs. This is
2753	* probably going to be a temporary hack, so don't depend on this.
2754	* The 1st byte of the value is the stepping, the 2nd byte value is the model
2755	* number and the 3rd byte value is the family, and the 4th value must be zero.
2756	*/
2757	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &pConfig->uMaxIntelFamilyModelStep, UINT32_MAX);
2758	AssertLogRelRCReturn(rc, rc);
2759
2760	/** @cfgm{/CPUM/MaxStdLeaf, uint32_t, 0x00000016}
2761	* The last standard leaf to keep. The actual last value that is stored in EAX
2762	* is RT_MAX(CPUID[0].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max leaf are
2763	* removed. (This works independently of and differently from NT4LeafLimit.)
2764	* The default is usually set to what we're able to reasonably sanitize.
2765	*/
2766	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxStdLeaf", &pConfig->uMaxStdLeaf, UINT32_C(0x00000016));
2767	AssertLogRelRCReturn(rc, rc);
2768
2769	/** @cfgm{/CPUM/MaxExtLeaf, uint32_t, 0x8000001e}
2770	* The last extended leaf to keep. The actual last value that is stored in EAX
2771	* is RT_MAX(CPUID[0x80000000].EAX,/CPUM/MaxStdLeaf). Leaves beyond the max
2772	* leaf are removed. The default is set to what we're able to sanitize.
2773	*/
2774	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxExtLeaf", &pConfig->uMaxExtLeaf, UINT32_C(0x8000001e));
2775	AssertLogRelRCReturn(rc, rc);
2776
2777	/** @cfgm{/CPUM/MaxCentaurLeaf, uint32_t, 0xc0000004}
2778	* The last extended leaf to keep. The actual last value that is stored in EAX
2779	* is RT_MAX(CPUID[0xc0000000].EAX,/CPUM/MaxCentaurLeaf). Leaves beyond the max
2780	* leaf are removed. The default is set to what we're able to sanitize.
2781	*/
2782	rc = CFGMR3QueryU32Def(pCpumCfg, "MaxCentaurLeaf", &pConfig->uMaxCentaurLeaf, UINT32_C(0xc0000004));
2783	AssertLogRelRCReturn(rc, rc);
2784
2785	bool fQueryNestedHwvirt = false
2786	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2787	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
2788	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON
2789	#endif
2790	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2791	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
2792	\|\| pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA
2793	#endif
2794	;
2795	if (fQueryNestedHwvirt)
2796	{
2797	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
2798	* Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
2799	* The default is false, and when enabled requires a 64-bit CPU with support for
2800	* nested-paging and AMD-V or unrestricted guest mode.
2801	*/
2802	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
2803	AssertLogRelRCReturn(rc, rc);
2804	if (pConfig->fNestedHWVirt)
2805	{
2806	/** @todo Think about enabling this later with NEM/KVM. */
2807	if (VM_IS_NEM_ENABLED(pVM))
2808	{
2809	LogRel(("CPUM: Warning! Can't turn on nested VT-x/AMD-V when NEM is used! (later)\n"));
2810	pConfig->fNestedHWVirt = false;
2811	}
2812	else if (!fNestedPagingAndFullGuestExec)
2813	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
2814	"Cannot enable nested VT-x/AMD-V without nested-paging and unrestricted guest execution!\n");
2815	}
2816	}
2817
2818	/*
2819	* Instruction Set Architecture (ISA) Extensions.
2820	*/
2821	PCFGMNODE pIsaExts = CFGMR3GetChild(pCpumCfg, "IsaExts");
2822	if (pIsaExts)
2823	{
2824	rc = CFGMR3ValidateConfig(pIsaExts, "/CPUM/IsaExts/",
2825	"CMPXCHG16B"
2826	"\|MONITOR"
2827	"\|MWaitExtensions"
2828	"\|SSE4.1"
2829	"\|SSE4.2"
2830	"\|XSAVE"
2831	"\|AVX"
2832	"\|AVX2"
2833	"\|AESNI"
2834	"\|PCLMUL"
2835	"\|POPCNT"
2836	"\|MOVBE"
2837	"\|RDRAND"
2838	"\|RDSEED"
2839	"\|ADX"
2840	"\|CLFLUSHOPT"
2841	"\|SHA"
2842	"\|FSGSBASE"
2843	"\|PCID"
2844	"\|INVPCID"
2845	"\|FlushCmdMsr"
2846	"\|ABM"
2847	"\|SSE4A"
2848	"\|MISALNSSE"
2849	"\|3DNOWPRF"
2850	"\|AXMMX"
2851	, "" /pszValidNodes/, "CPUM" /pszWho/, 0 /uInstance/);
2852	if (RT_FAILURE(rc))
2853	return rc;
2854	}
2855
2856	/** @cfgm{/CPUM/IsaExts/CMPXCHG16B, boolean, true}
2857	* Expose CMPXCHG16B to the guest if available. All host CPUs which support
2858	* hardware virtualization have it.
2859	*/
2860	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "CMPXCHG16B", &pConfig->enmCmpXchg16b, true);
2861	AssertLogRelRCReturn(rc, rc);
2862
2863	/** @cfgm{/CPUM/IsaExts/MONITOR, boolean, true}
2864	* Expose MONITOR/MWAIT instructions to the guest.
2865	*/
2866	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MONITOR", &pConfig->enmMonitor, true);
2867	AssertLogRelRCReturn(rc, rc);
2868
2869	/** @cfgm{/CPUM/IsaExts/MWaitExtensions, boolean, false}
2870	* Expose MWAIT extended features to the guest. For now we expose just MWAIT
2871	* break on interrupt feature (bit 1).
2872	*/
2873	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "MWaitExtensions", &pConfig->enmMWaitExtensions, false);
2874	AssertLogRelRCReturn(rc, rc);
2875
2876	/** @cfgm{/CPUM/IsaExts/SSE4.1, boolean, true}
2877	* Expose SSE4.1 to the guest if available.
2878	*/
2879	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.1", &pConfig->enmSse41, true);
2880	AssertLogRelRCReturn(rc, rc);
2881
2882	/** @cfgm{/CPUM/IsaExts/SSE4.2, boolean, true}
2883	* Expose SSE4.2 to the guest if available.
2884	*/
2885	rc = cpumR3CpuIdReadIsaExtCfgLegacy(pVM, pIsaExts, pCpumCfg, "SSE4.2", &pConfig->enmSse42, true);
2886	AssertLogRelRCReturn(rc, rc);
2887
2888	bool const fMayHaveXSave = pVM->cpum.s.HostFeatures.fXSaveRstor
2889	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor
2890	&& ( VM_IS_NEM_ENABLED(pVM)
2891	? NEMHCGetFeatures(pVM) & NEM_FEAT_F_XSAVE_XRSTOR
2892	: VM_IS_EXEC_ENGINE_IEM(pVM)
2893	? true
2894	: fNestedPagingAndFullGuestExec);
2895	uint64_t const fXStateHostMask = pVM->cpum.s.fXStateHostMask;
2896
2897	/** @cfgm{/CPUM/IsaExts/XSAVE, boolean, depends}
2898	* Expose XSAVE/XRSTOR to the guest if available. For the time being the
2899	* default is to only expose this to VMs with nested paging and AMD-V or
2900	* unrestricted guest execution mode. Not possible to force this one without
2901	* host support at the moment.
2902	*/
2903	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "XSAVE", &pConfig->enmXSave, true,
2904	fMayHaveXSave /fAllowed/);
2905	AssertLogRelRCReturn(rc, rc);
2906
2907	/** @cfgm{/CPUM/IsaExts/AVX, boolean, depends}
2908	* Expose the AVX instruction set extensions to the guest if available and
2909	* XSAVE is exposed too. For the time being the default is to only expose this
2910	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2911	*/
2912	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX", &pConfig->enmAvx, fNestedPagingAndFullGuestExec,
2913	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2914	AssertLogRelRCReturn(rc, rc);
2915
2916	/** @cfgm{/CPUM/IsaExts/AVX2, boolean, depends}
2917	* Expose the AVX2 instruction set extensions to the guest if available and
2918	* XSAVE is exposed too. For the time being the default is to only expose this
2919	* to VMs with nested paging and AMD-V or unrestricted guest execution mode.
2920	*/
2921	rc = cpumR3CpuIdReadIsaExtCfgEx(pVM, pIsaExts, "AVX2", &pConfig->enmAvx2, fNestedPagingAndFullGuestExec /* temporarily */,
2922	fMayHaveXSave && pConfig->enmXSave && (fXStateHostMask & XSAVE_C_YMM) /fAllowed/);
2923	AssertLogRelRCReturn(rc, rc);
2924
2925	/** @cfgm{/CPUM/IsaExts/AESNI, isaextcfg, depends}
2926	* Whether to expose the AES instructions to the guest. For the time being the
2927	* default is to only do this for VMs with nested paging and AMD-V or
2928	* unrestricted guest mode.
2929	*/
2930	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AESNI", &pConfig->enmAesNi, fNestedPagingAndFullGuestExec);
2931	AssertLogRelRCReturn(rc, rc);
2932
2933	/** @cfgm{/CPUM/IsaExts/PCLMUL, isaextcfg, depends}
2934	* Whether to expose the PCLMULQDQ instructions to the guest. For the time
2935	* being the default is to only do this for VMs with nested paging and AMD-V or
2936	* unrestricted guest mode.
2937	*/
2938	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCLMUL", &pConfig->enmPClMul, fNestedPagingAndFullGuestExec);
2939	AssertLogRelRCReturn(rc, rc);
2940
2941	/** @cfgm{/CPUM/IsaExts/POPCNT, isaextcfg, true}
2942	* Whether to expose the POPCNT instructions to the guest.
2943	*/
2944	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "POPCNT", &pConfig->enmPopCnt, CPUMISAEXTCFG_ENABLED_SUPPORTED);
2945	AssertLogRelRCReturn(rc, rc);
2946
2947	/** @cfgm{/CPUM/IsaExts/MOVBE, isaextcfg, depends}
2948	* Whether to expose the MOVBE instructions to the guest. For the time
2949	* being the default is to only do this for VMs with nested paging and AMD-V or
2950	* unrestricted guest mode.
2951	*/
2952	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MOVBE", &pConfig->enmMovBe, true);
2953	AssertLogRelRCReturn(rc, rc);
2954
2955	/** @cfgm{/CPUM/IsaExts/RDRAND, isaextcfg, depends}
2956	* Whether to expose the RDRAND instructions to the guest. For the time being
2957	* the default is to only do this for VMs with nested paging and AMD-V or
2958	* unrestricted guest mode.
2959	*/
2960	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDRAND", &pConfig->enmRdRand, fNestedPagingAndFullGuestExec);
2961	AssertLogRelRCReturn(rc, rc);
2962
2963	/** @cfgm{/CPUM/IsaExts/RDSEED, isaextcfg, depends}
2964	* Whether to expose the RDSEED instructions to the guest. For the time being
2965	* the default is to only do this for VMs with nested paging and AMD-V or
2966	* unrestricted guest mode.
2967	*/
2968	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "RDSEED", &pConfig->enmRdSeed, fNestedPagingAndFullGuestExec);
2969	AssertLogRelRCReturn(rc, rc);
2970
2971	/** @cfgm{/CPUM/IsaExts/ADX, isaextcfg, depends}
2972	* Whether to expose the ADX instructions to the guest. For the time being
2973	* the default is to only do this for VMs with nested paging and AMD-V or
2974	* unrestricted guest mode.
2975	*/
2976	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ADX", &pConfig->enmAdx, fNestedPagingAndFullGuestExec);
2977	AssertLogRelRCReturn(rc, rc);
2978
2979	/** @cfgm{/CPUM/IsaExts/CLFLUSHOPT, isaextcfg, depends}
2980	* Whether to expose the CLFLUSHOPT instructions to the guest. For the time
2981	* being the default is to only do this for VMs with nested paging and AMD-V or
2982	* unrestricted guest mode.
2983	*/
2984	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "CLFLUSHOPT", &pConfig->enmCLFlushOpt, fNestedPagingAndFullGuestExec);
2985	AssertLogRelRCReturn(rc, rc);
2986
2987	/** @cfgm{/CPUM/IsaExts/SHA, isaextcfg, depends}
2988	* Whether to expose the SHA instructions to the guest. For the time being
2989	* the default is to only do this for VMs with nested paging and AMD-V or
2990	* unrestricted guest mode.
2991	*/
2992	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SHA", &pConfig->enmSha, fNestedPagingAndFullGuestExec);
2993	AssertLogRelRCReturn(rc, rc);
2994
2995	/** @cfgm{/CPUM/IsaExts/FSGSBASE, isaextcfg, true}
2996	* Whether to expose the read/write FSGSBASE instructions to the guest.
2997	*/
2998	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FSGSBASE", &pConfig->enmFsGsBase, true);
2999	AssertLogRelRCReturn(rc, rc);
3000
3001	/** @cfgm{/CPUM/IsaExts/PCID, isaextcfg, true}
3002	* Whether to expose the PCID feature to the guest.
3003	*/
3004	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "PCID", &pConfig->enmPcid, pConfig->enmFsGsBase);
3005	AssertLogRelRCReturn(rc, rc);
3006
3007	/** @cfgm{/CPUM/IsaExts/INVPCID, isaextcfg, true}
3008	* Whether to expose the INVPCID instruction to the guest.
3009	*/
3010	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "INVPCID", &pConfig->enmInvpcid, pConfig->enmFsGsBase);
3011	AssertLogRelRCReturn(rc, rc);
3012
3013	/** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
3014	* Whether to expose the IA32_FLUSH_CMD MSR to the guest.
3015	*/
3016	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3017	AssertLogRelRCReturn(rc, rc);
3018
3019	/** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
3020	* Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
3021	* the guest. Requires FlushCmdMsr to be present too.
3022	*/
3023	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3024	AssertLogRelRCReturn(rc, rc);
3025
3026	/** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
3027	* Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
3028	*/
3029	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3030	AssertLogRelRCReturn(rc, rc);
3031
3032
3033	/* AMD: */
3034
3035	/** @cfgm{/CPUM/IsaExts/ABM, isaextcfg, true}
3036	* Whether to expose the AMD ABM instructions to the guest.
3037	*/
3038	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ABM", &pConfig->enmAbm, CPUMISAEXTCFG_ENABLED_SUPPORTED);
3039	AssertLogRelRCReturn(rc, rc);
3040
3041	/** @cfgm{/CPUM/IsaExts/SSE4A, isaextcfg, depends}
3042	* Whether to expose the AMD SSE4A instructions to the guest. For the time
3043	* being the default is to only do this for VMs with nested paging and AMD-V or
3044	* unrestricted guest mode.
3045	*/
3046	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "SSE4A", &pConfig->enmSse4A, fNestedPagingAndFullGuestExec);
3047	AssertLogRelRCReturn(rc, rc);
3048
3049	/** @cfgm{/CPUM/IsaExts/MISALNSSE, isaextcfg, depends}
3050	* Whether to expose the AMD MisAlSse feature (MXCSR flag 17) to the guest. For
3051	* the time being the default is to only do this for VMs with nested paging and
3052	* AMD-V or unrestricted guest mode.
3053	*/
3054	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MISALNSSE", &pConfig->enmMisAlnSse, fNestedPagingAndFullGuestExec);
3055	AssertLogRelRCReturn(rc, rc);
3056
3057	/** @cfgm{/CPUM/IsaExts/3DNOWPRF, isaextcfg, depends}
3058	* Whether to expose the AMD 3D Now! prefetch instructions to the guest.
3059	* For the time being the default is to only do this for VMs with nested paging
3060	* and AMD-V or unrestricted guest mode.
3061	*/
3062	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "3DNOWPRF", &pConfig->enm3dNowPrf, fNestedPagingAndFullGuestExec);
3063	AssertLogRelRCReturn(rc, rc);
3064
3065	/** @cfgm{/CPUM/IsaExts/AXMMX, isaextcfg, depends}
3066	* Whether to expose the AMD's MMX Extensions to the guest. For the time being
3067	* the default is to only do this for VMs with nested paging and AMD-V or
3068	* unrestricted guest mode.
3069	*/
3070	rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "AXMMX", &pConfig->enmAmdExtMmx, fNestedPagingAndFullGuestExec);
3071	AssertLogRelRCReturn(rc, rc);
3072
3073	return VINF_SUCCESS;
3074	}
3075
3076
3077	/**
3078	* Checks and fixes the maximum physical address width supported by the
3079	* variable-range MTRR MSRs to be consistent with what is reported in CPUID.
3080	*
3081	* @returns VBox status code.
3082	* @param pVM The cross context VM structure.
3083	* @param cVarMtrrs The number of variable-range MTRRs reported to the guest.
3084	*/
3085	static int cpumR3FixVarMtrrPhysAddrWidths(PVM pVM, uint8_t const cVarMtrrs)
3086	{
3087	AssertLogRelMsgReturn(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs),
3088	("Invalid number of variable range MTRRs reported (%u)\n", cVarMtrrs),
3089	VERR_CPUM_IPE_2);
3090
3091	/*
3092	* CPUID determines the actual maximum physical address width reported and supported.
3093	* If the CPU DB profile reported fewer address bits, we must correct it here by
3094	* updating the MSR write #GP masks of all the variable-range MTRR MSRs. Otherwise,
3095	* they cause problems when guests write to these MTRR MSRs, see @bugref{10498#c32}.
3096	*/
3097	PCPUMMSRRANGE pBaseRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0);
3098	AssertLogRelMsgReturn(pBaseRange0, ("Failed to lookup the IA32_MTRR_PHYSBASE[0] MSR range\n"), VERR_NOT_FOUND);
3099
3100	PCPUMMSRRANGE pMaskRange0 = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0);
3101	AssertLogRelMsgReturn(pMaskRange0, ("Failed to lookup the IA32_MTRR_PHYSMASK[0] MSR range\n"), VERR_NOT_FOUND);
3102
3103	uint64_t const fPhysBaseWrGpMask = pBaseRange0->fWrGpMask;
3104	uint64_t const fPhysMaskWrGpMask = pMaskRange0->fWrGpMask;
3105
3106	uint8_t const cGuestMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3107	uint8_t const cProfilePhysBaseMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysBaseWrGpMask);
3108	uint8_t const cProfilePhysMaskMaxPhysAddrWidth = ASMBitLastSetU64(~fPhysMaskWrGpMask);
3109
3110	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth == cProfilePhysMaskMaxPhysAddrWidth,
3111	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK report different physical address widths (%u and %u)\n",
3112	cProfilePhysBaseMaxPhysAddrWidth, cProfilePhysMaskMaxPhysAddrWidth),
3113	VERR_CPUM_IPE_2);
3114	AssertLogRelMsgReturn(cProfilePhysBaseMaxPhysAddrWidth > 12 && cProfilePhysBaseMaxPhysAddrWidth <= 64,
3115	("IA32_MTRR_PHYSBASE and IA32_MTRR_PHYSMASK reports an invalid physical address width of %u bits\n",
3116	cProfilePhysBaseMaxPhysAddrWidth), VERR_CPUM_IPE_2);
3117
3118	if (cProfilePhysBaseMaxPhysAddrWidth < cGuestMaxPhysAddrWidth)
3119	{
3120	uint64_t fNewPhysBaseWrGpMask = fPhysBaseWrGpMask;
3121	uint64_t fNewPhysMaskWrGpMask = fPhysMaskWrGpMask;
3122	int8_t cBits = cGuestMaxPhysAddrWidth - cProfilePhysBaseMaxPhysAddrWidth;
3123	while (cBits)
3124	{
3125	uint64_t const fWrGpAndMask = ~(uint64_t)RT_BIT_64(cProfilePhysBaseMaxPhysAddrWidth + cBits - 1);
3126	fNewPhysBaseWrGpMask &= fWrGpAndMask;
3127	fNewPhysMaskWrGpMask &= fWrGpAndMask;
3128	--cBits;
3129	}
3130
3131	for (uint8_t iVarMtrr = 1; iVarMtrr < cVarMtrrs; iVarMtrr++)
3132	{
3133	PCPUMMSRRANGE pBaseRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSBASE0 + (iVarMtrr * 2));
3134	AssertLogRelMsgReturn(pBaseRange, ("Failed to lookup the IA32_MTRR_PHYSBASE[%u] MSR range\n", iVarMtrr),
3135	VERR_NOT_FOUND);
3136
3137	PCPUMMSRRANGE pMaskRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_PHYSMASK0 + (iVarMtrr * 2));
3138	AssertLogRelMsgReturn(pMaskRange, ("Failed to lookup the IA32_MTRR_PHYSMASK[%u] MSR range\n", iVarMtrr),
3139	VERR_NOT_FOUND);
3140
3141	AssertLogRelMsgReturn(pBaseRange->fWrGpMask == fPhysBaseWrGpMask,
3142	("IA32_MTRR_PHYSBASE[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSBASE[0] write GP mask (%#016RX64)\n",
3143	iVarMtrr, pBaseRange->fWrGpMask, fPhysBaseWrGpMask),
3144	VERR_CPUM_IPE_1);
3145	AssertLogRelMsgReturn(pMaskRange->fWrGpMask == fPhysMaskWrGpMask,
3146	("IA32_MTRR_PHYSMASK[%u] write GP mask (%#016RX64) differs from IA32_MTRR_PHYSMASK[0] write GP mask (%#016RX64)\n",
3147	iVarMtrr, pMaskRange->fWrGpMask, fPhysMaskWrGpMask),
3148	VERR_CPUM_IPE_1);
3149
3150	pBaseRange->fWrGpMask = fNewPhysBaseWrGpMask;
3151	pMaskRange->fWrGpMask = fNewPhysMaskWrGpMask;
3152	}
3153
3154	pBaseRange0->fWrGpMask = fNewPhysBaseWrGpMask;
3155	pMaskRange0->fWrGpMask = fNewPhysMaskWrGpMask;
3156
3157	LogRel(("CPUM: Updated IA32_MTRR_PHYSBASE[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3158	cVarMtrrs - 1, fPhysBaseWrGpMask, fNewPhysBaseWrGpMask));
3159	LogRel(("CPUM: Updated IA32_MTRR_PHYSMASK[0..%u] MSR write #GP mask (old=%#016RX64 new=%#016RX64)\n",
3160	cVarMtrrs - 1, fPhysMaskWrGpMask, fNewPhysMaskWrGpMask));
3161	}
3162
3163	return VINF_SUCCESS;
3164	}
3165
3166
3167	/**
3168	* Inserts variable-range MTRR MSR ranges based on the given count.
3169	*
3170	* Since we need to insert the MSRs beyond what the CPU profile has inserted, we
3171	* reinsert the whole range here since the variable-range MTRR MSR read+write
3172	* functions handle ranges as well as the \#GP checking.
3173	*
3174	* @returns VBox status code.
3175	* @param pVM The cross context VM structure.
3176	* @param cVarMtrrs The number of variable-range MTRRs to insert. This must be
3177	* less than or equal to CPUMCTX_MAX_MTRRVAR_COUNT.
3178	*/
3179	static int cpumR3VarMtrrMsrRangeInsert(PVM pVM, uint8_t const cVarMtrrs)
3180	{
3181	#ifdef VBOX_WITH_STATISTICS
3182	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3183	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3184	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3185	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
3186	#else
3187	# define CPUM_MTRR_PHYSBASE_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3188	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysBaseN, kCpumMsrWrFn_Ia32MtrrPhysBaseN, 0, 0, a_uValue, 0, 0, a_szName }
3189	# define CPUM_MTRR_PHYSMASK_MSRRANGE(a_uMsr, a_uValue, a_szName) \
3190	{ (a_uMsr), (a_uMsr), kCpumMsrRdFn_Ia32MtrrPhysMaskN, kCpumMsrWrFn_Ia32MtrrPhysMaskN, 0, 0, a_uValue, 0, 0, a_szName }
3191	#endif
3192	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysBase[CPUMCTX_MAX_MTRRVAR_COUNT] =
3193	{
3194	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE0, 0, "MSR_IA32_MTRR_PHYSBASE0"),
3195	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE1, 1, "MSR_IA32_MTRR_PHYSBASE1"),
3196	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE2, 2, "MSR_IA32_MTRR_PHYSBASE2"),
3197	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE3, 3, "MSR_IA32_MTRR_PHYSBASE3"),
3198	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE4, 4, "MSR_IA32_MTRR_PHYSBASE4"),
3199	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE5, 5, "MSR_IA32_MTRR_PHYSBASE5"),
3200	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE6, 6, "MSR_IA32_MTRR_PHYSBASE6"),
3201	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE7, 7, "MSR_IA32_MTRR_PHYSBASE7"),
3202	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE8, 8, "MSR_IA32_MTRR_PHYSBASE8"),
3203	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9, 9, "MSR_IA32_MTRR_PHYSBASE9"),
3204	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 2, 10, "MSR_IA32_MTRR_PHYSBASE10"),
3205	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 4, 11, "MSR_IA32_MTRR_PHYSBASE11"),
3206	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 6, 12, "MSR_IA32_MTRR_PHYSBASE12"),
3207	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 8, 13, "MSR_IA32_MTRR_PHYSBASE13"),
3208	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 10, 14, "MSR_IA32_MTRR_PHYSBASE14"),
3209	CPUM_MTRR_PHYSBASE_MSRRANGE(MSR_IA32_MTRR_PHYSBASE9 + 12, 15, "MSR_IA32_MTRR_PHYSBASE15"),
3210	};
3211	static CPUMMSRRANGE const s_aMsrRanges_MtrrPhysMask[CPUMCTX_MAX_MTRRVAR_COUNT] =
3212	{
3213	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK0, 0, "MSR_IA32_MTRR_PHYSMASK0"),
3214	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK1, 1, "MSR_IA32_MTRR_PHYSMASK1"),
3215	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK2, 2, "MSR_IA32_MTRR_PHYSMASK2"),
3216	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK3, 3, "MSR_IA32_MTRR_PHYSMASK3"),
3217	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK4, 4, "MSR_IA32_MTRR_PHYSMASK4"),
3218	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK5, 5, "MSR_IA32_MTRR_PHYSMASK5"),
3219	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK6, 6, "MSR_IA32_MTRR_PHYSMASK6"),
3220	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK7, 7, "MSR_IA32_MTRR_PHYSMASK7"),
3221	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK8, 8, "MSR_IA32_MTRR_PHYSMASK8"),
3222	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9, 9, "MSR_IA32_MTRR_PHYSMASK9"),
3223	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 2, 10, "MSR_IA32_MTRR_PHYSMASK10"),
3224	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 4, 11, "MSR_IA32_MTRR_PHYSMASK11"),
3225	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 6, 12, "MSR_IA32_MTRR_PHYSMASK12"),
3226	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 8, 13, "MSR_IA32_MTRR_PHYSMASK13"),
3227	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 10, 14, "MSR_IA32_MTRR_PHYSMASK14"),
3228	CPUM_MTRR_PHYSMASK_MSRRANGE(MSR_IA32_MTRR_PHYSMASK9 + 12, 15, "MSR_IA32_MTRR_PHYSMASK15"),
3229	};
3230	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysBase) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3231	AssertCompile(RT_ELEMENTS(s_aMsrRanges_MtrrPhysMask) == RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3232
3233	Assert(cVarMtrrs <= RT_ELEMENTS(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.aMtrrVarMsrs));
3234	for (unsigned i = 0; i < cVarMtrrs; i++)
3235	{
3236	int rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysBase[i]);
3237	AssertLogRelRCReturn(rc, rc);
3238	rc = CPUMR3MsrRangesInsert(pVM, &s_aMsrRanges_MtrrPhysMask[i]);
3239	AssertLogRelRCReturn(rc, rc);
3240	}
3241	return VINF_SUCCESS;
3242
3243	#undef CPUM_MTRR_PHYSBASE_MSRRANGE
3244	#undef CPUM_MTRR_PHYSMASK_MSRRANGE
3245	}
3246
3247
3248	/**
3249	* Initialize MTRR capability based on what the guest CPU profile (typically host)
3250	* supports.
3251	*
3252	* @returns VBox status code.
3253	* @param pVM The cross context VM structure.
3254	* @param fMtrrVarCountIsVirt Whether the variable-range MTRR count is fully
3255	* virtualized (@c true) or derived from the CPU
3256	* profile (@c false).
3257	*/
3258	static int cpumR3InitMtrrCap(PVM pVM, bool fMtrrVarCountIsVirt)
3259	{
3260	#ifdef RT_ARCH_AMD64
3261	Assert(pVM->cpum.s.HostFeatures.fMtrr);
3262	#endif
3263
3264	/* Lookup the number of variable-range MTRRs supported by the CPU profile. */
3265	PCCPUMMSRRANGE pMtrrCapRange = cpumLookupMsrRange(pVM, MSR_IA32_MTRR_CAP);
3266	AssertLogRelMsgReturn(pMtrrCapRange, ("Failed to lookup IA32_MTRR_CAP MSR range\n"), VERR_NOT_FOUND);
3267	uint8_t const cProfileVarRangeRegs = pMtrrCapRange->uValue & MSR_IA32_MTRR_CAP_VCNT_MASK;
3268
3269	/* Construct guest MTRR support capabilities. */
3270	uint8_t const cGuestVarRangeRegs = fMtrrVarCountIsVirt ? CPUMCTX_MAX_MTRRVAR_COUNT
3271	: RT_MIN(cProfileVarRangeRegs, CPUMCTX_MAX_MTRRVAR_COUNT);
3272	uint64_t const uGstMtrrCap = cGuestVarRangeRegs
3273	\| MSR_IA32_MTRR_CAP_FIX
3274	\| MSR_IA32_MTRR_CAP_WC;
3275	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3276	{
3277	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3278	pVCpu->cpum.s.GuestMsrs.msr.MtrrCap = uGstMtrrCap;
3279	pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = MSR_IA32_MTRR_DEF_TYPE_FIXED_EN
3280	\| MSR_IA32_MTRR_DEF_TYPE_MTRR_EN
3281	\| X86_MTRR_MT_UC;
3282	}
3283
3284	if (fMtrrVarCountIsVirt)
3285	{
3286	/*
3287	* Insert the full variable-range MTRR MSR range ourselves so it extends beyond what is
3288	* typically reported by the hardware CPU profile.
3289	*/
3290	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (virtualized) variable-range MTRRs\n", cGuestVarRangeRegs));
3291	return cpumR3VarMtrrMsrRangeInsert(pVM, cGuestVarRangeRegs);
3292	}
3293
3294	/*
3295	* Ensure that the maximum physical address width supported by the variable-range MTRRs
3296	* are consistent with what is reported to the guest via CPUID.
3297	*/
3298	LogRel(("CPUM: Enabled fixed-range MTRRs and %u (CPU profile derived) variable-range MTRRs\n", cGuestVarRangeRegs));
3299	return cpumR3FixVarMtrrPhysAddrWidths(pVM, cGuestVarRangeRegs);
3300	}
3301
3302
3303	/**
3304	* Initializes the emulated CPU's CPUID & MSR information.
3305	*
3306	* @returns VBox status code.
3307	* @param pVM The cross context VM structure.
3308	* @param pHostMsrs Pointer to the host MSRs.
3309	*/
3310	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs)
3311	{
3312	Assert(pHostMsrs);
3313
3314	PCPUM pCpum = &pVM->cpum.s;
3315	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
3316
3317	/*
3318	* Set the fCpuIdApicFeatureVisible flags so the APIC can assume visibility
3319	* on construction and manage everything from here on.
3320	*/
3321	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3322	{
3323	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3324	pVCpu->cpum.s.fCpuIdApicFeatureVisible = true;
3325	}
3326
3327	/*
3328	* Read the configuration.
3329	*/
3330	CPUMCPUIDCONFIG Config;
3331	RT_ZERO(Config);
3332
3333	bool const fNestedPagingAndFullGuestExec = VM_IS_NEM_ENABLED(pVM)
3334	\|\| HMAreNestedPagingAndFullGuestExecEnabled(pVM);
3335	int rc = cpumR3CpuIdReadConfig(pVM, &Config, pCpumCfg, fNestedPagingAndFullGuestExec);
3336	AssertRCReturn(rc, rc);
3337
3338	/*
3339	* Get the guest CPU data from the database and/or the host.
3340	*
3341	* The CPUID and MSRs are currently living on the regular heap to avoid
3342	* fragmenting the hyper heap (and because there isn't/wasn't any realloc
3343	* API for the hyper heap). This means special cleanup considerations.
3344	*/
3345	/** @todo The hyper heap will be removed ASAP, so the final destination is
3346	* now a fixed sized arrays in the VM structure. Maybe we can simplify
3347	* this allocation fun a little now? Or maybe it's too convenient for
3348	* the CPU reporter code... No time to figure that out now. */
3349	rc = cpumR3DbGetCpuInfo(Config.szCpuName, &pCpum->GuestInfo);
3350	if (RT_FAILURE(rc))
3351	return rc == VERR_CPUM_DB_CPU_NOT_FOUND
3352	? VMSetError(pVM, rc, RT_SRC_POS,
3353	"Info on guest CPU '%s' could not be found. Please, select a different CPU.", Config.szCpuName)
3354	: rc;
3355
3356	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
3357	if (pCpum->GuestInfo.fMxCsrMask & ~pVM->cpum.s.fHostMxCsrMask)
3358	{
3359	LogRel(("Stripping unsupported MXCSR bits from guest mask: %#x -> %#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask,
3360	pCpum->GuestInfo.fMxCsrMask & pVM->cpum.s.fHostMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3361	pCpum->GuestInfo.fMxCsrMask &= pVM->cpum.s.fHostMxCsrMask;
3362	}
3363	LogRel(("CPUM: MXCSR_MASK=%#x (host: %#x)\n", pCpum->GuestInfo.fMxCsrMask, pVM->cpum.s.fHostMxCsrMask));
3364	#else
3365	LogRel(("CPUM: MXCSR_MASK=%#x\n", pCpum->GuestInfo.fMxCsrMask));
3366	#endif
3367
3368	/** @cfgm{/CPUM/MSRs/[Name]/[First\|Last\|Type\|Value\|...],}
3369	* Overrides the guest MSRs.
3370	*/
3371	rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
3372
3373	/** @cfgm{/CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
3374	* Overrides the CPUID leaf values (from the host CPU usually) used for
3375	* calculating the guest CPUID leaves. This can be used to preserve the CPUID
3376	* values when moving a VM to a different machine. Another use is restricting
3377	* (or extending) the feature set exposed to the guest. */
3378	if (RT_SUCCESS(rc))
3379	rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
3380
3381	if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
3382	rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
3383	"Found unsupported configuration node '/CPUM/CPUID/'. "
3384	"Please use IMachine::setCPUIDLeaf() instead.");
3385
3386	CPUMMSRS GuestMsrs;
3387	RT_ZERO(GuestMsrs);
3388
3389	/*
3390	* Pre-explode the CPUID info.
3391	*/
3392	if (RT_SUCCESS(rc))
3393	rc = cpumCpuIdExplodeFeaturesX86(pCpum->GuestInfo.paCpuIdLeavesR3, pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs,
3394	&pCpum->GuestFeatures);
3395
3396	/*
3397	* Sanitize the cpuid information passed on to the guest.
3398	*/
3399	if (RT_SUCCESS(rc))
3400	{
3401	rc = cpumR3CpuIdSanitize(pVM, pCpum, &Config);
3402	if (RT_SUCCESS(rc))
3403	{
3404	cpumR3CpuIdLimitLeaves(pCpum, &Config);
3405	cpumR3CpuIdLimitIntelFamModStep(pCpum, &Config);
3406	}
3407	}
3408
3409	/*
3410	* Setup MSRs introduced in microcode updates or that are otherwise not in
3411	* the CPU profile, but are advertised in the CPUID info we just sanitized.
3412	*/
3413	if (RT_SUCCESS(rc))
3414	rc = cpumR3MsrReconcileWithCpuId(pVM);
3415	/*
3416	* MSR fudging.
3417	*/
3418	if (RT_SUCCESS(rc))
3419	{
3420	/** @cfgm{/CPUM/FudgeMSRs, boolean, true}
3421	* Fudges some common MSRs if not present in the selected CPU database entry.
3422	* This is for trying to keep VMs running when moved between different hosts
3423	* and different CPU vendors. */
3424	bool fEnable;
3425	rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRC(rc);
3426	if (RT_SUCCESS(rc) && fEnable)
3427	{
3428	rc = cpumR3MsrApplyFudge(pVM);
3429	AssertLogRelRC(rc);
3430	}
3431	}
3432	if (RT_SUCCESS(rc))
3433	{
3434	/*
3435	* Move the MSR and CPUID arrays over to the static VM structure allocations
3436	* and explode guest CPU features again.
3437	*/
3438	void *pvFree = pCpum->GuestInfo.paCpuIdLeavesR3;
3439	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCpum, pCpum->GuestInfo.paCpuIdLeavesR3,
3440	pCpum->GuestInfo.cCpuIdLeaves, &GuestMsrs);
3441	RTMemFree(pvFree);
3442
3443	AssertFatalMsg(pCpum->GuestInfo.cMsrRanges <= RT_ELEMENTS(pCpum->GuestInfo.aMsrRanges),
3444	("%u\n", pCpum->GuestInfo.cMsrRanges));
3445	memcpy(pCpum->GuestInfo.aMsrRanges, pCpum->GuestInfo.paMsrRangesR3,
3446	sizeof(pCpum->GuestInfo.paMsrRangesR3[0]) * pCpum->GuestInfo.cMsrRanges);
3447	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3448	pCpum->GuestInfo.paMsrRangesR3 = pCpum->GuestInfo.aMsrRanges;
3449
3450	AssertLogRelRCReturn(rc, rc);
3451
3452	/*
3453	* Some more configuration that we're applying at the end of everything
3454	* via the CPUMR3SetGuestCpuIdFeature API.
3455	*/
3456
3457	/* Check if 64-bit guest supported was enabled. */
3458	bool fEnable64bit;
3459	rc = CFGMR3QueryBoolDef(pCpumCfg, "Enable64bit", &fEnable64bit, false);
3460	AssertRCReturn(rc, rc);
3461	if (fEnable64bit)
3462	{
3463	/* In case of a CPU upgrade: */
3464	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
3465	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
3466	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3467	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
3468	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3469
3470	/* The actual feature: */
3471	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
3472	}
3473
3474	/* Check if PAE was explicitely enabled by the user. */
3475	bool fEnable;
3476	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, fEnable64bit);
3477	AssertRCReturn(rc, rc);
3478	if (fEnable && !pVM->cpum.s.GuestFeatures.fPae)
3479	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
3480
3481	/* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
3482	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, fEnable64bit);
3483	AssertRCReturn(rc, rc);
3484	if (fEnable && !pVM->cpum.s.GuestFeatures.fNoExecute)
3485	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
3486
3487	/* Check if speculation control is enabled. */
3488	rc = CFGMR3QueryBoolDef(pCpumCfg, "SpecCtrl", &fEnable, false);
3489	AssertRCReturn(rc, rc);
3490	if (fEnable)
3491	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SPEC_CTRL);
3492	else
3493	{
3494	/*
3495	* Set the "SSBD-not-needed" flag to work around a bug in some Linux kernels when the VIRT_SPEC_CTL
3496	* feature is not exposed on AMD CPUs and there is only 1 vCPU configured.
3497	* This was observed with kernel "4.15.0-29-generic #31~16.04.1-Ubuntu" but more versions are likely affected.
3498	*
3499	* The kernel doesn't initialize a lock and causes a NULL pointer exception later on when configuring SSBD:
3500	* EIP: _raw_spin_lock+0x14/0x30
3501	* EFLAGS: 00010046 CPU: 0
3502	* EAX: 00000000 EBX: 00000001 ECX: 00000004 EDX: 00000000
3503	* ESI: 00000000 EDI: 00000000 EBP: ee023f1c ESP: ee023f18
3504	* DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
3505	* CR0: 80050033 CR2: 00000004 CR3: 3671c180 CR4: 000006f0
3506	* Call Trace:
3507	* speculative_store_bypass_update+0x8e/0x180
3508	* ssb_prctl_set+0xc0/0xe0
3509	* arch_seccomp_spec_mitigate+0x1d/0x20
3510	* do_seccomp+0x3cb/0x610
3511	* SyS_seccomp+0x16/0x20
3512	* do_fast_syscall_32+0x7f/0x1d0
3513	* entry_SYSENTER_32+0x4e/0x7c
3514	*
3515	* The lock would've been initialized in process.c:speculative_store_bypass_ht_init() called from two places in smpboot.c.
3516	* First when a secondary CPU is started and second in native_smp_prepare_cpus() which is not called in a single vCPU environment.
3517	*
3518	* As spectre control features are completely disabled anyway when we arrived here there is no harm done in informing the
3519	* guest to not even try.
3520	*/
3521	if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3522	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3523	{
3524	PCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x80000008), 0);
3525	if (pLeaf)
3526	{
3527	pLeaf->uEbx \|= X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED;
3528	LogRel(("CPUM: Set SSBD not required flag for AMD to work around some buggy Linux kernels!\n"));
3529	}
3530	}
3531	}
3532
3533	/*
3534	* MTRR support.
3535	* We've always reported the MTRR feature bit in CPUID.
3536	* Here we allow exposing MTRRs with reasonable default values (especially required
3537	* by Windows 10 guests with Hyper-V enabled). The MTRR support isn't feature
3538	* complete, see @bugref{10318} and bugref{10498}.
3539	*/
3540	if (pVM->cpum.s.GuestFeatures.fMtrr)
3541	{
3542	/** @cfgm{/CPUM/MtrrWrite, boolean, true}
3543	* Whether to enable MTRR read-write support. This overrides the MTRR read-only CFGM
3544	* setting. */
3545	bool fEnableMtrrReadWrite;
3546	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadWrite", &fEnableMtrrReadWrite, true);
3547	AssertRCReturn(rc, rc);
3548	if (fEnableMtrrReadWrite)
3549	{
3550	pVM->cpum.s.fMtrrRead = true;
3551	pVM->cpum.s.fMtrrWrite = true;
3552	LogRel(("CPUM: Enabled MTRR read-write support\n"));
3553	}
3554	else
3555	{
3556	/** @cfgm{/CPUM/MtrrReadOnly, boolean, false}
3557	* Whether to enable MTRR read-only support and to initialize mapping of guest
3558	* memory via MTRRs. When disabled, MTRRs are left blank, returns 0 on reads and
3559	* ignores writes. Some guests like GNU/Linux recognize a virtual system when MTRRs
3560	* are left blank but some guests may expect their RAM to be mapped via MTRRs
3561	* similar to real hardware. */
3562	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrReadOnly", &pVM->cpum.s.fMtrrRead, false);
3563	AssertRCReturn(rc, rc);
3564	LogRel(("CPUM: Enabled MTRR read-only support\n"));
3565	}
3566
3567	/* Setup MTRR capability based on what the guest CPU profile (typically host) supports. */
3568	Assert(!pVM->cpum.s.fMtrrWrite \|\| pVM->cpum.s.fMtrrRead);
3569	if (pVM->cpum.s.fMtrrRead)
3570	{
3571	/** @cfgm{/CPUM/MtrrVarCountIsVirtual, boolean, true}
3572	* When enabled, the number of variable-range MTRRs are virtualized. When disabled,
3573	* the number of variable-range MTRRs are derived from the CPU profile. Unless
3574	* guests have problems with a virtualized number of variable-range MTRRs, it is
3575	* recommended to keep this enabled so that there are sufficient MTRRs to fully
3576	* describe all regions of the guest RAM. */
3577	bool fMtrrVarCountIsVirt;
3578	rc = CFGMR3QueryBoolDef(pCpumCfg, "MtrrVarCountIsVirtual", &fMtrrVarCountIsVirt, true);
3579	AssertRCReturn(rc, rc);
3580
3581	rc = cpumR3InitMtrrCap(pVM, fMtrrVarCountIsVirt);
3582	if (RT_SUCCESS(rc))
3583	{ /* likely */ }
3584	else
3585	return rc;
3586	}
3587	}
3588
3589	/*
3590	* Finally, initialize guest VMX MSRs.
3591	*
3592	* This needs to be done -after- exploding guest features and sanitizing CPUID leaves
3593	* as constructing VMX capabilities MSRs rely on CPU feature bits like long mode,
3594	* unrestricted-guest execution, CR4 feature bits and possibly more in the future.
3595	*/
3596	/** @todo r=bird: given that long mode never used to be enabled before the
3597	* VMINITCOMPLETED_RING0 state, and we're a lot earlier here in ring-3
3598	* init, the above comment cannot be entirely accurate. */
3599	if (pVM->cpum.s.GuestFeatures.fVmx)
3600	{
3601	Assert(Config.fNestedHWVirt);
3602	cpumR3InitVmxGuestFeaturesAndMsrs(pVM, pCpumCfg, &pHostMsrs->hwvirt.vmx, &GuestMsrs.hwvirt.vmx);
3603
3604	/* Copy MSRs to all VCPUs */
3605	PCVMXMSRS pVmxMsrs = &GuestMsrs.hwvirt.vmx;
3606	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3607	{
3608	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3609	memcpy(&pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs, pVmxMsrs, sizeof(*pVmxMsrs));
3610	}
3611	}
3612
3613	return VINF_SUCCESS;
3614	}
3615
3616	/*
3617	* Failed before switching to hyper heap.
3618	*/
3619	RTMemFree(pCpum->GuestInfo.paCpuIdLeavesR3);
3620	pCpum->GuestInfo.paCpuIdLeavesR3 = NULL;
3621	RTMemFree(pCpum->GuestInfo.paMsrRangesR3);
3622	pCpum->GuestInfo.paMsrRangesR3 = NULL;
3623	return rc;
3624	}
3625
3626
3627	/**
3628	* Sets a CPUID feature bit during VM initialization.
3629	*
3630	* Since the CPUID feature bits are generally related to CPU features, other
3631	* CPUM configuration like MSRs can also be modified by calls to this API.
3632	*
3633	* @param pVM The cross context VM structure.
3634	* @param enmFeature The feature to set.
3635	*/
3636	VMMR3_INT_DECL(void) CPUMR3SetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3637	{
3638	PCPUMCPUIDLEAF pLeaf;
3639	PCPUMMSRRANGE pMsrRange;
3640
3641	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
3642	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3643	if (!pVM->cpum.s.HostFeatures. a_fFeature) \
3644	{ \
3645	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when the host doesn't support it!\n")); \
3646	return; \
3647	} else do { } while (0)
3648	#else
3649	# define CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) do { } while (0)
3650	#endif
3651
3652	#define GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(a_fFeature, a_szFeature) \
3653	do \
3654	{ \
3655	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001)); \
3656	if (!pLeaf) \
3657	{ \
3658	LogRel(("CPUM: WARNING! Can't turn on " a_szFeature " when no 0x80000001 CPUID leaf!\n")); \
3659	return; \
3660	} \
3661	CHECK_X86_HOST_FEATURE_RET(a_fFeature,a_szFeature); \
3662	} while (0)
3663
3664	switch (enmFeature)
3665	{
3666	/*
3667	* Set the APIC bit in both feature masks.
3668	*/
3669	case CPUMCPUIDFEATURE_APIC:
3670	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3671	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3672	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_APIC;
3673
3674	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3675	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
3676	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_APIC;
3677
3678	pVM->cpum.s.GuestFeatures.fApic = 1;
3679
3680	/* Make sure we've got the APICBASE MSR present. */
3681	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3682	if (!pMsrRange)
3683	{
3684	static CPUMMSRRANGE const s_ApicBase =
3685	{
3686	/.uFirst =/ MSR_IA32_APICBASE, /.uLast =/ MSR_IA32_APICBASE,
3687	/.enmRdFn =/ kCpumMsrRdFn_Ia32ApicBase, /.enmWrFn =/ kCpumMsrWrFn_Ia32ApicBase,
3688	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3689	/.szName = / "IA32_APIC_BASE"
3690	};
3691	int rc = CPUMR3MsrRangesInsert(pVM, &s_ApicBase);
3692	AssertLogRelRC(rc);
3693	}
3694
3695	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled xAPIC\n"));
3696	break;
3697
3698	/*
3699	* Set the x2APIC bit in the standard feature mask.
3700	* Note! ASSUMES CPUMCPUIDFEATURE_APIC is called first.
3701	*/
3702	case CPUMCPUIDFEATURE_X2APIC:
3703	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3704	if (pLeaf)
3705	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_X2APIC;
3706	pVM->cpum.s.GuestFeatures.fX2Apic = 1;
3707
3708	/* Make sure the MSR doesn't GP or ignore the EXTD bit. */
3709	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_APICBASE);
3710	if (pMsrRange)
3711	{
3712	pMsrRange->fWrGpMask &= ~MSR_IA32_APICBASE_EXTD;
3713	pMsrRange->fWrIgnMask &= ~MSR_IA32_APICBASE_EXTD;
3714	}
3715
3716	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled x2APIC\n"));
3717	break;
3718
3719	/*
3720	* Set the sysenter/sysexit bit in the standard feature mask.
3721	* Assumes the caller knows what it's doing! (host must support these)
3722	*/
3723	case CPUMCPUIDFEATURE_SEP:
3724	CHECK_X86_HOST_FEATURE_RET(fSysEnter, "SEP");
3725	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3726	if (pLeaf)
3727	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_SEP;
3728	pVM->cpum.s.GuestFeatures.fSysEnter = 1;
3729	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSENTER/EXIT\n"));
3730	break;
3731
3732	/*
3733	* Set the syscall/sysret bit in the extended feature mask.
3734	* Assumes the caller knows what it's doing! (host must support these)
3735	*/
3736	case CPUMCPUIDFEATURE_SYSCALL:
3737	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fSysCall, "SYSCALL/SYSRET");
3738
3739	/* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
3740	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
3741	pVM->cpum.s.GuestFeatures.fSysCall = 1;
3742	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled SYSCALL/RET\n"));
3743	break;
3744
3745	/*
3746	* Set the PAE bit in both feature masks.
3747	* Assumes the caller knows what it's doing! (host must support these)
3748	*/
3749	case CPUMCPUIDFEATURE_PAE:
3750	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3751	if (pLeaf)
3752	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx \|= X86_CPUID_FEATURE_EDX_PAE;
3753
3754	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3755	if ( pLeaf
3756	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3757	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
3758	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_AMD_FEATURE_EDX_PAE;
3759
3760	pVM->cpum.s.GuestFeatures.fPae = 1;
3761	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled PAE\n"));
3762	break;
3763
3764	/*
3765	* Set the LONG MODE bit in the extended feature mask.
3766	* Assumes the caller knows what it's doing! (host must support these)
3767	*/
3768	case CPUMCPUIDFEATURE_LONG_MODE:
3769	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLongMode, "LONG MODE");
3770
3771	/* Valid for both Intel and AMD. */
3772	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
3773	pVM->cpum.s.GuestFeatures.fLongMode = 1;
3774	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth;
3775	if (pVM->cpum.s.GuestFeatures.fVmx)
3776	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3777	{
3778	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3779	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic &= ~VMX_BASIC_PHYSADDR_WIDTH_32BIT;
3780	}
3781	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LONG MODE\n"));
3782	break;
3783
3784	/*
3785	* Set the NX/XD bit in the extended feature mask.
3786	* Assumes the caller knows what it's doing! (host must support these)
3787	*/
3788	case CPUMCPUIDFEATURE_NX:
3789	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fNoExecute, "NX/XD");
3790
3791	/* Valid for both Intel and AMD. */
3792	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_NX;
3793	pVM->cpum.s.GuestFeatures.fNoExecute = 1;
3794	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled NX\n"));
3795	break;
3796
3797
3798	/*
3799	* Set the LAHF/SAHF support in 64-bit mode.
3800	* Assumes the caller knows what it's doing! (host must support this)
3801	*/
3802	case CPUMCPUIDFEATURE_LAHF:
3803	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fLahfSahf, "LAHF/SAHF");
3804
3805	/* Valid for both Intel and AMD. */
3806	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx \|= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
3807	pVM->cpum.s.GuestFeatures.fLahfSahf = 1;
3808	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
3809	break;
3810
3811	/*
3812	* Set the RDTSCP support bit.
3813	* Assumes the caller knows what it's doing! (host must support this)
3814	*/
3815	case CPUMCPUIDFEATURE_RDTSCP:
3816	if (pVM->cpum.s.u8PortableCpuIdLevel > 0)
3817	return;
3818	GET_8000_0001_CHECK_X86_HOST_FEATURE_RET(fRdTscP, "RDTSCP");
3819	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
3820
3821	/* Valid for both Intel and AMD. */
3822	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx \|= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
3823	pVM->cpum.s.HostFeatures.fRdTscP = 1;
3824	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled RDTSCP.\n"));
3825	break;
3826
3827	/*
3828	* Set the Hypervisor Present bit in the standard feature mask.
3829	*/
3830	case CPUMCPUIDFEATURE_HVP:
3831	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3832	if (pLeaf)
3833	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx \|= X86_CPUID_FEATURE_ECX_HVP;
3834	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 1;
3835	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
3836	break;
3837
3838	/*
3839	* Set up the speculation control CPUID bits and MSRs. This is quite complicated
3840	* on Intel CPUs, and different on AMDs.
3841	*/
3842	case CPUMCPUIDFEATURE_SPEC_CTRL:
3843	if (pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
3844	{
3845	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
3846	if ( !pLeaf
3847	\|\| !(pVM->cpum.s.HostFeatures.fIbpb \|\| pVM->cpum.s.HostFeatures.fIbrs))
3848	{
3849	LogRel(("CPUM: WARNING! Can't turn on Speculation Control when the host doesn't support it!\n"));
3850	return;
3851	}
3852
3853	/* The feature can be enabled. Let's see what we can actually do. */
3854	pVM->cpum.s.GuestFeatures.fSpeculationControl = 1;
3855
3856	/* We will only expose STIBP if IBRS is present to keep things simpler (simple is not an option). */
3857	if (pVM->cpum.s.HostFeatures.fIbrs)
3858	{
3859	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB;
3860	pVM->cpum.s.GuestFeatures.fIbrs = 1;
3861	if (pVM->cpum.s.HostFeatures.fStibp)
3862	{
3863	pLeaf->uEdx \|= X86_CPUID_STEXT_FEATURE_EDX_STIBP;
3864	pVM->cpum.s.GuestFeatures.fStibp = 1;
3865	}
3866
3867	/* Make sure we have the speculation control MSR... */
3868	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_SPEC_CTRL);
3869	if (!pMsrRange)
3870	{
3871	static CPUMMSRRANGE const s_SpecCtrl =
3872	{
3873	/.uFirst =/ MSR_IA32_SPEC_CTRL, /.uLast =/ MSR_IA32_SPEC_CTRL,
3874	/.enmRdFn =/ kCpumMsrRdFn_Ia32SpecCtrl, /.enmWrFn =/ kCpumMsrWrFn_Ia32SpecCtrl,
3875	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3876	/.szName = / "IA32_SPEC_CTRL"
3877	};
3878	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3879	AssertLogRelRC(rc);
3880	}
3881
3882	/* ... and the predictor command MSR. */
3883	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_PRED_CMD);
3884	if (!pMsrRange)
3885	{
3886	/** @todo incorrect fWrGpMask. */
3887	static CPUMMSRRANGE const s_SpecCtrl =
3888	{
3889	/.uFirst =/ MSR_IA32_PRED_CMD, /.uLast =/ MSR_IA32_PRED_CMD,
3890	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly, /.enmWrFn =/ kCpumMsrWrFn_Ia32PredCmd,
3891	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ 0,
3892	/.szName = / "IA32_PRED_CMD"
3893	};
3894	int rc = CPUMR3MsrRangesInsert(pVM, &s_SpecCtrl);
3895	AssertLogRelRC(rc);
3896	}
3897
3898	}
3899
3900	if (pVM->cpum.s.HostFeatures.fArchCap)
3901	{
3902	/* Install the architectural capabilities MSR. */
3903	pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
3904	if (!pMsrRange)
3905	{
3906	static CPUMMSRRANGE const s_ArchCaps =
3907	{
3908	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES, /.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
3909	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities, /.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
3910	/.offCpumCpu =/ UINT16_MAX, /.fReserved =/ 0, /.uValue =/ 0, /.fWrIgnMask =/ 0, /.fWrGpMask =/ UINT64_MAX,
3911	/.szName = / "IA32_ARCH_CAPABILITIES"
3912	};
3913	int rc = CPUMR3MsrRangesInsert(pVM, &s_ArchCaps);
3914	AssertLogRelRC(rc);
3915	}
3916
3917	/* Advertise IBRS_ALL if present at this point... */
3918	if (pVM->cpum.s.HostFeatures.fArchCap & MSR_IA32_ARCH_CAP_F_IBRS_ALL)
3919	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps \|= MSR_IA32_ARCH_CAP_F_IBRS_ALL);
3920	}
3921
3922	LogRel(("CPUM: SetGuestCpuIdFeature: Enabled Speculation Control.\n"));
3923	}
3924	else if ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
3925	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON)
3926	{
3927	/* The precise details of AMD's implementation are not yet clear. */
3928	}
3929	break;
3930
3931	default:
3932	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
3933	break;
3934	}
3935
3936	/** @todo can probably kill this as this API is now init time only... */
3937	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3938	{
3939	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3940	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
3941	}
3942
3943	#undef GET_8000_0001_CHECK_X86_HOST_FEATURE_RET
3944	#undef CHECK_X86_HOST_FEATURE_RET
3945	}
3946
3947
3948	/**
3949	* Queries a CPUID feature bit.
3950	*
3951	* @returns boolean for feature presence
3952	* @param pVM The cross context VM structure.
3953	* @param enmFeature The feature to query.
3954	* @deprecated Use the cpum.ro.GuestFeatures directly instead.
3955	*/
3956	VMMR3_INT_DECL(bool) CPUMR3GetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3957	{
3958	switch (enmFeature)
3959	{
3960	case CPUMCPUIDFEATURE_APIC: return pVM->cpum.s.GuestFeatures.fApic;
3961	case CPUMCPUIDFEATURE_X2APIC: return pVM->cpum.s.GuestFeatures.fX2Apic;
3962	case CPUMCPUIDFEATURE_SYSCALL: return pVM->cpum.s.GuestFeatures.fSysCall;
3963	case CPUMCPUIDFEATURE_SEP: return pVM->cpum.s.GuestFeatures.fSysEnter;
3964	case CPUMCPUIDFEATURE_PAE: return pVM->cpum.s.GuestFeatures.fPae;
3965	case CPUMCPUIDFEATURE_NX: return pVM->cpum.s.GuestFeatures.fNoExecute;
3966	case CPUMCPUIDFEATURE_LAHF: return pVM->cpum.s.GuestFeatures.fLahfSahf;
3967	case CPUMCPUIDFEATURE_LONG_MODE: return pVM->cpum.s.GuestFeatures.fLongMode;
3968	case CPUMCPUIDFEATURE_RDTSCP: return pVM->cpum.s.GuestFeatures.fRdTscP;
3969	case CPUMCPUIDFEATURE_HVP: return pVM->cpum.s.GuestFeatures.fHypervisorPresent;
3970	case CPUMCPUIDFEATURE_SPEC_CTRL: return pVM->cpum.s.GuestFeatures.fSpeculationControl;
3971	case CPUMCPUIDFEATURE_INVALID:
3972	case CPUMCPUIDFEATURE_32BIT_HACK:
3973	break;
3974	}
3975	AssertFailed();
3976	return false;
3977	}
3978
3979
3980	/**
3981	* Clears a CPUID feature bit.
3982	*
3983	* @param pVM The cross context VM structure.
3984	* @param enmFeature The feature to clear.
3985	*
3986	* @deprecated Probably better to default the feature to disabled and only allow
3987	* setting (enabling) it during construction.
3988	*/
3989	VMMR3_INT_DECL(void) CPUMR3ClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
3990	{
3991	PCPUMCPUIDLEAF pLeaf;
3992	switch (enmFeature)
3993	{
3994	case CPUMCPUIDFEATURE_APIC:
3995	Assert(!pVM->cpum.s.GuestFeatures.fApic); /* We only expect this call during init. No MSR adjusting needed. */
3996	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
3997	if (pLeaf)
3998	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_APIC;
3999
4000	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4001	if (pLeaf && (pLeaf->fFlags & CPUMCPUIDLEAF_F_CONTAINS_APIC))
4002	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
4003
4004	pVM->cpum.s.GuestFeatures.fApic = 0;
4005	Log(("CPUM: ClearGuestCpuIdFeature: Disabled xAPIC\n"));
4006	break;
4007
4008	case CPUMCPUIDFEATURE_X2APIC:
4009	Assert(!pVM->cpum.s.GuestFeatures.fX2Apic); /* We only expect this call during init. No MSR adjusting needed. */
4010	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4011	if (pLeaf)
4012	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
4013	pVM->cpum.s.GuestFeatures.fX2Apic = 0;
4014	Log(("CPUM: ClearGuestCpuIdFeature: Disabled x2APIC\n"));
4015	break;
4016
4017	#if 0
4018	case CPUMCPUIDFEATURE_PAE:
4019	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4020	if (pLeaf)
4021	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_FEATURE_EDX_PAE;
4022
4023	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4024	if ( pLeaf
4025	&& ( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD
4026	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_HYGON))
4027	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
4028
4029	pVM->cpum.s.GuestFeatures.fPae = 0;
4030	Log(("CPUM: ClearGuestCpuIdFeature: Disabled PAE!\n"));
4031	break;
4032
4033	case CPUMCPUIDFEATURE_LONG_MODE:
4034	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4035	if (pLeaf)
4036	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
4037	pVM->cpum.s.GuestFeatures.fLongMode = 0;
4038	pVM->cpum.s.GuestFeatures.cVmxMaxPhysAddrWidth = 32;
4039	if (pVM->cpum.s.GuestFeatures.fVmx)
4040	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4041	{
4042	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4043	pVCpu->cpum.s.Guest.hwvirt.vmx.Msrs.u64Basic \|= VMX_BASIC_PHYSADDR_WIDTH_32BIT;
4044	}
4045	break;
4046
4047	case CPUMCPUIDFEATURE_LAHF:
4048	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4049	if (pLeaf)
4050	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
4051	pVM->cpum.s.GuestFeatures.fLahfSahf = 0;
4052	break;
4053	#endif
4054	case CPUMCPUIDFEATURE_RDTSCP:
4055	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4056	if (pLeaf)
4057	pVM->cpum.s.aGuestCpuIdPatmExt[1].uEdx = pLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
4058	pVM->cpum.s.GuestFeatures.fRdTscP = 0;
4059	Log(("CPUM: ClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
4060	break;
4061
4062	#if 0
4063	case CPUMCPUIDFEATURE_HVP:
4064	pLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4065	if (pLeaf)
4066	pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx = pLeaf->uEcx &= ~X86_CPUID_FEATURE_ECX_HVP;
4067	pVM->cpum.s.GuestFeatures.fHypervisorPresent = 0;
4068	break;
4069
4070	case CPUMCPUIDFEATURE_SPEC_CTRL:
4071	pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
4072	if (pLeaf)
4073	pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB \| X86_CPUID_STEXT_FEATURE_EDX_STIBP);
4074	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps &= ~MSR_IA32_ARCH_CAP_F_IBRS_ALL);
4075	Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
4076	break;
4077	#endif
4078	default:
4079	AssertMsgFailed(("enmFeature=%d\n", enmFeature));
4080	break;
4081	}
4082
4083	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4084	{
4085	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4086	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_CPUID;
4087	}
4088	}
4089
4090
4091	/**
4092	* Do some final polishing after all calls to CPUMR3SetGuestCpuIdFeature and
4093	* CPUMR3ClearGuestCpuIdFeature are (probably) done.
4094	*
4095	* @param pVM The cross context VM structure.
4096	*/
4097	void cpumR3CpuIdRing3InitDone(PVM pVM)
4098	{
4099	/*
4100	* Do not advertise NX w/o PAE, seems to confuse windows 7 (black screen very
4101	* early in real mode).
4102	*/
4103	PCPUMCPUIDLEAF pStdLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x00000001));
4104	PCPUMCPUIDLEAF pExtLeaf = cpumCpuIdGetLeaf(pVM, UINT32_C(0x80000001));
4105	if (pStdLeaf && pExtLeaf)
4106	{
4107	if ( !(pStdLeaf->uEdx & X86_CPUID_FEATURE_EDX_PAE)
4108	&& (pExtLeaf->uEdx & X86_CPUID_EXT_FEATURE_EDX_NX))
4109	pExtLeaf->uEdx &= ~X86_CPUID_EXT_FEATURE_EDX_NX;
4110	}
4111	}
4112
4113
4114	/*
4115	*
4116	*
4117	* Saved state related code.
4118	* Saved state related code.
4119	* Saved state related code.
4120	*
4121	*
4122	*/
4123
4124	/**
4125	* Called both in pass 0 and the final pass.
4126	*
4127	* @param pVM The cross context VM structure.
4128	* @param pSSM The saved state handle.
4129	*/
4130	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
4131	{
4132	/*
4133	* Save all the CPU ID leaves.
4134	*/
4135	SSMR3PutU32(pSSM, sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]));
4136	SSMR3PutU32(pSSM, pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4137	SSMR3PutMem(pSSM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3,
4138	sizeof(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3[0]) * pVM->cpum.s.GuestInfo.cCpuIdLeaves);
4139
4140	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4141
4142	/*
4143	* Save a good portion of the raw CPU IDs as well as they may come in
4144	* handy when validating features for raw mode.
4145	*/
4146	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4147	CPUMCPUID aRawStd[16];
4148	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
4149	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4150	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
4151	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
4152
4153	CPUMCPUID aRawExt[32];
4154	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
4155	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4156	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
4157	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
4158
4159	#else
4160	/* Two zero counts on non-x86 hosts. */
4161	SSMR3PutU32(pSSM, 0);
4162	SSMR3PutU32(pSSM, 0);
4163	#endif
4164	}
4165
4166
4167	static int cpumR3LoadOneOldGuestCpuIdArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4168	{
4169	uint32_t cCpuIds;
4170	int rc = SSMR3GetU32(pSSM, &cCpuIds);
4171	if (RT_SUCCESS(rc))
4172	{
4173	if (cCpuIds < 64)
4174	{
4175	for (uint32_t i = 0; i < cCpuIds; i++)
4176	{
4177	CPUMCPUID CpuId;
4178	rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
4179	if (RT_FAILURE(rc))
4180	break;
4181
4182	CPUMCPUIDLEAF NewLeaf;
4183	NewLeaf.uLeaf = uBase + i;
4184	NewLeaf.uSubLeaf = 0;
4185	NewLeaf.fSubLeafMask = 0;
4186	NewLeaf.uEax = CpuId.uEax;
4187	NewLeaf.uEbx = CpuId.uEbx;
4188	NewLeaf.uEcx = CpuId.uEcx;
4189	NewLeaf.uEdx = CpuId.uEdx;
4190	NewLeaf.fFlags = 0;
4191	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &NewLeaf);
4192	}
4193	}
4194	else
4195	rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4196	}
4197	if (RT_FAILURE(rc))
4198	{
4199	RTMemFree(*ppaLeaves);
4200	*ppaLeaves = NULL;
4201	*pcLeaves = 0;
4202	}
4203	return rc;
4204	}
4205
4206
4207	static int cpumR3LoadGuestCpuIdArray(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves)
4208	{
4209	*ppaLeaves = NULL;
4210	*pcLeaves = 0;
4211
4212	int rc;
4213	if (uVersion > CPUM_SAVED_STATE_VERSION_PUT_STRUCT)
4214	{
4215	/*
4216	* The new format. Starts by declaring the leave size and count.
4217	*/
4218	uint32_t cbLeaf;
4219	SSMR3GetU32(pSSM, &cbLeaf);
4220	uint32_t cLeaves;
4221	rc = SSMR3GetU32(pSSM, &cLeaves);
4222	if (RT_SUCCESS(rc))
4223	{
4224	if (cbLeaf == sizeof(**ppaLeaves))
4225	{
4226	if (cLeaves <= CPUM_CPUID_MAX_LEAVES)
4227	{
4228	/*
4229	* Load the leaves one by one.
4230	*
4231	* The uPrev stuff is a kludge for working around a week worth of bad saved
4232	* states during the CPUID revamp in March 2015. We saved too many leaves
4233	* due to a bug in cpumR3CpuIdInstallAndExplodeLeaves, thus ending up with
4234	* garbage entires at the end of the array when restoring. We also had
4235	* a subleaf insertion bug that triggered with the leaf 4 stuff below,
4236	* this kludge doesn't deal correctly with that, but who cares...
4237	*/
4238	uint32_t uPrev = 0;
4239	for (uint32_t i = 0; i < cLeaves && RT_SUCCESS(rc); i++)
4240	{
4241	CPUMCPUIDLEAF Leaf;
4242	rc = SSMR3GetMem(pSSM, &Leaf, sizeof(Leaf));
4243	if (RT_SUCCESS(rc))
4244	{
4245	if ( uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
4246	\|\| Leaf.uLeaf >= uPrev)
4247	{
4248	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4249	uPrev = Leaf.uLeaf;
4250	}
4251	else
4252	uPrev = UINT32_MAX;
4253	}
4254	}
4255	}
4256	else
4257	rc = SSMR3SetLoadError(pSSM, VERR_TOO_MANY_CPUID_LEAVES, RT_SRC_POS,
4258	"Too many CPUID leaves: %#x, max %#x", cLeaves, CPUM_CPUID_MAX_LEAVES);
4259	}
4260	else
4261	rc = SSMR3SetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4262	"CPUMCPUIDLEAF size differs: saved=%#x, our=%#x", cbLeaf, sizeof(**ppaLeaves));
4263	}
4264	}
4265	else
4266	{
4267	/*
4268	* The old format with its three inflexible arrays.
4269	*/
4270	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
4271	if (RT_SUCCESS(rc))
4272	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
4273	if (RT_SUCCESS(rc))
4274	rc = cpumR3LoadOneOldGuestCpuIdArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
4275	if (RT_SUCCESS(rc))
4276	{
4277	/*
4278	* Fake up leaf 4 on intel like we used to do in CPUMGetGuestCpuId earlier.
4279	*/
4280	PCPUMCPUIDLEAF pLeaf = cpumCpuIdGetLeafInt(ppaLeaves, pcLeaves, 0, 0);
4281	if ( pLeaf
4282	&& RTX86IsIntelCpu(pLeaf->uEbx, pLeaf->uEcx, pLeaf->uEdx))
4283	{
4284	CPUMCPUIDLEAF Leaf;
4285	Leaf.uLeaf = 4;
4286	Leaf.fSubLeafMask = UINT32_MAX;
4287	Leaf.uSubLeaf = 0;
4288	Leaf.uEdx = UINT32_C(0); /* 3 flags, 0 is fine. */
4289	Leaf.uEcx = UINT32_C(63); /* sets - 1 */
4290	Leaf.uEbx = (UINT32_C(7) << 22) /* associativity -1 */
4291	\| (UINT32_C(0) << 12) /* phys line partitions - 1 */
4292	\| UINT32_C(63); /* system coherency line size - 1 */
4293	Leaf.uEax = (RT_MIN(pVM->cCpus - 1, UINT32_C(0x3f)) << 26) /* cores per package - 1 */
4294	\| (UINT32_C(0) << 14) /* threads per cache - 1 */
4295	\| (UINT32_C(1) << 5) /* cache level */
4296	\| UINT32_C(1); /* cache type (data) */
4297	Leaf.fFlags = 0;
4298	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4299	if (RT_SUCCESS(rc))
4300	{
4301	Leaf.uSubLeaf = 1; /* Should've been cache type 2 (code), but buggy code made it data. */
4302	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4303	}
4304	if (RT_SUCCESS(rc))
4305	{
4306	Leaf.uSubLeaf = 2; /* Should've been cache type 3 (unified), but buggy code made it data. */
4307	Leaf.uEcx = 4095; /* sets - 1 */
4308	Leaf.uEbx &= UINT32_C(0x003fffff); /* associativity - 1 */
4309	Leaf.uEbx \|= UINT32_C(23) << 22;
4310	Leaf.uEax &= UINT32_C(0xfc003fff); /* threads per cache - 1 */
4311	Leaf.uEax \|= RT_MIN(pVM->cCpus - 1, UINT32_C(0xfff)) << 14;
4312	Leaf.uEax &= UINT32_C(0xffffff1f); /* level */
4313	Leaf.uEax \|= UINT32_C(2) << 5;
4314	rc = cpumR3CpuIdInsert(NULL /* pVM */, ppaLeaves, pcLeaves, &Leaf);
4315	}
4316	}
4317	}
4318	}
4319	return rc;
4320	}
4321
4322
4323	/**
4324	* Loads the CPU ID leaves saved by pass 0, inner worker.
4325	*
4326	* @returns VBox status code.
4327	* @param pVM The cross context VM structure.
4328	* @param pSSM The saved state handle.
4329	* @param uVersion The format version.
4330	* @param paLeaves Guest CPUID leaves loaded from the state.
4331	* @param cLeaves The number of leaves in @a paLeaves.
4332	* @param pMsrs The guest MSRs.
4333	*/
4334	static int cpumR3LoadCpuIdInner(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs)
4335	{
4336	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4337	#if !defined(RT_ARCH_AMD64) && !defined(RT_ARCH_X86)
4338	AssertMsgFailed(("Port me!"));
4339	#endif
4340
4341	/*
4342	* Continue loading the state into stack buffers.
4343	*/
4344	CPUMCPUID GuestDefCpuId;
4345	int rc = SSMR3GetMem(pSSM, &GuestDefCpuId, sizeof(GuestDefCpuId));
4346	AssertRCReturn(rc, rc);
4347
4348	CPUMCPUID aRawStd[16];
4349	uint32_t cRawStd;
4350	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
4351	if (cRawStd > RT_ELEMENTS(aRawStd))
4352	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4353	rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
4354	AssertRCReturn(rc, rc);
4355	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
4356	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4357	ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].uEax, &aRawStd[i].uEbx, &aRawStd[i].uEcx, &aRawStd[i].uEdx);
4358	#else
4359	RT_ZERO(aRawStd[i]);
4360	#endif
4361
4362	CPUMCPUID aRawExt[32];
4363	uint32_t cRawExt;
4364	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
4365	if (cRawExt > RT_ELEMENTS(aRawExt))
4366	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4367	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
4368	AssertRCReturn(rc, rc);
4369	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
4370	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4371	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].uEax, &aRawExt[i].uEbx, &aRawExt[i].uEcx, &aRawExt[i].uEdx);
4372	#else
4373	RT_ZERO(aRawExt[i]);
4374	#endif
4375
4376	/*
4377	* Get the raw CPU IDs for the current host.
4378	*/
4379	CPUMCPUID aHostRawStd[16];
4380	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4381	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
4382	ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].uEax, &aHostRawStd[i].uEbx, &aHostRawStd[i].uEcx, &aHostRawStd[i].uEdx);
4383	#else
4384	RT_ZERO(aHostRawStd);
4385	#endif
4386
4387	CPUMCPUID aHostRawExt[32];
4388	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4389	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
4390	ASMCpuIdExSlow(i \| UINT32_C(0x80000000), 0, 0, 0,
4391	&aHostRawExt[i].uEax, &aHostRawExt[i].uEbx, &aHostRawExt[i].uEcx, &aHostRawExt[i].uEdx);
4392	#else
4393	RT_ZERO(aHostRawExt);
4394	#endif
4395
4396	/*
4397	* Get the host and guest overrides so we don't reject the state because
4398	* some feature was enabled thru these interfaces.
4399	* Note! We currently only need the feature leaves, so skip rest.
4400	*/
4401	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
4402	CPUMCPUID aHostOverrideStd[2];
4403	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
4404	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
4405
4406	CPUMCPUID aHostOverrideExt[2];
4407	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
4408	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
4409
4410	/*
4411	* This can be skipped.
4412	*/
4413	bool fStrictCpuIdChecks;
4414	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
4415
4416	/*
4417	* Define a bunch of macros for simplifying the santizing/checking code below.
4418	*/
4419	/* Generic expression + failure message. */
4420	#define CPUID_CHECK_RET(expr, fmt) \
4421	do { \
4422	if (!(expr)) \
4423	{ \
4424	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
4425	if (fStrictCpuIdChecks) \
4426	{ \
4427	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
4428	RTStrFree(pszMsg); \
4429	return rcCpuid; \
4430	} \
4431	LogRel(("CPUM: %s\n", pszMsg)); \
4432	RTStrFree(pszMsg); \
4433	} \
4434	} while (0)
4435	#define CPUID_CHECK_WRN(expr, fmt) \
4436	do { \
4437	if (!(expr)) \
4438	LogRel(fmt); \
4439	} while (0)
4440
4441	/* For comparing two values and bitch if they differs. */
4442	#define CPUID_CHECK2_RET(what, host, saved) \
4443	do { \
4444	if ((host) != (saved)) \
4445	{ \
4446	if (fStrictCpuIdChecks) \
4447	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4448	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
4449	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4450	} \
4451	} while (0)
4452	#define CPUID_CHECK2_WRN(what, host, saved) \
4453	do { \
4454	if ((host) != (saved)) \
4455	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
4456	} while (0)
4457
4458	/* For checking raw cpu features (raw mode). */
4459	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
4460	do { \
4461	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4462	{ \
4463	if (fStrictCpuIdChecks) \
4464	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4465	N_(#bit " mismatch: host=%d saved=%d"), \
4466	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
4467	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4468	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4469	} \
4470	} while (0)
4471	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
4472	do { \
4473	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
4474	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
4475	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
4476	} while (0)
4477	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
4478
4479	/* For checking guest features. */
4480	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
4481	do { \
4482	if ( (aGuestCpuId##set [1].reg & bit) \
4483	&& !(aHostRaw##set [1].reg & bit) \
4484	&& !(aHostOverride##set [1].reg & bit) \
4485	) \
4486	{ \
4487	if (fStrictCpuIdChecks) \
4488	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4489	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4490	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4491	} \
4492	} while (0)
4493	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
4494	do { \
4495	if ( (aGuestCpuId##set [1].reg & bit) \
4496	&& !(aHostRaw##set [1].reg & bit) \
4497	&& !(aHostOverride##set [1].reg & bit) \
4498	) \
4499	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4500	} while (0)
4501	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
4502	do { \
4503	if ( (aGuestCpuId##set [1].reg & bit) \
4504	&& !(aHostRaw##set [1].reg & bit) \
4505	&& !(aHostOverride##set [1].reg & bit) \
4506	) \
4507	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4508	} while (0)
4509	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
4510
4511	/* For checking guest features if AMD guest CPU. */
4512	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
4513	do { \
4514	if ( (aGuestCpuId##set [1].reg & bit) \
4515	&& fGuestAmd \
4516	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4517	&& !(aHostOverride##set [1].reg & bit) \
4518	) \
4519	{ \
4520	if (fStrictCpuIdChecks) \
4521	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4522	N_(#bit " is not supported by the host but has already exposed to the guest")); \
4523	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4524	} \
4525	} while (0)
4526	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
4527	do { \
4528	if ( (aGuestCpuId##set [1].reg & bit) \
4529	&& fGuestAmd \
4530	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4531	&& !(aHostOverride##set [1].reg & bit) \
4532	) \
4533	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
4534	} while (0)
4535	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
4536	do { \
4537	if ( (aGuestCpuId##set [1].reg & bit) \
4538	&& fGuestAmd \
4539	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
4540	&& !(aHostOverride##set [1].reg & bit) \
4541	) \
4542	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4543	} while (0)
4544	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
4545
4546	/* For checking AMD features which have a corresponding bit in the standard
4547	range. (Intel defines very few bits in the extended feature sets.) */
4548	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
4549	do { \
4550	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4551	&& !(fHostAmd \
4552	? aHostRawExt[1].reg & (ExtBit) \
4553	: aHostRawStd[1].reg & (StdBit)) \
4554	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4555	) \
4556	{ \
4557	if (fStrictCpuIdChecks) \
4558	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
4559	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
4560	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4561	} \
4562	} while (0)
4563	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
4564	do { \
4565	if ( (aGuestCpuId[1].reg & (ExtBit)) \
4566	&& !(fHostAmd \
4567	? aHostRawExt[1].reg & (ExtBit) \
4568	: aHostRawStd[1].reg & (StdBit)) \
4569	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4570	) \
4571	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
4572	} while (0)
4573	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
4574	do { \
4575	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
4576	&& !(fHostAmd \
4577	? aHostRawExt[1].reg & (ExtBit) \
4578	: aHostRawStd[1].reg & (StdBit)) \
4579	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
4580	) \
4581	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
4582	} while (0)
4583	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
4584
4585
4586	/*
4587	* Verify that we can support the features already exposed to the guest on
4588	* this host.
4589	*
4590	* Most of the features we're emulating requires intercepting instruction
4591	* and doing it the slow way, so there is no need to warn when they aren't
4592	* present in the host CPU. Thus we use IGN instead of EMU on these.
4593	*
4594	* Trailing comments:
4595	* "EMU" - Possible to emulate, could be lots of work and very slow.
4596	* "EMU?" - Can this be emulated?
4597	*/
4598	CPUMCPUID aGuestCpuIdStd[2];
4599	RT_ZERO(aGuestCpuIdStd);
4600	cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
4601
4602	/* CPUID(1).ecx */
4603	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
4604	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
4605	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
4606	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_MONITOR);
4607	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
4608	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
4609	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
4610	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
4611	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
4612	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
4613	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
4614	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_SDBG);
4615	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
4616	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
4617	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
4618	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
4619	CPUID_GST_FEATURE_RET(Std, uEcx, RT_BIT_32(16) /reserved/);
4620	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_PCID);
4621	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
4622	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
4623	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
4624	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_X2APIC);
4625	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
4626	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
4627	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_TSCDEADL);
4628	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
4629	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
4630	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_OSXSAVE);
4631	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
4632	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_F16C);
4633	CPUID_GST_FEATURE_RET(Std, uEcx, X86_CPUID_FEATURE_ECX_RDRAND);
4634	CPUID_GST_FEATURE_IGN(Std, uEcx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
4635
4636	/* CPUID(1).edx */
4637	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FPU);
4638	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_VME);
4639	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
4640	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE);
4641	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4642	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4643	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PAE);
4644	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCE);
4645	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4646	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_APIC);
4647	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(10) /reserved/);
4648	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_SEP);
4649	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MTRR);
4650	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PGE);
4651	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_MCA);
4652	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4653	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PAT);
4654	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSE36);
4655	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_PSN);
4656	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
4657	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(20) /reserved/);
4658	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
4659	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
4660	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4661	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4662	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
4663	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
4664	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
4665	CPUID_GST_FEATURE_IGN(Std, uEdx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
4666	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
4667	CPUID_GST_FEATURE_RET(Std, uEdx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
4668	CPUID_GST_FEATURE_RET(Std, uEdx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
4669
4670	/* CPUID(0x80000000). */
4671	CPUMCPUID aGuestCpuIdExt[2];
4672	RT_ZERO(aGuestCpuIdExt);
4673	if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
4674	{
4675	/** @todo deal with no 0x80000001 on the host. */
4676	bool const fHostAmd = RTX86IsAmdCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx)
4677	\|\| RTX86IsHygonCpu(aHostRawStd[0].uEbx, aHostRawStd[0].uEcx, aHostRawStd[0].uEdx);
4678	bool const fGuestAmd = RTX86IsAmdCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx)
4679	\|\| RTX86IsHygonCpu(aGuestCpuIdExt[0].uEbx, aGuestCpuIdExt[0].uEcx, aGuestCpuIdExt[0].uEdx);
4680
4681	/* CPUID(0x80000001).ecx */
4682	CPUID_GST_FEATURE_WRN(Ext, uEcx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
4683	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
4684	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
4685	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
4686	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
4687	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
4688	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
4689	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
4690	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
4691	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
4692	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
4693	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_XOP); // -> EMU
4694	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
4695	CPUID_GST_AMD_FEATURE_RET(Ext, uEcx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
4696	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(14));
4697	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(15));
4698	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(16));
4699	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(17));
4700	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(18));
4701	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(19));
4702	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(20));
4703	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(21));
4704	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(22));
4705	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(23));
4706	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(24));
4707	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(25));
4708	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(26));
4709	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(27));
4710	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(28));
4711	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(29));
4712	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(30));
4713	CPUID_GST_AMD_FEATURE_WRN(Ext, uEcx, RT_BIT_32(31));
4714
4715	/* CPUID(0x80000001).edx */
4716	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
4717	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
4718	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
4719	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
4720	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
4721	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
4722	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
4723	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
4724	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
4725	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
4726	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(10) /reserved/);
4727	CPUID_GST_FEATURE_IGN( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
4728	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
4729	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
4730	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
4731	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
4732	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
4733	CPUID_GST_FEATURE2_IGN( uEdx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
4734	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(18) /reserved/);
4735	CPUID_GST_AMD_FEATURE_WRN(Ext, uEdx, RT_BIT_32(19) /reserved/);
4736	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_NX);
4737	CPUID_GST_FEATURE_WRN( Ext, uEdx, RT_BIT_32(21) /reserved/);
4738	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
4739	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
4740	CPUID_GST_FEATURE2_RET( uEdx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
4741	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
4742	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
4743	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
4744	CPUID_GST_FEATURE_IGN( Ext, uEdx, RT_BIT_32(28) /reserved/);
4745	CPUID_GST_FEATURE_RET( Ext, uEdx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
4746	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
4747	CPUID_GST_AMD_FEATURE_RET(Ext, uEdx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
4748	}
4749
4750	/** @todo check leaf 7 */
4751
4752	/* CPUID(d) - XCR0 stuff - takes ECX as input.
4753	* ECX=0: EAX - Valid bits in XCR0[31:0].
4754	* EBX - Maximum state size as per current XCR0 value.
4755	* ECX - Maximum state size for all supported features.
4756	* EDX - Valid bits in XCR0[63:32].
4757	* ECX=1: EAX - Various X-features.
4758	* EBX - Maximum state size as per current XCR0\|IA32_XSS value.
4759	* ECX - Valid bits in IA32_XSS[31:0].
4760	* EDX - Valid bits in IA32_XSS[63:32].
4761	* ECX=N, where N in 2..63 and indicates a bit in XCR0 and/or IA32_XSS,
4762	* if the bit invalid all four registers are set to zero.
4763	* EAX - The state size for this feature.
4764	* EBX - The state byte offset of this feature.
4765	* ECX - Bit 0 indicates whether this sub-leaf maps to a valid IA32_XSS bit (=1) or a valid XCR0 bit (=0).
4766	* EDX - Reserved, but is set to zero if invalid sub-leaf index.
4767	*/
4768	uint64_t fGuestXcr0Mask = 0;
4769	PCPUMCPUIDLEAF pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0);
4770	if ( pCurLeaf
4771	&& (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE)
4772	&& ( pCurLeaf->uEax
4773	\|\| pCurLeaf->uEbx
4774	\|\| pCurLeaf->uEcx
4775	\|\| pCurLeaf->uEdx) )
4776	{
4777	fGuestXcr0Mask = RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx);
4778	if (fGuestXcr0Mask & ~pVM->cpum.s.fXStateHostMask)
4779	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4780	N_("CPUID(0xd/0).EDX:EAX mismatch: %#llx saved, %#llx supported by the current host (XCR0 bits)"),
4781	fGuestXcr0Mask, pVM->cpum.s.fXStateHostMask);
4782	if ((fGuestXcr0Mask & (XSAVE_C_X87 \| XSAVE_C_SSE)) != (XSAVE_C_X87 \| XSAVE_C_SSE))
4783	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4784	N_("CPUID(0xd/0).EDX:EAX missing mandatory X87 or SSE bits: %#RX64"), fGuestXcr0Mask);
4785
4786	/* We don't support any additional features yet. */
4787	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 1);
4788	if (pCurLeaf && pCurLeaf->uEax)
4789	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4790	N_("CPUID(0xd/1).EAX=%#x, expected zero"), pCurLeaf->uEax);
4791	if (pCurLeaf && (pCurLeaf->uEcx \|\| pCurLeaf->uEdx))
4792	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4793	N_("CPUID(0xd/1).EDX:ECX=%#llx, expected zero"),
4794	RT_MAKE_U64(pCurLeaf->uEdx, pCurLeaf->uEcx));
4795
4796
4797	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4798	for (uint32_t uSubLeaf = 2; uSubLeaf < 64; uSubLeaf++)
4799	{
4800	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4801	if (pCurLeaf)
4802	{
4803	/* If advertised, the state component offset and size must match the one used by host. */
4804	if (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx)
4805	{
4806	CPUMCPUID RawHost;
4807	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0,
4808	&RawHost.uEax, &RawHost.uEbx, &RawHost.uEcx, &RawHost.uEdx);
4809	if ( RawHost.uEbx != pCurLeaf->uEbx
4810	\|\| RawHost.uEax != pCurLeaf->uEax)
4811	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4812	N_("CPUID(0xd/%#x).EBX/EAX=%#x/%#x, current host uses %#x/%#x (offset/size)"),
4813	uSubLeaf, pCurLeaf->uEbx, pCurLeaf->uEax, RawHost.uEbx, RawHost.uEax);
4814	}
4815	}
4816	}
4817	#endif
4818	}
4819	/* Clear leaf 0xd just in case we're loading an old state... */
4820	else if (pCurLeaf)
4821	{
4822	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
4823	{
4824	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), uSubLeaf);
4825	if (pCurLeaf)
4826	{
4827	AssertLogRelMsg( uVersion <= CPUM_SAVED_STATE_VERSION_PUT_STRUCT
4828	\|\| ( pCurLeaf->uEax == 0
4829	&& pCurLeaf->uEbx == 0
4830	&& pCurLeaf->uEcx == 0
4831	&& pCurLeaf->uEdx == 0),
4832	("uVersion=%#x; %#x %#x %#x %#x\n",
4833	uVersion, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx));
4834	pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
4835	}
4836	}
4837	}
4838
4839	/* Update the fXStateGuestMask value for the VM. */
4840	if (pVM->cpum.s.fXStateGuestMask != fGuestXcr0Mask)
4841	{
4842	LogRel(("CPUM: fXStateGuestMask=%#llx -> %#llx\n", pVM->cpum.s.fXStateGuestMask, fGuestXcr0Mask));
4843	pVM->cpum.s.fXStateGuestMask = fGuestXcr0Mask;
4844	if (!fGuestXcr0Mask && (aGuestCpuIdStd[1].uEcx & X86_CPUID_FEATURE_ECX_XSAVE))
4845	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS,
4846	N_("Internal Processing Error: XSAVE feature bit enabled, but leaf 0xd is empty."));
4847	}
4848
4849	#undef CPUID_CHECK_RET
4850	#undef CPUID_CHECK_WRN
4851	#undef CPUID_CHECK2_RET
4852	#undef CPUID_CHECK2_WRN
4853	#undef CPUID_RAW_FEATURE_RET
4854	#undef CPUID_RAW_FEATURE_WRN
4855	#undef CPUID_RAW_FEATURE_IGN
4856	#undef CPUID_GST_FEATURE_RET
4857	#undef CPUID_GST_FEATURE_WRN
4858	#undef CPUID_GST_FEATURE_EMU
4859	#undef CPUID_GST_FEATURE_IGN
4860	#undef CPUID_GST_FEATURE2_RET
4861	#undef CPUID_GST_FEATURE2_WRN
4862	#undef CPUID_GST_FEATURE2_EMU
4863	#undef CPUID_GST_FEATURE2_IGN
4864	#undef CPUID_GST_AMD_FEATURE_RET
4865	#undef CPUID_GST_AMD_FEATURE_WRN
4866	#undef CPUID_GST_AMD_FEATURE_EMU
4867	#undef CPUID_GST_AMD_FEATURE_IGN
4868
4869	/*
4870	* We're good, commit the CPU ID leaves.
4871	*/
4872	pVM->cpum.s.GuestInfo.DefCpuId = GuestDefCpuId;
4873	rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves, pMsrs);
4874	AssertLogRelRCReturn(rc, rc);
4875
4876	return VINF_SUCCESS;
4877	}
4878
4879
4880	/**
4881	* Loads the CPU ID leaves saved by pass 0.
4882	*
4883	* @returns VBox status code.
4884	* @param pVM The cross context VM structure.
4885	* @param pSSM The saved state handle.
4886	* @param uVersion The format version.
4887	* @param pMsrs The guest MSRs.
4888	*/
4889	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pMsrs)
4890	{
4891	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4892
4893	/*
4894	* Load the CPUID leaves array first and call worker to do the rest, just so
4895	* we can free the memory when we need to without ending up in column 1000.
4896	*/
4897	PCPUMCPUIDLEAF paLeaves;
4898	uint32_t cLeaves;
4899	int rc = cpumR3LoadGuestCpuIdArray(pVM, pSSM, uVersion, &paLeaves, &cLeaves);
4900	AssertRC(rc);
4901	if (RT_SUCCESS(rc))
4902	{
4903	rc = cpumR3LoadCpuIdInner(pVM, pSSM, uVersion, paLeaves, cLeaves, pMsrs);
4904	RTMemFree(paLeaves);
4905	}
4906	return rc;
4907	}
4908
4909
4910
4911	/**
4912	* Loads the CPU ID leaves saved by pass 0 in an pre 3.2 saved state.
4913	*
4914	* @returns VBox status code.
4915	* @param pVM The cross context VM structure.
4916	* @param pSSM The saved state handle.
4917	* @param uVersion The format version.
4918	*/
4919	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
4920	{
4921	AssertMsgReturn(uVersion < CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
4922
4923	/*
4924	* Restore the CPUID leaves.
4925	*
4926	* Note that we support restoring less than the current amount of standard
4927	* leaves because we've been allowed more is newer version of VBox.
4928	*/
4929	uint32_t cElements;
4930	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4931	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
4932	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4933	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
4934
4935	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4936	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
4937	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4938	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
4939
4940	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
4941	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
4942	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
4943	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
4944
4945	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
4946
4947	/*
4948	* Check that the basic cpuid id information is unchanged.
4949	*/
4950	/** @todo we should check the 64 bits capabilities too! */
4951	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
4952	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
4953	ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
4954	ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
4955	#endif
4956	uint32_t au32CpuIdSaved[8];
4957	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
4958	if (RT_SUCCESS(rc))
4959	{
4960	/* Ignore CPU stepping. */
4961	au32CpuId[4] &= 0xfffffff0;
4962	au32CpuIdSaved[4] &= 0xfffffff0;
4963
4964	/* Ignore APIC ID (AMD specs). */
4965	au32CpuId[5] &= ~0xff000000;
4966	au32CpuIdSaved[5] &= ~0xff000000;
4967
4968	/* Ignore the number of Logical CPUs (AMD specs). */
4969	au32CpuId[5] &= ~0x00ff0000;
4970	au32CpuIdSaved[5] &= ~0x00ff0000;
4971
4972	/* Ignore some advanced capability bits, that we don't expose to the guest. */
4973	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4974	\| X86_CPUID_FEATURE_ECX_VMX
4975	\| X86_CPUID_FEATURE_ECX_SMX
4976	\| X86_CPUID_FEATURE_ECX_EST
4977	\| X86_CPUID_FEATURE_ECX_TM2
4978	\| X86_CPUID_FEATURE_ECX_CNTXID
4979	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4980	\| X86_CPUID_FEATURE_ECX_PDCM
4981	\| X86_CPUID_FEATURE_ECX_DCA
4982	\| X86_CPUID_FEATURE_ECX_X2APIC
4983	);
4984	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
4985	\| X86_CPUID_FEATURE_ECX_VMX
4986	\| X86_CPUID_FEATURE_ECX_SMX
4987	\| X86_CPUID_FEATURE_ECX_EST
4988	\| X86_CPUID_FEATURE_ECX_TM2
4989	\| X86_CPUID_FEATURE_ECX_CNTXID
4990	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
4991	\| X86_CPUID_FEATURE_ECX_PDCM
4992	\| X86_CPUID_FEATURE_ECX_DCA
4993	\| X86_CPUID_FEATURE_ECX_X2APIC
4994	);
4995
4996	/* Make sure we don't forget to update the masks when enabling
4997	* features in the future.
4998	*/
4999	AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
5000	( X86_CPUID_FEATURE_ECX_DTES64
5001	\| X86_CPUID_FEATURE_ECX_VMX
5002	\| X86_CPUID_FEATURE_ECX_SMX
5003	\| X86_CPUID_FEATURE_ECX_EST
5004	\| X86_CPUID_FEATURE_ECX_TM2
5005	\| X86_CPUID_FEATURE_ECX_CNTXID
5006	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
5007	\| X86_CPUID_FEATURE_ECX_PDCM
5008	\| X86_CPUID_FEATURE_ECX_DCA
5009	\| X86_CPUID_FEATURE_ECX_X2APIC
5010	)));
5011	/* do the compare */
5012	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
5013	{
5014	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
5015	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
5016	"Saved=%.*Rhxs\n"
5017	"Real =%.*Rhxs\n",
5018	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5019	sizeof(au32CpuId), au32CpuId));
5020	else
5021	{
5022	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
5023	"Saved=%.*Rhxs\n"
5024	"Real =%.*Rhxs\n",
5025	sizeof(au32CpuIdSaved), au32CpuIdSaved,
5026	sizeof(au32CpuId), au32CpuId));
5027	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
5028	}
5029	}
5030	}
5031
5032	return rc;
5033	}
5034
5035
5036
5037	/*
5038	*
5039	*
5040	* CPUID Info Handler.
5041	* CPUID Info Handler.
5042	* CPUID Info Handler.
5043	*
5044	*
5045	*/
5046
5047
5048
5049	/**
5050	* Get L1 cache / TLS associativity.
5051	*/
5052	static const char getCacheAss(unsigned u, char pszBuf)
5053	{
5054	if (u == 0)
5055	return "res0 ";
5056	if (u == 1)
5057	return "direct";
5058	if (u == 255)
5059	return "fully";
5060	if (u >= 256)
5061	return "???";
5062
5063	RTStrPrintf(pszBuf, 16, "%d way", u);
5064	return pszBuf;
5065	}
5066
5067
5068	/**
5069	* Get L2/L3 cache associativity.
5070	*/
5071	static const char *getL23CacheAss(unsigned u)
5072	{
5073	switch (u)
5074	{
5075	case 0: return "off ";
5076	case 1: return "direct";
5077	case 2: return "2 way ";
5078	case 3: return "3 way ";
5079	case 4: return "4 way ";
5080	case 5: return "6 way ";
5081	case 6: return "8 way ";
5082	case 7: return "res7 ";
5083	case 8: return "16 way";
5084	case 9: return "tpoext"; /* Overridden by Fn8000_001D */
5085	case 10: return "32 way";
5086	case 11: return "48 way";
5087	case 12: return "64 way";
5088	case 13: return "96 way";
5089	case 14: return "128way";
5090	case 15: return "fully ";
5091	default: return "????";
5092	}
5093	}
5094
5095
5096	/** CPUID(1).EDX field descriptions. */
5097	static DBGFREGSUBFIELD const g_aLeaf1EdxSubFields[] =
5098	{
5099	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5100	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5101	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5102	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5103	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5104	DBGFREGSUBFIELD_RO("MSR\0" "Model Specific Registers", 5, 1, 0),
5105	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5106	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5107	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5108	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5109	DBGFREGSUBFIELD_RO("SEP\0" "SYSENTER and SYSEXIT Present", 11, 1, 0),
5110	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5111	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5112	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5113	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5114	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5115	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5116	DBGFREGSUBFIELD_RO("PSN\0" "Processor Serial Number", 18, 1, 0),
5117	DBGFREGSUBFIELD_RO("CLFSH\0" "CLFLUSH instruction", 19, 1, 0),
5118	DBGFREGSUBFIELD_RO("DS\0" "Debug Store", 21, 1, 0),
5119	DBGFREGSUBFIELD_RO("ACPI\0" "Thermal Mon. & Soft. Clock Ctrl.", 22, 1, 0),
5120	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5121	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR instructions", 24, 1, 0),
5122	DBGFREGSUBFIELD_RO("SSE\0" "SSE support", 25, 1, 0),
5123	DBGFREGSUBFIELD_RO("SSE2\0" "SSE2 support", 26, 1, 0),
5124	DBGFREGSUBFIELD_RO("SS\0" "Self Snoop", 27, 1, 0),
5125	DBGFREGSUBFIELD_RO("HTT\0" "Hyper-Threading Technology", 28, 1, 0),
5126	DBGFREGSUBFIELD_RO("TM\0" "Therm. Monitor", 29, 1, 0),
5127	DBGFREGSUBFIELD_RO("PBE\0" "Pending Break Enabled", 31, 1, 0),
5128	DBGFREGSUBFIELD_TERMINATOR()
5129	};
5130
5131	/** CPUID(1).ECX field descriptions. */
5132	static DBGFREGSUBFIELD const g_aLeaf1EcxSubFields[] =
5133	{
5134	DBGFREGSUBFIELD_RO("SSE3\0" "SSE3 support", 0, 1, 0),
5135	DBGFREGSUBFIELD_RO("PCLMUL\0" "PCLMULQDQ support (for AES-GCM)", 1, 1, 0),
5136	DBGFREGSUBFIELD_RO("DTES64\0" "DS Area 64-bit Layout", 2, 1, 0),
5137	DBGFREGSUBFIELD_RO("MONITOR\0" "MONITOR/MWAIT instructions", 3, 1, 0),
5138	DBGFREGSUBFIELD_RO("CPL-DS\0" "CPL Qualified Debug Store", 4, 1, 0),
5139	DBGFREGSUBFIELD_RO("VMX\0" "Virtual Machine Extensions", 5, 1, 0),
5140	DBGFREGSUBFIELD_RO("SMX\0" "Safer Mode Extensions", 6, 1, 0),
5141	DBGFREGSUBFIELD_RO("EST\0" "Enhanced SpeedStep Technology", 7, 1, 0),
5142	DBGFREGSUBFIELD_RO("TM2\0" "Terminal Monitor 2", 8, 1, 0),
5143	DBGFREGSUBFIELD_RO("SSSE3\0" "Supplemental Streaming SIMD Extensions 3", 9, 1, 0),
5144	DBGFREGSUBFIELD_RO("CNTX-ID\0" "L1 Context ID", 10, 1, 0),
5145	DBGFREGSUBFIELD_RO("SDBG\0" "Silicon Debug interface", 11, 1, 0),
5146	DBGFREGSUBFIELD_RO("FMA\0" "Fused Multiply Add extensions", 12, 1, 0),
5147	DBGFREGSUBFIELD_RO("CX16\0" "CMPXCHG16B instruction", 13, 1, 0),
5148	DBGFREGSUBFIELD_RO("TPRUPDATE\0" "xTPR Update Control", 14, 1, 0),
5149	DBGFREGSUBFIELD_RO("PDCM\0" "Perf/Debug Capability MSR", 15, 1, 0),
5150	DBGFREGSUBFIELD_RO("PCID\0" "Process Context Identifiers", 17, 1, 0),
5151	DBGFREGSUBFIELD_RO("DCA\0" "Direct Cache Access", 18, 1, 0),
5152	DBGFREGSUBFIELD_RO("SSE4_1\0" "SSE4_1 support", 19, 1, 0),
5153	DBGFREGSUBFIELD_RO("SSE4_2\0" "SSE4_2 support", 20, 1, 0),
5154	DBGFREGSUBFIELD_RO("X2APIC\0" "x2APIC support", 21, 1, 0),
5155	DBGFREGSUBFIELD_RO("MOVBE\0" "MOVBE instruction", 22, 1, 0),
5156	DBGFREGSUBFIELD_RO("POPCNT\0" "POPCNT instruction", 23, 1, 0),
5157	DBGFREGSUBFIELD_RO("TSCDEADL\0" "Time Stamp Counter Deadline", 24, 1, 0),
5158	DBGFREGSUBFIELD_RO("AES\0" "AES instructions", 25, 1, 0),
5159	DBGFREGSUBFIELD_RO("XSAVE\0" "XSAVE instruction", 26, 1, 0),
5160	DBGFREGSUBFIELD_RO("OSXSAVE\0" "OSXSAVE instruction", 27, 1, 0),
5161	DBGFREGSUBFIELD_RO("AVX\0" "AVX support", 28, 1, 0),
5162	DBGFREGSUBFIELD_RO("F16C\0" "16-bit floating point conversion instructions", 29, 1, 0),
5163	DBGFREGSUBFIELD_RO("RDRAND\0" "RDRAND instruction", 30, 1, 0),
5164	DBGFREGSUBFIELD_RO("HVP\0" "Hypervisor Present (we're a guest)", 31, 1, 0),
5165	DBGFREGSUBFIELD_TERMINATOR()
5166	};
5167
5168	/** CPUID(7,0).EBX field descriptions. */
5169	static DBGFREGSUBFIELD const g_aLeaf7Sub0EbxSubFields[] =
5170	{
5171	DBGFREGSUBFIELD_RO("FSGSBASE\0" "RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instr.", 0, 1, 0),
5172	DBGFREGSUBFIELD_RO("TSCADJUST\0" "Supports MSR_IA32_TSC_ADJUST", 1, 1, 0),
5173	DBGFREGSUBFIELD_RO("SGX\0" "Supports Software Guard Extensions", 2, 1, 0),
5174	DBGFREGSUBFIELD_RO("BMI1\0" "Advanced Bit Manipulation extension 1", 3, 1, 0),
5175	DBGFREGSUBFIELD_RO("HLE\0" "Hardware Lock Elision", 4, 1, 0),
5176	DBGFREGSUBFIELD_RO("AVX2\0" "Advanced Vector Extensions 2", 5, 1, 0),
5177	DBGFREGSUBFIELD_RO("FDP_EXCPTN_ONLY\0" "FPU DP only updated on exceptions", 6, 1, 0),
5178	DBGFREGSUBFIELD_RO("SMEP\0" "Supervisor Mode Execution Prevention", 7, 1, 0),
5179	DBGFREGSUBFIELD_RO("BMI2\0" "Advanced Bit Manipulation extension 2", 8, 1, 0),
5180	DBGFREGSUBFIELD_RO("ERMS\0" "Enhanced REP MOVSB/STOSB instructions", 9, 1, 0),
5181	DBGFREGSUBFIELD_RO("INVPCID\0" "INVPCID instruction", 10, 1, 0),
5182	DBGFREGSUBFIELD_RO("RTM\0" "Restricted Transactional Memory", 11, 1, 0),
5183	DBGFREGSUBFIELD_RO("PQM\0" "Platform Quality of Service Monitoring", 12, 1, 0),
5184	DBGFREGSUBFIELD_RO("DEPFPU_CS_DS\0" "Deprecates FPU CS, FPU DS values if set", 13, 1, 0),
5185	DBGFREGSUBFIELD_RO("MPE\0" "Intel Memory Protection Extensions", 14, 1, 0),
5186	DBGFREGSUBFIELD_RO("PQE\0" "Platform Quality of Service Enforcement", 15, 1, 0),
5187	DBGFREGSUBFIELD_RO("AVX512F\0" "AVX512 Foundation instructions", 16, 1, 0),
5188	DBGFREGSUBFIELD_RO("RDSEED\0" "RDSEED instruction", 18, 1, 0),
5189	DBGFREGSUBFIELD_RO("ADX\0" "ADCX/ADOX instructions", 19, 1, 0),
5190	DBGFREGSUBFIELD_RO("SMAP\0" "Supervisor Mode Access Prevention", 20, 1, 0),
5191	DBGFREGSUBFIELD_RO("CLFLUSHOPT\0" "CLFLUSHOPT (Cache Line Flush) instruction", 23, 1, 0),
5192	DBGFREGSUBFIELD_RO("CLWB\0" "CLWB instruction", 24, 1, 0),
5193	DBGFREGSUBFIELD_RO("INTEL_PT\0" "Intel Processor Trace", 25, 1, 0),
5194	DBGFREGSUBFIELD_RO("AVX512PF\0" "AVX512 Prefetch instructions", 26, 1, 0),
5195	DBGFREGSUBFIELD_RO("AVX512ER\0" "AVX512 Exponential & Reciprocal instructions", 27, 1, 0),
5196	DBGFREGSUBFIELD_RO("AVX512CD\0" "AVX512 Conflict Detection instructions", 28, 1, 0),
5197	DBGFREGSUBFIELD_RO("SHA\0" "Secure Hash Algorithm extensions", 29, 1, 0),
5198	DBGFREGSUBFIELD_TERMINATOR()
5199	};
5200
5201	/** CPUID(7,0).ECX field descriptions. */
5202	static DBGFREGSUBFIELD const g_aLeaf7Sub0EcxSubFields[] =
5203	{
5204	DBGFREGSUBFIELD_RO("PREFETCHWT1\0" "PREFETCHWT1 instruction", 0, 1, 0),
5205	DBGFREGSUBFIELD_RO("UMIP\0" "User mode insturction prevention", 2, 1, 0),
5206	DBGFREGSUBFIELD_RO("PKU\0" "Protection Key for Usermode pages", 3, 1, 0),
5207	DBGFREGSUBFIELD_RO("OSPKE\0" "CR4.PKU mirror", 4, 1, 0),
5208	DBGFREGSUBFIELD_RO("MAWAU\0" "Value used by BNDLDX & BNDSTX", 17, 5, 0),
5209	DBGFREGSUBFIELD_RO("RDPID\0" "Read processor ID support", 22, 1, 0),
5210	DBGFREGSUBFIELD_RO("SGX_LC\0" "Supports SGX Launch Configuration", 30, 1, 0),
5211	DBGFREGSUBFIELD_TERMINATOR()
5212	};
5213
5214	/** CPUID(7,0).EDX field descriptions. */
5215	static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
5216	{
5217	DBGFREGSUBFIELD_RO("MD_CLEAR\0" "Supports MDS related buffer clearing", 10, 1, 0),
5218	DBGFREGSUBFIELD_RO("IBRS_IBPB\0" "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB", 26, 1, 0),
5219	DBGFREGSUBFIELD_RO("STIBP\0" "Supports IA32_SPEC_CTRL.STIBP", 27, 1, 0),
5220	DBGFREGSUBFIELD_RO("FLUSH_CMD\0" "Supports IA32_FLUSH_CMD", 28, 1, 0),
5221	DBGFREGSUBFIELD_RO("ARCHCAP\0" "Supports IA32_ARCH_CAP", 29, 1, 0),
5222	DBGFREGSUBFIELD_RO("CORECAP\0" "Supports IA32_CORE_CAP", 30, 1, 0),
5223	DBGFREGSUBFIELD_RO("SSBD\0" "Supports IA32_SPEC_CTRL.SSBD", 31, 1, 0),
5224	DBGFREGSUBFIELD_TERMINATOR()
5225	};
5226
5227
5228	/** CPUID(13,0).EAX+EDX, XCR0, ++ bit descriptions. */
5229	static DBGFREGSUBFIELD const g_aXSaveStateBits[] =
5230	{
5231	DBGFREGSUBFIELD_RO("x87\0" "Legacy FPU state", 0, 1, 0),
5232	DBGFREGSUBFIELD_RO("SSE\0" "128-bit SSE state", 1, 1, 0),
5233	DBGFREGSUBFIELD_RO("YMM_Hi128\0" "Upper 128 bits of YMM0-15 (AVX)", 2, 1, 0),
5234	DBGFREGSUBFIELD_RO("BNDREGS\0" "MPX bound register state", 3, 1, 0),
5235	DBGFREGSUBFIELD_RO("BNDCSR\0" "MPX bound config and status state", 4, 1, 0),
5236	DBGFREGSUBFIELD_RO("Opmask\0" "opmask state", 5, 1, 0),
5237	DBGFREGSUBFIELD_RO("ZMM_Hi256\0" "Upper 256 bits of ZMM0-15 (AVX-512)", 6, 1, 0),
5238	DBGFREGSUBFIELD_RO("Hi16_ZMM\0" "512-bits ZMM16-31 state (AVX-512)", 7, 1, 0),
5239	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling (AMD)", 62, 1, 0),
5240	DBGFREGSUBFIELD_TERMINATOR()
5241	};
5242
5243	/** CPUID(13,1).EAX field descriptions. */
5244	static DBGFREGSUBFIELD const g_aLeaf13Sub1EaxSubFields[] =
5245	{
5246	DBGFREGSUBFIELD_RO("XSAVEOPT\0" "XSAVEOPT is available", 0, 1, 0),
5247	DBGFREGSUBFIELD_RO("XSAVEC\0" "XSAVEC and compacted XRSTOR supported", 1, 1, 0),
5248	DBGFREGSUBFIELD_RO("XGETBC1\0" "XGETBV with ECX=1 supported", 2, 1, 0),
5249	DBGFREGSUBFIELD_RO("XSAVES\0" "XSAVES/XRSTORS and IA32_XSS supported", 3, 1, 0),
5250	DBGFREGSUBFIELD_TERMINATOR()
5251	};
5252
5253
5254	/** CPUID(0x80000001,0).EDX field descriptions. */
5255	static DBGFREGSUBFIELD const g_aExtLeaf1EdxSubFields[] =
5256	{
5257	DBGFREGSUBFIELD_RO("FPU\0" "x87 FPU on Chip", 0, 1, 0),
5258	DBGFREGSUBFIELD_RO("VME\0" "Virtual 8086 Mode Enhancements", 1, 1, 0),
5259	DBGFREGSUBFIELD_RO("DE\0" "Debugging extensions", 2, 1, 0),
5260	DBGFREGSUBFIELD_RO("PSE\0" "Page Size Extension", 3, 1, 0),
5261	DBGFREGSUBFIELD_RO("TSC\0" "Time Stamp Counter", 4, 1, 0),
5262	DBGFREGSUBFIELD_RO("MSR\0" "K86 Model Specific Registers", 5, 1, 0),
5263	DBGFREGSUBFIELD_RO("PAE\0" "Physical Address Extension", 6, 1, 0),
5264	DBGFREGSUBFIELD_RO("MCE\0" "Machine Check Exception", 7, 1, 0),
5265	DBGFREGSUBFIELD_RO("CX8\0" "CMPXCHG8B instruction", 8, 1, 0),
5266	DBGFREGSUBFIELD_RO("APIC\0" "APIC On-Chip", 9, 1, 0),
5267	DBGFREGSUBFIELD_RO("SEP\0" "SYSCALL/SYSRET", 11, 1, 0),
5268	DBGFREGSUBFIELD_RO("MTRR\0" "Memory Type Range Registers", 12, 1, 0),
5269	DBGFREGSUBFIELD_RO("PGE\0" "PTE Global Bit", 13, 1, 0),
5270	DBGFREGSUBFIELD_RO("MCA\0" "Machine Check Architecture", 14, 1, 0),
5271	DBGFREGSUBFIELD_RO("CMOV\0" "Conditional Move instructions", 15, 1, 0),
5272	DBGFREGSUBFIELD_RO("PAT\0" "Page Attribute Table", 16, 1, 0),
5273	DBGFREGSUBFIELD_RO("PSE-36\0" "36-bit Page Size Extension", 17, 1, 0),
5274	DBGFREGSUBFIELD_RO("NX\0" "No-Execute/Execute-Disable", 20, 1, 0),
5275	DBGFREGSUBFIELD_RO("AXMMX\0" "AMD Extensions to MMX instructions", 22, 1, 0),
5276	DBGFREGSUBFIELD_RO("MMX\0" "Intel MMX Technology", 23, 1, 0),
5277	DBGFREGSUBFIELD_RO("FXSR\0" "FXSAVE and FXRSTOR Instructions", 24, 1, 0),
5278	DBGFREGSUBFIELD_RO("FFXSR\0" "AMD fast FXSAVE and FXRSTOR instructions", 25, 1, 0),
5279	DBGFREGSUBFIELD_RO("Page1GB\0" "1 GB large page", 26, 1, 0),
5280	DBGFREGSUBFIELD_RO("RDTSCP\0" "RDTSCP instruction", 27, 1, 0),
5281	DBGFREGSUBFIELD_RO("LM\0" "AMD64 Long Mode", 29, 1, 0),
5282	DBGFREGSUBFIELD_RO("3DNOWEXT\0" "AMD Extensions to 3DNow", 30, 1, 0),
5283	DBGFREGSUBFIELD_RO("3DNOW\0" "AMD 3DNow", 31, 1, 0),
5284	DBGFREGSUBFIELD_TERMINATOR()
5285	};
5286
5287	/** CPUID(0x80000001,0).ECX field descriptions. */
5288	static DBGFREGSUBFIELD const g_aExtLeaf1EcxSubFields[] =
5289	{
5290	DBGFREGSUBFIELD_RO("LahfSahf\0" "LAHF/SAHF support in 64-bit mode", 0, 1, 0),
5291	DBGFREGSUBFIELD_RO("CmpLegacy\0" "Core multi-processing legacy mode", 1, 1, 0),
5292	DBGFREGSUBFIELD_RO("SVM\0" "AMD Secure Virtual Machine extensions", 2, 1, 0),
5293	DBGFREGSUBFIELD_RO("EXTAPIC\0" "AMD Extended APIC registers", 3, 1, 0),
5294	DBGFREGSUBFIELD_RO("CR8L\0" "AMD LOCK MOV CR0 means MOV CR8", 4, 1, 0),
5295	DBGFREGSUBFIELD_RO("ABM\0" "AMD Advanced Bit Manipulation", 5, 1, 0),
5296	DBGFREGSUBFIELD_RO("SSE4A\0" "SSE4A instructions", 6, 1, 0),
5297	DBGFREGSUBFIELD_RO("MISALIGNSSE\0" "AMD Misaligned SSE mode", 7, 1, 0),
5298	DBGFREGSUBFIELD_RO("3DNOWPRF\0" "AMD PREFETCH and PREFETCHW instructions", 8, 1, 0),
5299	DBGFREGSUBFIELD_RO("OSVW\0" "AMD OS Visible Workaround", 9, 1, 0),
5300	DBGFREGSUBFIELD_RO("IBS\0" "Instruct Based Sampling", 10, 1, 0),
5301	DBGFREGSUBFIELD_RO("XOP\0" "Extended Operation support", 11, 1, 0),
5302	DBGFREGSUBFIELD_RO("SKINIT\0" "SKINIT, STGI, and DEV support", 12, 1, 0),
5303	DBGFREGSUBFIELD_RO("WDT\0" "AMD Watchdog Timer support", 13, 1, 0),
5304	DBGFREGSUBFIELD_RO("LWP\0" "Lightweight Profiling support", 15, 1, 0),
5305	DBGFREGSUBFIELD_RO("FMA4\0" "Four operand FMA instruction support", 16, 1, 0),
5306	DBGFREGSUBFIELD_RO("TCE\0" "Translation Cache Extension support", 17, 1, 0),
5307	DBGFREGSUBFIELD_RO("NodeId\0" "NodeId in MSR C001_100C", 19, 1, 0),
5308	DBGFREGSUBFIELD_RO("TBM\0" "Trailing Bit Manipulation instructions", 21, 1, 0),
5309	DBGFREGSUBFIELD_RO("TOPOEXT\0" "Topology Extensions", 22, 1, 0),
5310	DBGFREGSUBFIELD_RO("PRFEXTCORE\0" "Performance Counter Extensions support", 23, 1, 0),
5311	DBGFREGSUBFIELD_RO("PRFEXTNB\0" "NB Performance Counter Extensions support", 24, 1, 0),
5312	DBGFREGSUBFIELD_RO("DATABPEXT\0" "Data-access Breakpoint Extension", 26, 1, 0),
5313	DBGFREGSUBFIELD_RO("PERFTSC\0" "Performance Time Stamp Counter", 27, 1, 0),
5314	DBGFREGSUBFIELD_RO("PCX_L2I\0" "L2I/L3 Performance Counter Extensions", 28, 1, 0),
5315	DBGFREGSUBFIELD_RO("MONITORX\0" "MWAITX and MONITORX instructions", 29, 1, 0),
5316	DBGFREGSUBFIELD_RO("AddrMaskExt\0" "BP Addressing masking extended to bit 31", 30, 1, 0),
5317	DBGFREGSUBFIELD_TERMINATOR()
5318	};
5319
5320	/** CPUID(0x8000000a,0).EDX field descriptions. */
5321	static DBGFREGSUBFIELD const g_aExtLeafAEdxSubFields[] =
5322	{
5323	DBGFREGSUBFIELD_RO("NP\0" "Nested Paging", 0, 1, 0),
5324	DBGFREGSUBFIELD_RO("LbrVirt\0" "Last Branch Record Virtualization", 1, 1, 0),
5325	DBGFREGSUBFIELD_RO("SVML\0" "SVM Lock", 2, 1, 0),
5326	DBGFREGSUBFIELD_RO("NRIPS\0" "NextRIP Save", 3, 1, 0),
5327	DBGFREGSUBFIELD_RO("TscRateMsr\0" "MSR based TSC rate control", 4, 1, 0),
5328	DBGFREGSUBFIELD_RO("VmcbClean\0" "VMCB clean bits", 5, 1, 0),
5329	DBGFREGSUBFIELD_RO("FlushByASID\0" "Flush by ASID", 6, 1, 0),
5330	DBGFREGSUBFIELD_RO("DecodeAssists\0" "Decode Assists", 7, 1, 0),
5331	DBGFREGSUBFIELD_RO("PauseFilter\0" "Pause intercept filter", 10, 1, 0),
5332	DBGFREGSUBFIELD_RO("PauseFilterThreshold\0" "Pause filter threshold", 12, 1, 0),
5333	DBGFREGSUBFIELD_RO("AVIC\0" "Advanced Virtual Interrupt Controller", 13, 1, 0),
5334	DBGFREGSUBFIELD_RO("VMSAVEVirt\0" "VMSAVE and VMLOAD Virtualization", 15, 1, 0),
5335	DBGFREGSUBFIELD_RO("VGIF\0" "Virtual Global-Interrupt Flag", 16, 1, 0),
5336	DBGFREGSUBFIELD_RO("GMET\0" "Guest Mode Execute Trap Extension", 17, 1, 0),
5337	DBGFREGSUBFIELD_RO("x2AVIC\0" "AVIC support for x2APIC mode", 18, 1, 0),
5338	DBGFREGSUBFIELD_RO("SSSCheck\0" "SVM supervisor shadow stack restrictions", 19, 1, 0),
5339	DBGFREGSUBFIELD_RO("SpecCtrl\0" "SPEC_CTRL virtualization", 20, 1, 0),
5340	DBGFREGSUBFIELD_RO("ROGPT\0" "Read-Only Guest Page Table feature support", 21, 1, 0),
5341	DBGFREGSUBFIELD_RO("HOST_MCE_OVERRIDE\0" "Guest #MC can be intercepted", 23, 1, 0),
5342	DBGFREGSUBFIELD_RO("TlbiCtl\0" "INVLPGB/TLBSYNC enable and intercept", 24, 1, 0),
5343	DBGFREGSUBFIELD_RO("VNMI\0" "NMI Virtualization", 25, 1, 0),
5344	DBGFREGSUBFIELD_RO("IbsVirt\0" "IBS Virtualization", 26, 1, 0),
5345	DBGFREGSUBFIELD_RO("ExtLvtAvicAccessChg\0" "Extended LVT AVIC access changes", 27, 1, 0),
5346	DBGFREGSUBFIELD_RO("NestedVirtVmcbAddrChk\0""Guest VMCB address check", 28, 1, 0),
5347	DBGFREGSUBFIELD_RO("BusLockThreshold\0" "Bus Lock Threshold", 29, 1, 0),
5348	DBGFREGSUBFIELD_TERMINATOR()
5349	};
5350
5351
5352	/** CPUID(0x80000007,0).EDX field descriptions. */
5353	static DBGFREGSUBFIELD const g_aExtLeaf7EdxSubFields[] =
5354	{
5355	DBGFREGSUBFIELD_RO("TS\0" "Temperature Sensor", 0, 1, 0),
5356	DBGFREGSUBFIELD_RO("FID\0" "Frequency ID control", 1, 1, 0),
5357	DBGFREGSUBFIELD_RO("VID\0" "Voltage ID control", 2, 1, 0),
5358	DBGFREGSUBFIELD_RO("TTP\0" "Thermal Trip", 3, 1, 0),
5359	DBGFREGSUBFIELD_RO("TM\0" "Hardware Thermal Control (HTC)", 4, 1, 0),
5360	DBGFREGSUBFIELD_RO("100MHzSteps\0" "100 MHz Multiplier control", 6, 1, 0),
5361	DBGFREGSUBFIELD_RO("HwPstate\0" "Hardware P-state control", 7, 1, 0),
5362	DBGFREGSUBFIELD_RO("TscInvariant\0" "Invariant Time Stamp Counter", 8, 1, 0),
5363	DBGFREGSUBFIELD_RO("CPB\0" "Core Performance Boost", 9, 1, 0),
5364	DBGFREGSUBFIELD_RO("EffFreqRO\0" "Read-only Effective Frequency Interface", 10, 1, 0),
5365	DBGFREGSUBFIELD_RO("ProcFdbkIf\0" "Processor Feedback Interface", 11, 1, 0),
5366	DBGFREGSUBFIELD_RO("ProcPwrRep\0" "Core power reporting interface support", 12, 1, 0),
5367	DBGFREGSUBFIELD_RO("ConnectedStandby\0" "Connected Standby", 13, 1, 0),
5368	DBGFREGSUBFIELD_RO("RAPL\0" "Running average power limit", 14, 1, 0),
5369	DBGFREGSUBFIELD_TERMINATOR()
5370	};
5371
5372	/** CPUID(0x80000008,0).EBX field descriptions. */
5373	static DBGFREGSUBFIELD const g_aExtLeaf8EbxSubFields[] =
5374	{
5375	DBGFREGSUBFIELD_RO("CLZERO\0" "Clear zero instruction (cacheline)", 0, 1, 0),
5376	DBGFREGSUBFIELD_RO("IRPerf\0" "Instructions retired count support", 1, 1, 0),
5377	DBGFREGSUBFIELD_RO("XSaveErPtr\0" "Save/restore error pointers (FXSAVE/RSTOR)", 2, 1, 0),
5378	DBGFREGSUBFIELD_RO("INVLPGB\0" "INVLPGB and TLBSYNC instructions", 3, 1, 0),
5379	DBGFREGSUBFIELD_RO("RDPRU\0" "RDPRU instruction", 4, 1, 0),
5380	DBGFREGSUBFIELD_RO("BE\0" "Bandwidth Enforcement extension", 6, 1, 0),
5381	DBGFREGSUBFIELD_RO("MCOMMIT\0" "MCOMMIT instruction", 8, 1, 0),
5382	DBGFREGSUBFIELD_RO("WBNOINVD\0" "WBNOINVD instruction", 9, 1, 0),
5383	DBGFREGSUBFIELD_RO("IBPB\0" "Supports the IBPB command in IA32_PRED_CMD", 12, 1, 0),
5384	DBGFREGSUBFIELD_RO("INT_WBINVD\0" "WBINVD/WBNOINVD interruptible", 13, 1, 0),
5385	DBGFREGSUBFIELD_RO("IBRS\0" "Indirect Branch Restricted Speculation", 14, 1, 0),
5386	DBGFREGSUBFIELD_RO("STIBP\0" "Single Thread Indirect Branch Prediction", 15, 1, 0),
5387	DBGFREGSUBFIELD_RO("IbrsAlwaysOn\0" "Processor prefers that IBRS be left on", 16, 1, 0),
5388	DBGFREGSUBFIELD_RO("StibpAlwaysOn\0""Processor prefers that STIBP be left on", 17, 1, 0),
5389	DBGFREGSUBFIELD_RO("IbrsPreferred\0""IBRS preferred over software solution", 18, 1, 0),
5390	DBGFREGSUBFIELD_RO("IbrsSameMode\0" "IBRS limits same mode speculation", 19, 1, 0),
5391	DBGFREGSUBFIELD_RO("EferLmsleUnsupported\0" "EFER.LMSLE is unsupported", 20, 1, 0),
5392	DBGFREGSUBFIELD_RO("INVLPGBnestedPages\0" "INVLPGB for nested translation", 21, 1, 0),
5393	DBGFREGSUBFIELD_RO("SSBD\0" "Speculative Store Bypass Disable", 24, 1, 0),
5394	DBGFREGSUBFIELD_RO("SsbdVirtSpecCtrl\0" "Use VIRT_SPEC_CTL for SSBD", 25, 1, 0),
5395	DBGFREGSUBFIELD_RO("SsbdNotRequired\0" "SSBD not needed on this processor", 26, 1, 0),
5396	DBGFREGSUBFIELD_RO("CPPC\0" "Collaborative Processor Performance Control", 27, 1, 0),
5397	DBGFREGSUBFIELD_RO("PSFD\0" "Predictive Store Forward Disable", 28, 1, 0),
5398	DBGFREGSUBFIELD_RO("BTC_NO\0" "Unaffected by branch type confusion", 29, 1, 0),
5399	DBGFREGSUBFIELD_RO("IBPB_RET\0" "Clears RA predictor when PRED_CMD.IBPB set", 30, 1, 0),
5400	DBGFREGSUBFIELD_TERMINATOR()
5401	};
5402
5403
5404	static void cpumR3CpuIdInfoMnemonicListU32(PCDBGFINFOHLP pHlp, uint32_t uVal, PCDBGFREGSUBFIELD pDesc,
5405	const char *pszLeadIn, uint32_t cchWidth)
5406	{
5407	if (pszLeadIn)
5408	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5409
5410	for (uint32_t iBit = 0; iBit < 32; iBit++)
5411	if (RT_BIT_32(iBit) & uVal)
5412	{
5413	while ( pDesc->pszName != NULL
5414	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5415	pDesc++;
5416	if ( pDesc->pszName != NULL
5417	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5418	{
5419	if (pDesc->cBits == 1)
5420	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5421	else
5422	{
5423	uint32_t uFieldValue = uVal >> pDesc->iFirstBit;
5424	if (pDesc->cBits < 32)
5425	uFieldValue &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5426	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%u" : " %s=%#x", pDesc->pszName, uFieldValue);
5427	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5428	}
5429	}
5430	else
5431	pHlp->pfnPrintf(pHlp, " %u", iBit);
5432	}
5433	if (pszLeadIn)
5434	pHlp->pfnPrintf(pHlp, "\n");
5435	}
5436
5437
5438	static void cpumR3CpuIdInfoMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5439	const char *pszLeadIn, uint32_t cchWidth)
5440	{
5441	if (pszLeadIn)
5442	pHlp->pfnPrintf(pHlp, "%*s", cchWidth, pszLeadIn);
5443
5444	for (uint32_t iBit = 0; iBit < 64; iBit++)
5445	if (RT_BIT_64(iBit) & uVal)
5446	{
5447	while ( pDesc->pszName != NULL
5448	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5449	pDesc++;
5450	if ( pDesc->pszName != NULL
5451	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5452	{
5453	if (pDesc->cBits == 1)
5454	pHlp->pfnPrintf(pHlp, " %s", pDesc->pszName);
5455	else
5456	{
5457	uint64_t uFieldValue = uVal >> pDesc->iFirstBit;
5458	if (pDesc->cBits < 64)
5459	uFieldValue &= RT_BIT_64(pDesc->cBits) - UINT64_C(1);
5460	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s=%llu" : " %s=%#llx", pDesc->pszName, uFieldValue);
5461	iBit = pDesc->iFirstBit + pDesc->cBits - 1;
5462	}
5463	}
5464	else
5465	pHlp->pfnPrintf(pHlp, " %u", iBit);
5466	}
5467	if (pszLeadIn)
5468	pHlp->pfnPrintf(pHlp, "\n");
5469	}
5470
5471
5472	static void cpumR3CpuIdInfoValueWithMnemonicListU64(PCDBGFINFOHLP pHlp, uint64_t uVal, PCDBGFREGSUBFIELD pDesc,
5473	const char *pszLeadIn, uint32_t cchWidth)
5474	{
5475	if (!uVal)
5476	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x\n", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5477	else
5478	{
5479	pHlp->pfnPrintf(pHlp, "%*s %#010x`%08x (", cchWidth, pszLeadIn, RT_HI_U32(uVal), RT_LO_U32(uVal));
5480	cpumR3CpuIdInfoMnemonicListU64(pHlp, uVal, pDesc, NULL, 0);
5481	pHlp->pfnPrintf(pHlp, " )\n");
5482	}
5483	}
5484
5485
5486	static void cpumR3CpuIdInfoVerboseCompareListU32(PCDBGFINFOHLP pHlp, uint32_t uVal1, uint32_t uVal2, PCDBGFREGSUBFIELD pDesc,
5487	uint32_t cchWidth)
5488	{
5489	uint32_t uCombined = uVal1 \| uVal2;
5490	for (uint32_t iBit = 0; iBit < 32; iBit++)
5491	if ( (RT_BIT_32(iBit) & uCombined)
5492	\|\| (iBit == pDesc->iFirstBit && pDesc->pszName) )
5493	{
5494	while ( pDesc->pszName != NULL
5495	&& iBit >= (uint32_t)pDesc->iFirstBit + pDesc->cBits)
5496	pDesc++;
5497
5498	if ( pDesc->pszName != NULL
5499	&& iBit - (uint32_t)pDesc->iFirstBit < (uint32_t)pDesc->cBits)
5500	{
5501	size_t cchMnemonic = strlen(pDesc->pszName);
5502	const char *pszDesc = pDesc->pszName + cchMnemonic + 1;
5503	size_t cchDesc = strlen(pszDesc);
5504	uint32_t uFieldValue1 = uVal1 >> pDesc->iFirstBit;
5505	uint32_t uFieldValue2 = uVal2 >> pDesc->iFirstBit;
5506	if (pDesc->cBits < 32)
5507	{
5508	uFieldValue1 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5509	uFieldValue2 &= RT_BIT_32(pDesc->cBits) - UINT32_C(1);
5510	}
5511
5512	pHlp->pfnPrintf(pHlp, pDesc->cBits < 4 ? " %s - %s%s= %u (%u)\n" : " %s - %s%s= %#x (%#x)\n",
5513	pDesc->pszName, pszDesc,
5514	cchMnemonic + 3 + cchDesc < cchWidth ? cchWidth - (cchMnemonic + 3 + cchDesc) : 1, "",
5515	uFieldValue1, uFieldValue2);
5516
5517	iBit = pDesc->iFirstBit + pDesc->cBits - 1U;
5518	pDesc++;
5519	}
5520	else
5521	pHlp->pfnPrintf(pHlp, " %2u - Reserved%*s= %u (%u)\n", iBit, 13 < cchWidth ? cchWidth - 13 : 1, "",
5522	RT_BOOL(uVal1 & RT_BIT_32(iBit)), RT_BOOL(uVal2 & RT_BIT_32(iBit)));
5523	}
5524	}
5525
5526
5527	/**
5528	* Produces a detailed summary of standard leaf 0x00000001.
5529	*
5530	* @param pHlp The info helper functions.
5531	* @param pCurLeaf The 0x00000001 leaf.
5532	* @param fVerbose Whether to be very verbose or not.
5533	* @param fIntel Set if intel CPU.
5534	*/
5535	static void cpumR3CpuIdInfoStdLeaf1Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose, bool fIntel)
5536	{
5537	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 1);
5538	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
5539	uint32_t uEAX = pCurLeaf->uEax;
5540	uint32_t uEBX = pCurLeaf->uEbx;
5541
5542	pHlp->pfnPrintf(pHlp,
5543	"%36s %2d \tExtended: %d \tEffective: %d\n"
5544	"%36s %2d \tExtended: %d \tEffective: %d\n"
5545	"%36s %d\n"
5546	"%36s %d (%s)\n"
5547	"%36s %#04x\n"
5548	"%36s %d\n"
5549	"%36s %d\n"
5550	"%36s %#04x\n"
5551	,
5552	"Family:", (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5553	"Model:", (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5554	"Stepping:", RTX86GetCpuStepping(uEAX),
5555	"Type:", (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
5556	"APIC ID:", (uEBX >> 24) & 0xff,
5557	"Logical CPUs:",(uEBX >> 16) & 0xff,
5558	"CLFLUSH Size:",(uEBX >> 8) & 0xff,
5559	"Brand ID:", (uEBX >> 0) & 0xff);
5560	if (fVerbose)
5561	{
5562	CPUMCPUID Host = {0};
5563	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5564	ASMCpuIdExSlow(1, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5565	#endif
5566	pHlp->pfnPrintf(pHlp, "Features\n");
5567	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5568	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf1EdxSubFields, 56);
5569	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf1EcxSubFields, 56);
5570	}
5571	else
5572	{
5573	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf1EdxSubFields, "Features EDX:", 36);
5574	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf1EcxSubFields, "Features ECX:", 36);
5575	}
5576	}
5577
5578
5579	/**
5580	* Produces a detailed summary of standard leaf 0x00000007.
5581	*
5582	* @param pHlp The info helper functions.
5583	* @param paLeaves The CPUID leaves array.
5584	* @param cLeaves The number of leaves in the array.
5585	* @param pCurLeaf The first 0x00000007 leaf.
5586	* @param fVerbose Whether to be very verbose or not.
5587	*/
5588	static void cpumR3CpuIdInfoStdLeaf7Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5589	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5590	{
5591	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 7);
5592	pHlp->pfnPrintf(pHlp, "Structured Extended Feature Flags Enumeration (leaf 7):\n");
5593	for (;;)
5594	{
5595	CPUMCPUID Host = {0};
5596	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5597	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5598	#endif
5599
5600	switch (pCurLeaf->uSubLeaf)
5601	{
5602	case 0:
5603	if (fVerbose)
5604	{
5605	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5606	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aLeaf7Sub0EbxSubFields, 56);
5607	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aLeaf7Sub0EcxSubFields, 56);
5608	if (pCurLeaf->uEdx \|\| Host.uEdx)
5609	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aLeaf7Sub0EdxSubFields, 56);
5610	}
5611	else
5612	{
5613	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aLeaf7Sub0EbxSubFields, "Ext Features EBX:", 36);
5614	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aLeaf7Sub0EcxSubFields, "Ext Features ECX:", 36);
5615	if (pCurLeaf->uEdx)
5616	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aLeaf7Sub0EdxSubFields, "Ext Features EDX:", 36);
5617	}
5618	break;
5619
5620	default:
5621	if (pCurLeaf->uEdx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEbx)
5622	pHlp->pfnPrintf(pHlp, "Unknown extended feature sub-leaf #%u: EAX=%#x EBX=%#x ECX=%#x EDX=%#x\n",
5623	pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx);
5624	break;
5625
5626	}
5627
5628	/* advance. */
5629	pCurLeaf++;
5630	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5631	\|\| pCurLeaf->uLeaf != 0x7)
5632	break;
5633	}
5634	}
5635
5636
5637	/**
5638	* Produces a detailed summary of standard leaf 0x0000000d.
5639	*
5640	* @param pHlp The info helper functions.
5641	* @param paLeaves The CPUID leaves array.
5642	* @param cLeaves The number of leaves in the array.
5643	* @param pCurLeaf The first 0x00000007 leaf.
5644	* @param fVerbose Whether to be very verbose or not.
5645	*/
5646	static void cpumR3CpuIdInfoStdLeaf13Details(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5647	PCCPUMCPUIDLEAF pCurLeaf, bool fVerbose)
5648	{
5649	RT_NOREF_PV(fVerbose);
5650	Assert(pCurLeaf); Assert(pCurLeaf->uLeaf == 13);
5651	pHlp->pfnPrintf(pHlp, "Processor Extended State Enumeration (leaf 0xd):\n");
5652	for (uint32_t uSubLeaf = 0; uSubLeaf < 64; uSubLeaf++)
5653	{
5654	CPUMCPUID Host = {0};
5655	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5656	ASMCpuIdExSlow(UINT32_C(0x0000000d), 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5657	#endif
5658
5659	switch (uSubLeaf)
5660	{
5661	case 0:
5662	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5663	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, guest:",
5664	pCurLeaf->uEbx, pCurLeaf->uEcx);
5665	pHlp->pfnPrintf(pHlp, "%42s %#x/%#x\n", "XSAVE area cur/max size by XCR0, host:", Host.uEbx, Host.uEcx);
5666
5667	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5668	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEax, pCurLeaf->uEdx), g_aXSaveStateBits,
5669	"Valid XCR0 bits, guest:", 42);
5670	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEax, Host.uEdx), g_aXSaveStateBits,
5671	"Valid XCR0 bits, host:", 42);
5672	break;
5673
5674	case 1:
5675	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5676	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, guest:", 42);
5677	cpumR3CpuIdInfoMnemonicListU32(pHlp, Host.uEax, g_aLeaf13Sub1EaxSubFields, "XSAVE features, host:", 42);
5678
5679	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5680	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, guest:", pCurLeaf->uEbx);
5681	pHlp->pfnPrintf(pHlp, "%42s %#x\n", "XSAVE area cur size XCR0\|XSS, host:", Host.uEbx);
5682
5683	if (pCurLeaf && pCurLeaf->uSubLeaf == uSubLeaf)
5684	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(pCurLeaf->uEcx, pCurLeaf->uEdx), g_aXSaveStateBits,
5685	" Valid IA32_XSS bits, guest:", 42);
5686	cpumR3CpuIdInfoValueWithMnemonicListU64(pHlp, RT_MAKE_U64(Host.uEdx, Host.uEcx), g_aXSaveStateBits,
5687	" Valid IA32_XSS bits, host:", 42);
5688	break;
5689
5690	default:
5691	if ( pCurLeaf
5692	&& pCurLeaf->uSubLeaf == uSubLeaf
5693	&& (pCurLeaf->uEax \|\| pCurLeaf->uEbx \|\| pCurLeaf->uEcx \|\| pCurLeaf->uEdx) )
5694	{
5695	pHlp->pfnPrintf(pHlp, " State #%u, guest: off=%#06x, cb=%#06x %s", uSubLeaf, pCurLeaf->uEbx,
5696	pCurLeaf->uEax, pCurLeaf->uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5697	if (pCurLeaf->uEcx & ~RT_BIT_32(0))
5698	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", pCurLeaf->uEcx & ~RT_BIT_32(0));
5699	if (pCurLeaf->uEdx)
5700	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", pCurLeaf->uEdx);
5701	pHlp->pfnPrintf(pHlp, " --");
5702	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5703	pHlp->pfnPrintf(pHlp, "\n");
5704	}
5705	if (Host.uEax \|\| Host.uEbx \|\| Host.uEcx \|\| Host.uEdx)
5706	{
5707	pHlp->pfnPrintf(pHlp, " State #%u, host: off=%#06x, cb=%#06x %s", uSubLeaf, Host.uEbx,
5708	Host.uEax, Host.uEcx & RT_BIT_32(0) ? "XCR0-bit" : "IA32_XSS-bit");
5709	if (Host.uEcx & ~RT_BIT_32(0))
5710	pHlp->pfnPrintf(pHlp, " ECX[reserved]=%#x\n", Host.uEcx & ~RT_BIT_32(0));
5711	if (Host.uEdx)
5712	pHlp->pfnPrintf(pHlp, " EDX[reserved]=%#x\n", Host.uEdx);
5713	pHlp->pfnPrintf(pHlp, " --");
5714	cpumR3CpuIdInfoMnemonicListU64(pHlp, RT_BIT_64(uSubLeaf), g_aXSaveStateBits, NULL, 0);
5715	pHlp->pfnPrintf(pHlp, "\n");
5716	}
5717	break;
5718
5719	}
5720
5721	/* advance. */
5722	if (pCurLeaf)
5723	{
5724	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5725	&& pCurLeaf->uSubLeaf <= uSubLeaf
5726	&& pCurLeaf->uLeaf == UINT32_C(0x0000000d))
5727	pCurLeaf++;
5728	if ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5729	\|\| pCurLeaf->uLeaf != UINT32_C(0x0000000d))
5730	pCurLeaf = NULL;
5731	}
5732	}
5733	}
5734
5735
5736	static PCCPUMCPUIDLEAF cpumR3CpuIdInfoRawRange(PCDBGFINFOHLP pHlp, PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves,
5737	PCCPUMCPUIDLEAF pCurLeaf, uint32_t uUpToLeaf, const char *pszTitle)
5738	{
5739	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5740	&& pCurLeaf->uLeaf <= uUpToLeaf)
5741	{
5742	pHlp->pfnPrintf(pHlp,
5743	" %s\n"
5744	" Leaf/sub-leaf eax ebx ecx edx\n", pszTitle);
5745	while ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5746	&& pCurLeaf->uLeaf <= uUpToLeaf)
5747	{
5748	CPUMCPUID Host = {0};
5749	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5750	ASMCpuIdExSlow(pCurLeaf->uLeaf, 0, pCurLeaf->uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5751	#endif
5752	pHlp->pfnPrintf(pHlp,
5753	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5754	"Hst: %08x %08x %08x %08x\n",
5755	pCurLeaf->uLeaf, pCurLeaf->uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5756	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5757	pCurLeaf++;
5758	}
5759	}
5760
5761	return pCurLeaf;
5762	}
5763
5764
5765	/**
5766	* Display the guest CpuId leaves.
5767	*
5768	* @param pVM The cross context VM structure.
5769	* @param pHlp The info helper functions.
5770	* @param pszArgs "terse", "default" or "verbose".
5771	*/
5772	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5773	{
5774	/*
5775	* Parse the argument.
5776	*/
5777	unsigned iVerbosity = 1;
5778	if (pszArgs)
5779	{
5780	pszArgs = RTStrStripL(pszArgs);
5781	if (!strcmp(pszArgs, "terse"))
5782	iVerbosity--;
5783	else if (!strcmp(pszArgs, "verbose"))
5784	iVerbosity++;
5785	}
5786
5787	uint32_t uLeaf;
5788	CPUMCPUID Host = {0};
5789	uint32_t cLeaves = pVM->cpum.s.GuestInfo.cCpuIdLeaves;
5790	PCPUMCPUIDLEAF paLeaves = pVM->cpum.s.GuestInfo.paCpuIdLeavesR3;
5791	PCCPUMCPUIDLEAF pCurLeaf;
5792	PCCPUMCPUIDLEAF pNextLeaf;
5793	bool const fIntel = RTX86IsIntelCpu(pVM->cpum.s.aGuestCpuIdPatmStd[0].uEbx,
5794	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEcx,
5795	pVM->cpum.s.aGuestCpuIdPatmStd[0].uEdx);
5796
5797	/*
5798	* Standard leaves. Custom raw dump here due to ECX sub-leaves host handling.
5799	*/
5800	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5801	uint32_t cHstMax = ASMCpuId_EAX(0);
5802	#else
5803	uint32_t cHstMax = 0;
5804	#endif
5805	uint32_t cGstMax = paLeaves[0].uLeaf == 0 ? paLeaves[0].uEax : 0;
5806	uint32_t cMax = RT_MAX(cGstMax, cHstMax);
5807	pHlp->pfnPrintf(pHlp,
5808	" Raw Standard CPUID Leaves\n"
5809	" Leaf/sub-leaf eax ebx ecx edx\n");
5810	for (uLeaf = 0, pCurLeaf = paLeaves; uLeaf <= cMax; uLeaf++)
5811	{
5812	uint32_t cMaxSubLeaves = 1;
5813	if (uLeaf == 4 \|\| uLeaf == 7 \|\| uLeaf == 0xb)
5814	cMaxSubLeaves = 16;
5815	else if (uLeaf == 0xd)
5816	cMaxSubLeaves = 128;
5817
5818	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5819	{
5820	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5821	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5822	#endif
5823	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5824	&& pCurLeaf->uLeaf == uLeaf
5825	&& pCurLeaf->uSubLeaf == uSubLeaf)
5826	{
5827	pHlp->pfnPrintf(pHlp,
5828	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5829	"Hst: %08x %08x %08x %08x\n",
5830	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5831	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5832	pCurLeaf++;
5833	}
5834	else if ( uLeaf != 0xd
5835	\|\| uSubLeaf <= 1
5836	\|\| Host.uEbx != 0 )
5837	pHlp->pfnPrintf(pHlp,
5838	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5839	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5840
5841	/* Done? */
5842	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5843	\|\| pCurLeaf->uLeaf != uLeaf)
5844	&& ( (uLeaf == 0x4 && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8))
5845	\|\| (uLeaf == 0x7 && Host.uEax == 0)
5846	\|\| (uLeaf == 0xb && ((Host.uEcx & 0xff00) == 0 \|\| (Host.uEcx & 0xff00) >= 8))
5847	\|\| (uLeaf == 0xb && (Host.uEcx & 0xff) != uSubLeaf)
5848	\|\| (uLeaf == 0xd && uSubLeaf >= 128)
5849	)
5850	)
5851	break;
5852	}
5853	}
5854	pNextLeaf = pCurLeaf;
5855
5856	/*
5857	* If verbose, decode it.
5858	*/
5859	if (iVerbosity && paLeaves[0].uLeaf == 0)
5860	pHlp->pfnPrintf(pHlp,
5861	"%36s %.04s%.04s%.04s\n"
5862	"%36s 0x00000000-%#010x\n"
5863	,
5864	"Name:", &paLeaves[0].uEbx, &paLeaves[0].uEdx, &paLeaves[0].uEcx,
5865	"Supports:", paLeaves[0].uEax);
5866
5867	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000001), 0)) != NULL)
5868	cpumR3CpuIdInfoStdLeaf1Details(pHlp, pCurLeaf, iVerbosity > 1, fIntel);
5869
5870	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x00000007), 0)) != NULL)
5871	cpumR3CpuIdInfoStdLeaf7Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5872
5873	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x0000000d), 0)) != NULL)
5874	cpumR3CpuIdInfoStdLeaf13Details(pHlp, paLeaves, cLeaves, pCurLeaf, iVerbosity > 1);
5875
5876	pCurLeaf = pNextLeaf;
5877
5878	/*
5879	* Hypervisor leaves.
5880	*
5881	* Unlike most of the other leaves reported, the guest hypervisor leaves
5882	* aren't a subset of the host CPUID bits.
5883	*/
5884	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x3fffffff), "Unknown CPUID Leaves");
5885
5886	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5887	ASMCpuIdExSlow(UINT32_C(0x40000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5888	#endif
5889	cHstMax = Host.uEax >= UINT32_C(0x40000001) && Host.uEax <= UINT32_C(0x40000fff) ? Host.uEax : 0;
5890	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x40000000)
5891	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x40000fff)) : 0;
5892	cMax = RT_MAX(cHstMax, cGstMax);
5893	if (cMax >= UINT32_C(0x40000000))
5894	{
5895	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Hypervisor CPUID Leaves");
5896
5897	/** @todo dump these in more detail. */
5898
5899	pCurLeaf = pNextLeaf;
5900	}
5901
5902
5903	/*
5904	* Extended. Custom raw dump here due to ECX sub-leaves host handling.
5905	* Implemented after AMD specs.
5906	*/
5907	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0x7fffffff), "Unknown CPUID Leaves");
5908
5909	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5910	ASMCpuIdExSlow(UINT32_C(0x80000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5911	#endif
5912	cHstMax = RTX86IsValidExtRange(Host.uEax) ? RT_MIN(Host.uEax, UINT32_C(0x80000fff)) : 0;
5913	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0x80000000)
5914	? RT_MIN(pCurLeaf->uEax, UINT32_C(0x80000fff)) : 0;
5915	cMax = RT_MAX(cHstMax, cGstMax);
5916	if (cMax >= UINT32_C(0x80000000))
5917	{
5918
5919	pHlp->pfnPrintf(pHlp,
5920	" Raw Extended CPUID Leaves\n"
5921	" Leaf/sub-leaf eax ebx ecx edx\n");
5922	PCCPUMCPUIDLEAF pExtLeaf = pCurLeaf;
5923	for (uLeaf = UINT32_C(0x80000000); uLeaf <= cMax; uLeaf++)
5924	{
5925	uint32_t cMaxSubLeaves = 1;
5926	if (uLeaf == UINT32_C(0x8000001d))
5927	cMaxSubLeaves = 16;
5928
5929	for (uint32_t uSubLeaf = 0; uSubLeaf < cMaxSubLeaves; uSubLeaf++)
5930	{
5931	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5932	ASMCpuIdExSlow(uLeaf, 0, uSubLeaf, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5933	#endif
5934	if ( (uintptr_t)(pCurLeaf - paLeaves) < cLeaves
5935	&& pCurLeaf->uLeaf == uLeaf
5936	&& pCurLeaf->uSubLeaf == uSubLeaf)
5937	{
5938	pHlp->pfnPrintf(pHlp,
5939	"Gst: %08x/%04x %08x %08x %08x %08x\n"
5940	"Hst: %08x %08x %08x %08x\n",
5941	uLeaf, uSubLeaf, pCurLeaf->uEax, pCurLeaf->uEbx, pCurLeaf->uEcx, pCurLeaf->uEdx,
5942	Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5943	pCurLeaf++;
5944	}
5945	else if ( uLeaf != 0xd
5946	\|\| uSubLeaf <= 1
5947	\|\| Host.uEbx != 0 )
5948	pHlp->pfnPrintf(pHlp,
5949	"Hst: %08x/%04x %08x %08x %08x %08x\n",
5950	uLeaf, uSubLeaf, Host.uEax, Host.uEbx, Host.uEcx, Host.uEdx);
5951
5952	/* Done? */
5953	if ( ( (uintptr_t)(pCurLeaf - paLeaves) >= cLeaves
5954	\|\| pCurLeaf->uLeaf != uLeaf)
5955	&& (uLeaf == UINT32_C(0x8000001d) && ((Host.uEax & 0x000f) == 0 \|\| (Host.uEax & 0x000f) >= 8)) )
5956	break;
5957	}
5958	}
5959	pNextLeaf = pCurLeaf;
5960
5961	/*
5962	* Understandable output
5963	*/
5964	if (iVerbosity)
5965	pHlp->pfnPrintf(pHlp,
5966	"Ext Name: %.4s%.4s%.4s\n"
5967	"Ext Supports: 0x80000000-%#010x\n",
5968	&pExtLeaf->uEbx, &pExtLeaf->uEdx, &pExtLeaf->uEcx, pExtLeaf->uEax);
5969
5970	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000001), 0);
5971	if (iVerbosity && pCurLeaf)
5972	{
5973	uint32_t uEAX = pCurLeaf->uEax;
5974	pHlp->pfnPrintf(pHlp,
5975	"Family: %d \tExtended: %d \tEffective: %d\n"
5976	"Model: %d \tExtended: %d \tEffective: %d\n"
5977	"Stepping: %d\n"
5978	"Brand ID: %#05x\n",
5979	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, RTX86GetCpuFamily(uEAX),
5980	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, RTX86GetCpuModel(uEAX, fIntel),
5981	RTX86GetCpuStepping(uEAX),
5982	pCurLeaf->uEbx & 0xfff);
5983
5984	if (iVerbosity == 1)
5985	{
5986	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf1EdxSubFields, "Ext Features EDX:", 34);
5987	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEcx, g_aExtLeaf1EdxSubFields, "Ext Features ECX:", 34);
5988	}
5989	else
5990	{
5991	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
5992	ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
5993	#endif
5994	pHlp->pfnPrintf(pHlp, "Ext Features\n");
5995	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
5996	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf1EdxSubFields, 56);
5997	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEcx, Host.uEcx, g_aExtLeaf1EcxSubFields, 56);
5998	if (Host.uEcx & X86_CPUID_AMD_FEATURE_ECX_SVM)
5999	{
6000	pHlp->pfnPrintf(pHlp, "SVM Feature Identification (leaf A):\n");
6001	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6002	ASMCpuIdExSlow(0x8000000a, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6003	#endif
6004	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x8000000a), 0);
6005	uint32_t const uGstEdx = pCurLeaf ? pCurLeaf->uEdx : 0;
6006	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, uGstEdx, Host.uEdx, g_aExtLeafAEdxSubFields, 56);
6007	}
6008	}
6009	}
6010
6011	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000002), 0)) != NULL)
6012	{
6013	char szString[443+1] = {0};
6014	uint32_t pu32 = (uint32_t )szString;
6015	*pu32++ = pCurLeaf->uEax;
6016	*pu32++ = pCurLeaf->uEbx;
6017	*pu32++ = pCurLeaf->uEcx;
6018	*pu32++ = pCurLeaf->uEdx;
6019	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000003), 0);
6020	if (pCurLeaf)
6021	{
6022	*pu32++ = pCurLeaf->uEax;
6023	*pu32++ = pCurLeaf->uEbx;
6024	*pu32++ = pCurLeaf->uEcx;
6025	*pu32++ = pCurLeaf->uEdx;
6026	}
6027	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000004), 0);
6028	if (pCurLeaf)
6029	{
6030	*pu32++ = pCurLeaf->uEax;
6031	*pu32++ = pCurLeaf->uEbx;
6032	*pu32++ = pCurLeaf->uEcx;
6033	*pu32++ = pCurLeaf->uEdx;
6034	}
6035	pHlp->pfnPrintf(pHlp, "Full Name: \"%s\"\n", szString);
6036	}
6037
6038	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000005), 0)) != NULL)
6039	{
6040	uint32_t uEAX = pCurLeaf->uEax;
6041	uint32_t uEBX = pCurLeaf->uEbx;
6042	uint32_t uECX = pCurLeaf->uEcx;
6043	uint32_t uEDX = pCurLeaf->uEdx;
6044	char sz1[32];
6045	char sz2[32];
6046
6047	pHlp->pfnPrintf(pHlp,
6048	"TLB 2/4M Instr/Uni: %s %3d entries\n"
6049	"TLB 2/4M Data: %s %3d entries\n",
6050	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
6051	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
6052	pHlp->pfnPrintf(pHlp,
6053	"TLB 4K Instr/Uni: %s %3d entries\n"
6054	"TLB 4K Data: %s %3d entries\n",
6055	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
6056	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
6057	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
6058	"L1 Instr Cache Lines Per Tag: %d\n"
6059	"L1 Instr Cache Associativity: %s\n"
6060	"L1 Instr Cache Size: %d KB\n",
6061	(uEDX >> 0) & 0xff,
6062	(uEDX >> 8) & 0xff,
6063	getCacheAss((uEDX >> 16) & 0xff, sz1),
6064	(uEDX >> 24) & 0xff);
6065	pHlp->pfnPrintf(pHlp,
6066	"L1 Data Cache Line Size: %d bytes\n"
6067	"L1 Data Cache Lines Per Tag: %d\n"
6068	"L1 Data Cache Associativity: %s\n"
6069	"L1 Data Cache Size: %d KB\n",
6070	(uECX >> 0) & 0xff,
6071	(uECX >> 8) & 0xff,
6072	getCacheAss((uECX >> 16) & 0xff, sz1),
6073	(uECX >> 24) & 0xff);
6074	}
6075
6076	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000006), 0)) != NULL)
6077	{
6078	uint32_t uEAX = pCurLeaf->uEax;
6079	uint32_t uEBX = pCurLeaf->uEbx;
6080	uint32_t uECX = pCurLeaf->uEcx;
6081	uint32_t uEDX = pCurLeaf->uEdx;
6082
6083	pHlp->pfnPrintf(pHlp,
6084	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
6085	"L2 TLB 2/4M Data: %s %4d entries\n",
6086	getL23CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
6087	getL23CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
6088	pHlp->pfnPrintf(pHlp,
6089	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
6090	"L2 TLB 4K Data: %s %4d entries\n",
6091	getL23CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
6092	getL23CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
6093	pHlp->pfnPrintf(pHlp,
6094	"L2 Cache Line Size: %d bytes\n"
6095	"L2 Cache Lines Per Tag: %d\n"
6096	"L2 Cache Associativity: %s\n"
6097	"L2 Cache Size: %d KB\n",
6098	(uECX >> 0) & 0xff,
6099	(uECX >> 8) & 0xf,
6100	getL23CacheAss((uECX >> 12) & 0xf),
6101	(uECX >> 16) & 0xffff);
6102	pHlp->pfnPrintf(pHlp,
6103	"L3 Cache Line Size: %d bytes\n"
6104	"L3 Cache Lines Per Tag: %d\n"
6105	"L3 Cache Associativity: %s\n"
6106	"L3 Cache Size: %d KB\n",
6107	(uEDX >> 0) & 0xff,
6108	(uEDX >> 8) & 0xf,
6109	getL23CacheAss((uEDX >> 12) & 0xf),
6110	((uEDX >> 18) & 0x3fff) * 512);
6111	}
6112
6113	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000007), 0)) != NULL)
6114	{
6115	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6116	ASMCpuIdExSlow(UINT32_C(0x80000007), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6117	#endif
6118	if (pCurLeaf->uEdx \|\| (Host.uEdx && iVerbosity))
6119	{
6120	if (iVerbosity < 1)
6121	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEdx, g_aExtLeaf7EdxSubFields, "APM Features EDX:", 34);
6122	else
6123	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEdx, Host.uEdx, g_aExtLeaf7EdxSubFields, 56);
6124	}
6125	}
6126
6127	pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0x80000008), 0);
6128	if (pCurLeaf != NULL)
6129	{
6130	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6131	ASMCpuIdExSlow(UINT32_C(0x80000008), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6132	#endif
6133	if (pCurLeaf->uEbx \|\| (Host.uEbx && iVerbosity))
6134	{
6135	if (iVerbosity < 1)
6136	cpumR3CpuIdInfoMnemonicListU32(pHlp, pCurLeaf->uEbx, g_aExtLeaf8EbxSubFields, "Ext Features ext IDs EBX:", 34);
6137	else
6138	cpumR3CpuIdInfoVerboseCompareListU32(pHlp, pCurLeaf->uEbx, Host.uEbx, g_aExtLeaf8EbxSubFields, 56);
6139	}
6140
6141	if (iVerbosity)
6142	{
6143	uint32_t uEAX = pCurLeaf->uEax;
6144	uint32_t uECX = pCurLeaf->uEcx;
6145
6146	/** @todo 0x80000008:EAX[23:16] is only defined for AMD. We'll get 0 on Intel. On
6147	* AMD if we get 0, the guest physical address width should be taken from
6148	* 0x80000008:EAX[7:0] instead. Guest Physical address width is relevant
6149	* for guests using nested paging. */
6150	pHlp->pfnPrintf(pHlp,
6151	"Physical Address Width: %d bits\n"
6152	"Virtual Address Width: %d bits\n"
6153	"Guest Physical Address Width: %d bits\n",
6154	(uEAX >> 0) & 0xff,
6155	(uEAX >> 8) & 0xff,
6156	(uEAX >> 16) & 0xff);
6157
6158	/** @todo 0x80000008:ECX is reserved on Intel (we'll get incorrect physical core
6159	* count here). */
6160	pHlp->pfnPrintf(pHlp,
6161	"Physical Core Count: %d\n",
6162	((uECX >> 0) & 0xff) + 1);
6163	}
6164	}
6165
6166	pCurLeaf = pNextLeaf;
6167	}
6168
6169
6170
6171	/*
6172	* Centaur.
6173	*/
6174	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xbfffffff), "Unknown CPUID Leaves");
6175
6176	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6177	ASMCpuIdExSlow(UINT32_C(0xc0000000), 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6178	#endif
6179	cHstMax = Host.uEax >= UINT32_C(0xc0000001) && Host.uEax <= UINT32_C(0xc0000fff)
6180	? RT_MIN(Host.uEax, UINT32_C(0xc0000fff)) : 0;
6181	cGstMax = (uintptr_t)(pCurLeaf - paLeaves) < cLeaves && pCurLeaf->uLeaf == UINT32_C(0xc0000000)
6182	? RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000fff)) : 0;
6183	cMax = RT_MAX(cHstMax, cGstMax);
6184	if (cMax >= UINT32_C(0xc0000000))
6185	{
6186	pNextLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, cMax, "Raw Centaur CPUID Leaves");
6187
6188	/*
6189	* Understandable output
6190	*/
6191	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000000), 0)) != NULL)
6192	pHlp->pfnPrintf(pHlp,
6193	"Centaur Supports: 0xc0000000-%#010x\n",
6194	pCurLeaf->uEax);
6195
6196	if (iVerbosity && (pCurLeaf = cpumCpuIdGetLeafInt(paLeaves, cLeaves, UINT32_C(0xc0000001), 0)) != NULL)
6197	{
6198	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
6199	ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.uEax, &Host.uEbx, &Host.uEcx, &Host.uEdx);
6200	#endif
6201	uint32_t uEdxGst = pCurLeaf->uEdx;
6202	uint32_t uEdxHst = Host.uEdx;
6203
6204	if (iVerbosity == 1)
6205	{
6206	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
6207	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
6208	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
6209	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
6210	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
6211	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
6212	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
6213	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
6214	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
6215	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6216	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
6217	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
6218	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
6219	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
6220	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
6221	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
6222	for (unsigned iBit = 14; iBit < 32; iBit++)
6223	if (uEdxGst & RT_BIT(iBit))
6224	pHlp->pfnPrintf(pHlp, " %d", iBit);
6225	pHlp->pfnPrintf(pHlp, "\n");
6226	}
6227	else
6228	{
6229	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
6230	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
6231	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
6232	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
6233	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
6234	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
6235	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
6236	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
6237	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
6238	/* possibly indicating MM/HE and MM/HE-E on older chips... */
6239	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
6240	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
6241	pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
6242	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
6243	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
6244	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
6245	pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
6246	pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
6247	pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
6248	pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
6249	pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
6250	pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
6251	pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
6252	pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
6253	pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
6254	pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
6255	pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
6256	pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
6257	pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
6258	for (unsigned iBit = 27; iBit < 32; iBit++)
6259	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
6260	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
6261	pHlp->pfnPrintf(pHlp, "\n");
6262	}
6263	}
6264
6265	pCurLeaf = pNextLeaf;
6266	}
6267
6268	/*
6269	* The remainder.
6270	*/
6271	pCurLeaf = cpumR3CpuIdInfoRawRange(pHlp, paLeaves, cLeaves, pCurLeaf, UINT32_C(0xffffffff), "Unknown CPUID Leaves");
6272	}
6273
6274	#endif /* !IN_VBOX_CPU_REPORT */
6275

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

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