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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 98103

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1/* $Id: CPUM.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_cpum CPUM - CPU Monitor / Manager
29 *
30 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
31 * also responsible for lazy FPU handling and some of the context loading
32 * in raw mode.
33 *
34 * There are three CPU contexts, the most important one is the guest one (GC).
35 * When running in raw-mode (RC) there is a special hyper context for the VMM
36 * part that floats around inside the guest address space. When running in
37 * raw-mode, CPUM also maintains a host context for saving and restoring
38 * registers across world switches. This latter is done in cooperation with the
39 * world switcher (@see pg_vmm).
40 *
41 * @see grp_cpum
42 *
43 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44 *
45 * TODO: proper write up, currently just some notes.
46 *
47 * The ring-0 FPU handling per OS:
48 *
49 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
50 * convention (Visual C++ doesn't seem to have a way to disable
51 * generating such code either), so CR0.TS/EM are always zero from what I
52 * can tell. We are also forced to always load/save the guest XMM0-XMM15
53 * registers when entering/leaving guest context. Interrupt handlers
54 * using FPU/SSE will offically have call save and restore functions
55 * exported by the kernel, if the really really have to use the state.
56 *
57 * - 32-bit windows does lazy FPU handling, I think, probably including
58 * lazying saving. The Windows Internals book states that it's a bad
59 * idea to use the FPU in kernel space. However, it looks like it will
60 * restore the FPU state of the current thread in case of a kernel \#NM.
61 * Interrupt handlers should be same as for 64-bit.
62 *
63 * - Darwin allows taking \#NM in kernel space, restoring current thread's
64 * state if I read the code correctly. It saves the FPU state of the
65 * outgoing thread, and uses CR0.TS to lazily load the state of the
66 * incoming one. No idea yet how the FPU is treated by interrupt
67 * handlers, i.e. whether they are allowed to disable the state or
68 * something.
69 *
70 * - Linux also allows \#NM in kernel space (don't know since when), and
71 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72 * loads the incoming unless configured to agressivly load it. Interrupt
73 * handlers can ask whether they're allowed to use the FPU, and may
74 * freely trash the state if Linux thinks it has saved the thread's state
75 * already. This is a problem.
76 *
77 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78 * context. When switching threads, the kernel will save the state of
79 * the outgoing thread and lazy load the incoming one using CR0.TS.
80 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
81 * to do stuff, HAT are among the users. The routines there will
82 * manually clear CR0.TS and save the XMM registers they use only if
83 * CR0.TS was zero upon entry. They will skip it when not, because as
84 * mentioned above, the FPU state is saved when switching away from a
85 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86 * preserve. This is a problem if we restore CR0.TS to 1 after loading
87 * the guest state.
88 *
89 * - FreeBSD - no idea yet.
90 *
91 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93 * FPU states.
94 *
95 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96 * saving and restoring the host and guest states. The motivation for this
97 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98 *
99 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100 * state and only restore it once we've restore the host FPU state. This has the
101 * accidental side effect of triggering Solaris to preserve XMM registers in
102 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104 *
105 *
106 * @section sec_cpum_logging Logging Level Assignments.
107 *
108 * Following log level assignments:
109 * - Log6 is used for FPU state management.
110 * - Log7 is used for FPU state actualization.
111 *
112 */
113
114
115/*********************************************************************************************************************************
116* Header Files *
117*********************************************************************************************************************************/
118#define LOG_GROUP LOG_GROUP_CPUM
119#define CPUM_WITH_NONCONST_HOST_FEATURES
120#include <VBox/vmm/cpum.h>
121#include <VBox/vmm/cpumdis.h>
122#include <VBox/vmm/cpumctx-v1_6.h>
123#include <VBox/vmm/pgm.h>
124#include <VBox/vmm/apic.h>
125#include <VBox/vmm/mm.h>
126#include <VBox/vmm/em.h>
127#include <VBox/vmm/iem.h>
128#include <VBox/vmm/selm.h>
129#include <VBox/vmm/dbgf.h>
130#include <VBox/vmm/hm.h>
131#include <VBox/vmm/hmvmxinline.h>
132#include <VBox/vmm/ssm.h>
133#include "CPUMInternal.h"
134#include <VBox/vmm/vm.h>
135
136#include <VBox/param.h>
137#include <VBox/dis.h>
138#include <VBox/err.h>
139#include <VBox/log.h>
140#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
141# include <iprt/asm-amd64-x86.h>
142#endif
143#include <iprt/assert.h>
144#include <iprt/cpuset.h>
145#include <iprt/mem.h>
146#include <iprt/mp.h>
147#include <iprt/rand.h>
148#include <iprt/string.h>
149
150
151/*********************************************************************************************************************************
152* Defined Constants And Macros *
153*********************************************************************************************************************************/
154/**
155 * This was used in the saved state up to the early life of version 14.
156 *
157 * It indicates that we may have some out-of-sync hidden segement registers.
158 * It is only relevant for raw-mode.
159 */
160#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
161
162
163/** For saved state only: Block injection of non-maskable interrupts to the guest.
164 * @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
165#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
166
167
168/*********************************************************************************************************************************
169* Structures and Typedefs *
170*********************************************************************************************************************************/
171
172/**
173 * What kind of cpu info dump to perform.
174 */
175typedef enum CPUMDUMPTYPE
176{
177 CPUMDUMPTYPE_TERSE,
178 CPUMDUMPTYPE_DEFAULT,
179 CPUMDUMPTYPE_VERBOSE
180} CPUMDUMPTYPE;
181/** Pointer to a cpu info dump type. */
182typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
183
184
185/*********************************************************************************************************************************
186* Internal Functions *
187*********************************************************************************************************************************/
188static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
189static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
190static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
191static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
192static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
193static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
194static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
195static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
196static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
197static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
198static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
199
200
201/*********************************************************************************************************************************
202* Global Variables *
203*********************************************************************************************************************************/
204#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
205/** Host CPU features. */
206DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
207#endif
208
209/** Saved state field descriptors for CPUMCTX. */
210static const SSMFIELD g_aCpumCtxFields[] =
211{
212 SSMFIELD_ENTRY( CPUMCTX, rdi),
213 SSMFIELD_ENTRY( CPUMCTX, rsi),
214 SSMFIELD_ENTRY( CPUMCTX, rbp),
215 SSMFIELD_ENTRY( CPUMCTX, rax),
216 SSMFIELD_ENTRY( CPUMCTX, rbx),
217 SSMFIELD_ENTRY( CPUMCTX, rdx),
218 SSMFIELD_ENTRY( CPUMCTX, rcx),
219 SSMFIELD_ENTRY( CPUMCTX, rsp),
220 SSMFIELD_ENTRY( CPUMCTX, rflags),
221 SSMFIELD_ENTRY( CPUMCTX, rip),
222 SSMFIELD_ENTRY( CPUMCTX, r8),
223 SSMFIELD_ENTRY( CPUMCTX, r9),
224 SSMFIELD_ENTRY( CPUMCTX, r10),
225 SSMFIELD_ENTRY( CPUMCTX, r11),
226 SSMFIELD_ENTRY( CPUMCTX, r12),
227 SSMFIELD_ENTRY( CPUMCTX, r13),
228 SSMFIELD_ENTRY( CPUMCTX, r14),
229 SSMFIELD_ENTRY( CPUMCTX, r15),
230 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
231 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
232 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
233 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
234 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
235 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
236 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
237 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
238 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
239 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
240 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
241 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
242 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
243 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
244 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
245 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
246 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
247 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
248 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
249 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
250 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
251 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
252 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
253 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
254 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
255 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
256 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
257 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
258 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
259 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
260 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
261 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
262 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
263 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
264 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
265 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
266 SSMFIELD_ENTRY( CPUMCTX, cr0),
267 SSMFIELD_ENTRY( CPUMCTX, cr2),
268 SSMFIELD_ENTRY( CPUMCTX, cr3),
269 SSMFIELD_ENTRY( CPUMCTX, cr4),
270 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
271 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
272 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
273 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
274 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
275 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
276 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
277 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
278 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
279 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
280 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
281 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
282 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
283 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
284 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
285 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
286 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
287 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
288 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
289 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
290 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
291 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
292 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
293 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
294 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
295 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
296 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
297 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
298 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
299 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
300 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
301 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
302 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
303 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
304 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
305 SSMFIELD_ENTRY_TERM()
306};
307
308/** Saved state field descriptors for SVM nested hardware-virtualization
309 * Host State. */
310static const SSMFIELD g_aSvmHwvirtHostState[] =
311{
312 SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
313 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
314 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
315 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
316 SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
317 SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
318 SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
319 SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
320 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
321 SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
322 SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
323 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
324 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
325 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
326 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
327 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
328 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
329 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
330 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
331 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
332 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
333 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
334 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
335 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
336 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
337 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
338 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
339 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
340 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
341 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
342 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
343 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
344 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
345 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
346 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
347 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
348 SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
349 SSMFIELD_ENTRY_TERM()
350};
351
352/** Saved state field descriptors for VMX nested hardware-virtualization
353 * VMCS. */
354static const SSMFIELD g_aVmxHwvirtVmcs[] =
355{
356 SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
357 SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
358 SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
359 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
360 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
361
362 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
363
364 SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
365 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
366 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
367 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
368 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
369 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
370 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
371 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
372 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
373
374 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
375 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
376
377 SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
378 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
379 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
380 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
381 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
382 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
383 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
384
385 SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
386 SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
387 SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
388 SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
389 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
390
391 SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
392 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
393 SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
394 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
395 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
396 SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
397 SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
398 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
399 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
400 SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
401 SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
402 SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
403 SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
404 SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
405 SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
406 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
407 SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
408 SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
409 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
410
411 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
412 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
413 SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
414 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
415 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
416 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
417 SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
418 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
419 SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
420 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
421 SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
422 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
423 SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
424 SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
425 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
426 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
427 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
428 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
429 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
430 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
431 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
432 SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
433 SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
434 SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
435 SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
436 SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
437 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
438 SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
439 SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
440 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
441 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
442 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
443
444 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
445 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
446 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
447 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
448 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
449 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
450 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
451 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
452 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
453
454 SSMFIELD_ENTRY( VMXVVMCS, HostEs),
455 SSMFIELD_ENTRY( VMXVVMCS, HostCs),
456 SSMFIELD_ENTRY( VMXVVMCS, HostSs),
457 SSMFIELD_ENTRY( VMXVVMCS, HostDs),
458 SSMFIELD_ENTRY( VMXVVMCS, HostFs),
459 SSMFIELD_ENTRY( VMXVVMCS, HostGs),
460 SSMFIELD_ENTRY( VMXVVMCS, HostTr),
461 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
462
463 SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
464 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
465
466 SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
467 SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
468 SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
469 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
470 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
471
472 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
473 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
474 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
475 SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
476 SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
477 SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
478 SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
479 SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
480 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
481 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
482 SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
483 SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
484 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
485 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
486 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
487 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
488
489 SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
490 SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
491 SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
492 SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
493 SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
494 SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
495 SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
496 SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
497 SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
498 SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
499 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
500
501 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
502 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
503 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
504 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
505 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
506 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
507 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
508 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
509 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
510 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
511 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
512 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
513 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
514 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
515 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
516 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
517 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
518 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
519 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
520 SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
521 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
522 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
523 SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
524 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
525
526 SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
527 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
528 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
529 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
530 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
531 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
532 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
533 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
534 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
535 SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
536 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
537 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
538 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
539
540 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
541 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
542 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
543 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
544 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
545 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
546 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
547 SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
548 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
549 SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
550 SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
551 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
552 SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
553 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
554 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
555 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
556 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
557 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
558 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
559 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
560 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
561 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
562 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
563 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
564
565 SSMFIELD_ENTRY_TERM()
566};
567
568/** Saved state field descriptors for CPUMCTX. */
569static const SSMFIELD g_aCpumX87Fields[] =
570{
571 SSMFIELD_ENTRY( X86FXSTATE, FCW),
572 SSMFIELD_ENTRY( X86FXSTATE, FSW),
573 SSMFIELD_ENTRY( X86FXSTATE, FTW),
574 SSMFIELD_ENTRY( X86FXSTATE, FOP),
575 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
576 SSMFIELD_ENTRY( X86FXSTATE, CS),
577 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
578 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
579 SSMFIELD_ENTRY( X86FXSTATE, DS),
580 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
581 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
582 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
583 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
584 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
585 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
586 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
587 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
588 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
589 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
590 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
591 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
592 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
593 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
594 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
595 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
596 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
604 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
605 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
606 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
607 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
608 SSMFIELD_ENTRY_TERM()
609};
610
611/** Saved state field descriptors for X86XSAVEHDR. */
612static const SSMFIELD g_aCpumXSaveHdrFields[] =
613{
614 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
615 SSMFIELD_ENTRY_TERM()
616};
617
618/** Saved state field descriptors for X86XSAVEYMMHI. */
619static const SSMFIELD g_aCpumYmmHiFields[] =
620{
621 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
622 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
623 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
624 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
625 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
626 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
627 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
628 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
629 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
630 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
631 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
632 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
633 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
634 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
635 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
636 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
637 SSMFIELD_ENTRY_TERM()
638};
639
640/** Saved state field descriptors for X86XSAVEBNDREGS. */
641static const SSMFIELD g_aCpumBndRegsFields[] =
642{
643 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
644 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
645 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
646 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
647 SSMFIELD_ENTRY_TERM()
648};
649
650/** Saved state field descriptors for X86XSAVEBNDCFG. */
651static const SSMFIELD g_aCpumBndCfgFields[] =
652{
653 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
654 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
655 SSMFIELD_ENTRY_TERM()
656};
657
658#if 0 /** @todo */
659/** Saved state field descriptors for X86XSAVEOPMASK. */
660static const SSMFIELD g_aCpumOpmaskFields[] =
661{
662 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
663 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
664 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
665 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
666 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
667 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
668 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
669 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
670 SSMFIELD_ENTRY_TERM()
671};
672#endif
673
674/** Saved state field descriptors for X86XSAVEZMMHI256. */
675static const SSMFIELD g_aCpumZmmHi256Fields[] =
676{
677 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
678 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
679 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
680 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
681 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
682 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
683 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
684 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
685 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
686 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
687 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
688 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
689 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
690 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
691 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
692 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
693 SSMFIELD_ENTRY_TERM()
694};
695
696/** Saved state field descriptors for X86XSAVEZMM16HI. */
697static const SSMFIELD g_aCpumZmm16HiFields[] =
698{
699 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
700 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
701 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
702 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
703 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
704 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
705 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
706 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
707 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
708 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
709 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
710 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
711 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
712 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
713 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
714 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
715 SSMFIELD_ENTRY_TERM()
716};
717
718
719
720/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
721 * registeres changed. */
722static const SSMFIELD g_aCpumX87FieldsMem[] =
723{
724 SSMFIELD_ENTRY( X86FXSTATE, FCW),
725 SSMFIELD_ENTRY( X86FXSTATE, FSW),
726 SSMFIELD_ENTRY( X86FXSTATE, FTW),
727 SSMFIELD_ENTRY( X86FXSTATE, FOP),
728 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
729 SSMFIELD_ENTRY( X86FXSTATE, CS),
730 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
731 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
732 SSMFIELD_ENTRY( X86FXSTATE, DS),
733 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
734 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
735 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
736 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
737 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
738 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
739 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
740 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
741 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
742 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
743 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
744 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
745 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
746 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
747 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
748 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
749 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
750 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
751 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
752 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
753 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
754 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
755 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
756 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
757 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
758 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
759 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
760 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
761 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
762};
763
764/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
765 * registeres changed. */
766static const SSMFIELD g_aCpumCtxFieldsMem[] =
767{
768 SSMFIELD_ENTRY( CPUMCTX, rdi),
769 SSMFIELD_ENTRY( CPUMCTX, rsi),
770 SSMFIELD_ENTRY( CPUMCTX, rbp),
771 SSMFIELD_ENTRY( CPUMCTX, rax),
772 SSMFIELD_ENTRY( CPUMCTX, rbx),
773 SSMFIELD_ENTRY( CPUMCTX, rdx),
774 SSMFIELD_ENTRY( CPUMCTX, rcx),
775 SSMFIELD_ENTRY( CPUMCTX, rsp),
776 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
777 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
778 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
779 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
780 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
781 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
782 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
783 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
784 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
785 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
786 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
787 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
788 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
789 SSMFIELD_ENTRY( CPUMCTX, rflags),
790 SSMFIELD_ENTRY( CPUMCTX, rip),
791 SSMFIELD_ENTRY( CPUMCTX, r8),
792 SSMFIELD_ENTRY( CPUMCTX, r9),
793 SSMFIELD_ENTRY( CPUMCTX, r10),
794 SSMFIELD_ENTRY( CPUMCTX, r11),
795 SSMFIELD_ENTRY( CPUMCTX, r12),
796 SSMFIELD_ENTRY( CPUMCTX, r13),
797 SSMFIELD_ENTRY( CPUMCTX, r14),
798 SSMFIELD_ENTRY( CPUMCTX, r15),
799 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
800 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
801 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
802 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
803 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
804 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
805 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
806 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
807 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
808 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
809 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
810 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
811 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
812 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
813 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
814 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
815 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
816 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
817 SSMFIELD_ENTRY( CPUMCTX, cr0),
818 SSMFIELD_ENTRY( CPUMCTX, cr2),
819 SSMFIELD_ENTRY( CPUMCTX, cr3),
820 SSMFIELD_ENTRY( CPUMCTX, cr4),
821 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
822 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
823 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
824 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
825 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
826 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
827 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
828 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
829 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
830 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
831 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
832 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
833 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
834 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
835 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
836 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
837 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
838 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
839 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
840 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
841 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
842 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
843 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
844 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
845 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
846 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
847 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
848 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
849 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
850 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
851 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
852 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
853 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
854 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
855 SSMFIELD_ENTRY_TERM()
856};
857
858/** Saved state field descriptors for CPUMCTX_VER1_6. */
859static const SSMFIELD g_aCpumX87FieldsV16[] =
860{
861 SSMFIELD_ENTRY( X86FXSTATE, FCW),
862 SSMFIELD_ENTRY( X86FXSTATE, FSW),
863 SSMFIELD_ENTRY( X86FXSTATE, FTW),
864 SSMFIELD_ENTRY( X86FXSTATE, FOP),
865 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
866 SSMFIELD_ENTRY( X86FXSTATE, CS),
867 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
868 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
869 SSMFIELD_ENTRY( X86FXSTATE, DS),
870 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
871 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
872 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
873 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
874 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
875 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
876 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
877 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
878 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
879 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
880 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
881 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
882 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
883 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
884 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
885 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
886 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
887 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
888 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
889 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
890 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
891 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
892 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
893 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
894 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
895 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
896 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
897 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
898 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
899 SSMFIELD_ENTRY_TERM()
900};
901
902/** Saved state field descriptors for CPUMCTX_VER1_6. */
903static const SSMFIELD g_aCpumCtxFieldsV16[] =
904{
905 SSMFIELD_ENTRY( CPUMCTX, rdi),
906 SSMFIELD_ENTRY( CPUMCTX, rsi),
907 SSMFIELD_ENTRY( CPUMCTX, rbp),
908 SSMFIELD_ENTRY( CPUMCTX, rax),
909 SSMFIELD_ENTRY( CPUMCTX, rbx),
910 SSMFIELD_ENTRY( CPUMCTX, rdx),
911 SSMFIELD_ENTRY( CPUMCTX, rcx),
912 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
913 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
914 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
915 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
916 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
917 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
918 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
919 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
920 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
921 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
922 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
923 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
924 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
925 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
926 SSMFIELD_ENTRY( CPUMCTX, rflags),
927 SSMFIELD_ENTRY( CPUMCTX, rip),
928 SSMFIELD_ENTRY( CPUMCTX, r8),
929 SSMFIELD_ENTRY( CPUMCTX, r9),
930 SSMFIELD_ENTRY( CPUMCTX, r10),
931 SSMFIELD_ENTRY( CPUMCTX, r11),
932 SSMFIELD_ENTRY( CPUMCTX, r12),
933 SSMFIELD_ENTRY( CPUMCTX, r13),
934 SSMFIELD_ENTRY( CPUMCTX, r14),
935 SSMFIELD_ENTRY( CPUMCTX, r15),
936 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
937 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
938 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
939 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
940 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
941 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
942 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
943 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
944 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
945 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
946 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
947 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
948 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
949 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
950 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
951 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
952 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
953 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
954 SSMFIELD_ENTRY( CPUMCTX, cr0),
955 SSMFIELD_ENTRY( CPUMCTX, cr2),
956 SSMFIELD_ENTRY( CPUMCTX, cr3),
957 SSMFIELD_ENTRY( CPUMCTX, cr4),
958 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
959 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
960 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
961 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
962 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
963 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
964 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
965 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
966 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
967 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
968 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
969 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
970 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
971 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
972 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
973 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
974 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
975 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
976 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
977 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
978 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
979 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
980 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
981 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
982 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
983 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
984 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
985 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
986 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
987 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
988 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
989 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
990 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
991 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
992 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
993 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
994 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
995 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
996 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
997 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
998 SSMFIELD_ENTRY_TERM()
999};
1000
1001
1002#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1003/**
1004 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1005 *
1006 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1007 * (last instruction pointer, last data pointer, last opcode) except when the ES
1008 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1009 * clear these registers there is potential, local FPU leakage from a process
1010 * using the FPU to another.
1011 *
1012 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
1013 *
1014 * @param pVM The cross context VM structure.
1015 */
1016static void cpumR3CheckLeakyFpu(PVM pVM)
1017{
1018 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1019 uint32_t const u32Family = u32CpuVersion >> 8;
1020 if ( u32Family >= 6 /* K7 and higher */
1021 && (ASMIsAmdCpu() || ASMIsHygonCpu()) )
1022 {
1023 uint32_t cExt = ASMCpuId_EAX(0x80000000);
1024 if (RTX86IsValidExtRange(cExt))
1025 {
1026 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1027 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1028 {
1029 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1030 {
1031 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1032 pVCpu->cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
1033 }
1034 Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1035 }
1036 }
1037 }
1038}
1039#endif
1040
1041
1042/**
1043 * Initialize the SVM hardware virtualization state.
1044 *
1045 * @param pVM The cross context VM structure.
1046 */
1047static void cpumR3InitSvmHwVirtState(PVM pVM)
1048{
1049 LogRel(("CPUM: AMD-V nested-guest init\n"));
1050 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1051 {
1052 PVMCPU pVCpu = pVM->apCpusR3[i];
1053 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1054
1055 /* Initialize that SVM hardware virtualization is available. */
1056 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1057
1058 AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1059 AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1060 AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1061
1062 /* Initialize non-zero values. */
1063 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1064 }
1065}
1066
1067
1068/**
1069 * Resets per-VCPU SVM hardware virtualization state.
1070 *
1071 * @param pVCpu The cross context virtual CPU structure.
1072 */
1073DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1074{
1075 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1076 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1077
1078 RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1079 RT_ZERO(pCtx->hwvirt.svm.HostState);
1080 RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1081 RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1082
1083 pCtx->hwvirt.svm.uMsrHSavePa = 0;
1084 pCtx->hwvirt.svm.uPrevPauseTick = 0;
1085 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1086 pCtx->hwvirt.svm.cPauseFilter = 0;
1087 pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1088 pCtx->hwvirt.svm.fInterceptEvents = false;
1089}
1090
1091
1092/**
1093 * Initializes the VMX hardware virtualization state.
1094 *
1095 * @param pVM The cross context VM structure.
1096 */
1097static void cpumR3InitVmxHwVirtState(PVM pVM)
1098{
1099 LogRel(("CPUM: VT-x nested-guest init\n"));
1100 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1101 {
1102 PVMCPU pVCpu = pVM->apCpusR3[i];
1103 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1104
1105 /* Initialize that VMX hardware virtualization is available. */
1106 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1107
1108 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1109 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1110 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1111 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1112 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1113 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1114 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1115 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1116 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1117 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1118 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1119 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1120 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1121 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1122 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1123 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1124 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1125 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1126
1127 /* Initialize non-zero values. */
1128 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1129 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1130 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1131 }
1132}
1133
1134
1135/**
1136 * Resets per-VCPU VMX hardware virtualization state.
1137 *
1138 * @param pVCpu The cross context virtual CPU structure.
1139 */
1140DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1141{
1142 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1143 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1144
1145 RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1146 RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1147 RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1148 RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1149 RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1150 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1151 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1152 RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1153 RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1154
1155 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1156 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1157 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1158 pCtx->hwvirt.vmx.fInVmxRootMode = false;
1159 pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1160 /* Don't reset diagnostics here. */
1161
1162 pCtx->hwvirt.vmx.fInterceptEvents = false;
1163 pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1164 pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1165 pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1166 pCtx->hwvirt.vmx.uEntryTick = 0;
1167 pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1168 pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1169
1170 /* Stop any VMX-preemption timer. */
1171 CPUMStopGuestVmxPremptTimer(pVCpu);
1172
1173 /* Clear all nested-guest FFs. */
1174 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1175}
1176
1177
1178/**
1179 * Displays the host and guest VMX features.
1180 *
1181 * @param pVM The cross context VM structure.
1182 * @param pHlp The info helper functions.
1183 * @param pszArgs "terse", "default" or "verbose".
1184 */
1185DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1186{
1187 RT_NOREF(pszArgs);
1188 PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1189 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1190 if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1191 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1192 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1193 {
1194#define VMXFEATDUMP(a_szDesc, a_Var) \
1195 pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1196
1197 pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1198 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1199 VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1200 /* Basic. */
1201 VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1202
1203 /* Pin-based controls. */
1204 VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1205 VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1206 VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1207 VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1208 VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1209
1210 /* Processor-based controls. */
1211 VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1212 VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1213 VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1214 VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1215 VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1216 VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1217 VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1218 VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1219 VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1220 VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1221 VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1222 VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1223 VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1224 VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1225 VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1226 VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1227 VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1228 VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1229 VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1230 VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1231 VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1232 VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1233
1234 /* Secondary processor-based controls. */
1235 VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1236 VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1237 VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1238 VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1239 VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1240 VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1241 VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1242 VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1243 VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1244 VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1245 VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1246 VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1247 VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1248 VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1249 VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1250 VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1251 VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1252 VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1253 VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1254 VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1255 VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1256 VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1257 VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1258 VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1259 VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1260 VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1261
1262 /* Tertiary processor-based controls. */
1263 VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1264
1265 /* VM-entry controls. */
1266 VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1267 VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1268 VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1269 VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1270
1271 /* VM-exit controls. */
1272 VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1273 VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1274 VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1275 VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1276 VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1277 VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1278 VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1279 VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1280 VMXFEATDUMP("SecondaryExitCtls - Secondary VM-exit controls ", fVmxSecondaryExitCtls);
1281
1282 /* Miscellaneous data. */
1283 VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1284 VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1285 VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1286 VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1287#undef VMXFEATDUMP
1288 }
1289 else
1290 pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1291}
1292
1293
1294/**
1295 * Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1296 * or NEM) is allowed.
1297 *
1298 * @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1299 * otherwise.
1300 * @param pVM The cross context VM structure.
1301 */
1302static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1303{
1304 AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1305#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1306 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1307 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1308 return true;
1309#else
1310 NOREF(pVM);
1311#endif
1312 return false;
1313}
1314
1315
1316/**
1317 * Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1318 *
1319 * @param pVM The cross context VM structure.
1320 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1321 * and no hardware-assisted nested-guest execution is
1322 * possible for this VM.
1323 * @param pGuestFeatures The guest features to use (only VMX features are
1324 * accessed).
1325 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1326 *
1327 * @remarks This function ASSUMES the VMX guest-features are already exploded!
1328 */
1329static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1330{
1331 bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1332
1333 Assert(!fIsNstGstHwExecAllowed || pHostVmxMsrs);
1334 Assert(pGuestFeatures->fVmx);
1335
1336 /* Basic information. */
1337 uint8_t const fTrueVmxMsrs = 1;
1338 {
1339 uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1340 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1341 | RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1342 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1343 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1344 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1345 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1346 pGuestVmxMsrs->u64Basic = u64Basic;
1347 }
1348
1349 /* Pin-based VM-execution controls. */
1350 {
1351 uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1352 | (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1353 | (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1354 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1355 | (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1356 uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1357 uint32_t const fAllowed1 = fFeatures | VMX_PIN_CTLS_DEFAULT1;
1358 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1359 fAllowed0, fAllowed1, fFeatures));
1360 pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1361
1362 /* True pin-based VM-execution controls. */
1363 if (fTrueVmxMsrs)
1364 {
1365 /* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1366 pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1367 }
1368 }
1369
1370 /* Processor-based VM-execution controls. */
1371 {
1372 uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1373 | (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1374 | (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1375 | (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1376 | (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1377 | (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1378 | (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1379 | (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1380 | (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1381 | (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1382 | (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1383 | (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1384 | (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1385 | (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1386 | (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1387 | (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1388 | (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1389 | (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1390 | (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1391 | (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1392 | (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1393 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1394 uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1395 uint32_t const fAllowed1 = fFeatures | VMX_PROC_CTLS_DEFAULT1;
1396 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1397 fAllowed1, fFeatures));
1398 pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1399
1400 /* True processor-based VM-execution controls. */
1401 if (fTrueVmxMsrs)
1402 {
1403 /* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1404 uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1405 | VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1406 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1407 pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1408 }
1409 }
1410
1411 /* Secondary processor-based VM-execution controls. */
1412 if (pGuestFeatures->fVmxSecondaryExecCtls)
1413 {
1414 uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1415 | (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1416 | (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1417 | (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1418 | (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1419 | (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1420 | (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1421 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1422 | (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1423 | (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1424 | (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1425 | (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1426 | (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1427 | (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1428 | (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1429 | (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1430 | (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1431 | (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1432 | (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1433 | (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1434 | (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1435 | (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1436 | (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1437 | (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1438 | (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1439 | (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1440 uint32_t const fAllowed0 = 0;
1441 uint32_t const fAllowed1 = fFeatures;
1442 pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1443 }
1444
1445 /* Tertiary processor-based VM-execution controls. */
1446 if (pGuestFeatures->fVmxTertiaryExecCtls)
1447 {
1448 pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1449 }
1450
1451 /* VM-exit controls. */
1452 {
1453 uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1454 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1455 | (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1456 | (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1457 | (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1458 | (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1459 | (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1460 | (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1461 | (pGuestFeatures->fVmxSecondaryExitCtls << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1462 /* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1463 uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1464 uint32_t const fAllowed1 = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
1465 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1466 fAllowed1, fFeatures));
1467 pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1468
1469 /* True VM-exit controls. */
1470 if (fTrueVmxMsrs)
1471 {
1472 /* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1473 uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1474 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1475 pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1476 }
1477 }
1478
1479 /* VM-entry controls. */
1480 {
1481 uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1482 | (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1483 | (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1484 | (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1485 uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1486 uint32_t const fAllowed1 = fFeatures | VMX_ENTRY_CTLS_DEFAULT1;
1487 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1488 fAllowed1, fFeatures));
1489 pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1490
1491 /* True VM-entry controls. */
1492 if (fTrueVmxMsrs)
1493 {
1494 /* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1495 uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1496 | VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1497 | VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1498 | VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1499 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1500 pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1501 }
1502 }
1503
1504 /* Miscellaneous data. */
1505 {
1506 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1507
1508 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1509 uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1510 pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1511 | RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1512 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1513 | RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1514 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1515 | RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1516 | RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1517 | RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1518 | RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1519 | RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1520 | RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1521 }
1522
1523 /* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1524 pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1525
1526 /* CR0 Fixed-1. */
1527 {
1528 /*
1529 * All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1530 * This is different from CR4 fixed-1 bits which are reported as per the
1531 * CPU features and/or micro-architecture/generation. Why? Ask Intel.
1532 */
1533 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1534 pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1535 }
1536
1537 /* CR4 Fixed-0. */
1538 pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1539
1540 /* CR4 Fixed-1. */
1541 {
1542 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1543 pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1544 }
1545
1546 /* VMCS Enumeration. */
1547 pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1548
1549 /* VPID and EPT Capabilities. */
1550 if (pGuestFeatures->fVmxEpt)
1551 {
1552 /*
1553 * INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1554 * and emulate any INVVPID flush type. However, it only makes sense to expose the types
1555 * when INVVPID instruction is supported just to be more compatible with guest
1556 * hypervisors that may make assumptions by only looking at this MSR even though they
1557 * are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1558 *
1559 * See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1560 * See Intel spec. 30.3 "VMX Instructions".
1561 */
1562 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1563 uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1564
1565 uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1566 uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1567 uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1568 uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1569 uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1570 uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1571 /** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1572 /* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1573 uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1574 uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1575 uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1576 uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1577 uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1578 uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1579 pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1580 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1581 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1582 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1583 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1584 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1585 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1586 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1587 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1588 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1589 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1590 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1591 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1592 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1593 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1594 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1595 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1596 }
1597
1598 /* VM Functions. */
1599 if (pGuestFeatures->fVmxVmFunc)
1600 pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1601}
1602
1603
1604/**
1605 * Checks whether the given guest CPU VMX features are compatible with the provided
1606 * base features.
1607 *
1608 * @returns @c true if compatible, @c false otherwise.
1609 * @param pVM The cross context VM structure.
1610 * @param pBase The base VMX CPU features.
1611 * @param pGst The guest VMX CPU features.
1612 *
1613 * @remarks Only VMX feature bits are examined.
1614 */
1615static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1616{
1617 if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1618 return false;
1619
1620#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1621#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1622 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1623 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1624 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1625 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1626 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1627 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1628 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1629 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1630 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1631 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1632 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1633 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1634 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1635 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1636 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1637 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1638 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1639 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1640 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1641 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1642 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1643 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1644 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1645 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1646 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1647 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1648 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1649 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1650 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1651 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1652 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1653 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1654 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1655 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1656 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1657 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1658 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1659 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1660 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1661 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1662 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1663 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1664 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1665 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1666 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1667 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1668 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1669 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1670 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1671 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1672 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1673 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1674 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1675 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1676 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1677 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1678 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1679 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1680 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1681 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1682 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1683 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1684
1685#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1686 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1687 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1688 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1689 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExitCtls , 4) \
1690 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 5) \
1691 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 6) \
1692 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 7) \
1693 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 8))
1694
1695 /* Check first set of feature bits. */
1696 {
1697 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1698 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1699 if ((fBase | fGst) != fBase)
1700 {
1701 uint64_t const fDiff = fBase ^ fGst;
1702 LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1703 fBase, fGst, fDiff));
1704 return false;
1705 }
1706 }
1707
1708 /* Check second set of feature bits. */
1709 {
1710 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1711 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1712 if ((fBase | fGst) != fBase)
1713 {
1714 uint64_t const fDiff = fBase ^ fGst;
1715 LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1716 fBase, fGst, fDiff));
1717 return false;
1718 }
1719 }
1720#undef CPUM_VMX_FEAT_SHIFT
1721#undef CPUM_VMX_MAKE_FEATURES_1
1722#undef CPUM_VMX_MAKE_FEATURES_2
1723
1724 return true;
1725}
1726
1727
1728/**
1729 * Initializes VMX guest features and MSRs.
1730 *
1731 * @param pVM The cross context VM structure.
1732 * @param pCpumCfg The CPUM CFGM configuration node.
1733 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1734 * and no hardware-assisted nested-guest execution is
1735 * possible for this VM.
1736 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1737 */
1738void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1739{
1740 Assert(pVM);
1741 Assert(pCpumCfg);
1742 Assert(pGuestVmxMsrs);
1743
1744 /*
1745 * Query VMX features from CFGM.
1746 */
1747 bool fVmxPreemptTimer;
1748 bool fVmxEpt;
1749 bool fVmxUnrestrictedGuest;
1750 {
1751 /** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1752 * Whether to expose the VMX-preemption timer feature to the guest (if also
1753 * supported by the host hardware). When disabled will prevent exposing the
1754 * VMX-preemption timer feature to the guest even if the host supports it.
1755 *
1756 * @todo Currently disabled, see @bugref{9180#c108}.
1757 */
1758 int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1759 AssertLogRelRCReturnVoid(rc);
1760
1761#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1762 /** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1763 * Whether to expose the EPT feature to the guest. The default is true.
1764 * When disabled will automatically prevent exposing features that rely
1765 * on it. This is dependent upon nested paging being enabled for the VM.
1766 */
1767 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1768 AssertLogRelRCReturnVoid(rc);
1769
1770 /** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1771 * Whether to expose the Unrestricted Guest feature to the guest. The
1772 * default is the same a /CPUM/Nested/VmxEpt. When disabled will
1773 * automatically prevent exposing features that rely on it.
1774 */
1775 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1776 AssertLogRelRCReturnVoid(rc);
1777#else
1778 fVmxEpt = fVmxUnrestrictedGuest = false;
1779#endif
1780 }
1781
1782 if (fVmxEpt)
1783 {
1784 const char *pszWhy = NULL;
1785 if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1786 pszWhy = "execution engine is neither HM nor IEM";
1787 else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1788 pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1789 else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1790 pszWhy = "NX is not available on the host";
1791 if (pszWhy)
1792 {
1793 LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1794 fVmxEpt = false;
1795 }
1796 }
1797 else if (fVmxUnrestrictedGuest)
1798 {
1799 LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1800 fVmxUnrestrictedGuest = false;
1801 }
1802
1803 /*
1804 * Initialize the set of VMX features we emulate.
1805 *
1806 * Note! Some bits might be reported as 1 always if they fall under the
1807 * default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1808 */
1809 CPUMFEATURES EmuFeat;
1810 RT_ZERO(EmuFeat);
1811 EmuFeat.fVmx = 1;
1812 EmuFeat.fVmxInsOutInfo = 1;
1813 EmuFeat.fVmxExtIntExit = 1;
1814 EmuFeat.fVmxNmiExit = 1;
1815 EmuFeat.fVmxVirtNmi = 1;
1816 EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1817 EmuFeat.fVmxPostedInt = 0;
1818 EmuFeat.fVmxIntWindowExit = 1;
1819 EmuFeat.fVmxTscOffsetting = 1;
1820 EmuFeat.fVmxHltExit = 1;
1821 EmuFeat.fVmxInvlpgExit = 1;
1822 EmuFeat.fVmxMwaitExit = 1;
1823 EmuFeat.fVmxRdpmcExit = 1;
1824 EmuFeat.fVmxRdtscExit = 1;
1825 EmuFeat.fVmxCr3LoadExit = 1;
1826 EmuFeat.fVmxCr3StoreExit = 1;
1827 EmuFeat.fVmxTertiaryExecCtls = 0;
1828 EmuFeat.fVmxCr8LoadExit = 1;
1829 EmuFeat.fVmxCr8StoreExit = 1;
1830 EmuFeat.fVmxUseTprShadow = 1;
1831 EmuFeat.fVmxNmiWindowExit = 1;
1832 EmuFeat.fVmxMovDRxExit = 1;
1833 EmuFeat.fVmxUncondIoExit = 1;
1834 EmuFeat.fVmxUseIoBitmaps = 1;
1835 EmuFeat.fVmxMonitorTrapFlag = 0;
1836 EmuFeat.fVmxUseMsrBitmaps = 1;
1837 EmuFeat.fVmxMonitorExit = 1;
1838 EmuFeat.fVmxPauseExit = 1;
1839 EmuFeat.fVmxSecondaryExecCtls = 1;
1840 EmuFeat.fVmxVirtApicAccess = 1;
1841 EmuFeat.fVmxEpt = fVmxEpt;
1842 EmuFeat.fVmxDescTableExit = 1;
1843 EmuFeat.fVmxRdtscp = 1;
1844 EmuFeat.fVmxVirtX2ApicMode = 0;
1845 EmuFeat.fVmxVpid = 1;
1846 EmuFeat.fVmxWbinvdExit = 1;
1847 EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1848 EmuFeat.fVmxApicRegVirt = 0;
1849 EmuFeat.fVmxVirtIntDelivery = 0;
1850 EmuFeat.fVmxPauseLoopExit = 1;
1851 EmuFeat.fVmxRdrandExit = 0;
1852 EmuFeat.fVmxInvpcid = 1;
1853 EmuFeat.fVmxVmFunc = 0;
1854 EmuFeat.fVmxVmcsShadowing = 0;
1855 EmuFeat.fVmxRdseedExit = 0;
1856 EmuFeat.fVmxPml = 0;
1857 EmuFeat.fVmxEptXcptVe = 0;
1858 EmuFeat.fVmxConcealVmxFromPt = 0;
1859 EmuFeat.fVmxXsavesXrstors = 0;
1860 EmuFeat.fVmxModeBasedExecuteEpt = 0;
1861 EmuFeat.fVmxSppEpt = 0;
1862 EmuFeat.fVmxPtEpt = 0;
1863 EmuFeat.fVmxUseTscScaling = 0;
1864 EmuFeat.fVmxUserWaitPause = 0;
1865 EmuFeat.fVmxEnclvExit = 0;
1866 EmuFeat.fVmxLoadIwKeyExit = 0;
1867 EmuFeat.fVmxEntryLoadDebugCtls = 1;
1868 EmuFeat.fVmxIa32eModeGuest = 1;
1869 EmuFeat.fVmxEntryLoadEferMsr = 1;
1870 EmuFeat.fVmxEntryLoadPatMsr = 1;
1871 EmuFeat.fVmxExitSaveDebugCtls = 1;
1872 EmuFeat.fVmxHostAddrSpaceSize = 1;
1873 EmuFeat.fVmxExitAckExtInt = 1;
1874 EmuFeat.fVmxExitSavePatMsr = 0;
1875 EmuFeat.fVmxExitLoadPatMsr = 1;
1876 EmuFeat.fVmxExitSaveEferMsr = 1;
1877 EmuFeat.fVmxExitLoadEferMsr = 1;
1878 EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1879 EmuFeat.fVmxSecondaryExitCtls = 0;
1880 EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1881 EmuFeat.fVmxPt = 0;
1882 EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1883 EmuFeat.fVmxEntryInjectSoftInt = 1;
1884
1885 /*
1886 * Merge guest features.
1887 *
1888 * When hardware-assisted VMX may be used, any feature we emulate must also be supported
1889 * by the hardware, hence we merge our emulated features with the host features below.
1890 */
1891 PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1892 PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1893 Assert(pBaseFeat->fVmx);
1894 pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1895 pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1896 pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1897 pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1898 pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1899 pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1900 pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1901 pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1902 pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1903 pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1904 pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1905 pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1906 pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1907 pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1908 pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1909 pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1910 pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1911 pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1912 pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1913 pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1914 pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1915 pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1916 pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1917 pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1918 pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1919 pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1920 pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1921 pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1922 pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1923 pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1924 pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1925 pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1926 pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1927 pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1928 pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1929 pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1930 pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1931 pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1932 pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1933 pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1934 pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1935 pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1936 pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1937 pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1938 pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1939 pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1940 pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1941 pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1942 pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1943 pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1944 pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1945 pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1946 pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1947 pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1948 pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1949 pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1950 pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1951 pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1952 pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1953 pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1954 pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1955 pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1956 pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1957 pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1958 pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1959 pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1960 pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1961 pGuestFeat->fVmxSecondaryExitCtls = (pBaseFeat->fVmxSecondaryExitCtls & EmuFeat.fVmxSecondaryExitCtls );
1962 pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1963 pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1964 pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1965 pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1966
1967#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
1968 /* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1969 if ( pGuestFeat->fVmxPreemptTimer
1970 && HMIsSubjectToVmxPreemptTimerErratum())
1971 {
1972 LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
1973 pGuestFeat->fVmxPreemptTimer = 0;
1974 pGuestFeat->fVmxSavePreemptTimer = 0;
1975 }
1976#endif
1977
1978 /* Sanity checking. */
1979 if (!pGuestFeat->fVmxSecondaryExecCtls)
1980 {
1981 Assert(!pGuestFeat->fVmxVirtApicAccess);
1982 Assert(!pGuestFeat->fVmxEpt);
1983 Assert(!pGuestFeat->fVmxDescTableExit);
1984 Assert(!pGuestFeat->fVmxRdtscp);
1985 Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1986 Assert(!pGuestFeat->fVmxVpid);
1987 Assert(!pGuestFeat->fVmxWbinvdExit);
1988 Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1989 Assert(!pGuestFeat->fVmxApicRegVirt);
1990 Assert(!pGuestFeat->fVmxVirtIntDelivery);
1991 Assert(!pGuestFeat->fVmxPauseLoopExit);
1992 Assert(!pGuestFeat->fVmxRdrandExit);
1993 Assert(!pGuestFeat->fVmxInvpcid);
1994 Assert(!pGuestFeat->fVmxVmFunc);
1995 Assert(!pGuestFeat->fVmxVmcsShadowing);
1996 Assert(!pGuestFeat->fVmxRdseedExit);
1997 Assert(!pGuestFeat->fVmxPml);
1998 Assert(!pGuestFeat->fVmxEptXcptVe);
1999 Assert(!pGuestFeat->fVmxConcealVmxFromPt);
2000 Assert(!pGuestFeat->fVmxXsavesXrstors);
2001 Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
2002 Assert(!pGuestFeat->fVmxSppEpt);
2003 Assert(!pGuestFeat->fVmxPtEpt);
2004 Assert(!pGuestFeat->fVmxUseTscScaling);
2005 Assert(!pGuestFeat->fVmxUserWaitPause);
2006 Assert(!pGuestFeat->fVmxEnclvExit);
2007 }
2008 else if (pGuestFeat->fVmxUnrestrictedGuest)
2009 {
2010 /* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2011 Assert(pGuestFeat->fVmxExitSaveEferLma);
2012 /* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2013 Assert(pGuestFeat->fVmxEpt);
2014 }
2015
2016 if (!pGuestFeat->fVmxTertiaryExecCtls)
2017 Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2018
2019 /*
2020 * Finally initialize the VMX guest MSRs.
2021 */
2022 cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2023}
2024
2025
2026/**
2027 * Gets the host hardware-virtualization MSRs.
2028 *
2029 * @returns VBox status code.
2030 * @param pMsrs Where to store the MSRs.
2031 */
2032static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2033{
2034 Assert(pMsrs);
2035
2036 uint32_t fCaps = 0;
2037 int rc = SUPR3QueryVTCaps(&fCaps);
2038 if (RT_SUCCESS(rc))
2039 {
2040 if (fCaps & (SUPVTCAPS_VT_X | SUPVTCAPS_AMD_V))
2041 {
2042 SUPHWVIRTMSRS HwvirtMsrs;
2043 rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2044 if (RT_SUCCESS(rc))
2045 {
2046 if (fCaps & SUPVTCAPS_VT_X)
2047 HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2048 else
2049 HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2050 return VINF_SUCCESS;
2051 }
2052
2053 LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2054 return rc;
2055 }
2056
2057 LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2058 return VERR_INTERNAL_ERROR_5;
2059 }
2060
2061 LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2062 return VINF_SUCCESS;
2063}
2064
2065
2066/**
2067 * @callback_method_impl{FNTMTIMERINT,
2068 * Callback that fires when the nested VMX-preemption timer expired.}
2069 */
2070static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2071{
2072 RT_NOREF(pVM, hTimer);
2073 PVMCPU pVCpu = (PVMCPUR3)pvUser;
2074 AssertPtr(pVCpu);
2075 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2076}
2077
2078
2079/**
2080 * Initializes the CPUM.
2081 *
2082 * @returns VBox status code.
2083 * @param pVM The cross context VM structure.
2084 */
2085VMMR3DECL(int) CPUMR3Init(PVM pVM)
2086{
2087 LogFlow(("CPUMR3Init\n"));
2088
2089 /*
2090 * Assert alignment, sizes and tables.
2091 */
2092 AssertCompileMemberAlignment(VM, cpum.s, 32);
2093 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2094 AssertCompileSizeAlignment(CPUMCTX, 64);
2095 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2096 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2097 AssertCompileMemberAlignment(VM, cpum, 64);
2098 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2099#ifdef VBOX_STRICT
2100 int rc2 = cpumR3MsrStrictInitChecks();
2101 AssertRCReturn(rc2, rc2);
2102#endif
2103
2104 /*
2105 * Gather info about the host CPU.
2106 */
2107#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2108 if (!ASMHasCpuId())
2109 {
2110 LogRel(("The CPU doesn't support CPUID!\n"));
2111 return VERR_UNSUPPORTED_CPU;
2112 }
2113
2114 pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2115#endif
2116
2117 CPUMMSRS HostMsrs;
2118 RT_ZERO(HostMsrs);
2119 int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2120 AssertLogRelRCReturn(rc, rc);
2121
2122#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2123 /* Use the host features detected by CPUMR0ModuleInit if available. */
2124 if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2125 g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2126 else
2127 {
2128 PCPUMCPUIDLEAF paLeaves;
2129 uint32_t cLeaves;
2130 rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2131 AssertLogRelRCReturn(rc, rc);
2132
2133 rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2134 RTMemFree(paLeaves);
2135 AssertLogRelRCReturn(rc, rc);
2136 }
2137 pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2138 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2139#endif
2140
2141 /*
2142 * Check that the CPU supports the minimum features we require.
2143 */
2144#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
2145 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2146 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2147 if (!pVM->cpum.s.HostFeatures.fMmx)
2148 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2149 if (!pVM->cpum.s.HostFeatures.fTsc)
2150 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2151#endif
2152
2153 /*
2154 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
2155 */
2156 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
2157 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2158
2159 /*
2160 * Figure out which XSAVE/XRSTOR features are available on the host.
2161 */
2162 uint64_t fXcr0Host = 0;
2163 uint64_t fXStateHostMask = 0;
2164#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2165 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2166 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2167 {
2168 fXStateHostMask = fXcr0Host = ASMGetXcr0();
2169 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
2170 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
2171 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2172 }
2173#endif
2174 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2175 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2176 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2177
2178 /*
2179 * Initialize the host XSAVE/XRSTOR mask.
2180 */
2181#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2182 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2183 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2184 AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2185 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2186 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2187 , VERR_CPUM_IPE_2);
2188#endif
2189
2190 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2191 {
2192 PVMCPU pVCpu = pVM->apCpusR3[i];
2193
2194 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2195 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2196 }
2197
2198 /*
2199 * Register saved state data item.
2200 */
2201 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2202 NULL, cpumR3LiveExec, NULL,
2203 NULL, cpumR3SaveExec, NULL,
2204 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2205 if (RT_FAILURE(rc))
2206 return rc;
2207
2208 /*
2209 * Register info handlers and registers with the debugger facility.
2210 */
2211 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2212 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2213 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2214 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2215 DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2216 &cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2217 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2218 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2219 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2220 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2221 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2222 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2223 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2224 &cpumR3CpuIdInfo);
2225 DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2226 &cpumR3InfoVmxFeatures);
2227
2228 rc = cpumR3DbgInit(pVM);
2229 if (RT_FAILURE(rc))
2230 return rc;
2231
2232#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2233 /*
2234 * Check if we need to workaround partial/leaky FPU handling.
2235 */
2236 cpumR3CheckLeakyFpu(pVM);
2237#endif
2238
2239 /*
2240 * Initialize the Guest CPUID and MSR states.
2241 */
2242 rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2243 if (RT_FAILURE(rc))
2244 return rc;
2245
2246 /*
2247 * Generate the RFLAGS cookie.
2248 */
2249 pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64);
2250
2251 /*
2252 * Init the VMX/SVM state.
2253 *
2254 * This must be done after initializing CPUID/MSR features as we access the
2255 * the VMX/SVM guest features below.
2256 *
2257 * In the case of nested VT-x, we also need to create the per-VCPU
2258 * VMX preemption timers.
2259 */
2260 if (pVM->cpum.s.GuestFeatures.fVmx)
2261 cpumR3InitVmxHwVirtState(pVM);
2262 else if (pVM->cpum.s.GuestFeatures.fSvm)
2263 cpumR3InitSvmHwVirtState(pVM);
2264 else
2265 Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2266
2267 /*
2268 * Initialize the general guest CPU state.
2269 */
2270 CPUMR3Reset(pVM);
2271
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/**
2277 * Applies relocations to data and code managed by this
2278 * component. This function will be called at init and
2279 * whenever the VMM need to relocate it self inside the GC.
2280 *
2281 * The CPUM will update the addresses used by the switcher.
2282 *
2283 * @param pVM The cross context VM structure.
2284 */
2285VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2286{
2287 RT_NOREF(pVM);
2288}
2289
2290
2291/**
2292 * Terminates the CPUM.
2293 *
2294 * Termination means cleaning up and freeing all resources,
2295 * the VM it self is at this point powered off or suspended.
2296 *
2297 * @returns VBox status code.
2298 * @param pVM The cross context VM structure.
2299 */
2300VMMR3DECL(int) CPUMR3Term(PVM pVM)
2301{
2302#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2303 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2304 {
2305 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2306 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2307 pVCpu->cpum.s.uMagic = 0;
2308 pvCpu->cpum.s.Guest.dr[5] = 0;
2309 }
2310#endif
2311
2312 if (pVM->cpum.s.GuestFeatures.fVmx)
2313 {
2314 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2315 {
2316 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2317 if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2318 {
2319 int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2320 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2321 }
2322 }
2323 }
2324 return VINF_SUCCESS;
2325}
2326
2327
2328/**
2329 * Resets a virtual CPU.
2330 *
2331 * Used by CPUMR3Reset and CPU hot plugging.
2332 *
2333 * @param pVM The cross context VM structure.
2334 * @param pVCpu The cross context virtual CPU structure of the CPU that is
2335 * being reset. This may differ from the current EMT.
2336 */
2337VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2338{
2339 /** @todo anything different for VCPU > 0? */
2340 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2341
2342 /*
2343 * Initialize everything to ZERO first.
2344 */
2345 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2346
2347 RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2348
2349 pVCpu->cpum.s.fUseFlags = fUseFlags;
2350
2351 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
2352 pCtx->eip = 0x0000fff0;
2353 pCtx->edx = 0x00000600; /* P6 processor */
2354
2355 Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK | X86_EFL_RAZ_LO_MASK | X86_EFL_RA1_MASK)) == 0);
2356 pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie | X86_EFL_RA1_MASK;
2357
2358 pCtx->cs.Sel = 0xf000;
2359 pCtx->cs.ValidSel = 0xf000;
2360 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2361 pCtx->cs.u64Base = UINT64_C(0xffff0000);
2362 pCtx->cs.u32Limit = 0x0000ffff;
2363 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2364 pCtx->cs.Attr.n.u1Present = 1;
2365 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2366
2367 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2368 pCtx->ds.u32Limit = 0x0000ffff;
2369 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2370 pCtx->ds.Attr.n.u1Present = 1;
2371 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2372
2373 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2374 pCtx->es.u32Limit = 0x0000ffff;
2375 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2376 pCtx->es.Attr.n.u1Present = 1;
2377 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2378
2379 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2380 pCtx->fs.u32Limit = 0x0000ffff;
2381 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2382 pCtx->fs.Attr.n.u1Present = 1;
2383 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2384
2385 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2386 pCtx->gs.u32Limit = 0x0000ffff;
2387 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2388 pCtx->gs.Attr.n.u1Present = 1;
2389 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2390
2391 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2392 pCtx->ss.u32Limit = 0x0000ffff;
2393 pCtx->ss.Attr.n.u1Present = 1;
2394 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2395 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2396
2397 pCtx->idtr.cbIdt = 0xffff;
2398 pCtx->gdtr.cbGdt = 0xffff;
2399
2400 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2401 pCtx->ldtr.u32Limit = 0xffff;
2402 pCtx->ldtr.Attr.n.u1Present = 1;
2403 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2404
2405 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2406 pCtx->tr.u32Limit = 0xffff;
2407 pCtx->tr.Attr.n.u1Present = 1;
2408 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2409
2410 pCtx->dr[6] = X86_DR6_INIT_VAL;
2411 pCtx->dr[7] = X86_DR7_INIT_VAL;
2412
2413 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2414 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2415 pFpuCtx->FCW = 0x37f;
2416
2417 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2418 IA-32 Processor States Following Power-up, Reset, or INIT */
2419 pFpuCtx->MXCSR = 0x1F80;
2420 pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2421
2422 pCtx->aXcr[0] = XSAVE_C_X87;
2423 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2424 {
2425 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2426 as we don't know what happened before. (Bother optimize later?) */
2427 pCtx->XState.Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
2428 }
2429
2430 /*
2431 * MSRs.
2432 */
2433 /* Init PAT MSR */
2434 pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2435
2436 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2437 * The Intel docs don't mention it. */
2438 Assert(!pCtx->msrEFER);
2439
2440 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2441 is supposed to be here, just trying provide useful/sensible values. */
2442 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2443 if (pRange)
2444 {
2445 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2446 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2447 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2448 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2449 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2450 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2451 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2452 }
2453
2454 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2455
2456 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2457 * called from each EMT while we're getting called by CPUMR3Reset()
2458 * iteratively on the same thread. Fix later. */
2459#if 0 /** @todo r=bird: This we will do in TM, not here. */
2460 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2461 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2462#endif
2463
2464
2465 /* C-state control. Guesses. */
2466 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
2467 /* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2468 * it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2469 * functionality. The default value must be different due to incompatible write mask.
2470 */
2471 if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2472 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2473 else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2474 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2475
2476 /*
2477 * Hardware virtualization state.
2478 */
2479 CPUMSetGuestGif(pCtx, true);
2480 Assert(!pVM->cpum.s.GuestFeatures.fVmx || !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2481 if (pVM->cpum.s.GuestFeatures.fVmx)
2482 cpumR3ResetVmxHwVirtState(pVCpu);
2483 else if (pVM->cpum.s.GuestFeatures.fSvm)
2484 cpumR3ResetSvmHwVirtState(pVCpu);
2485}
2486
2487
2488/**
2489 * Resets the CPU.
2490 *
2491 * @returns VINF_SUCCESS.
2492 * @param pVM The cross context VM structure.
2493 */
2494VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2495{
2496 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2497 {
2498 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2499 CPUMR3ResetCpu(pVM, pVCpu);
2500
2501#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2502
2503 /* Magic marker for searching in crash dumps. */
2504 strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2505 pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2506 pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2507#endif
2508 }
2509}
2510
2511
2512
2513
2514/**
2515 * Pass 0 live exec callback.
2516 *
2517 * @returns VINF_SSM_DONT_CALL_AGAIN.
2518 * @param pVM The cross context VM structure.
2519 * @param pSSM The saved state handle.
2520 * @param uPass The pass (0).
2521 */
2522static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2523{
2524 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2525 cpumR3SaveCpuId(pVM, pSSM);
2526 return VINF_SSM_DONT_CALL_AGAIN;
2527}
2528
2529
2530/**
2531 * Execute state save operation.
2532 *
2533 * @returns VBox status code.
2534 * @param pVM The cross context VM structure.
2535 * @param pSSM SSM operation handle.
2536 */
2537static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2538{
2539 /*
2540 * Save.
2541 */
2542 SSMR3PutU32(pSSM, pVM->cCpus);
2543 SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2544 CPUMCTX DummyHyperCtx;
2545 RT_ZERO(DummyHyperCtx);
2546 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2547 {
2548 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2549 PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2550
2551 /** @todo ditch this the next time we change the saved state. */
2552 SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2553
2554 uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2555 pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2556 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2557 pGstCtx->rflags.uBoth = fSavedRFlags;
2558
2559 SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2560 if (pGstCtx->fXStateMask != 0)
2561 SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2562 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2563 {
2564 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2565 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2566 }
2567 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2568 {
2569 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2570 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2571 }
2572 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2573 {
2574 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2575 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2576 }
2577 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2578 {
2579 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2580 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2581 }
2582 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2583 {
2584 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2585 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2586 }
2587 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2588 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2589 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2590 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2591 if (pVM->cpum.s.GuestFeatures.fSvm)
2592 {
2593 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2594 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2595 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2596 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2597 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2598 SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2599 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2600 g_aSvmHwvirtHostState, NULL /* pvUser */);
2601 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2602 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2603 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2604 /* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2605 SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2606 SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2607 }
2608 if (pVM->cpum.s.GuestFeatures.fVmx)
2609 {
2610 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2611 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2612 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2613 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2614 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2615 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2616 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2617 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2618 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2619 0, g_aVmxHwvirtVmcs, NULL);
2620 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2621 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2622 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2623 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2624 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2625 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2626 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2627 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2628 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2629 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2630 SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2631 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2632 SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2633 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2634 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2635 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2636 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2637 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2638 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2639 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2640 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2641 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2642 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2643 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2644 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2645 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2646 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2647 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2648 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2649 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2650 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2651 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2652 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2653 }
2654 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2655 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2656 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2657 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2658 }
2659
2660 cpumR3SaveCpuId(pVM, pSSM);
2661 return VINF_SUCCESS;
2662}
2663
2664
2665/**
2666 * @callback_method_impl{FNSSMINTLOADPREP}
2667 */
2668static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2669{
2670 NOREF(pSSM);
2671 pVM->cpum.s.fPendingRestore = true;
2672 return VINF_SUCCESS;
2673}
2674
2675
2676/**
2677 * @callback_method_impl{FNSSMINTLOADEXEC}
2678 */
2679static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2680{
2681 int rc; /* Only for AssertRCReturn use. */
2682
2683 /*
2684 * Validate version.
2685 */
2686 if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2687 && uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2688 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2689 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2690 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2691 && uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2692 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2693 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2694 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2695 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2696 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2697 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2698 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2699 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2700 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2701 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2702 {
2703 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2704 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2705 }
2706
2707 if (uPass == SSM_PASS_FINAL)
2708 {
2709 /*
2710 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2711 * really old SSM file versions.)
2712 */
2713 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2714 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2715 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2716 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2717
2718 /*
2719 * Figure x86 and ctx field definitions to use for older states.
2720 */
2721 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2722 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2723 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2724 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2725 {
2726 paCpumCtx1Fields = g_aCpumX87FieldsV16;
2727 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2728 }
2729 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2730 {
2731 paCpumCtx1Fields = g_aCpumX87FieldsMem;
2732 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2733 }
2734
2735 /*
2736 * The hyper state used to preceed the CPU count. Starting with
2737 * XSAVE it was moved down till after we've got the count.
2738 */
2739 CPUMCTX HyperCtxIgnored;
2740 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2741 {
2742 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2743 {
2744 X86FXSTATE Ign;
2745 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2746 SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2747 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2748 }
2749 }
2750
2751 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2752 {
2753 uint32_t cCpus;
2754 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2755 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2756 VERR_SSM_UNEXPECTED_DATA);
2757 }
2758 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2759 || pVM->cCpus == 1,
2760 ("cCpus=%u\n", pVM->cCpus),
2761 VERR_SSM_UNEXPECTED_DATA);
2762
2763 uint32_t cbMsrs = 0;
2764 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2765 {
2766 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2767 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2768 VERR_SSM_UNEXPECTED_DATA);
2769 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2770 VERR_SSM_UNEXPECTED_DATA);
2771 }
2772
2773 /*
2774 * Do the per-CPU restoring.
2775 */
2776 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2777 {
2778 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2779 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2780
2781 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2782 {
2783 /*
2784 * The XSAVE saved state layout moved the hyper state down here.
2785 */
2786 rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2787 AssertRCReturn(rc, rc);
2788
2789 /*
2790 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2791 */
2792 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2793 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2794 AssertRCReturn(rc, rc);
2795
2796 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2797 if (pGstCtx->fXStateMask != 0)
2798 {
2799 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2800 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2801 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2802 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2803 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2804 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2805 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2806 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2807 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2808 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2809 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2810 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2811 }
2812
2813 /* Check that the XCR0 mask is valid (invalid results in #GP). */
2814 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2815 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2816 {
2817 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
2818 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2819 VERR_CPUM_INVALID_XCR0);
2820 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2821 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2822 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2823 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2824 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2825 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2826 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2827 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2828 }
2829
2830 /* Check that the XCR1 is zero, as we don't implement it yet. */
2831 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2832
2833 /*
2834 * Restore the individual extended state components we support.
2835 */
2836 if (pGstCtx->fXStateMask != 0)
2837 {
2838 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2839 0, g_aCpumXSaveHdrFields, NULL);
2840 AssertRCReturn(rc, rc);
2841 AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2842 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
2843 pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2844 VERR_CPUM_INVALID_XSAVE_HDR);
2845 }
2846 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2847 {
2848 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2849 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2850 }
2851 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2852 {
2853 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2854 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2855 }
2856 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2857 {
2858 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2859 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2860 }
2861 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2862 {
2863 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2864 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2865 }
2866 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2867 {
2868 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2869 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2870 }
2871 if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2872 {
2873 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2874 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2875 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2876 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2877 }
2878 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2879 {
2880 if (pVM->cpum.s.GuestFeatures.fSvm)
2881 {
2882 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2883 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2884 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2885 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2886 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2887 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2888 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2889 0 /* fFlags */, g_aSvmHwvirtHostState, NULL /* pvUser */);
2890 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2891 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2892 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2893
2894 uint32_t fSavedLocalFFs = 0;
2895 rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2896 AssertRCReturn(rc, rc);
2897 Assert(fSavedLocalFFs == 0 || fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2898 pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2899
2900 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2901 }
2902 }
2903 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2904 {
2905 if (pVM->cpum.s.GuestFeatures.fVmx)
2906 {
2907 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2908 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2909 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2910 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2911 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2912 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2913 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2914 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2915 0, g_aVmxHwvirtVmcs, NULL);
2916 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2917 0, g_aVmxHwvirtVmcs, NULL);
2918 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2919 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2920 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2921 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2922 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2923 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2924 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2925 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2926 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2927 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2928 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2929 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2930 SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2931 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2932 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2933 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2934 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2935 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2936 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2937 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2938 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2939 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2940 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2941 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2942 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2943 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2944 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2945 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2946 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2947 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2948 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2949 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2950 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2951 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
2952 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2953 }
2954 }
2955 }
2956 else
2957 {
2958 /*
2959 * Pre XSAVE saved state.
2960 */
2961 SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2962 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2963 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2964 }
2965
2966 /*
2967 * Restore a couple of flags and the MSRs.
2968 */
2969 uint32_t fIgnoredUsedFlags = 0;
2970 rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2971 AssertRCReturn(rc, rc);
2972 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2973
2974 rc = VINF_SUCCESS;
2975 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2976 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2977 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2978 {
2979 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2980 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2981 }
2982 AssertRCReturn(rc, rc);
2983
2984 /* Deal with the reusing of reserved RFLAGS bits. */
2985 pGstCtx->rflags.uBoth |= pVM->cpum.s.fReservedRFlagsCookie;
2986
2987 /* REM and other may have cleared must-be-one fields in DR6 and
2988 DR7, fix these. */
2989 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2990 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
2991 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2992 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
2993 }
2994
2995 /* Older states does not have the internal selector register flags
2996 and valid selector value. Supply those. */
2997 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2998 {
2999 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3000 {
3001 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3002 bool const fValid = true /*!VM_IS_RAW_MODE_ENABLED(pVM)*/
3003 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3004 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3005 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3006 if (fValid)
3007 {
3008 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3009 {
3010 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3011 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3012 }
3013
3014 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3015 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3016 }
3017 else
3018 {
3019 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3020 {
3021 paSelReg[iSelReg].fFlags = 0;
3022 paSelReg[iSelReg].ValidSel = 0;
3023 }
3024
3025 /* This might not be 104% correct, but I think it's close
3026 enough for all practical purposes... (REM always loaded
3027 LDTR registers.) */
3028 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3029 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3030 }
3031 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3032 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3033 }
3034 }
3035
3036 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3037 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3038 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3039 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3040 {
3041 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3042 pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3043 }
3044
3045 /*
3046 * A quick sanity check.
3047 */
3048 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3049 {
3050 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3051 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3052 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3053 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3054 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3055 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3056 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3057 }
3058 }
3059
3060 pVM->cpum.s.fPendingRestore = false;
3061
3062 /*
3063 * Guest CPUIDs (and VMX MSR features).
3064 */
3065 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3066 {
3067 CPUMMSRS GuestMsrs;
3068 RT_ZERO(GuestMsrs);
3069
3070 CPUMFEATURES BaseFeatures;
3071 bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3072 if (fVmxGstFeat)
3073 {
3074 /*
3075 * At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3076 * However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3077 * here so we can compare them for compatibility after exploding guest features.
3078 */
3079 BaseFeatures = pVM->cpum.s.GuestFeatures;
3080
3081 /* Use the VMX MSR features from the saved state while exploding guest features. */
3082 GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3083 }
3084
3085 /* Load CPUID and explode guest features. */
3086 rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3087 if (fVmxGstFeat)
3088 {
3089 /*
3090 * Check if the exploded VMX features from the saved state are compatible with the host-derived features
3091 * we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3092 * VMX features presented to the guest.
3093 */
3094 bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3095 if (!fIsCompat)
3096 return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3097 }
3098 return rc;
3099 }
3100 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3101}
3102
3103
3104/**
3105 * @callback_method_impl{FNSSMINTLOADDONE}
3106 */
3107static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3108{
3109 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3110 return VINF_SUCCESS;
3111
3112 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3113 if (pVM->cpum.s.fPendingRestore)
3114 {
3115 LogRel(("CPUM: Missing state!\n"));
3116 return VERR_INTERNAL_ERROR_2;
3117 }
3118
3119 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3120 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3121 {
3122 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3123
3124 /* Notify PGM of the NXE states in case they've changed. */
3125 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3126
3127 /* During init. this is done in CPUMR3InitCompleted(). */
3128 if (fSupportsLongMode)
3129 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
3130
3131 /* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3132 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3133 }
3134 return VINF_SUCCESS;
3135}
3136
3137
3138/**
3139 * Checks if the CPUM state restore is still pending.
3140 *
3141 * @returns true / false.
3142 * @param pVM The cross context VM structure.
3143 */
3144VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3145{
3146 return pVM->cpum.s.fPendingRestore;
3147}
3148
3149
3150/**
3151 * Formats the EFLAGS value into mnemonics.
3152 *
3153 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3154 * @param efl The EFLAGS value with both guest hardware and VBox
3155 * internal bits included.
3156 */
3157static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3158{
3159 /*
3160 * Format the flags.
3161 */
3162 static const struct
3163 {
3164 const char *pszSet; const char *pszClear; uint32_t fFlag;
3165 } s_aFlags[] =
3166 {
3167 { "vip",NULL, X86_EFL_VIP },
3168 { "vif",NULL, X86_EFL_VIF },
3169 { "ac", NULL, X86_EFL_AC },
3170 { "vm", NULL, X86_EFL_VM },
3171 { "rf", NULL, X86_EFL_RF },
3172 { "nt", NULL, X86_EFL_NT },
3173 { "ov", "nv", X86_EFL_OF },
3174 { "dn", "up", X86_EFL_DF },
3175 { "ei", "di", X86_EFL_IF },
3176 { "tf", NULL, X86_EFL_TF },
3177 { "nt", "pl", X86_EFL_SF },
3178 { "nz", "zr", X86_EFL_ZF },
3179 { "ac", "na", X86_EFL_AF },
3180 { "po", "pe", X86_EFL_PF },
3181 { "cy", "nc", X86_EFL_CF },
3182 { "inh-ss", NULL, CPUMCTX_INHIBIT_SHADOW_SS },
3183 { "inh-sti", NULL, CPUMCTX_INHIBIT_SHADOW_STI },
3184 { "inh-nmi", NULL, CPUMCTX_INHIBIT_NMI },
3185 };
3186 char *psz = pszEFlags;
3187 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3188 {
3189 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3190 if (pszAdd)
3191 {
3192 strcpy(psz, pszAdd);
3193 psz += strlen(pszAdd);
3194 *psz++ = ' ';
3195 }
3196 }
3197 psz[-1] = '\0';
3198}
3199
3200
3201/**
3202 * Formats a full register dump.
3203 *
3204 * @param pVM The cross context VM structure.
3205 * @param pCtx The context to format.
3206 * @param pHlp Output functions.
3207 * @param enmType The dump type.
3208 * @param pszPrefix Register name prefix.
3209 */
3210static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
3211{
3212 NOREF(pVM);
3213
3214 /*
3215 * Format the EFLAGS.
3216 */
3217 char szEFlags[80];
3218 cpumR3InfoFormatFlags(&szEFlags[0], pCtx->eflags.uBoth);
3219
3220 /*
3221 * Format the registers.
3222 */
3223 uint32_t const efl = pCtx->eflags.u;
3224 switch (enmType)
3225 {
3226 case CPUMDUMPTYPE_TERSE:
3227 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3228 pHlp->pfnPrintf(pHlp,
3229 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3230 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3231 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3232 "%sr14=%016RX64 %sr15=%016RX64\n"
3233 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3234 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3235 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3236 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3237 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3238 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3239 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3240 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3241 else
3242 pHlp->pfnPrintf(pHlp,
3243 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3244 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3245 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3246 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3247 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3248 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3249 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3250 break;
3251
3252 case CPUMDUMPTYPE_DEFAULT:
3253 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3254 pHlp->pfnPrintf(pHlp,
3255 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3256 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3257 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3258 "%sr14=%016RX64 %sr15=%016RX64\n"
3259 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3260 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3261 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3262 ,
3263 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3264 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3265 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3266 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3267 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3268 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3269 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3270 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3271 else
3272 pHlp->pfnPrintf(pHlp,
3273 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3274 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3275 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3276 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3277 ,
3278 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3279 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3280 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3281 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3282 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3283 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3284 break;
3285
3286 case CPUMDUMPTYPE_VERBOSE:
3287 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3288 pHlp->pfnPrintf(pHlp,
3289 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3290 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3291 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3292 "%sr14=%016RX64 %sr15=%016RX64\n"
3293 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3294 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3295 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3296 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3297 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3298 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3299 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3300 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3301 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3302 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3303 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3304 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3305 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3306 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3307 ,
3308 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3309 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3310 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3311 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3312 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3313 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3314 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3315 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3316 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3317 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3318 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3319 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3320 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3321 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3322 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3323 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3324 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3325 else
3326 pHlp->pfnPrintf(pHlp,
3327 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3328 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3329 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3330 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3331 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3332 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3333 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3334 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3335 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3336 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3337 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3338 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3339 ,
3340 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3341 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3342 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3343 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3344 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3345 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3346 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3347 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3348 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3349 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3350 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3351 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3352
3353 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3354 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3355 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3356 {
3357 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3358 pHlp->pfnPrintf(pHlp,
3359 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3360 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3361 ,
3362 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3363 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3364 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3365 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3366 );
3367 /*
3368 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3369 * not (FP)R0-7 as Intel SDM suggests.
3370 */
3371 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3372 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3373 {
3374 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3375 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3376 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3377 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3378 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3379 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3380 iExponent -= 16383; /* subtract bias */
3381 /** @todo This isn't entirenly correct and needs more work! */
3382 pHlp->pfnPrintf(pHlp,
3383 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3384 pszPrefix, iST, pszPrefix, iFPR,
3385 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3386 uTag, chSign, iInteger, u64Fraction, iExponent);
3387 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
3388 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3389 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3390 else
3391 pHlp->pfnPrintf(pHlp, "\n");
3392 }
3393
3394 /* XMM/YMM/ZMM registers. */
3395 if (pCtx->fXStateMask & XSAVE_C_YMM)
3396 {
3397 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3398 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3399 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3400 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3401 pszPrefix, i, i < 10 ? " " : "",
3402 pYmmHiCtx->aYmmHi[i].au32[3],
3403 pYmmHiCtx->aYmmHi[i].au32[2],
3404 pYmmHiCtx->aYmmHi[i].au32[1],
3405 pYmmHiCtx->aYmmHi[i].au32[0],
3406 pFpuCtx->aXMM[i].au32[3],
3407 pFpuCtx->aXMM[i].au32[2],
3408 pFpuCtx->aXMM[i].au32[1],
3409 pFpuCtx->aXMM[i].au32[0]);
3410 else
3411 {
3412 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3413 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3414 pHlp->pfnPrintf(pHlp,
3415 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3416 pszPrefix, i, i < 10 ? " " : "",
3417 pZmmHi256->aHi256Regs[i].au32[7],
3418 pZmmHi256->aHi256Regs[i].au32[6],
3419 pZmmHi256->aHi256Regs[i].au32[5],
3420 pZmmHi256->aHi256Regs[i].au32[4],
3421 pZmmHi256->aHi256Regs[i].au32[3],
3422 pZmmHi256->aHi256Regs[i].au32[2],
3423 pZmmHi256->aHi256Regs[i].au32[1],
3424 pZmmHi256->aHi256Regs[i].au32[0],
3425 pYmmHiCtx->aYmmHi[i].au32[3],
3426 pYmmHiCtx->aYmmHi[i].au32[2],
3427 pYmmHiCtx->aYmmHi[i].au32[1],
3428 pYmmHiCtx->aYmmHi[i].au32[0],
3429 pFpuCtx->aXMM[i].au32[3],
3430 pFpuCtx->aXMM[i].au32[2],
3431 pFpuCtx->aXMM[i].au32[1],
3432 pFpuCtx->aXMM[i].au32[0]);
3433
3434 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3435 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3436 pHlp->pfnPrintf(pHlp,
3437 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3438 pszPrefix, i + 16,
3439 pZmm16Hi->aRegs[i].au32[15],
3440 pZmm16Hi->aRegs[i].au32[14],
3441 pZmm16Hi->aRegs[i].au32[13],
3442 pZmm16Hi->aRegs[i].au32[12],
3443 pZmm16Hi->aRegs[i].au32[11],
3444 pZmm16Hi->aRegs[i].au32[10],
3445 pZmm16Hi->aRegs[i].au32[9],
3446 pZmm16Hi->aRegs[i].au32[8],
3447 pZmm16Hi->aRegs[i].au32[7],
3448 pZmm16Hi->aRegs[i].au32[6],
3449 pZmm16Hi->aRegs[i].au32[5],
3450 pZmm16Hi->aRegs[i].au32[4],
3451 pZmm16Hi->aRegs[i].au32[3],
3452 pZmm16Hi->aRegs[i].au32[2],
3453 pZmm16Hi->aRegs[i].au32[1],
3454 pZmm16Hi->aRegs[i].au32[0]);
3455 }
3456 }
3457 else
3458 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3459 pHlp->pfnPrintf(pHlp,
3460 i & 1
3461 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3462 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3463 pszPrefix, i, i < 10 ? " " : "",
3464 pFpuCtx->aXMM[i].au32[3],
3465 pFpuCtx->aXMM[i].au32[2],
3466 pFpuCtx->aXMM[i].au32[1],
3467 pFpuCtx->aXMM[i].au32[0]);
3468
3469 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3470 {
3471 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3472 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3473 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3474 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3475 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3476 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3477 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3478 }
3479
3480 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3481 {
3482 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3483 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3484 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3485 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3486 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3487 }
3488
3489 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3490 {
3491 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3492 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3493 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3494 }
3495
3496 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3497 if (pFpuCtx->au32RsrvdRest[i])
3498 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3499 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3500 }
3501
3502 pHlp->pfnPrintf(pHlp,
3503 "%sEFER =%016RX64\n"
3504 "%sPAT =%016RX64\n"
3505 "%sSTAR =%016RX64\n"
3506 "%sCSTAR =%016RX64\n"
3507 "%sLSTAR =%016RX64\n"
3508 "%sSFMASK =%016RX64\n"
3509 "%sKERNELGSBASE =%016RX64\n",
3510 pszPrefix, pCtx->msrEFER,
3511 pszPrefix, pCtx->msrPAT,
3512 pszPrefix, pCtx->msrSTAR,
3513 pszPrefix, pCtx->msrCSTAR,
3514 pszPrefix, pCtx->msrLSTAR,
3515 pszPrefix, pCtx->msrSFMASK,
3516 pszPrefix, pCtx->msrKERNELGSBASE);
3517
3518 if (CPUMIsGuestInPAEModeEx(pCtx))
3519 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3520 pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3521 break;
3522 }
3523}
3524
3525
3526/**
3527 * Display all cpu states and any other cpum info.
3528 *
3529 * @param pVM The cross context VM structure.
3530 * @param pHlp The info helper functions.
3531 * @param pszArgs Arguments, ignored.
3532 */
3533static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3534{
3535 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3536 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3537 cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3538 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3539 cpumR3InfoHost(pVM, pHlp, pszArgs);
3540}
3541
3542
3543/**
3544 * Parses the info argument.
3545 *
3546 * The argument starts with 'verbose', 'terse' or 'default' and then
3547 * continues with the comment string.
3548 *
3549 * @param pszArgs The pointer to the argument string.
3550 * @param penmType Where to store the dump type request.
3551 * @param ppszComment Where to store the pointer to the comment string.
3552 */
3553static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3554{
3555 if (!pszArgs)
3556 {
3557 *penmType = CPUMDUMPTYPE_DEFAULT;
3558 *ppszComment = "";
3559 }
3560 else
3561 {
3562 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3563 {
3564 pszArgs += 7;
3565 *penmType = CPUMDUMPTYPE_VERBOSE;
3566 }
3567 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3568 {
3569 pszArgs += 5;
3570 *penmType = CPUMDUMPTYPE_TERSE;
3571 }
3572 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3573 {
3574 pszArgs += 7;
3575 *penmType = CPUMDUMPTYPE_DEFAULT;
3576 }
3577 else
3578 *penmType = CPUMDUMPTYPE_DEFAULT;
3579 *ppszComment = RTStrStripL(pszArgs);
3580 }
3581}
3582
3583
3584/**
3585 * Display the guest cpu state.
3586 *
3587 * @param pVM The cross context VM structure.
3588 * @param pHlp The info helper functions.
3589 * @param pszArgs Arguments.
3590 */
3591static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3592{
3593 CPUMDUMPTYPE enmType;
3594 const char *pszComment;
3595 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3596
3597 PVMCPU pVCpu = VMMGetCpu(pVM);
3598 if (!pVCpu)
3599 pVCpu = pVM->apCpusR3[0];
3600
3601 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3602
3603 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3604 cpumR3InfoOne(pVM, pCtx, pHlp, enmType, "");
3605}
3606
3607
3608/**
3609 * Displays an SVM VMCB control area.
3610 *
3611 * @param pHlp The info helper functions.
3612 * @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3613 * @param pszPrefix Caller specified string prefix.
3614 */
3615static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3616{
3617 AssertReturnVoid(pHlp);
3618 AssertReturnVoid(pVmcbCtrl);
3619
3620 pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3621 pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3622 pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3623 pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3624 pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3625 pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3626 pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3627 pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3628 pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3629 pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3630 pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3631 pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3632 pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3633 pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3634 pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3635 pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3636 pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3637 pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3638 pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3639 pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3640 pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3641 pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3642 pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3643 pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3644 pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3645 pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3646 pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3647 pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3648 pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3649 pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3650 pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3651 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3652 pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3653 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3654 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3655 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3656 pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3657 pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3658 pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3659 pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3660 pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3661 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3662 pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3663 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3664 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3665 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3666 pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3667 pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3668 pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3669 pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3670 pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3671 pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3672 pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3673 pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3674 pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3675 pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3676 pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3677 pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3678 pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3679 pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3680}
3681
3682
3683/**
3684 * Helper for dumping the SVM VMCB selector registers.
3685 *
3686 * @param pHlp The info helper functions.
3687 * @param pSel Pointer to the SVM selector register.
3688 * @param pszName Name of the selector.
3689 * @param pszPrefix Caller specified string prefix.
3690 */
3691DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char *pszName, const char *pszPrefix)
3692{
3693 /* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3694 pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3695 pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3696}
3697
3698
3699/**
3700 * Helper for dumping the SVM VMCB GDTR/IDTR registers.
3701 *
3702 * @param pHlp The info helper functions.
3703 * @param pXdtr Pointer to the descriptor table register.
3704 * @param pszName Name of the descriptor table register.
3705 * @param pszPrefix Caller specified string prefix.
3706 */
3707DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char *pszName, const char *pszPrefix)
3708{
3709 /* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3710 pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3711}
3712
3713
3714/**
3715 * Displays an SVM VMCB state-save area.
3716 *
3717 * @param pHlp The info helper functions.
3718 * @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3719 * @param pszPrefix Caller specified string prefix.
3720 */
3721static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3722{
3723 AssertReturnVoid(pHlp);
3724 AssertReturnVoid(pVmcbStateSave);
3725
3726 char szEFlags[80];
3727 cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3728
3729 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3730 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3731 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3732 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3733 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3734 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3735 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3736 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3737 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3738 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3739 pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3740 pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3741 pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3742 pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3743 pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3744 pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3745 pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3746 pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3747 pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3748 pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3749 pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3750 pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3751 pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3752 pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3753 pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3754 pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3755 pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3756 pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3757 pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3758 pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3759 pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3760 pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3761 pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3762 pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3763 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3764 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3765}
3766
3767
3768/**
3769 * Displays a virtual-VMCS.
3770 *
3771 * @param pVCpu The cross context virtual CPU structure.
3772 * @param pHlp The info helper functions.
3773 * @param pVmcs Pointer to a virtual VMCS.
3774 * @param pszPrefix Caller specified string prefix.
3775 */
3776static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3777{
3778 AssertReturnVoid(pHlp);
3779 AssertReturnVoid(pVmcs);
3780
3781 /* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3782#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3783 do { \
3784 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3785 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3786 } while (0)
3787
3788#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3789 do { \
3790 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3791 (a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3792 } while (0)
3793
3794#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3795 do { \
3796 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3797 (a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3798 (a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3799 } while (0)
3800
3801#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3802 do { \
3803 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3804 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3805 } while (0)
3806
3807 /* Header. */
3808 {
3809 pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3810 pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3811 pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3812 pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3813 }
3814
3815 /* Control fields. */
3816 {
3817 /* 16-bit. */
3818 pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3819 pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3820 pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3821 pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3822 pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
3823
3824 /* 32-bit. */
3825 pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3826 pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3827 pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3828 pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3829 pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3830 pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3831 pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3832 pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3833 pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3834 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3835 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3836 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3837 pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3838 {
3839 uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3840 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3841 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3842 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3843 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3844 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3845 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3846 }
3847 pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3848 pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3849 pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3850 pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3851 pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3852
3853 /* 64-bit. */
3854 pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3855 pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3856 pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3857 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3858 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3859 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3860 pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3861 pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3862 pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3863 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3864 pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3865 pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3866 pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3867 pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3868 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3869 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3870 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3871 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3872 pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3873 pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3874 pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3875 pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3876 pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3877 pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3878 pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3879 pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3880 pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3881 pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3882 pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
3883 pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
3884 pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
3885
3886 /* Natural width. */
3887 pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3888 pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3889 pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3890 pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3891 pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3892 pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3893 pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3894 pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3895 }
3896
3897 /* Guest state. */
3898 {
3899 char szEFlags[80];
3900 cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3901 pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3902
3903 /* 16-bit. */
3904 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3905 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3906 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3907 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3908 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3909 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3910 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3911 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3912 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3913 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3914 pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3915 pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3916
3917 /* 32-bit. */
3918 pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3919 pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3920 pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3921 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3922 pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3923
3924 /* 64-bit. */
3925 pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3926 pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3927 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3928 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3929 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3930 pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3931 pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3932 pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3933 pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3934 pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3935 pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3936 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3937
3938 /* Natural width. */
3939 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3940 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3941 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3942 pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3943 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3944 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3945 pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3946 pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3947 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3948 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3949 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3950 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3951 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3952 }
3953
3954 /* Host state. */
3955 {
3956 pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3957
3958 /* 16-bit. */
3959 pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3960 pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3961 pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3962 pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3963 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3964 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3965 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3966 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3967 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3968
3969 /* 32-bit. */
3970 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3971
3972 /* 64-bit. */
3973 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3974 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3975 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3976 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3977
3978 /* Natural width. */
3979 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3980 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3981 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3982 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3983 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3984 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3985 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3986 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3987 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3988 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3989 }
3990
3991 /* Read-only fields. */
3992 {
3993 pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3994
3995 /* 16-bit (none currently). */
3996
3997 /* 32-bit. */
3998 pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3999 pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4000 pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4001 pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4002 {
4003 uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4004 uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4005 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4006 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4007 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4008 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4009 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4010 }
4011 pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4012 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4013 {
4014 uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4015 uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4016 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4017 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4018 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4019 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4020 }
4021 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4022 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4023 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4024
4025 /* 64-bit. */
4026 pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4027
4028 /* Natural width. */
4029 pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4030 pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4031 pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4032 pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4033 pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4034 }
4035
4036#ifdef DEBUG_ramshankar
4037 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4038 {
4039 void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4040 Assert(pvPage);
4041 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4042 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4043 if (RT_SUCCESS(rc))
4044 {
4045 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4046 pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4047 pHlp->pfnPrintf(pHlp, "\n");
4048 }
4049 RTMemTmpFree(pvPage);
4050 }
4051#else
4052 NOREF(pVCpu);
4053#endif
4054
4055#undef CPUMVMX_DUMP_HOST_XDTR
4056#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4057#undef CPUMVMX_DUMP_GUEST_SEGREG
4058#undef CPUMVMX_DUMP_GUEST_XDTR
4059}
4060
4061
4062/**
4063 * Display the guest's hardware-virtualization cpu state.
4064 *
4065 * @param pVM The cross context VM structure.
4066 * @param pHlp The info helper functions.
4067 * @param pszArgs Arguments, ignored.
4068 */
4069static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4070{
4071 RT_NOREF(pszArgs);
4072
4073 PVMCPU pVCpu = VMMGetCpu(pVM);
4074 if (!pVCpu)
4075 pVCpu = pVM->apCpusR3[0];
4076
4077 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4078 bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4079 bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4080
4081 pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4082 pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4083 pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4084
4085 if (fSvm)
4086 {
4087 pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4088 pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4089
4090 char szEFlags[80];
4091 cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4092 pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4093 pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4094 pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4095 cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4096 pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4097 cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4098 pHlp->pfnPrintf(pHlp, " HostState:\n");
4099 pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4100 pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4101 pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4102 pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4103 pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4104 pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4105 pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4106 pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4107 PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4108 pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4109 pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4110 PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4111 pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4112 pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4113 PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4114 pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4115 pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4116 PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4117 pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4118 pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4119 pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4120 pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4121 pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4122 pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4123 pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4124 pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4125 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4126 }
4127 else if (fVmx)
4128 {
4129 pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4130 pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4131 pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4132 pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4133 pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4134 pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4135 pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4136 pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4137 pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4138 pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4139 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4140 pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4141 pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4142 pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4143 pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4144 pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4145 pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4146 pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4147 cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4148 }
4149 else
4150 pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4151
4152#undef CPUMHWVIRTDUMP_NONE
4153#undef CPUMHWVIRTDUMP_COMMON
4154#undef CPUMHWVIRTDUMP_SVM
4155#undef CPUMHWVIRTDUMP_VMX
4156#undef CPUMHWVIRTDUMP_LAST
4157#undef CPUMHWVIRTDUMP_ALL
4158}
4159
4160/**
4161 * Display the current guest instruction
4162 *
4163 * @param pVM The cross context VM structure.
4164 * @param pHlp The info helper functions.
4165 * @param pszArgs Arguments, ignored.
4166 */
4167static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4168{
4169 NOREF(pszArgs);
4170
4171 PVMCPU pVCpu = VMMGetCpu(pVM);
4172 if (!pVCpu)
4173 pVCpu = pVM->apCpusR3[0];
4174
4175 char szInstruction[256];
4176 szInstruction[0] = '\0';
4177 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4178 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4179}
4180
4181
4182/**
4183 * Display the hypervisor cpu state.
4184 *
4185 * @param pVM The cross context VM structure.
4186 * @param pHlp The info helper functions.
4187 * @param pszArgs Arguments, ignored.
4188 */
4189static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4190{
4191 PVMCPU pVCpu = VMMGetCpu(pVM);
4192 if (!pVCpu)
4193 pVCpu = pVM->apCpusR3[0];
4194
4195 CPUMDUMPTYPE enmType;
4196 const char *pszComment;
4197 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4198 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4199
4200 pHlp->pfnPrintf(pHlp,
4201 ".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4202 ".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4203 pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4204 pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4205 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4206}
4207
4208
4209/**
4210 * Display the host cpu state.
4211 *
4212 * @param pVM The cross context VM structure.
4213 * @param pHlp The info helper functions.
4214 * @param pszArgs Arguments, ignored.
4215 */
4216static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4217{
4218 CPUMDUMPTYPE enmType;
4219 const char *pszComment;
4220 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4221 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4222
4223 PVMCPU pVCpu = VMMGetCpu(pVM);
4224 if (!pVCpu)
4225 pVCpu = pVM->apCpusR3[0];
4226 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4227
4228 /*
4229 * Format the EFLAGS.
4230 */
4231 uint64_t efl = pCtx->rflags;
4232 char szEFlags[80];
4233 cpumR3InfoFormatFlags(&szEFlags[0], efl);
4234
4235 /*
4236 * Format the registers.
4237 */
4238 pHlp->pfnPrintf(pHlp,
4239 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4240 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4241 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4242 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4243 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4244 "r14=%016RX64 r15=%016RX64\n"
4245 "iopl=%d %31s\n"
4246 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4247 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4248 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
4249 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4250 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4251 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4252 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4253 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4254 ,
4255 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
4256 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4257 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
4258 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
4259 pCtx->r11, pCtx->r12, pCtx->r13,
4260 pCtx->r14, pCtx->r15,
4261 X86_EFL_GET_IOPL(efl), szEFlags,
4262 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4263 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
4264 pCtx->cr4, pCtx->ldtr, pCtx->tr,
4265 pCtx->dr0, pCtx->dr1, pCtx->dr2,
4266 pCtx->dr3, pCtx->dr6, pCtx->dr7,
4267 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4268 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4269 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4270}
4271
4272/**
4273 * Structure used when disassembling and instructions in DBGF.
4274 * This is used so the reader function can get the stuff it needs.
4275 */
4276typedef struct CPUMDISASSTATE
4277{
4278 /** Pointer to the CPU structure. */
4279 PDISCPUSTATE pCpu;
4280 /** Pointer to the VM. */
4281 PVM pVM;
4282 /** Pointer to the VMCPU. */
4283 PVMCPU pVCpu;
4284 /** Pointer to the first byte in the segment. */
4285 RTGCUINTPTR GCPtrSegBase;
4286 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4287 RTGCUINTPTR GCPtrSegEnd;
4288 /** The size of the segment minus 1. */
4289 RTGCUINTPTR cbSegLimit;
4290 /** Pointer to the current page - R3 Ptr. */
4291 void const *pvPageR3;
4292 /** Pointer to the current page - GC Ptr. */
4293 RTGCPTR pvPageGC;
4294 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4295 PGMPAGEMAPLOCK PageMapLock;
4296 /** Whether the PageMapLock is valid or not. */
4297 bool fLocked;
4298 /** 64 bits mode or not. */
4299 bool f64Bits;
4300} CPUMDISASSTATE, *PCPUMDISASSTATE;
4301
4302
4303/**
4304 * @callback_method_impl{FNDISREADBYTES}
4305 */
4306static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4307{
4308 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4309 for (;;)
4310 {
4311 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4312
4313 /*
4314 * Need to update the page translation?
4315 */
4316 if ( !pState->pvPageR3
4317 || (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4318 {
4319 /* translate the address */
4320 pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4321
4322 /* Release mapping lock previously acquired. */
4323 if (pState->fLocked)
4324 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4325 int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4326 if (RT_SUCCESS(rc))
4327 pState->fLocked = true;
4328 else
4329 {
4330 pState->fLocked = false;
4331 pState->pvPageR3 = NULL;
4332 return rc;
4333 }
4334 }
4335
4336 /*
4337 * Check the segment limit.
4338 */
4339 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4340 return VERR_OUT_OF_SELECTOR_BOUNDS;
4341
4342 /*
4343 * Calc how much we can read.
4344 */
4345 uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4346 if (!pState->f64Bits)
4347 {
4348 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4349 if (cb > cbSeg && cbSeg)
4350 cb = cbSeg;
4351 }
4352 if (cb > cbMaxRead)
4353 cb = cbMaxRead;
4354
4355 /*
4356 * Read and advance or exit.
4357 */
4358 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4359 offInstr += (uint8_t)cb;
4360 if (cb >= cbMinRead)
4361 {
4362 pDis->cbCachedInstr = offInstr;
4363 return VINF_SUCCESS;
4364 }
4365 cbMinRead -= (uint8_t)cb;
4366 cbMaxRead -= (uint8_t)cb;
4367 }
4368}
4369
4370
4371/**
4372 * Disassemble an instruction and return the information in the provided structure.
4373 *
4374 * @returns VBox status code.
4375 * @param pVM The cross context VM structure.
4376 * @param pVCpu The cross context virtual CPU structure.
4377 * @param pCtx Pointer to the guest CPU context.
4378 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4379 * @param pCpu Disassembly state.
4380 * @param pszPrefix String prefix for logging (debug only).
4381 *
4382 */
4383VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4384 const char *pszPrefix)
4385{
4386 CPUMDISASSTATE State;
4387 int rc;
4388
4389 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4390 State.pCpu = pCpu;
4391 State.pvPageGC = 0;
4392 State.pvPageR3 = NULL;
4393 State.pVM = pVM;
4394 State.pVCpu = pVCpu;
4395 State.fLocked = false;
4396 State.f64Bits = false;
4397
4398 /*
4399 * Get selector information.
4400 */
4401 DISCPUMODE enmDisCpuMode;
4402 if ( (pCtx->cr0 & X86_CR0_PE)
4403 && pCtx->eflags.Bits.u1VM == 0)
4404 {
4405 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4406 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4407 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4408 State.GCPtrSegBase = pCtx->cs.u64Base;
4409 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4410 State.cbSegLimit = pCtx->cs.u32Limit;
4411 enmDisCpuMode = (State.f64Bits)
4412 ? DISCPUMODE_64BIT
4413 : pCtx->cs.Attr.n.u1DefBig
4414 ? DISCPUMODE_32BIT
4415 : DISCPUMODE_16BIT;
4416 }
4417 else
4418 {
4419 /* real or V86 mode */
4420 enmDisCpuMode = DISCPUMODE_16BIT;
4421 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4422 State.GCPtrSegEnd = 0xFFFFFFFF;
4423 State.cbSegLimit = 0xFFFFFFFF;
4424 }
4425
4426 /*
4427 * Disassemble the instruction.
4428 */
4429 uint32_t cbInstr;
4430#ifndef LOG_ENABLED
4431 RT_NOREF_PV(pszPrefix);
4432 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4433 if (RT_SUCCESS(rc))
4434 {
4435#else
4436 char szOutput[160];
4437 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4438 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4439 if (RT_SUCCESS(rc))
4440 {
4441 /* log it */
4442 if (pszPrefix)
4443 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4444 else
4445 Log(("%s", szOutput));
4446#endif
4447 rc = VINF_SUCCESS;
4448 }
4449 else
4450 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4451
4452 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4453 if (State.fLocked)
4454 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4455
4456 return rc;
4457}
4458
4459
4460
4461/**
4462 * API for controlling a few of the CPU features found in CR4.
4463 *
4464 * Currently only X86_CR4_TSD is accepted as input.
4465 *
4466 * @returns VBox status code.
4467 *
4468 * @param pVM The cross context VM structure.
4469 * @param fOr The CR4 OR mask.
4470 * @param fAnd The CR4 AND mask.
4471 */
4472VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4473{
4474 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4475 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4476
4477 pVM->cpum.s.CR4.OrMask &= fAnd;
4478 pVM->cpum.s.CR4.OrMask |= fOr;
4479
4480 return VINF_SUCCESS;
4481}
4482
4483
4484/**
4485 * Called when the ring-3 init phase completes.
4486 *
4487 * @returns VBox status code.
4488 * @param pVM The cross context VM structure.
4489 * @param enmWhat Which init phase.
4490 */
4491VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4492{
4493 switch (enmWhat)
4494 {
4495 case VMINITCOMPLETED_RING3:
4496 {
4497 /*
4498 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4499 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4500 */
4501 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4502 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4503 {
4504 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4505
4506 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4507 if (fSupportsLongMode)
4508 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
4509 }
4510
4511 /* Register statistic counters for MSRs. */
4512 cpumR3MsrRegStats(pVM);
4513
4514 /* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4515 CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4516 cpumR3CpuIdRing3InitDone(pVM);
4517
4518 /* Create VMX-preemption timer for nested guests if required. Must be
4519 done here as CPUM is initialized before TM. */
4520 if (pVM->cpum.s.GuestFeatures.fVmx)
4521 {
4522 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4523 {
4524 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4525 char szName[32];
4526 RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4527 int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4528 TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4529 AssertLogRelRCReturn(rc, rc);
4530 }
4531 }
4532 break;
4533 }
4534
4535 default:
4536 break;
4537 }
4538 return VINF_SUCCESS;
4539}
4540
4541
4542/**
4543 * Called when the ring-0 init phases completed.
4544 *
4545 * @param pVM The cross context VM structure.
4546 */
4547VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4548{
4549 /*
4550 * Enable log buffering as we're going to log a lot of lines.
4551 */
4552 bool const fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4553
4554 /*
4555 * Log the cpuid.
4556 */
4557 RTCPUSET OnlineSet;
4558 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4559 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4560 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4561 RTCPUID cCores = RTMpGetCoreCount();
4562 if (cCores)
4563 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4564 LogRel(("************************* CPUID dump ************************\n"));
4565 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4566 LogRel(("\n"));
4567 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4568 LogRel(("******************** End of CPUID dump **********************\n"));
4569
4570 /*
4571 * Log VT-x extended features.
4572 *
4573 * SVM features are currently all covered under CPUID so there is nothing
4574 * to do here for SVM.
4575 */
4576 if (pVM->cpum.s.HostFeatures.fVmx)
4577 {
4578 LogRel(("*********************** VT-x features ***********************\n"));
4579 DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4580 LogRel(("\n"));
4581 LogRel(("******************* End of VT-x features ********************\n"));
4582 }
4583
4584 /*
4585 * Restore the log buffering state to what it was previously.
4586 */
4587 RTLogRelSetBuffering(fOldBuffered);
4588}
4589
4590
4591/**
4592 * Marks the guest debug state as active.
4593 *
4594 * @returns nothing.
4595 * @param pVCpu The cross context virtual CPU structure.
4596 *
4597 * @note This is used solely by NEM (hence the name) to set the correct flags here
4598 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
4599 * The specific NEM backends have to make sure to load the correct values.
4600 */
4601VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4602{
4603 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4604 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4605}
4606
4607
4608/**
4609 * Marks the hyper debug state as active.
4610 *
4611 * @returns nothing.
4612 * @param pVCpu The cross context virtual CPU structure.
4613 *
4614 * @note This is used solely by NEM (hence the name) to set the correct flags here
4615 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
4616 * The specific NEM backends have to make sure to load the correct values.
4617 */
4618VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4619{
4620 /*
4621 * Make sure the hypervisor values are up to date.
4622 */
4623 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4624
4625 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4626 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4627}
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