VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 50653

Last change on this file since 50653 was 50590, checked in by vboxsync, 10 years ago

CPUM,VMM: More work related to bus, cpu and tsc frequency info. Should cover older core and p6 as well as p4 now.
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File size: 225.2 KB
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1/* $Id: CPUM.cpp 50590 2014-02-25 18:51:23Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/** The current saved state version. */
70#define CPUM_SAVED_STATE_VERSION 14
71/** The current saved state version before using SSMR3PutStruct. */
72#define CPUM_SAVED_STATE_VERSION_MEM 13
73/** The saved state version before introducing the MSR size field. */
74#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
75/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
76 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
77#define CPUM_SAVED_STATE_VERSION_VER3_2 11
78/** The saved state version of 3.0 and 3.1 trunk before the teleportation
79 * changes. */
80#define CPUM_SAVED_STATE_VERSION_VER3_0 10
81/** The saved state version for the 2.1 trunk before the MSR changes. */
82#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
83/** The saved state version of 2.0, used for backwards compatibility. */
84#define CPUM_SAVED_STATE_VERSION_VER2_0 8
85/** The saved state version of 1.6, used for backwards compatibility. */
86#define CPUM_SAVED_STATE_VERSION_VER1_6 6
87
88
89/**
90 * This was used in the saved state up to the early life of version 14.
91 *
92 * It indicates that we may have some out-of-sync hidden segement registers.
93 * It is only relevant for raw-mode.
94 */
95#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
96
97
98/*******************************************************************************
99* Structures and Typedefs *
100*******************************************************************************/
101
102/**
103 * What kind of cpu info dump to perform.
104 */
105typedef enum CPUMDUMPTYPE
106{
107 CPUMDUMPTYPE_TERSE,
108 CPUMDUMPTYPE_DEFAULT,
109 CPUMDUMPTYPE_VERBOSE
110} CPUMDUMPTYPE;
111/** Pointer to a cpu info dump type. */
112typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
113
114
115/*******************************************************************************
116* Internal Functions *
117*******************************************************************************/
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
538 *
539 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error
540 * pointers (last instruction pointer, last data pointer, last opcode)
541 * except when the ES bit (Exception Summary) in x87 FSW (FPU Status
542 * Word) is set. Thus if we don't clear these registers there is
543 * potential, local FPU leakage from a process using the FPU to
544 * another.
545 *
546 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
547 *
548 * @param pVM Pointer to the VM.
549 */
550static void cpumR3CheckLeakyFpu(PVM pVM)
551{
552 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
553 uint32_t const u32Family = u32CpuVersion >> 8;
554 if ( u32Family >= 6 /* K7 and higher */
555 && ASMIsAmdCpu())
556 {
557 uint32_t cExt = ASMCpuId_EAX(0x80000000);
558 if (ASMIsValidExtRange(cExt))
559 {
560 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
561 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
562 {
563 for (VMCPUID i = 0; i < pVM->cCpus; i++)
564 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
565 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
566 }
567 }
568 }
569}
570
571
572/**
573 * Initializes the CPUM.
574 *
575 * @returns VBox status code.
576 * @param pVM Pointer to the VM.
577 */
578VMMR3DECL(int) CPUMR3Init(PVM pVM)
579{
580 LogFlow(("CPUMR3Init\n"));
581
582 /*
583 * Assert alignment, sizes and tables.
584 */
585 AssertCompileMemberAlignment(VM, cpum.s, 32);
586 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
587 AssertCompileSizeAlignment(CPUMCTX, 64);
588 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
589 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
590 AssertCompileMemberAlignment(VM, cpum, 64);
591 AssertCompileMemberAlignment(VM, aCpus, 64);
592 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
593 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
594#ifdef VBOX_STRICT
595 int rc2 = cpumR3MsrStrictInitChecks();
596 AssertRCReturn(rc2, rc2);
597#endif
598
599 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
602
603
604 /* Calculate the offset from CPUMCPU to CPUM. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
611 }
612
613 /*
614 * Check that the CPU supports the minimum features we require.
615 */
616 if (!ASMHasCpuId())
617 {
618 Log(("The CPU doesn't support CPUID!\n"));
619 return VERR_UNSUPPORTED_CPU;
620 }
621 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
622 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
623
624 /* Setup the CR4 AND and OR masks used in the switcher */
625 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
626 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
627 {
628 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
629 /* No FXSAVE implies no SSE */
630 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
631 pVM->cpum.s.CR4.OrMask = 0;
632 }
633 else
634 {
635 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
636 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
637 }
638
639 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
640 {
641 Log(("The CPU doesn't support MMX!\n"));
642 return VERR_UNSUPPORTED_CPU;
643 }
644 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
645 {
646 Log(("The CPU doesn't support TSC!\n"));
647 return VERR_UNSUPPORTED_CPU;
648 }
649 /* Bogus on AMD? */
650 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
651 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
652
653 /*
654 * Gather info about the host CPU.
655 */
656 PCPUMCPUIDLEAF paLeaves;
657 uint32_t cLeaves;
658 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
659 AssertLogRelRCReturn(rc, rc);
660
661 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
662 RTMemFree(paLeaves);
663 AssertLogRelRCReturn(rc, rc);
664 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
665
666 /*
667 * Setup hypervisor startup values.
668 */
669
670 /*
671 * Register saved state data item.
672 */
673 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
674 NULL, cpumR3LiveExec, NULL,
675 NULL, cpumR3SaveExec, NULL,
676 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
677 if (RT_FAILURE(rc))
678 return rc;
679
680 /*
681 * Register info handlers and registers with the debugger facility.
682 */
683 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
684 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
685 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
686 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
687 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
688 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
689
690 rc = cpumR3DbgInit(pVM);
691 if (RT_FAILURE(rc))
692 return rc;
693
694 /*
695 * Check if we need to workaround partial/leaky FPU handling.
696 */
697 cpumR3CheckLeakyFpu(pVM);
698
699 /*
700 * Initialize the Guest CPUID state.
701 */
702 rc = cpumR3CpuIdInit(pVM);
703 if (RT_FAILURE(rc))
704 return rc;
705 CPUMR3Reset(pVM);
706 return VINF_SUCCESS;
707}
708
709
710/**
711 * Loads MSR range overrides.
712 *
713 * This must be called before the MSR ranges are moved from the normal heap to
714 * the hyper heap!
715 *
716 * @returns VBox status code (VMSetError called).
717 * @param pVM Pointer to the cross context VM structure
718 * @param pMsrNode The CFGM node with the MSR overrides.
719 */
720static int cpumR3LoadMsrOverrides(PVM pVM, PCFGMNODE pMsrNode)
721{
722 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pMsrNode); pNode; pNode = CFGMR3GetNextChild(pNode))
723 {
724 /*
725 * Assemble a valid MSR range.
726 */
727 CPUMMSRRANGE MsrRange;
728 MsrRange.offCpumCpu = 0;
729 MsrRange.fReserved = 0;
730
731 int rc = CFGMR3GetName(pNode, MsrRange.szName, sizeof(MsrRange.szName));
732 if (RT_FAILURE(rc))
733 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry (name is probably too long): %Rrc\n", rc);
734
735 rc = CFGMR3QueryU32(pNode, "First", &MsrRange.uFirst);
736 if (RT_FAILURE(rc))
737 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying mandatory 'First' value: %Rrc\n",
738 MsrRange.szName, rc);
739
740 rc = CFGMR3QueryU32Def(pNode, "Last", &MsrRange.uLast, MsrRange.uFirst);
741 if (RT_FAILURE(rc))
742 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Last' value: %Rrc\n",
743 MsrRange.szName, rc);
744
745 char szType[32];
746 rc = CFGMR3QueryStringDef(pNode, "Type", szType, sizeof(szType), "FixedValue");
747 if (RT_FAILURE(rc))
748 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Type' value: %Rrc\n",
749 MsrRange.szName, rc);
750 if (!RTStrICmp(szType, "FixedValue"))
751 {
752 MsrRange.enmRdFn = kCpumMsrRdFn_FixedValue;
753 MsrRange.enmWrFn = kCpumMsrWrFn_IgnoreWrite;
754
755 rc = CFGMR3QueryU64Def(pNode, "Value", &MsrRange.uValue, 0);
756 if (RT_FAILURE(rc))
757 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'Value' value: %Rrc\n",
758 MsrRange.szName, rc);
759
760 rc = CFGMR3QueryU64Def(pNode, "WrGpMask", &MsrRange.fWrGpMask, 0);
761 if (RT_FAILURE(rc))
762 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrGpMask' value: %Rrc\n",
763 MsrRange.szName, rc);
764
765 rc = CFGMR3QueryU64Def(pNode, "WrIgnMask", &MsrRange.fWrIgnMask, 0);
766 if (RT_FAILURE(rc))
767 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid MSR entry '%s': Error querying 'WrIgnMask' value: %Rrc\n",
768 MsrRange.szName, rc);
769 }
770 else
771 return VMSetError(pVM, VERR_INVALID_PARAMETER, RT_SRC_POS,
772 "Invalid MSR entry '%s': Unknown type '%s'\n", MsrRange.szName, szType);
773
774 /*
775 * Insert the range into the table (replaces/splits/shrinks existing
776 * MSR ranges).
777 */
778 rc = cpumR3MsrRangesInsert(&pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges, &MsrRange);
779 if (RT_FAILURE(rc))
780 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding MSR entry '%s': %Rrc\n", MsrRange.szName, rc);
781 }
782
783 return VINF_SUCCESS;
784}
785
786
787/**
788 * Loads CPUID leaf overrides.
789 *
790 * This must be called before the CPUID leaves are moved from the normal
791 * heap to the hyper heap!
792 *
793 * @returns VBox status code (VMSetError called).
794 * @param pVM Pointer to the cross context VM structure
795 * @param pParentNode The CFGM node with the CPUID leaves.
796 * @param pszLabel How to label the overrides we're loading.
797 */
798static int cpumR3LoadCpuIdOverrides(PVM pVM, PCFGMNODE pParentNode, const char *pszLabel)
799{
800 for (PCFGMNODE pNode = CFGMR3GetFirstChild(pParentNode); pNode; pNode = CFGMR3GetNextChild(pNode))
801 {
802 /*
803 * Get the leaf and subleaf numbers.
804 */
805 char szName[128];
806 int rc = CFGMR3GetName(pNode, szName, sizeof(szName));
807 if (RT_FAILURE(rc))
808 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry (name is probably too long): %Rrc\n", pszLabel, rc);
809
810 /* The leaf number is either specified directly or thru the node name. */
811 uint32_t uLeaf;
812 rc = CFGMR3QueryU32(pNode, "Leaf", &uLeaf);
813 if (rc == VERR_CFGM_VALUE_NOT_FOUND)
814 {
815 rc = RTStrToUInt32Full(szName, 16, &uLeaf);
816 if (rc != VINF_SUCCESS)
817 return VMSetError(pVM, VERR_INVALID_NAME, RT_SRC_POS,
818 "Invalid %s entry: Invalid leaf number: '%s' \n", pszLabel, szName);
819 }
820 else if (RT_FAILURE(rc))
821 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'Leaf' value: %Rrc\n",
822 pszLabel, szName, rc);
823
824 uint32_t uSubLeaf;
825 rc = CFGMR3QueryU32Def(pNode, "SubLeaf", &uSubLeaf, 0);
826 if (RT_FAILURE(rc))
827 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeaf' value: %Rrc\n",
828 pszLabel, szName, rc);
829
830 uint32_t fSubLeafMask;
831 rc = CFGMR3QueryU32Def(pNode, "SubLeafMask", &fSubLeafMask, 0);
832 if (RT_FAILURE(rc))
833 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'SubLeafMask' value: %Rrc\n",
834 pszLabel, szName, rc);
835
836 /*
837 * Look up the specified leaf, since the output register values
838 * defaults to any existing values. This allows overriding a single
839 * register, without needing to know the other values.
840 */
841 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, pVM->cpum.s.GuestInfo.cCpuIdLeaves,
842 uLeaf, uSubLeaf);
843 CPUMCPUIDLEAF Leaf;
844 if (pLeaf)
845 Leaf = *pLeaf;
846 else
847 RT_ZERO(Leaf);
848 Leaf.uLeaf = uLeaf;
849 Leaf.uSubLeaf = uSubLeaf;
850 Leaf.fSubLeafMask = fSubLeafMask;
851
852 rc = CFGMR3QueryU32Def(pNode, "eax", &Leaf.uEax, Leaf.uEax);
853 if (RT_FAILURE(rc))
854 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'eax' value: %Rrc\n",
855 pszLabel, szName, rc);
856 rc = CFGMR3QueryU32Def(pNode, "ebx", &Leaf.uEbx, Leaf.uEbx);
857 if (RT_FAILURE(rc))
858 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ebx' value: %Rrc\n",
859 pszLabel, szName, rc);
860 rc = CFGMR3QueryU32Def(pNode, "ecx", &Leaf.uEcx, Leaf.uEcx);
861 if (RT_FAILURE(rc))
862 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'ecx' value: %Rrc\n",
863 pszLabel, szName, rc);
864 rc = CFGMR3QueryU32Def(pNode, "edx", &Leaf.uEdx, Leaf.uEdx);
865 if (RT_FAILURE(rc))
866 return VMSetError(pVM, rc, RT_SRC_POS, "Invalid %s entry '%s': Error querying 'edx' value: %Rrc\n",
867 pszLabel, szName, rc);
868
869 /*
870 * Insert the leaf into the table (replaces existing ones).
871 */
872 rc = cpumR3CpuIdInsert(&pVM->cpum.s.GuestInfo.paCpuIdLeavesR3, &pVM->cpum.s.GuestInfo.cCpuIdLeaves, &Leaf);
873 if (RT_FAILURE(rc))
874 return VMSetError(pVM, rc, RT_SRC_POS, "Error adding CPUID leaf entry '%s': %Rrc\n", szName, rc);
875 }
876
877 return VINF_SUCCESS;
878}
879
880
881
882/**
883 * Fetches overrides for a CPUID leaf.
884 *
885 * @returns VBox status code.
886 * @param pLeaf The leaf to load the overrides into.
887 * @param pCfgNode The CFGM node containing the overrides
888 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
889 * @param iLeaf The CPUID leaf number.
890 */
891static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
892{
893 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
894 if (pLeafNode)
895 {
896 uint32_t u32;
897 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
898 if (RT_SUCCESS(rc))
899 pLeaf->eax = u32;
900 else
901 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
902
903 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
904 if (RT_SUCCESS(rc))
905 pLeaf->ebx = u32;
906 else
907 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
908
909 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
910 if (RT_SUCCESS(rc))
911 pLeaf->ecx = u32;
912 else
913 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
914
915 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
916 if (RT_SUCCESS(rc))
917 pLeaf->edx = u32;
918 else
919 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
920
921 }
922 return VINF_SUCCESS;
923}
924
925
926/**
927 * Load the overrides for a set of CPUID leaves.
928 *
929 * @returns VBox status code.
930 * @param paLeaves The leaf array.
931 * @param cLeaves The number of leaves.
932 * @param uStart The start leaf number.
933 * @param pCfgNode The CFGM node containing the overrides
934 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
935 */
936static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
937{
938 for (uint32_t i = 0; i < cLeaves; i++)
939 {
940 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
941 if (RT_FAILURE(rc))
942 return rc;
943 }
944
945 return VINF_SUCCESS;
946}
947
948/**
949 * Init a set of host CPUID leaves.
950 *
951 * @returns VBox status code.
952 * @param paLeaves The leaf array.
953 * @param cLeaves The number of leaves.
954 * @param uStart The start leaf number.
955 * @param pCfgNode The /CPUM/HostCPUID/ node.
956 */
957static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
958{
959 /* Using the ECX variant for all of them can't hurt... */
960 for (uint32_t i = 0; i < cLeaves; i++)
961 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
962
963 /* Load CPUID leaf override; we currently don't care if the user
964 specifies features the host CPU doesn't support. */
965 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
966}
967
968
969static int cpumR3CpuIdInstallAndExplodeLeaves(PVM pVM, PCPUM pCPUM, PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves)
970{
971 /*
972 * Install the CPUID information.
973 */
974 int rc = MMHyperDupMem(pVM, paLeaves, sizeof(paLeaves[0]) * cLeaves, 32,
975 MM_TAG_CPUM_CPUID, (void **)&pCPUM->GuestInfo.paCpuIdLeavesR3);
976
977 AssertLogRelRCReturn(rc, rc);
978
979 pCPUM->GuestInfo.paCpuIdLeavesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
980 pCPUM->GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paCpuIdLeavesR3);
981 Assert(MMHyperR0ToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesR0) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
982 Assert(MMHyperRCToR3(pVM, pCPUM->GuestInfo.paCpuIdLeavesRC) == (void *)pCPUM->GuestInfo.paCpuIdLeavesR3);
983
984 /*
985 * Explode the guest CPU features.
986 */
987 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
988 AssertLogRelRCReturn(rc, rc);
989
990 /*
991 * Adjust the scalable bus frequency according to the CPUID information
992 * we're now using.
993 */
994 if (CPUMMICROARCH_IS_INTEL_CORE7(pVM->cpum.s.GuestFeatures.enmMicroarch))
995 pCPUM->GuestInfo.uScalableBusFreq = pCPUM->GuestFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_SandyBridge
996 ? UINT64_C(100000000) /* 100MHz */
997 : UINT64_C(133333333); /* 133MHz */
998
999 /*
1000 * Populate the legacy arrays. Currently used for everything, later only
1001 * for patch manager.
1002 */
1003 struct { PCPUMCPUID paCpuIds; uint32_t cCpuIds, uBase; } aOldRanges[] =
1004 {
1005 { pCPUM->aGuestCpuIdStd, RT_ELEMENTS(pCPUM->aGuestCpuIdStd), 0x00000000 },
1006 { pCPUM->aGuestCpuIdExt, RT_ELEMENTS(pCPUM->aGuestCpuIdExt), 0x80000000 },
1007 { pCPUM->aGuestCpuIdCentaur, RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), 0xc0000000 },
1008 { pCPUM->aGuestCpuIdHyper, RT_ELEMENTS(pCPUM->aGuestCpuIdHyper), 0x40000000 },
1009 };
1010 for (uint32_t i = 0; i < RT_ELEMENTS(aOldRanges); i++)
1011 {
1012 uint32_t cLeft = aOldRanges[i].cCpuIds;
1013 uint32_t uLeaf = aOldRanges[i].uBase + cLeft;
1014 PCPUMCPUID pLegacyLeaf = &aOldRanges[i].paCpuIds[cLeft];
1015 while (cLeft-- > 0)
1016 {
1017 uLeaf--;
1018 pLegacyLeaf--;
1019
1020 PCCPUMCPUIDLEAF pLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, uLeaf, 0);
1021 if (pLeaf)
1022 {
1023 pLegacyLeaf->eax = pLeaf->uEax;
1024 pLegacyLeaf->ebx = pLeaf->uEbx;
1025 pLegacyLeaf->ecx = pLeaf->uEcx;
1026 pLegacyLeaf->edx = pLeaf->uEdx;
1027 }
1028 else
1029 *pLegacyLeaf = pCPUM->GuestInfo.DefCpuId;
1030 }
1031 }
1032
1033 pCPUM->GuestCpuIdDef = pCPUM->GuestInfo.DefCpuId;
1034
1035 return VINF_SUCCESS;
1036}
1037
1038
1039/**
1040 * Initializes the emulated CPU's cpuid information.
1041 *
1042 * @returns VBox status code.
1043 * @param pVM Pointer to the VM.
1044 */
1045static int cpumR3CpuIdInit(PVM pVM)
1046{
1047 PCPUM pCPUM = &pVM->cpum.s;
1048 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
1049 int rc;
1050
1051#define PORTABLE_CLEAR_BITS_WHEN(Lvl, a_pLeafReg, FeatNm, fMask, uValue) \
1052 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fMask)) == (uValue) ) \
1053 { \
1054 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: %#x -> 0\n", (a_pLeafReg) & (fMask))); \
1055 (a_pLeafReg) &= ~(uint32_t)(fMask); \
1056 }
1057#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, a_pLeafReg, FeatNm, fBitMask) \
1058 if ( pCPUM->u8PortableCpuIdLevel >= (Lvl) && ((a_pLeafReg) & (fBitMask)) ) \
1059 { \
1060 LogRel(("PortableCpuId: " #a_pLeafReg "[" #FeatNm "]: 1 -> 0\n")); \
1061 (a_pLeafReg) &= ~(uint32_t)(fBitMask); \
1062 }
1063
1064 /*
1065 * Read the configuration.
1066 */
1067 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
1068 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
1069 * completely overridden by VirtualBox custom strings. Some
1070 * CPUID information is withheld, like the cache info.
1071 *
1072 * This is obsoleted by PortableCpuIdLevel. */
1073 bool fSyntheticCpu;
1074 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &fSyntheticCpu, false);
1075 AssertRCReturn(rc, rc);
1076
1077 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
1078 * When non-zero CPUID features that could cause portability issues will be
1079 * stripped. The higher the value the more features gets stripped. Higher
1080 * values should only be used when older CPUs are involved since it may
1081 * harm performance and maybe also cause problems with specific guests. */
1082 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, fSyntheticCpu ? 1 : 0);
1083 AssertLogRelRCReturn(rc, rc);
1084
1085 /** @cfgm{CPUM/GuestCpuName, string}
1086 * The name of of the CPU we're to emulate. The default is the host CPU.
1087 * Note! CPUs other than "host" one is currently unsupported. */
1088 char szCpuName[128];
1089 rc = CFGMR3QueryStringDef(pCpumCfg, "GuestCpuName", szCpuName, sizeof(szCpuName), "host");
1090 AssertLogRelRCReturn(rc, rc);
1091
1092 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
1093 * Expose CMPXCHG16B to the guest if supported by the host.
1094 */
1095 bool fCmpXchg16b;
1096 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false);
1097 AssertLogRelRCReturn(rc, rc);
1098
1099 /** @cfgm{/CPUM/MONITOR, boolean, true}
1100 * Expose MONITOR/MWAIT instructions to the guest.
1101 */
1102 bool fMonitor;
1103 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true);
1104 AssertLogRelRCReturn(rc, rc);
1105
1106 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1107 * Expose MWAIT extended features to the guest. For now we expose just MWAIT
1108 * break on interrupt feature (bit 1).
1109 */
1110 bool fMWaitExtensions;
1111 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false);
1112 AssertLogRelRCReturn(rc, rc);
1113
1114 /** @cfgm{/CPUM/SSE4.1, boolean, true}
1115 * Expose SSE4.1 to the guest if available.
1116 */
1117 bool fSse41;
1118 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.1", &fSse41, true);
1119 AssertLogRelRCReturn(rc, rc);
1120
1121 /** @cfgm{/CPUM/SSE4.2, boolean, true}
1122 * Expose SSE4.2 to the guest if available.
1123 */
1124 bool fSse42;
1125 rc = CFGMR3QueryBoolDef(pCpumCfg, "SSE4.2", &fSse42, true);
1126 AssertLogRelRCReturn(rc, rc);
1127
1128 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1129 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1130 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1131 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1132 */
1133 bool fNt4LeafLimit;
1134 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false);
1135 AssertLogRelRCReturn(rc, rc);
1136
1137 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1138 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1139 * probably going to be a temporary hack, so don't depend on this.
1140 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1141 * number and the 3rd byte value is the family, and the 4th value must be zero.
1142 */
1143 uint32_t uMaxIntelFamilyModelStep;
1144 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1145 AssertLogRelRCReturn(rc, rc);
1146
1147 /*
1148 * Get the guest CPU data from the database and/or the host.
1149 */
1150 rc = cpumR3DbGetCpuInfo(szCpuName, &pCPUM->GuestInfo);
1151 if (RT_FAILURE(rc))
1152 return rc == VERR_CPUM_DB_CPU_NOT_FOUND
1153 ? VMSetError(pVM, rc, RT_SRC_POS,
1154 "Info on guest CPU '%s' could not be found. Please, select a different CPU.", szCpuName)
1155 : rc;
1156
1157 /** @cfgm{CPUM/MSRs/[Name]/[First|Last|Type|Value|...],}
1158 * Overrides the guest MSRs.
1159 */
1160 rc = cpumR3LoadMsrOverrides(pVM, CFGMR3GetChild(pCpumCfg, "MSRs"));
1161
1162 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1163 * Overrides the CPUID leaf values (from the host CPU usually) used for
1164 * calculating the guest CPUID leaves. This can be used to preserve the CPUID
1165 * values when moving a VM to a different machine. Another use is restricting
1166 * (or extending) the feature set exposed to the guest. */
1167 if (RT_SUCCESS(rc))
1168 rc = cpumR3LoadCpuIdOverrides(pVM, CFGMR3GetChild(pCpumCfg, "HostCPUID"), "HostCPUID");
1169
1170 if (RT_SUCCESS(rc) && CFGMR3GetChild(pCpumCfg, "CPUID")) /* 2nd override, now discontinued. */
1171 rc = VMSetError(pVM, VERR_CFGM_CONFIG_UNKNOWN_NODE, RT_SRC_POS,
1172 "Found unsupported configuration node '/CPUM/CPUID/'. "
1173 "Please use IMachine::setCPUIDLeaf() instead.");
1174
1175 /*
1176 * Pre-exploded the CPUID info.
1177 */
1178 if (RT_SUCCESS(rc))
1179 rc = cpumR3CpuIdExplodeFeatures(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, &pCPUM->GuestFeatures);
1180 if (RT_FAILURE(rc))
1181 {
1182 RTMemFree(pCPUM->GuestInfo.paCpuIdLeavesR3);
1183 pCPUM->GuestInfo.paCpuIdLeavesR3 = NULL;
1184 RTMemFree(pCPUM->GuestInfo.paMsrRangesR3);
1185 pCPUM->GuestInfo.paMsrRangesR3 = NULL;
1186 return rc;
1187 }
1188
1189
1190 /* ... split this function about here ... */
1191
1192
1193 /* Cpuid 1:
1194 * Only report features we can support.
1195 *
1196 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1197 * options may require adjusting (i.e. stripping what was enabled).
1198 */
1199 PCPUMCPUIDLEAF pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1200 1, 0); /* Note! Must refetch when used later. */
1201 AssertLogRelReturn(pStdFeatureLeaf, VERR_CPUM_IPE_2);
1202 pStdFeatureLeaf->uEdx &= X86_CPUID_FEATURE_EDX_FPU
1203 | X86_CPUID_FEATURE_EDX_VME
1204 | X86_CPUID_FEATURE_EDX_DE
1205 | X86_CPUID_FEATURE_EDX_PSE
1206 | X86_CPUID_FEATURE_EDX_TSC
1207 | X86_CPUID_FEATURE_EDX_MSR
1208 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
1209 | X86_CPUID_FEATURE_EDX_MCE
1210 | X86_CPUID_FEATURE_EDX_CX8
1211 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
1212 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1213 //| X86_CPUID_FEATURE_EDX_SEP
1214 | X86_CPUID_FEATURE_EDX_MTRR
1215 | X86_CPUID_FEATURE_EDX_PGE
1216 | X86_CPUID_FEATURE_EDX_MCA
1217 | X86_CPUID_FEATURE_EDX_CMOV
1218 | X86_CPUID_FEATURE_EDX_PAT
1219 | X86_CPUID_FEATURE_EDX_PSE36
1220 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
1221 | X86_CPUID_FEATURE_EDX_CLFSH
1222 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
1223 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
1224 | X86_CPUID_FEATURE_EDX_MMX
1225 | X86_CPUID_FEATURE_EDX_FXSR
1226 | X86_CPUID_FEATURE_EDX_SSE
1227 | X86_CPUID_FEATURE_EDX_SSE2
1228 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
1229 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
1230 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
1231 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
1232 | 0;
1233 pStdFeatureLeaf->uEcx &= 0
1234 | X86_CPUID_FEATURE_ECX_SSE3
1235 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
1236 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
1237 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
1238 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
1239 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
1240 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
1241 | X86_CPUID_FEATURE_ECX_SSSE3
1242 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
1243 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
1244 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
1245 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
1246 | (fSse41 ? X86_CPUID_FEATURE_ECX_SSE4_1 : 0)
1247 | (fSse42 ? X86_CPUID_FEATURE_ECX_SSE4_2 : 0)
1248 /* ECX Bit 21 - x2APIC support - not yet. */
1249 // | X86_CPUID_FEATURE_ECX_X2APIC
1250 /* ECX Bit 23 - POPCNT instruction. */
1251 //| X86_CPUID_FEATURE_ECX_POPCNT
1252 | 0;
1253 if (pCPUM->u8PortableCpuIdLevel > 0)
1254 {
1255 PORTABLE_CLEAR_BITS_WHEN(1, pStdFeatureLeaf->uEax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
1256 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
1257 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
1258 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_1, X86_CPUID_FEATURE_ECX_SSE4_1);
1259 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, SSE4_2, X86_CPUID_FEATURE_ECX_SSE4_2);
1260 PORTABLE_DISABLE_FEATURE_BIT(1, pStdFeatureLeaf->uEcx, CX16, X86_CPUID_FEATURE_ECX_CX16);
1261 PORTABLE_DISABLE_FEATURE_BIT(2, pStdFeatureLeaf->uEdx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
1262 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, SSE, X86_CPUID_FEATURE_EDX_SSE);
1263 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
1264 PORTABLE_DISABLE_FEATURE_BIT(3, pStdFeatureLeaf->uEdx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
1265
1266 Assert(!(pStdFeatureLeaf->uEdx & ( X86_CPUID_FEATURE_EDX_SEP
1267 | X86_CPUID_FEATURE_EDX_PSN
1268 | X86_CPUID_FEATURE_EDX_DS
1269 | X86_CPUID_FEATURE_EDX_ACPI
1270 | X86_CPUID_FEATURE_EDX_SS
1271 | X86_CPUID_FEATURE_EDX_TM
1272 | X86_CPUID_FEATURE_EDX_PBE
1273 )));
1274 Assert(!(pStdFeatureLeaf->uEcx & ( X86_CPUID_FEATURE_ECX_PCLMUL
1275 | X86_CPUID_FEATURE_ECX_DTES64
1276 | X86_CPUID_FEATURE_ECX_CPLDS
1277 | X86_CPUID_FEATURE_ECX_VMX
1278 | X86_CPUID_FEATURE_ECX_SMX
1279 | X86_CPUID_FEATURE_ECX_EST
1280 | X86_CPUID_FEATURE_ECX_TM2
1281 | X86_CPUID_FEATURE_ECX_CNTXID
1282 | X86_CPUID_FEATURE_ECX_FMA
1283 | X86_CPUID_FEATURE_ECX_CX16
1284 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1285 | X86_CPUID_FEATURE_ECX_PDCM
1286 | X86_CPUID_FEATURE_ECX_DCA
1287 | X86_CPUID_FEATURE_ECX_MOVBE
1288 | X86_CPUID_FEATURE_ECX_AES
1289 | X86_CPUID_FEATURE_ECX_POPCNT
1290 | X86_CPUID_FEATURE_ECX_XSAVE
1291 | X86_CPUID_FEATURE_ECX_OSXSAVE
1292 | X86_CPUID_FEATURE_ECX_AVX
1293 )));
1294 }
1295
1296 /* Cpuid 0x80000001:
1297 * Only report features we can support.
1298 *
1299 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1300 * options may require adjusting (i.e. stripping what was enabled).
1301 *
1302 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
1303 */
1304 PCPUMCPUIDLEAF pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1305 UINT32_C(0x80000001), 0); /* Note! Must refetch when used later. */
1306 if (pExtFeatureLeaf)
1307 {
1308 pExtFeatureLeaf->uEdx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1309 | X86_CPUID_AMD_FEATURE_EDX_VME
1310 | X86_CPUID_AMD_FEATURE_EDX_DE
1311 | X86_CPUID_AMD_FEATURE_EDX_PSE
1312 | X86_CPUID_AMD_FEATURE_EDX_TSC
1313 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1314 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
1315 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1316 | X86_CPUID_AMD_FEATURE_EDX_CX8
1317 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1318 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1319 //| X86_CPUID_EXT_FEATURE_EDX_SEP
1320 | X86_CPUID_AMD_FEATURE_EDX_MTRR
1321 | X86_CPUID_AMD_FEATURE_EDX_PGE
1322 | X86_CPUID_AMD_FEATURE_EDX_MCA
1323 | X86_CPUID_AMD_FEATURE_EDX_CMOV
1324 | X86_CPUID_AMD_FEATURE_EDX_PAT
1325 | X86_CPUID_AMD_FEATURE_EDX_PSE36
1326 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
1327 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1328 | X86_CPUID_AMD_FEATURE_EDX_MMX
1329 | X86_CPUID_AMD_FEATURE_EDX_FXSR
1330 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
1331 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1332 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1333 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1334 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1335 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
1336 | 0;
1337 pExtFeatureLeaf->uEcx &= 0
1338 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1339 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1340 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1341 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1342 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1343 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1344 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1345 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1346 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1347 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1348 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1349 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1350 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1351 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1352 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1353 | 0;
1354 if (pCPUM->u8PortableCpuIdLevel > 0)
1355 {
1356 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEcx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1357 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1358 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1359 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1360 PORTABLE_DISABLE_FEATURE_BIT(1, pExtFeatureLeaf->uEdx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1361 PORTABLE_DISABLE_FEATURE_BIT(2, pExtFeatureLeaf->uEcx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1362 PORTABLE_DISABLE_FEATURE_BIT(3, pExtFeatureLeaf->uEcx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1363
1364 Assert(!(pExtFeatureLeaf->uEcx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1365 | X86_CPUID_AMD_FEATURE_ECX_SVM
1366 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1367 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1368 | X86_CPUID_AMD_FEATURE_ECX_ABM
1369 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1370 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1371 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1372 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1373 | X86_CPUID_AMD_FEATURE_ECX_IBS
1374 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1375 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1376 | X86_CPUID_AMD_FEATURE_ECX_WDT
1377 | UINT32_C(0xffffc000)
1378 )));
1379 Assert(!(pExtFeatureLeaf->uEdx & ( RT_BIT(10)
1380 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1381 | RT_BIT(18)
1382 | RT_BIT(19)
1383 | RT_BIT(21)
1384 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1385 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1386 | RT_BIT(28)
1387 )));
1388 }
1389 }
1390
1391 /*
1392 * Hide HTT, multicode, SMP, whatever.
1393 * (APIC-ID := 0 and #LogCpus := 0)
1394 */
1395 pStdFeatureLeaf->uEbx &= 0x0000ffff;
1396#ifdef VBOX_WITH_MULTI_CORE
1397 if (pVM->cCpus > 1)
1398 {
1399 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1400 pStdFeatureLeaf->uEbx |= (pVM->cCpus << 16);
1401 pStdFeatureLeaf->uEdx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1402 }
1403#endif
1404
1405 /* Cpuid 2:
1406 * Intel: Cache and TLB information
1407 * AMD: Reserved
1408 * VIA: Reserved
1409 * Safe to expose; restrict the number of calls to 1 for the portable case.
1410 */
1411 PCPUMCPUIDLEAF pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 2, 0);
1412 if ( pCPUM->u8PortableCpuIdLevel > 0
1413 && pCurLeaf
1414 && (pCurLeaf->uEax & 0xff) > 1)
1415 {
1416 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCurLeaf->uEax & 0xff));
1417 pCurLeaf->uEax &= UINT32_C(0xfffffffe);
1418 }
1419
1420 /* Cpuid 3:
1421 * Intel: EAX, EBX - reserved (transmeta uses these)
1422 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1423 * AMD: Reserved
1424 * VIA: Reserved
1425 * Safe to expose
1426 */
1427 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 3, 0);
1428 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1429 if ( !(pStdFeatureLeaf->uEdx & X86_CPUID_FEATURE_EDX_PSN)
1430 && pCurLeaf)
1431 {
1432 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1433 if (pCPUM->u8PortableCpuIdLevel > 0)
1434 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1435 }
1436
1437 /* Cpuid 4:
1438 * Intel: Deterministic Cache Parameters Leaf
1439 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1440 * AMD: Reserved
1441 * VIA: Reserved
1442 * Safe to expose, except for EAX:
1443 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1444 * Bits 31-26: Maximum number of processor cores in this physical package**
1445 * Note: These SMP values are constant regardless of ECX
1446 */
1447 CPUMCPUIDLEAF NewLeaf;
1448 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 4, 0);
1449 if (pCurLeaf)
1450 {
1451 NewLeaf.uLeaf = 4;
1452 NewLeaf.uSubLeaf = 0;
1453 NewLeaf.fSubLeafMask = 0;
1454 NewLeaf.uEax = 0;
1455 NewLeaf.uEbx = 0;
1456 NewLeaf.uEcx = 0;
1457 NewLeaf.uEdx = 0;
1458 NewLeaf.fFlags = 0;
1459#ifdef VBOX_WITH_MULTI_CORE
1460 if ( pVM->cCpus > 1
1461 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1462 {
1463 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1464 /* One logical processor with possibly multiple cores. */
1465 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1466 NewLeaf.uEax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1467 }
1468#endif
1469 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1470 AssertLogRelRCReturn(rc, rc);
1471 }
1472
1473 /* Cpuid 5: Monitor/mwait Leaf
1474 * Intel: ECX, EDX - reserved
1475 * EAX, EBX - Smallest and largest monitor line size
1476 * AMD: EDX - reserved
1477 * EAX, EBX - Smallest and largest monitor line size
1478 * ECX - extensions (ignored for now)
1479 * VIA: Reserved
1480 * Safe to expose
1481 */
1482 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 5, 0);
1483 if (pCurLeaf)
1484 {
1485 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1486 if (!(pStdFeatureLeaf->uEcx & X86_CPUID_FEATURE_ECX_MONITOR))
1487 pCurLeaf->uEax = pCurLeaf->uEbx = 0;
1488
1489 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1490 if (fMWaitExtensions)
1491 {
1492 pCurLeaf->uEcx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1493 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1494 it shall be part of our power management virtualization model */
1495#if 0
1496 /* MWAIT sub C-states */
1497 pCurLeaf->uEdx =
1498 (0 << 0) /* 0 in C0 */ |
1499 (2 << 4) /* 2 in C1 */ |
1500 (2 << 8) /* 2 in C2 */ |
1501 (2 << 12) /* 2 in C3 */ |
1502 (0 << 16) /* 0 in C4 */
1503 ;
1504#endif
1505 }
1506 else
1507 pCurLeaf->uEcx = pCurLeaf->uEdx = 0;
1508 }
1509
1510 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1511 * Safe to pass on to the guest.
1512 *
1513 * Intel: 0x800000005 reserved
1514 * 0x800000006 L2 cache information
1515 * AMD: 0x800000005 L1 cache information
1516 * 0x800000006 L2/L3 cache information
1517 * VIA: 0x800000005 TLB and L1 cache information
1518 * 0x800000006 L2 cache information
1519 */
1520
1521 /* Cpuid 0x800000007:
1522 * Intel: Reserved
1523 * AMD: EAX, EBX, ECX - reserved
1524 * EDX: Advanced Power Management Information
1525 * VIA: Reserved
1526 */
1527 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000007), 0);
1528 if (pCurLeaf)
1529 {
1530 Assert(pCPUM->GuestFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID);
1531
1532 pCurLeaf->uEax = pCurLeaf->uEbx = pCurLeaf->uEcx = 0;
1533
1534 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1535 {
1536 /* Only expose the TSC invariant capability bit to the guest. */
1537 pCurLeaf->uEdx &= 0
1538 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1539 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1540 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1541 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1542 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1543 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1544 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1545 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1546#if 0
1547 /*
1548 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1549 * Linux kernels blindly assume that the AMD performance counters work
1550 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1551 * bit for them though.)
1552 */
1553 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1554#endif
1555 | 0;
1556 }
1557 else
1558 pCurLeaf->uEdx = 0;
1559 }
1560
1561 /* Cpuid 0x800000008:
1562 * Intel: EAX: Virtual/Physical address Size
1563 * EBX, ECX, EDX - reserved
1564 * AMD: EBX, EDX - reserved
1565 * EAX: Virtual/Physical/Guest address Size
1566 * ECX: Number of cores + APICIdCoreIdSize
1567 * VIA: EAX: Virtual/Physical address Size
1568 * EBX, ECX, EDX - reserved
1569 */
1570 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000008), 0);
1571 if (pCurLeaf)
1572 {
1573 /* Only expose the virtual and physical address sizes to the guest. */
1574 pCurLeaf->uEax &= UINT32_C(0x0000ffff);
1575 pCurLeaf->uEbx = pCurLeaf->uEdx = 0; /* reserved */
1576 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1577 * NC (0-7) Number of cores; 0 equals 1 core */
1578 pCurLeaf->uEcx = 0;
1579#ifdef VBOX_WITH_MULTI_CORE
1580 if ( pVM->cCpus > 1
1581 && pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD)
1582 {
1583 /* Legacy method to determine the number of cores. */
1584 pCurLeaf->uEcx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1585 pExtFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1586 UINT32_C(0x80000001), 0);
1587 if (pExtFeatureLeaf)
1588 pExtFeatureLeaf->uEcx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1589 }
1590#endif
1591 }
1592
1593
1594 /*
1595 * Limit it the number of entries, zapping the remainder.
1596 *
1597 * The limits are masking off stuff about power saving and similar, this
1598 * is perhaps a bit crudely done as there is probably some relatively harmless
1599 * info too in these leaves (like words about having a constant TSC).
1600 */
1601 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 0, 0);
1602 if (pCurLeaf)
1603 {
1604 if (pCurLeaf->uEax > 5)
1605 {
1606 pCurLeaf->uEax = 5;
1607 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1608 pCurLeaf->uEax + 1, UINT32_C(0x000fffff));
1609 }
1610
1611 /* NT4 hack, no zapping of extra leaves here. */
1612 if (fNt4LeafLimit && pCurLeaf->uEax > 3)
1613 pCurLeaf->uEax = 3;
1614 }
1615
1616 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0x80000000), 0);
1617 if (pCurLeaf)
1618 {
1619 if (pCurLeaf->uEax > UINT32_C(0x80000008))
1620 {
1621 pCurLeaf->uEax = UINT32_C(0x80000008);
1622 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1623 pCurLeaf->uEax + 1, UINT32_C(0x800fffff));
1624 }
1625 }
1626
1627 /*
1628 * Centaur stuff (VIA).
1629 *
1630 * The important part here (we think) is to make sure the 0xc0000000
1631 * function returns 0xc0000001. As for the features, we don't currently
1632 * let on about any of those... 0xc0000002 seems to be some
1633 * temperature/hz/++ stuff, include it as well (static).
1634 */
1635 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, UINT32_C(0xc0000000), 0);
1636 if (pCurLeaf)
1637 {
1638 if ( pCurLeaf->uEax >= UINT32_C(0xc0000000)
1639 && pCurLeaf->uEax <= UINT32_C(0xc0000004))
1640 {
1641 pCurLeaf->uEax = RT_MIN(pCurLeaf->uEax, UINT32_C(0xc0000002));
1642 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1643 UINT32_C(0xc0000002), UINT32_C(0xc00fffff));
1644
1645 pCurLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves,
1646 UINT32_C(0xc0000001), 0);
1647 if (pCurLeaf)
1648 pCurLeaf->uEdx = 0; /* all features hidden */
1649 }
1650 else
1651 cpumR3CpuIdRemoveRange(pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves,
1652 UINT32_C(0xc0000000), UINT32_C(0xc00fffff));
1653 }
1654
1655 /*
1656 * Hypervisor identification.
1657 *
1658 * We only return minimal information, primarily ensuring that the
1659 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1660 * Currently we do not support any hypervisor-specific interface.
1661 */
1662 NewLeaf.uLeaf = UINT32_C(0x40000000);
1663 NewLeaf.uSubLeaf = 0;
1664 NewLeaf.fSubLeafMask = 0;
1665 NewLeaf.uEax = UINT32_C(0x40000001);
1666 NewLeaf.uEbx = 0x786f4256 /* 'VBox' */;
1667 NewLeaf.uEcx = 0x786f4256 /* 'VBox' */;
1668 NewLeaf.uEdx = 0x786f4256 /* 'VBox' */;
1669 NewLeaf.fFlags = 0;
1670 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1671 AssertLogRelRCReturn(rc, rc);
1672
1673 NewLeaf.uLeaf = UINT32_C(0x40000001);
1674 NewLeaf.uEax = 0x656e6f6e; /* 'none' */
1675 NewLeaf.uEbx = 0;
1676 NewLeaf.uEcx = 0;
1677 NewLeaf.uEdx = 0;
1678 NewLeaf.fFlags = 0;
1679 rc = cpumR3CpuIdInsert(&pCPUM->GuestInfo.paCpuIdLeavesR3, &pCPUM->GuestInfo.cCpuIdLeaves, &NewLeaf);
1680 AssertLogRelRCReturn(rc, rc);
1681
1682 /*
1683 * Mini CPU selection support for making Mac OS X happy.
1684 */
1685 if (pCPUM->GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL)
1686 {
1687 pStdFeatureLeaf = cpumR3CpuIdGetLeaf(pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves, 1, 0);
1688 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pStdFeatureLeaf->uEax),
1689 ASMGetCpuModelIntel(pStdFeatureLeaf->uEax),
1690 ASMGetCpuFamily(pStdFeatureLeaf->uEax),
1691 0);
1692 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1693 {
1694 uint32_t uNew = pStdFeatureLeaf->uEax & UINT32_C(0xf0003000);
1695 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1696 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1697 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1698 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1699 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1700 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1701 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1702 pStdFeatureLeaf->uEax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1703 pStdFeatureLeaf->uEax = uNew;
1704 }
1705 }
1706
1707 /*
1708 * MSR fudging.
1709 */
1710 /** @cfgm{CPUM/FudgeMSRs, boolean, true}
1711 * Fudges some common MSRs if not present in the selected CPU database entry.
1712 * This is for trying to keep VMs running when moved between different hosts
1713 * and different CPU vendors. */
1714 bool fEnable;
1715 rc = CFGMR3QueryBoolDef(pCpumCfg, "FudgeMSRs", &fEnable, true); AssertRCReturn(rc, rc);
1716 if (fEnable)
1717 {
1718 rc = cpumR3MsrApplyFudge(pVM);
1719 AssertLogRelRCReturn(rc, rc);
1720 }
1721
1722 /*
1723 * Move the MSR and CPUID arrays over on the hypervisor heap, and explode
1724 * guest CPU features again.
1725 */
1726 void *pvFree = pCPUM->GuestInfo.paCpuIdLeavesR3;
1727 int rc1 = cpumR3CpuIdInstallAndExplodeLeaves(pVM, pCPUM, pCPUM->GuestInfo.paCpuIdLeavesR3, pCPUM->GuestInfo.cCpuIdLeaves);
1728 RTMemFree(pvFree);
1729
1730 pvFree = pCPUM->GuestInfo.paMsrRangesR3;
1731 int rc2 = MMHyperDupMem(pVM, pvFree,
1732 sizeof(pCPUM->GuestInfo.paMsrRangesR3[0]) * pCPUM->GuestInfo.cMsrRanges, 32,
1733 MM_TAG_CPUM_MSRS, (void **)&pCPUM->GuestInfo.paMsrRangesR3);
1734 RTMemFree(pvFree);
1735 AssertLogRelRCReturn(rc1, rc1);
1736 AssertLogRelRCReturn(rc2, rc2);
1737
1738 pCPUM->GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1739 pCPUM->GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pCPUM->GuestInfo.paMsrRangesR3);
1740 cpumR3MsrRegStats(pVM);
1741
1742 /*
1743 * Some more configuration that we're applying at the end of everything
1744 * via the CPUMSetGuestCpuIdFeature API.
1745 */
1746
1747 /* Check if PAE was explicitely enabled by the user. */
1748 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1749 if (fEnable)
1750 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1751
1752 /* We don't normally enable NX for raw-mode, so give the user a chance to force it on. */
1753 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1754 if (fEnable)
1755 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1756
1757 /* We don't enable the Hypervisor Present bit by default, but it may be needed by some guests. */
1758 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1759 if (fEnable)
1760 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1761
1762#undef PORTABLE_DISABLE_FEATURE_BIT
1763#undef PORTABLE_CLEAR_BITS_WHEN
1764
1765 return VINF_SUCCESS;
1766}
1767
1768
1769/**
1770 * Applies relocations to data and code managed by this
1771 * component. This function will be called at init and
1772 * whenever the VMM need to relocate it self inside the GC.
1773 *
1774 * The CPUM will update the addresses used by the switcher.
1775 *
1776 * @param pVM The VM.
1777 */
1778VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1779{
1780 LogFlow(("CPUMR3Relocate\n"));
1781
1782 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1783 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1784
1785 /* Recheck the guest DRx values in raw-mode. */
1786 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1787 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1788}
1789
1790
1791/**
1792 * Apply late CPUM property changes based on the fHWVirtEx setting
1793 *
1794 * @param pVM Pointer to the VM.
1795 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1796 */
1797VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1798{
1799 /*
1800 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1801 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1802 * of processors from (cpuid(4).eax >> 26) + 1.
1803 *
1804 * Note: this code is obsolete, but let's keep it here for reference.
1805 * Purpose is valid when we artificially cap the max std id to less than 4.
1806 */
1807 if (!fHWVirtExEnabled)
1808 {
1809 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1810 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1811 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1812 }
1813}
1814
1815/**
1816 * Terminates the CPUM.
1817 *
1818 * Termination means cleaning up and freeing all resources,
1819 * the VM it self is at this point powered off or suspended.
1820 *
1821 * @returns VBox status code.
1822 * @param pVM Pointer to the VM.
1823 */
1824VMMR3DECL(int) CPUMR3Term(PVM pVM)
1825{
1826#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1827 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1828 {
1829 PVMCPU pVCpu = &pVM->aCpus[i];
1830 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1831
1832 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1833 pVCpu->cpum.s.uMagic = 0;
1834 pCtx->dr[5] = 0;
1835 }
1836#else
1837 NOREF(pVM);
1838#endif
1839 return VINF_SUCCESS;
1840}
1841
1842
1843/**
1844 * Resets a virtual CPU.
1845 *
1846 * Used by CPUMR3Reset and CPU hot plugging.
1847 *
1848 * @param pVM Pointer to the cross context VM structure.
1849 * @param pVCpu Pointer to the cross context virtual CPU structure of
1850 * the CPU that is being reset. This may differ from the
1851 * current EMT.
1852 */
1853VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1854{
1855 /** @todo anything different for VCPU > 0? */
1856 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1857
1858 /*
1859 * Initialize everything to ZERO first.
1860 */
1861 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1862 memset(pCtx, 0, sizeof(*pCtx));
1863 pVCpu->cpum.s.fUseFlags = fUseFlags;
1864
1865 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1866 pCtx->eip = 0x0000fff0;
1867 pCtx->edx = 0x00000600; /* P6 processor */
1868 pCtx->eflags.Bits.u1Reserved0 = 1;
1869
1870 pCtx->cs.Sel = 0xf000;
1871 pCtx->cs.ValidSel = 0xf000;
1872 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1873 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1874 pCtx->cs.u32Limit = 0x0000ffff;
1875 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1876 pCtx->cs.Attr.n.u1Present = 1;
1877 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1878
1879 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1880 pCtx->ds.u32Limit = 0x0000ffff;
1881 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1882 pCtx->ds.Attr.n.u1Present = 1;
1883 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1884
1885 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1886 pCtx->es.u32Limit = 0x0000ffff;
1887 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1888 pCtx->es.Attr.n.u1Present = 1;
1889 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1890
1891 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1892 pCtx->fs.u32Limit = 0x0000ffff;
1893 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1894 pCtx->fs.Attr.n.u1Present = 1;
1895 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1896
1897 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1898 pCtx->gs.u32Limit = 0x0000ffff;
1899 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1900 pCtx->gs.Attr.n.u1Present = 1;
1901 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1902
1903 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1904 pCtx->ss.u32Limit = 0x0000ffff;
1905 pCtx->ss.Attr.n.u1Present = 1;
1906 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1907 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1908
1909 pCtx->idtr.cbIdt = 0xffff;
1910 pCtx->gdtr.cbGdt = 0xffff;
1911
1912 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1913 pCtx->ldtr.u32Limit = 0xffff;
1914 pCtx->ldtr.Attr.n.u1Present = 1;
1915 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1916
1917 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1918 pCtx->tr.u32Limit = 0xffff;
1919 pCtx->tr.Attr.n.u1Present = 1;
1920 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1921
1922 pCtx->dr[6] = X86_DR6_INIT_VAL;
1923 pCtx->dr[7] = X86_DR7_INIT_VAL;
1924
1925 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1926 pCtx->fpu.FCW = 0x37f;
1927
1928 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1929 IA-32 Processor States Following Power-up, Reset, or INIT */
1930 pCtx->fpu.MXCSR = 0x1F80;
1931 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1932 supports all bits, since a zero value here should be read as 0xffbf. */
1933
1934 /*
1935 * MSRs.
1936 */
1937 /* Init PAT MSR */
1938 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1939
1940 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1941 * The Intel docs don't mention it. */
1942 Assert(!pCtx->msrEFER);
1943
1944 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1945 is supposed to be here, just trying provide useful/sensible values. */
1946 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1947 if (pRange)
1948 {
1949 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1950 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1951 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1952 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1953 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1954 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1955 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1956 }
1957
1958 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1959
1960 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1961 * called from each EMT while we're getting called by CPUMR3Reset()
1962 * iteratively on the same thread. Fix later. */
1963#if 0 /** @todo r=bird: This we will do in TM, not here. */
1964 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1965 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1966#endif
1967
1968
1969 /* C-state control. Guesses. */
1970 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1971
1972
1973 /*
1974 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1975 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1976 */
1977 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1978}
1979
1980
1981/**
1982 * Resets the CPU.
1983 *
1984 * @returns VINF_SUCCESS.
1985 * @param pVM Pointer to the VM.
1986 */
1987VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1988{
1989 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1990 {
1991 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1992
1993#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1994 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1995
1996 /* Magic marker for searching in crash dumps. */
1997 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1998 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1999 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2000#endif
2001 }
2002}
2003
2004
2005/**
2006 * Called both in pass 0 and the final pass.
2007 *
2008 * @param pVM Pointer to the VM.
2009 * @param pSSM The saved state handle.
2010 */
2011static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
2012{
2013 /*
2014 * Save all the CPU ID leaves here so we can check them for compatibility
2015 * upon loading.
2016 */
2017 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
2018 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
2019
2020 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
2021 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2022
2023 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
2024 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2025
2026 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2027
2028 /*
2029 * Save a good portion of the raw CPU IDs as well as they may come in
2030 * handy when validating features for raw mode.
2031 */
2032 CPUMCPUID aRawStd[16];
2033 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
2034 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
2035 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
2036 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
2037
2038 CPUMCPUID aRawExt[32];
2039 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
2040 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2041 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
2042 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
2043}
2044
2045
2046static int cpumR3LoadCpuIdOneGuestArray(PSSMHANDLE pSSM, uint32_t uBase, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2047{
2048 uint32_t cCpuIds;
2049 int rc = SSMR3GetU32(pSSM, &cCpuIds);
2050 if (RT_SUCCESS(rc))
2051 {
2052 if (cCpuIds < 64)
2053 {
2054 for (uint32_t i = 0; i < cCpuIds; i++)
2055 {
2056 CPUMCPUID CpuId;
2057 rc = SSMR3GetMem(pSSM, &CpuId, sizeof(CpuId));
2058 if (RT_FAILURE(rc))
2059 break;
2060
2061 CPUMCPUIDLEAF NewLeaf;
2062 NewLeaf.uLeaf = uBase + i;
2063 NewLeaf.uSubLeaf = 0;
2064 NewLeaf.fSubLeafMask = 0;
2065 NewLeaf.uEax = CpuId.eax;
2066 NewLeaf.uEbx = CpuId.ebx;
2067 NewLeaf.uEcx = CpuId.ecx;
2068 NewLeaf.uEdx = CpuId.edx;
2069 NewLeaf.fFlags = 0;
2070 rc = cpumR3CpuIdInsert(ppaLeaves, pcLeaves, &NewLeaf);
2071 }
2072 }
2073 else
2074 rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2075 }
2076 if (RT_FAILURE(rc))
2077 {
2078 RTMemFree(*ppaLeaves);
2079 *ppaLeaves = NULL;
2080 *pcLeaves = 0;
2081 }
2082 return rc;
2083}
2084
2085
2086static int cpumR3LoadCpuIdGuestArrays(PSSMHANDLE pSSM, uint32_t uVersion, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves)
2087{
2088 *ppaLeaves = NULL;
2089 *pcLeaves = 0;
2090
2091 int rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x00000000), ppaLeaves, pcLeaves);
2092 if (RT_SUCCESS(rc))
2093 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0x80000000), ppaLeaves, pcLeaves);
2094 if (RT_SUCCESS(rc))
2095 rc = cpumR3LoadCpuIdOneGuestArray(pSSM, UINT32_C(0xc0000000), ppaLeaves, pcLeaves);
2096
2097 return rc;
2098}
2099
2100
2101/**
2102 * Loads the CPU ID leaves saved by pass 0.
2103 *
2104 * @returns VBox status code.
2105 * @param pVM Pointer to the VM.
2106 * @param pSSM The saved state handle.
2107 * @param uVersion The format version.
2108 */
2109static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
2110{
2111 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
2112
2113 /*
2114 * Define a bunch of macros for simplifying the code.
2115 */
2116 /* Generic expression + failure message. */
2117#define CPUID_CHECK_RET(expr, fmt) \
2118 do { \
2119 if (!(expr)) \
2120 { \
2121 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
2122 if (fStrictCpuIdChecks) \
2123 { \
2124 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
2125 RTStrFree(pszMsg); \
2126 return rcCpuid; \
2127 } \
2128 LogRel(("CPUM: %s\n", pszMsg)); \
2129 RTStrFree(pszMsg); \
2130 } \
2131 } while (0)
2132#define CPUID_CHECK_WRN(expr, fmt) \
2133 do { \
2134 if (!(expr)) \
2135 LogRel(fmt); \
2136 } while (0)
2137
2138 /* For comparing two values and bitch if they differs. */
2139#define CPUID_CHECK2_RET(what, host, saved) \
2140 do { \
2141 if ((host) != (saved)) \
2142 { \
2143 if (fStrictCpuIdChecks) \
2144 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2145 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
2146 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2147 } \
2148 } while (0)
2149#define CPUID_CHECK2_WRN(what, host, saved) \
2150 do { \
2151 if ((host) != (saved)) \
2152 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
2153 } while (0)
2154
2155 /* For checking raw cpu features (raw mode). */
2156#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
2157 do { \
2158 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2159 { \
2160 if (fStrictCpuIdChecks) \
2161 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2162 N_(#bit " mismatch: host=%d saved=%d"), \
2163 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
2164 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2165 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2166 } \
2167 } while (0)
2168#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
2169 do { \
2170 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
2171 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
2172 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
2173 } while (0)
2174#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
2175
2176 /* For checking guest features. */
2177#define CPUID_GST_FEATURE_RET(set, reg, bit) \
2178 do { \
2179 if ( (aGuestCpuId##set [1].reg & bit) \
2180 && !(aHostRaw##set [1].reg & bit) \
2181 && !(aHostOverride##set [1].reg & bit) \
2182 ) \
2183 { \
2184 if (fStrictCpuIdChecks) \
2185 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2186 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2187 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2188 } \
2189 } while (0)
2190#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
2191 do { \
2192 if ( (aGuestCpuId##set [1].reg & bit) \
2193 && !(aHostRaw##set [1].reg & bit) \
2194 && !(aHostOverride##set [1].reg & bit) \
2195 ) \
2196 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2197 } while (0)
2198#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
2199 do { \
2200 if ( (aGuestCpuId##set [1].reg & bit) \
2201 && !(aHostRaw##set [1].reg & bit) \
2202 && !(aHostOverride##set [1].reg & bit) \
2203 ) \
2204 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2205 } while (0)
2206#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
2207
2208 /* For checking guest features if AMD guest CPU. */
2209#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
2210 do { \
2211 if ( (aGuestCpuId##set [1].reg & bit) \
2212 && fGuestAmd \
2213 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2214 && !(aHostOverride##set [1].reg & bit) \
2215 ) \
2216 { \
2217 if (fStrictCpuIdChecks) \
2218 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2219 N_(#bit " is not supported by the host but has already exposed to the guest")); \
2220 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2221 } \
2222 } while (0)
2223#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
2224 do { \
2225 if ( (aGuestCpuId##set [1].reg & bit) \
2226 && fGuestAmd \
2227 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2228 && !(aHostOverride##set [1].reg & bit) \
2229 ) \
2230 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
2231 } while (0)
2232#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
2233 do { \
2234 if ( (aGuestCpuId##set [1].reg & bit) \
2235 && fGuestAmd \
2236 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
2237 && !(aHostOverride##set [1].reg & bit) \
2238 ) \
2239 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2240 } while (0)
2241#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
2242
2243 /* For checking AMD features which have a corresponding bit in the standard
2244 range. (Intel defines very few bits in the extended feature sets.) */
2245#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
2246 do { \
2247 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2248 && !(fHostAmd \
2249 ? aHostRawExt[1].reg & (ExtBit) \
2250 : aHostRawStd[1].reg & (StdBit)) \
2251 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2252 ) \
2253 { \
2254 if (fStrictCpuIdChecks) \
2255 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
2256 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
2257 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2258 } \
2259 } while (0)
2260#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
2261 do { \
2262 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2263 && !(fHostAmd \
2264 ? aHostRawExt[1].reg & (ExtBit) \
2265 : aHostRawStd[1].reg & (StdBit)) \
2266 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2267 ) \
2268 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
2269 } while (0)
2270#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
2271 do { \
2272 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
2273 && !(fHostAmd \
2274 ? aHostRawExt[1].reg & (ExtBit) \
2275 : aHostRawStd[1].reg & (StdBit)) \
2276 && !(aHostOverrideExt[1].reg & (ExtBit)) \
2277 ) \
2278 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
2279 } while (0)
2280#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
2281
2282 /*
2283 * Load them into stack buffers first.
2284 */
2285 PCPUMCPUIDLEAF paLeaves;
2286 uint32_t cLeaves;
2287 int rc = cpumR3LoadCpuIdGuestArrays(pSSM, uVersion, &paLeaves, &cLeaves);
2288 AssertRCReturn(rc, rc);
2289
2290 /** @todo we'll be leaking paLeaves on error return... */
2291
2292 CPUMCPUID GuestCpuIdDef;
2293 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
2294 AssertRCReturn(rc, rc);
2295
2296 CPUMCPUID aRawStd[16];
2297 uint32_t cRawStd;
2298 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
2299 if (cRawStd > RT_ELEMENTS(aRawStd))
2300 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2301 rc = SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
2302 AssertRCReturn(rc, rc);
2303 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
2304 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
2305
2306 CPUMCPUID aRawExt[32];
2307 uint32_t cRawExt;
2308 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
2309 if (cRawExt > RT_ELEMENTS(aRawExt))
2310 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2311 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
2312 AssertRCReturn(rc, rc);
2313 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
2314 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
2315
2316 /*
2317 * Get the raw CPU IDs for the current host.
2318 */
2319 CPUMCPUID aHostRawStd[16];
2320 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
2321 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
2322
2323 CPUMCPUID aHostRawExt[32];
2324 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
2325 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
2326 &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
2327
2328 /*
2329 * Get the host and guest overrides so we don't reject the state because
2330 * some feature was enabled thru these interfaces.
2331 * Note! We currently only need the feature leaves, so skip rest.
2332 */
2333 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
2334 CPUMCPUID aHostOverrideStd[2];
2335 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
2336 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
2337
2338 CPUMCPUID aHostOverrideExt[2];
2339 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
2340 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
2341
2342 /*
2343 * This can be skipped.
2344 */
2345 bool fStrictCpuIdChecks;
2346 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
2347
2348
2349
2350 /*
2351 * For raw-mode we'll require that the CPUs are very similar since we don't
2352 * intercept CPUID instructions for user mode applications.
2353 */
2354 if (!HMIsEnabled(pVM))
2355 {
2356 /* CPUID(0) */
2357 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
2358 && aHostRawStd[0].ecx == aRawStd[0].ecx
2359 && aHostRawStd[0].edx == aRawStd[0].edx,
2360 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2361 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
2362 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
2363 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
2364 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2365 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2366
2367 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2368
2369 /* CPUID(1).eax */
2370 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2371 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2372 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2373
2374 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2375 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2376 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2377
2378 /* CPUID(1).ecx */
2379 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2380 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2381 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2382 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2383 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2384 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2385 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2386 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2387 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2388 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2389 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2390 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2391 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2392 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2393 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2394 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2395 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2396 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2397 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2398 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2399 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2400 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2401 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2402 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2403 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2404 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2405 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2406 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2407 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2408 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2409 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2410 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2411
2412 /* CPUID(1).edx */
2413 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2414 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2415 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2416 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2417 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2418 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2419 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2420 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2421 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2422 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2423 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2424 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2425 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2426 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2427 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2428 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2429 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2430 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2431 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2432 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2433 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2434 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2435 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2436 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2437 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2438 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2439 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2440 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2441 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2442 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2443 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2444 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2445
2446 /* CPUID(2) - config, mostly about caches. ignore. */
2447 /* CPUID(3) - processor serial number. ignore. */
2448 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2449 /* CPUID(5) - mwait/monitor config. ignore. */
2450 /* CPUID(6) - power management. ignore. */
2451 /* CPUID(7) - ???. ignore. */
2452 /* CPUID(8) - ???. ignore. */
2453 /* CPUID(9) - DCA. ignore for now. */
2454 /* CPUID(a) - PeMo info. ignore for now. */
2455 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2456
2457 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2458 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2459 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2460 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2461 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2462 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2463 {
2464 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2465 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2466 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2467 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2468 }
2469
2470 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2471 Note! Intel have/is marking many of the fields here as reserved. We
2472 will verify them as if it's an AMD CPU. */
2473 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2474 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2475 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2476 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2477 {
2478 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2479 && aHostRawExt[0].ecx == aRawExt[0].ecx
2480 && aHostRawExt[0].edx == aRawExt[0].edx,
2481 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2482 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2483 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2484 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2485
2486 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2487 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2488 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2489 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2490 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2491 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2492
2493 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2494 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2495 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2496 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2497
2498 /* CPUID(0x80000001).ecx */
2499 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2500 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2501 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2502 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2503 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2504 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2505 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2506 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2507 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2508 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2509 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2510 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2511 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2512 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2513 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2514 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2515 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2516 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2517 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2518 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2519 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2520 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2521 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2522 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2523 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2524 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2525 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2526 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2527 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2528 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2529 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2530 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2531
2532 /* CPUID(0x80000001).edx */
2533 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2534 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2535 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2536 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2537 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2538 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2539 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2540 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2541 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2542 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2543 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2544 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2545 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2546 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2547 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2548 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2549 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2550 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2551 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2552 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2553 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2554 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2555 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2556 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2557 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2558 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2559 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2560 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2561 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2562 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2563 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2564 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2565
2566 /** @todo verify the rest as well. */
2567 }
2568 }
2569
2570
2571
2572 /*
2573 * Verify that we can support the features already exposed to the guest on
2574 * this host.
2575 *
2576 * Most of the features we're emulating requires intercepting instruction
2577 * and doing it the slow way, so there is no need to warn when they aren't
2578 * present in the host CPU. Thus we use IGN instead of EMU on these.
2579 *
2580 * Trailing comments:
2581 * "EMU" - Possible to emulate, could be lots of work and very slow.
2582 * "EMU?" - Can this be emulated?
2583 */
2584 CPUMCPUID aGuestCpuIdStd[2];
2585 RT_ZERO(aGuestCpuIdStd);
2586 cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, 1, 0, &aGuestCpuIdStd[1]);
2587
2588 /* CPUID(1).ecx */
2589 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2590 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2591 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2592 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2593 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2594 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2595 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2596 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2597 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2598 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2599 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2600 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2601 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2602 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2603 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2604 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2605 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2606 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2607 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2608 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2609 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2610 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2611 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2612 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2613 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2614 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2615 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2616 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2617 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2618 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2619 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2620 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2621
2622 /* CPUID(1).edx */
2623 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2624 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2625 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2626 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2627 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2628 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2629 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2630 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2631 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2632 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2633 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2634 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2635 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2636 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2637 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2638 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2639 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2640 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2641 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2642 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2643 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2644 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2645 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2646 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2647 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2648 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2649 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2650 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2651 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2652 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2653 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2654 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2655
2656 /* CPUID(0x80000000). */
2657 CPUMCPUID aGuestCpuIdExt[2];
2658 RT_ZERO(aGuestCpuIdExt);
2659 if (cpumR3CpuIdGetLeafLegacy(paLeaves, cLeaves, UINT32_C(0x80000001), 0, &aGuestCpuIdExt[1]))
2660 {
2661 /** @todo deal with no 0x80000001 on the host. */
2662 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2663 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2664
2665 /* CPUID(0x80000001).ecx */
2666 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2667 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2668 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2669 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2670 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2671 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2672 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2673 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2674 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2675 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2676 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2677 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2678 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2679 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2680 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2681 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2682 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2683 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2684 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2685 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2686 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2687 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2688 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2689 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2690 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2691 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2692 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2693 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2694 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2695 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2696 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2697 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2698
2699 /* CPUID(0x80000001).edx */
2700 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2701 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2702 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2703 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2704 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2705 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2706 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2707 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2708 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2709 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2710 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2711 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2712 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2713 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2714 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2715 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2716 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2717 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2718 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2719 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2720 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2721 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2722 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2723 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2724 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2725 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2726 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2727 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2728 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2729 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2730 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2731 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2732 }
2733
2734 /*
2735 * We're good, commit the CPU ID leaves.
2736 */
2737 MMHyperFree(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2738 pVM->cpum.s.GuestInfo.paCpuIdLeavesR0 = NIL_RTR0PTR;
2739 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = NIL_RTRCPTR;
2740 pVM->cpum.s.GuestInfo.DefCpuId = GuestCpuIdDef;
2741 rc = cpumR3CpuIdInstallAndExplodeLeaves(pVM, &pVM->cpum.s, paLeaves, cLeaves);
2742 RTMemFree(paLeaves);
2743 AssertLogRelRCReturn(rc, rc);
2744
2745
2746#undef CPUID_CHECK_RET
2747#undef CPUID_CHECK_WRN
2748#undef CPUID_CHECK2_RET
2749#undef CPUID_CHECK2_WRN
2750#undef CPUID_RAW_FEATURE_RET
2751#undef CPUID_RAW_FEATURE_WRN
2752#undef CPUID_RAW_FEATURE_IGN
2753#undef CPUID_GST_FEATURE_RET
2754#undef CPUID_GST_FEATURE_WRN
2755#undef CPUID_GST_FEATURE_EMU
2756#undef CPUID_GST_FEATURE_IGN
2757#undef CPUID_GST_FEATURE2_RET
2758#undef CPUID_GST_FEATURE2_WRN
2759#undef CPUID_GST_FEATURE2_EMU
2760#undef CPUID_GST_FEATURE2_IGN
2761#undef CPUID_GST_AMD_FEATURE_RET
2762#undef CPUID_GST_AMD_FEATURE_WRN
2763#undef CPUID_GST_AMD_FEATURE_EMU
2764#undef CPUID_GST_AMD_FEATURE_IGN
2765
2766 return VINF_SUCCESS;
2767}
2768
2769
2770/**
2771 * Pass 0 live exec callback.
2772 *
2773 * @returns VINF_SSM_DONT_CALL_AGAIN.
2774 * @param pVM Pointer to the VM.
2775 * @param pSSM The saved state handle.
2776 * @param uPass The pass (0).
2777 */
2778static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2779{
2780 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2781 cpumR3SaveCpuId(pVM, pSSM);
2782 return VINF_SSM_DONT_CALL_AGAIN;
2783}
2784
2785
2786/**
2787 * Execute state save operation.
2788 *
2789 * @returns VBox status code.
2790 * @param pVM Pointer to the VM.
2791 * @param pSSM SSM operation handle.
2792 */
2793static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2794{
2795 /*
2796 * Save.
2797 */
2798 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2799 {
2800 PVMCPU pVCpu = &pVM->aCpus[i];
2801 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2802 }
2803
2804 SSMR3PutU32(pSSM, pVM->cCpus);
2805 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2806 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2807 {
2808 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2809
2810 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2811 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2812 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2813 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2814 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2815 }
2816
2817 cpumR3SaveCpuId(pVM, pSSM);
2818 return VINF_SUCCESS;
2819}
2820
2821
2822/**
2823 * @copydoc FNSSMINTLOADPREP
2824 */
2825static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2826{
2827 NOREF(pSSM);
2828 pVM->cpum.s.fPendingRestore = true;
2829 return VINF_SUCCESS;
2830}
2831
2832
2833/**
2834 * @copydoc FNSSMINTLOADEXEC
2835 */
2836static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2837{
2838 /*
2839 * Validate version.
2840 */
2841 if ( uVersion != CPUM_SAVED_STATE_VERSION
2842 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2843 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2844 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2845 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2846 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2847 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2848 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2849 {
2850 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2851 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2852 }
2853
2854 if (uPass == SSM_PASS_FINAL)
2855 {
2856 /*
2857 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2858 * really old SSM file versions.)
2859 */
2860 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2861 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2862 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2863 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2864
2865 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2866 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2867 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2868 paCpumCtxFields = g_aCpumCtxFieldsV16;
2869 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2870 paCpumCtxFields = g_aCpumCtxFieldsMem;
2871
2872 /*
2873 * Restore.
2874 */
2875 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2876 {
2877 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2878 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2879 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2880 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2881 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2882 pVCpu->cpum.s.Hyper.rsp = uRSP;
2883 }
2884
2885 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2886 {
2887 uint32_t cCpus;
2888 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2889 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2890 VERR_SSM_UNEXPECTED_DATA);
2891 }
2892 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2893 || pVM->cCpus == 1,
2894 ("cCpus=%u\n", pVM->cCpus),
2895 VERR_SSM_UNEXPECTED_DATA);
2896
2897 uint32_t cbMsrs = 0;
2898 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2899 {
2900 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2901 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2902 VERR_SSM_UNEXPECTED_DATA);
2903 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2904 VERR_SSM_UNEXPECTED_DATA);
2905 }
2906
2907 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2908 {
2909 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2910 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2911 paCpumCtxFields, NULL);
2912 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2913 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2914 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2915 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2916 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2917 {
2918 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2919 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2920 }
2921
2922 /* REM and other may have cleared must-be-one fields in DR6 and
2923 DR7, fix these. */
2924 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2925 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2926 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2927 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2928 }
2929
2930 /* Older states does not have the internal selector register flags
2931 and valid selector value. Supply those. */
2932 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2933 {
2934 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2935 {
2936 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2937 bool const fValid = HMIsEnabled(pVM)
2938 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2939 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2940 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2941 if (fValid)
2942 {
2943 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2944 {
2945 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2946 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2947 }
2948
2949 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2950 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2951 }
2952 else
2953 {
2954 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2955 {
2956 paSelReg[iSelReg].fFlags = 0;
2957 paSelReg[iSelReg].ValidSel = 0;
2958 }
2959
2960 /* This might not be 104% correct, but I think it's close
2961 enough for all practical purposes... (REM always loaded
2962 LDTR registers.) */
2963 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2964 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2965 }
2966 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2967 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2968 }
2969 }
2970
2971 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2972 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2973 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2974 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2975 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2976
2977 /*
2978 * A quick sanity check.
2979 */
2980 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2981 {
2982 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2983 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2984 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2985 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2986 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2987 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2988 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2989 }
2990 }
2991
2992 pVM->cpum.s.fPendingRestore = false;
2993
2994 /*
2995 * Guest CPUIDs.
2996 */
2997 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2998 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2999
3000 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
3001 * actually required. */
3002
3003 /*
3004 * Restore the CPUID leaves.
3005 *
3006 * Note that we support restoring less than the current amount of standard
3007 * leaves because we've been allowed more is newer version of VBox.
3008 */
3009 uint32_t cElements;
3010 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3011 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3012 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3013 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
3014
3015 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3016 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
3017 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3018 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
3019
3020 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
3021 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
3022 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3023 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
3024
3025 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
3026
3027 /*
3028 * Check that the basic cpuid id information is unchanged.
3029 */
3030 /** @todo we should check the 64 bits capabilities too! */
3031 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
3032 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
3033 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
3034 uint32_t au32CpuIdSaved[8];
3035 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
3036 if (RT_SUCCESS(rc))
3037 {
3038 /* Ignore CPU stepping. */
3039 au32CpuId[4] &= 0xfffffff0;
3040 au32CpuIdSaved[4] &= 0xfffffff0;
3041
3042 /* Ignore APIC ID (AMD specs). */
3043 au32CpuId[5] &= ~0xff000000;
3044 au32CpuIdSaved[5] &= ~0xff000000;
3045
3046 /* Ignore the number of Logical CPUs (AMD specs). */
3047 au32CpuId[5] &= ~0x00ff0000;
3048 au32CpuIdSaved[5] &= ~0x00ff0000;
3049
3050 /* Ignore some advanced capability bits, that we don't expose to the guest. */
3051 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3052 | X86_CPUID_FEATURE_ECX_VMX
3053 | X86_CPUID_FEATURE_ECX_SMX
3054 | X86_CPUID_FEATURE_ECX_EST
3055 | X86_CPUID_FEATURE_ECX_TM2
3056 | X86_CPUID_FEATURE_ECX_CNTXID
3057 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3058 | X86_CPUID_FEATURE_ECX_PDCM
3059 | X86_CPUID_FEATURE_ECX_DCA
3060 | X86_CPUID_FEATURE_ECX_X2APIC
3061 );
3062 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
3063 | X86_CPUID_FEATURE_ECX_VMX
3064 | X86_CPUID_FEATURE_ECX_SMX
3065 | X86_CPUID_FEATURE_ECX_EST
3066 | X86_CPUID_FEATURE_ECX_TM2
3067 | X86_CPUID_FEATURE_ECX_CNTXID
3068 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3069 | X86_CPUID_FEATURE_ECX_PDCM
3070 | X86_CPUID_FEATURE_ECX_DCA
3071 | X86_CPUID_FEATURE_ECX_X2APIC
3072 );
3073
3074 /* Make sure we don't forget to update the masks when enabling
3075 * features in the future.
3076 */
3077 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
3078 ( X86_CPUID_FEATURE_ECX_DTES64
3079 | X86_CPUID_FEATURE_ECX_VMX
3080 | X86_CPUID_FEATURE_ECX_SMX
3081 | X86_CPUID_FEATURE_ECX_EST
3082 | X86_CPUID_FEATURE_ECX_TM2
3083 | X86_CPUID_FEATURE_ECX_CNTXID
3084 | X86_CPUID_FEATURE_ECX_TPRUPDATE
3085 | X86_CPUID_FEATURE_ECX_PDCM
3086 | X86_CPUID_FEATURE_ECX_DCA
3087 | X86_CPUID_FEATURE_ECX_X2APIC
3088 )));
3089 /* do the compare */
3090 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
3091 {
3092 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
3093 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
3094 "Saved=%.*Rhxs\n"
3095 "Real =%.*Rhxs\n",
3096 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3097 sizeof(au32CpuId), au32CpuId));
3098 else
3099 {
3100 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
3101 "Saved=%.*Rhxs\n"
3102 "Real =%.*Rhxs\n",
3103 sizeof(au32CpuIdSaved), au32CpuIdSaved,
3104 sizeof(au32CpuId), au32CpuId));
3105 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
3106 }
3107 }
3108 }
3109
3110 return rc;
3111}
3112
3113
3114/**
3115 * @copydoc FNSSMINTLOADPREP
3116 */
3117static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3118{
3119 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3120 return VINF_SUCCESS;
3121
3122 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3123 if (pVM->cpum.s.fPendingRestore)
3124 {
3125 LogRel(("CPUM: Missing state!\n"));
3126 return VERR_INTERNAL_ERROR_2;
3127 }
3128
3129 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3130 {
3131 /* Notify PGM of the NXE states in case they've changed. */
3132 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3133
3134 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
3135 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
3136 }
3137 return VINF_SUCCESS;
3138}
3139
3140
3141/**
3142 * Checks if the CPUM state restore is still pending.
3143 *
3144 * @returns true / false.
3145 * @param pVM Pointer to the VM.
3146 */
3147VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3148{
3149 return pVM->cpum.s.fPendingRestore;
3150}
3151
3152
3153/**
3154 * Formats the EFLAGS value into mnemonics.
3155 *
3156 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3157 * @param efl The EFLAGS value.
3158 */
3159static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3160{
3161 /*
3162 * Format the flags.
3163 */
3164 static const struct
3165 {
3166 const char *pszSet; const char *pszClear; uint32_t fFlag;
3167 } s_aFlags[] =
3168 {
3169 { "vip",NULL, X86_EFL_VIP },
3170 { "vif",NULL, X86_EFL_VIF },
3171 { "ac", NULL, X86_EFL_AC },
3172 { "vm", NULL, X86_EFL_VM },
3173 { "rf", NULL, X86_EFL_RF },
3174 { "nt", NULL, X86_EFL_NT },
3175 { "ov", "nv", X86_EFL_OF },
3176 { "dn", "up", X86_EFL_DF },
3177 { "ei", "di", X86_EFL_IF },
3178 { "tf", NULL, X86_EFL_TF },
3179 { "nt", "pl", X86_EFL_SF },
3180 { "nz", "zr", X86_EFL_ZF },
3181 { "ac", "na", X86_EFL_AF },
3182 { "po", "pe", X86_EFL_PF },
3183 { "cy", "nc", X86_EFL_CF },
3184 };
3185 char *psz = pszEFlags;
3186 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3187 {
3188 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3189 if (pszAdd)
3190 {
3191 strcpy(psz, pszAdd);
3192 psz += strlen(pszAdd);
3193 *psz++ = ' ';
3194 }
3195 }
3196 psz[-1] = '\0';
3197}
3198
3199
3200/**
3201 * Formats a full register dump.
3202 *
3203 * @param pVM Pointer to the VM.
3204 * @param pCtx The context to format.
3205 * @param pCtxCore The context core to format.
3206 * @param pHlp Output functions.
3207 * @param enmType The dump type.
3208 * @param pszPrefix Register name prefix.
3209 */
3210static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3211 const char *pszPrefix)
3212{
3213 NOREF(pVM);
3214
3215 /*
3216 * Format the EFLAGS.
3217 */
3218 uint32_t efl = pCtxCore->eflags.u32;
3219 char szEFlags[80];
3220 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3221
3222 /*
3223 * Format the registers.
3224 */
3225 switch (enmType)
3226 {
3227 case CPUMDUMPTYPE_TERSE:
3228 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3229 pHlp->pfnPrintf(pHlp,
3230 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3231 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3232 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3233 "%sr14=%016RX64 %sr15=%016RX64\n"
3234 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3235 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3236 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3237 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3238 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3239 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3240 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3241 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3242 else
3243 pHlp->pfnPrintf(pHlp,
3244 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3245 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3246 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3247 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3248 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3249 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3250 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3251 break;
3252
3253 case CPUMDUMPTYPE_DEFAULT:
3254 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3255 pHlp->pfnPrintf(pHlp,
3256 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3257 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3258 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3259 "%sr14=%016RX64 %sr15=%016RX64\n"
3260 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3261 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3262 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3263 ,
3264 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3265 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3266 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3267 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3268 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3269 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3270 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3271 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3272 else
3273 pHlp->pfnPrintf(pHlp,
3274 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3275 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3276 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3277 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3278 ,
3279 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3280 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3281 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3282 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3283 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3284 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3285 break;
3286
3287 case CPUMDUMPTYPE_VERBOSE:
3288 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3289 pHlp->pfnPrintf(pHlp,
3290 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3291 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3292 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3293 "%sr14=%016RX64 %sr15=%016RX64\n"
3294 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3295 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3296 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3297 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3298 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3299 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3300 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3301 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3302 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3303 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3304 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3305 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3306 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3307 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3308 ,
3309 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3310 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3311 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3312 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3313 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3314 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3315 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3316 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3317 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3318 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3319 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3320 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3321 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3322 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3323 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3324 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3325 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3326 else
3327 pHlp->pfnPrintf(pHlp,
3328 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3329 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3330 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3331 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3332 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3333 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3334 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3335 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3336 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3337 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3338 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3339 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3340 ,
3341 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3342 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3343 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3344 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3345 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3346 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3347 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3348 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3349 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3350 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3351 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3352 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3353
3354 pHlp->pfnPrintf(pHlp,
3355 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3356 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3357 ,
3358 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
3359 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
3360 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
3361 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
3362 );
3363 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
3364 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
3365 {
3366 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
3367 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
3368 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
3369 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
3370 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
3371 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
3372 /** @todo This isn't entirenly correct and needs more work! */
3373 pHlp->pfnPrintf(pHlp,
3374 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3375 pszPrefix, iST, pszPrefix, iFPR,
3376 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3377 uTag, chSign, iInteger, u64Fraction, uExponent);
3378 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3379 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3380 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3381 else
3382 pHlp->pfnPrintf(pHlp, "\n");
3383 }
3384 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3385 pHlp->pfnPrintf(pHlp,
3386 iXMM & 1
3387 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3388 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3389 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3390 pCtx->fpu.aXMM[iXMM].au32[3],
3391 pCtx->fpu.aXMM[iXMM].au32[2],
3392 pCtx->fpu.aXMM[iXMM].au32[1],
3393 pCtx->fpu.aXMM[iXMM].au32[0]);
3394 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3395 if (pCtx->fpu.au32RsrvdRest[i])
3396 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3397 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3398
3399 pHlp->pfnPrintf(pHlp,
3400 "%sEFER =%016RX64\n"
3401 "%sPAT =%016RX64\n"
3402 "%sSTAR =%016RX64\n"
3403 "%sCSTAR =%016RX64\n"
3404 "%sLSTAR =%016RX64\n"
3405 "%sSFMASK =%016RX64\n"
3406 "%sKERNELGSBASE =%016RX64\n",
3407 pszPrefix, pCtx->msrEFER,
3408 pszPrefix, pCtx->msrPAT,
3409 pszPrefix, pCtx->msrSTAR,
3410 pszPrefix, pCtx->msrCSTAR,
3411 pszPrefix, pCtx->msrLSTAR,
3412 pszPrefix, pCtx->msrSFMASK,
3413 pszPrefix, pCtx->msrKERNELGSBASE);
3414 break;
3415 }
3416}
3417
3418
3419/**
3420 * Display all cpu states and any other cpum info.
3421 *
3422 * @param pVM Pointer to the VM.
3423 * @param pHlp The info helper functions.
3424 * @param pszArgs Arguments, ignored.
3425 */
3426static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3427{
3428 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3429 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3430 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3431 cpumR3InfoHost(pVM, pHlp, pszArgs);
3432}
3433
3434
3435/**
3436 * Parses the info argument.
3437 *
3438 * The argument starts with 'verbose', 'terse' or 'default' and then
3439 * continues with the comment string.
3440 *
3441 * @param pszArgs The pointer to the argument string.
3442 * @param penmType Where to store the dump type request.
3443 * @param ppszComment Where to store the pointer to the comment string.
3444 */
3445static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3446{
3447 if (!pszArgs)
3448 {
3449 *penmType = CPUMDUMPTYPE_DEFAULT;
3450 *ppszComment = "";
3451 }
3452 else
3453 {
3454 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3455 {
3456 pszArgs += 7;
3457 *penmType = CPUMDUMPTYPE_VERBOSE;
3458 }
3459 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3460 {
3461 pszArgs += 5;
3462 *penmType = CPUMDUMPTYPE_TERSE;
3463 }
3464 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3465 {
3466 pszArgs += 7;
3467 *penmType = CPUMDUMPTYPE_DEFAULT;
3468 }
3469 else
3470 *penmType = CPUMDUMPTYPE_DEFAULT;
3471 *ppszComment = RTStrStripL(pszArgs);
3472 }
3473}
3474
3475
3476/**
3477 * Display the guest cpu state.
3478 *
3479 * @param pVM Pointer to the VM.
3480 * @param pHlp The info helper functions.
3481 * @param pszArgs Arguments, ignored.
3482 */
3483static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3484{
3485 CPUMDUMPTYPE enmType;
3486 const char *pszComment;
3487 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3488
3489 /* @todo SMP support! */
3490 PVMCPU pVCpu = VMMGetCpu(pVM);
3491 if (!pVCpu)
3492 pVCpu = &pVM->aCpus[0];
3493
3494 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3495
3496 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3497 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3498}
3499
3500
3501/**
3502 * Display the current guest instruction
3503 *
3504 * @param pVM Pointer to the VM.
3505 * @param pHlp The info helper functions.
3506 * @param pszArgs Arguments, ignored.
3507 */
3508static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3509{
3510 NOREF(pszArgs);
3511
3512 /** @todo SMP support! */
3513 PVMCPU pVCpu = VMMGetCpu(pVM);
3514 if (!pVCpu)
3515 pVCpu = &pVM->aCpus[0];
3516
3517 char szInstruction[256];
3518 szInstruction[0] = '\0';
3519 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3520 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3521}
3522
3523
3524/**
3525 * Display the hypervisor cpu state.
3526 *
3527 * @param pVM Pointer to the VM.
3528 * @param pHlp The info helper functions.
3529 * @param pszArgs Arguments, ignored.
3530 */
3531static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3532{
3533 CPUMDUMPTYPE enmType;
3534 const char *pszComment;
3535 /* @todo SMP */
3536 PVMCPU pVCpu = &pVM->aCpus[0];
3537
3538 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3539 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3540 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3541 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3542}
3543
3544
3545/**
3546 * Display the host cpu state.
3547 *
3548 * @param pVM Pointer to the VM.
3549 * @param pHlp The info helper functions.
3550 * @param pszArgs Arguments, ignored.
3551 */
3552static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3553{
3554 CPUMDUMPTYPE enmType;
3555 const char *pszComment;
3556 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3557 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3558
3559 /*
3560 * Format the EFLAGS.
3561 */
3562 /* @todo SMP */
3563 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3564#if HC_ARCH_BITS == 32
3565 uint32_t efl = pCtx->eflags.u32;
3566#else
3567 uint64_t efl = pCtx->rflags;
3568#endif
3569 char szEFlags[80];
3570 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3571
3572 /*
3573 * Format the registers.
3574 */
3575#if HC_ARCH_BITS == 32
3576# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3577 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3578# endif
3579 {
3580 pHlp->pfnPrintf(pHlp,
3581 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3582 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3583 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3584 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3585 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3586 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3587 ,
3588 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3589 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3590 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3591 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3592 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3593 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3594 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3595 }
3596# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3597 else
3598# endif
3599#endif
3600#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3601 {
3602 pHlp->pfnPrintf(pHlp,
3603 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3604 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3605 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3606 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3607 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3608 "r14=%016RX64 r15=%016RX64\n"
3609 "iopl=%d %31s\n"
3610 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3611 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3612 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3613 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3614 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3615 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3616 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3617 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3618 ,
3619 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3620 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3621 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3622 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3623 pCtx->r11, pCtx->r12, pCtx->r13,
3624 pCtx->r14, pCtx->r15,
3625 X86_EFL_GET_IOPL(efl), szEFlags,
3626 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3627 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3628 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3629 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3630 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3631 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3632 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3633 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3634 }
3635#endif
3636}
3637
3638
3639/**
3640 * Get L1 cache / TLS associativity.
3641 */
3642static const char *getCacheAss(unsigned u, char *pszBuf)
3643{
3644 if (u == 0)
3645 return "res0 ";
3646 if (u == 1)
3647 return "direct";
3648 if (u == 255)
3649 return "fully";
3650 if (u >= 256)
3651 return "???";
3652
3653 RTStrPrintf(pszBuf, 16, "%d way", u);
3654 return pszBuf;
3655}
3656
3657
3658/**
3659 * Get L2 cache associativity.
3660 */
3661const char *getL2CacheAss(unsigned u)
3662{
3663 switch (u)
3664 {
3665 case 0: return "off ";
3666 case 1: return "direct";
3667 case 2: return "2 way ";
3668 case 3: return "res3 ";
3669 case 4: return "4 way ";
3670 case 5: return "res5 ";
3671 case 6: return "8 way ";
3672 case 7: return "res7 ";
3673 case 8: return "16 way";
3674 case 9: return "res9 ";
3675 case 10: return "res10 ";
3676 case 11: return "res11 ";
3677 case 12: return "res12 ";
3678 case 13: return "res13 ";
3679 case 14: return "res14 ";
3680 case 15: return "fully ";
3681 default: return "????";
3682 }
3683}
3684
3685
3686/**
3687 * Display the guest CpuId leaves.
3688 *
3689 * @param pVM Pointer to the VM.
3690 * @param pHlp The info helper functions.
3691 * @param pszArgs "terse", "default" or "verbose".
3692 */
3693static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3694{
3695 /*
3696 * Parse the argument.
3697 */
3698 unsigned iVerbosity = 1;
3699 if (pszArgs)
3700 {
3701 pszArgs = RTStrStripL(pszArgs);
3702 if (!strcmp(pszArgs, "terse"))
3703 iVerbosity--;
3704 else if (!strcmp(pszArgs, "verbose"))
3705 iVerbosity++;
3706 }
3707
3708 /*
3709 * Start cracking.
3710 */
3711 CPUMCPUID Host;
3712 CPUMCPUID Guest;
3713 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3714
3715 uint32_t cStdHstMax;
3716 uint32_t dummy;
3717 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3718
3719 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3720
3721 pHlp->pfnPrintf(pHlp,
3722 " RAW Standard CPUIDs\n"
3723 " Function eax ebx ecx edx\n");
3724 for (unsigned i = 0; i <= cStdLstMax ; i++)
3725 {
3726 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3727 {
3728 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3729 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3730
3731 pHlp->pfnPrintf(pHlp,
3732 "Gst: %08x %08x %08x %08x %08x%s\n"
3733 "Hst: %08x %08x %08x %08x\n",
3734 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3735 i <= cStdMax ? "" : "*",
3736 Host.eax, Host.ebx, Host.ecx, Host.edx);
3737 }
3738 else
3739 {
3740 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3741
3742 pHlp->pfnPrintf(pHlp,
3743 "Hst: %08x %08x %08x %08x %08x\n",
3744 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3745 }
3746 }
3747
3748 /*
3749 * If verbose, decode it.
3750 */
3751 if (iVerbosity)
3752 {
3753 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3754 pHlp->pfnPrintf(pHlp,
3755 "Name: %.04s%.04s%.04s\n"
3756 "Supports: 0-%x\n",
3757 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3758 }
3759
3760 /*
3761 * Get Features.
3762 */
3763 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3764 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3765 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3766 if (cStdMax >= 1 && iVerbosity)
3767 {
3768 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3769
3770 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3771 uint32_t uEAX = Guest.eax;
3772
3773 pHlp->pfnPrintf(pHlp,
3774 "Family: %d \tExtended: %d \tEffective: %d\n"
3775 "Model: %d \tExtended: %d \tEffective: %d\n"
3776 "Stepping: %d\n"
3777 "Type: %d (%s)\n"
3778 "APIC ID: %#04x\n"
3779 "Logical CPUs: %d\n"
3780 "CLFLUSH Size: %d\n"
3781 "Brand ID: %#04x\n",
3782 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3783 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3784 ASMGetCpuStepping(uEAX),
3785 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3786 (Guest.ebx >> 24) & 0xff,
3787 (Guest.ebx >> 16) & 0xff,
3788 (Guest.ebx >> 8) & 0xff,
3789 (Guest.ebx >> 0) & 0xff);
3790 if (iVerbosity == 1)
3791 {
3792 uint32_t uEDX = Guest.edx;
3793 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3794 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3795 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3796 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3797 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3798 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3799 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3800 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3801 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3802 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3803 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3804 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3805 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3806 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3807 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3808 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3809 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3810 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3811 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3812 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3813 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3814 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3815 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3816 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3817 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3818 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3819 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3820 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3821 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3822 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3823 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3824 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3825 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3826 pHlp->pfnPrintf(pHlp, "\n");
3827
3828 uint32_t uECX = Guest.ecx;
3829 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3830 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3831 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3832 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3833 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3834 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3835 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3836 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3837 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3838 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3839 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3840 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3841 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3842 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3843 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3844 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3845 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3846 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3847 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3848 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3849 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3850 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3851 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3852 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3853 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3854 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3855 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3856 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3857 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3858 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3859 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " F16C");
3860 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " RDRAND");
3861 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " HVP");
3862 pHlp->pfnPrintf(pHlp, "\n");
3863 }
3864 else
3865 {
3866 ASMCpuIdExSlow(1, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3867
3868 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3869 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3870 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3871 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3872
3873 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3874 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3875 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3876 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3877 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3878 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3879 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3880 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3881 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3882 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3883 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3884 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3885 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3886 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3887 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3888 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3889 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3890 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3891 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3892 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3893 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3894 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3895 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3896 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3897 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3898 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3899 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3900 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3901 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3902 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3903 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3904 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3905 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3906
3907 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3908 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3909 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3910 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3911 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3912 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3913 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3914 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3915 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3916 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3917 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3918 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3919 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3920 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3921 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3922 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3923 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3924 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3925 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3926 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3927 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3928 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3929 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3930 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3931 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3932 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3933 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3934 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3935 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3936 pHlp->pfnPrintf(pHlp, "16-bit floating point conversion instr = %d (%d)\n", EcxGuest.u1F16C, EcxHost.u1F16C);
3937 pHlp->pfnPrintf(pHlp, "RDRAND instruction = %d (%d)\n", EcxGuest.u1RDRAND, EcxHost.u1RDRAND);
3938 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3939 }
3940 }
3941 if (cStdMax >= 2 && iVerbosity)
3942 {
3943 /** @todo */
3944 }
3945
3946 /*
3947 * Extended.
3948 * Implemented after AMD specs.
3949 */
3950 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3951
3952 pHlp->pfnPrintf(pHlp,
3953 "\n"
3954 " RAW Extended CPUIDs\n"
3955 " Function eax ebx ecx edx\n");
3956 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3957 {
3958 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3959 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3960
3961 pHlp->pfnPrintf(pHlp,
3962 "Gst: %08x %08x %08x %08x %08x%s\n"
3963 "Hst: %08x %08x %08x %08x\n",
3964 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3965 i <= cExtMax ? "" : "*",
3966 Host.eax, Host.ebx, Host.ecx, Host.edx);
3967 }
3968
3969 /*
3970 * Understandable output
3971 */
3972 if (iVerbosity)
3973 {
3974 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3975 pHlp->pfnPrintf(pHlp,
3976 "Ext Name: %.4s%.4s%.4s\n"
3977 "Ext Supports: 0x80000000-%#010x\n",
3978 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3979 }
3980
3981 if (iVerbosity && cExtMax >= 1)
3982 {
3983 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3984 uint32_t uEAX = Guest.eax;
3985 pHlp->pfnPrintf(pHlp,
3986 "Family: %d \tExtended: %d \tEffective: %d\n"
3987 "Model: %d \tExtended: %d \tEffective: %d\n"
3988 "Stepping: %d\n"
3989 "Brand ID: %#05x\n",
3990 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3991 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3992 ASMGetCpuStepping(uEAX),
3993 Guest.ebx & 0xfff);
3994
3995 if (iVerbosity == 1)
3996 {
3997 uint32_t uEDX = Guest.edx;
3998 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3999 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
4000 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
4001 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
4002 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
4003 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
4004 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
4005 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
4006 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
4007 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
4008 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
4009 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
4010 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
4011 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
4012 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
4013 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
4014 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
4015 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
4016 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
4017 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
4018 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
4019 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
4020 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
4021 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
4022 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
4023 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
4024 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
4025 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
4026 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
4027 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
4028 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
4029 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
4030 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
4031 pHlp->pfnPrintf(pHlp, "\n");
4032
4033 uint32_t uECX = Guest.ecx;
4034 pHlp->pfnPrintf(pHlp, "Features ECX: ");
4035 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
4036 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
4037 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
4038 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
4039 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
4040 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
4041 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
4042 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
4043 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
4044 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
4045 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
4046 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
4047 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
4048 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
4049 for (unsigned iBit = 5; iBit < 32; iBit++)
4050 if (uECX & RT_BIT(iBit))
4051 pHlp->pfnPrintf(pHlp, " %d", iBit);
4052 pHlp->pfnPrintf(pHlp, "\n");
4053 }
4054 else
4055 {
4056 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4057
4058 uint32_t uEdxGst = Guest.edx;
4059 uint32_t uEdxHst = Host.edx;
4060 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4061 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4062 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4063 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4064 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4065 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4066 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4067 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4068 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4069 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4070 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4071 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4072 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4073 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4074 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4075 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4076 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4077 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4078 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4079 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4080 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4081 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4082 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4083 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4084 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4085 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4086 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4087 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4088 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
4089 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
4090 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
4091 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
4092 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
4093
4094 uint32_t uEcxGst = Guest.ecx;
4095 uint32_t uEcxHst = Host.ecx;
4096 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
4097 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
4098 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
4099 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
4100 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
4101 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
4102 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
4103 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
4104 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
4105 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
4106 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
4107 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
4108 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
4109 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
4110 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
4111 }
4112 }
4113
4114 if (iVerbosity && cExtMax >= 2)
4115 {
4116 char szString[4*4*3+1] = {0};
4117 uint32_t *pu32 = (uint32_t *)szString;
4118 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
4119 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
4120 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
4121 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
4122 if (cExtMax >= 3)
4123 {
4124 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
4125 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
4126 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
4127 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
4128 }
4129 if (cExtMax >= 4)
4130 {
4131 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
4132 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
4133 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
4134 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
4135 }
4136 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
4137 }
4138
4139 if (iVerbosity && cExtMax >= 5)
4140 {
4141 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
4142 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
4143 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
4144 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
4145 char sz1[32];
4146 char sz2[32];
4147
4148 pHlp->pfnPrintf(pHlp,
4149 "TLB 2/4M Instr/Uni: %s %3d entries\n"
4150 "TLB 2/4M Data: %s %3d entries\n",
4151 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
4152 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
4153 pHlp->pfnPrintf(pHlp,
4154 "TLB 4K Instr/Uni: %s %3d entries\n"
4155 "TLB 4K Data: %s %3d entries\n",
4156 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
4157 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
4158 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
4159 "L1 Instr Cache Lines Per Tag: %d\n"
4160 "L1 Instr Cache Associativity: %s\n"
4161 "L1 Instr Cache Size: %d KB\n",
4162 (uEDX >> 0) & 0xff,
4163 (uEDX >> 8) & 0xff,
4164 getCacheAss((uEDX >> 16) & 0xff, sz1),
4165 (uEDX >> 24) & 0xff);
4166 pHlp->pfnPrintf(pHlp,
4167 "L1 Data Cache Line Size: %d bytes\n"
4168 "L1 Data Cache Lines Per Tag: %d\n"
4169 "L1 Data Cache Associativity: %s\n"
4170 "L1 Data Cache Size: %d KB\n",
4171 (uECX >> 0) & 0xff,
4172 (uECX >> 8) & 0xff,
4173 getCacheAss((uECX >> 16) & 0xff, sz1),
4174 (uECX >> 24) & 0xff);
4175 }
4176
4177 if (iVerbosity && cExtMax >= 6)
4178 {
4179 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
4180 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
4181 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
4182
4183 pHlp->pfnPrintf(pHlp,
4184 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
4185 "L2 TLB 2/4M Data: %s %4d entries\n",
4186 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
4187 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
4188 pHlp->pfnPrintf(pHlp,
4189 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
4190 "L2 TLB 4K Data: %s %4d entries\n",
4191 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
4192 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
4193 pHlp->pfnPrintf(pHlp,
4194 "L2 Cache Line Size: %d bytes\n"
4195 "L2 Cache Lines Per Tag: %d\n"
4196 "L2 Cache Associativity: %s\n"
4197 "L2 Cache Size: %d KB\n",
4198 (uEDX >> 0) & 0xff,
4199 (uEDX >> 8) & 0xf,
4200 getL2CacheAss((uEDX >> 12) & 0xf),
4201 (uEDX >> 16) & 0xffff);
4202 }
4203
4204 if (iVerbosity && cExtMax >= 7)
4205 {
4206 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
4207
4208 pHlp->pfnPrintf(pHlp, "APM Features: ");
4209 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
4210 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
4211 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
4212 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
4213 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
4214 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
4215 for (unsigned iBit = 6; iBit < 32; iBit++)
4216 if (uEDX & RT_BIT(iBit))
4217 pHlp->pfnPrintf(pHlp, " %d", iBit);
4218 pHlp->pfnPrintf(pHlp, "\n");
4219 }
4220
4221 if (iVerbosity && cExtMax >= 8)
4222 {
4223 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
4224 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
4225
4226 pHlp->pfnPrintf(pHlp,
4227 "Physical Address Width: %d bits\n"
4228 "Virtual Address Width: %d bits\n"
4229 "Guest Physical Address Width: %d bits\n",
4230 (uEAX >> 0) & 0xff,
4231 (uEAX >> 8) & 0xff,
4232 (uEAX >> 16) & 0xff);
4233 pHlp->pfnPrintf(pHlp,
4234 "Physical Core Count: %d\n",
4235 (uECX >> 0) & 0xff);
4236 }
4237
4238
4239 /*
4240 * Centaur.
4241 */
4242 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
4243
4244 pHlp->pfnPrintf(pHlp,
4245 "\n"
4246 " RAW Centaur CPUIDs\n"
4247 " Function eax ebx ecx edx\n");
4248 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
4249 {
4250 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
4251 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4252
4253 pHlp->pfnPrintf(pHlp,
4254 "Gst: %08x %08x %08x %08x %08x%s\n"
4255 "Hst: %08x %08x %08x %08x\n",
4256 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
4257 i <= cCentaurMax ? "" : "*",
4258 Host.eax, Host.ebx, Host.ecx, Host.edx);
4259 }
4260
4261 /*
4262 * Understandable output
4263 */
4264 if (iVerbosity)
4265 {
4266 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
4267 pHlp->pfnPrintf(pHlp,
4268 "Centaur Supports: 0xc0000000-%#010x\n",
4269 Guest.eax);
4270 }
4271
4272 if (iVerbosity && cCentaurMax >= 1)
4273 {
4274 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
4275 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdCentaur[1].edx;
4276 uint32_t uEdxHst = Host.edx;
4277
4278 if (iVerbosity == 1)
4279 {
4280 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
4281 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
4282 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
4283 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
4284 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
4285 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
4286 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
4287 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
4288 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
4289 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4290 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
4291 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
4292 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
4293 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
4294 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
4295 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
4296 for (unsigned iBit = 14; iBit < 32; iBit++)
4297 if (uEdxGst & RT_BIT(iBit))
4298 pHlp->pfnPrintf(pHlp, " %d", iBit);
4299 pHlp->pfnPrintf(pHlp, "\n");
4300 }
4301 else
4302 {
4303 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
4304 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
4305 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
4306 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
4307 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
4308 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
4309 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
4310 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
4311 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
4312 /* possibly indicating MM/HE and MM/HE-E on older chips... */
4313 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
4314 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
4315 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
4316 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
4317 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
4318 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
4319 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
4320 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
4321 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
4322 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
4323 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
4324 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
4325 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
4326 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
4327 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
4328 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
4329 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
4330 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4331 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4332 for (unsigned iBit = 27; iBit < 32; iBit++)
4333 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
4334 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
4335 pHlp->pfnPrintf(pHlp, "\n");
4336 }
4337 }
4338}
4339
4340
4341/**
4342 * Structure used when disassembling and instructions in DBGF.
4343 * This is used so the reader function can get the stuff it needs.
4344 */
4345typedef struct CPUMDISASSTATE
4346{
4347 /** Pointer to the CPU structure. */
4348 PDISCPUSTATE pCpu;
4349 /** Pointer to the VM. */
4350 PVM pVM;
4351 /** Pointer to the VMCPU. */
4352 PVMCPU pVCpu;
4353 /** Pointer to the first byte in the segment. */
4354 RTGCUINTPTR GCPtrSegBase;
4355 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4356 RTGCUINTPTR GCPtrSegEnd;
4357 /** The size of the segment minus 1. */
4358 RTGCUINTPTR cbSegLimit;
4359 /** Pointer to the current page - R3 Ptr. */
4360 void const *pvPageR3;
4361 /** Pointer to the current page - GC Ptr. */
4362 RTGCPTR pvPageGC;
4363 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4364 PGMPAGEMAPLOCK PageMapLock;
4365 /** Whether the PageMapLock is valid or not. */
4366 bool fLocked;
4367 /** 64 bits mode or not. */
4368 bool f64Bits;
4369} CPUMDISASSTATE, *PCPUMDISASSTATE;
4370
4371
4372/**
4373 * @callback_method_impl{FNDISREADBYTES}
4374 */
4375static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4376{
4377 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4378 for (;;)
4379 {
4380 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4381
4382 /*
4383 * Need to update the page translation?
4384 */
4385 if ( !pState->pvPageR3
4386 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4387 {
4388 int rc = VINF_SUCCESS;
4389
4390 /* translate the address */
4391 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4392 if ( !HMIsEnabled(pState->pVM)
4393 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4394 {
4395 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4396 if (!pState->pvPageR3)
4397 rc = VERR_INVALID_POINTER;
4398 }
4399 else
4400 {
4401 /* Release mapping lock previously acquired. */
4402 if (pState->fLocked)
4403 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4404 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4405 pState->fLocked = RT_SUCCESS_NP(rc);
4406 }
4407 if (RT_FAILURE(rc))
4408 {
4409 pState->pvPageR3 = NULL;
4410 return rc;
4411 }
4412 }
4413
4414 /*
4415 * Check the segment limit.
4416 */
4417 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4418 return VERR_OUT_OF_SELECTOR_BOUNDS;
4419
4420 /*
4421 * Calc how much we can read.
4422 */
4423 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4424 if (!pState->f64Bits)
4425 {
4426 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4427 if (cb > cbSeg && cbSeg)
4428 cb = cbSeg;
4429 }
4430 if (cb > cbMaxRead)
4431 cb = cbMaxRead;
4432
4433 /*
4434 * Read and advance or exit.
4435 */
4436 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4437 offInstr += (uint8_t)cb;
4438 if (cb >= cbMinRead)
4439 {
4440 pDis->cbCachedInstr = offInstr;
4441 return VINF_SUCCESS;
4442 }
4443 cbMinRead -= (uint8_t)cb;
4444 cbMaxRead -= (uint8_t)cb;
4445 }
4446}
4447
4448
4449/**
4450 * Disassemble an instruction and return the information in the provided structure.
4451 *
4452 * @returns VBox status code.
4453 * @param pVM Pointer to the VM.
4454 * @param pVCpu Pointer to the VMCPU.
4455 * @param pCtx Pointer to the guest CPU context.
4456 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4457 * @param pCpu Disassembly state.
4458 * @param pszPrefix String prefix for logging (debug only).
4459 *
4460 */
4461VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4462{
4463 CPUMDISASSTATE State;
4464 int rc;
4465
4466 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4467 State.pCpu = pCpu;
4468 State.pvPageGC = 0;
4469 State.pvPageR3 = NULL;
4470 State.pVM = pVM;
4471 State.pVCpu = pVCpu;
4472 State.fLocked = false;
4473 State.f64Bits = false;
4474
4475 /*
4476 * Get selector information.
4477 */
4478 DISCPUMODE enmDisCpuMode;
4479 if ( (pCtx->cr0 & X86_CR0_PE)
4480 && pCtx->eflags.Bits.u1VM == 0)
4481 {
4482 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4483 {
4484# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4485 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4486# endif
4487 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4488 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4489 }
4490 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4491 State.GCPtrSegBase = pCtx->cs.u64Base;
4492 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4493 State.cbSegLimit = pCtx->cs.u32Limit;
4494 enmDisCpuMode = (State.f64Bits)
4495 ? DISCPUMODE_64BIT
4496 : pCtx->cs.Attr.n.u1DefBig
4497 ? DISCPUMODE_32BIT
4498 : DISCPUMODE_16BIT;
4499 }
4500 else
4501 {
4502 /* real or V86 mode */
4503 enmDisCpuMode = DISCPUMODE_16BIT;
4504 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4505 State.GCPtrSegEnd = 0xFFFFFFFF;
4506 State.cbSegLimit = 0xFFFFFFFF;
4507 }
4508
4509 /*
4510 * Disassemble the instruction.
4511 */
4512 uint32_t cbInstr;
4513#ifndef LOG_ENABLED
4514 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4515 if (RT_SUCCESS(rc))
4516 {
4517#else
4518 char szOutput[160];
4519 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4520 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4521 if (RT_SUCCESS(rc))
4522 {
4523 /* log it */
4524 if (pszPrefix)
4525 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4526 else
4527 Log(("%s", szOutput));
4528#endif
4529 rc = VINF_SUCCESS;
4530 }
4531 else
4532 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4533
4534 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4535 if (State.fLocked)
4536 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4537
4538 return rc;
4539}
4540
4541
4542
4543/**
4544 * API for controlling a few of the CPU features found in CR4.
4545 *
4546 * Currently only X86_CR4_TSD is accepted as input.
4547 *
4548 * @returns VBox status code.
4549 *
4550 * @param pVM Pointer to the VM.
4551 * @param fOr The CR4 OR mask.
4552 * @param fAnd The CR4 AND mask.
4553 */
4554VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4555{
4556 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4557 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4558
4559 pVM->cpum.s.CR4.OrMask &= fAnd;
4560 pVM->cpum.s.CR4.OrMask |= fOr;
4561
4562 return VINF_SUCCESS;
4563}
4564
4565
4566/**
4567 * Gets a pointer to the array of standard CPUID leaves.
4568 *
4569 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4570 *
4571 * @returns Pointer to the standard CPUID leaves (read-only).
4572 * @param pVM Pointer to the VM.
4573 * @remark Intended for PATM.
4574 */
4575VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4576{
4577 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4578}
4579
4580
4581/**
4582 * Gets a pointer to the array of extended CPUID leaves.
4583 *
4584 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4585 *
4586 * @returns Pointer to the extended CPUID leaves (read-only).
4587 * @param pVM Pointer to the VM.
4588 * @remark Intended for PATM.
4589 */
4590VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4591{
4592 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4593}
4594
4595
4596/**
4597 * Gets a pointer to the array of centaur CPUID leaves.
4598 *
4599 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4600 *
4601 * @returns Pointer to the centaur CPUID leaves (read-only).
4602 * @param pVM Pointer to the VM.
4603 * @remark Intended for PATM.
4604 */
4605VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4606{
4607 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4608}
4609
4610
4611/**
4612 * Gets a pointer to the default CPUID leaf.
4613 *
4614 * @returns Pointer to the default CPUID leaf (read-only).
4615 * @param pVM Pointer to the VM.
4616 * @remark Intended for PATM.
4617 */
4618VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4619{
4620 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4621}
4622
4623
4624/**
4625 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4626 *
4627 * Only REM should ever call this function!
4628 *
4629 * @returns The changed flags.
4630 * @param pVCpu Pointer to the VMCPU.
4631 * @param puCpl Where to return the current privilege level (CPL).
4632 */
4633VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4634{
4635 Assert(!pVCpu->cpum.s.fRawEntered);
4636 Assert(!pVCpu->cpum.s.fRemEntered);
4637
4638 /*
4639 * Get the CPL first.
4640 */
4641 *puCpl = CPUMGetGuestCPL(pVCpu);
4642
4643 /*
4644 * Get and reset the flags.
4645 */
4646 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4647 pVCpu->cpum.s.fChanged = 0;
4648
4649 /** @todo change the switcher to use the fChanged flags. */
4650 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4651 {
4652 fFlags |= CPUM_CHANGED_FPU_REM;
4653 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4654 }
4655
4656 pVCpu->cpum.s.fRemEntered = true;
4657 return fFlags;
4658}
4659
4660
4661/**
4662 * Leaves REM.
4663 *
4664 * @param pVCpu Pointer to the VMCPU.
4665 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4666 * registers.
4667 */
4668VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4669{
4670 Assert(!pVCpu->cpum.s.fRawEntered);
4671 Assert(pVCpu->cpum.s.fRemEntered);
4672
4673 pVCpu->cpum.s.fRemEntered = false;
4674}
4675
4676
4677/**
4678 * Called when the ring-3 init phase completes.
4679 *
4680 * @returns VBox status code.
4681 * @param pVM Pointer to the VM.
4682 */
4683VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4684{
4685 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4686 {
4687 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4688 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4689 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4690 }
4691 return VINF_SUCCESS;
4692}
4693
4694/**
4695 * Called when the ring-0 init phases comleted.
4696 *
4697 * @param pVM Pointer to the VM.
4698 */
4699VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4700{
4701 /*
4702 * Log the cpuid.
4703 */
4704 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4705 RTCPUSET OnlineSet;
4706 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4707 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4708 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4709 RTCPUID cCores = RTMpGetCoreCount();
4710 if (cCores)
4711 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4712 LogRel(("************************* CPUID dump ************************\n"));
4713 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4714 LogRel(("\n"));
4715 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4716 RTLogRelSetBuffering(fOldBuffered);
4717 LogRel(("******************** End of CPUID dump **********************\n"));
4718}
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