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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 103018

Last change on this file since 103018 was 103018, checked in by vboxsync, 4 months ago

VMM/CPUM: bugref:10498 Typo.
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1/* $Id: CPUM.cpp 103018 2024-01-24 11:20:40Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28/** @page pg_cpum CPUM - CPU Monitor / Manager
29 *
30 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
31 * also responsible for lazy FPU handling and some of the context loading
32 * in raw mode.
33 *
34 * There are three CPU contexts, the most important one is the guest one (GC).
35 * When running in raw-mode (RC) there is a special hyper context for the VMM
36 * part that floats around inside the guest address space. When running in
37 * raw-mode, CPUM also maintains a host context for saving and restoring
38 * registers across world switches. This latter is done in cooperation with the
39 * world switcher (@see pg_vmm).
40 *
41 * @see grp_cpum
42 *
43 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44 *
45 * TODO: proper write up, currently just some notes.
46 *
47 * The ring-0 FPU handling per OS:
48 *
49 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
50 * convention (Visual C++ doesn't seem to have a way to disable
51 * generating such code either), so CR0.TS/EM are always zero from what I
52 * can tell. We are also forced to always load/save the guest XMM0-XMM15
53 * registers when entering/leaving guest context. Interrupt handlers
54 * using FPU/SSE will offically have call save and restore functions
55 * exported by the kernel, if the really really have to use the state.
56 *
57 * - 32-bit windows does lazy FPU handling, I think, probably including
58 * lazying saving. The Windows Internals book states that it's a bad
59 * idea to use the FPU in kernel space. However, it looks like it will
60 * restore the FPU state of the current thread in case of a kernel \#NM.
61 * Interrupt handlers should be same as for 64-bit.
62 *
63 * - Darwin allows taking \#NM in kernel space, restoring current thread's
64 * state if I read the code correctly. It saves the FPU state of the
65 * outgoing thread, and uses CR0.TS to lazily load the state of the
66 * incoming one. No idea yet how the FPU is treated by interrupt
67 * handlers, i.e. whether they are allowed to disable the state or
68 * something.
69 *
70 * - Linux also allows \#NM in kernel space (don't know since when), and
71 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72 * loads the incoming unless configured to agressivly load it. Interrupt
73 * handlers can ask whether they're allowed to use the FPU, and may
74 * freely trash the state if Linux thinks it has saved the thread's state
75 * already. This is a problem.
76 *
77 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78 * context. When switching threads, the kernel will save the state of
79 * the outgoing thread and lazy load the incoming one using CR0.TS.
80 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
81 * to do stuff, HAT are among the users. The routines there will
82 * manually clear CR0.TS and save the XMM registers they use only if
83 * CR0.TS was zero upon entry. They will skip it when not, because as
84 * mentioned above, the FPU state is saved when switching away from a
85 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86 * preserve. This is a problem if we restore CR0.TS to 1 after loading
87 * the guest state.
88 *
89 * - FreeBSD - no idea yet.
90 *
91 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93 * FPU states.
94 *
95 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96 * saving and restoring the host and guest states. The motivation for this
97 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98 *
99 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100 * state and only restore it once we've restore the host FPU state. This has the
101 * accidental side effect of triggering Solaris to preserve XMM registers in
102 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104 *
105 *
106 * @section sec_cpum_logging Logging Level Assignments.
107 *
108 * Following log level assignments:
109 * - Log6 is used for FPU state management.
110 * - Log7 is used for FPU state actualization.
111 *
112 */
113
114
115/*********************************************************************************************************************************
116* Header Files *
117*********************************************************************************************************************************/
118#define LOG_GROUP LOG_GROUP_CPUM
119#define CPUM_WITH_NONCONST_HOST_FEATURES
120#include <VBox/vmm/cpum.h>
121#include <VBox/vmm/cpumdis.h>
122#include <VBox/vmm/cpumctx-v1_6.h>
123#include <VBox/vmm/pgm.h>
124#include <VBox/vmm/apic.h>
125#include <VBox/vmm/mm.h>
126#include <VBox/vmm/em.h>
127#include <VBox/vmm/iem.h>
128#include <VBox/vmm/selm.h>
129#include <VBox/vmm/dbgf.h>
130#include <VBox/vmm/hm.h>
131#include <VBox/vmm/hmvmxinline.h>
132#include <VBox/vmm/ssm.h>
133#include "CPUMInternal.h"
134#include <VBox/vmm/vm.h>
135
136#include <VBox/param.h>
137#include <VBox/dis.h>
138#include <VBox/err.h>
139#include <VBox/log.h>
140#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
141# include <iprt/asm-amd64-x86.h>
142#endif
143#include <iprt/assert.h>
144#include <iprt/cpuset.h>
145#include <iprt/mem.h>
146#include <iprt/mp.h>
147#include <iprt/rand.h>
148#include <iprt/string.h>
149
150
151/*********************************************************************************************************************************
152* Defined Constants And Macros *
153*********************************************************************************************************************************/
154/**
155 * This was used in the saved state up to the early life of version 14.
156 *
157 * It indicates that we may have some out-of-sync hidden segement registers.
158 * It is only relevant for raw-mode.
159 */
160#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
161
162
163/** For saved state only: Block injection of non-maskable interrupts to the guest.
164 * @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
165#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
166
167
168/*********************************************************************************************************************************
169* Structures and Typedefs *
170*********************************************************************************************************************************/
171
172/**
173 * What kind of cpu info dump to perform.
174 */
175typedef enum CPUMDUMPTYPE
176{
177 CPUMDUMPTYPE_TERSE,
178 CPUMDUMPTYPE_DEFAULT,
179 CPUMDUMPTYPE_VERBOSE
180} CPUMDUMPTYPE;
181/** Pointer to a cpu info dump type. */
182typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
183
184/**
185 * Map of variable-range MTRRs.
186 */
187typedef struct CPUMMTRRMAP
188{
189 /** The index of the next available MTRR. */
190 uint8_t idxMtrr;
191 /** The number of usable MTRRs. */
192 uint8_t cMtrrs;
193 /** Alignment padding. */
194 uint16_t uAlign;
195 /** The number of bytes to map via these MTRRs (not including UC regions). */
196 uint64_t cbToMap;
197 /** The number of bytes mapped via these MTRRs (not including UC regions). */
198 uint64_t cbMapped;
199 /** The variable-range MTRRs. */
200 X86MTRRVAR aMtrrs[CPUMCTX_MAX_MTRRVAR_COUNT];
201} CPUMMTRRMAP;
202/** Pointer to a CPUM variable-range MTRR structure. */
203typedef CPUMMTRRMAP *PCPUMMTRRMAP;
204/** Pointer to a const CPUM variable-range MTRR structure. */
205typedef CPUMMTRRMAP const *PCCPUMMTRRMAP;
206
207
208/*********************************************************************************************************************************
209* Internal Functions *
210*********************************************************************************************************************************/
211static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
212static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
213static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
214static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
215static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
216static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
217static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
218static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
219static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
220static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
221static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
222
223
224/*********************************************************************************************************************************
225* Global Variables *
226*********************************************************************************************************************************/
227#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
228/** Host CPU features. */
229DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
230#endif
231
232/** Saved state field descriptors for CPUMCTX. */
233static const SSMFIELD g_aCpumCtxFields[] =
234{
235 SSMFIELD_ENTRY( CPUMCTX, rdi),
236 SSMFIELD_ENTRY( CPUMCTX, rsi),
237 SSMFIELD_ENTRY( CPUMCTX, rbp),
238 SSMFIELD_ENTRY( CPUMCTX, rax),
239 SSMFIELD_ENTRY( CPUMCTX, rbx),
240 SSMFIELD_ENTRY( CPUMCTX, rdx),
241 SSMFIELD_ENTRY( CPUMCTX, rcx),
242 SSMFIELD_ENTRY( CPUMCTX, rsp),
243 SSMFIELD_ENTRY( CPUMCTX, rflags),
244 SSMFIELD_ENTRY( CPUMCTX, rip),
245 SSMFIELD_ENTRY( CPUMCTX, r8),
246 SSMFIELD_ENTRY( CPUMCTX, r9),
247 SSMFIELD_ENTRY( CPUMCTX, r10),
248 SSMFIELD_ENTRY( CPUMCTX, r11),
249 SSMFIELD_ENTRY( CPUMCTX, r12),
250 SSMFIELD_ENTRY( CPUMCTX, r13),
251 SSMFIELD_ENTRY( CPUMCTX, r14),
252 SSMFIELD_ENTRY( CPUMCTX, r15),
253 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
265 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
266 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
267 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
268 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
269 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
270 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
271 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
272 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
273 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
274 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
275 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
276 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
277 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
278 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
279 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
280 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
281 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
282 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
283 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
284 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
285 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
286 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
287 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
288 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
289 SSMFIELD_ENTRY( CPUMCTX, cr0),
290 SSMFIELD_ENTRY( CPUMCTX, cr2),
291 SSMFIELD_ENTRY( CPUMCTX, cr3),
292 SSMFIELD_ENTRY( CPUMCTX, cr4),
293 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
294 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
295 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
296 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
297 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
298 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
299 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
300 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
301 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
302 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
303 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
304 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
305 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
306 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
307 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
308 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
309 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
310 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
311 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
312 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
313 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
314 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
315 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
316 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
317 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
318 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
319 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
320 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
321 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
322 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
323 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
324 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
325 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
326 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
327 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
328 SSMFIELD_ENTRY_TERM()
329};
330
331/** Saved state field descriptors for SVM nested hardware-virtualization
332 * Host State. */
333static const SSMFIELD g_aSvmHwvirtHostState[] =
334{
335 SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
336 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
337 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
338 SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
339 SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
340 SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
341 SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
342 SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
343 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
344 SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
345 SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
346 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
347 SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
348 SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
349 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
350 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
351 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
352 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
353 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
354 SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
355 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
356 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
357 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
358 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
359 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
360 SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
361 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
362 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
363 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
364 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
365 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
366 SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
367 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
368 SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
369 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
370 SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
371 SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
372 SSMFIELD_ENTRY_TERM()
373};
374
375/** Saved state field descriptors for VMX nested hardware-virtualization
376 * VMCS. */
377static const SSMFIELD g_aVmxHwvirtVmcs[] =
378{
379 SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
380 SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
381 SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
382 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
383 SSMFIELD_ENTRY_VER( VMXVVMCS, u32RestoreProcCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4),
384 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
385
386 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
387
388 SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
389 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
390 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
391 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
392 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
393 SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
394 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
395 SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
396 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
397
398 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
399 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
400
401 SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
402 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
403 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
404 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
405 SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
406 SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
407 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
408
409 SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
410 SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
411 SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
412 SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
413 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
414
415 SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
416 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
417 SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
418 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
419 SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
420 SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
421 SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
422 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
423 SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
424 SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
425 SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
426 SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
427 SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
428 SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
429 SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
430 SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
431 SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
432 SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
433 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
434
435 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
436 SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
437 SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
438 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
439 SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
440 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
441 SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
442 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
443 SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
444 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
445 SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
446 SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
447 SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
448 SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
449 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
450 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
451 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
452 SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
453 SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
454 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
455 SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
456 SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
457 SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
458 SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
459 SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
460 SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
461 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
462 SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
463 SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
464 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
465 SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
466 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
467
468 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
469 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
470 SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
471 SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
472 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
473 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
474 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
475 SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
476 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
477
478 SSMFIELD_ENTRY( VMXVVMCS, HostEs),
479 SSMFIELD_ENTRY( VMXVVMCS, HostCs),
480 SSMFIELD_ENTRY( VMXVVMCS, HostSs),
481 SSMFIELD_ENTRY( VMXVVMCS, HostDs),
482 SSMFIELD_ENTRY( VMXVVMCS, HostFs),
483 SSMFIELD_ENTRY( VMXVVMCS, HostGs),
484 SSMFIELD_ENTRY( VMXVVMCS, HostTr),
485 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
486
487 SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
488 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
489
490 SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
491 SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
492 SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
493 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
494 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
495
496 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
497 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
498 SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
499 SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
500 SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
501 SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
502 SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
503 SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
504 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
505 SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
506 SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
507 SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
508 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
509 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510 SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
511 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
512
513 SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
514 SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
515 SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
516 SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
517 SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
518 SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
519 SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
520 SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
521 SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
522 SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
523 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
524
525 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
526 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
527 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
528 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
529 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
530 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
531 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
532 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
533 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
534 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
535 SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
536 SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
537 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
538 SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
539 SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
540 SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
541 SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
542 SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
543 SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
544 SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
545 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
546 SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
547 SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
548 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
549
550 SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
551 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
552 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
553 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
554 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
555 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
556 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
557 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
558 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
559 SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
560 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
561 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
562 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
563
564 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
565 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
566 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
567 SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
568 SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
569 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
570 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
571 SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
572 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
573 SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
574 SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
575 SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
576 SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
577 SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
578 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
579 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
580 SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
581 SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
582 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
583 SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
584 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
585 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
586 SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
587 SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
588
589 SSMFIELD_ENTRY_TERM()
590};
591
592/** Saved state field descriptors for CPUMCTX. */
593static const SSMFIELD g_aCpumX87Fields[] =
594{
595 SSMFIELD_ENTRY( X86FXSTATE, FCW),
596 SSMFIELD_ENTRY( X86FXSTATE, FSW),
597 SSMFIELD_ENTRY( X86FXSTATE, FTW),
598 SSMFIELD_ENTRY( X86FXSTATE, FOP),
599 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
600 SSMFIELD_ENTRY( X86FXSTATE, CS),
601 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
602 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
603 SSMFIELD_ENTRY( X86FXSTATE, DS),
604 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
605 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
606 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
607 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
608 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
609 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
610 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
611 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
612 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
613 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
614 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
615 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
616 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
617 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
618 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
619 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
620 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
621 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
622 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
623 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
624 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
625 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
626 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
627 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
628 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
629 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
630 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
631 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
632 SSMFIELD_ENTRY_TERM()
633};
634
635/** Saved state field descriptors for X86XSAVEHDR. */
636static const SSMFIELD g_aCpumXSaveHdrFields[] =
637{
638 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
639 SSMFIELD_ENTRY_TERM()
640};
641
642/** Saved state field descriptors for X86XSAVEYMMHI. */
643static const SSMFIELD g_aCpumYmmHiFields[] =
644{
645 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
646 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
647 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
648 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
649 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
650 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
651 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
652 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
653 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
654 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
655 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
656 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
657 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
658 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
659 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
660 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
661 SSMFIELD_ENTRY_TERM()
662};
663
664/** Saved state field descriptors for X86XSAVEBNDREGS. */
665static const SSMFIELD g_aCpumBndRegsFields[] =
666{
667 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
668 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
669 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
670 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
671 SSMFIELD_ENTRY_TERM()
672};
673
674/** Saved state field descriptors for X86XSAVEBNDCFG. */
675static const SSMFIELD g_aCpumBndCfgFields[] =
676{
677 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
678 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
679 SSMFIELD_ENTRY_TERM()
680};
681
682#if 0 /** @todo */
683/** Saved state field descriptors for X86XSAVEOPMASK. */
684static const SSMFIELD g_aCpumOpmaskFields[] =
685{
686 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
687 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
688 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
689 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
690 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
691 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
692 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
693 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
694 SSMFIELD_ENTRY_TERM()
695};
696#endif
697
698/** Saved state field descriptors for X86XSAVEZMMHI256. */
699static const SSMFIELD g_aCpumZmmHi256Fields[] =
700{
701 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
702 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
703 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
704 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
705 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
706 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
707 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
708 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
709 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
710 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
711 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
712 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
713 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
714 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
715 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
716 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
717 SSMFIELD_ENTRY_TERM()
718};
719
720/** Saved state field descriptors for X86XSAVEZMM16HI. */
721static const SSMFIELD g_aCpumZmm16HiFields[] =
722{
723 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
724 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
725 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
726 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
727 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
728 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
729 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
730 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
731 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
732 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
733 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
734 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
735 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
736 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
737 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
738 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
739 SSMFIELD_ENTRY_TERM()
740};
741
742
743
744/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
745 * registeres changed. */
746static const SSMFIELD g_aCpumX87FieldsMem[] =
747{
748 SSMFIELD_ENTRY( X86FXSTATE, FCW),
749 SSMFIELD_ENTRY( X86FXSTATE, FSW),
750 SSMFIELD_ENTRY( X86FXSTATE, FTW),
751 SSMFIELD_ENTRY( X86FXSTATE, FOP),
752 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
753 SSMFIELD_ENTRY( X86FXSTATE, CS),
754 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
755 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
756 SSMFIELD_ENTRY( X86FXSTATE, DS),
757 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
758 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
759 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
760 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
761 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
762 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
763 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
764 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
765 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
766 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
767 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
768 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
769 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
770 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
771 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
772 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
773 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
774 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
775 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
776 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
777 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
778 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
779 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
780 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
781 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
782 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
783 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
784 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
785 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
786};
787
788/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
789 * registeres changed. */
790static const SSMFIELD g_aCpumCtxFieldsMem[] =
791{
792 SSMFIELD_ENTRY( CPUMCTX, rdi),
793 SSMFIELD_ENTRY( CPUMCTX, rsi),
794 SSMFIELD_ENTRY( CPUMCTX, rbp),
795 SSMFIELD_ENTRY( CPUMCTX, rax),
796 SSMFIELD_ENTRY( CPUMCTX, rbx),
797 SSMFIELD_ENTRY( CPUMCTX, rdx),
798 SSMFIELD_ENTRY( CPUMCTX, rcx),
799 SSMFIELD_ENTRY( CPUMCTX, rsp),
800 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
801 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
802 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
803 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
804 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
805 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
806 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
807 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
808 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
809 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
810 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
811 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
812 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
813 SSMFIELD_ENTRY( CPUMCTX, rflags),
814 SSMFIELD_ENTRY( CPUMCTX, rip),
815 SSMFIELD_ENTRY( CPUMCTX, r8),
816 SSMFIELD_ENTRY( CPUMCTX, r9),
817 SSMFIELD_ENTRY( CPUMCTX, r10),
818 SSMFIELD_ENTRY( CPUMCTX, r11),
819 SSMFIELD_ENTRY( CPUMCTX, r12),
820 SSMFIELD_ENTRY( CPUMCTX, r13),
821 SSMFIELD_ENTRY( CPUMCTX, r14),
822 SSMFIELD_ENTRY( CPUMCTX, r15),
823 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
824 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
825 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
826 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
827 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
828 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
829 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
830 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
831 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
832 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
833 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
834 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
835 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
836 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
837 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
838 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
839 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
840 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
841 SSMFIELD_ENTRY( CPUMCTX, cr0),
842 SSMFIELD_ENTRY( CPUMCTX, cr2),
843 SSMFIELD_ENTRY( CPUMCTX, cr3),
844 SSMFIELD_ENTRY( CPUMCTX, cr4),
845 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
846 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
847 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
848 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
849 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
850 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
851 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
852 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
853 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
854 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
855 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
856 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
857 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
858 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
859 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
860 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
861 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
862 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
863 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
864 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
865 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
866 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
867 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
868 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
869 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
870 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
871 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
872 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
873 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
874 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
875 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
876 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
877 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
878 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
879 SSMFIELD_ENTRY_TERM()
880};
881
882/** Saved state field descriptors for CPUMCTX_VER1_6. */
883static const SSMFIELD g_aCpumX87FieldsV16[] =
884{
885 SSMFIELD_ENTRY( X86FXSTATE, FCW),
886 SSMFIELD_ENTRY( X86FXSTATE, FSW),
887 SSMFIELD_ENTRY( X86FXSTATE, FTW),
888 SSMFIELD_ENTRY( X86FXSTATE, FOP),
889 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
890 SSMFIELD_ENTRY( X86FXSTATE, CS),
891 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
892 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
893 SSMFIELD_ENTRY( X86FXSTATE, DS),
894 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
895 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
896 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
897 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
898 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
899 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
900 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
901 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
902 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
903 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
904 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
905 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
906 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
907 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
908 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
909 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
910 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
911 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
912 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
913 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
914 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
915 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
916 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
917 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
918 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
919 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
920 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
921 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
922 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
923 SSMFIELD_ENTRY_TERM()
924};
925
926/** Saved state field descriptors for CPUMCTX_VER1_6. */
927static const SSMFIELD g_aCpumCtxFieldsV16[] =
928{
929 SSMFIELD_ENTRY( CPUMCTX, rdi),
930 SSMFIELD_ENTRY( CPUMCTX, rsi),
931 SSMFIELD_ENTRY( CPUMCTX, rbp),
932 SSMFIELD_ENTRY( CPUMCTX, rax),
933 SSMFIELD_ENTRY( CPUMCTX, rbx),
934 SSMFIELD_ENTRY( CPUMCTX, rdx),
935 SSMFIELD_ENTRY( CPUMCTX, rcx),
936 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
937 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
938 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
939 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
940 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
941 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
942 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
943 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
944 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
945 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
946 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
947 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
948 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
949 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
950 SSMFIELD_ENTRY( CPUMCTX, rflags),
951 SSMFIELD_ENTRY( CPUMCTX, rip),
952 SSMFIELD_ENTRY( CPUMCTX, r8),
953 SSMFIELD_ENTRY( CPUMCTX, r9),
954 SSMFIELD_ENTRY( CPUMCTX, r10),
955 SSMFIELD_ENTRY( CPUMCTX, r11),
956 SSMFIELD_ENTRY( CPUMCTX, r12),
957 SSMFIELD_ENTRY( CPUMCTX, r13),
958 SSMFIELD_ENTRY( CPUMCTX, r14),
959 SSMFIELD_ENTRY( CPUMCTX, r15),
960 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
961 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
962 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
963 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
964 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
965 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
966 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
967 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
968 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
969 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
970 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
971 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
972 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
973 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
974 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
975 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
976 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
977 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
978 SSMFIELD_ENTRY( CPUMCTX, cr0),
979 SSMFIELD_ENTRY( CPUMCTX, cr2),
980 SSMFIELD_ENTRY( CPUMCTX, cr3),
981 SSMFIELD_ENTRY( CPUMCTX, cr4),
982 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
983 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
984 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
985 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
986 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
987 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
988 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
989 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
990 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
991 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
992 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
993 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
994 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
995 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
996 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
997 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
998 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
999 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
1000 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
1001 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
1002 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
1003 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
1004 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
1005 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
1006 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
1007 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
1008 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
1009 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
1010 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
1011 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
1012 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
1013 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
1014 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
1015 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
1016 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
1017 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
1018 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
1019 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
1020 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
1021 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
1022 SSMFIELD_ENTRY_TERM()
1023};
1024
1025
1026#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
1027/**
1028 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1029 *
1030 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1031 * (last instruction pointer, last data pointer, last opcode) except when the ES
1032 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1033 * clear these registers there is potential, local FPU leakage from a process
1034 * using the FPU to another.
1035 *
1036 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
1037 *
1038 * @param pVM The cross context VM structure.
1039 */
1040static void cpumR3CheckLeakyFpu(PVM pVM)
1041{
1042 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1043 uint32_t const u32Family = u32CpuVersion >> 8;
1044 if ( u32Family >= 6 /* K7 and higher */
1045 && (ASMIsAmdCpu() || ASMIsHygonCpu()) )
1046 {
1047 uint32_t cExt = ASMCpuId_EAX(0x80000000);
1048 if (RTX86IsValidExtRange(cExt))
1049 {
1050 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1051 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1052 {
1053 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1054 {
1055 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1056 pVCpu->cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
1057 }
1058 Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1059 }
1060 }
1061 }
1062}
1063#endif
1064
1065
1066/**
1067 * Initialize the SVM hardware virtualization state.
1068 *
1069 * @param pVM The cross context VM structure.
1070 */
1071static void cpumR3InitSvmHwVirtState(PVM pVM)
1072{
1073 LogRel(("CPUM: AMD-V nested-guest init\n"));
1074 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1075 {
1076 PVMCPU pVCpu = pVM->apCpusR3[i];
1077 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1078
1079 /* Initialize that SVM hardware virtualization is available. */
1080 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1081
1082 AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1083 AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1084 AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1085
1086 /* Initialize non-zero values. */
1087 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1088 }
1089}
1090
1091
1092/**
1093 * Resets per-VCPU SVM hardware virtualization state.
1094 *
1095 * @param pVCpu The cross context virtual CPU structure.
1096 */
1097DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1098{
1099 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1100 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1101
1102 RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1103 RT_ZERO(pCtx->hwvirt.svm.HostState);
1104 RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1105 RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1106
1107 pCtx->hwvirt.svm.uMsrHSavePa = 0;
1108 pCtx->hwvirt.svm.uPrevPauseTick = 0;
1109 pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1110 pCtx->hwvirt.svm.cPauseFilter = 0;
1111 pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1112 pCtx->hwvirt.svm.fInterceptEvents = false;
1113}
1114
1115
1116/**
1117 * Initializes the VMX hardware virtualization state.
1118 *
1119 * @param pVM The cross context VM structure.
1120 */
1121static void cpumR3InitVmxHwVirtState(PVM pVM)
1122{
1123 LogRel(("CPUM: VT-x nested-guest init\n"));
1124 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1125 {
1126 PVMCPU pVCpu = pVM->apCpusR3[i];
1127 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1128
1129 /* Initialize that VMX hardware virtualization is available. */
1130 pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1131
1132 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1133 AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1134 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1135 AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1136 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1137 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1138 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1139 AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1140 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1141 AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1142 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1143 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1144 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1145 AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1146 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1147 AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1148 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1149 AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1150
1151 /* Initialize non-zero values. */
1152 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1153 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1154 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1155 }
1156}
1157
1158
1159/**
1160 * Resets per-VCPU VMX hardware virtualization state.
1161 *
1162 * @param pVCpu The cross context virtual CPU structure.
1163 */
1164DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1165{
1166 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1167 Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1168
1169 RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1170 RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1171 RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1172 RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1173 RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1174 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1175 RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1176 RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1177 RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1178
1179 pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1180 pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1181 pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1182 pCtx->hwvirt.vmx.fInVmxRootMode = false;
1183 pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1184 /* Don't reset diagnostics here. */
1185
1186 pCtx->hwvirt.vmx.fInterceptEvents = false;
1187 pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1188 pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1189 pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1190 pCtx->hwvirt.vmx.uEntryTick = 0;
1191 pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1192 pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1193
1194 /* Stop any VMX-preemption timer. */
1195 CPUMStopGuestVmxPremptTimer(pVCpu);
1196
1197 /* Clear all nested-guest FFs. */
1198 VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1199}
1200
1201
1202/**
1203 * Displays the host and guest VMX features.
1204 *
1205 * @param pVM The cross context VM structure.
1206 * @param pHlp The info helper functions.
1207 * @param pszArgs "terse", "default" or "verbose".
1208 */
1209static DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1210{
1211 RT_NOREF(pszArgs);
1212 PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1213 PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1214 if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1215 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1216 || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1217 {
1218#define VMXFEATDUMP(a_szDesc, a_Var) \
1219 pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1220
1221 pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1222 pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1223 VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1224 /* Basic. */
1225 VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1226
1227 /* Pin-based controls. */
1228 VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1229 VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1230 VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1231 VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1232 VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1233
1234 /* Processor-based controls. */
1235 VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1236 VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1237 VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1238 VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1239 VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1240 VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1241 VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1242 VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1243 VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1244 VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1245 VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1246 VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1247 VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1248 VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1249 VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1250 VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1251 VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1252 VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1253 VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1254 VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1255 VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1256 VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1257
1258 /* Secondary processor-based controls. */
1259 VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1260 VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1261 VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1262 VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1263 VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1264 VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1265 VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1266 VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1267 VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1268 VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1269 VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1270 VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1271 VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1272 VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1273 VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1274 VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1275 VMXFEATDUMP("PML - Page-Modification Log ", fVmxPml);
1276 VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1277 VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1278 VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1279 VMXFEATDUMP("PasidTranslate - PASID translation ", fVmxPasidTranslate);
1280 VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1281 VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1282 VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1283 VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1284 VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1285 VMXFEATDUMP("Pconfig - Enable PCONFIG ", fVmxPconfig);
1286 VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1287 VMXFEATDUMP("BusLockDetect - VMM Bus-Lock detection ", fVmxBusLockDetect);
1288 VMXFEATDUMP("InstrTimeout - Instruction timeout ", fVmxInstrTimeout);
1289
1290 /* Tertiary processor-based controls. */
1291 VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1292 VMXFEATDUMP("HLAT - Hypervisor-managed linear-address translation ", fVmxHlat);
1293 VMXFEATDUMP("EptPagingWrite - EPT paging-write ", fVmxEptPagingWrite);
1294 VMXFEATDUMP("GstPagingVerify - Guest-paging verification ", fVmxGstPagingVerify);
1295 VMXFEATDUMP("IpiVirt - IPI virtualization ", fVmxIpiVirt);
1296 VMXFEATDUMP("VirtSpecCtrl - Virtualize IA32_SPEC_CTRL ", fVmxVirtSpecCtrl);
1297
1298 /* VM-entry controls. */
1299 VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1300 VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1301 VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1302 VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1303
1304 /* VM-exit controls. */
1305 VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1306 VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1307 VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1308 VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1309 VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1310 VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1311 VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1312 VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1313 VMXFEATDUMP("SecondaryExitCtls - Secondary VM-exit controls ", fVmxSecondaryExitCtls);
1314
1315 /* Miscellaneous data. */
1316 VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1317 VMXFEATDUMP("IntelPt - Intel Processor Trace in VMX operation ", fVmxPt);
1318 VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1319 VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1320#undef VMXFEATDUMP
1321 }
1322 else
1323 pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1324}
1325
1326
1327/**
1328 * Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1329 * or NEM) is allowed.
1330 *
1331 * @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1332 * otherwise.
1333 * @param pVM The cross context VM structure.
1334 */
1335static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1336{
1337 AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1338#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1339 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1340 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1341 return true;
1342#else
1343 NOREF(pVM);
1344#endif
1345 return false;
1346}
1347
1348
1349/**
1350 * Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1351 *
1352 * @param pVM The cross context VM structure.
1353 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1354 * and no hardware-assisted nested-guest execution is
1355 * possible for this VM.
1356 * @param pGuestFeatures The guest features to use (only VMX features are
1357 * accessed).
1358 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1359 *
1360 * @remarks This function ASSUMES the VMX guest-features are already exploded!
1361 */
1362static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1363{
1364 bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1365
1366 Assert(!fIsNstGstHwExecAllowed || pHostVmxMsrs);
1367 Assert(pGuestFeatures->fVmx);
1368
1369 /* Basic information. */
1370 uint8_t const fTrueVmxMsrs = 1;
1371 {
1372 uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1373 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1374 | RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1375 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1376 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1377 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1378 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1379 pGuestVmxMsrs->u64Basic = u64Basic;
1380 }
1381
1382 /* Pin-based VM-execution controls. */
1383 {
1384 uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1385 | (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1386 | (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1387 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1388 | (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1389 uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1390 uint32_t const fAllowed1 = fFeatures | VMX_PIN_CTLS_DEFAULT1;
1391 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1392 fAllowed0, fAllowed1, fFeatures));
1393 pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1394
1395 /* True pin-based VM-execution controls. */
1396 if (fTrueVmxMsrs)
1397 {
1398 /* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1399 pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1400 }
1401 }
1402
1403 /* Processor-based VM-execution controls. */
1404 {
1405 uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1406 | (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1407 | (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1408 | (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1409 | (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1410 | (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1411 | (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1412 | (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1413 | (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1414 | (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1415 | (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1416 | (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1417 | (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1418 | (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1419 | (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1420 | (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1421 | (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1422 | (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1423 | (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1424 | (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1425 | (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1426 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1427 uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1428 uint32_t const fAllowed1 = fFeatures | VMX_PROC_CTLS_DEFAULT1;
1429 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1430 fAllowed1, fFeatures));
1431 pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1432
1433 /* True processor-based VM-execution controls. */
1434 if (fTrueVmxMsrs)
1435 {
1436 /* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1437 uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1438 | VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1439 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1440 pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1441 }
1442 }
1443
1444 /* Secondary processor-based VM-execution controls. */
1445 if (pGuestFeatures->fVmxSecondaryExecCtls)
1446 {
1447 uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1448 | (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1449 | (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1450 | (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1451 | (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1452 | (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1453 | (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1454 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1455 | (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1456 | (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1457 | (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1458 | (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1459 | (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1460 | (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1461 | (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1462 | (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1463 | (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1464 | (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1465 | (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1466 | (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1467 | (pGuestFeatures->fVmxPasidTranslate << VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT )
1468 | (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1469 | (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1470 | (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1471 | (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1472 | (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1473 | (pGuestFeatures->fVmxPconfig << VMX_BF_PROC_CTLS2_PCONFIG_SHIFT )
1474 | (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT )
1475 | (pGuestFeatures->fVmxBusLockDetect << VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT )
1476 | (pGuestFeatures->fVmxInstrTimeout << VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT );
1477 uint32_t const fAllowed0 = 0;
1478 uint32_t const fAllowed1 = fFeatures;
1479 pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1480 }
1481
1482 /* Tertiary processor-based VM-execution controls. */
1483 if (pGuestFeatures->fVmxTertiaryExecCtls)
1484 {
1485 pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT)
1486 | (pGuestFeatures->fVmxHlat << VMX_BF_PROC_CTLS3_HLAT_SHIFT)
1487 | (pGuestFeatures->fVmxEptPagingWrite << VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT)
1488 | (pGuestFeatures->fVmxGstPagingVerify << VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT)
1489 | (pGuestFeatures->fVmxIpiVirt << VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT)
1490 | (pGuestFeatures->fVmxVirtSpecCtrl << VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT);
1491 }
1492
1493 /* VM-exit controls. */
1494 {
1495 uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1496 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1497 | (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1498 | (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1499 | (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1500 | (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1501 | (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1502 | (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1503 | (pGuestFeatures->fVmxSecondaryExitCtls << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1504 /* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1505 uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1506 uint32_t const fAllowed1 = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
1507 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1508 fAllowed1, fFeatures));
1509 pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1510
1511 /* True VM-exit controls. */
1512 if (fTrueVmxMsrs)
1513 {
1514 /* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1515 uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1516 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1517 pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1518 }
1519 }
1520
1521 /* VM-entry controls. */
1522 {
1523 uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1524 | (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1525 | (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1526 | (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1527 uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1528 uint32_t const fAllowed1 = fFeatures | VMX_ENTRY_CTLS_DEFAULT1;
1529 AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1530 fAllowed1, fFeatures));
1531 pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1532
1533 /* True VM-entry controls. */
1534 if (fTrueVmxMsrs)
1535 {
1536 /* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1537 uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1538 | VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1539 | VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1540 | VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1541 uint32_t const fTrueAllowed1 = fFeatures | fTrueAllowed0;
1542 pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1543 }
1544 }
1545
1546 /* Miscellaneous data. */
1547 {
1548 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1549
1550 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1551 uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1552 pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1553 | RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1554 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1555 | RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1556 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1557 | RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1558 | RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1559 | RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1560 | RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1561 | RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1562 | RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1563 }
1564
1565 /* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1566 pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1567
1568 /* CR0 Fixed-1. */
1569 {
1570 /*
1571 * All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1572 * This is different from CR4 fixed-1 bits which are reported as per the
1573 * CPU features and/or micro-architecture/generation. Why? Ask Intel.
1574 */
1575 pGuestVmxMsrs->u64Cr0Fixed1 = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1576
1577 /* Make sure the CR0 MB1 bits are not clear. */
1578 Assert((pGuestVmxMsrs->u64Cr0Fixed1 & pGuestVmxMsrs->u64Cr0Fixed0) == pGuestVmxMsrs->u64Cr0Fixed0);
1579 }
1580
1581 /* CR4 Fixed-0. */
1582 pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1583
1584 /* CR4 Fixed-1. */
1585 {
1586 pGuestVmxMsrs->u64Cr4Fixed1 = CPUMGetGuestCR4ValidMask(pVM) & pHostVmxMsrs->u64Cr4Fixed1;
1587
1588 /* Make sure the CR4 MB1 bits are not clear. */
1589 Assert((pGuestVmxMsrs->u64Cr4Fixed1 & pGuestVmxMsrs->u64Cr4Fixed0) == pGuestVmxMsrs->u64Cr4Fixed0);
1590
1591 /* Make sure bits that must always be set are set. */
1592 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_PAE);
1593 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_VMXE);
1594 }
1595
1596 /* VMCS Enumeration. */
1597 pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1598
1599 /* VPID and EPT Capabilities. */
1600 if (pGuestFeatures->fVmxEpt)
1601 {
1602 /*
1603 * INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1604 * and emulate any INVVPID flush type. However, it only makes sense to expose the types
1605 * when INVVPID instruction is supported just to be more compatible with guest
1606 * hypervisors that may make assumptions by only looking at this MSR even though they
1607 * are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1608 *
1609 * See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1610 * See Intel spec. 30.3 "VMX Instructions".
1611 */
1612 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1613 uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1614
1615 uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1616 uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1617 uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1618 uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1619 uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1620 uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1621 /** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1622 /* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1623 uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1624 uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1625 uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1626 uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1627 uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1628 uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1629 pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1630 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1631 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1632 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1633 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1634 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1635 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1636 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1637 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1638 //| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1639 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1640 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1641 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1642 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1643 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1644 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1645 | RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1646 }
1647
1648 /* VM Functions. */
1649 if (pGuestFeatures->fVmxVmFunc)
1650 pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1651}
1652
1653
1654/**
1655 * Checks whether the given guest CPU VMX features are compatible with the provided
1656 * base features.
1657 *
1658 * @returns @c true if compatible, @c false otherwise.
1659 * @param pVM The cross context VM structure.
1660 * @param pBase The base VMX CPU features.
1661 * @param pGst The guest VMX CPU features.
1662 *
1663 * @remarks Only VMX feature bits are examined.
1664 */
1665static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1666{
1667 if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1668 return false;
1669
1670#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1671#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1672 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1673 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1674 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1675 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1676 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1677 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1678 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1679 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1680 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1681 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1682 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1683 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1684 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1685 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1686 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1687 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1688 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1689 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1690 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1691 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1692 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1693 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1694 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1695 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1696 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1697 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1698 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1699 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1700 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1701 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1702 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1703 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1704 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1705 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1706 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1707 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1708 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1709 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1710 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1711 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1712 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1713 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1714 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1715 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1716 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1717 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1718 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1719 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPasidTranslate , 49) \
1720 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 50) \
1721 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 51) \
1722 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 52) \
1723 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 53) \
1724 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 54) \
1725 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPconfig , 55) \
1726 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 56) \
1727 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxBusLockDetect , 57) \
1728 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInstrTimeout , 58) \
1729 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 59) \
1730 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHlat , 60) \
1731 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptPagingWrite , 61) \
1732 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxGstPagingVerify , 62) \
1733 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIpiVirt , 63))
1734
1735#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtSpecCtrl , 0) \
1736 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 1) \
1737 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 2) \
1738 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 3) \
1739 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 4) \
1740 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 5) \
1741 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 6) \
1742 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 7) \
1743 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 8) \
1744 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 9) \
1745 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 10) \
1746 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 12) \
1747 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 13) \
1748 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExitCtls , 14) \
1749 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 15) \
1750 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 16) \
1751 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 17) \
1752 | CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 18))
1753
1754 /* Check first set of feature bits. */
1755 {
1756 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1757 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1758 if ((fBase | fGst) != fBase)
1759 {
1760 uint64_t const fDiff = fBase ^ fGst;
1761 LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1762 fBase, fGst, fDiff));
1763 return false;
1764 }
1765 }
1766
1767 /* Check second set of feature bits. */
1768 {
1769 uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1770 uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1771 if ((fBase | fGst) != fBase)
1772 {
1773 uint64_t const fDiff = fBase ^ fGst;
1774 LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1775 fBase, fGst, fDiff));
1776 return false;
1777 }
1778 }
1779#undef CPUM_VMX_FEAT_SHIFT
1780#undef CPUM_VMX_MAKE_FEATURES_1
1781#undef CPUM_VMX_MAKE_FEATURES_2
1782
1783 return true;
1784}
1785
1786
1787/**
1788 * Initializes VMX guest features and MSRs.
1789 *
1790 * @param pVM The cross context VM structure.
1791 * @param pCpumCfg The CPUM CFGM configuration node.
1792 * @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1793 * and no hardware-assisted nested-guest execution is
1794 * possible for this VM.
1795 * @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1796 */
1797void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1798{
1799 Assert(pVM);
1800 Assert(pCpumCfg);
1801 Assert(pGuestVmxMsrs);
1802
1803 /*
1804 * Query VMX features from CFGM.
1805 */
1806 bool fVmxPreemptTimer;
1807 bool fVmxEpt;
1808 bool fVmxUnrestrictedGuest;
1809 {
1810 /** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1811 * Whether to expose the VMX-preemption timer feature to the guest (if also
1812 * supported by the host hardware). When disabled will prevent exposing the
1813 * VMX-preemption timer feature to the guest even if the host supports it.
1814 *
1815 * @todo Currently disabled, see @bugref{9180#c108}.
1816 */
1817 int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1818 AssertLogRelRCReturnVoid(rc);
1819
1820#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1821 /** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1822 * Whether to expose the EPT feature to the guest. The default is true.
1823 * When disabled will automatically prevent exposing features that rely
1824 * on it. This is dependent upon nested paging being enabled for the VM.
1825 */
1826 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1827 AssertLogRelRCReturnVoid(rc);
1828
1829 /** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1830 * Whether to expose the Unrestricted Guest feature to the guest. The
1831 * default is the same a /CPUM/Nested/VmxEpt. When disabled will
1832 * automatically prevent exposing features that rely on it.
1833 */
1834 rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1835 AssertLogRelRCReturnVoid(rc);
1836#else
1837 fVmxEpt = fVmxUnrestrictedGuest = false;
1838#endif
1839 }
1840
1841 if (fVmxEpt)
1842 {
1843 const char *pszWhy = NULL;
1844 if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1845 pszWhy = "execution engine is neither HM nor IEM";
1846 else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1847 pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1848 else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1849 pszWhy = "NX is not available on the host";
1850 if (pszWhy)
1851 {
1852 LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1853 fVmxEpt = false;
1854 }
1855 }
1856 else if (fVmxUnrestrictedGuest)
1857 {
1858 LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1859 fVmxUnrestrictedGuest = false;
1860 }
1861
1862 /*
1863 * Initialize the set of VMX features we emulate.
1864 *
1865 * Note! Some bits might be reported as 1 always if they fall under the
1866 * default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1867 */
1868 CPUMFEATURES EmuFeat;
1869 RT_ZERO(EmuFeat);
1870 EmuFeat.fVmx = 1;
1871 EmuFeat.fVmxInsOutInfo = 1;
1872 EmuFeat.fVmxExtIntExit = 1;
1873 EmuFeat.fVmxNmiExit = 1;
1874 EmuFeat.fVmxVirtNmi = 1;
1875 EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1876 EmuFeat.fVmxPostedInt = 0;
1877 EmuFeat.fVmxIntWindowExit = 1;
1878 EmuFeat.fVmxTscOffsetting = 1;
1879 EmuFeat.fVmxHltExit = 1;
1880 EmuFeat.fVmxInvlpgExit = 1;
1881 EmuFeat.fVmxMwaitExit = 1;
1882 EmuFeat.fVmxRdpmcExit = 1;
1883 EmuFeat.fVmxRdtscExit = 1;
1884 EmuFeat.fVmxCr3LoadExit = 1;
1885 EmuFeat.fVmxCr3StoreExit = 1;
1886 EmuFeat.fVmxTertiaryExecCtls = 0;
1887 EmuFeat.fVmxCr8LoadExit = 1;
1888 EmuFeat.fVmxCr8StoreExit = 1;
1889 EmuFeat.fVmxUseTprShadow = 1;
1890 EmuFeat.fVmxNmiWindowExit = 1;
1891 EmuFeat.fVmxMovDRxExit = 1;
1892 EmuFeat.fVmxUncondIoExit = 1;
1893 EmuFeat.fVmxUseIoBitmaps = 1;
1894 EmuFeat.fVmxMonitorTrapFlag = 0;
1895 EmuFeat.fVmxUseMsrBitmaps = 1;
1896 EmuFeat.fVmxMonitorExit = 1;
1897 EmuFeat.fVmxPauseExit = 1;
1898 EmuFeat.fVmxSecondaryExecCtls = 1;
1899 EmuFeat.fVmxVirtApicAccess = 1;
1900 EmuFeat.fVmxEpt = fVmxEpt;
1901 EmuFeat.fVmxDescTableExit = 1;
1902 EmuFeat.fVmxRdtscp = 1;
1903 EmuFeat.fVmxVirtX2ApicMode = 0;
1904 EmuFeat.fVmxVpid = 1;
1905 EmuFeat.fVmxWbinvdExit = 1;
1906 EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1907 EmuFeat.fVmxApicRegVirt = 0;
1908 EmuFeat.fVmxVirtIntDelivery = 0;
1909 EmuFeat.fVmxPauseLoopExit = 1;
1910 EmuFeat.fVmxRdrandExit = 1;
1911 EmuFeat.fVmxInvpcid = 1;
1912 EmuFeat.fVmxVmFunc = 0;
1913 EmuFeat.fVmxVmcsShadowing = 0;
1914 EmuFeat.fVmxRdseedExit = 1;
1915 EmuFeat.fVmxPml = 0;
1916 EmuFeat.fVmxEptXcptVe = 0;
1917 EmuFeat.fVmxConcealVmxFromPt = 0;
1918 EmuFeat.fVmxXsavesXrstors = 0;
1919 EmuFeat.fVmxPasidTranslate = 0;
1920 EmuFeat.fVmxModeBasedExecuteEpt = 0;
1921 EmuFeat.fVmxSppEpt = 0;
1922 EmuFeat.fVmxPtEpt = 0;
1923 EmuFeat.fVmxUseTscScaling = 0;
1924 EmuFeat.fVmxUserWaitPause = 0;
1925 EmuFeat.fVmxPconfig = 0;
1926 EmuFeat.fVmxEnclvExit = 0;
1927 EmuFeat.fVmxBusLockDetect = 0;
1928 EmuFeat.fVmxInstrTimeout = 0;
1929 EmuFeat.fVmxLoadIwKeyExit = 0;
1930 EmuFeat.fVmxHlat = 0;
1931 EmuFeat.fVmxEptPagingWrite = 0;
1932 EmuFeat.fVmxGstPagingVerify = 0;
1933 EmuFeat.fVmxIpiVirt = 0;
1934 EmuFeat.fVmxVirtSpecCtrl = 0;
1935 EmuFeat.fVmxEntryLoadDebugCtls = 1;
1936 EmuFeat.fVmxIa32eModeGuest = 1;
1937 EmuFeat.fVmxEntryLoadEferMsr = 1;
1938 EmuFeat.fVmxEntryLoadPatMsr = 1;
1939 EmuFeat.fVmxExitSaveDebugCtls = 1;
1940 EmuFeat.fVmxHostAddrSpaceSize = 1;
1941 EmuFeat.fVmxExitAckExtInt = 1;
1942 EmuFeat.fVmxExitSavePatMsr = 1;
1943 EmuFeat.fVmxExitLoadPatMsr = 1;
1944 EmuFeat.fVmxExitSaveEferMsr = 1;
1945 EmuFeat.fVmxExitLoadEferMsr = 1;
1946 EmuFeat.fVmxSavePreemptTimer = 0 & fVmxPreemptTimer; /* Cannot be enabled if VMX-preemption timer is disabled. */
1947 EmuFeat.fVmxSecondaryExitCtls = 0;
1948 EmuFeat.fVmxExitSaveEferLma = 1 | fVmxUnrestrictedGuest; /* Cannot be disabled if unrestricted guest is enabled. */
1949 EmuFeat.fVmxPt = 0;
1950 EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1951 EmuFeat.fVmxEntryInjectSoftInt = 1;
1952
1953 /*
1954 * Merge guest features.
1955 *
1956 * When hardware-assisted VMX may be used, any feature we emulate must also be supported
1957 * by the hardware, hence we merge our emulated features with the host features below.
1958 */
1959 PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1960 PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1961 Assert(pBaseFeat->fVmx);
1962#define CPUMVMX_SET_GST_FEAT(a_Feat) \
1963 do { \
1964 pGuestFeat->a_Feat = (pBaseFeat->a_Feat & EmuFeat.a_Feat); \
1965 } while (0)
1966
1967 CPUMVMX_SET_GST_FEAT(fVmxInsOutInfo);
1968 CPUMVMX_SET_GST_FEAT(fVmxExtIntExit);
1969 CPUMVMX_SET_GST_FEAT(fVmxNmiExit);
1970 CPUMVMX_SET_GST_FEAT(fVmxVirtNmi);
1971 CPUMVMX_SET_GST_FEAT(fVmxPreemptTimer);
1972 CPUMVMX_SET_GST_FEAT(fVmxPostedInt);
1973 CPUMVMX_SET_GST_FEAT(fVmxIntWindowExit);
1974 CPUMVMX_SET_GST_FEAT(fVmxTscOffsetting);
1975 CPUMVMX_SET_GST_FEAT(fVmxHltExit);
1976 CPUMVMX_SET_GST_FEAT(fVmxInvlpgExit);
1977 CPUMVMX_SET_GST_FEAT(fVmxMwaitExit);
1978 CPUMVMX_SET_GST_FEAT(fVmxRdpmcExit);
1979 CPUMVMX_SET_GST_FEAT(fVmxRdtscExit);
1980 CPUMVMX_SET_GST_FEAT(fVmxCr3LoadExit);
1981 CPUMVMX_SET_GST_FEAT(fVmxCr3StoreExit);
1982 CPUMVMX_SET_GST_FEAT(fVmxTertiaryExecCtls);
1983 CPUMVMX_SET_GST_FEAT(fVmxCr8LoadExit);
1984 CPUMVMX_SET_GST_FEAT(fVmxCr8StoreExit);
1985 CPUMVMX_SET_GST_FEAT(fVmxUseTprShadow);
1986 CPUMVMX_SET_GST_FEAT(fVmxNmiWindowExit);
1987 CPUMVMX_SET_GST_FEAT(fVmxMovDRxExit);
1988 CPUMVMX_SET_GST_FEAT(fVmxUncondIoExit);
1989 CPUMVMX_SET_GST_FEAT(fVmxUseIoBitmaps);
1990 CPUMVMX_SET_GST_FEAT(fVmxMonitorTrapFlag);
1991 CPUMVMX_SET_GST_FEAT(fVmxUseMsrBitmaps);
1992 CPUMVMX_SET_GST_FEAT(fVmxMonitorExit);
1993 CPUMVMX_SET_GST_FEAT(fVmxPauseExit);
1994 CPUMVMX_SET_GST_FEAT(fVmxSecondaryExecCtls);
1995 CPUMVMX_SET_GST_FEAT(fVmxVirtApicAccess);
1996 CPUMVMX_SET_GST_FEAT(fVmxEpt);
1997 CPUMVMX_SET_GST_FEAT(fVmxDescTableExit);
1998 CPUMVMX_SET_GST_FEAT(fVmxRdtscp);
1999 CPUMVMX_SET_GST_FEAT(fVmxVirtX2ApicMode);
2000 CPUMVMX_SET_GST_FEAT(fVmxVpid);
2001 CPUMVMX_SET_GST_FEAT(fVmxWbinvdExit);
2002 CPUMVMX_SET_GST_FEAT(fVmxUnrestrictedGuest);
2003 CPUMVMX_SET_GST_FEAT(fVmxApicRegVirt);
2004 CPUMVMX_SET_GST_FEAT(fVmxVirtIntDelivery);
2005 CPUMVMX_SET_GST_FEAT(fVmxPauseLoopExit);
2006 CPUMVMX_SET_GST_FEAT(fVmxRdrandExit);
2007 CPUMVMX_SET_GST_FEAT(fVmxInvpcid);
2008 CPUMVMX_SET_GST_FEAT(fVmxVmFunc);
2009 CPUMVMX_SET_GST_FEAT(fVmxVmcsShadowing);
2010 CPUMVMX_SET_GST_FEAT(fVmxRdseedExit);
2011 CPUMVMX_SET_GST_FEAT(fVmxPml);
2012 CPUMVMX_SET_GST_FEAT(fVmxEptXcptVe);
2013 CPUMVMX_SET_GST_FEAT(fVmxConcealVmxFromPt);
2014 CPUMVMX_SET_GST_FEAT(fVmxXsavesXrstors);
2015 CPUMVMX_SET_GST_FEAT(fVmxPasidTranslate);
2016 CPUMVMX_SET_GST_FEAT(fVmxModeBasedExecuteEpt);
2017 CPUMVMX_SET_GST_FEAT(fVmxSppEpt);
2018 CPUMVMX_SET_GST_FEAT(fVmxPtEpt);
2019 CPUMVMX_SET_GST_FEAT(fVmxUseTscScaling);
2020 CPUMVMX_SET_GST_FEAT(fVmxUserWaitPause);
2021 CPUMVMX_SET_GST_FEAT(fVmxPconfig);
2022 CPUMVMX_SET_GST_FEAT(fVmxEnclvExit);
2023 CPUMVMX_SET_GST_FEAT(fVmxBusLockDetect);
2024 CPUMVMX_SET_GST_FEAT(fVmxInstrTimeout);
2025 CPUMVMX_SET_GST_FEAT(fVmxLoadIwKeyExit);
2026 CPUMVMX_SET_GST_FEAT(fVmxHlat);
2027 CPUMVMX_SET_GST_FEAT(fVmxEptPagingWrite);
2028 CPUMVMX_SET_GST_FEAT(fVmxGstPagingVerify);
2029 CPUMVMX_SET_GST_FEAT(fVmxIpiVirt);
2030 CPUMVMX_SET_GST_FEAT(fVmxVirtSpecCtrl);
2031 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadDebugCtls);
2032 CPUMVMX_SET_GST_FEAT(fVmxIa32eModeGuest);
2033 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadEferMsr);
2034 CPUMVMX_SET_GST_FEAT(fVmxEntryLoadPatMsr);
2035 CPUMVMX_SET_GST_FEAT(fVmxExitSaveDebugCtls);
2036 CPUMVMX_SET_GST_FEAT(fVmxHostAddrSpaceSize);
2037 CPUMVMX_SET_GST_FEAT(fVmxExitAckExtInt);
2038 CPUMVMX_SET_GST_FEAT(fVmxExitSavePatMsr);
2039 CPUMVMX_SET_GST_FEAT(fVmxExitLoadPatMsr);
2040 CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferMsr);
2041 CPUMVMX_SET_GST_FEAT(fVmxExitLoadEferMsr);
2042 CPUMVMX_SET_GST_FEAT(fVmxSavePreemptTimer);
2043 CPUMVMX_SET_GST_FEAT(fVmxSecondaryExitCtls);
2044 CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferLma);
2045 CPUMVMX_SET_GST_FEAT(fVmxPt);
2046 CPUMVMX_SET_GST_FEAT(fVmxVmwriteAll);
2047 CPUMVMX_SET_GST_FEAT(fVmxEntryInjectSoftInt);
2048
2049#undef CPUMVMX_SET_GST_FEAT
2050
2051#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
2052 /* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
2053 if ( pGuestFeat->fVmxPreemptTimer
2054 && HMIsSubjectToVmxPreemptTimerErratum())
2055 {
2056 LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
2057 pGuestFeat->fVmxPreemptTimer = 0;
2058 pGuestFeat->fVmxSavePreemptTimer = 0;
2059 }
2060#endif
2061
2062 /* Sanity checking. */
2063 if (!pGuestFeat->fVmxSecondaryExecCtls)
2064 {
2065 Assert(!pGuestFeat->fVmxVirtApicAccess);
2066 Assert(!pGuestFeat->fVmxEpt);
2067 Assert(!pGuestFeat->fVmxDescTableExit);
2068 Assert(!pGuestFeat->fVmxRdtscp);
2069 Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2070 Assert(!pGuestFeat->fVmxVpid);
2071 Assert(!pGuestFeat->fVmxWbinvdExit);
2072 Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2073 Assert(!pGuestFeat->fVmxApicRegVirt);
2074 Assert(!pGuestFeat->fVmxVirtIntDelivery);
2075 Assert(!pGuestFeat->fVmxPauseLoopExit);
2076 Assert(!pGuestFeat->fVmxRdrandExit);
2077 Assert(!pGuestFeat->fVmxInvpcid);
2078 Assert(!pGuestFeat->fVmxVmFunc);
2079 Assert(!pGuestFeat->fVmxVmcsShadowing);
2080 Assert(!pGuestFeat->fVmxRdseedExit);
2081 Assert(!pGuestFeat->fVmxPml);
2082 Assert(!pGuestFeat->fVmxEptXcptVe);
2083 Assert(!pGuestFeat->fVmxConcealVmxFromPt);
2084 Assert(!pGuestFeat->fVmxXsavesXrstors);
2085 Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
2086 Assert(!pGuestFeat->fVmxSppEpt);
2087 Assert(!pGuestFeat->fVmxPtEpt);
2088 Assert(!pGuestFeat->fVmxUseTscScaling);
2089 Assert(!pGuestFeat->fVmxUserWaitPause);
2090 Assert(!pGuestFeat->fVmxEnclvExit);
2091 }
2092 else if (pGuestFeat->fVmxUnrestrictedGuest)
2093 {
2094 /* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2095 Assert(pGuestFeat->fVmxExitSaveEferLma);
2096 /* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2097 Assert(pGuestFeat->fVmxEpt);
2098 }
2099
2100 if (!pGuestFeat->fVmxTertiaryExecCtls)
2101 {
2102 Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2103 Assert(!pGuestFeat->fVmxHlat);
2104 Assert(!pGuestFeat->fVmxEptPagingWrite);
2105 Assert(!pGuestFeat->fVmxGstPagingVerify);
2106 Assert(!pGuestFeat->fVmxIpiVirt);
2107 Assert(!pGuestFeat->fVmxVirtSpecCtrl);
2108 }
2109
2110 /*
2111 * Finally initialize the VMX guest MSRs.
2112 */
2113 cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2114}
2115
2116
2117/**
2118 * Gets the host hardware-virtualization MSRs.
2119 *
2120 * @returns VBox status code.
2121 * @param pMsrs Where to store the MSRs.
2122 */
2123static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2124{
2125 Assert(pMsrs);
2126
2127 uint32_t fCaps = 0;
2128 int rc = SUPR3QueryVTCaps(&fCaps);
2129 if (RT_SUCCESS(rc))
2130 {
2131 if (fCaps & (SUPVTCAPS_VT_X | SUPVTCAPS_AMD_V))
2132 {
2133 SUPHWVIRTMSRS HwvirtMsrs;
2134 rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2135 if (RT_SUCCESS(rc))
2136 {
2137 if (fCaps & SUPVTCAPS_VT_X)
2138 HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2139 else
2140 HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2141 return VINF_SUCCESS;
2142 }
2143
2144 LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2145 return rc;
2146 }
2147
2148 LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2149 return VERR_INTERNAL_ERROR_5;
2150 }
2151
2152 LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2153 return VINF_SUCCESS;
2154}
2155
2156
2157/**
2158 * @callback_method_impl{FNTMTIMERINT,
2159 * Callback that fires when the nested VMX-preemption timer expired.}
2160 */
2161static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2162{
2163 RT_NOREF(pVM, hTimer);
2164 PVMCPU pVCpu = (PVMCPUR3)pvUser;
2165 AssertPtr(pVCpu);
2166 VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2167}
2168
2169
2170/**
2171 * Initializes the CPUM.
2172 *
2173 * @returns VBox status code.
2174 * @param pVM The cross context VM structure.
2175 */
2176VMMR3DECL(int) CPUMR3Init(PVM pVM)
2177{
2178 LogFlow(("CPUMR3Init\n"));
2179
2180 /*
2181 * Assert alignment, sizes and tables.
2182 */
2183 AssertCompileMemberAlignment(VM, cpum.s, 32);
2184 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2185 AssertCompileSizeAlignment(CPUMCTX, 64);
2186 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2187 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2188 AssertCompileMemberAlignment(VM, cpum, 64);
2189 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2190#ifdef VBOX_STRICT
2191 int rc2 = cpumR3MsrStrictInitChecks();
2192 AssertRCReturn(rc2, rc2);
2193#endif
2194
2195 /*
2196 * Gather info about the host CPU.
2197 */
2198#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2199 if (!ASMHasCpuId())
2200 {
2201 LogRel(("The CPU doesn't support CPUID!\n"));
2202 return VERR_UNSUPPORTED_CPU;
2203 }
2204
2205 pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2206#endif
2207
2208 CPUMMSRS HostMsrs;
2209 RT_ZERO(HostMsrs);
2210 int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2211 AssertLogRelRCReturn(rc, rc);
2212
2213#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2214 /* Use the host features detected by CPUMR0ModuleInit if available. */
2215 if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2216 g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2217 else
2218 {
2219 PCPUMCPUIDLEAF paLeaves;
2220 uint32_t cLeaves;
2221 rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2222 AssertLogRelRCReturn(rc, rc);
2223
2224 rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2225 RTMemFree(paLeaves);
2226 AssertLogRelRCReturn(rc, rc);
2227 }
2228 pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2229 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2230
2231#elif defined(RT_ARCH_ARM64)
2232 /** @todo we shouldn't be using the x86/AMD64 CPUMFEATURES for HostFeatures,
2233 * but it's too much work to fix that now. So, instead we just set
2234 * the bits we think are important for CPUMR3CpuId... This must
2235 * correspond to what IEM can emulate on ARM64. */
2236 pVM->cpum.s.HostFeatures.fCmpXchg8b = true;
2237 pVM->cpum.s.HostFeatures.fCmpXchg16b = true;
2238 pVM->cpum.s.HostFeatures.fPopCnt = true;
2239 pVM->cpum.s.HostFeatures.fAbm = true;
2240 pVM->cpum.s.HostFeatures.fBmi1 = true;
2241 pVM->cpum.s.HostFeatures.fBmi2 = true;
2242 pVM->cpum.s.HostFeatures.fAdx = true;
2243#endif
2244
2245 /*
2246 * Check that the CPU supports the minimum features we require.
2247 */
2248#if defined(RT_ARCH_AMD64) || defined(RT_ARCH_X86)
2249 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2250 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2251 if (!pVM->cpum.s.HostFeatures.fMmx)
2252 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2253 if (!pVM->cpum.s.HostFeatures.fTsc)
2254 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2255#endif
2256
2257 /*
2258 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
2259 */
2260 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
2261 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2262
2263 /*
2264 * Figure out which XSAVE/XRSTOR features are available on the host.
2265 */
2266 uint64_t fXcr0Host = 0;
2267 uint64_t fXStateHostMask = 0;
2268#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2269 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2270 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2271 {
2272 fXStateHostMask = fXcr0Host = ASMGetXcr0();
2273 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
2274 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
2275 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2276 }
2277#endif
2278 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2279 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2280 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2281
2282 /*
2283 * Initialize the host XSAVE/XRSTOR mask.
2284 */
2285#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2286 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2287 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2288 AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2289 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.abXState)
2290 && pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.abXState)
2291 , VERR_CPUM_IPE_2);
2292#endif
2293
2294 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2295 {
2296 PVMCPU pVCpu = pVM->apCpusR3[i];
2297
2298 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2299 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2300 }
2301
2302 /*
2303 * Register saved state data item.
2304 */
2305 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2306 NULL, cpumR3LiveExec, NULL,
2307 NULL, cpumR3SaveExec, NULL,
2308 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2309 if (RT_FAILURE(rc))
2310 return rc;
2311
2312 /*
2313 * Register info handlers and registers with the debugger facility.
2314 */
2315 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2316 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2317 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2318 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2319 DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2320 &cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2321 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2322 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2323 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2324 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2325 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2326 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2327 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2328 &cpumR3CpuIdInfo);
2329 DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2330 &cpumR3InfoVmxFeatures);
2331
2332 rc = cpumR3DbgInit(pVM);
2333 if (RT_FAILURE(rc))
2334 return rc;
2335
2336#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
2337 /*
2338 * Check if we need to workaround partial/leaky FPU handling.
2339 */
2340 cpumR3CheckLeakyFpu(pVM);
2341#endif
2342
2343 /*
2344 * Initialize the Guest CPUID and MSR states.
2345 */
2346 rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2347 if (RT_FAILURE(rc))
2348 return rc;
2349
2350 /*
2351 * Generate the RFLAGS cookie.
2352 */
2353 pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 | CPUMX86EFLAGS_INT_MASK_64);
2354
2355 /*
2356 * Init the VMX/SVM state.
2357 *
2358 * This must be done after initializing CPUID/MSR features as we access the
2359 * the VMX/SVM guest features below.
2360 *
2361 * In the case of nested VT-x, we also need to create the per-VCPU
2362 * VMX preemption timers.
2363 */
2364 if (pVM->cpum.s.GuestFeatures.fVmx)
2365 cpumR3InitVmxHwVirtState(pVM);
2366 else if (pVM->cpum.s.GuestFeatures.fSvm)
2367 cpumR3InitSvmHwVirtState(pVM);
2368 else
2369 Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2370
2371 /*
2372 * Initialize the general guest CPU state.
2373 */
2374 CPUMR3Reset(pVM);
2375
2376 return VINF_SUCCESS;
2377}
2378
2379
2380/**
2381 * Applies relocations to data and code managed by this
2382 * component. This function will be called at init and
2383 * whenever the VMM need to relocate it self inside the GC.
2384 *
2385 * The CPUM will update the addresses used by the switcher.
2386 *
2387 * @param pVM The cross context VM structure.
2388 */
2389VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2390{
2391 RT_NOREF(pVM);
2392}
2393
2394
2395/**
2396 * Terminates the CPUM.
2397 *
2398 * Termination means cleaning up and freeing all resources,
2399 * the VM it self is at this point powered off or suspended.
2400 *
2401 * @returns VBox status code.
2402 * @param pVM The cross context VM structure.
2403 */
2404VMMR3DECL(int) CPUMR3Term(PVM pVM)
2405{
2406#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2407 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2408 {
2409 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2410 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2411 pVCpu->cpum.s.uMagic = 0;
2412 pvCpu->cpum.s.Guest.dr[5] = 0;
2413 }
2414#endif
2415
2416 if (pVM->cpum.s.GuestFeatures.fVmx)
2417 {
2418 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2419 {
2420 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2421 if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2422 {
2423 int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2424 pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2425 }
2426 }
2427 }
2428 return VINF_SUCCESS;
2429}
2430
2431
2432/**
2433 * Resets a virtual CPU.
2434 *
2435 * Used by CPUMR3Reset and CPU hot plugging.
2436 *
2437 * @param pVM The cross context VM structure.
2438 * @param pVCpu The cross context virtual CPU structure of the CPU that is
2439 * being reset. This may differ from the current EMT.
2440 */
2441VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2442{
2443 /** @todo anything different for VCPU > 0? */
2444 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2445
2446 /*
2447 * Initialize everything to ZERO first.
2448 */
2449 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2450
2451 RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2452
2453 pVCpu->cpum.s.fUseFlags = fUseFlags;
2454
2455 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
2456 pCtx->eip = 0x0000fff0;
2457 pCtx->edx = 0x00000600; /* P6 processor */
2458
2459 Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK | X86_EFL_RAZ_LO_MASK | X86_EFL_RA1_MASK)) == 0);
2460 pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie | X86_EFL_RA1_MASK;
2461
2462 pCtx->cs.Sel = 0xf000;
2463 pCtx->cs.ValidSel = 0xf000;
2464 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2465 pCtx->cs.u64Base = UINT64_C(0xffff0000);
2466 pCtx->cs.u32Limit = 0x0000ffff;
2467 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2468 pCtx->cs.Attr.n.u1Present = 1;
2469 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2470
2471 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2472 pCtx->ds.u32Limit = 0x0000ffff;
2473 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2474 pCtx->ds.Attr.n.u1Present = 1;
2475 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2476
2477 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2478 pCtx->es.u32Limit = 0x0000ffff;
2479 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2480 pCtx->es.Attr.n.u1Present = 1;
2481 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2482
2483 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2484 pCtx->fs.u32Limit = 0x0000ffff;
2485 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2486 pCtx->fs.Attr.n.u1Present = 1;
2487 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2488
2489 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2490 pCtx->gs.u32Limit = 0x0000ffff;
2491 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2492 pCtx->gs.Attr.n.u1Present = 1;
2493 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2494
2495 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2496 pCtx->ss.u32Limit = 0x0000ffff;
2497 pCtx->ss.Attr.n.u1Present = 1;
2498 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2499 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2500
2501 pCtx->idtr.cbIdt = 0xffff;
2502 pCtx->gdtr.cbGdt = 0xffff;
2503
2504 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2505 pCtx->ldtr.u32Limit = 0xffff;
2506 pCtx->ldtr.Attr.n.u1Present = 1;
2507 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2508
2509 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2510 pCtx->tr.u32Limit = 0xffff;
2511 pCtx->tr.Attr.n.u1Present = 1;
2512 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2513
2514 pCtx->dr[6] = X86_DR6_INIT_VAL;
2515 pCtx->dr[7] = X86_DR7_INIT_VAL;
2516
2517 PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2518 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2519 pFpuCtx->FCW = 0x37f;
2520
2521 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2522 IA-32 Processor States Following Power-up, Reset, or INIT */
2523 pFpuCtx->MXCSR = 0x1F80;
2524 pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2525
2526 pCtx->aXcr[0] = XSAVE_C_X87;
2527 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2528 {
2529 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2530 as we don't know what happened before. (Bother optimize later?) */
2531 pCtx->XState.Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
2532 }
2533
2534 /*
2535 * MSRs.
2536 */
2537 /* Init PAT MSR */
2538 pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2539
2540 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2541 * The Intel docs don't mention it. */
2542 Assert(!pCtx->msrEFER);
2543
2544 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2545 is supposed to be here, just trying provide useful/sensible values. */
2546 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2547 if (pRange)
2548 {
2549 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2550 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2551 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2552 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2553 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2554 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2555 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2556 }
2557
2558 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2559
2560 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2561 * called from each EMT while we're getting called by CPUMR3Reset()
2562 * iteratively on the same thread. Fix later. */
2563#if 0 /** @todo r=bird: This we will do in TM, not here. */
2564 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2565 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2566#endif
2567
2568
2569 /* C-state control. Guesses. */
2570 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
2571 /* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2572 * it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2573 * functionality. The default value must be different due to incompatible write mask.
2574 */
2575 if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2576 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2577 else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2578 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2579
2580 /*
2581 * Hardware virtualization state.
2582 */
2583 CPUMSetGuestGif(pCtx, true);
2584 Assert(!pVM->cpum.s.GuestFeatures.fVmx || !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2585 if (pVM->cpum.s.GuestFeatures.fVmx)
2586 cpumR3ResetVmxHwVirtState(pVCpu);
2587 else if (pVM->cpum.s.GuestFeatures.fSvm)
2588 cpumR3ResetSvmHwVirtState(pVCpu);
2589}
2590
2591
2592/**
2593 * Resets the CPU.
2594 *
2595 * @param pVM The cross context VM structure.
2596 */
2597VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2598{
2599 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2600 {
2601 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2602 CPUMR3ResetCpu(pVM, pVCpu);
2603
2604#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2605
2606 /* Magic marker for searching in crash dumps. */
2607 strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2608 pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2609 pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2610#endif
2611 }
2612}
2613
2614
2615
2616
2617/**
2618 * Pass 0 live exec callback.
2619 *
2620 * @returns VINF_SSM_DONT_CALL_AGAIN.
2621 * @param pVM The cross context VM structure.
2622 * @param pSSM The saved state handle.
2623 * @param uPass The pass (0).
2624 */
2625static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2626{
2627 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2628 cpumR3SaveCpuId(pVM, pSSM);
2629 return VINF_SSM_DONT_CALL_AGAIN;
2630}
2631
2632
2633/**
2634 * Execute state save operation.
2635 *
2636 * @returns VBox status code.
2637 * @param pVM The cross context VM structure.
2638 * @param pSSM SSM operation handle.
2639 */
2640static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2641{
2642 /*
2643 * Save.
2644 */
2645 SSMR3PutU32(pSSM, pVM->cCpus);
2646 SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2647 CPUMCTX DummyHyperCtx;
2648 RT_ZERO(DummyHyperCtx);
2649 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2650 {
2651 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2652 PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2653
2654 /** @todo ditch this the next time we change the saved state. */
2655 SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2656
2657 uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2658 pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2659 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2660 pGstCtx->rflags.uBoth = fSavedRFlags;
2661
2662 SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2663 if (pGstCtx->fXStateMask != 0)
2664 SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2665 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2666 {
2667 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2668 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2669 }
2670 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2671 {
2672 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2673 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2674 }
2675 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2676 {
2677 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2678 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2679 }
2680 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2681 {
2682 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2683 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2684 }
2685 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2686 {
2687 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2688 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2689 }
2690 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2691 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2692 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2693 SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2694 if (pVM->cpum.s.GuestFeatures.fSvm)
2695 {
2696 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2697 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2698 SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2699 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2700 SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2701 SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2702 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2703 g_aSvmHwvirtHostState, NULL /* pvUser */);
2704 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2705 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2706 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2707 /* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2708 SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2709 SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2710 }
2711 if (pVM->cpum.s.GuestFeatures.fVmx)
2712 {
2713 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2714 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2715 SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2716 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2717 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2718 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2719 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2720 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2721 SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2722 0, g_aVmxHwvirtVmcs, NULL);
2723 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2724 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2725 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2726 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2727 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2728 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2729 SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2730 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2731 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2732 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2733 SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2734 SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2735 SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK | MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2736 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2737 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2738 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2739 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2740 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2741 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2742 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2743 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2744 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2745 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2746 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2747 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2748 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2749 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2750 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2751 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2752 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2753 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2754 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2755 SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2756 }
2757 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2758 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2759 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2760 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2761 }
2762
2763 cpumR3SaveCpuId(pVM, pSSM);
2764 return VINF_SUCCESS;
2765}
2766
2767
2768/**
2769 * @callback_method_impl{FNSSMINTLOADPREP}
2770 */
2771static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2772{
2773 NOREF(pSSM);
2774 pVM->cpum.s.fPendingRestore = true;
2775 return VINF_SUCCESS;
2776}
2777
2778
2779/**
2780 * @callback_method_impl{FNSSMINTLOADEXEC}
2781 */
2782static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2783{
2784 int rc; /* Only for AssertRCReturn use. */
2785
2786 /*
2787 * Validate version.
2788 */
2789 if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
2790 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2791 && uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2792 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2793 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2794 && uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2795 && uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2796 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2797 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2798 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2799 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2800 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2801 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2802 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2803 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2804 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2805 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2806 {
2807 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2808 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2809 }
2810
2811 if (uPass == SSM_PASS_FINAL)
2812 {
2813 /*
2814 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2815 * really old SSM file versions.)
2816 */
2817 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2818 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2819 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2820 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2821
2822 /*
2823 * Figure x86 and ctx field definitions to use for older states.
2824 */
2825 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2826 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2827 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2828 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2829 {
2830 paCpumCtx1Fields = g_aCpumX87FieldsV16;
2831 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2832 }
2833 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2834 {
2835 paCpumCtx1Fields = g_aCpumX87FieldsMem;
2836 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2837 }
2838
2839 /*
2840 * The hyper state used to preceed the CPU count. Starting with
2841 * XSAVE it was moved down till after we've got the count.
2842 */
2843 CPUMCTX HyperCtxIgnored;
2844 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2845 {
2846 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2847 {
2848 X86FXSTATE Ign;
2849 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2850 SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2851 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2852 }
2853 }
2854
2855 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2856 {
2857 uint32_t cCpus;
2858 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2859 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2860 VERR_SSM_UNEXPECTED_DATA);
2861 }
2862 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2863 || pVM->cCpus == 1,
2864 ("cCpus=%u\n", pVM->cCpus),
2865 VERR_SSM_UNEXPECTED_DATA);
2866
2867 uint32_t cbMsrs = 0;
2868 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2869 {
2870 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2871 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2872 VERR_SSM_UNEXPECTED_DATA);
2873 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2874 VERR_SSM_UNEXPECTED_DATA);
2875 }
2876
2877 /*
2878 * Do the per-CPU restoring.
2879 */
2880 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2881 {
2882 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2883 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2884
2885 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2886 {
2887 /*
2888 * The XSAVE saved state layout moved the hyper state down here.
2889 */
2890 rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2891 AssertRCReturn(rc, rc);
2892
2893 /*
2894 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2895 */
2896 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2897 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2898 AssertRCReturn(rc, rc);
2899
2900 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2901 if (pGstCtx->fXStateMask != 0)
2902 {
2903 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2904 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2905 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2906 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2907 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2908 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2909 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2910 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2911 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2912 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2913 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2914 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2915 }
2916
2917 /* Check that the XCR0 mask is valid (invalid results in #GP). */
2918 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2919 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2920 {
2921 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
2922 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2923 VERR_CPUM_INVALID_XCR0);
2924 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2925 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2926 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
2927 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2928 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
2929 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
2930 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
2931 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2932 }
2933
2934 /* Check that the XCR1 is zero, as we don't implement it yet. */
2935 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2936
2937 /*
2938 * Restore the individual extended state components we support.
2939 */
2940 if (pGstCtx->fXStateMask != 0)
2941 {
2942 rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2943 0, g_aCpumXSaveHdrFields, NULL);
2944 AssertRCReturn(rc, rc);
2945 AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2946 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
2947 pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2948 VERR_CPUM_INVALID_XSAVE_HDR);
2949 }
2950 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2951 {
2952 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2953 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2954 }
2955 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2956 {
2957 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2958 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2959 }
2960 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2961 {
2962 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2963 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2964 }
2965 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2966 {
2967 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2968 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2969 }
2970 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2971 {
2972 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2973 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2974 }
2975 if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2976 {
2977 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2978 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2979 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2980 SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2981 }
2982 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2983 {
2984 if (pVM->cpum.s.GuestFeatures.fSvm)
2985 {
2986 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2987 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2988 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2989 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2990 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2991 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2992 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2993 0 /* fFlags */, g_aSvmHwvirtHostState, NULL /* pvUser */);
2994 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2995 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2996 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2997
2998 uint32_t fSavedLocalFFs = 0;
2999 rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
3000 AssertRCReturn(rc, rc);
3001 Assert(fSavedLocalFFs == 0 || fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
3002 pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
3003
3004 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
3005 }
3006 }
3007 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
3008 {
3009 if (pVM->cpum.s.GuestFeatures.fVmx)
3010 {
3011 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
3012 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
3013 SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
3014 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
3015 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
3016 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
3017 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
3018 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
3019 0, g_aVmxHwvirtVmcs, NULL);
3020 SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
3021 0, g_aVmxHwvirtVmcs, NULL);
3022 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
3023 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
3024 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
3025 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
3026 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
3027 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
3028 SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
3029 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
3030 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
3031 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
3032 SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
3033 SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
3034 SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
3035 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
3036 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
3037 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
3038 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
3039 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
3040 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
3041 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
3042 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
3043 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
3044 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
3045 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
3046 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
3047 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
3048 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
3049 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
3050 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
3051 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
3052 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
3053 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
3054 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
3055 if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
3056 SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
3057 }
3058 }
3059 }
3060 else
3061 {
3062 /*
3063 * Pre XSAVE saved state.
3064 */
3065 SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
3066 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
3067 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
3068 }
3069
3070 /*
3071 * Restore a couple of flags and the MSRs.
3072 */
3073 uint32_t fIgnoredUsedFlags = 0;
3074 rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
3075 AssertRCReturn(rc, rc);
3076 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
3077
3078 rc = VINF_SUCCESS;
3079 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
3080 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
3081 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
3082 {
3083 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
3084 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
3085 }
3086 AssertRCReturn(rc, rc);
3087
3088 /* Deal with the reusing of reserved RFLAGS bits. */
3089 pGstCtx->rflags.uBoth |= pVM->cpum.s.fReservedRFlagsCookie;
3090
3091 /* REM and other may have cleared must-be-one fields in DR6 and
3092 DR7, fix these. */
3093 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
3094 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
3095 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
3096 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
3097 }
3098
3099 /* Older states does not have the internal selector register flags
3100 and valid selector value. Supply those. */
3101 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3102 {
3103 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3104 {
3105 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3106 bool const fValid = true /*!VM_IS_RAW_MODE_ENABLED(pVM)*/
3107 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3108 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3109 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3110 if (fValid)
3111 {
3112 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3113 {
3114 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3115 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3116 }
3117
3118 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3119 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3120 }
3121 else
3122 {
3123 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3124 {
3125 paSelReg[iSelReg].fFlags = 0;
3126 paSelReg[iSelReg].ValidSel = 0;
3127 }
3128
3129 /* This might not be 104% correct, but I think it's close
3130 enough for all practical purposes... (REM always loaded
3131 LDTR registers.) */
3132 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3133 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3134 }
3135 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3136 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3137 }
3138 }
3139
3140 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3141 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3142 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3143 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3144 {
3145 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3146 pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3147 }
3148
3149 /*
3150 * A quick sanity check.
3151 */
3152 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3153 {
3154 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3155 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3156 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3157 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3158 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3159 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3160 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3161 }
3162 }
3163
3164 pVM->cpum.s.fPendingRestore = false;
3165
3166 /*
3167 * Guest CPUIDs (and VMX MSR features).
3168 */
3169 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3170 {
3171 CPUMMSRS GuestMsrs;
3172 RT_ZERO(GuestMsrs);
3173
3174 CPUMFEATURES BaseFeatures;
3175 bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3176 if (fVmxGstFeat)
3177 {
3178 /*
3179 * At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3180 * However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3181 * here so we can compare them for compatibility after exploding guest features.
3182 */
3183 BaseFeatures = pVM->cpum.s.GuestFeatures;
3184
3185 /* Use the VMX MSR features from the saved state while exploding guest features. */
3186 GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3187 }
3188
3189 /* Load CPUID and explode guest features. */
3190 rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3191 if (fVmxGstFeat)
3192 {
3193 /*
3194 * Check if the exploded VMX features from the saved state are compatible with the host-derived features
3195 * we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3196 * VMX features presented to the guest.
3197 */
3198 bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3199 if (!fIsCompat)
3200 return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3201 }
3202 return rc;
3203 }
3204 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3205}
3206
3207
3208/**
3209 * @callback_method_impl{FNSSMINTLOADDONE}
3210 */
3211static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3212{
3213 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3214 return VINF_SUCCESS;
3215
3216 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3217 if (pVM->cpum.s.fPendingRestore)
3218 {
3219 LogRel(("CPUM: Missing state!\n"));
3220 return VERR_INTERNAL_ERROR_2;
3221 }
3222
3223 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3224 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3225 {
3226 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3227
3228 /* Notify PGM of the NXE states in case they've changed. */
3229 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3230
3231 /* During init. this is done in CPUMR3InitCompleted(). */
3232 if (fSupportsLongMode)
3233 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
3234
3235 /* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3236 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3237 }
3238 return VINF_SUCCESS;
3239}
3240
3241
3242/**
3243 * Checks if the CPUM state restore is still pending.
3244 *
3245 * @returns true / false.
3246 * @param pVM The cross context VM structure.
3247 */
3248VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3249{
3250 return pVM->cpum.s.fPendingRestore;
3251}
3252
3253
3254/**
3255 * Gets the variable-range MTRR physical address mask given an address range.
3256 *
3257 * @returns The MTRR physical address mask.
3258 * @param pVM The cross context VM structure.
3259 * @param GCPhysFirst The first guest-physical address of the memory range
3260 * (inclusive).
3261 * @param GCPhysLast The last guest-physical address of the memory range
3262 * (inclusive).
3263 */
3264static uint64_t cpumR3GetVarMtrrMask(PVM pVM, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast)
3265{
3266 RTGCPHYS const GCPhysLength = GCPhysLast - GCPhysFirst;
3267 uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3268 RTGCPHYS const GCPhysMask = (~(GCPhysLength - 1) & ~fInvPhysMask) & X86_PAGE_BASE_MASK;
3269#ifdef VBOX_STRICT
3270 AssertMsg(GCPhysLast == ((GCPhysFirst | ~GCPhysMask) & ~fInvPhysMask),
3271 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3272 AssertMsg(((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask)),
3273 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3274 AssertMsg(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask),
3275 ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3276
3277 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
3278 AssertMsg(cbRange >= _4K, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3279 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3280 AssertMsg(RT_IS_POWER_OF_TWO(cbRange), ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3281 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3282 AssertMsg(GCPhysFirst == 0 || cbRange <= GCPhysFirst, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3283 GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3284#endif
3285 return GCPhysMask;
3286}
3287
3288
3289/**
3290 * Gets the first and last guest-physical address for the given variable-range
3291 * MTRR.
3292 *
3293 * @param pVM The cross context VM structure.
3294 * @param pMtrrVar The variable-range MTRR.
3295 * @param pGCPhysFirst Where to store the first guest-physical address of the
3296 * memory range (inclusive).
3297 * @param pGCPhysLast Where to store the last guest-physical address of the
3298 * memory range (inclusive).
3299 */
3300static void cpumR3GetVarMtrrAddrs(PVM pVM, PCX86MTRRVAR pMtrrVar, PRTGCPHYS pGCPhysFirst, PRTGCPHYS pGCPhysLast)
3301{
3302 Assert(pMtrrVar);
3303 Assert(pGCPhysFirst);
3304 Assert(pGCPhysLast);
3305 uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3306 RTGCPHYS const GCPhysMask = pMtrrVar->MtrrPhysMask & X86_PAGE_BASE_MASK;
3307 RTGCPHYS const GCPhysFirst = pMtrrVar->MtrrPhysBase & X86_PAGE_BASE_MASK;
3308 RTGCPHYS const GCPhysLast = (GCPhysFirst | ~GCPhysMask) & ~fInvPhysMask;
3309 Assert((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask));
3310 Assert(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask));
3311 *pGCPhysFirst = GCPhysFirst;
3312 *pGCPhysLast = GCPhysLast;
3313}
3314
3315
3316/**
3317 * Gets the previous power of two for a given value.
3318 *
3319 * @returns Previous power of two.
3320 * @param uVal The value (must not be zero).
3321 */
3322static uint64_t cpumR3GetPrevPowerOfTwo(uint64_t uVal)
3323{
3324 Assert(uVal > 1);
3325 uint8_t const cBits = sizeof(uVal) << 3;
3326 return RT_BIT_64(cBits - 1 - ASMCountLeadingZerosU64(uVal));
3327}
3328
3329
3330/**
3331 * Gets the next power of two for a given value.
3332 *
3333 * @returns Next power of two.
3334 * @param uVal The value (must not be zero).
3335 */
3336static uint64_t cpumR3GetNextPowerOfTwo(uint64_t uVal)
3337{
3338 Assert(uVal > 1);
3339 uint8_t const cBits = sizeof(uVal) << 3;
3340 return RT_BIT_64(cBits - ASMCountLeadingZerosU64(uVal));
3341}
3342
3343
3344/**
3345 * Gets the MTRR memory type description.
3346 *
3347 * @returns The MTRR memory type description.
3348 * @param fType The MTRR memory type.
3349 */
3350static const char *cpumR3GetVarMtrrMemType(uint8_t fType)
3351{
3352 switch (fType)
3353 {
3354 case X86_MTRR_MT_UC: return "UC";
3355 case X86_MTRR_MT_WC: return "WC";
3356 case X86_MTRR_MT_WT: return "WT";
3357 case X86_MTRR_MT_WP: return "WP";
3358 case X86_MTRR_MT_WB: return "WB";
3359 default: return "--";
3360 }
3361}
3362
3363
3364/**
3365 * Adds a memory region to the given MTRR map.
3366 *
3367 * @returns VBox status code.
3368 * @retval VINF_SUCCESS when the map could accommodate a memory region being
3369 * added.
3370 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3371 * memory region.
3372 *
3373 * @param pVM The cross context VM structure.
3374 * @param pMtrrMap The variable-range MTRR map to add to.
3375 * @param GCPhysFirst The first guest-physical address in the memory region.
3376 * @param GCPhysLast The last guest-physical address in the memory region.
3377 * @param fType The MTRR memory type of the memory region being added.
3378 */
3379static int cpumR3MtrrMapAddRegion(PVM pVM, PCPUMMTRRMAP pMtrrMap, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast, uint8_t fType)
3380{
3381 Assert(fType < 7 && fType != 2 && fType != 3);
3382 if (pMtrrMap->idxMtrr < pMtrrMap->cMtrrs)
3383 {
3384 /*
3385 * We must ensure the physical-address does not exceed the maximum guest-physical address width.
3386 * Otherwise, the MTRR physical mask computation gets totally busted rather than returning 0 to
3387 * indicate such mapping is impossible.
3388 */
3389 RTGCPHYS const GCPhysLastMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U;
3390 if (GCPhysLast <= GCPhysLastMax)
3391 {
3392 pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysBase = GCPhysFirst | fType;
3393 pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysMask = cpumR3GetVarMtrrMask(pVM, GCPhysFirst, GCPhysLast)
3394 | MSR_IA32_MTRR_PHYSMASK_VALID;
3395 ++pMtrrMap->idxMtrr;
3396
3397 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
3398 if (fType != X86_MTRR_MT_UC)
3399 pMtrrMap->cbMapped += cbRange;
3400 else
3401 {
3402 Assert(pMtrrMap->cbMapped >= cbRange);
3403 pMtrrMap->cbMapped -= cbRange;
3404 }
3405 return VINF_SUCCESS;
3406 }
3407 }
3408 return VERR_OUT_OF_RESOURCES;
3409}
3410
3411
3412/**
3413 * Adds an MTRR to the given MTRR map.
3414 *
3415 * @returns VBox status code.
3416 * @retval VINF_SUCCESS when the map could accommodate the MTRR being added.
3417 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3418 * MTRR.
3419 *
3420 * @param pVM The cross context VM structure.
3421 * @param pMtrrMap The variable-range MTRR map to add to.
3422 * @param pVarMtrr The variable-range MTRR to add from.
3423 */
3424static int cpumR3MtrrMapAddMtrr(PVM pVM, PCPUMMTRRMAP pMtrrMap, PCX86MTRRVAR pVarMtrr)
3425{
3426 RTGCPHYS GCPhysFirst;
3427 RTGCPHYS GCPhysLast;
3428 cpumR3GetVarMtrrAddrs(pVM, pVarMtrr, &GCPhysFirst, &GCPhysLast);
3429 uint8_t const fType = pVarMtrr->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
3430 return cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysFirst, GCPhysLast, fType);
3431}
3432
3433
3434/**
3435 * Adds a source MTRR map to the given destination MTRR map.
3436 *
3437 * @returns VBox status code.
3438 * @retval VINF_SUCCESS when the map could fully accommodate the map being added.
3439 * @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3440 * specified map.
3441 *
3442 * @param pVM The cross context VM structure.
3443 * @param pMtrrMapDst The variable-range MTRR map to add to (destination).
3444 * @param pMtrrMapSrc The variable-range MTRR map to add from (source).
3445 */
3446static int cpumR3MtrrMapAddMap(PVM pVM, PCPUMMTRRMAP pMtrrMapDst, PCCPUMMTRRMAP pMtrrMapSrc)
3447{
3448 Assert(pMtrrMapDst);
3449 Assert(pMtrrMapSrc);
3450 for (uint8_t i = 0 ; i < pMtrrMapSrc->idxMtrr; i++)
3451 {
3452 int const rc = cpumR3MtrrMapAddMtrr(pVM, pMtrrMapDst, &pMtrrMapSrc->aMtrrs[i]);
3453 if (RT_FAILURE(rc))
3454 return rc;
3455 }
3456 return VINF_SUCCESS;
3457}
3458
3459
3460/**
3461 * Maps memory using an additive method using variable-range MTRRs.
3462 *
3463 * The additive method fits as many valid MTRR WB (write-back) sub-regions to map
3464 * the specified memory size. For instance, 3584 MB is mapped as 2048 MB, 1024 MB
3465 * and 512 MB of WB memory, requiring 3 MTRRs.
3466 *
3467 * @returns VBox status code.
3468 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3469 * given number of MTRRs.
3470 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3471 * mapped within the given number of MTRRs.
3472 *
3473 * @param pVM The cross context VM structure.
3474 * @param GCPhysRegionFirst The guest-physical address in the region being
3475 * mapped.
3476 * @param cb The number of bytes being mapped.
3477 * @param pMtrrMap The variable-range MTRR map to populate.
3478 */
3479static int cpumR3MapMtrrsAdditive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3480{
3481 Assert(pMtrrMap);
3482 Assert(pMtrrMap->cMtrrs > 1);
3483 Assert(cb >= _4K);
3484 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3485
3486 uint64_t cbLeft = cb;
3487 uint64_t offRegion = GCPhysRegionFirst;
3488 while (cbLeft > 0)
3489 {
3490 uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cbLeft) ? cpumR3GetPrevPowerOfTwo(cbLeft) : cbLeft;
3491
3492 Log3(("CPUM: MTRR: Add[%u]: %' Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3493 int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
3494 if (RT_FAILURE(rc))
3495 return rc;
3496
3497 cbLeft -= RT_MIN(cbRegion, cbLeft);
3498 offRegion += cbRegion;
3499 }
3500 return VINF_SUCCESS;
3501}
3502
3503
3504/**
3505 * Maps memory using a subtractive method using variable-range MTRRs.
3506 *
3507 * The subtractive method rounds up the memory region using WB (write-back) memory
3508 * type and then "subtracts" sub-regions using UC (uncacheable) memory type. For
3509 * instance, 3584 MB is mapped as 4096 MB of WB minus 512 MB of UC, requiring 2
3510 * MTRRs.
3511 *
3512 * @returns VBox status code.
3513 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3514 * given number of MTRRs.
3515 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3516 * mapped within the given number of MTRRs.
3517 *
3518 * @param pVM The cross context VM structure.
3519 * @param GCPhysRegionFirst The guest-physical address in the region being
3520 * mapped.
3521 * @param cb The number of bytes being mapped.
3522 * @param pMtrrMap The variable-range MTRR map to populate.
3523 */
3524static int cpumR3MapMtrrsSubtractive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3525{
3526 Assert(pMtrrMap);
3527 Assert(pMtrrMap->cMtrrs > 1);
3528 Assert(cb >= _4K);
3529 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3530
3531 uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cb) ? cpumR3GetNextPowerOfTwo(cb) : cb;
3532 Assert(cbRegion >= cb);
3533
3534 Log3(("CPUM: MTRR: Sub[%u]: %' Rhcb (%RU64 bytes) [WB]\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3535 int rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysRegionFirst, GCPhysRegionFirst + cbRegion - 1, X86_MTRR_MT_WB);
3536 if (RT_FAILURE(rc))
3537 return rc;
3538
3539 uint64_t cbLeft = cbRegion - cb;
3540 RTGCPHYS offRegion = GCPhysRegionFirst + cbRegion;
3541 while (cbLeft > 0)
3542 {
3543 uint64_t const cbSubRegion = cpumR3GetPrevPowerOfTwo(cbLeft);
3544
3545 Log3(("CPUM: MTRR: Sub[%u]: %' Rhcb (%RU64 bytes) [UC]\n", pMtrrMap->idxMtrr, cbSubRegion, cbSubRegion));
3546 rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion - cbSubRegion, offRegion - 1, X86_MTRR_MT_UC);
3547 if (RT_FAILURE(rc))
3548 return rc;
3549
3550 cbLeft -= RT_MIN(cbSubRegion, cbLeft);
3551 offRegion -= cbSubRegion;
3552 }
3553 return rc;
3554}
3555
3556
3557/**
3558 * Optimally maps RAM when it's not necessarily aligned to a power of two using
3559 * variable-range MTRRs.
3560 *
3561 * @returns VBox status code.
3562 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3563 * given number of MTRRs.
3564 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3565 * mapped within the given number of MTRRs.
3566 *
3567 * @param pVM The cross context VM structure.
3568 * @param GCPhysRegionFirst The guest-physical address in the region being
3569 * mapped.
3570 * @param cb The number of bytes being mapped.
3571 * @param pMtrrMap The variable-range MTRR map to populate.
3572 */
3573static int cpumR3MapMtrrsOptimal(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3574{
3575 Assert(pMtrrMap);
3576 Assert(pMtrrMap->cMtrrs > 1);
3577 Assert(cb >= _4K);
3578 Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3579
3580 /*
3581 * Additive method.
3582 */
3583 CPUMMTRRMAP MtrrMapAdd;
3584 RT_ZERO(MtrrMapAdd);
3585 MtrrMapAdd.cMtrrs = pMtrrMap->cMtrrs;
3586 MtrrMapAdd.cbToMap = cb;
3587 int rcAdd;
3588 {
3589 rcAdd = cpumR3MapMtrrsAdditive(pVM, GCPhysRegionFirst, cb, &MtrrMapAdd);
3590 if (RT_SUCCESS(rcAdd))
3591 {
3592 Assert(MtrrMapAdd.idxMtrr > 0);
3593 Assert(MtrrMapAdd.idxMtrr <= MtrrMapAdd.cMtrrs);
3594 Assert(MtrrMapAdd.cbMapped == MtrrMapAdd.cbToMap);
3595 Log3(("CPUM: MTRR: Mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3596
3597 /*
3598 * If we were able to map memory using 2 or fewer MTRRs, don't bother with trying
3599 * to map using the subtractive method as that requires at least 2 MTRRs anyway.
3600 */
3601 if (MtrrMapAdd.idxMtrr <= 2)
3602 return cpumR3MtrrMapAddMap(pVM, pMtrrMap, &MtrrMapAdd);
3603 }
3604 else
3605 Log3(("CPUM: MTRR: Partially mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3606 }
3607
3608 /*
3609 * Subtractive method.
3610 */
3611 CPUMMTRRMAP MtrrMapSub;
3612 RT_ZERO(MtrrMapSub);
3613 MtrrMapSub.cMtrrs = pMtrrMap->cMtrrs;
3614 MtrrMapSub.cbToMap = cb;
3615 int rcSub;
3616 {
3617 rcSub = cpumR3MapMtrrsSubtractive(pVM, GCPhysRegionFirst, cb, &MtrrMapSub);
3618 if (RT_SUCCESS(rcSub))
3619 {
3620 Assert(MtrrMapSub.idxMtrr > 0);
3621 Assert(MtrrMapSub.idxMtrr <= MtrrMapSub.cMtrrs);
3622 Assert(MtrrMapSub.cbMapped == MtrrMapSub.cbToMap);
3623 Log3(("CPUM: MTRR: Mapped %u regions using subtractive method\n", MtrrMapSub.idxMtrr));
3624 }
3625 else
3626 Log3(("CPUM: MTRR: Partially mapped %u regions using subtractive method\n", MtrrMapAdd.idxMtrr));
3627 }
3628
3629 /*
3630 * Pick whichever method requires fewer MTRRs to map the memory.
3631 */
3632 PCCPUMMTRRMAP pMtrrMapOptimal;
3633 if ( RT_SUCCESS(rcAdd)
3634 && RT_SUCCESS(rcSub))
3635 {
3636 Assert(MtrrMapAdd.cbMapped == MtrrMapSub.cbMapped);
3637 if (MtrrMapSub.idxMtrr < MtrrMapAdd.idxMtrr)
3638 pMtrrMapOptimal = &MtrrMapSub;
3639 else
3640 pMtrrMapOptimal = &MtrrMapAdd;
3641 }
3642 else if (RT_SUCCESS(rcAdd))
3643 pMtrrMapOptimal = &MtrrMapAdd;
3644 else if (RT_SUCCESS(rcSub))
3645 pMtrrMapOptimal = &MtrrMapSub;
3646 else
3647 {
3648 /*
3649 * If both methods fail, use the additive method as it gives partially mapped
3650 * memory as opposed to memory that isn't present.
3651 */
3652 pMtrrMapOptimal = &MtrrMapAdd;
3653 }
3654
3655 int const rc = cpumR3MtrrMapAddMap(pVM, pMtrrMap, pMtrrMapOptimal);
3656 if ( RT_SUCCESS(rc)
3657 && pMtrrMapOptimal->cbMapped == pMtrrMapOptimal->cbToMap) /* Required to distinguish full vs overflow state. */
3658 return VINF_SUCCESS;
3659 return VERR_OUT_OF_RESOURCES;
3660}
3661
3662
3663/**
3664 * Maps RAM above 4GB using variable-range MTRRs.
3665 *
3666 * @returns VBox status code.
3667 * @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3668 * given number of MTRRs.
3669 * @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3670 * mapped within the given number of MTRRs.
3671 *
3672 * @param pVM The cross context VM structure.
3673 * @param cb The number of bytes above 4GB to map.
3674 * @param pMtrrMap The variable-range MTRR map to populate.
3675 */
3676static int cpumR3MapMtrrsAbove4GB(PVM pVM, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3677{
3678 Assert(pMtrrMap);
3679 Assert(pMtrrMap->cMtrrs > 1);
3680 Assert(cb >= _4K);
3681
3682 /*
3683 * Map regions at incremental powers of two offsets and sizes.
3684 * Note: We cannot map an 8GB region in a 4GB offset.
3685 */
3686 uint64_t cbLeft = cb;
3687 uint64_t offRegion = _4G;
3688 while (cbLeft > offRegion)
3689 {
3690 uint64_t const cbRegion = offRegion;
3691
3692 Log3(("CPUM: MTRR: [%u]: %' Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3693 int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
3694 if (RT_FAILURE(rc))
3695 return rc;
3696
3697 offRegion <<= 1;
3698 cbLeft -= RT_MIN(cbRegion, cbLeft);
3699 }
3700
3701 /*
3702 * Optimally try and map any remaining memory that is smaller than
3703 * the last power of two offset (size) above.
3704 */
3705 if (cbLeft > 0)
3706 {
3707 Assert(pMtrrMap->cMtrrs - pMtrrMap->idxMtrr > 0);
3708 return cpumR3MapMtrrsOptimal(pVM, offRegion, cbLeft, pMtrrMap);
3709 }
3710 return VINF_SUCCESS;
3711}
3712
3713
3714/**
3715 * Maps guest RAM via MTRRs.
3716 *
3717 * @returns VBox status code.
3718 * @param pVM The cross context VM structure.
3719 */
3720static int cpumR3MapMtrrs(PVM pVM)
3721{
3722 /*
3723 * The RAM size configured for the VM does NOT include the RAM hole!
3724 * We cannot make ANY assumptions about the RAM size or the RAM hole size
3725 * of the VM since it is configurable by the user. Hence, we must check for
3726 * atypical sizes.
3727 */
3728 uint64_t cbRam;
3729 int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
3730 if (RT_FAILURE(rc))
3731 {
3732 LogRel(("CPUM: Cannot map RAM via MTRRs since the RAM size is not configured for the VM\n"));
3733 return VINF_SUCCESS;
3734 }
3735 if (!(cbRam & ~X86_PAGE_4K_BASE_MASK))
3736 { /* likely */ }
3737 else
3738 {
3739 LogRel(("CPUM: WARNING! RAM size %u bytes is not 4K aligned, using %u bytes\n", cbRam, cbRam & X86_PAGE_4K_BASE_MASK));
3740 cbRam &= X86_PAGE_4K_BASE_MASK;
3741 }
3742
3743 /*
3744 * Map the RAM below 1MB.
3745 */
3746 if (cbRam >= _1M)
3747 {
3748 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3749 {
3750 PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3751 pCtxMsrs->msr.MtrrFix64K_00000 = 0x0606060606060606;
3752 pCtxMsrs->msr.MtrrFix16K_80000 = 0x0606060606060606;
3753 pCtxMsrs->msr.MtrrFix16K_A0000 = 0;
3754 pCtxMsrs->msr.MtrrFix4K_C0000 = 0x0505050505050505;
3755 pCtxMsrs->msr.MtrrFix4K_C8000 = 0x0505050505050505;
3756 pCtxMsrs->msr.MtrrFix4K_D0000 = 0x0505050505050505;
3757 pCtxMsrs->msr.MtrrFix4K_D8000 = 0x0505050505050505;
3758 pCtxMsrs->msr.MtrrFix4K_E0000 = 0x0505050505050505;
3759 pCtxMsrs->msr.MtrrFix4K_E8000 = 0x0505050505050505;
3760 pCtxMsrs->msr.MtrrFix4K_F0000 = 0x0505050505050505;
3761 pCtxMsrs->msr.MtrrFix4K_F8000 = 0x0505050505050505;
3762 }
3763 LogRel(("CPUM: Mapped %' Rhcb (%RU64 bytes) of RAM using fixed-range MTRRs\n", _1M, _1M));
3764 }
3765 else
3766 {
3767 LogRel(("CPUM: WARNING! Cannot map RAM via MTRRs since the RAM size is below 1 MiB\n"));
3768 return VINF_SUCCESS;
3769 }
3770
3771 if (cbRam > _1M + _4K)
3772 { /* likely */ }
3773 else
3774 {
3775 LogRel(("CPUM: WARNING! Cannot map RAM above 1M via MTRRs since the RAM size above 1M is below 4K\n"));
3776 return VINF_SUCCESS;
3777 }
3778
3779 /*
3780 * Check if there is at least 1 MTRR available in addition to MTRRs reserved
3781 * for use by software for mapping guest memory, see @bugref{10498#c34}.
3782 *
3783 * Intel Pentium Pro Processor's BIOS Writers Guide and our EFI code reserves
3784 * 2 MTRRs for use by software and thus we reserve the same here.
3785 */
3786 uint8_t const cMtrrsMax = pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.MtrrCap & MSR_IA32_MTRR_CAP_VCNT_MASK;
3787 uint8_t const cMtrrsRsvd = 2;
3788 if (cMtrrsMax < cMtrrsRsvd + 1)
3789 {
3790 LogRel(("CPUM: WARNING! Variable-range MTRRs (%u) insufficient to map RAM since %u of them are reserved for software\n",
3791 cMtrrsMax, cMtrrsRsvd));
3792 return VINF_SUCCESS;
3793 }
3794
3795 CPUMMTRRMAP MtrrMap;
3796 RT_ZERO(MtrrMap);
3797 uint8_t const cMtrrsMappable = cMtrrsMax - cMtrrsRsvd;
3798 Assert(cMtrrsMappable > 0); /* Paranoia. */
3799 AssertLogRelMsgReturn(cMtrrsMappable <= RT_ELEMENTS(MtrrMap.aMtrrs),
3800 ("Mappable variable-range MTRRs (%u) exceed MTRRs available (%u)\n", cMtrrsMappable,
3801 RT_ELEMENTS(MtrrMap.aMtrrs)),
3802 VERR_CPUM_IPE_1);
3803 MtrrMap.cMtrrs = cMtrrsMappable;
3804 MtrrMap.cbToMap = cbRam;
3805
3806 /*
3807 * Get the RAM hole size configured for the VM.
3808 * Since MM has already validated it, we only debug assert the same constraints here.
3809 *
3810 * Although it is not required by the MTRR mapping code that the RAM hole size be a
3811 * power of 2, it is highly recommended to keep it this way in order to drastically
3812 * reduce the number of MTRRs used.
3813 */
3814 uint32_t const cbRamHole = MMR3PhysGet4GBRamHoleSize(pVM);
3815 AssertMsg(cbRamHole <= 4032U * _1M, ("RAM hole size (%RU32 bytes) is too large\n", cbRamHole));
3816 AssertMsg(cbRamHole > 16 * _1M, ("RAM hole size (%RU32 bytes) is too small\n", cbRamHole));
3817 AssertMsg(!(cbRamHole & (_4M - 1)), ("RAM hole size (%RU32 bytes) must be 4MB aligned\n", cbRamHole));
3818
3819 /*
3820 * Paranoia.
3821 * Ensure the maximum physical-address width can accommodate the specified RAM size.
3822 */
3823 RTGCPHYS const GCPhysEndMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth);
3824 RTGCPHYS const GCPhysEnd = cbRam + cbRamHole;
3825 if (GCPhysEnd <= GCPhysEndMax)
3826 { /* likely */ }
3827 else
3828 {
3829 LogRel(("CPUM: WARNING! Cannot fully map RAM of %' Rhcb (%RU64 bytes) as it exceeds maximum physical-address (%#RX64)\n",
3830 GCPhysEnd, GCPhysEnd, GCPhysEndMax - 1));
3831 }
3832
3833 /*
3834 * Map the RAM (and RAM hole) below 4GB.
3835 */
3836 uint64_t const cbBelow4GB = RT_MIN(cbRam, (uint64_t)_4G - cbRamHole);
3837 rc = cpumR3MapMtrrsOptimal(pVM, 0 /* GCPhysFirst */, cbBelow4GB, &MtrrMap);
3838 if (RT_SUCCESS(rc))
3839 {
3840 Assert(MtrrMap.idxMtrr > 0);
3841 Assert(MtrrMap.idxMtrr <= MtrrMap.cMtrrs);
3842 Assert(MtrrMap.cbMapped == cbBelow4GB);
3843
3844 /*
3845 * Map the RAM above 4GB.
3846 */
3847 uint64_t const cbAbove4GB = cbRam + cbRamHole > _4G ? cbRam + cbRamHole - _4G : 0;
3848 if (cbAbove4GB)
3849 {
3850 rc = cpumR3MapMtrrsAbove4GB(pVM, cbAbove4GB, &MtrrMap);
3851 if (RT_SUCCESS(rc))
3852 Assert(MtrrMap.cbMapped == MtrrMap.cbToMap);
3853 }
3854 LogRel(("CPUM: Mapped %' Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", MtrrMap.cbMapped, MtrrMap.cbMapped,
3855 MtrrMap.idxMtrr));
3856 }
3857
3858 /*
3859 * Check if we ran out of MTRRs while mapping the memory.
3860 */
3861 if (MtrrMap.cbMapped < cbRam)
3862 {
3863 Assert(rc == VERR_OUT_OF_RESOURCES);
3864 Assert(MtrrMap.idxMtrr == cMtrrsMappable);
3865 Assert(MtrrMap.idxMtrr == MtrrMap.cMtrrs);
3866 uint64_t const cbLost = cbRam - MtrrMap.cbMapped;
3867 LogRel(("CPUM: WARNING! Could not map %' Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", cbLost, cbLost,
3868 MtrrMap.cMtrrs));
3869 }
3870
3871 /*
3872 * Copy mapped MTRRs to all VCPUs.
3873 */
3874 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3875 {
3876 PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3877 Assert(sizeof(pCtxMsrs->msr.aMtrrVarMsrs) == sizeof(MtrrMap.aMtrrs));
3878 memcpy(&pCtxMsrs->msr.aMtrrVarMsrs[0], &MtrrMap.aMtrrs[0], sizeof(MtrrMap.aMtrrs));
3879 }
3880
3881 return VINF_SUCCESS;
3882}
3883
3884
3885/**
3886 * Formats the EFLAGS value into mnemonics.
3887 *
3888 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3889 * @param efl The EFLAGS value with both guest hardware and VBox
3890 * internal bits included.
3891 */
3892static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3893{
3894 /*
3895 * Format the flags.
3896 */
3897 static const struct
3898 {
3899 const char *pszSet; const char *pszClear; uint32_t fFlag;
3900 } s_aFlags[] =
3901 {
3902 { "vip",NULL, X86_EFL_VIP },
3903 { "vif",NULL, X86_EFL_VIF },
3904 { "ac", NULL, X86_EFL_AC },
3905 { "vm", NULL, X86_EFL_VM },
3906 { "rf", NULL, X86_EFL_RF },
3907 { "nt", NULL, X86_EFL_NT },
3908 { "ov", "nv", X86_EFL_OF },
3909 { "dn", "up", X86_EFL_DF },
3910 { "ei", "di", X86_EFL_IF },
3911 { "tf", NULL, X86_EFL_TF },
3912 { "nt", "pl", X86_EFL_SF },
3913 { "nz", "zr", X86_EFL_ZF },
3914 { "ac", "na", X86_EFL_AF },
3915 { "po", "pe", X86_EFL_PF },
3916 { "cy", "nc", X86_EFL_CF },
3917 { "inh-ss", NULL, CPUMCTX_INHIBIT_SHADOW_SS },
3918 { "inh-sti", NULL, CPUMCTX_INHIBIT_SHADOW_STI },
3919 { "inh-nmi", NULL, CPUMCTX_INHIBIT_NMI },
3920 };
3921 char *psz = pszEFlags;
3922 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3923 {
3924 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3925 if (pszAdd)
3926 {
3927 strcpy(psz, pszAdd);
3928 psz += strlen(pszAdd);
3929 *psz++ = ' ';
3930 }
3931 }
3932 psz[-1] = '\0';
3933}
3934
3935
3936/**
3937 * Formats a full register dump.
3938 *
3939 * @param pVM The cross context VM structure.
3940 * @param pVCpu The cross context virtual CPU structure.
3941 * @param pHlp Output functions.
3942 * @param enmType The dump type.
3943 * @param pszPrefix Register name prefix.
3944 */
3945static void cpumR3InfoOne(PVM pVM, PCVMCPU pVCpu, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
3946{
3947 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3948
3949 /*
3950 * Format the EFLAGS.
3951 */
3952 char szEFlags[80];
3953 cpumR3InfoFormatFlags(&szEFlags[0], pCtx->eflags.uBoth);
3954
3955 /*
3956 * Format the registers.
3957 */
3958 uint32_t const efl = pCtx->eflags.u;
3959 switch (enmType)
3960 {
3961 case CPUMDUMPTYPE_TERSE:
3962 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3963 pHlp->pfnPrintf(pHlp,
3964 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3965 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3966 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3967 "%sr14=%016RX64 %sr15=%016RX64\n"
3968 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3969 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3970 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3971 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3972 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3973 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3974 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3975 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3976 else
3977 pHlp->pfnPrintf(pHlp,
3978 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3979 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3980 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3981 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3982 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3983 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3984 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3985 break;
3986
3987 case CPUMDUMPTYPE_DEFAULT:
3988 if (CPUMIsGuestIn64BitCodeEx(pCtx))
3989 pHlp->pfnPrintf(pHlp,
3990 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3991 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3992 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3993 "%sr14=%016RX64 %sr15=%016RX64\n"
3994 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3995 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3996 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3997 ,
3998 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3999 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
4000 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
4001 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4002 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4003 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
4004 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4005 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
4006 else
4007 pHlp->pfnPrintf(pHlp,
4008 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
4009 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
4010 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
4011 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
4012 ,
4013 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
4014 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4015 pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4016 pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
4017 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4018 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
4019 break;
4020
4021 case CPUMDUMPTYPE_VERBOSE:
4022 if (CPUMIsGuestIn64BitCodeEx(pCtx))
4023 pHlp->pfnPrintf(pHlp,
4024 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
4025 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
4026 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
4027 "%sr14=%016RX64 %sr15=%016RX64\n"
4028 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
4029 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4030 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4031 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4032 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4033 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4034 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4035 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
4036 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
4037 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
4038 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
4039 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4040 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4041 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
4042 ,
4043 pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
4044 pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
4045 pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
4046 pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4047 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
4048 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
4049 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
4050 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
4051 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
4052 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
4053 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4054 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
4055 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
4056 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
4057 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
4058 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
4059 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4060 else
4061 pHlp->pfnPrintf(pHlp,
4062 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
4063 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
4064 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
4065 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
4066 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
4067 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
4068 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
4069 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
4070 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
4071 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4072 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4073 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
4074 ,
4075 pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
4076 pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4077 pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
4078 pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
4079 pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
4080 pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
4081 pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
4082 pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4083 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
4084 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
4085 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
4086 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4087
4088 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
4089 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
4090 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
4091 {
4092 PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
4093 pHlp->pfnPrintf(pHlp,
4094 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
4095 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
4096 ,
4097 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
4098 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
4099 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
4100 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
4101 );
4102 /*
4103 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
4104 * not (FP)R0-7 as Intel SDM suggests.
4105 */
4106 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
4107 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
4108 {
4109 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
4110 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
4111 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
4112 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
4113 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
4114 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
4115 iExponent -= 16383; /* subtract bias */
4116 /** @todo This isn't entirenly correct and needs more work! */
4117 pHlp->pfnPrintf(pHlp,
4118 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
4119 pszPrefix, iST, pszPrefix, iFPR,
4120 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
4121 uTag, chSign, iInteger, u64Fraction, iExponent);
4122 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
4123 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
4124 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
4125 else
4126 pHlp->pfnPrintf(pHlp, "\n");
4127 }
4128
4129 /* XMM/YMM/ZMM registers. */
4130 if (pCtx->fXStateMask & XSAVE_C_YMM)
4131 {
4132 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
4133 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
4134 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4135 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4136 pszPrefix, i, i < 10 ? " " : "",
4137 pYmmHiCtx->aYmmHi[i].au32[3],
4138 pYmmHiCtx->aYmmHi[i].au32[2],
4139 pYmmHiCtx->aYmmHi[i].au32[1],
4140 pYmmHiCtx->aYmmHi[i].au32[0],
4141 pFpuCtx->aXMM[i].au32[3],
4142 pFpuCtx->aXMM[i].au32[2],
4143 pFpuCtx->aXMM[i].au32[1],
4144 pFpuCtx->aXMM[i].au32[0]);
4145 else
4146 {
4147 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
4148 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4149 pHlp->pfnPrintf(pHlp,
4150 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4151 pszPrefix, i, i < 10 ? " " : "",
4152 pZmmHi256->aHi256Regs[i].au32[7],
4153 pZmmHi256->aHi256Regs[i].au32[6],
4154 pZmmHi256->aHi256Regs[i].au32[5],
4155 pZmmHi256->aHi256Regs[i].au32[4],
4156 pZmmHi256->aHi256Regs[i].au32[3],
4157 pZmmHi256->aHi256Regs[i].au32[2],
4158 pZmmHi256->aHi256Regs[i].au32[1],
4159 pZmmHi256->aHi256Regs[i].au32[0],
4160 pYmmHiCtx->aYmmHi[i].au32[3],
4161 pYmmHiCtx->aYmmHi[i].au32[2],
4162 pYmmHiCtx->aYmmHi[i].au32[1],
4163 pYmmHiCtx->aYmmHi[i].au32[0],
4164 pFpuCtx->aXMM[i].au32[3],
4165 pFpuCtx->aXMM[i].au32[2],
4166 pFpuCtx->aXMM[i].au32[1],
4167 pFpuCtx->aXMM[i].au32[0]);
4168
4169 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
4170 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
4171 pHlp->pfnPrintf(pHlp,
4172 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4173 pszPrefix, i + 16,
4174 pZmm16Hi->aRegs[i].au32[15],
4175 pZmm16Hi->aRegs[i].au32[14],
4176 pZmm16Hi->aRegs[i].au32[13],
4177 pZmm16Hi->aRegs[i].au32[12],
4178 pZmm16Hi->aRegs[i].au32[11],
4179 pZmm16Hi->aRegs[i].au32[10],
4180 pZmm16Hi->aRegs[i].au32[9],
4181 pZmm16Hi->aRegs[i].au32[8],
4182 pZmm16Hi->aRegs[i].au32[7],
4183 pZmm16Hi->aRegs[i].au32[6],
4184 pZmm16Hi->aRegs[i].au32[5],
4185 pZmm16Hi->aRegs[i].au32[4],
4186 pZmm16Hi->aRegs[i].au32[3],
4187 pZmm16Hi->aRegs[i].au32[2],
4188 pZmm16Hi->aRegs[i].au32[1],
4189 pZmm16Hi->aRegs[i].au32[0]);
4190 }
4191 }
4192 else
4193 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4194 pHlp->pfnPrintf(pHlp,
4195 i & 1
4196 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
4197 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
4198 pszPrefix, i, i < 10 ? " " : "",
4199 pFpuCtx->aXMM[i].au32[3],
4200 pFpuCtx->aXMM[i].au32[2],
4201 pFpuCtx->aXMM[i].au32[1],
4202 pFpuCtx->aXMM[i].au32[0]);
4203
4204 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
4205 {
4206 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
4207 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
4208 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
4209 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
4210 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
4211 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
4212 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
4213 }
4214
4215 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
4216 {
4217 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
4218 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
4219 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
4220 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
4221 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
4222 }
4223
4224 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
4225 {
4226 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
4227 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
4228 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
4229 }
4230
4231 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
4232 if (pFpuCtx->au32RsrvdRest[i])
4233 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
4234 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
4235 }
4236
4237 pHlp->pfnPrintf(pHlp,
4238 "%sEFER =%016RX64\n"
4239 "%sPAT =%016RX64\n"
4240 "%sSTAR =%016RX64\n"
4241 "%sCSTAR =%016RX64\n"
4242 "%sLSTAR =%016RX64\n"
4243 "%sSFMASK =%016RX64\n"
4244 "%sKERNELGSBASE =%016RX64\n",
4245 pszPrefix, pCtx->msrEFER,
4246 pszPrefix, pCtx->msrPAT,
4247 pszPrefix, pCtx->msrSTAR,
4248 pszPrefix, pCtx->msrCSTAR,
4249 pszPrefix, pCtx->msrLSTAR,
4250 pszPrefix, pCtx->msrSFMASK,
4251 pszPrefix, pCtx->msrKERNELGSBASE);
4252
4253 if (CPUMIsGuestInPAEModeEx(pCtx))
4254 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
4255 pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
4256
4257 /*
4258 * MTRRs.
4259 */
4260 if (pVM->cpum.s.GuestFeatures.fMtrr)
4261 {
4262 pHlp->pfnPrintf(pHlp,
4263 "%sMTRR_CAP =%016RX64\n"
4264 "%sMTRR_DEF_TYPE =%016RX64\n"
4265 "%sMTRR_FIX64K_00000 =%016RX64\n"
4266 "%sMTRR_FIX16K_80000 =%016RX64\n"
4267 "%sMTRR_FIX16K_A0000 =%016RX64\n"
4268 "%sMTRR_FIX4K_C0000 =%016RX64\n"
4269 "%sMTRR_FIX4K_C8000 =%016RX64\n"
4270 "%sMTRR_FIX4K_D0000 =%016RX64\n"
4271 "%sMTRR_FIX4K_D8000 =%016RX64\n"
4272 "%sMTRR_FIX4K_E0000 =%016RX64\n"
4273 "%sMTRR_FIX4K_E8000 =%016RX64\n"
4274 "%sMTRR_FIX4K_F0000 =%016RX64\n"
4275 "%sMTRR_FIX4K_F8000 =%016RX64\n",
4276 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrCap,
4277 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType,
4278 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000,
4279 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000,
4280 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000,
4281 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000,
4282 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000,
4283 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000,
4284 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000,
4285 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000,
4286 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000,
4287 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000,
4288 pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000);
4289
4290 for (uint8_t iRange = 0; iRange < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs); iRange++)
4291 {
4292 PCX86MTRRVAR pMtrrVar = &pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[iRange];
4293 bool const fIsValid = RT_BOOL(pMtrrVar->MtrrPhysMask & MSR_IA32_MTRR_PHYSMASK_VALID);
4294 if (fIsValid)
4295 {
4296 RTGCPHYS GCPhysFirst;
4297 RTGCPHYS GCPhysLast;
4298 cpumR3GetVarMtrrAddrs(pVM, pMtrrVar, &GCPhysFirst, &GCPhysLast);
4299 uint8_t const fType = pMtrrVar->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
4300 const char *pszType = cpumR3GetVarMtrrMemType(fType);
4301 uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
4302 pHlp->pfnPrintf(pHlp,
4303 "%sMTRR_PHYSBASE[%2u] =%016RX64 First=%016RX64 %6RU64 MB [%s]\n"
4304 "%sMTRR_PHYSMASK[%2u] =%016RX64 Last =%016RX64 %6RU64 MB [%RU64 MB]\n",
4305 pszPrefix, iRange, pMtrrVar->MtrrPhysBase, GCPhysFirst, GCPhysFirst / _1M, pszType,
4306 pszPrefix, iRange, pMtrrVar->MtrrPhysMask, GCPhysLast, GCPhysLast / _1M, cbRange / (uint64_t)_1M);
4307 }
4308 else
4309 pHlp->pfnPrintf(pHlp,
4310 "%sMTRR_PHYSBASE[%2u] =%016RX64\n"
4311 "%sMTRR_PHYSMASK[%2u] =%016RX64\n",
4312 pszPrefix, iRange, pMtrrVar->MtrrPhysBase,
4313 pszPrefix, iRange, pMtrrVar->MtrrPhysMask);
4314 }
4315 }
4316 break;
4317 }
4318}
4319
4320
4321/**
4322 * Display all cpu states and any other cpum info.
4323 *
4324 * @param pVM The cross context VM structure.
4325 * @param pHlp The info helper functions.
4326 * @param pszArgs Arguments, ignored.
4327 */
4328static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4329{
4330 cpumR3InfoGuest(pVM, pHlp, pszArgs);
4331 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
4332 cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
4333 cpumR3InfoHyper(pVM, pHlp, pszArgs);
4334 cpumR3InfoHost(pVM, pHlp, pszArgs);
4335}
4336
4337
4338/**
4339 * Parses the info argument.
4340 *
4341 * The argument starts with 'verbose', 'terse' or 'default' and then
4342 * continues with the comment string.
4343 *
4344 * @param pszArgs The pointer to the argument string.
4345 * @param penmType Where to store the dump type request.
4346 * @param ppszComment Where to store the pointer to the comment string.
4347 */
4348static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
4349{
4350 if (!pszArgs)
4351 {
4352 *penmType = CPUMDUMPTYPE_DEFAULT;
4353 *ppszComment = "";
4354 }
4355 else
4356 {
4357 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
4358 {
4359 pszArgs += 7;
4360 *penmType = CPUMDUMPTYPE_VERBOSE;
4361 }
4362 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
4363 {
4364 pszArgs += 5;
4365 *penmType = CPUMDUMPTYPE_TERSE;
4366 }
4367 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
4368 {
4369 pszArgs += 7;
4370 *penmType = CPUMDUMPTYPE_DEFAULT;
4371 }
4372 else
4373 *penmType = CPUMDUMPTYPE_DEFAULT;
4374 *ppszComment = RTStrStripL(pszArgs);
4375 }
4376}
4377
4378
4379/**
4380 * Display the guest cpu state.
4381 *
4382 * @param pVM The cross context VM structure.
4383 * @param pHlp The info helper functions.
4384 * @param pszArgs Arguments.
4385 */
4386static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4387{
4388 CPUMDUMPTYPE enmType;
4389 const char *pszComment;
4390 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4391
4392 PCVMCPU pVCpu = VMMGetCpu(pVM);
4393 if (!pVCpu)
4394 pVCpu = pVM->apCpusR3[0];
4395
4396 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
4397
4398 cpumR3InfoOne(pVM, pVCpu, pHlp, enmType, "");
4399}
4400
4401
4402/**
4403 * Displays an SVM VMCB control area.
4404 *
4405 * @param pHlp The info helper functions.
4406 * @param pVmcbCtrl Pointer to a SVM VMCB controls area.
4407 * @param pszPrefix Caller specified string prefix.
4408 */
4409static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
4410{
4411 AssertReturnVoid(pHlp);
4412 AssertReturnVoid(pVmcbCtrl);
4413
4414 pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
4415 pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
4416 pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
4417 pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
4418 pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
4419 pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
4420 pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
4421 pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
4422 pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
4423 pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
4424 pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
4425 pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
4426 pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
4427 pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
4428 pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
4429 pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
4430 pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
4431 pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
4432 pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
4433 pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
4434 pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
4435 pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
4436 pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
4437 pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
4438 pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
4439 pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
4440 pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
4441 pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
4442 pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
4443 pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
4444 pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
4445 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
4446 pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
4447 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
4448 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
4449 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
4450 pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
4451 pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
4452 pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
4453 pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
4454 pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
4455 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
4456 pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
4457 pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
4458 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
4459 pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
4460 pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
4461 pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
4462 pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
4463 pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
4464 pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
4465 pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
4466 pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
4467 pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
4468 pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
4469 pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
4470 pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
4471 pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
4472 pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
4473 pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
4474}
4475
4476
4477/**
4478 * Helper for dumping the SVM VMCB selector registers.
4479 *
4480 * @param pHlp The info helper functions.
4481 * @param pSel Pointer to the SVM selector register.
4482 * @param pszName Name of the selector.
4483 * @param pszPrefix Caller specified string prefix.
4484 */
4485DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char *pszName, const char *pszPrefix)
4486{
4487 /* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
4488 pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
4489 pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
4490}
4491
4492
4493/**
4494 * Helper for dumping the SVM VMCB GDTR/IDTR registers.
4495 *
4496 * @param pHlp The info helper functions.
4497 * @param pXdtr Pointer to the descriptor table register.
4498 * @param pszName Name of the descriptor table register.
4499 * @param pszPrefix Caller specified string prefix.
4500 */
4501DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char *pszName, const char *pszPrefix)
4502{
4503 /* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
4504 pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
4505}
4506
4507
4508/**
4509 * Displays an SVM VMCB state-save area.
4510 *
4511 * @param pHlp The info helper functions.
4512 * @param pVmcbStateSave Pointer to a SVM VMCB controls area.
4513 * @param pszPrefix Caller specified string prefix.
4514 */
4515static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
4516{
4517 AssertReturnVoid(pHlp);
4518 AssertReturnVoid(pVmcbStateSave);
4519
4520 char szEFlags[80];
4521 cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
4522
4523 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
4524 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
4525 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
4526 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
4527 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
4528 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
4529 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
4530 cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
4531 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
4532 cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
4533 pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
4534 pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
4535 pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
4536 pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
4537 pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
4538 pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
4539 pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
4540 pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
4541 pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
4542 pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
4543 pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
4544 pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
4545 pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
4546 pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
4547 pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
4548 pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
4549 pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
4550 pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
4551 pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
4552 pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
4553 pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
4554 pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
4555 pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
4556 pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
4557 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
4558 pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
4559}
4560
4561
4562/**
4563 * Displays a virtual-VMCS.
4564 *
4565 * @param pVCpu The cross context virtual CPU structure.
4566 * @param pHlp The info helper functions.
4567 * @param pVmcs Pointer to a virtual VMCS.
4568 * @param pszPrefix Caller specified string prefix.
4569 */
4570static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
4571{
4572 AssertReturnVoid(pHlp);
4573 AssertReturnVoid(pVmcs);
4574
4575 /* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
4576#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4577 do { \
4578 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
4579 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
4580 } while (0)
4581
4582#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4583 do { \
4584 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
4585 (a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
4586 } while (0)
4587
4588#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4589 do { \
4590 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
4591 (a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
4592 (a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
4593 } while (0)
4594
4595#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4596 do { \
4597 (a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
4598 (a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
4599 } while (0)
4600
4601 /* Header. */
4602 {
4603 pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
4604 pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
4605 pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
4606 pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
4607 }
4608
4609 /* Control fields. */
4610 {
4611 /* 16-bit. */
4612 pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
4613 pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
4614 pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
4615 pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
4616 pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
4617
4618 /* 32-bit. */
4619 pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
4620 pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
4621 pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
4622 pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
4623 pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
4624 pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
4625 pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
4626 pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
4627 pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
4628 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
4629 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
4630 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
4631 pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
4632 {
4633 uint32_t const fInfo = pVmcs->u32EntryIntInfo;
4634 uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
4635 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
4636 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
4637 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
4638 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4639 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4640 }
4641 pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
4642 pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
4643 pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
4644 pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
4645 pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
4646
4647 /* 64-bit. */
4648 pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
4649 pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
4650 pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
4651 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
4652 pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
4653 pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
4654 pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
4655 pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
4656 pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
4657 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
4658 pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
4659 pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
4660 pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
4661 pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
4662 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
4663 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
4664 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
4665 pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
4666 pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
4667 pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
4668 pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
4669 pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
4670 pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
4671 pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
4672 pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
4673 pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
4674 pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
4675 pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
4676 pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
4677 pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
4678 pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
4679
4680 /* Natural width. */
4681 pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
4682 pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
4683 pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
4684 pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
4685 pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
4686 pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
4687 pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
4688 pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
4689 }
4690
4691 /* Guest state. */
4692 {
4693 char szEFlags[80];
4694 cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
4695 pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
4696
4697 /* 16-bit. */
4698 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
4699 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
4700 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
4701 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
4702 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
4703 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
4704 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
4705 CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
4706 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4707 CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4708 pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
4709 pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
4710
4711 /* 32-bit. */
4712 pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
4713 pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
4714 pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
4715 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
4716 pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
4717
4718 /* 64-bit. */
4719 pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
4720 pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
4721 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
4722 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
4723 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
4724 pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
4725 pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
4726 pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
4727 pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
4728 pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
4729 pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
4730 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
4731
4732 /* Natural width. */
4733 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
4734 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
4735 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
4736 pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
4737 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
4738 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
4739 pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
4740 pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
4741 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
4742 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
4743 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
4744 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
4745 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
4746 }
4747
4748 /* Host state. */
4749 {
4750 pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
4751
4752 /* 16-bit. */
4753 pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
4754 pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
4755 pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
4756 pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
4757 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
4758 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
4759 CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
4760 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4761 CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4762
4763 /* 32-bit. */
4764 pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
4765
4766 /* 64-bit. */
4767 pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
4768 pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
4769 pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
4770 pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
4771
4772 /* Natural width. */
4773 pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
4774 pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
4775 pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
4776 pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
4777 pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
4778 pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
4779 pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
4780 pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
4781 pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
4782 pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
4783 }
4784
4785 /* Read-only fields. */
4786 {
4787 pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
4788
4789 /* 16-bit (none currently). */
4790
4791 /* 32-bit. */
4792 pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
4793 pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4794 pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4795 pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4796 {
4797 uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4798 uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4799 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4800 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4801 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4802 pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4803 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4804 }
4805 pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4806 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4807 {
4808 uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4809 uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4810 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4811 pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4812 pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4813 pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4814 }
4815 pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4816 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4817 pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4818
4819 /* 64-bit. */
4820 pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4821
4822 /* Natural width. */
4823 pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4824 pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4825 pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4826 pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4827 pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4828 }
4829
4830#ifdef DEBUG_ramshankar
4831 if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4832 {
4833 void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4834 Assert(pvPage);
4835 RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4836 int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4837 if (RT_SUCCESS(rc))
4838 {
4839 pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4840 pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4841 pHlp->pfnPrintf(pHlp, "\n");
4842 }
4843 RTMemTmpFree(pvPage);
4844 }
4845#else
4846 NOREF(pVCpu);
4847#endif
4848
4849#undef CPUMVMX_DUMP_HOST_XDTR
4850#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4851#undef CPUMVMX_DUMP_GUEST_SEGREG
4852#undef CPUMVMX_DUMP_GUEST_XDTR
4853}
4854
4855
4856/**
4857 * Display the guest's hardware-virtualization cpu state.
4858 *
4859 * @param pVM The cross context VM structure.
4860 * @param pHlp The info helper functions.
4861 * @param pszArgs Arguments, ignored.
4862 */
4863static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4864{
4865 RT_NOREF(pszArgs);
4866
4867 PVMCPU pVCpu = VMMGetCpu(pVM);
4868 if (!pVCpu)
4869 pVCpu = pVM->apCpusR3[0];
4870
4871 PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4872 bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4873 bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4874
4875 pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4876 pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4877 pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4878
4879 if (fSvm)
4880 {
4881 pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4882 pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4883
4884 char szEFlags[80];
4885 cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4886 pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4887 pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4888 pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4889 cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4890 pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4891 cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4892 pHlp->pfnPrintf(pHlp, " HostState:\n");
4893 pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4894 pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4895 pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4896 pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4897 pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4898 pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4899 pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4900 pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4901 PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4902 pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4903 pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4904 PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4905 pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4906 pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4907 PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4908 pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4909 pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4910 PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4911 pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4912 pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4913 pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4914 pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4915 pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4916 pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4917 pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4918 pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4919 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4920 }
4921 else if (fVmx)
4922 {
4923 pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4924 pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4925 pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4926 pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4927 pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4928 pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4929 pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4930 pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4931 pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4932 pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4933 pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4934 pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4935 pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4936 pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4937 pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4938 pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4939 pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4940 pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4941 cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4942 }
4943 else
4944 pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4945
4946#undef CPUMHWVIRTDUMP_NONE
4947#undef CPUMHWVIRTDUMP_COMMON
4948#undef CPUMHWVIRTDUMP_SVM
4949#undef CPUMHWVIRTDUMP_VMX
4950#undef CPUMHWVIRTDUMP_LAST
4951#undef CPUMHWVIRTDUMP_ALL
4952}
4953
4954/**
4955 * Display the current guest instruction
4956 *
4957 * @param pVM The cross context VM structure.
4958 * @param pHlp The info helper functions.
4959 * @param pszArgs Arguments, ignored.
4960 */
4961static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4962{
4963 NOREF(pszArgs);
4964
4965 PVMCPU pVCpu = VMMGetCpu(pVM);
4966 if (!pVCpu)
4967 pVCpu = pVM->apCpusR3[0];
4968
4969 char szInstruction[256];
4970 szInstruction[0] = '\0';
4971 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4972 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4973}
4974
4975
4976/**
4977 * Display the hypervisor cpu state.
4978 *
4979 * @param pVM The cross context VM structure.
4980 * @param pHlp The info helper functions.
4981 * @param pszArgs Arguments, ignored.
4982 */
4983static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4984{
4985 PVMCPU pVCpu = VMMGetCpu(pVM);
4986 if (!pVCpu)
4987 pVCpu = pVM->apCpusR3[0];
4988
4989 CPUMDUMPTYPE enmType;
4990 const char *pszComment;
4991 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4992 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4993
4994 pHlp->pfnPrintf(pHlp,
4995 ".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4996 ".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4997 pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4998 pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4999 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
5000}
5001
5002
5003/**
5004 * Display the host cpu state.
5005 *
5006 * @param pVM The cross context VM structure.
5007 * @param pHlp The info helper functions.
5008 * @param pszArgs Arguments, ignored.
5009 */
5010static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5011{
5012 CPUMDUMPTYPE enmType;
5013 const char *pszComment;
5014 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
5015 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
5016
5017 PVMCPU pVCpu = VMMGetCpu(pVM);
5018 if (!pVCpu)
5019 pVCpu = pVM->apCpusR3[0];
5020 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
5021
5022 /*
5023 * Format the EFLAGS.
5024 */
5025 uint64_t efl = pCtx->rflags;
5026 char szEFlags[80];
5027 cpumR3InfoFormatFlags(&szEFlags[0], efl);
5028
5029 /*
5030 * Format the registers.
5031 */
5032 pHlp->pfnPrintf(pHlp,
5033 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
5034 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
5035 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
5036 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
5037 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
5038 "r14=%016RX64 r15=%016RX64\n"
5039 "iopl=%d %31s\n"
5040 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
5041 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
5042 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
5043 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
5044 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
5045 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
5046 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
5047 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
5048 ,
5049 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
5050 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
5051 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
5052 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
5053 pCtx->r11, pCtx->r12, pCtx->r13,
5054 pCtx->r14, pCtx->r15,
5055 X86_EFL_GET_IOPL(efl), szEFlags,
5056 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
5057 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
5058 pCtx->cr4, pCtx->ldtr, pCtx->tr,
5059 pCtx->dr0, pCtx->dr1, pCtx->dr2,
5060 pCtx->dr3, pCtx->dr6, pCtx->dr7,
5061 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
5062 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
5063 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
5064}
5065
5066/**
5067 * Structure used when disassembling and instructions in DBGF.
5068 * This is used so the reader function can get the stuff it needs.
5069 */
5070typedef struct CPUMDISASSTATE
5071{
5072 /** Pointer to the CPU structure. */
5073 PDISSTATE pDis;
5074 /** Pointer to the VM. */
5075 PVM pVM;
5076 /** Pointer to the VMCPU. */
5077 PVMCPU pVCpu;
5078 /** Pointer to the first byte in the segment. */
5079 RTGCUINTPTR GCPtrSegBase;
5080 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
5081 RTGCUINTPTR GCPtrSegEnd;
5082 /** The size of the segment minus 1. */
5083 RTGCUINTPTR cbSegLimit;
5084 /** Pointer to the current page - R3 Ptr. */
5085 void const *pvPageR3;
5086 /** Pointer to the current page - GC Ptr. */
5087 RTGCPTR pvPageGC;
5088 /** The lock information that PGMPhysReleasePageMappingLock needs. */
5089 PGMPAGEMAPLOCK PageMapLock;
5090 /** Whether the PageMapLock is valid or not. */
5091 bool fLocked;
5092 /** 64 bits mode or not. */
5093 bool f64Bits;
5094} CPUMDISASSTATE, *PCPUMDISASSTATE;
5095
5096
5097/**
5098 * @callback_method_impl{FNDISREADBYTES}
5099 */
5100static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
5101{
5102 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
5103 for (;;)
5104 {
5105 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
5106
5107 /*
5108 * Need to update the page translation?
5109 */
5110 if ( !pState->pvPageR3
5111 || (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
5112 {
5113 /* translate the address */
5114 pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
5115
5116 /* Release mapping lock previously acquired. */
5117 if (pState->fLocked)
5118 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
5119 int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
5120 if (RT_SUCCESS(rc))
5121 pState->fLocked = true;
5122 else
5123 {
5124 pState->fLocked = false;
5125 pState->pvPageR3 = NULL;
5126 return rc;
5127 }
5128 }
5129
5130 /*
5131 * Check the segment limit.
5132 */
5133 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
5134 return VERR_OUT_OF_SELECTOR_BOUNDS;
5135
5136 /*
5137 * Calc how much we can read.
5138 */
5139 uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
5140 if (!pState->f64Bits)
5141 {
5142 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
5143 if (cb > cbSeg && cbSeg)
5144 cb = cbSeg;
5145 }
5146 if (cb > cbMaxRead)
5147 cb = cbMaxRead;
5148
5149 /*
5150 * Read and advance or exit.
5151 */
5152 memcpy(&pDis->Instr.ab[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
5153 offInstr += (uint8_t)cb;
5154 if (cb >= cbMinRead)
5155 {
5156 pDis->cbCachedInstr = offInstr;
5157 return VINF_SUCCESS;
5158 }
5159 cbMinRead -= (uint8_t)cb;
5160 cbMaxRead -= (uint8_t)cb;
5161 }
5162}
5163
5164
5165/**
5166 * Disassemble an instruction and return the information in the provided structure.
5167 *
5168 * @returns VBox status code.
5169 * @param pVM The cross context VM structure.
5170 * @param pVCpu The cross context virtual CPU structure.
5171 * @param pCtx Pointer to the guest CPU context.
5172 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
5173 * @param pDis Disassembly state.
5174 * @param pszPrefix String prefix for logging (debug only).
5175 *
5176 */
5177VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISSTATE pDis,
5178 const char *pszPrefix)
5179{
5180 CPUMDISASSTATE State;
5181 int rc;
5182
5183 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
5184 State.pDis = pDis;
5185 State.pvPageGC = 0;
5186 State.pvPageR3 = NULL;
5187 State.pVM = pVM;
5188 State.pVCpu = pVCpu;
5189 State.fLocked = false;
5190 State.f64Bits = false;
5191
5192 /*
5193 * Get selector information.
5194 */
5195 DISCPUMODE enmDisCpuMode;
5196 if ( (pCtx->cr0 & X86_CR0_PE)
5197 && pCtx->eflags.Bits.u1VM == 0)
5198 {
5199 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
5200 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
5201 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
5202 State.GCPtrSegBase = pCtx->cs.u64Base;
5203 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
5204 State.cbSegLimit = pCtx->cs.u32Limit;
5205 enmDisCpuMode = (State.f64Bits)
5206 ? DISCPUMODE_64BIT
5207 : pCtx->cs.Attr.n.u1DefBig
5208 ? DISCPUMODE_32BIT
5209 : DISCPUMODE_16BIT;
5210 }
5211 else
5212 {
5213 /* real or V86 mode */
5214 enmDisCpuMode = DISCPUMODE_16BIT;
5215 State.GCPtrSegBase = pCtx->cs.Sel * 16;
5216 State.GCPtrSegEnd = 0xFFFFFFFF;
5217 State.cbSegLimit = 0xFFFFFFFF;
5218 }
5219
5220 /*
5221 * Disassemble the instruction.
5222 */
5223 uint32_t cbInstr;
5224#ifndef LOG_ENABLED
5225 RT_NOREF_PV(pszPrefix);
5226 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pDis, &cbInstr);
5227 if (RT_SUCCESS(rc))
5228 {
5229#else
5230 char szOutput[160];
5231 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
5232 pDis, &cbInstr, szOutput, sizeof(szOutput));
5233 if (RT_SUCCESS(rc))
5234 {
5235 /* log it */
5236 if (pszPrefix)
5237 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
5238 else
5239 Log(("%s", szOutput));
5240#endif
5241 rc = VINF_SUCCESS;
5242 }
5243 else
5244 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
5245
5246 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
5247 if (State.fLocked)
5248 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
5249
5250 return rc;
5251}
5252
5253
5254
5255/**
5256 * API for controlling a few of the CPU features found in CR4.
5257 *
5258 * Currently only X86_CR4_TSD is accepted as input.
5259 *
5260 * @returns VBox status code.
5261 *
5262 * @param pVM The cross context VM structure.
5263 * @param fOr The CR4 OR mask.
5264 * @param fAnd The CR4 AND mask.
5265 */
5266VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
5267{
5268 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
5269 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
5270
5271 pVM->cpum.s.CR4.OrMask &= fAnd;
5272 pVM->cpum.s.CR4.OrMask |= fOr;
5273
5274 return VINF_SUCCESS;
5275}
5276
5277
5278/**
5279 * Called when the ring-3 init phase completes.
5280 *
5281 * @returns VBox status code.
5282 * @param pVM The cross context VM structure.
5283 * @param enmWhat Which init phase.
5284 */
5285VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
5286{
5287 switch (enmWhat)
5288 {
5289 case VMINITCOMPLETED_RING3:
5290 {
5291 /*
5292 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
5293 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
5294 */
5295 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
5296 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5297 {
5298 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5299
5300 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
5301 if (fSupportsLongMode)
5302 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
5303 }
5304
5305 /* Register statistic counters for MSRs. */
5306 cpumR3MsrRegStats(pVM);
5307
5308 /* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
5309 CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
5310 cpumR3CpuIdRing3InitDone(pVM);
5311
5312 /* Create VMX-preemption timer for nested guests if required. Must be
5313 done here as CPUM is initialized before TM. */
5314 if (pVM->cpum.s.GuestFeatures.fVmx)
5315 {
5316 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5317 {
5318 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5319 char szName[32];
5320 RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
5321 int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
5322 TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
5323 AssertLogRelRCReturn(rc, rc);
5324 }
5325 }
5326
5327 /*
5328 * Map guest RAM via MTRRs.
5329 */
5330 if (pVM->cpum.s.fMtrrRead)
5331 {
5332 int const rc = cpumR3MapMtrrs(pVM);
5333 if (RT_SUCCESS(rc))
5334 { /* likely */ }
5335 else
5336 return rc;
5337 }
5338 break;
5339 }
5340
5341 default:
5342 break;
5343 }
5344 return VINF_SUCCESS;
5345}
5346
5347
5348/**
5349 * Called when the ring-0 init phases completed.
5350 *
5351 * @param pVM The cross context VM structure.
5352 */
5353VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
5354{
5355 /*
5356 * Enable log buffering as we're going to log a lot of lines.
5357 */
5358 bool const fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
5359
5360 /*
5361 * Log the cpuid.
5362 */
5363 RTCPUSET OnlineSet;
5364 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
5365 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
5366 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
5367 RTCPUID cCores = RTMpGetCoreCount();
5368 if (cCores)
5369 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
5370 LogRel(("************************* CPUID dump ************************\n"));
5371 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
5372 LogRel(("\n"));
5373 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
5374 LogRel(("******************** End of CPUID dump **********************\n"));
5375
5376 /*
5377 * Log VT-x extended features.
5378 *
5379 * SVM features are currently all covered under CPUID so there is nothing
5380 * to do here for SVM.
5381 */
5382 if (pVM->cpum.s.HostFeatures.fVmx)
5383 {
5384 LogRel(("*********************** VT-x features ***********************\n"));
5385 DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
5386 LogRel(("\n"));
5387 LogRel(("******************* End of VT-x features ********************\n"));
5388 }
5389
5390 /*
5391 * Restore the log buffering state to what it was previously.
5392 */
5393 RTLogRelSetBuffering(fOldBuffered);
5394}
5395
5396
5397/**
5398 * Marks the guest debug state as active.
5399 *
5400 * @param pVCpu The cross context virtual CPU structure.
5401 *
5402 * @note This is used solely by NEM (hence the name) to set the correct flags here
5403 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
5404 * The specific NEM backends have to make sure to load the correct values.
5405 */
5406VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
5407{
5408 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
5409 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
5410}
5411
5412
5413/**
5414 * Marks the hyper debug state as active.
5415 *
5416 * @param pVCpu The cross context virtual CPU structure.
5417 *
5418 * @note This is used solely by NEM (hence the name) to set the correct flags here
5419 * without loading the host's DRx registers, which is not possible from ring-3 anyway.
5420 * The specific NEM backends have to make sure to load the correct values.
5421 */
5422VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
5423{
5424 /*
5425 * Make sure the hypervisor values are up to date.
5426 */
5427 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
5428
5429 ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
5430 ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
5431}
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