[23] | 1 | /* $Id: HMR0.cpp 101412 2023-10-11 07:01:45Z vboxsync $ */
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[1] | 2 | /** @file
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[38684] | 3 | * Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
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[1] | 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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[1] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[1] | 26 | */
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| 27 |
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[57358] | 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[43387] | 32 | #define LOG_GROUP LOG_GROUP_HM
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[72769] | 33 | #define VMCPU_INCL_CPUM_GST_CTX
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[43387] | 34 | #include <VBox/vmm/hm.h>
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[35346] | 35 | #include <VBox/vmm/pgm.h>
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[43387] | 36 | #include "HMInternal.h"
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[80274] | 37 | #include <VBox/vmm/vmcc.h>
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[76464] | 38 | #include <VBox/vmm/hm_svm.h>
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[76397] | 39 | #include <VBox/vmm/hmvmxinline.h>
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[1] | 40 | #include <VBox/err.h>
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| 41 | #include <VBox/log.h>
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| 42 | #include <iprt/assert.h>
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| 43 | #include <iprt/asm.h>
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[29250] | 44 | #include <iprt/asm-amd64-x86.h>
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[20132] | 45 | #include <iprt/cpuset.h>
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[36245] | 46 | #include <iprt/mem.h>
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[7471] | 47 | #include <iprt/memobj.h>
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[37319] | 48 | #include <iprt/once.h>
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[20132] | 49 | #include <iprt/param.h>
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[13514] | 50 | #include <iprt/power.h>
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[20132] | 51 | #include <iprt/string.h>
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| 52 | #include <iprt/thread.h>
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[37955] | 53 | #include <iprt/x86.h>
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[47472] | 54 | #include "HMVMXR0.h"
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| 55 | #include "HMSVMR0.h"
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[1] | 56 |
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[37319] | 57 |
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[57358] | 58 | /*********************************************************************************************************************************
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| 59 | * Internal Functions *
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| 60 | *********************************************************************************************************************************/
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[37320] | 61 | static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2);
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| 62 | static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2);
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| 63 | static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
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| 64 | static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
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[7471] | 65 |
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[37319] | 66 |
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[57358] | 67 | /*********************************************************************************************************************************
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| 68 | * Structures and Typedefs *
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| 69 | *********************************************************************************************************************************/
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[37320] | 70 | /**
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| 71 | * This is used to manage the status code of a RTMpOnAll in HM.
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| 72 | */
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| 73 | typedef struct HMR0FIRSTRC
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| 74 | {
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| 75 | /** The status code. */
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| 76 | int32_t volatile rc;
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| 77 | /** The ID of the CPU reporting the first failure. */
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| 78 | RTCPUID volatile idCpu;
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| 79 | } HMR0FIRSTRC;
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| 80 | /** Pointer to a first return code structure. */
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| 81 | typedef HMR0FIRSTRC *PHMR0FIRSTRC;
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| 82 |
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| 83 | /**
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[87535] | 84 | * Ring-0 method table for AMD-V and VT-x specific operations.
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[37320] | 85 | */
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[87535] | 86 | typedef struct HMR0VTABLE
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[7471] | 87 | {
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[80587] | 88 | DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
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| 89 | DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
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[92392] | 90 | DECLR0CALLBACKMEMBER(int, pfnAssertionCallback, (PVMCPUCC pVCpu));
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[80587] | 91 | DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
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[80274] | 92 | DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
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[80587] | 93 | DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
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| 94 | bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
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[80911] | 95 | DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
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[80587] | 96 | DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
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| 97 | DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
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| 98 | DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
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[87535] | 99 | } HMR0VTABLE;
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[9407] | 100 |
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[87535] | 101 |
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| 102 | /*********************************************************************************************************************************
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| 103 | * Global Variables *
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| 104 | *********************************************************************************************************************************/
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| 105 | /** The active ring-0 HM operations (copied from one of the table at init). */
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[87537] | 106 | static HMR0VTABLE g_HmR0Ops;
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| 107 | /** Indicates whether the host is suspending or not. We'll refuse a few
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| 108 | * actions when the host is being suspended to speed up the suspending and
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| 109 | * avoid trouble. */
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| 110 | static bool volatile g_fHmSuspended;
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| 111 | /** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
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| 112 | * enabled and disabled each time it's used to execute guest code. */
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| 113 | static bool g_fHmGlobalInit;
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[87539] | 114 | /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
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| 115 | uint32_t g_fHmHostKernelFeatures;
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[87535] | 116 | /** Maximum allowed ASID/VPID (inclusive).
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| 117 | * @todo r=bird: This is exclusive for VT-x according to source code comment.
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| 118 | * Couldn't immediately find any docs on AMD-V, but suspect it is
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| 119 | * exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */
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[87537] | 120 | uint32_t g_uHmMaxAsid;
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[87535] | 121 |
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| 122 |
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[87536] | 123 | /** Set if VT-x (VMX) is supported by the CPU. */
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[87537] | 124 | bool g_fHmVmxSupported = false;
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[87556] | 125 | /** VMX: Whether we're using the preemption timer or not. */
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[87537] | 126 | bool g_fHmVmxUsePreemptTimer;
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[87556] | 127 | /** VMX: The shift mask employed by the VMX-Preemption timer. */
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[87537] | 128 | uint8_t g_cHmVmxPreemptTimerShift;
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[87556] | 129 | /** VMX: Set if swapping EFER is supported. */
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| 130 | bool g_fHmVmxSupportsVmcsEfer = false;
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| 131 | /** VMX: Whether we're using SUPR0EnableVTx or not. */
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[87537] | 132 | static bool g_fHmVmxUsingSUPR0EnableVTx = false;
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[87556] | 133 | /** VMX: Set if we've called SUPR0EnableVTx(true) and should disable it during
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[87537] | 134 | * module termination. */
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| 135 | static bool g_fHmVmxCalledSUPR0EnableVTx = false;
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[87556] | 136 | /** VMX: Host CR4 value (set by ring-0 VMX init) */
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[87537] | 137 | uint64_t g_uHmVmxHostCr4;
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[87556] | 138 | /** VMX: Host EFER value (set by ring-0 VMX init) */
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[87537] | 139 | uint64_t g_uHmVmxHostMsrEfer;
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[87556] | 140 | /** VMX: Host SMM monitor control (used for logging/diagnostics) */
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[87537] | 141 | uint64_t g_uHmVmxHostSmmMonitorCtl;
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[87536] | 142 |
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[87537] | 143 |
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[87536] | 144 | /** Set if AMD-V is supported by the CPU. */
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[87537] | 145 | bool g_fHmSvmSupported = false;
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[87536] | 146 | /** SVM revision. */
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[87537] | 147 | uint32_t g_uHmSvmRev;
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[87536] | 148 | /** SVM feature bits from cpuid 0x8000000a */
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[87538] | 149 | uint32_t g_fHmSvmFeatures;
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[87536] | 150 |
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[87537] | 151 |
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[87536] | 152 | /** MSRs. */
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[87537] | 153 | SUPHWVIRTMSRS g_HmMsrs;
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[87536] | 154 |
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[87537] | 155 | /** Last recorded error code during HM ring-0 init. */
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| 156 | static int32_t g_rcHmInit = VINF_SUCCESS;
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[87536] | 157 |
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[87537] | 158 | /** Per CPU globals. */
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| 159 | static HMPHYSCPU g_aHmCpuInfo[RTCPUSET_MAX_CPUS];
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[87535] | 160 |
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[87537] | 161 | /** Whether we've already initialized all CPUs.
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| 162 | * @remarks We could check the EnableAllCpusOnce state, but this is
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| 163 | * simpler and hopefully easier to understand. */
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| 164 | static bool g_fHmEnabled = false;
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| 165 | /** Serialize initialization in HMR0EnableAllCpus. */
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| 166 | static RTONCE g_HmEnableAllCpusOnce = RTONCE_INITIALIZER;
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[59020] | 167 |
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[7471] | 168 |
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[87535] | 169 | /** HM ring-0 operations for VT-x. */
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| 170 | static HMR0VTABLE const g_HmR0OpsVmx =
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| 171 | {
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| 172 | /* .pfnEnterSession = */ VMXR0Enter,
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| 173 | /* .pfnThreadCtxCallback = */ VMXR0ThreadCtxCallback,
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[92392] | 174 | /* .pfnAssertionCallback = */ VMXR0AssertionCallback,
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[87535] | 175 | /* .pfnExportHostState = */ VMXR0ExportHostState,
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| 176 | /* .pfnRunGuestCode = */ VMXR0RunGuestCode,
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| 177 | /* .pfnEnableCpu = */ VMXR0EnableCpu,
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| 178 | /* .pfnDisableCpu = */ VMXR0DisableCpu,
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| 179 | /* .pfnInitVM = */ VMXR0InitVM,
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| 180 | /* .pfnTermVM = */ VMXR0TermVM,
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| 181 | /* .pfnSetupVM = */ VMXR0SetupVM,
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| 182 | };
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[7471] | 183 |
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[87535] | 184 | /** HM ring-0 operations for AMD-V. */
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| 185 | static HMR0VTABLE const g_HmR0OpsSvm =
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| 186 | {
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| 187 | /* .pfnEnterSession = */ SVMR0Enter,
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| 188 | /* .pfnThreadCtxCallback = */ SVMR0ThreadCtxCallback,
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[92392] | 189 | /* .pfnAssertionCallback = */ SVMR0AssertionCallback,
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[87535] | 190 | /* .pfnExportHostState = */ SVMR0ExportHostState,
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| 191 | /* .pfnRunGuestCode = */ SVMR0RunGuestCode,
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| 192 | /* .pfnEnableCpu = */ SVMR0EnableCpu,
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| 193 | /* .pfnDisableCpu = */ SVMR0DisableCpu,
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| 194 | /* .pfnInitVM = */ SVMR0InitVM,
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| 195 | /* .pfnTermVM = */ SVMR0TermVM,
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| 196 | /* .pfnSetupVM = */ SVMR0SetupVM,
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| 197 | };
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[87521] | 198 |
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[87535] | 199 |
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| 200 | /** @name Dummy callback handlers for when neither VT-x nor AMD-V is supported.
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| 201 | * @{ */
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| 202 |
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| 203 | static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
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| 204 | {
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| 205 | RT_NOREF(pVCpu);
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| 206 | return VINF_SUCCESS;
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| 207 | }
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| 208 |
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| 209 | static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
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| 210 | {
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| 211 | RT_NOREF(enmEvent, pVCpu, fGlobalInit);
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| 212 | }
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| 213 |
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| 214 | static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
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| 215 | bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
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| 216 | {
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| 217 | RT_NOREF(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
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| 218 | return VINF_SUCCESS;
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| 219 | }
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| 220 |
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| 221 | static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
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| 222 | {
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| 223 | RT_NOREF(pHostCpu, pvCpuPage, HCPhysCpuPage);
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| 224 | return VINF_SUCCESS;
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| 225 | }
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| 226 |
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| 227 | static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
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| 228 | {
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| 229 | RT_NOREF(pVM);
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| 230 | return VINF_SUCCESS;
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| 231 | }
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| 232 |
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| 233 | static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
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| 234 | {
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| 235 | RT_NOREF(pVM);
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| 236 | return VINF_SUCCESS;
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| 237 | }
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| 238 |
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| 239 | static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
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| 240 | {
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| 241 | RT_NOREF(pVM);
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| 242 | return VINF_SUCCESS;
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| 243 | }
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| 244 |
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[92392] | 245 | static DECLCALLBACK(int) hmR0DummyAssertionCallback(PVMCPUCC pVCpu)
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[87535] | 246 | {
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[92392] | 247 | RT_NOREF(pVCpu);
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[87535] | 248 | return VINF_SUCCESS;
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| 249 | }
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| 250 |
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| 251 | static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
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| 252 | {
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| 253 | RT_NOREF(pVCpu);
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| 254 | return VERR_NOT_SUPPORTED;
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| 255 | }
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| 256 |
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| 257 | static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
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| 258 | {
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| 259 | RT_NOREF(pVCpu);
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| 260 | return VINF_SUCCESS;
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| 261 | }
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| 262 |
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| 263 | /** Dummy ops. */
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| 264 | static HMR0VTABLE const g_HmR0OpsDummy =
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| 265 | {
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| 266 | /* .pfnEnterSession = */ hmR0DummyEnter,
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| 267 | /* .pfnThreadCtxCallback = */ hmR0DummyThreadCtxCallback,
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[92392] | 268 | /* .pfnAssertionCallback = */ hmR0DummyAssertionCallback,
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[87535] | 269 | /* .pfnExportHostState = */ hmR0DummyExportHostState,
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| 270 | /* .pfnRunGuestCode = */ hmR0DummyRunGuestCode,
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| 271 | /* .pfnEnableCpu = */ hmR0DummyEnableCpu,
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| 272 | /* .pfnDisableCpu = */ hmR0DummyDisableCpu,
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| 273 | /* .pfnInitVM = */ hmR0DummyInitVM,
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| 274 | /* .pfnTermVM = */ hmR0DummyTermVM,
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| 275 | /* .pfnSetupVM = */ hmR0DummySetupVM,
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| 276 | };
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| 277 |
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| 278 | /** @} */
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| 279 |
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| 280 |
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[1] | 281 | /**
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[36245] | 282 | * Initializes a first return code structure.
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| 283 | *
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| 284 | * @param pFirstRc The structure to init.
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| 285 | */
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[37320] | 286 | static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
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[36245] | 287 | {
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| 288 | pFirstRc->rc = VINF_SUCCESS;
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| 289 | pFirstRc->idCpu = NIL_RTCPUID;
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| 290 | }
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| 291 |
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| 292 |
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| 293 | /**
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[43414] | 294 | * Try set the status code (success ignored).
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[36245] | 295 | *
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| 296 | * @param pFirstRc The first return code structure.
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| 297 | * @param rc The status code.
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| 298 | */
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[48296] | 299 | static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
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[36245] | 300 | {
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| 301 | if ( RT_FAILURE(rc)
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| 302 | && ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
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| 303 | pFirstRc->idCpu = RTMpCpuId();
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| 304 | }
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| 305 |
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| 306 |
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| 307 | /**
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| 308 | * Get the status code of a first return code structure.
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| 309 | *
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| 310 | * @returns The status code; VINF_SUCCESS or error status, no informational or
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| 311 | * warning errors.
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| 312 | * @param pFirstRc The first return code structure.
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| 313 | */
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[37320] | 314 | static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
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[36245] | 315 | {
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| 316 | return pFirstRc->rc;
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| 317 | }
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| 318 |
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| 319 |
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[39070] | 320 | #ifdef VBOX_STRICT
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[62869] | 321 | # ifndef DEBUG_bird
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[36245] | 322 | /**
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| 323 | * Get the CPU ID on which the failure status code was reported.
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| 324 | *
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| 325 | * @returns The CPU ID, NIL_RTCPUID if no failure was reported.
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| 326 | * @param pFirstRc The first return code structure.
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| 327 | */
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[37320] | 328 | static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
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[36245] | 329 | {
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| 330 | return pFirstRc->idCpu;
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| 331 | }
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[62869] | 332 | # endif
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[39070] | 333 | #endif /* VBOX_STRICT */
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[36245] | 334 |
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| 335 |
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[101380] | 336 | /**
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| 337 | * Verify if VMX is really usable by entering and exiting VMX root mode.
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| 338 | *
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| 339 | * @returns VBox status code.
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| 340 | * @param uVmxBasicMsr The host's IA32_VMX_BASIC_MSR value.
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| 341 | */
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| 342 | static int hmR0InitIntelVerifyVmxUsability(uint64_t uVmxBasicMsr)
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| 343 | {
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| 344 | /* Allocate a temporary VMXON region. */
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| 345 | RTR0MEMOBJ hScatchMemObj;
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| 346 | int rc = RTR0MemObjAllocCont(&hScatchMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /* PhysHighest */, false /* fExecutable */);
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| 347 | if (RT_FAILURE(rc))
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| 348 | {
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| 349 | LogRelFunc(("RTR0MemObjAllocCont(,HOST_PAGE_SIZE,false) -> %Rrc\n", rc));
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| 350 | return rc;
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| 351 | }
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| 352 | void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
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| 353 | RTHCPHYS const HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
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| 354 | RT_BZERO(pvScatchPage, HOST_PAGE_SIZE);
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[37298] | 355 |
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[101380] | 356 | /* Set revision dword at the beginning of the VMXON structure. */
|
---|
| 357 | *(uint32_t *)pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
|
---|
| 358 |
|
---|
| 359 | /* Make sure we don't get rescheduled to another CPU during this probe. */
|
---|
| 360 | RTCCUINTREG const fEFlags = ASMIntDisableFlags();
|
---|
| 361 |
|
---|
| 362 | /* Enable CR4.VMXE if it isn't already set. */
|
---|
| 363 | RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
|
---|
| 364 |
|
---|
| 365 | /*
|
---|
| 366 | * The only way of checking if we're in VMX root mode is to try and enter it.
|
---|
| 367 | * There is no instruction or control bit that tells us if we're in VMX root mode.
|
---|
| 368 | * Therefore, try and enter and exit VMX root mode.
|
---|
| 369 | */
|
---|
| 370 | rc = VMXEnable(HCPhysScratchPage);
|
---|
| 371 | if (RT_SUCCESS(rc))
|
---|
| 372 | VMXDisable();
|
---|
| 373 | else
|
---|
| 374 | {
|
---|
| 375 | /*
|
---|
| 376 | * KVM leaves the CPU in VMX root mode. Not only is this not allowed,
|
---|
| 377 | * it will crash the host when we enter raw mode, because:
|
---|
| 378 | *
|
---|
| 379 | * (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
|
---|
| 380 | * this bit), and
|
---|
| 381 | * (b) turning off paging causes a #GP (unavoidable when switching
|
---|
| 382 | * from long to 32 bits mode or 32 bits to PAE).
|
---|
| 383 | *
|
---|
| 384 | * They should fix their code, but until they do we simply refuse to run.
|
---|
| 385 | */
|
---|
| 386 | rc = VERR_VMX_IN_VMX_ROOT_MODE;
|
---|
| 387 | }
|
---|
| 388 |
|
---|
| 389 | /* Restore CR4.VMXE if it wasn't set prior to us setting it above. */
|
---|
| 390 | if (!(uOldCr4 & X86_CR4_VMXE))
|
---|
| 391 | SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
|
---|
| 392 |
|
---|
| 393 | /* Restore interrupts. */
|
---|
| 394 | ASMSetFlags(fEFlags);
|
---|
| 395 |
|
---|
| 396 | RTR0MemObjFree(hScatchMemObj, false);
|
---|
| 397 |
|
---|
| 398 | return rc;
|
---|
| 399 | }
|
---|
| 400 |
|
---|
| 401 |
|
---|
[87535] | 402 | /**
|
---|
| 403 | * Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
|
---|
| 404 | * on a CPU.
|
---|
| 405 | *
|
---|
| 406 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
| 407 | * @param pvUser1 Pointer to the first RC structure.
|
---|
| 408 | * @param pvUser2 Ignored.
|
---|
| 409 | */
|
---|
| 410 | static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
[37298] | 411 | {
|
---|
[87535] | 412 | PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
|
---|
| 413 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
| 414 | Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
|
---|
| 415 | NOREF(idCpu); NOREF(pvUser2);
|
---|
[37298] | 416 |
|
---|
[87535] | 417 | int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
|
---|
| 418 | hmR0FirstRcSetStatus(pFirstRc, rc);
|
---|
[47760] | 419 | }
|
---|
| 420 |
|
---|
[37298] | 421 |
|
---|
[36245] | 422 | /**
|
---|
[37320] | 423 | * Intel specific initialization code.
|
---|
| 424 | *
|
---|
| 425 | * @returns VBox status code (will only fail if out of memory).
|
---|
| 426 | */
|
---|
[76227] | 427 | static int hmR0InitIntel(void)
|
---|
[37320] | 428 | {
|
---|
[76227] | 429 | /* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
|
---|
[87536] | 430 | g_HmMsrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
|
---|
[76227] | 431 |
|
---|
[1] | 432 | /*
|
---|
[76227] | 433 | * First try use native kernel API for controlling VT-x.
|
---|
| 434 | * (This is only supported by some Mac OS X kernels atm.)
|
---|
[36236] | 435 | */
|
---|
[87535] | 436 | int rc;
|
---|
[87537] | 437 | g_rcHmInit = rc = SUPR0EnableVTx(true /* fEnable */);
|
---|
| 438 | g_fHmVmxUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
|
---|
| 439 | if (g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[36236] | 440 | {
|
---|
[76227] | 441 | AssertLogRelMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
|
---|
| 442 | if (RT_SUCCESS(rc))
|
---|
| 443 | {
|
---|
[87532] | 444 | g_fHmVmxSupported = true;
|
---|
[76227] | 445 | rc = SUPR0EnableVTx(false /* fEnable */);
|
---|
| 446 | AssertLogRelRC(rc);
|
---|
[87535] | 447 | rc = VINF_SUCCESS;
|
---|
[76227] | 448 | }
|
---|
| 449 | }
|
---|
| 450 | else
|
---|
| 451 | {
|
---|
| 452 | HMR0FIRSTRC FirstRc;
|
---|
| 453 | hmR0FirstRcInit(&FirstRc);
|
---|
[87537] | 454 | g_rcHmInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
|
---|
[87535] | 455 | if (RT_SUCCESS(rc))
|
---|
[87537] | 456 | g_rcHmInit = rc = hmR0FirstRcGetStatus(&FirstRc);
|
---|
[76227] | 457 | }
|
---|
[56619] | 458 |
|
---|
[87535] | 459 | if (RT_SUCCESS(rc))
|
---|
[76227] | 460 | {
|
---|
[76232] | 461 | /* Read CR4 and EFER for logging/diagnostic purposes. */
|
---|
[87536] | 462 | g_uHmVmxHostCr4 = ASMGetCR4();
|
---|
| 463 | g_uHmVmxHostMsrEfer = ASMRdMsr(MSR_K6_EFER);
|
---|
[76227] | 464 |
|
---|
[91323] | 465 | /* Get VMX MSRs (and feature control MSR) for determining VMX features we can ultimately use. */
|
---|
[87536] | 466 | SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_VT_X, false /* fForce */);
|
---|
[76232] | 467 |
|
---|
[37319] | 468 | /*
|
---|
[76464] | 469 | * Nested KVM workaround: Intel SDM section 34.15.5 describes that
|
---|
| 470 | * MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
|
---|
| 471 | * table 35-2 says that this MSR is available if either VMX or SMX is supported.
|
---|
[37319] | 472 | */
|
---|
[87536] | 473 | uint64_t const uVmxBasicMsr = g_HmMsrs.u.vmx.u64Basic;
|
---|
[76464] | 474 | if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
|
---|
[87536] | 475 | g_uHmVmxHostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
|
---|
[76227] | 476 |
|
---|
[76232] | 477 | /* Initialize VPID - 16 bits ASID. */
|
---|
[87521] | 478 | g_uHmMaxAsid = 0x10000; /* exclusive */
|
---|
[76227] | 479 |
|
---|
[76232] | 480 | /*
|
---|
| 481 | * If the host OS has not enabled VT-x for us, try enter VMX root mode
|
---|
| 482 | * to really verify if VT-x is usable.
|
---|
| 483 | */
|
---|
[87537] | 484 | if (!g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[37320] | 485 | {
|
---|
[101408] | 486 | /*
|
---|
[101412] | 487 | * We don't verify VMX root mode on all CPUs here because the verify
|
---|
[101408] | 488 | * function exits VMX root mode thus potentially allowing other
|
---|
[101412] | 489 | * programs to grab VT-x. Our global init's entering and staying in
|
---|
| 490 | * VMX root mode (until our module termination) is done later when
|
---|
| 491 | * the first VM powers up (after module initialization) using
|
---|
| 492 | * VMMR0_DO_HM_ENABLE which calls HMR0EnableAllCpus().
|
---|
[101411] | 493 | *
|
---|
[101408] | 494 | * This is just a quick sanity check.
|
---|
| 495 | */
|
---|
[101380] | 496 | rc = hmR0InitIntelVerifyVmxUsability(uVmxBasicMsr);
|
---|
[76227] | 497 | if (RT_SUCCESS(rc))
|
---|
[87532] | 498 | g_fHmVmxSupported = true;
|
---|
[76227] | 499 | else
|
---|
| 500 | {
|
---|
[101380] | 501 | g_rcHmInit = rc;
|
---|
[87532] | 502 | Assert(g_fHmVmxSupported == false);
|
---|
[76227] | 503 | }
|
---|
| 504 | }
|
---|
[8554] | 505 |
|
---|
[87532] | 506 | if (g_fHmVmxSupported)
|
---|
[76227] | 507 | {
|
---|
| 508 | rc = VMXR0GlobalInit();
|
---|
[87535] | 509 | if (RT_SUCCESS(rc))
|
---|
| 510 | {
|
---|
| 511 | /*
|
---|
| 512 | * Install the VT-x methods.
|
---|
| 513 | */
|
---|
| 514 | g_HmR0Ops = g_HmR0OpsVmx;
|
---|
[10817] | 515 |
|
---|
[87535] | 516 | /*
|
---|
| 517 | * Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
|
---|
| 518 | * Timer Does Not Count Down at the Rate Specified" CPU erratum.
|
---|
| 519 | */
|
---|
[87542] | 520 | if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
|
---|
[87535] | 521 | {
|
---|
[87536] | 522 | g_fHmVmxUsePreemptTimer = true;
|
---|
[87542] | 523 | g_cHmVmxPreemptTimerShift = RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
|
---|
[87535] | 524 | if (HMIsSubjectToVmxPreemptTimerErratum())
|
---|
[87536] | 525 | g_cHmVmxPreemptTimerShift = 0; /* This is about right most of the time here. */
|
---|
[87535] | 526 | }
|
---|
[87556] | 527 | else
|
---|
| 528 | g_fHmVmxUsePreemptTimer = false;
|
---|
| 529 |
|
---|
| 530 | /*
|
---|
| 531 | * Check for EFER swapping support.
|
---|
| 532 | */
|
---|
| 533 | g_fHmVmxSupportsVmcsEfer = (g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
|
---|
| 534 | && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
|
---|
| 535 | && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR);
|
---|
[87535] | 536 | }
|
---|
| 537 | else
|
---|
[1] | 538 | {
|
---|
[87537] | 539 | g_rcHmInit = rc;
|
---|
[87535] | 540 | g_fHmVmxSupported = false;
|
---|
[37320] | 541 | }
|
---|
| 542 | }
|
---|
[76227] | 543 | }
|
---|
[37320] | 544 | #ifdef LOG_ENABLED
|
---|
[76227] | 545 | else
|
---|
[87537] | 546 | SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_rcHmInit);
|
---|
[37320] | 547 | #endif
|
---|
| 548 | return VINF_SUCCESS;
|
---|
| 549 | }
|
---|
[25931] | 550 |
|
---|
| 551 |
|
---|
[37320] | 552 | /**
|
---|
[87535] | 553 | * Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
|
---|
| 554 | * on a CPU.
|
---|
| 555 | *
|
---|
| 556 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
| 557 | * @param pvUser1 Pointer to the first RC structure.
|
---|
| 558 | * @param pvUser2 Ignored.
|
---|
| 559 | */
|
---|
| 560 | static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
| 561 | {
|
---|
| 562 | PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
|
---|
| 563 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
| 564 | Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
|
---|
| 565 | NOREF(idCpu); NOREF(pvUser2);
|
---|
| 566 |
|
---|
| 567 | int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
|
---|
| 568 | hmR0FirstRcSetStatus(pFirstRc, rc);
|
---|
| 569 | }
|
---|
| 570 |
|
---|
| 571 |
|
---|
| 572 | /**
|
---|
[41776] | 573 | * AMD-specific initialization code.
|
---|
[46297] | 574 | *
|
---|
[76227] | 575 | * @returns VBox status code (will only fail if out of memory).
|
---|
[37320] | 576 | */
|
---|
[76227] | 577 | static int hmR0InitAmd(void)
|
---|
[37320] | 578 | {
|
---|
[76227] | 579 | /* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
|
---|
| 580 | int rc = SVMR0GlobalInit();
|
---|
[87535] | 581 | if (RT_SUCCESS(rc))
|
---|
[76227] | 582 | {
|
---|
[87535] | 583 | /*
|
---|
| 584 | * Install the AMD-V methods.
|
---|
| 585 | */
|
---|
| 586 | g_HmR0Ops = g_HmR0OpsSvm;
|
---|
[76227] | 587 |
|
---|
[87535] | 588 | /* Query AMD features. */
|
---|
| 589 | uint32_t u32Dummy;
|
---|
[87538] | 590 | ASMCpuId(0x8000000a, &g_uHmSvmRev, &g_uHmMaxAsid, &u32Dummy, &g_fHmSvmFeatures);
|
---|
[46297] | 591 |
|
---|
[87535] | 592 | /*
|
---|
| 593 | * We need to check if AMD-V has been properly initialized on all CPUs.
|
---|
| 594 | * Some BIOSes might do a poor job.
|
---|
| 595 | */
|
---|
| 596 | HMR0FIRSTRC FirstRc;
|
---|
| 597 | hmR0FirstRcInit(&FirstRc);
|
---|
| 598 | rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
|
---|
| 599 | AssertRC(rc);
|
---|
| 600 | if (RT_SUCCESS(rc))
|
---|
| 601 | rc = hmR0FirstRcGetStatus(&FirstRc);
|
---|
[24507] | 602 | #ifndef DEBUG_bird
|
---|
[87535] | 603 | AssertMsg(rc == VINF_SUCCESS || rc == VERR_SVM_IN_USE,
|
---|
| 604 | ("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
|
---|
[24507] | 605 | #endif
|
---|
[87535] | 606 | if (RT_SUCCESS(rc))
|
---|
| 607 | {
|
---|
[87536] | 608 | SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_AMD_V, false /* fForce */);
|
---|
[87535] | 609 | g_fHmSvmSupported = true;
|
---|
| 610 | }
|
---|
| 611 | else
|
---|
| 612 | {
|
---|
[87537] | 613 | g_rcHmInit = rc;
|
---|
[87535] | 614 | if (rc == VERR_SVM_DISABLED || rc == VERR_SVM_IN_USE)
|
---|
| 615 | rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
|
---|
| 616 | }
|
---|
[1] | 617 | }
|
---|
[3292] | 618 | else
|
---|
[87537] | 619 | g_rcHmInit = rc;
|
---|
[46297] | 620 | return rc;
|
---|
[37320] | 621 | }
|
---|
[3292] | 622 |
|
---|
[37320] | 623 |
|
---|
| 624 | /**
|
---|
| 625 | * Does global Ring-0 HM initialization (at module init).
|
---|
| 626 | *
|
---|
| 627 | * @returns VBox status code.
|
---|
| 628 | */
|
---|
[44373] | 629 | VMMR0_INT_DECL(int) HMR0Init(void)
|
---|
[37320] | 630 | {
|
---|
[37319] | 631 | /*
|
---|
[37320] | 632 | * Initialize the globals.
|
---|
| 633 | */
|
---|
[87537] | 634 | g_fHmEnabled = false;
|
---|
| 635 | for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
|
---|
[50800] | 636 | {
|
---|
[87537] | 637 | g_aHmCpuInfo[i].idCpu = NIL_RTCPUID;
|
---|
| 638 | g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
|
---|
| 639 | g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
|
---|
| 640 | g_aHmCpuInfo[i].pvMemObj = NULL;
|
---|
[72208] | 641 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
[87537] | 642 | g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
|
---|
| 643 | g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
|
---|
| 644 | g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
|
---|
[71529] | 645 | #endif
|
---|
[50800] | 646 | }
|
---|
[37320] | 647 |
|
---|
| 648 | /* Fill in all callbacks with placeholders. */
|
---|
[87537] | 649 | g_HmR0Ops = g_HmR0OpsDummy;
|
---|
[37320] | 650 |
|
---|
[42157] | 651 | /* Default is global VT-x/AMD-V init. */
|
---|
[87537] | 652 | g_fHmGlobalInit = true;
|
---|
[37320] | 653 |
|
---|
[87532] | 654 | g_fHmVmxSupported = false;
|
---|
| 655 | g_fHmSvmSupported = false;
|
---|
| 656 | g_uHmMaxAsid = 0;
|
---|
| 657 |
|
---|
[37320] | 658 | /*
|
---|
[87539] | 659 | * Get host kernel features that HM might need to know in order
|
---|
| 660 | * to co-operate and function properly with the host OS (e.g. SMAP).
|
---|
| 661 | */
|
---|
| 662 | g_fHmHostKernelFeatures = SUPR0GetKernelFeatures();
|
---|
| 663 |
|
---|
| 664 | /*
|
---|
[37320] | 665 | * Make sure aCpuInfo is big enough for all the CPUs on this system.
|
---|
| 666 | */
|
---|
[87537] | 667 | if (RTMpGetArraySize() > RT_ELEMENTS(g_aHmCpuInfo))
|
---|
[37320] | 668 | {
|
---|
[87537] | 669 | LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aHmCpuInfo)));
|
---|
[37320] | 670 | return VERR_TOO_MANY_CPUS;
|
---|
| 671 | }
|
---|
| 672 |
|
---|
| 673 | /*
|
---|
[76227] | 674 | * Check for VT-x or AMD-V support.
|
---|
| 675 | * Return failure only in out-of-memory situations.
|
---|
[37320] | 676 | */
|
---|
[76227] | 677 | uint32_t fCaps = 0;
|
---|
| 678 | int rc = SUPR0GetVTSupport(&fCaps);
|
---|
| 679 | if (RT_SUCCESS(rc))
|
---|
[37320] | 680 | {
|
---|
[76227] | 681 | if (fCaps & SUPVTCAPS_VT_X)
|
---|
| 682 | rc = hmR0InitIntel();
|
---|
[37320] | 683 | else
|
---|
[76227] | 684 | {
|
---|
| 685 | Assert(fCaps & SUPVTCAPS_AMD_V);
|
---|
| 686 | rc = hmR0InitAmd();
|
---|
| 687 | }
|
---|
[87535] | 688 | if (RT_SUCCESS(rc))
|
---|
| 689 | {
|
---|
| 690 | /*
|
---|
| 691 | * Register notification callbacks that we can use to disable/enable CPUs
|
---|
| 692 | * when brought offline/online or suspending/resuming.
|
---|
| 693 | */
|
---|
[87537] | 694 | if (!g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[87535] | 695 | {
|
---|
| 696 | rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
|
---|
| 697 | if (RT_SUCCESS(rc))
|
---|
| 698 | {
|
---|
| 699 | rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
|
---|
| 700 | if (RT_FAILURE(rc))
|
---|
| 701 | RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
|
---|
| 702 | }
|
---|
| 703 | if (RT_FAILURE(rc))
|
---|
| 704 | {
|
---|
| 705 | /* There shouldn't be any per-cpu allocations at this point,
|
---|
| 706 | so just have to call SVMR0GlobalTerm and VMXR0GlobalTerm. */
|
---|
| 707 | if (fCaps & SUPVTCAPS_VT_X)
|
---|
| 708 | VMXR0GlobalTerm();
|
---|
| 709 | else
|
---|
| 710 | SVMR0GlobalTerm();
|
---|
| 711 | g_HmR0Ops = g_HmR0OpsDummy;
|
---|
[87537] | 712 | g_rcHmInit = rc;
|
---|
[87535] | 713 | g_fHmSvmSupported = false;
|
---|
| 714 | g_fHmVmxSupported = false;
|
---|
| 715 | }
|
---|
| 716 | }
|
---|
| 717 | }
|
---|
[37320] | 718 | }
|
---|
| 719 | else
|
---|
[15134] | 720 | {
|
---|
[87537] | 721 | g_rcHmInit = rc;
|
---|
[87535] | 722 | rc = VINF_SUCCESS; /* We return success here because module init shall not fail if HM fails to initialize. */
|
---|
[15134] | 723 | }
|
---|
[87535] | 724 | return rc;
|
---|
[7476] | 725 | }
|
---|
| 726 |
|
---|
| 727 |
|
---|
| 728 | /**
|
---|
[37320] | 729 | * Does global Ring-0 HM termination (at module termination).
|
---|
[32361] | 730 | *
|
---|
[87535] | 731 | * @returns VBox status code (ignored).
|
---|
[7471] | 732 | */
|
---|
[44373] | 733 | VMMR0_INT_DECL(int) HMR0Term(void)
|
---|
[7471] | 734 | {
|
---|
[13514] | 735 | int rc;
|
---|
[87532] | 736 | if ( g_fHmVmxSupported
|
---|
[87537] | 737 | && g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[14903] | 738 | {
|
---|
[37319] | 739 | /*
|
---|
| 740 | * Simple if the host OS manages VT-x.
|
---|
| 741 | */
|
---|
[87537] | 742 | Assert(g_fHmGlobalInit);
|
---|
[37319] | 743 |
|
---|
[87537] | 744 | if (g_fHmVmxCalledSUPR0EnableVTx)
|
---|
[56705] | 745 | {
|
---|
| 746 | rc = SUPR0EnableVTx(false /* fEnable */);
|
---|
[87537] | 747 | g_fHmVmxCalledSUPR0EnableVTx = false;
|
---|
[56705] | 748 | }
|
---|
[56706] | 749 | else
|
---|
| 750 | rc = VINF_SUCCESS;
|
---|
[56705] | 751 |
|
---|
[87537] | 752 | for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aHmCpuInfo); iCpu++)
|
---|
[14903] | 753 | {
|
---|
[87537] | 754 | g_aHmCpuInfo[iCpu].fConfigured = false;
|
---|
| 755 | Assert(g_aHmCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
|
---|
[14903] | 756 | }
|
---|
| 757 | }
|
---|
| 758 | else
|
---|
| 759 | {
|
---|
[87537] | 760 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[13514] | 761 |
|
---|
[56360] | 762 | /* Doesn't really matter if this fails. */
|
---|
[87535] | 763 | RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
|
---|
| 764 | RTPowerNotificationDeregister(hmR0PowerCallback, NULL);
|
---|
| 765 | rc = VINF_SUCCESS;
|
---|
[56360] | 766 |
|
---|
[37320] | 767 | /*
|
---|
| 768 | * Disable VT-x/AMD-V on all CPUs if we enabled it before.
|
---|
| 769 | */
|
---|
[87537] | 770 | if (g_fHmGlobalInit)
|
---|
[23476] | 771 | {
|
---|
[37320] | 772 | HMR0FIRSTRC FirstRc;
|
---|
| 773 | hmR0FirstRcInit(&FirstRc);
|
---|
[48208] | 774 | rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
|
---|
[23476] | 775 | Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
|
---|
[36245] | 776 | if (RT_SUCCESS(rc))
|
---|
[37320] | 777 | rc = hmR0FirstRcGetStatus(&FirstRc);
|
---|
[23476] | 778 | }
|
---|
| 779 |
|
---|
[37320] | 780 | /*
|
---|
| 781 | * Free the per-cpu pages used for VT-x and AMD-V.
|
---|
| 782 | */
|
---|
[87537] | 783 | for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
|
---|
[7471] | 784 | {
|
---|
[87537] | 785 | if (g_aHmCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
|
---|
[14903] | 786 | {
|
---|
[87537] | 787 | RTR0MemObjFree(g_aHmCpuInfo[i].hMemObj, false);
|
---|
| 788 | g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
|
---|
| 789 | g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
|
---|
| 790 | g_aHmCpuInfo[i].pvMemObj = NULL;
|
---|
[14903] | 791 | }
|
---|
[72208] | 792 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
[87537] | 793 | if (g_aHmCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
|
---|
[71529] | 794 | {
|
---|
[87537] | 795 | RTR0MemObjFree(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, false);
|
---|
| 796 | g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
|
---|
| 797 | g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
|
---|
| 798 | g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
|
---|
[71529] | 799 | }
|
---|
| 800 | #endif
|
---|
[7471] | 801 | }
|
---|
| 802 | }
|
---|
[45091] | 803 |
|
---|
[46297] | 804 | /** @todo This needs cleaning up. There's no matching
|
---|
| 805 | * hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
|
---|
| 806 | * should move into their respective modules. */
|
---|
[45091] | 807 | /* Finally, call global VT-x/AMD-V termination. */
|
---|
[87532] | 808 | if (g_fHmVmxSupported)
|
---|
[45091] | 809 | VMXR0GlobalTerm();
|
---|
[87532] | 810 | else if (g_fHmSvmSupported)
|
---|
[46297] | 811 | SVMR0GlobalTerm();
|
---|
[45091] | 812 |
|
---|
[7471] | 813 | return rc;
|
---|
| 814 | }
|
---|
| 815 |
|
---|
[7476] | 816 |
|
---|
[37320] | 817 | /**
|
---|
[44577] | 818 | * Enable VT-x or AMD-V on the current CPU
|
---|
[8115] | 819 | *
|
---|
[23476] | 820 | * @returns VBox status code.
|
---|
[58122] | 821 | * @param pVM The cross context VM structure. Can be NULL.
|
---|
| 822 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
[48448] | 823 | *
|
---|
| 824 | * @remarks Maybe called with interrupts disabled!
|
---|
[7471] | 825 | */
|
---|
[80274] | 826 | static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
|
---|
[7471] | 827 | {
|
---|
[87537] | 828 | PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
|
---|
[7471] | 829 |
|
---|
[48426] | 830 | Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
|
---|
[87537] | 831 | Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
|
---|
[72907] | 832 | Assert(!pHostCpu->fConfigured);
|
---|
[50872] | 833 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[7471] | 834 |
|
---|
[72907] | 835 | pHostCpu->idCpu = idCpu;
|
---|
[43494] | 836 | /* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
|
---|
[13025] | 837 |
|
---|
[43307] | 838 | int rc;
|
---|
[87532] | 839 | if ( g_fHmVmxSupported
|
---|
[87537] | 840 | && g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[87536] | 841 | rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmMsrs);
|
---|
[43307] | 842 | else
|
---|
| 843 | {
|
---|
[72907] | 844 | AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
|
---|
[87536] | 845 | rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmMsrs);
|
---|
[43307] | 846 | }
|
---|
[23476] | 847 | if (RT_SUCCESS(rc))
|
---|
[72907] | 848 | pHostCpu->fConfigured = true;
|
---|
[23476] | 849 | return rc;
|
---|
[7471] | 850 | }
|
---|
| 851 |
|
---|
[23476] | 852 |
|
---|
[7471] | 853 | /**
|
---|
[48267] | 854 | * Worker function passed to RTMpOnAll() that is to be called on all CPUs.
|
---|
[8115] | 855 | *
|
---|
[7471] | 856 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
[48208] | 857 | * @param pvUser1 Opaque pointer to the VM (can be NULL!).
|
---|
[7471] | 858 | * @param pvUser2 The 2nd user argument.
|
---|
| 859 | */
|
---|
[37320] | 860 | static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
[7471] | 861 | {
|
---|
[81861] | 862 | PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
|
---|
[37320] | 863 | PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
|
---|
[87537] | 864 | AssertReturnVoid(g_fHmGlobalInit);
|
---|
[49932] | 865 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[37320] | 866 | hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
|
---|
[23476] | 867 | }
|
---|
| 868 |
|
---|
| 869 |
|
---|
| 870 | /**
|
---|
[43387] | 871 | * RTOnce callback employed by HMR0EnableAllCpus.
|
---|
[37319] | 872 | *
|
---|
[41776] | 873 | * @returns VBox status code.
|
---|
| 874 | * @param pvUser Pointer to the VM.
|
---|
[37319] | 875 | */
|
---|
[43879] | 876 | static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
|
---|
[37319] | 877 | {
|
---|
[80274] | 878 | PVMCC pVM = (PVMCC)pvUser;
|
---|
[37319] | 879 |
|
---|
| 880 | /*
|
---|
| 881 | * Indicate that we've initialized.
|
---|
| 882 | *
|
---|
| 883 | * Note! There is a potential race between this function and the suspend
|
---|
| 884 | * notification. Kind of unlikely though, so ignored for now.
|
---|
| 885 | */
|
---|
[87537] | 886 | AssertReturn(!g_fHmEnabled, VERR_HM_ALREADY_ENABLED_IPE);
|
---|
| 887 | ASMAtomicWriteBool(&g_fHmEnabled, true);
|
---|
[37319] | 888 |
|
---|
| 889 | /*
|
---|
| 890 | * The global init variable is set by the first VM.
|
---|
| 891 | */
|
---|
[87537] | 892 | g_fHmGlobalInit = pVM->hm.s.fGlobalInit;
|
---|
[37319] | 893 |
|
---|
[49934] | 894 | #ifdef VBOX_STRICT
|
---|
[87537] | 895 | for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
|
---|
[43307] | 896 | {
|
---|
[87537] | 897 | Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
|
---|
| 898 | Assert(g_aHmCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
|
---|
| 899 | Assert(g_aHmCpuInfo[i].pvMemObj == NULL);
|
---|
| 900 | Assert(!g_aHmCpuInfo[i].fConfigured);
|
---|
| 901 | Assert(!g_aHmCpuInfo[i].cTlbFlushes);
|
---|
| 902 | Assert(!g_aHmCpuInfo[i].uCurrentAsid);
|
---|
[72208] | 903 | # ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
[87537] | 904 | Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
|
---|
| 905 | Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
|
---|
| 906 | Assert(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
|
---|
[71529] | 907 | # endif
|
---|
[43307] | 908 | }
|
---|
[49934] | 909 | #endif
|
---|
[43307] | 910 |
|
---|
[37319] | 911 | int rc;
|
---|
[87532] | 912 | if ( g_fHmVmxSupported
|
---|
[87537] | 913 | && g_fHmVmxUsingSUPR0EnableVTx)
|
---|
[37319] | 914 | {
|
---|
| 915 | /*
|
---|
| 916 | * Global VT-x initialization API (only darwin for now).
|
---|
| 917 | */
|
---|
| 918 | rc = SUPR0EnableVTx(true /* fEnable */);
|
---|
| 919 | if (RT_SUCCESS(rc))
|
---|
[50748] | 920 | {
|
---|
[87537] | 921 | g_fHmVmxCalledSUPR0EnableVTx = true;
|
---|
[37319] | 922 | /* If the host provides a VT-x init API, then we'll rely on that for global init. */
|
---|
[87537] | 923 | g_fHmGlobalInit = pVM->hm.s.fGlobalInit = true;
|
---|
[50748] | 924 | }
|
---|
[37319] | 925 | else
|
---|
[42045] | 926 | AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
|
---|
[37319] | 927 | }
|
---|
| 928 | else
|
---|
| 929 | {
|
---|
| 930 | /*
|
---|
| 931 | * We're doing the job ourselves.
|
---|
| 932 | */
|
---|
[47989] | 933 | /* Allocate one page per cpu for the global VT-x and AMD-V pages */
|
---|
[87537] | 934 | for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
|
---|
[37319] | 935 | {
|
---|
[87537] | 936 | Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
|
---|
[72208] | 937 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
[87537] | 938 | Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
|
---|
[71529] | 939 | #endif
|
---|
[37319] | 940 | if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
|
---|
| 941 | {
|
---|
[58912] | 942 | /** @todo NUMA */
|
---|
[100357] | 943 | rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].hMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /*PhysHighest*/, false /* executable R0 mapping */);
|
---|
[37319] | 944 | AssertLogRelRCReturn(rc, rc);
|
---|
| 945 |
|
---|
[87537] | 946 | g_aHmCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].hMemObj, 0);
|
---|
| 947 | Assert(g_aHmCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
|
---|
[93554] | 948 | Assert(!(g_aHmCpuInfo[i].HCPhysMemObj & HOST_PAGE_OFFSET_MASK));
|
---|
[58912] | 949 |
|
---|
[87537] | 950 | g_aHmCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_aHmCpuInfo[i].hMemObj);
|
---|
| 951 | AssertPtr(g_aHmCpuInfo[i].pvMemObj);
|
---|
[93557] | 952 | RT_BZERO(g_aHmCpuInfo[i].pvMemObj, HOST_PAGE_SIZE);
|
---|
[71529] | 953 |
|
---|
[72208] | 954 | #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
|
---|
[87537] | 955 | rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
|
---|
[100357] | 956 | NIL_RTHCPHYS /*PhysHighest*/, false /* executable R0 mapping */);
|
---|
[71529] | 957 | AssertLogRelRCReturn(rc, rc);
|
---|
| 958 |
|
---|
[87537] | 959 | g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, 0);
|
---|
| 960 | Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
|
---|
[93554] | 961 | Assert(!(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm & HOST_PAGE_OFFSET_MASK));
|
---|
[71529] | 962 |
|
---|
[87537] | 963 | g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm);
|
---|
| 964 | AssertPtr(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm);
|
---|
| 965 | ASMMemFill32(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
|
---|
[71529] | 966 | #endif
|
---|
[37319] | 967 | }
|
---|
| 968 | }
|
---|
| 969 |
|
---|
[43307] | 970 | rc = VINF_SUCCESS;
|
---|
[37319] | 971 | }
|
---|
| 972 |
|
---|
[47989] | 973 | if ( RT_SUCCESS(rc)
|
---|
[87537] | 974 | && g_fHmGlobalInit)
|
---|
[43307] | 975 | {
|
---|
[101380] | 976 | /*
|
---|
| 977 | * It's possible we end up here with VMX (and perhaps SVM) not supported, see @bugref{9918}.
|
---|
| 978 | * In that case, our HMR0 function table contains the dummy placeholder functions which pretend
|
---|
| 979 | * success. However, we must not pretend success any longer (like we did during HMR0Init called
|
---|
| 980 | * during VMMR0 module init) as the HM init error code (g_rcHmInit) should be propagated to
|
---|
[101388] | 981 | * ring-3 especially since we now have a VM instance.
|
---|
[101380] | 982 | */
|
---|
| 983 | if ( !g_fHmVmxSupported
|
---|
| 984 | && !g_fHmSvmSupported)
|
---|
| 985 | {
|
---|
| 986 | Assert(g_HmR0Ops.pfnEnableCpu == hmR0DummyEnableCpu);
|
---|
| 987 | Assert(RT_FAILURE(g_rcHmInit));
|
---|
| 988 | rc = g_rcHmInit;
|
---|
| 989 | }
|
---|
| 990 | else
|
---|
| 991 | {
|
---|
| 992 | /* First time, so initialize each cpu/core. */
|
---|
| 993 | HMR0FIRSTRC FirstRc;
|
---|
| 994 | hmR0FirstRcInit(&FirstRc);
|
---|
| 995 | Assert(g_HmR0Ops.pfnEnableCpu != hmR0DummyEnableCpu);
|
---|
| 996 | rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
|
---|
| 997 | if (RT_SUCCESS(rc))
|
---|
| 998 | rc = hmR0FirstRcGetStatus(&FirstRc);
|
---|
| 999 | }
|
---|
[43307] | 1000 | }
|
---|
| 1001 |
|
---|
[37319] | 1002 | return rc;
|
---|
| 1003 | }
|
---|
| 1004 |
|
---|
| 1005 |
|
---|
| 1006 | /**
|
---|
[43387] | 1007 | * Sets up HM on all cpus.
|
---|
[37319] | 1008 | *
|
---|
| 1009 | * @returns VBox status code.
|
---|
[58122] | 1010 | * @param pVM The cross context VM structure.
|
---|
[37319] | 1011 | */
|
---|
[80274] | 1012 | VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
|
---|
[37319] | 1013 | {
|
---|
[50748] | 1014 | /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
|
---|
[87537] | 1015 | if (ASMAtomicReadBool(&g_fHmSuspended))
|
---|
[43387] | 1016 | return VERR_HM_SUSPEND_PENDING;
|
---|
[37319] | 1017 |
|
---|
[87537] | 1018 | return RTOnce(&g_HmEnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
|
---|
[37319] | 1019 | }
|
---|
| 1020 |
|
---|
| 1021 |
|
---|
| 1022 | /**
|
---|
[41776] | 1023 | * Disable VT-x or AMD-V on the current CPU.
|
---|
[23476] | 1024 | *
|
---|
| 1025 | * @returns VBox status code.
|
---|
[54395] | 1026 | * @param idCpu The identifier for the CPU this function is called on.
|
---|
[48426] | 1027 | *
|
---|
| 1028 | * @remarks Must be called with preemption disabled.
|
---|
[23476] | 1029 | */
|
---|
[37320] | 1030 | static int hmR0DisableCpu(RTCPUID idCpu)
|
---|
[23476] | 1031 | {
|
---|
[87537] | 1032 | PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
|
---|
[7471] | 1033 |
|
---|
[87537] | 1034 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[48448] | 1035 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[48426] | 1036 | Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
|
---|
[87537] | 1037 | Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
|
---|
[72907] | 1038 | Assert(!pHostCpu->fConfigured || pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
|
---|
[54395] | 1039 | AssertRelease(idCpu == RTMpCpuId());
|
---|
[7471] | 1040 |
|
---|
[72907] | 1041 | if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
|
---|
| 1042 | return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
|
---|
| 1043 | AssertPtr(pHostCpu->pvMemObj);
|
---|
| 1044 | Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
|
---|
[7471] | 1045 |
|
---|
[37319] | 1046 | int rc;
|
---|
[72907] | 1047 | if (pHostCpu->fConfigured)
|
---|
[13514] | 1048 | {
|
---|
[87535] | 1049 | rc = g_HmR0Ops.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
|
---|
[48426] | 1050 | AssertRCReturn(rc, rc);
|
---|
| 1051 |
|
---|
[72907] | 1052 | pHostCpu->fConfigured = false;
|
---|
| 1053 | pHostCpu->idCpu = NIL_RTCPUID;
|
---|
[13514] | 1054 | }
|
---|
| 1055 | else
|
---|
[23476] | 1056 | rc = VINF_SUCCESS; /* nothing to do */
|
---|
| 1057 | return rc;
|
---|
[7471] | 1058 | }
|
---|
| 1059 |
|
---|
[37319] | 1060 |
|
---|
[13514] | 1061 | /**
|
---|
[48426] | 1062 | * Worker function passed to RTMpOnAll() that is to be called on the target
|
---|
| 1063 | * CPUs.
|
---|
[23476] | 1064 | *
|
---|
| 1065 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
| 1066 | * @param pvUser1 The 1st user argument.
|
---|
[48208] | 1067 | * @param pvUser2 Opaque pointer to the FirstRc.
|
---|
[23476] | 1068 | */
|
---|
[37320] | 1069 | static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
[23476] | 1070 | {
|
---|
[39078] | 1071 | PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
|
---|
[87537] | 1072 | AssertReturnVoid(g_fHmGlobalInit);
|
---|
[37320] | 1073 | hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
|
---|
[23476] | 1074 | }
|
---|
| 1075 |
|
---|
[37062] | 1076 |
|
---|
[23476] | 1077 | /**
|
---|
[54395] | 1078 | * Worker function passed to RTMpOnSpecific() that is to be called on the target
|
---|
| 1079 | * CPU.
|
---|
| 1080 | *
|
---|
| 1081 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
| 1082 | * @param pvUser1 Null, not used.
|
---|
| 1083 | * @param pvUser2 Null, not used.
|
---|
| 1084 | */
|
---|
| 1085 | static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
| 1086 | {
|
---|
| 1087 | NOREF(pvUser1);
|
---|
| 1088 | NOREF(pvUser2);
|
---|
| 1089 | hmR0DisableCpu(idCpu);
|
---|
| 1090 | }
|
---|
| 1091 |
|
---|
| 1092 |
|
---|
| 1093 | /**
|
---|
[37062] | 1094 | * Callback function invoked when a cpu goes online or offline.
|
---|
| 1095 | *
|
---|
| 1096 | * @param enmEvent The Mp event.
|
---|
| 1097 | * @param idCpu The identifier for the CPU the function is called on.
|
---|
[80274] | 1098 | * @param pvData Opaque data (PVMCC pointer).
|
---|
[37062] | 1099 | */
|
---|
[37320] | 1100 | static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
|
---|
[37062] | 1101 | {
|
---|
[39078] | 1102 | NOREF(pvData);
|
---|
[87537] | 1103 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[39078] | 1104 |
|
---|
[37062] | 1105 | /*
|
---|
| 1106 | * We only care about uninitializing a CPU that is going offline. When a
|
---|
[43387] | 1107 | * CPU comes online, the initialization is done lazily in HMR0Enter().
|
---|
[37062] | 1108 | */
|
---|
| 1109 | switch (enmEvent)
|
---|
| 1110 | {
|
---|
| 1111 | case RTMPEVENT_OFFLINE:
|
---|
| 1112 | {
|
---|
[54395] | 1113 | RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
|
---|
| 1114 | RTThreadPreemptDisable(&PreemptState);
|
---|
| 1115 | if (idCpu == RTMpCpuId())
|
---|
| 1116 | {
|
---|
| 1117 | int rc = hmR0DisableCpu(idCpu);
|
---|
| 1118 | AssertRC(rc);
|
---|
| 1119 | RTThreadPreemptRestore(&PreemptState);
|
---|
| 1120 | }
|
---|
| 1121 | else
|
---|
| 1122 | {
|
---|
| 1123 | RTThreadPreemptRestore(&PreemptState);
|
---|
| 1124 | RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 */, NULL /* pvUser2 */);
|
---|
| 1125 | }
|
---|
[37062] | 1126 | break;
|
---|
| 1127 | }
|
---|
| 1128 |
|
---|
| 1129 | default:
|
---|
| 1130 | break;
|
---|
| 1131 | }
|
---|
| 1132 | }
|
---|
| 1133 |
|
---|
| 1134 |
|
---|
| 1135 | /**
|
---|
[13514] | 1136 | * Called whenever a system power state change occurs.
|
---|
| 1137 | *
|
---|
[41776] | 1138 | * @param enmEvent The Power event.
|
---|
| 1139 | * @param pvUser User argument.
|
---|
[13514] | 1140 | */
|
---|
[37320] | 1141 | static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
|
---|
[13514] | 1142 | {
|
---|
| 1143 | NOREF(pvUser);
|
---|
[87537] | 1144 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[7471] | 1145 |
|
---|
[13514] | 1146 | #ifdef LOG_ENABLED
|
---|
[55436] | 1147 | if (enmEvent == RTPOWEREVENT_SUSPEND)
|
---|
| 1148 | SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
|
---|
| 1149 | else
|
---|
| 1150 | SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
|
---|
[13514] | 1151 | #endif
|
---|
| 1152 |
|
---|
[13516] | 1153 | if (enmEvent == RTPOWEREVENT_SUSPEND)
|
---|
[87537] | 1154 | ASMAtomicWriteBool(&g_fHmSuspended, true);
|
---|
[13516] | 1155 |
|
---|
[87537] | 1156 | if (g_fHmEnabled)
|
---|
[13514] | 1157 | {
|
---|
[37320] | 1158 | int rc;
|
---|
| 1159 | HMR0FIRSTRC FirstRc;
|
---|
| 1160 | hmR0FirstRcInit(&FirstRc);
|
---|
[13514] | 1161 |
|
---|
| 1162 | if (enmEvent == RTPOWEREVENT_SUSPEND)
|
---|
| 1163 | {
|
---|
[87537] | 1164 | if (g_fHmGlobalInit)
|
---|
[24484] | 1165 | {
|
---|
| 1166 | /* Turn off VT-x or AMD-V on all CPUs. */
|
---|
[48208] | 1167 | rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
|
---|
[24484] | 1168 | Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
|
---|
| 1169 | }
|
---|
| 1170 | /* else nothing to do here for the local init case */
|
---|
[13514] | 1171 | }
|
---|
[55436] | 1172 | else
|
---|
[13514] | 1173 | {
|
---|
[37320] | 1174 | /* Reinit the CPUs from scratch as the suspend state might have
|
---|
| 1175 | messed with the MSRs. (lousy BIOSes as usual) */
|
---|
[87532] | 1176 | if (g_fHmVmxSupported)
|
---|
[37320] | 1177 | rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
|
---|
| 1178 | else
|
---|
| 1179 | rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
|
---|
[13514] | 1180 | Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
|
---|
[13816] | 1181 | if (RT_SUCCESS(rc))
|
---|
[37320] | 1182 | rc = hmR0FirstRcGetStatus(&FirstRc);
|
---|
[13514] | 1183 | #ifdef LOG_ENABLED
|
---|
[13816] | 1184 | if (RT_FAILURE(rc))
|
---|
[37320] | 1185 | SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
|
---|
[13514] | 1186 | #endif
|
---|
[87537] | 1187 | if (g_fHmGlobalInit)
|
---|
[24484] | 1188 | {
|
---|
| 1189 | /* Turn VT-x or AMD-V back on on all CPUs. */
|
---|
[48208] | 1190 | rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM */, &FirstRc /* output ignored */);
|
---|
[24484] | 1191 | Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
|
---|
| 1192 | }
|
---|
| 1193 | /* else nothing to do here for the local init case */
|
---|
[13514] | 1194 | }
|
---|
| 1195 | }
|
---|
[37319] | 1196 |
|
---|
[13516] | 1197 | if (enmEvent == RTPOWEREVENT_RESUME)
|
---|
[87537] | 1198 | ASMAtomicWriteBool(&g_fHmSuspended, false);
|
---|
[13514] | 1199 | }
|
---|
| 1200 |
|
---|
| 1201 |
|
---|
[7471] | 1202 | /**
|
---|
[76464] | 1203 | * Does ring-0 per-VM HM initialization.
|
---|
[7471] | 1204 | *
|
---|
[76464] | 1205 | * This will call the CPU specific init. routine which may initialize and allocate
|
---|
| 1206 | * resources for virtual CPUs.
|
---|
[7471] | 1207 | *
|
---|
| 1208 | * @returns VBox status code.
|
---|
[58122] | 1209 | * @param pVM The cross context VM structure.
|
---|
[54153] | 1210 | *
|
---|
[76464] | 1211 | * @remarks This is called after HMR3Init(), see vmR3CreateU() and
|
---|
| 1212 | * vmR3InitRing3().
|
---|
[7471] | 1213 | */
|
---|
[80274] | 1214 | VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
|
---|
[7471] | 1215 | {
|
---|
[93655] | 1216 | AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
|
---|
| 1217 | AssertCompile(sizeof(pVM->hmr0.s) <= sizeof(pVM->hmr0.padding));
|
---|
| 1218 | AssertCompile(sizeof(pVM->aCpus[0].hm.s) <= sizeof(pVM->aCpus[0].hm.padding));
|
---|
| 1219 | AssertCompile(sizeof(pVM->aCpus[0].hmr0.s) <= sizeof(pVM->aCpus[0].hmr0.padding));
|
---|
[7496] | 1220 | AssertReturn(pVM, VERR_INVALID_PARAMETER);
|
---|
[7471] | 1221 |
|
---|
[76464] | 1222 | /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
|
---|
[87537] | 1223 | if (ASMAtomicReadBool(&g_fHmSuspended))
|
---|
[76464] | 1224 | return VERR_HM_SUSPEND_PENDING;
|
---|
| 1225 |
|
---|
[37320] | 1226 | /*
|
---|
| 1227 | * Copy globals to the VM structure.
|
---|
| 1228 | */
|
---|
[73293] | 1229 | Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
|
---|
| 1230 | if (pVM->hm.s.vmx.fSupported)
|
---|
| 1231 | {
|
---|
[87559] | 1232 | pVM->hmr0.s.vmx.fUsePreemptTimer = pVM->hm.s.vmx.fUsePreemptTimerCfg && g_fHmVmxUsePreemptTimer;
|
---|
| 1233 | pVM->hm.s.vmx.fUsePreemptTimerCfg = pVM->hmr0.s.vmx.fUsePreemptTimer;
|
---|
| 1234 | pVM->hm.s.vmx.cPreemptTimerShift = g_cHmVmxPreemptTimerShift;
|
---|
[87563] | 1235 | pVM->hm.s.ForR3.vmx.u64HostCr4 = g_uHmVmxHostCr4;
|
---|
| 1236 | pVM->hm.s.ForR3.vmx.u64HostMsrEfer = g_uHmVmxHostMsrEfer;
|
---|
| 1237 | pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl = g_uHmVmxHostSmmMonitorCtl;
|
---|
[91323] | 1238 | pVM->hm.s.ForR3.vmx.u64HostFeatCtrl = g_HmMsrs.u.vmx.u64FeatCtrl;
|
---|
[87563] | 1239 | HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.ForR3.vmx.Msrs);
|
---|
[79352] | 1240 | /* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
|
---|
[79345] | 1241 |
|
---|
| 1242 | /* Enable VPID if supported and configured. */
|
---|
[87543] | 1243 | if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
|
---|
[87563] | 1244 | pVM->hm.s.ForR3.vmx.fVpid = pVM->hmr0.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
|
---|
[79345] | 1245 |
|
---|
| 1246 | /* Use VMCS shadowing if supported. */
|
---|
[87557] | 1247 | pVM->hmr0.s.vmx.fUseVmcsShadowing = pVM->cpum.ro.GuestFeatures.fVmx
|
---|
| 1248 | && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING);
|
---|
[87563] | 1249 | pVM->hm.s.ForR3.vmx.fUseVmcsShadowing = pVM->hmr0.s.vmx.fUseVmcsShadowing;
|
---|
[79345] | 1250 |
|
---|
| 1251 | /* Use the VMCS controls for swapping the EFER MSR if supported. */
|
---|
[87563] | 1252 | pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer = g_fHmVmxSupportsVmcsEfer;
|
---|
[79345] | 1253 |
|
---|
| 1254 | #if 0
|
---|
| 1255 | /* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
|
---|
[87543] | 1256 | if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
|
---|
| 1257 | && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
|
---|
[79345] | 1258 | pVM->hm.s.fVirtApicRegs = true;
|
---|
| 1259 |
|
---|
| 1260 | /* Enable posted-interrupt processing if supported. */
|
---|
| 1261 | /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
|
---|
| 1262 | * here. */
|
---|
[87543] | 1263 | if ( (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
|
---|
| 1264 | && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
|
---|
[79345] | 1265 | pVM->hm.s.fPostedIntrs = true;
|
---|
| 1266 | #endif
|
---|
[73293] | 1267 | }
|
---|
| 1268 | else if (pVM->hm.s.svm.fSupported)
|
---|
| 1269 | {
|
---|
[87563] | 1270 | pVM->hm.s.ForR3.svm.u32Rev = g_uHmSvmRev;
|
---|
| 1271 | pVM->hm.s.ForR3.svm.fFeatures = g_fHmSvmFeatures;
|
---|
| 1272 | pVM->hm.s.ForR3.svm.u64MsrHwcr = g_HmMsrs.u.svm.u64MsrHwcr;
|
---|
[79352] | 1273 | /* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
|
---|
[73293] | 1274 | }
|
---|
[87563] | 1275 | pVM->hm.s.ForR3.rcInit = g_rcHmInit;
|
---|
| 1276 | pVM->hm.s.ForR3.uMaxAsid = g_uHmMaxAsid;
|
---|
[7496] | 1277 |
|
---|
[73293] | 1278 | /*
|
---|
| 1279 | * Set default maximum inner loops in ring-0 before returning to ring-3.
|
---|
| 1280 | * Can be overriden using CFGM.
|
---|
| 1281 | */
|
---|
[87519] | 1282 | uint32_t cMaxResumeLoops = pVM->hm.s.cMaxResumeLoopsCfg;
|
---|
| 1283 | if (!cMaxResumeLoops)
|
---|
[20132] | 1284 | {
|
---|
[87519] | 1285 | cMaxResumeLoops = 1024;
|
---|
[20132] | 1286 | if (RTThreadPreemptIsPendingTrusty())
|
---|
[87519] | 1287 | cMaxResumeLoops = 8192;
|
---|
[20132] | 1288 | }
|
---|
[87519] | 1289 | else if (cMaxResumeLoops > 16384)
|
---|
| 1290 | cMaxResumeLoops = 16384;
|
---|
| 1291 | else if (cMaxResumeLoops < 32)
|
---|
| 1292 | cMaxResumeLoops = 32;
|
---|
| 1293 | pVM->hm.s.cMaxResumeLoopsCfg = pVM->hmr0.s.cMaxResumeLoops = cMaxResumeLoops;
|
---|
[20132] | 1294 |
|
---|
[37320] | 1295 | /*
|
---|
[55754] | 1296 | * Initialize some per-VCPU fields.
|
---|
[37320] | 1297 | */
|
---|
[80274] | 1298 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
[13883] | 1299 | {
|
---|
[80274] | 1300 | PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
|
---|
[87479] | 1301 | pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
|
---|
| 1302 | pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
|
---|
[13898] | 1303 |
|
---|
[50789] | 1304 | /* We'll aways increment this the first time (host uses ASID 0). */
|
---|
[87479] | 1305 | AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
|
---|
[13883] | 1306 | }
|
---|
[13025] | 1307 |
|
---|
[76290] | 1308 | /*
|
---|
[87522] | 1309 | * Configure defences against spectre and other CPU bugs.
|
---|
| 1310 | */
|
---|
| 1311 | uint32_t fWorldSwitcher = 0;
|
---|
| 1312 | uint32_t cLastStdLeaf = ASMCpuId_EAX(0);
|
---|
[93515] | 1313 | if (cLastStdLeaf >= 0x00000007 && RTX86IsValidStdRange(cLastStdLeaf))
|
---|
[87522] | 1314 | {
|
---|
| 1315 | uint32_t uEdx = 0;
|
---|
| 1316 | ASMCpuIdExSlow(0x00000007, 0, 0, 0, NULL, NULL, NULL, &uEdx);
|
---|
| 1317 |
|
---|
[87606] | 1318 | if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB)
|
---|
[87522] | 1319 | {
|
---|
| 1320 | if (pVM->hm.s.fIbpbOnVmExit)
|
---|
| 1321 | fWorldSwitcher |= HM_WSF_IBPB_EXIT;
|
---|
| 1322 | if (pVM->hm.s.fIbpbOnVmEntry)
|
---|
| 1323 | fWorldSwitcher |= HM_WSF_IBPB_ENTRY;
|
---|
| 1324 | }
|
---|
[87606] | 1325 | if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
|
---|
| 1326 | {
|
---|
| 1327 | if (pVM->hm.s.fL1dFlushOnVmEntry)
|
---|
| 1328 | fWorldSwitcher |= HM_WSF_L1D_ENTRY;
|
---|
| 1329 | else if (pVM->hm.s.fL1dFlushOnSched)
|
---|
| 1330 | fWorldSwitcher |= HM_WSF_L1D_SCHED;
|
---|
| 1331 | }
|
---|
| 1332 | if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
|
---|
| 1333 | {
|
---|
| 1334 | if (pVM->hm.s.fMdsClearOnVmEntry)
|
---|
| 1335 | fWorldSwitcher |= HM_WSF_MDS_ENTRY;
|
---|
| 1336 | else if (pVM->hm.s.fMdsClearOnSched)
|
---|
| 1337 | fWorldSwitcher |= HM_WSF_MDS_SCHED;
|
---|
| 1338 | }
|
---|
[87522] | 1339 | }
|
---|
| 1340 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
| 1341 | {
|
---|
| 1342 | PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
|
---|
| 1343 | pVCpu->hmr0.s.fWorldSwitcher = fWorldSwitcher;
|
---|
| 1344 | }
|
---|
[87563] | 1345 | pVM->hm.s.ForR3.fWorldSwitcher = fWorldSwitcher;
|
---|
[87522] | 1346 |
|
---|
| 1347 |
|
---|
| 1348 | /*
|
---|
[37320] | 1349 | * Call the hardware specific initialization method.
|
---|
| 1350 | */
|
---|
[87535] | 1351 | return g_HmR0Ops.pfnInitVM(pVM);
|
---|
[1] | 1352 | }
|
---|
| 1353 |
|
---|
| 1354 |
|
---|
[7496] | 1355 | /**
|
---|
[51560] | 1356 | * Does ring-0 per VM HM termination.
|
---|
[7496] | 1357 | *
|
---|
| 1358 | * @returns VBox status code.
|
---|
[58122] | 1359 | * @param pVM The cross context VM structure.
|
---|
[7496] | 1360 | */
|
---|
[80274] | 1361 | VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
|
---|
[7496] | 1362 | {
|
---|
[43387] | 1363 | Log(("HMR0TermVM: %p\n", pVM));
|
---|
[7496] | 1364 | AssertReturn(pVM, VERR_INVALID_PARAMETER);
|
---|
| 1365 |
|
---|
[37320] | 1366 | /*
|
---|
| 1367 | * Call the hardware specific method.
|
---|
[48621] | 1368 | *
|
---|
| 1369 | * Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
|
---|
| 1370 | * mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
|
---|
[37320] | 1371 | */
|
---|
[87535] | 1372 | return g_HmR0Ops.pfnTermVM(pVM);
|
---|
[7496] | 1373 | }
|
---|
| 1374 |
|
---|
| 1375 |
|
---|
[1] | 1376 | /**
|
---|
[37320] | 1377 | * Sets up a VT-x or AMD-V session.
|
---|
[1] | 1378 | *
|
---|
[37320] | 1379 | * This is mostly about setting up the hardware VM state.
|
---|
| 1380 | *
|
---|
[1] | 1381 | * @returns VBox status code.
|
---|
[58122] | 1382 | * @param pVM The cross context VM structure.
|
---|
[1] | 1383 | */
|
---|
[80274] | 1384 | VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
|
---|
[1] | 1385 | {
|
---|
[43387] | 1386 | Log(("HMR0SetupVM: %p\n", pVM));
|
---|
[7496] | 1387 | AssertReturn(pVM, VERR_INVALID_PARAMETER);
|
---|
[1] | 1388 |
|
---|
[50748] | 1389 | /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
|
---|
[87537] | 1390 | AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
|
---|
[13516] | 1391 |
|
---|
[48621] | 1392 | /* On first entry we'll sync everything. */
|
---|
[80274] | 1393 | VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
|
---|
[48621] | 1394 |
|
---|
[37320] | 1395 | /*
|
---|
[48621] | 1396 | * Call the hardware specific setup VM method. This requires the CPU to be
|
---|
[37320] | 1397 | * enabled for AMD-V/VT-x and preemption to be prevented.
|
---|
| 1398 | */
|
---|
[48621] | 1399 | RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
|
---|
| 1400 | RTThreadPreemptDisable(&PreemptState);
|
---|
[72762] | 1401 | RTCPUID const idCpu = RTMpCpuId();
|
---|
[13533] | 1402 |
|
---|
[23476] | 1403 | /* Enable VT-x or AMD-V if local init is required. */
|
---|
[37320] | 1404 | int rc;
|
---|
[87537] | 1405 | if (!g_fHmGlobalInit)
|
---|
[23476] | 1406 | {
|
---|
[87537] | 1407 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[37320] | 1408 | rc = hmR0EnableCpu(pVM, idCpu);
|
---|
[55754] | 1409 | if (RT_FAILURE(rc))
|
---|
| 1410 | {
|
---|
[55755] | 1411 | RTThreadPreemptRestore(&PreemptState);
|
---|
[55754] | 1412 | return rc;
|
---|
| 1413 | }
|
---|
[23476] | 1414 | }
|
---|
| 1415 |
|
---|
[7496] | 1416 | /* Setup VT-x or AMD-V. */
|
---|
[87535] | 1417 | rc = g_HmR0Ops.pfnSetupVM(pVM);
|
---|
[13533] | 1418 |
|
---|
[23476] | 1419 | /* Disable VT-x or AMD-V if local init was done before. */
|
---|
[87537] | 1420 | if (!g_fHmGlobalInit)
|
---|
[23476] | 1421 | {
|
---|
[87537] | 1422 | Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
|
---|
[37320] | 1423 | int rc2 = hmR0DisableCpu(idCpu);
|
---|
| 1424 | AssertRC(rc2);
|
---|
[23476] | 1425 | }
|
---|
| 1426 |
|
---|
[48621] | 1427 | RTThreadPreemptRestore(&PreemptState);
|
---|
[13533] | 1428 | return rc;
|
---|
[1] | 1429 | }
|
---|
| 1430 |
|
---|
| 1431 |
|
---|
| 1432 | /**
|
---|
[92392] | 1433 | * Notification callback before an assertion longjump and guru mediation.
|
---|
[80587] | 1434 | *
|
---|
| 1435 | * @returns VBox status code.
|
---|
| 1436 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1437 | * @param pvUser User argument, currently unused, NULL.
|
---|
| 1438 | */
|
---|
[92392] | 1439 | static DECLCALLBACK(int) hmR0AssertionCallback(PVMCPUCC pVCpu, void *pvUser)
|
---|
[80587] | 1440 | {
|
---|
| 1441 | RT_NOREF(pvUser);
|
---|
| 1442 | Assert(pVCpu);
|
---|
[92392] | 1443 | Assert(g_HmR0Ops.pfnAssertionCallback);
|
---|
| 1444 | return g_HmR0Ops.pfnAssertionCallback(pVCpu);
|
---|
[80587] | 1445 | }
|
---|
| 1446 |
|
---|
| 1447 |
|
---|
| 1448 | /**
|
---|
[48037] | 1449 | * Turns on HM on the CPU if necessary and initializes the bare minimum state
|
---|
| 1450 | * required for entering HM context.
|
---|
[47760] | 1451 | *
|
---|
[48037] | 1452 | * @returns VBox status code.
|
---|
[58123] | 1453 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[47959] | 1454 | *
|
---|
| 1455 | * @remarks No-long-jump zone!!!
|
---|
[47760] | 1456 | */
|
---|
[80274] | 1457 | VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
|
---|
[47760] | 1458 | {
|
---|
| 1459 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
| 1460 |
|
---|
[72907] | 1461 | int rc = VINF_SUCCESS;
|
---|
| 1462 | RTCPUID const idCpu = RTMpCpuId();
|
---|
[87537] | 1463 | PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
|
---|
[72907] | 1464 | AssertPtr(pHostCpu);
|
---|
[47760] | 1465 |
|
---|
| 1466 | /* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
|
---|
[72907] | 1467 | if (!pHostCpu->fConfigured)
|
---|
[48037] | 1468 | rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
|
---|
[47802] | 1469 |
|
---|
[80587] | 1470 | /* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
|
---|
[92392] | 1471 | VMMR0AssertionSetNotification(pVCpu, hmR0AssertionCallback, NULL /*pvUser*/);
|
---|
[80587] | 1472 |
|
---|
[50748] | 1473 | /* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
|
---|
[87532] | 1474 | if (g_fHmVmxSupported)
|
---|
[72744] | 1475 | pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
|
---|
| 1476 | else
|
---|
| 1477 | pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
|
---|
[50800] | 1478 |
|
---|
[72907] | 1479 | Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
|
---|
[87479] | 1480 | pVCpu->hmr0.s.idEnteredCpu = idCpu;
|
---|
[48037] | 1481 | return rc;
|
---|
[47760] | 1482 | }
|
---|
| 1483 |
|
---|
| 1484 |
|
---|
| 1485 | /**
|
---|
[41776] | 1486 | * Enters the VT-x or AMD-V session.
|
---|
[1] | 1487 | *
|
---|
| 1488 | * @returns VBox status code.
|
---|
[58123] | 1489 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[37320] | 1490 | *
|
---|
| 1491 | * @remarks This is called with preemption disabled.
|
---|
[1] | 1492 | */
|
---|
[80274] | 1493 | VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
|
---|
[1] | 1494 | {
|
---|
[37320] | 1495 | /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
|
---|
[87537] | 1496 | AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
|
---|
[48037] | 1497 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[13516] | 1498 |
|
---|
[47760] | 1499 | /* Load the bare minimum state required for entering HM. */
|
---|
[72805] | 1500 | int rc = hmR0EnterCpu(pVCpu);
|
---|
[76482] | 1501 | if (RT_SUCCESS(rc))
|
---|
| 1502 | {
|
---|
[87532] | 1503 | if (g_fHmVmxSupported)
|
---|
| 1504 | Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
|
---|
| 1505 | == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
|
---|
[76482] | 1506 | else
|
---|
[87532] | 1507 | Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
|
---|
| 1508 | == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
|
---|
[20981] | 1509 |
|
---|
[76482] | 1510 | /* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
|
---|
[87535] | 1511 | rc = g_HmR0Ops.pfnEnterSession(pVCpu);
|
---|
[87479] | 1512 | AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
|
---|
[47760] | 1513 |
|
---|
[76482] | 1514 | /* Exports the host-state as we may be resuming code after a longjmp and quite
|
---|
| 1515 | possibly now be scheduled on a different CPU. */
|
---|
[87535] | 1516 | rc = g_HmR0Ops.pfnExportHostState(pVCpu);
|
---|
[87479] | 1517 | AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
|
---|
[76482] | 1518 | }
|
---|
[9407] | 1519 | return rc;
|
---|
[1] | 1520 | }
|
---|
| 1521 |
|
---|
| 1522 |
|
---|
| 1523 | /**
|
---|
[48037] | 1524 | * Deinitializes the bare minimum state used for HM context and if necessary
|
---|
| 1525 | * disable HM on the CPU.
|
---|
[47760] | 1526 | *
|
---|
| 1527 | * @returns VBox status code.
|
---|
[58123] | 1528 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[48044] | 1529 | *
|
---|
| 1530 | * @remarks No-long-jump zone!!!
|
---|
[47760] | 1531 | */
|
---|
[80274] | 1532 | VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
|
---|
[47760] | 1533 | {
|
---|
| 1534 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[51560] | 1535 | VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
|
---|
[47760] | 1536 |
|
---|
[76482] | 1537 | RTCPUID const idCpu = RTMpCpuId();
|
---|
[87537] | 1538 | PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
|
---|
[47989] | 1539 |
|
---|
[87537] | 1540 | if ( !g_fHmGlobalInit
|
---|
[72907] | 1541 | && pHostCpu->fConfigured)
|
---|
[47760] | 1542 | {
|
---|
| 1543 | int rc = hmR0DisableCpu(idCpu);
|
---|
| 1544 | AssertRCReturn(rc, rc);
|
---|
[72907] | 1545 | Assert(!pHostCpu->fConfigured);
|
---|
| 1546 | Assert(pHostCpu->idCpu == NIL_RTCPUID);
|
---|
[50740] | 1547 |
|
---|
| 1548 | /* For obtaining a non-zero ASID/VPID on next re-entry. */
|
---|
[87479] | 1549 | pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
|
---|
[47760] | 1550 | }
|
---|
| 1551 |
|
---|
[50740] | 1552 | /* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
|
---|
[87479] | 1553 | pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
|
---|
[47760] | 1554 |
|
---|
[80587] | 1555 | /* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
|
---|
[92392] | 1556 | VMMR0AssertionRemoveNotification(pVCpu);
|
---|
[47760] | 1557 | return VINF_SUCCESS;
|
---|
| 1558 | }
|
---|
| 1559 |
|
---|
| 1560 |
|
---|
| 1561 | /**
|
---|
| 1562 | * Thread-context hook for HM.
|
---|
| 1563 | *
|
---|
[90379] | 1564 | * This is used together with RTThreadCtxHookCreate() on platforms which
|
---|
| 1565 | * supports it, and directly from VMMR0EmtPrepareForBlocking() and
|
---|
| 1566 | * VMMR0EmtResumeAfterBlocking() on platforms which don't.
|
---|
| 1567 | *
|
---|
[47760] | 1568 | * @param enmEvent The thread-context event.
|
---|
| 1569 | * @param pvUser Opaque pointer to the VMCPU.
|
---|
| 1570 | */
|
---|
| 1571 | VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
|
---|
| 1572 | {
|
---|
[80274] | 1573 | PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
|
---|
[47760] | 1574 | Assert(pVCpu);
|
---|
[87535] | 1575 | Assert(g_HmR0Ops.pfnThreadCtxCallback);
|
---|
[23476] | 1576 |
|
---|
[87537] | 1577 | g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_fHmGlobalInit);
|
---|
[1] | 1578 | }
|
---|
| 1579 |
|
---|
[37320] | 1580 |
|
---|
[1] | 1581 | /**
|
---|
| 1582 | * Runs guest code in a hardware accelerated VM.
|
---|
| 1583 | *
|
---|
[58913] | 1584 | * @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
|
---|
| 1585 | * called from setjmp assembly.)
|
---|
[58122] | 1586 | * @param pVM The cross context VM structure.
|
---|
[58123] | 1587 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[37320] | 1588 | *
|
---|
[48426] | 1589 | * @remarks Can be called with preemption enabled if thread-context hooks are
|
---|
| 1590 | * used!!!
|
---|
[1] | 1591 | */
|
---|
[80274] | 1592 | VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
|
---|
[1] | 1593 | {
|
---|
[72805] | 1594 | RT_NOREF(pVM);
|
---|
| 1595 |
|
---|
[13533] | 1596 | #ifdef VBOX_STRICT
|
---|
[48426] | 1597 | /* With thread-context hooks we would be running this code with preemption enabled. */
|
---|
| 1598 | if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
|
---|
| 1599 | {
|
---|
[87537] | 1600 | PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[RTMpCpuId()];
|
---|
[74789] | 1601 | Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
|
---|
[72907] | 1602 | Assert(pHostCpu->fConfigured);
|
---|
[87537] | 1603 | AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
|
---|
[48426] | 1604 | }
|
---|
[37319] | 1605 | #endif
|
---|
[10301] | 1606 |
|
---|
[87535] | 1607 | VBOXSTRICTRC rcStrict = g_HmR0Ops.pfnRunGuestCode(pVCpu);
|
---|
[58913] | 1608 | return VBOXSTRICTRC_VAL(rcStrict);
|
---|
[1] | 1609 | }
|
---|
| 1610 |
|
---|
[61144] | 1611 |
|
---|
| 1612 | /**
|
---|
| 1613 | * Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
|
---|
| 1614 | * the host CPU and that guest access to it must be intercepted.
|
---|
| 1615 | *
|
---|
| 1616 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 1617 | */
|
---|
[80274] | 1618 | VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
|
---|
[61144] | 1619 | {
|
---|
[72744] | 1620 | ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
|
---|
[61144] | 1621 | }
|
---|
| 1622 |
|
---|
| 1623 |
|
---|
[61317] | 1624 | /**
|
---|
| 1625 | * Notification from CPUM that it has modified the host CR0 (because of FPU).
|
---|
| 1626 | *
|
---|
| 1627 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 1628 | */
|
---|
[80274] | 1629 | VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
|
---|
[61317] | 1630 | {
|
---|
[72744] | 1631 | ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
|
---|
[61317] | 1632 | }
|
---|
| 1633 |
|
---|
| 1634 |
|
---|
[10502] | 1635 | /**
|
---|
[41776] | 1636 | * Returns suspend status of the host.
|
---|
[13517] | 1637 | *
|
---|
[41776] | 1638 | * @returns Suspend pending or not.
|
---|
[13517] | 1639 | */
|
---|
[44373] | 1640 | VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
|
---|
[13517] | 1641 | {
|
---|
[87537] | 1642 | return ASMAtomicReadBool(&g_fHmSuspended);
|
---|
[13517] | 1643 | }
|
---|
| 1644 |
|
---|
[37320] | 1645 |
|
---|
[13517] | 1646 | /**
|
---|
[72643] | 1647 | * Invalidates a guest page from the host TLB.
|
---|
| 1648 | *
|
---|
| 1649 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1650 | * @param GCVirt Page to invalidate.
|
---|
| 1651 | */
|
---|
[80274] | 1652 | VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
|
---|
[72643] | 1653 | {
|
---|
[80274] | 1654 | PVMCC pVM = pVCpu->CTX_SUFF(pVM);
|
---|
[72643] | 1655 | if (pVM->hm.s.vmx.fSupported)
|
---|
[72805] | 1656 | return VMXR0InvalidatePage(pVCpu, GCVirt);
|
---|
| 1657 | return SVMR0InvalidatePage(pVCpu, GCVirt);
|
---|
[72643] | 1658 | }
|
---|
| 1659 |
|
---|
| 1660 |
|
---|
| 1661 | /**
|
---|
[10502] | 1662 | * Returns the cpu structure for the current cpu.
|
---|
| 1663 | * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
|
---|
| 1664 | *
|
---|
[41776] | 1665 | * @returns The cpu structure pointer.
|
---|
[10502] | 1666 | */
|
---|
[76482] | 1667 | VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
|
---|
[10502] | 1668 | {
|
---|
[48426] | 1669 | Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
|
---|
[72750] | 1670 | RTCPUID const idCpu = RTMpCpuId();
|
---|
[87537] | 1671 | Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
|
---|
| 1672 | return &g_aHmCpuInfo[idCpu];
|
---|
[10502] | 1673 | }
|
---|
| 1674 |
|
---|
[37320] | 1675 |
|
---|
[14845] | 1676 | /**
|
---|
[72643] | 1677 | * Interface for importing state on demand (used by IEM).
|
---|
| 1678 | *
|
---|
| 1679 | * @returns VBox status code.
|
---|
| 1680 | * @param pVCpu The cross context CPU structure.
|
---|
| 1681 | * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
|
---|
| 1682 | */
|
---|
[80274] | 1683 | VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
|
---|
[72643] | 1684 | {
|
---|
[72744] | 1685 | if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
|
---|
| 1686 | return VMXR0ImportStateOnDemand(pVCpu, fWhat);
|
---|
| 1687 | return SVMR0ImportStateOnDemand(pVCpu, fWhat);
|
---|
[72643] | 1688 | }
|
---|
| 1689 |
|
---|
[93963] | 1690 |
|
---|
| 1691 | /**
|
---|
| 1692 | * Gets HM VM-exit auxiliary information.
|
---|
| 1693 | *
|
---|
| 1694 | * @returns VBox status code.
|
---|
| 1695 | * @param pVCpu The cross context CPU structure.
|
---|
| 1696 | * @param pHmExitAux Where to store the auxiliary info.
|
---|
| 1697 | * @param fWhat What to get, see HMVMX_READ_XXX. This is ignored/unused
|
---|
| 1698 | * on AMD-V.
|
---|
| 1699 | *
|
---|
| 1700 | * @remarks Currently this works only when executing a nested-guest using
|
---|
| 1701 | * hardware-assisted execution as it's where the auxiliary information is
|
---|
| 1702 | * required outside of HM. In the future we can make this available while
|
---|
| 1703 | * executing a regular (non-nested) guest if necessary.
|
---|
| 1704 | */
|
---|
| 1705 | VMMR0_INT_DECL(int) HMR0GetExitAuxInfo(PVMCPUCC pVCpu, PHMEXITAUX pHmExitAux, uint32_t fWhat)
|
---|
| 1706 | {
|
---|
| 1707 | Assert(pHmExitAux);
|
---|
| 1708 | Assert(!(fWhat & ~HMVMX_READ_VALID_MASK));
|
---|
| 1709 | if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
|
---|
| 1710 | return VMXR0GetExitAuxInfo(pVCpu, &pHmExitAux->Vmx, fWhat);
|
---|
| 1711 | return SVMR0GetExitAuxInfo(pVCpu, &pHmExitAux->Svm);
|
---|
| 1712 | }
|
---|
| 1713 |
|
---|
| 1714 |
|
---|
[80047] | 1715 | #ifdef VBOX_STRICT
|
---|
[72643] | 1716 |
|
---|
[21208] | 1717 | /**
|
---|
[1] | 1718 | * Dumps a descriptor.
|
---|
| 1719 | *
|
---|
[9413] | 1720 | * @param pDesc Descriptor to dump.
|
---|
[80094] | 1721 | * @param Sel The selector.
|
---|
| 1722 | * @param pszSel The name of the selector.
|
---|
[1] | 1723 | */
|
---|
[80094] | 1724 | VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
|
---|
[1] | 1725 | {
|
---|
| 1726 | /*
|
---|
| 1727 | * Make variable description string.
|
---|
| 1728 | */
|
---|
| 1729 | static struct
|
---|
| 1730 | {
|
---|
| 1731 | unsigned cch;
|
---|
| 1732 | const char *psz;
|
---|
[22429] | 1733 | } const s_aTypes[32] =
|
---|
[1] | 1734 | {
|
---|
[12702] | 1735 | # define STRENTRY(str) { sizeof(str) - 1, str }
|
---|
[2811] | 1736 |
|
---|
[1] | 1737 | /* system */
|
---|
[12702] | 1738 | # if HC_ARCH_BITS == 64
|
---|
[1] | 1739 | STRENTRY("Reserved0 "), /* 0x00 */
|
---|
[2811] | 1740 | STRENTRY("Reserved1 "), /* 0x01 */
|
---|
| 1741 | STRENTRY("LDT "), /* 0x02 */
|
---|
| 1742 | STRENTRY("Reserved3 "), /* 0x03 */
|
---|
| 1743 | STRENTRY("Reserved4 "), /* 0x04 */
|
---|
| 1744 | STRENTRY("Reserved5 "), /* 0x05 */
|
---|
| 1745 | STRENTRY("Reserved6 "), /* 0x06 */
|
---|
| 1746 | STRENTRY("Reserved7 "), /* 0x07 */
|
---|
| 1747 | STRENTRY("Reserved8 "), /* 0x08 */
|
---|
| 1748 | STRENTRY("TSS64Avail "), /* 0x09 */
|
---|
| 1749 | STRENTRY("ReservedA "), /* 0x0a */
|
---|
| 1750 | STRENTRY("TSS64Busy "), /* 0x0b */
|
---|
| 1751 | STRENTRY("Call64 "), /* 0x0c */
|
---|
| 1752 | STRENTRY("ReservedD "), /* 0x0d */
|
---|
| 1753 | STRENTRY("Int64 "), /* 0x0e */
|
---|
| 1754 | STRENTRY("Trap64 "), /* 0x0f */
|
---|
[12702] | 1755 | # else
|
---|
[2811] | 1756 | STRENTRY("Reserved0 "), /* 0x00 */
|
---|
[1] | 1757 | STRENTRY("TSS16Avail "), /* 0x01 */
|
---|
| 1758 | STRENTRY("LDT "), /* 0x02 */
|
---|
| 1759 | STRENTRY("TSS16Busy "), /* 0x03 */
|
---|
| 1760 | STRENTRY("Call16 "), /* 0x04 */
|
---|
| 1761 | STRENTRY("Task "), /* 0x05 */
|
---|
| 1762 | STRENTRY("Int16 "), /* 0x06 */
|
---|
| 1763 | STRENTRY("Trap16 "), /* 0x07 */
|
---|
| 1764 | STRENTRY("Reserved8 "), /* 0x08 */
|
---|
| 1765 | STRENTRY("TSS32Avail "), /* 0x09 */
|
---|
| 1766 | STRENTRY("ReservedA "), /* 0x0a */
|
---|
| 1767 | STRENTRY("TSS32Busy "), /* 0x0b */
|
---|
| 1768 | STRENTRY("Call32 "), /* 0x0c */
|
---|
| 1769 | STRENTRY("ReservedD "), /* 0x0d */
|
---|
| 1770 | STRENTRY("Int32 "), /* 0x0e */
|
---|
| 1771 | STRENTRY("Trap32 "), /* 0x0f */
|
---|
[12702] | 1772 | # endif
|
---|
[1] | 1773 | /* non system */
|
---|
| 1774 | STRENTRY("DataRO "), /* 0x10 */
|
---|
| 1775 | STRENTRY("DataRO Accessed "), /* 0x11 */
|
---|
| 1776 | STRENTRY("DataRW "), /* 0x12 */
|
---|
| 1777 | STRENTRY("DataRW Accessed "), /* 0x13 */
|
---|
| 1778 | STRENTRY("DataDownRO "), /* 0x14 */
|
---|
| 1779 | STRENTRY("DataDownRO Accessed "), /* 0x15 */
|
---|
| 1780 | STRENTRY("DataDownRW "), /* 0x16 */
|
---|
| 1781 | STRENTRY("DataDownRW Accessed "), /* 0x17 */
|
---|
| 1782 | STRENTRY("CodeEO "), /* 0x18 */
|
---|
| 1783 | STRENTRY("CodeEO Accessed "), /* 0x19 */
|
---|
| 1784 | STRENTRY("CodeER "), /* 0x1a */
|
---|
| 1785 | STRENTRY("CodeER Accessed "), /* 0x1b */
|
---|
| 1786 | STRENTRY("CodeConfEO "), /* 0x1c */
|
---|
| 1787 | STRENTRY("CodeConfEO Accessed "), /* 0x1d */
|
---|
| 1788 | STRENTRY("CodeConfER "), /* 0x1e */
|
---|
| 1789 | STRENTRY("CodeConfER Accessed ") /* 0x1f */
|
---|
[12702] | 1790 | # undef SYSENTRY
|
---|
[1] | 1791 | };
|
---|
[12702] | 1792 | # define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
|
---|
[1] | 1793 | char szMsg[128];
|
---|
| 1794 | char *psz = &szMsg[0];
|
---|
[9413] | 1795 | unsigned i = pDesc->Gen.u1DescType << 4 | pDesc->Gen.u4Type;
|
---|
[22429] | 1796 | memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
|
---|
| 1797 | psz += s_aTypes[i].cch;
|
---|
[1] | 1798 |
|
---|
[9413] | 1799 | if (pDesc->Gen.u1Present)
|
---|
[1] | 1800 | ADD_STR(psz, "Present ");
|
---|
| 1801 | else
|
---|
| 1802 | ADD_STR(psz, "Not-Present ");
|
---|
[12702] | 1803 | # if HC_ARCH_BITS == 64
|
---|
[9413] | 1804 | if (pDesc->Gen.u1Long)
|
---|
[2811] | 1805 | ADD_STR(psz, "64-bit ");
|
---|
| 1806 | else
|
---|
[80094] | 1807 | ADD_STR(psz, "Comp ");
|
---|
[12702] | 1808 | # else
|
---|
[9413] | 1809 | if (pDesc->Gen.u1Granularity)
|
---|
[1] | 1810 | ADD_STR(psz, "Page ");
|
---|
[9413] | 1811 | if (pDesc->Gen.u1DefBig)
|
---|
[1] | 1812 | ADD_STR(psz, "32-bit ");
|
---|
| 1813 | else
|
---|
| 1814 | ADD_STR(psz, "16-bit ");
|
---|
[12702] | 1815 | # endif
|
---|
| 1816 | # undef ADD_STR
|
---|
[1] | 1817 | *psz = '\0';
|
---|
| 1818 |
|
---|
| 1819 | /*
|
---|
| 1820 | * Limit and Base and format the output.
|
---|
| 1821 | */
|
---|
[57564] | 1822 | #ifdef LOG_ENABLED
|
---|
| 1823 | uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
|
---|
[2811] | 1824 |
|
---|
[12702] | 1825 | # if HC_ARCH_BITS == 64
|
---|
[80094] | 1826 | uint64_t const u64Base = X86DESC64_BASE(pDesc);
|
---|
| 1827 | Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
|
---|
| 1828 | Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
|
---|
[12702] | 1829 | # else
|
---|
[80094] | 1830 | uint32_t const u32Base = X86DESC_BASE(pDesc);
|
---|
| 1831 | Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
|
---|
[9413] | 1832 | Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
|
---|
[12702] | 1833 | # endif
|
---|
[57859] | 1834 | #else
|
---|
[80094] | 1835 | NOREF(Sel); NOREF(pszSel);
|
---|
[57564] | 1836 | #endif
|
---|
[1] | 1837 | }
|
---|
| 1838 |
|
---|
[37320] | 1839 |
|
---|
[1] | 1840 | /**
|
---|
| 1841 | * Formats a full register dump.
|
---|
| 1842 | *
|
---|
[80266] | 1843 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 1844 | * @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
|
---|
[1] | 1845 | */
|
---|
[80274] | 1846 | VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
|
---|
[1] | 1847 | {
|
---|
| 1848 | /*
|
---|
| 1849 | * Format the flags.
|
---|
| 1850 | */
|
---|
| 1851 | static struct
|
---|
| 1852 | {
|
---|
[80266] | 1853 | const char *pszSet;
|
---|
| 1854 | const char *pszClear;
|
---|
| 1855 | uint32_t fFlag;
|
---|
[39078] | 1856 | } const s_aFlags[] =
|
---|
[1] | 1857 | {
|
---|
[50748] | 1858 | { "vip", NULL, X86_EFL_VIP },
|
---|
| 1859 | { "vif", NULL, X86_EFL_VIF },
|
---|
[72744] | 1860 | { "ac", NULL, X86_EFL_AC },
|
---|
| 1861 | { "vm", NULL, X86_EFL_VM },
|
---|
| 1862 | { "rf", NULL, X86_EFL_RF },
|
---|
| 1863 | { "nt", NULL, X86_EFL_NT },
|
---|
| 1864 | { "ov", "nv", X86_EFL_OF },
|
---|
| 1865 | { "dn", "up", X86_EFL_DF },
|
---|
| 1866 | { "ei", "di", X86_EFL_IF },
|
---|
| 1867 | { "tf", NULL, X86_EFL_TF },
|
---|
| 1868 | { "nt", "pl", X86_EFL_SF },
|
---|
| 1869 | { "nz", "zr", X86_EFL_ZF },
|
---|
| 1870 | { "ac", "na", X86_EFL_AF },
|
---|
| 1871 | { "po", "pe", X86_EFL_PF },
|
---|
| 1872 | { "cy", "nc", X86_EFL_CF },
|
---|
[1] | 1873 | };
|
---|
| 1874 | char szEFlags[80];
|
---|
| 1875 | char *psz = szEFlags;
|
---|
[72983] | 1876 | PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
|
---|
[97229] | 1877 | uint32_t fEFlags = pCtx->eflags.u;
|
---|
[39078] | 1878 | for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
|
---|
[1] | 1879 | {
|
---|
[97229] | 1880 | const char *pszAdd = s_aFlags[i].fFlag & fEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
|
---|
[1] | 1881 | if (pszAdd)
|
---|
| 1882 | {
|
---|
| 1883 | strcpy(psz, pszAdd);
|
---|
| 1884 | psz += strlen(pszAdd);
|
---|
| 1885 | *psz++ = ' ';
|
---|
| 1886 | }
|
---|
| 1887 | }
|
---|
| 1888 | psz[-1] = '\0';
|
---|
| 1889 |
|
---|
[80266] | 1890 | if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
|
---|
[10537] | 1891 | {
|
---|
[80266] | 1892 | /*
|
---|
| 1893 | * Format the registers.
|
---|
| 1894 | */
|
---|
| 1895 | if (CPUMIsGuestIn64BitCode(pVCpu))
|
---|
| 1896 | Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
|
---|
| 1897 | "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
|
---|
| 1898 | "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
|
---|
| 1899 | "r14=%016RX64 r15=%016RX64\n"
|
---|
| 1900 | "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
|
---|
| 1901 | "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1902 | "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1903 | "es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1904 | "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1905 | "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1906 | "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
|
---|
| 1907 | "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
|
---|
| 1908 | "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
|
---|
| 1909 | "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
|
---|
| 1910 | "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
|
---|
| 1911 | "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
| 1912 | "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
| 1913 | "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
|
---|
| 1914 | ,
|
---|
| 1915 | pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
|
---|
| 1916 | pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
|
---|
| 1917 | pCtx->r14, pCtx->r15,
|
---|
[97229] | 1918 | pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
|
---|
[80266] | 1919 | pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
|
---|
| 1920 | pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
|
---|
| 1921 | pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
|
---|
| 1922 | pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
|
---|
| 1923 | pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
|
---|
| 1924 | pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
|
---|
| 1925 | pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
|
---|
| 1926 | pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
|
---|
| 1927 | pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
|
---|
[97229] | 1928 | pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
|
---|
[80266] | 1929 | pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
|
---|
| 1930 | pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
|
---|
| 1931 | pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
|
---|
| 1932 | else
|
---|
| 1933 | Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
|
---|
| 1934 | "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
|
---|
| 1935 | "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
|
---|
| 1936 | "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
|
---|
| 1937 | "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
|
---|
| 1938 | "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
|
---|
| 1939 | "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
|
---|
| 1940 | "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
|
---|
| 1941 | "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
|
---|
| 1942 | "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
| 1943 | "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
|
---|
| 1944 | "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
|
---|
| 1945 | ,
|
---|
| 1946 | pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
|
---|
[97229] | 1947 | pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
|
---|
[80266] | 1948 | pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
|
---|
| 1949 | pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
|
---|
| 1950 | pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
|
---|
| 1951 | pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
|
---|
| 1952 | pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
|
---|
| 1953 | pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
|
---|
[97229] | 1954 | pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
|
---|
[80266] | 1955 | pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
|
---|
| 1956 | pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
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| 1957 | pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
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[10537] | 1958 | }
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[1] | 1959 |
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[80266] | 1960 | if (fFlags & HM_DUMP_REG_FLAGS_FPU)
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| 1961 | {
|
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[91281] | 1962 | PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
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[80266] | 1963 | Log(("FPU:\n"
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| 1964 | "FCW=%04x FSW=%04x FTW=%02x\n"
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| 1965 | "FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
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| 1966 | "FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
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| 1967 | ,
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| 1968 | pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
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| 1969 | pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
|
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| 1970 | pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
|
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| 1971 | pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
|
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| 1972 | NOREF(pFpuCtx);
|
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| 1973 | }
|
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[1] | 1974 |
|
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[80266] | 1975 | if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
|
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| 1976 | Log(("MSR:\n"
|
---|
| 1977 | "EFER =%016RX64\n"
|
---|
| 1978 | "PAT =%016RX64\n"
|
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| 1979 | "STAR =%016RX64\n"
|
---|
| 1980 | "CSTAR =%016RX64\n"
|
---|
| 1981 | "LSTAR =%016RX64\n"
|
---|
| 1982 | "SFMASK =%016RX64\n"
|
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| 1983 | "KERNELGSBASE =%016RX64\n",
|
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| 1984 | pCtx->msrEFER,
|
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| 1985 | pCtx->msrPAT,
|
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| 1986 | pCtx->msrSTAR,
|
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| 1987 | pCtx->msrCSTAR,
|
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| 1988 | pCtx->msrLSTAR,
|
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| 1989 | pCtx->msrSFMASK,
|
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| 1990 | pCtx->msrKERNELGSBASE));
|
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[1] | 1991 | }
|
---|
[80047] | 1992 |
|
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[12702] | 1993 | #endif /* VBOX_STRICT */
|
---|
[9407] | 1994 |
|
---|