VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp@ 101412

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1/* $Id: HMR0.cpp 101412 2023-10-11 07:01:45Z vboxsync $ */
2/** @file
3 * Hardware Assisted Virtualization Manager (HM) - Host Context Ring-0.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_HM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/hm.h>
35#include <VBox/vmm/pgm.h>
36#include "HMInternal.h"
37#include <VBox/vmm/vmcc.h>
38#include <VBox/vmm/hm_svm.h>
39#include <VBox/vmm/hmvmxinline.h>
40#include <VBox/err.h>
41#include <VBox/log.h>
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/asm-amd64-x86.h>
45#include <iprt/cpuset.h>
46#include <iprt/mem.h>
47#include <iprt/memobj.h>
48#include <iprt/once.h>
49#include <iprt/param.h>
50#include <iprt/power.h>
51#include <iprt/string.h>
52#include <iprt/thread.h>
53#include <iprt/x86.h>
54#include "HMVMXR0.h"
55#include "HMSVMR0.h"
56
57
58/*********************************************************************************************************************************
59* Internal Functions *
60*********************************************************************************************************************************/
61static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2);
62static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2);
63static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser);
64static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData);
65
66
67/*********************************************************************************************************************************
68* Structures and Typedefs *
69*********************************************************************************************************************************/
70/**
71 * This is used to manage the status code of a RTMpOnAll in HM.
72 */
73typedef struct HMR0FIRSTRC
74{
75 /** The status code. */
76 int32_t volatile rc;
77 /** The ID of the CPU reporting the first failure. */
78 RTCPUID volatile idCpu;
79} HMR0FIRSTRC;
80/** Pointer to a first return code structure. */
81typedef HMR0FIRSTRC *PHMR0FIRSTRC;
82
83/**
84 * Ring-0 method table for AMD-V and VT-x specific operations.
85 */
86typedef struct HMR0VTABLE
87{
88 DECLR0CALLBACKMEMBER(int, pfnEnterSession, (PVMCPUCC pVCpu));
89 DECLR0CALLBACKMEMBER(void, pfnThreadCtxCallback, (RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit));
90 DECLR0CALLBACKMEMBER(int, pfnAssertionCallback, (PVMCPUCC pVCpu));
91 DECLR0CALLBACKMEMBER(int, pfnExportHostState, (PVMCPUCC pVCpu));
92 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnRunGuestCode, (PVMCPUCC pVCpu));
93 DECLR0CALLBACKMEMBER(int, pfnEnableCpu, (PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
94 bool fEnabledByHost, PCSUPHWVIRTMSRS pHwvirtMsrs));
95 DECLR0CALLBACKMEMBER(int, pfnDisableCpu, (PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage));
96 DECLR0CALLBACKMEMBER(int, pfnInitVM, (PVMCC pVM));
97 DECLR0CALLBACKMEMBER(int, pfnTermVM, (PVMCC pVM));
98 DECLR0CALLBACKMEMBER(int, pfnSetupVM, (PVMCC pVM));
99} HMR0VTABLE;
100
101
102/*********************************************************************************************************************************
103* Global Variables *
104*********************************************************************************************************************************/
105/** The active ring-0 HM operations (copied from one of the table at init). */
106static HMR0VTABLE g_HmR0Ops;
107/** Indicates whether the host is suspending or not. We'll refuse a few
108 * actions when the host is being suspended to speed up the suspending and
109 * avoid trouble. */
110static bool volatile g_fHmSuspended;
111/** If set, VT-x/AMD-V is enabled globally at init time, otherwise it's
112 * enabled and disabled each time it's used to execute guest code. */
113static bool g_fHmGlobalInit;
114/** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
115uint32_t g_fHmHostKernelFeatures;
116/** Maximum allowed ASID/VPID (inclusive).
117 * @todo r=bird: This is exclusive for VT-x according to source code comment.
118 * Couldn't immediately find any docs on AMD-V, but suspect it is
119 * exclusive there as well given how hmR0SvmFlushTaggedTlb() use it. */
120uint32_t g_uHmMaxAsid;
121
122
123/** Set if VT-x (VMX) is supported by the CPU. */
124bool g_fHmVmxSupported = false;
125/** VMX: Whether we're using the preemption timer or not. */
126bool g_fHmVmxUsePreemptTimer;
127/** VMX: The shift mask employed by the VMX-Preemption timer. */
128uint8_t g_cHmVmxPreemptTimerShift;
129/** VMX: Set if swapping EFER is supported. */
130bool g_fHmVmxSupportsVmcsEfer = false;
131/** VMX: Whether we're using SUPR0EnableVTx or not. */
132static bool g_fHmVmxUsingSUPR0EnableVTx = false;
133/** VMX: Set if we've called SUPR0EnableVTx(true) and should disable it during
134 * module termination. */
135static bool g_fHmVmxCalledSUPR0EnableVTx = false;
136/** VMX: Host CR4 value (set by ring-0 VMX init) */
137uint64_t g_uHmVmxHostCr4;
138/** VMX: Host EFER value (set by ring-0 VMX init) */
139uint64_t g_uHmVmxHostMsrEfer;
140/** VMX: Host SMM monitor control (used for logging/diagnostics) */
141uint64_t g_uHmVmxHostSmmMonitorCtl;
142
143
144/** Set if AMD-V is supported by the CPU. */
145bool g_fHmSvmSupported = false;
146/** SVM revision. */
147uint32_t g_uHmSvmRev;
148/** SVM feature bits from cpuid 0x8000000a */
149uint32_t g_fHmSvmFeatures;
150
151
152/** MSRs. */
153SUPHWVIRTMSRS g_HmMsrs;
154
155/** Last recorded error code during HM ring-0 init. */
156static int32_t g_rcHmInit = VINF_SUCCESS;
157
158/** Per CPU globals. */
159static HMPHYSCPU g_aHmCpuInfo[RTCPUSET_MAX_CPUS];
160
161/** Whether we've already initialized all CPUs.
162 * @remarks We could check the EnableAllCpusOnce state, but this is
163 * simpler and hopefully easier to understand. */
164static bool g_fHmEnabled = false;
165/** Serialize initialization in HMR0EnableAllCpus. */
166static RTONCE g_HmEnableAllCpusOnce = RTONCE_INITIALIZER;
167
168
169/** HM ring-0 operations for VT-x. */
170static HMR0VTABLE const g_HmR0OpsVmx =
171{
172 /* .pfnEnterSession = */ VMXR0Enter,
173 /* .pfnThreadCtxCallback = */ VMXR0ThreadCtxCallback,
174 /* .pfnAssertionCallback = */ VMXR0AssertionCallback,
175 /* .pfnExportHostState = */ VMXR0ExportHostState,
176 /* .pfnRunGuestCode = */ VMXR0RunGuestCode,
177 /* .pfnEnableCpu = */ VMXR0EnableCpu,
178 /* .pfnDisableCpu = */ VMXR0DisableCpu,
179 /* .pfnInitVM = */ VMXR0InitVM,
180 /* .pfnTermVM = */ VMXR0TermVM,
181 /* .pfnSetupVM = */ VMXR0SetupVM,
182};
183
184/** HM ring-0 operations for AMD-V. */
185static HMR0VTABLE const g_HmR0OpsSvm =
186{
187 /* .pfnEnterSession = */ SVMR0Enter,
188 /* .pfnThreadCtxCallback = */ SVMR0ThreadCtxCallback,
189 /* .pfnAssertionCallback = */ SVMR0AssertionCallback,
190 /* .pfnExportHostState = */ SVMR0ExportHostState,
191 /* .pfnRunGuestCode = */ SVMR0RunGuestCode,
192 /* .pfnEnableCpu = */ SVMR0EnableCpu,
193 /* .pfnDisableCpu = */ SVMR0DisableCpu,
194 /* .pfnInitVM = */ SVMR0InitVM,
195 /* .pfnTermVM = */ SVMR0TermVM,
196 /* .pfnSetupVM = */ SVMR0SetupVM,
197};
198
199
200/** @name Dummy callback handlers for when neither VT-x nor AMD-V is supported.
201 * @{ */
202
203static DECLCALLBACK(int) hmR0DummyEnter(PVMCPUCC pVCpu)
204{
205 RT_NOREF(pVCpu);
206 return VINF_SUCCESS;
207}
208
209static DECLCALLBACK(void) hmR0DummyThreadCtxCallback(RTTHREADCTXEVENT enmEvent, PVMCPUCC pVCpu, bool fGlobalInit)
210{
211 RT_NOREF(enmEvent, pVCpu, fGlobalInit);
212}
213
214static DECLCALLBACK(int) hmR0DummyEnableCpu(PHMPHYSCPU pHostCpu, PVMCC pVM, void *pvCpuPage, RTHCPHYS HCPhysCpuPage,
215 bool fEnabledBySystem, PCSUPHWVIRTMSRS pHwvirtMsrs)
216{
217 RT_NOREF(pHostCpu, pVM, pvCpuPage, HCPhysCpuPage, fEnabledBySystem, pHwvirtMsrs);
218 return VINF_SUCCESS;
219}
220
221static DECLCALLBACK(int) hmR0DummyDisableCpu(PHMPHYSCPU pHostCpu, void *pvCpuPage, RTHCPHYS HCPhysCpuPage)
222{
223 RT_NOREF(pHostCpu, pvCpuPage, HCPhysCpuPage);
224 return VINF_SUCCESS;
225}
226
227static DECLCALLBACK(int) hmR0DummyInitVM(PVMCC pVM)
228{
229 RT_NOREF(pVM);
230 return VINF_SUCCESS;
231}
232
233static DECLCALLBACK(int) hmR0DummyTermVM(PVMCC pVM)
234{
235 RT_NOREF(pVM);
236 return VINF_SUCCESS;
237}
238
239static DECLCALLBACK(int) hmR0DummySetupVM(PVMCC pVM)
240{
241 RT_NOREF(pVM);
242 return VINF_SUCCESS;
243}
244
245static DECLCALLBACK(int) hmR0DummyAssertionCallback(PVMCPUCC pVCpu)
246{
247 RT_NOREF(pVCpu);
248 return VINF_SUCCESS;
249}
250
251static DECLCALLBACK(VBOXSTRICTRC) hmR0DummyRunGuestCode(PVMCPUCC pVCpu)
252{
253 RT_NOREF(pVCpu);
254 return VERR_NOT_SUPPORTED;
255}
256
257static DECLCALLBACK(int) hmR0DummyExportHostState(PVMCPUCC pVCpu)
258{
259 RT_NOREF(pVCpu);
260 return VINF_SUCCESS;
261}
262
263/** Dummy ops. */
264static HMR0VTABLE const g_HmR0OpsDummy =
265{
266 /* .pfnEnterSession = */ hmR0DummyEnter,
267 /* .pfnThreadCtxCallback = */ hmR0DummyThreadCtxCallback,
268 /* .pfnAssertionCallback = */ hmR0DummyAssertionCallback,
269 /* .pfnExportHostState = */ hmR0DummyExportHostState,
270 /* .pfnRunGuestCode = */ hmR0DummyRunGuestCode,
271 /* .pfnEnableCpu = */ hmR0DummyEnableCpu,
272 /* .pfnDisableCpu = */ hmR0DummyDisableCpu,
273 /* .pfnInitVM = */ hmR0DummyInitVM,
274 /* .pfnTermVM = */ hmR0DummyTermVM,
275 /* .pfnSetupVM = */ hmR0DummySetupVM,
276};
277
278/** @} */
279
280
281/**
282 * Initializes a first return code structure.
283 *
284 * @param pFirstRc The structure to init.
285 */
286static void hmR0FirstRcInit(PHMR0FIRSTRC pFirstRc)
287{
288 pFirstRc->rc = VINF_SUCCESS;
289 pFirstRc->idCpu = NIL_RTCPUID;
290}
291
292
293/**
294 * Try set the status code (success ignored).
295 *
296 * @param pFirstRc The first return code structure.
297 * @param rc The status code.
298 */
299static void hmR0FirstRcSetStatus(PHMR0FIRSTRC pFirstRc, int rc)
300{
301 if ( RT_FAILURE(rc)
302 && ASMAtomicCmpXchgS32(&pFirstRc->rc, rc, VINF_SUCCESS))
303 pFirstRc->idCpu = RTMpCpuId();
304}
305
306
307/**
308 * Get the status code of a first return code structure.
309 *
310 * @returns The status code; VINF_SUCCESS or error status, no informational or
311 * warning errors.
312 * @param pFirstRc The first return code structure.
313 */
314static int hmR0FirstRcGetStatus(PHMR0FIRSTRC pFirstRc)
315{
316 return pFirstRc->rc;
317}
318
319
320#ifdef VBOX_STRICT
321# ifndef DEBUG_bird
322/**
323 * Get the CPU ID on which the failure status code was reported.
324 *
325 * @returns The CPU ID, NIL_RTCPUID if no failure was reported.
326 * @param pFirstRc The first return code structure.
327 */
328static RTCPUID hmR0FirstRcGetCpuId(PHMR0FIRSTRC pFirstRc)
329{
330 return pFirstRc->idCpu;
331}
332# endif
333#endif /* VBOX_STRICT */
334
335
336/**
337 * Verify if VMX is really usable by entering and exiting VMX root mode.
338 *
339 * @returns VBox status code.
340 * @param uVmxBasicMsr The host's IA32_VMX_BASIC_MSR value.
341 */
342static int hmR0InitIntelVerifyVmxUsability(uint64_t uVmxBasicMsr)
343{
344 /* Allocate a temporary VMXON region. */
345 RTR0MEMOBJ hScatchMemObj;
346 int rc = RTR0MemObjAllocCont(&hScatchMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /* PhysHighest */, false /* fExecutable */);
347 if (RT_FAILURE(rc))
348 {
349 LogRelFunc(("RTR0MemObjAllocCont(,HOST_PAGE_SIZE,false) -> %Rrc\n", rc));
350 return rc;
351 }
352 void *pvScatchPage = RTR0MemObjAddress(hScatchMemObj);
353 RTHCPHYS const HCPhysScratchPage = RTR0MemObjGetPagePhysAddr(hScatchMemObj, 0);
354 RT_BZERO(pvScatchPage, HOST_PAGE_SIZE);
355
356 /* Set revision dword at the beginning of the VMXON structure. */
357 *(uint32_t *)pvScatchPage = RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_VMCS_ID);
358
359 /* Make sure we don't get rescheduled to another CPU during this probe. */
360 RTCCUINTREG const fEFlags = ASMIntDisableFlags();
361
362 /* Enable CR4.VMXE if it isn't already set. */
363 RTCCUINTREG const uOldCr4 = SUPR0ChangeCR4(X86_CR4_VMXE, RTCCUINTREG_MAX);
364
365 /*
366 * The only way of checking if we're in VMX root mode is to try and enter it.
367 * There is no instruction or control bit that tells us if we're in VMX root mode.
368 * Therefore, try and enter and exit VMX root mode.
369 */
370 rc = VMXEnable(HCPhysScratchPage);
371 if (RT_SUCCESS(rc))
372 VMXDisable();
373 else
374 {
375 /*
376 * KVM leaves the CPU in VMX root mode. Not only is this not allowed,
377 * it will crash the host when we enter raw mode, because:
378 *
379 * (a) clearing X86_CR4_VMXE in CR4 causes a #GP (we no longer modify
380 * this bit), and
381 * (b) turning off paging causes a #GP (unavoidable when switching
382 * from long to 32 bits mode or 32 bits to PAE).
383 *
384 * They should fix their code, but until they do we simply refuse to run.
385 */
386 rc = VERR_VMX_IN_VMX_ROOT_MODE;
387 }
388
389 /* Restore CR4.VMXE if it wasn't set prior to us setting it above. */
390 if (!(uOldCr4 & X86_CR4_VMXE))
391 SUPR0ChangeCR4(0 /* fOrMask */, ~(uint64_t)X86_CR4_VMXE);
392
393 /* Restore interrupts. */
394 ASMSetFlags(fEFlags);
395
396 RTR0MemObjFree(hScatchMemObj, false);
397
398 return rc;
399}
400
401
402/**
403 * Worker function used by hmR0PowerCallback() and HMR0Init() to initalize VT-x
404 * on a CPU.
405 *
406 * @param idCpu The identifier for the CPU the function is called on.
407 * @param pvUser1 Pointer to the first RC structure.
408 * @param pvUser2 Ignored.
409 */
410static DECLCALLBACK(void) hmR0InitIntelCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
411{
412 PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
413 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
414 Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
415 NOREF(idCpu); NOREF(pvUser2);
416
417 int rc = SUPR0GetVmxUsability(NULL /* pfIsSmxModeAmbiguous */);
418 hmR0FirstRcSetStatus(pFirstRc, rc);
419}
420
421
422/**
423 * Intel specific initialization code.
424 *
425 * @returns VBox status code (will only fail if out of memory).
426 */
427static int hmR0InitIntel(void)
428{
429 /* Read this MSR now as it may be useful for error reporting when initializing VT-x fails. */
430 g_HmMsrs.u.vmx.u64FeatCtrl = ASMRdMsr(MSR_IA32_FEATURE_CONTROL);
431
432 /*
433 * First try use native kernel API for controlling VT-x.
434 * (This is only supported by some Mac OS X kernels atm.)
435 */
436 int rc;
437 g_rcHmInit = rc = SUPR0EnableVTx(true /* fEnable */);
438 g_fHmVmxUsingSUPR0EnableVTx = rc != VERR_NOT_SUPPORTED;
439 if (g_fHmVmxUsingSUPR0EnableVTx)
440 {
441 AssertLogRelMsg(rc == VINF_SUCCESS || rc == VERR_VMX_IN_VMX_ROOT_MODE || rc == VERR_VMX_NO_VMX, ("%Rrc\n", rc));
442 if (RT_SUCCESS(rc))
443 {
444 g_fHmVmxSupported = true;
445 rc = SUPR0EnableVTx(false /* fEnable */);
446 AssertLogRelRC(rc);
447 rc = VINF_SUCCESS;
448 }
449 }
450 else
451 {
452 HMR0FIRSTRC FirstRc;
453 hmR0FirstRcInit(&FirstRc);
454 g_rcHmInit = rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
455 if (RT_SUCCESS(rc))
456 g_rcHmInit = rc = hmR0FirstRcGetStatus(&FirstRc);
457 }
458
459 if (RT_SUCCESS(rc))
460 {
461 /* Read CR4 and EFER for logging/diagnostic purposes. */
462 g_uHmVmxHostCr4 = ASMGetCR4();
463 g_uHmVmxHostMsrEfer = ASMRdMsr(MSR_K6_EFER);
464
465 /* Get VMX MSRs (and feature control MSR) for determining VMX features we can ultimately use. */
466 SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_VT_X, false /* fForce */);
467
468 /*
469 * Nested KVM workaround: Intel SDM section 34.15.5 describes that
470 * MSR_IA32_SMM_MONITOR_CTL depends on bit 49 of MSR_IA32_VMX_BASIC while
471 * table 35-2 says that this MSR is available if either VMX or SMX is supported.
472 */
473 uint64_t const uVmxBasicMsr = g_HmMsrs.u.vmx.u64Basic;
474 if (RT_BF_GET(uVmxBasicMsr, VMX_BF_BASIC_DUAL_MON))
475 g_uHmVmxHostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
476
477 /* Initialize VPID - 16 bits ASID. */
478 g_uHmMaxAsid = 0x10000; /* exclusive */
479
480 /*
481 * If the host OS has not enabled VT-x for us, try enter VMX root mode
482 * to really verify if VT-x is usable.
483 */
484 if (!g_fHmVmxUsingSUPR0EnableVTx)
485 {
486 /*
487 * We don't verify VMX root mode on all CPUs here because the verify
488 * function exits VMX root mode thus potentially allowing other
489 * programs to grab VT-x. Our global init's entering and staying in
490 * VMX root mode (until our module termination) is done later when
491 * the first VM powers up (after module initialization) using
492 * VMMR0_DO_HM_ENABLE which calls HMR0EnableAllCpus().
493 *
494 * This is just a quick sanity check.
495 */
496 rc = hmR0InitIntelVerifyVmxUsability(uVmxBasicMsr);
497 if (RT_SUCCESS(rc))
498 g_fHmVmxSupported = true;
499 else
500 {
501 g_rcHmInit = rc;
502 Assert(g_fHmVmxSupported == false);
503 }
504 }
505
506 if (g_fHmVmxSupported)
507 {
508 rc = VMXR0GlobalInit();
509 if (RT_SUCCESS(rc))
510 {
511 /*
512 * Install the VT-x methods.
513 */
514 g_HmR0Ops = g_HmR0OpsVmx;
515
516 /*
517 * Check for the VMX-Preemption Timer and adjust for the "VMX-Preemption
518 * Timer Does Not Count Down at the Rate Specified" CPU erratum.
519 */
520 if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
521 {
522 g_fHmVmxUsePreemptTimer = true;
523 g_cHmVmxPreemptTimerShift = RT_BF_GET(g_HmMsrs.u.vmx.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
524 if (HMIsSubjectToVmxPreemptTimerErratum())
525 g_cHmVmxPreemptTimerShift = 0; /* This is about right most of the time here. */
526 }
527 else
528 g_fHmVmxUsePreemptTimer = false;
529
530 /*
531 * Check for EFER swapping support.
532 */
533 g_fHmVmxSupportsVmcsEfer = (g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
534 && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
535 && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR);
536 }
537 else
538 {
539 g_rcHmInit = rc;
540 g_fHmVmxSupported = false;
541 }
542 }
543 }
544#ifdef LOG_ENABLED
545 else
546 SUPR0Printf("hmR0InitIntelCpu failed with rc=%Rrc\n", g_rcHmInit);
547#endif
548 return VINF_SUCCESS;
549}
550
551
552/**
553 * Worker function used by hmR0PowerCallback() and HMR0Init() to initalize AMD-V
554 * on a CPU.
555 *
556 * @param idCpu The identifier for the CPU the function is called on.
557 * @param pvUser1 Pointer to the first RC structure.
558 * @param pvUser2 Ignored.
559 */
560static DECLCALLBACK(void) hmR0InitAmdCpu(RTCPUID idCpu, void *pvUser1, void *pvUser2)
561{
562 PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser1;
563 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
564 Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
565 NOREF(idCpu); NOREF(pvUser2);
566
567 int rc = SUPR0GetSvmUsability(true /* fInitSvm */);
568 hmR0FirstRcSetStatus(pFirstRc, rc);
569}
570
571
572/**
573 * AMD-specific initialization code.
574 *
575 * @returns VBox status code (will only fail if out of memory).
576 */
577static int hmR0InitAmd(void)
578{
579 /* Call the global AMD-V initialization routine (should only fail in out-of-memory situations). */
580 int rc = SVMR0GlobalInit();
581 if (RT_SUCCESS(rc))
582 {
583 /*
584 * Install the AMD-V methods.
585 */
586 g_HmR0Ops = g_HmR0OpsSvm;
587
588 /* Query AMD features. */
589 uint32_t u32Dummy;
590 ASMCpuId(0x8000000a, &g_uHmSvmRev, &g_uHmMaxAsid, &u32Dummy, &g_fHmSvmFeatures);
591
592 /*
593 * We need to check if AMD-V has been properly initialized on all CPUs.
594 * Some BIOSes might do a poor job.
595 */
596 HMR0FIRSTRC FirstRc;
597 hmR0FirstRcInit(&FirstRc);
598 rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
599 AssertRC(rc);
600 if (RT_SUCCESS(rc))
601 rc = hmR0FirstRcGetStatus(&FirstRc);
602#ifndef DEBUG_bird
603 AssertMsg(rc == VINF_SUCCESS || rc == VERR_SVM_IN_USE,
604 ("hmR0InitAmdCpu failed for cpu %d with rc=%Rrc\n", hmR0FirstRcGetCpuId(&FirstRc), rc));
605#endif
606 if (RT_SUCCESS(rc))
607 {
608 SUPR0GetHwvirtMsrs(&g_HmMsrs, SUPVTCAPS_AMD_V, false /* fForce */);
609 g_fHmSvmSupported = true;
610 }
611 else
612 {
613 g_rcHmInit = rc;
614 if (rc == VERR_SVM_DISABLED || rc == VERR_SVM_IN_USE)
615 rc = VINF_SUCCESS; /* Don't fail if AMD-V is disabled or in use. */
616 }
617 }
618 else
619 g_rcHmInit = rc;
620 return rc;
621}
622
623
624/**
625 * Does global Ring-0 HM initialization (at module init).
626 *
627 * @returns VBox status code.
628 */
629VMMR0_INT_DECL(int) HMR0Init(void)
630{
631 /*
632 * Initialize the globals.
633 */
634 g_fHmEnabled = false;
635 for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
636 {
637 g_aHmCpuInfo[i].idCpu = NIL_RTCPUID;
638 g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
639 g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
640 g_aHmCpuInfo[i].pvMemObj = NULL;
641#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
642 g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
643 g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
644 g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
645#endif
646 }
647
648 /* Fill in all callbacks with placeholders. */
649 g_HmR0Ops = g_HmR0OpsDummy;
650
651 /* Default is global VT-x/AMD-V init. */
652 g_fHmGlobalInit = true;
653
654 g_fHmVmxSupported = false;
655 g_fHmSvmSupported = false;
656 g_uHmMaxAsid = 0;
657
658 /*
659 * Get host kernel features that HM might need to know in order
660 * to co-operate and function properly with the host OS (e.g. SMAP).
661 */
662 g_fHmHostKernelFeatures = SUPR0GetKernelFeatures();
663
664 /*
665 * Make sure aCpuInfo is big enough for all the CPUs on this system.
666 */
667 if (RTMpGetArraySize() > RT_ELEMENTS(g_aHmCpuInfo))
668 {
669 LogRel(("HM: Too many real CPUs/cores/threads - %u, max %u\n", RTMpGetArraySize(), RT_ELEMENTS(g_aHmCpuInfo)));
670 return VERR_TOO_MANY_CPUS;
671 }
672
673 /*
674 * Check for VT-x or AMD-V support.
675 * Return failure only in out-of-memory situations.
676 */
677 uint32_t fCaps = 0;
678 int rc = SUPR0GetVTSupport(&fCaps);
679 if (RT_SUCCESS(rc))
680 {
681 if (fCaps & SUPVTCAPS_VT_X)
682 rc = hmR0InitIntel();
683 else
684 {
685 Assert(fCaps & SUPVTCAPS_AMD_V);
686 rc = hmR0InitAmd();
687 }
688 if (RT_SUCCESS(rc))
689 {
690 /*
691 * Register notification callbacks that we can use to disable/enable CPUs
692 * when brought offline/online or suspending/resuming.
693 */
694 if (!g_fHmVmxUsingSUPR0EnableVTx)
695 {
696 rc = RTMpNotificationRegister(hmR0MpEventCallback, NULL);
697 if (RT_SUCCESS(rc))
698 {
699 rc = RTPowerNotificationRegister(hmR0PowerCallback, NULL);
700 if (RT_FAILURE(rc))
701 RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
702 }
703 if (RT_FAILURE(rc))
704 {
705 /* There shouldn't be any per-cpu allocations at this point,
706 so just have to call SVMR0GlobalTerm and VMXR0GlobalTerm. */
707 if (fCaps & SUPVTCAPS_VT_X)
708 VMXR0GlobalTerm();
709 else
710 SVMR0GlobalTerm();
711 g_HmR0Ops = g_HmR0OpsDummy;
712 g_rcHmInit = rc;
713 g_fHmSvmSupported = false;
714 g_fHmVmxSupported = false;
715 }
716 }
717 }
718 }
719 else
720 {
721 g_rcHmInit = rc;
722 rc = VINF_SUCCESS; /* We return success here because module init shall not fail if HM fails to initialize. */
723 }
724 return rc;
725}
726
727
728/**
729 * Does global Ring-0 HM termination (at module termination).
730 *
731 * @returns VBox status code (ignored).
732 */
733VMMR0_INT_DECL(int) HMR0Term(void)
734{
735 int rc;
736 if ( g_fHmVmxSupported
737 && g_fHmVmxUsingSUPR0EnableVTx)
738 {
739 /*
740 * Simple if the host OS manages VT-x.
741 */
742 Assert(g_fHmGlobalInit);
743
744 if (g_fHmVmxCalledSUPR0EnableVTx)
745 {
746 rc = SUPR0EnableVTx(false /* fEnable */);
747 g_fHmVmxCalledSUPR0EnableVTx = false;
748 }
749 else
750 rc = VINF_SUCCESS;
751
752 for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_aHmCpuInfo); iCpu++)
753 {
754 g_aHmCpuInfo[iCpu].fConfigured = false;
755 Assert(g_aHmCpuInfo[iCpu].hMemObj == NIL_RTR0MEMOBJ);
756 }
757 }
758 else
759 {
760 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
761
762 /* Doesn't really matter if this fails. */
763 RTMpNotificationDeregister(hmR0MpEventCallback, NULL);
764 RTPowerNotificationDeregister(hmR0PowerCallback, NULL);
765 rc = VINF_SUCCESS;
766
767 /*
768 * Disable VT-x/AMD-V on all CPUs if we enabled it before.
769 */
770 if (g_fHmGlobalInit)
771 {
772 HMR0FIRSTRC FirstRc;
773 hmR0FirstRcInit(&FirstRc);
774 rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
775 Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
776 if (RT_SUCCESS(rc))
777 rc = hmR0FirstRcGetStatus(&FirstRc);
778 }
779
780 /*
781 * Free the per-cpu pages used for VT-x and AMD-V.
782 */
783 for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
784 {
785 if (g_aHmCpuInfo[i].hMemObj != NIL_RTR0MEMOBJ)
786 {
787 RTR0MemObjFree(g_aHmCpuInfo[i].hMemObj, false);
788 g_aHmCpuInfo[i].hMemObj = NIL_RTR0MEMOBJ;
789 g_aHmCpuInfo[i].HCPhysMemObj = NIL_RTHCPHYS;
790 g_aHmCpuInfo[i].pvMemObj = NULL;
791 }
792#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
793 if (g_aHmCpuInfo[i].n.svm.hNstGstMsrpm != NIL_RTR0MEMOBJ)
794 {
795 RTR0MemObjFree(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, false);
796 g_aHmCpuInfo[i].n.svm.hNstGstMsrpm = NIL_RTR0MEMOBJ;
797 g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = NIL_RTHCPHYS;
798 g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = NULL;
799 }
800#endif
801 }
802 }
803
804 /** @todo This needs cleaning up. There's no matching
805 * hmR0TermIntel()/hmR0TermAmd() and all the VT-x/AMD-V specific bits
806 * should move into their respective modules. */
807 /* Finally, call global VT-x/AMD-V termination. */
808 if (g_fHmVmxSupported)
809 VMXR0GlobalTerm();
810 else if (g_fHmSvmSupported)
811 SVMR0GlobalTerm();
812
813 return rc;
814}
815
816
817/**
818 * Enable VT-x or AMD-V on the current CPU
819 *
820 * @returns VBox status code.
821 * @param pVM The cross context VM structure. Can be NULL.
822 * @param idCpu The identifier for the CPU the function is called on.
823 *
824 * @remarks Maybe called with interrupts disabled!
825 */
826static int hmR0EnableCpu(PVMCC pVM, RTCPUID idCpu)
827{
828 PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
829
830 Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
831 Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
832 Assert(!pHostCpu->fConfigured);
833 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
834
835 pHostCpu->idCpu = idCpu;
836 /* Do NOT reset cTlbFlushes here, see @bugref{6255}. */
837
838 int rc;
839 if ( g_fHmVmxSupported
840 && g_fHmVmxUsingSUPR0EnableVTx)
841 rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, NULL /* pvCpuPage */, NIL_RTHCPHYS, true, &g_HmMsrs);
842 else
843 {
844 AssertLogRelMsgReturn(pHostCpu->hMemObj != NIL_RTR0MEMOBJ, ("hmR0EnableCpu failed idCpu=%u.\n", idCpu), VERR_HM_IPE_1);
845 rc = g_HmR0Ops.pfnEnableCpu(pHostCpu, pVM, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj, false, &g_HmMsrs);
846 }
847 if (RT_SUCCESS(rc))
848 pHostCpu->fConfigured = true;
849 return rc;
850}
851
852
853/**
854 * Worker function passed to RTMpOnAll() that is to be called on all CPUs.
855 *
856 * @param idCpu The identifier for the CPU the function is called on.
857 * @param pvUser1 Opaque pointer to the VM (can be NULL!).
858 * @param pvUser2 The 2nd user argument.
859 */
860static DECLCALLBACK(void) hmR0EnableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
861{
862 PVMCC pVM = (PVMCC)pvUser1; /* can be NULL! */
863 PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2;
864 AssertReturnVoid(g_fHmGlobalInit);
865 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
866 hmR0FirstRcSetStatus(pFirstRc, hmR0EnableCpu(pVM, idCpu));
867}
868
869
870/**
871 * RTOnce callback employed by HMR0EnableAllCpus.
872 *
873 * @returns VBox status code.
874 * @param pvUser Pointer to the VM.
875 */
876static DECLCALLBACK(int32_t) hmR0EnableAllCpuOnce(void *pvUser)
877{
878 PVMCC pVM = (PVMCC)pvUser;
879
880 /*
881 * Indicate that we've initialized.
882 *
883 * Note! There is a potential race between this function and the suspend
884 * notification. Kind of unlikely though, so ignored for now.
885 */
886 AssertReturn(!g_fHmEnabled, VERR_HM_ALREADY_ENABLED_IPE);
887 ASMAtomicWriteBool(&g_fHmEnabled, true);
888
889 /*
890 * The global init variable is set by the first VM.
891 */
892 g_fHmGlobalInit = pVM->hm.s.fGlobalInit;
893
894#ifdef VBOX_STRICT
895 for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
896 {
897 Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
898 Assert(g_aHmCpuInfo[i].HCPhysMemObj == NIL_RTHCPHYS);
899 Assert(g_aHmCpuInfo[i].pvMemObj == NULL);
900 Assert(!g_aHmCpuInfo[i].fConfigured);
901 Assert(!g_aHmCpuInfo[i].cTlbFlushes);
902 Assert(!g_aHmCpuInfo[i].uCurrentAsid);
903# ifdef VBOX_WITH_NESTED_HWVIRT_SVM
904 Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
905 Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm == NIL_RTHCPHYS);
906 Assert(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm == NULL);
907# endif
908 }
909#endif
910
911 int rc;
912 if ( g_fHmVmxSupported
913 && g_fHmVmxUsingSUPR0EnableVTx)
914 {
915 /*
916 * Global VT-x initialization API (only darwin for now).
917 */
918 rc = SUPR0EnableVTx(true /* fEnable */);
919 if (RT_SUCCESS(rc))
920 {
921 g_fHmVmxCalledSUPR0EnableVTx = true;
922 /* If the host provides a VT-x init API, then we'll rely on that for global init. */
923 g_fHmGlobalInit = pVM->hm.s.fGlobalInit = true;
924 }
925 else
926 AssertMsgFailed(("hmR0EnableAllCpuOnce/SUPR0EnableVTx: rc=%Rrc\n", rc));
927 }
928 else
929 {
930 /*
931 * We're doing the job ourselves.
932 */
933 /* Allocate one page per cpu for the global VT-x and AMD-V pages */
934 for (unsigned i = 0; i < RT_ELEMENTS(g_aHmCpuInfo); i++)
935 {
936 Assert(g_aHmCpuInfo[i].hMemObj == NIL_RTR0MEMOBJ);
937#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
938 Assert(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm == NIL_RTR0MEMOBJ);
939#endif
940 if (RTMpIsCpuPossible(RTMpCpuIdFromSetIndex(i)))
941 {
942 /** @todo NUMA */
943 rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].hMemObj, HOST_PAGE_SIZE, NIL_RTHCPHYS /*PhysHighest*/, false /* executable R0 mapping */);
944 AssertLogRelRCReturn(rc, rc);
945
946 g_aHmCpuInfo[i].HCPhysMemObj = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].hMemObj, 0);
947 Assert(g_aHmCpuInfo[i].HCPhysMemObj != NIL_RTHCPHYS);
948 Assert(!(g_aHmCpuInfo[i].HCPhysMemObj & HOST_PAGE_OFFSET_MASK));
949
950 g_aHmCpuInfo[i].pvMemObj = RTR0MemObjAddress(g_aHmCpuInfo[i].hMemObj);
951 AssertPtr(g_aHmCpuInfo[i].pvMemObj);
952 RT_BZERO(g_aHmCpuInfo[i].pvMemObj, HOST_PAGE_SIZE);
953
954#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
955 rc = RTR0MemObjAllocCont(&g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT,
956 NIL_RTHCPHYS /*PhysHighest*/, false /* executable R0 mapping */);
957 AssertLogRelRCReturn(rc, rc);
958
959 g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm = RTR0MemObjGetPagePhysAddr(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm, 0);
960 Assert(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm != NIL_RTHCPHYS);
961 Assert(!(g_aHmCpuInfo[i].n.svm.HCPhysNstGstMsrpm & HOST_PAGE_OFFSET_MASK));
962
963 g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm = RTR0MemObjAddress(g_aHmCpuInfo[i].n.svm.hNstGstMsrpm);
964 AssertPtr(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm);
965 ASMMemFill32(g_aHmCpuInfo[i].n.svm.pvNstGstMsrpm, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT, UINT32_C(0xffffffff));
966#endif
967 }
968 }
969
970 rc = VINF_SUCCESS;
971 }
972
973 if ( RT_SUCCESS(rc)
974 && g_fHmGlobalInit)
975 {
976 /*
977 * It's possible we end up here with VMX (and perhaps SVM) not supported, see @bugref{9918}.
978 * In that case, our HMR0 function table contains the dummy placeholder functions which pretend
979 * success. However, we must not pretend success any longer (like we did during HMR0Init called
980 * during VMMR0 module init) as the HM init error code (g_rcHmInit) should be propagated to
981 * ring-3 especially since we now have a VM instance.
982 */
983 if ( !g_fHmVmxSupported
984 && !g_fHmSvmSupported)
985 {
986 Assert(g_HmR0Ops.pfnEnableCpu == hmR0DummyEnableCpu);
987 Assert(RT_FAILURE(g_rcHmInit));
988 rc = g_rcHmInit;
989 }
990 else
991 {
992 /* First time, so initialize each cpu/core. */
993 HMR0FIRSTRC FirstRc;
994 hmR0FirstRcInit(&FirstRc);
995 Assert(g_HmR0Ops.pfnEnableCpu != hmR0DummyEnableCpu);
996 rc = RTMpOnAll(hmR0EnableCpuCallback, (void *)pVM, &FirstRc);
997 if (RT_SUCCESS(rc))
998 rc = hmR0FirstRcGetStatus(&FirstRc);
999 }
1000 }
1001
1002 return rc;
1003}
1004
1005
1006/**
1007 * Sets up HM on all cpus.
1008 *
1009 * @returns VBox status code.
1010 * @param pVM The cross context VM structure.
1011 */
1012VMMR0_INT_DECL(int) HMR0EnableAllCpus(PVMCC pVM)
1013{
1014 /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1015 if (ASMAtomicReadBool(&g_fHmSuspended))
1016 return VERR_HM_SUSPEND_PENDING;
1017
1018 return RTOnce(&g_HmEnableAllCpusOnce, hmR0EnableAllCpuOnce, pVM);
1019}
1020
1021
1022/**
1023 * Disable VT-x or AMD-V on the current CPU.
1024 *
1025 * @returns VBox status code.
1026 * @param idCpu The identifier for the CPU this function is called on.
1027 *
1028 * @remarks Must be called with preemption disabled.
1029 */
1030static int hmR0DisableCpu(RTCPUID idCpu)
1031{
1032 PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1033
1034 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
1035 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1036 Assert(idCpu == (RTCPUID)RTMpCpuIdToSetIndex(idCpu)); /** @todo fix idCpu == index assumption (rainy day) */
1037 Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
1038 Assert(!pHostCpu->fConfigured || pHostCpu->hMemObj != NIL_RTR0MEMOBJ);
1039 AssertRelease(idCpu == RTMpCpuId());
1040
1041 if (pHostCpu->hMemObj == NIL_RTR0MEMOBJ)
1042 return pHostCpu->fConfigured ? VERR_NO_MEMORY : VINF_SUCCESS /* not initialized. */;
1043 AssertPtr(pHostCpu->pvMemObj);
1044 Assert(pHostCpu->HCPhysMemObj != NIL_RTHCPHYS);
1045
1046 int rc;
1047 if (pHostCpu->fConfigured)
1048 {
1049 rc = g_HmR0Ops.pfnDisableCpu(pHostCpu, pHostCpu->pvMemObj, pHostCpu->HCPhysMemObj);
1050 AssertRCReturn(rc, rc);
1051
1052 pHostCpu->fConfigured = false;
1053 pHostCpu->idCpu = NIL_RTCPUID;
1054 }
1055 else
1056 rc = VINF_SUCCESS; /* nothing to do */
1057 return rc;
1058}
1059
1060
1061/**
1062 * Worker function passed to RTMpOnAll() that is to be called on the target
1063 * CPUs.
1064 *
1065 * @param idCpu The identifier for the CPU the function is called on.
1066 * @param pvUser1 The 1st user argument.
1067 * @param pvUser2 Opaque pointer to the FirstRc.
1068 */
1069static DECLCALLBACK(void) hmR0DisableCpuCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
1070{
1071 PHMR0FIRSTRC pFirstRc = (PHMR0FIRSTRC)pvUser2; NOREF(pvUser1);
1072 AssertReturnVoid(g_fHmGlobalInit);
1073 hmR0FirstRcSetStatus(pFirstRc, hmR0DisableCpu(idCpu));
1074}
1075
1076
1077/**
1078 * Worker function passed to RTMpOnSpecific() that is to be called on the target
1079 * CPU.
1080 *
1081 * @param idCpu The identifier for the CPU the function is called on.
1082 * @param pvUser1 Null, not used.
1083 * @param pvUser2 Null, not used.
1084 */
1085static DECLCALLBACK(void) hmR0DisableCpuOnSpecificCallback(RTCPUID idCpu, void *pvUser1, void *pvUser2)
1086{
1087 NOREF(pvUser1);
1088 NOREF(pvUser2);
1089 hmR0DisableCpu(idCpu);
1090}
1091
1092
1093/**
1094 * Callback function invoked when a cpu goes online or offline.
1095 *
1096 * @param enmEvent The Mp event.
1097 * @param idCpu The identifier for the CPU the function is called on.
1098 * @param pvData Opaque data (PVMCC pointer).
1099 */
1100static DECLCALLBACK(void) hmR0MpEventCallback(RTMPEVENT enmEvent, RTCPUID idCpu, void *pvData)
1101{
1102 NOREF(pvData);
1103 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
1104
1105 /*
1106 * We only care about uninitializing a CPU that is going offline. When a
1107 * CPU comes online, the initialization is done lazily in HMR0Enter().
1108 */
1109 switch (enmEvent)
1110 {
1111 case RTMPEVENT_OFFLINE:
1112 {
1113 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1114 RTThreadPreemptDisable(&PreemptState);
1115 if (idCpu == RTMpCpuId())
1116 {
1117 int rc = hmR0DisableCpu(idCpu);
1118 AssertRC(rc);
1119 RTThreadPreemptRestore(&PreemptState);
1120 }
1121 else
1122 {
1123 RTThreadPreemptRestore(&PreemptState);
1124 RTMpOnSpecific(idCpu, hmR0DisableCpuOnSpecificCallback, NULL /* pvUser1 */, NULL /* pvUser2 */);
1125 }
1126 break;
1127 }
1128
1129 default:
1130 break;
1131 }
1132}
1133
1134
1135/**
1136 * Called whenever a system power state change occurs.
1137 *
1138 * @param enmEvent The Power event.
1139 * @param pvUser User argument.
1140 */
1141static DECLCALLBACK(void) hmR0PowerCallback(RTPOWEREVENT enmEvent, void *pvUser)
1142{
1143 NOREF(pvUser);
1144 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
1145
1146#ifdef LOG_ENABLED
1147 if (enmEvent == RTPOWEREVENT_SUSPEND)
1148 SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_SUSPEND\n");
1149 else
1150 SUPR0Printf("hmR0PowerCallback RTPOWEREVENT_RESUME\n");
1151#endif
1152
1153 if (enmEvent == RTPOWEREVENT_SUSPEND)
1154 ASMAtomicWriteBool(&g_fHmSuspended, true);
1155
1156 if (g_fHmEnabled)
1157 {
1158 int rc;
1159 HMR0FIRSTRC FirstRc;
1160 hmR0FirstRcInit(&FirstRc);
1161
1162 if (enmEvent == RTPOWEREVENT_SUSPEND)
1163 {
1164 if (g_fHmGlobalInit)
1165 {
1166 /* Turn off VT-x or AMD-V on all CPUs. */
1167 rc = RTMpOnAll(hmR0DisableCpuCallback, NULL /* pvUser 1 */, &FirstRc);
1168 Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
1169 }
1170 /* else nothing to do here for the local init case */
1171 }
1172 else
1173 {
1174 /* Reinit the CPUs from scratch as the suspend state might have
1175 messed with the MSRs. (lousy BIOSes as usual) */
1176 if (g_fHmVmxSupported)
1177 rc = RTMpOnAll(hmR0InitIntelCpu, &FirstRc, NULL);
1178 else
1179 rc = RTMpOnAll(hmR0InitAmdCpu, &FirstRc, NULL);
1180 Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
1181 if (RT_SUCCESS(rc))
1182 rc = hmR0FirstRcGetStatus(&FirstRc);
1183#ifdef LOG_ENABLED
1184 if (RT_FAILURE(rc))
1185 SUPR0Printf("hmR0PowerCallback hmR0InitXxxCpu failed with %Rc\n", rc);
1186#endif
1187 if (g_fHmGlobalInit)
1188 {
1189 /* Turn VT-x or AMD-V back on on all CPUs. */
1190 rc = RTMpOnAll(hmR0EnableCpuCallback, NULL /* pVM */, &FirstRc /* output ignored */);
1191 Assert(RT_SUCCESS(rc) || rc == VERR_NOT_SUPPORTED);
1192 }
1193 /* else nothing to do here for the local init case */
1194 }
1195 }
1196
1197 if (enmEvent == RTPOWEREVENT_RESUME)
1198 ASMAtomicWriteBool(&g_fHmSuspended, false);
1199}
1200
1201
1202/**
1203 * Does ring-0 per-VM HM initialization.
1204 *
1205 * This will call the CPU specific init. routine which may initialize and allocate
1206 * resources for virtual CPUs.
1207 *
1208 * @returns VBox status code.
1209 * @param pVM The cross context VM structure.
1210 *
1211 * @remarks This is called after HMR3Init(), see vmR3CreateU() and
1212 * vmR3InitRing3().
1213 */
1214VMMR0_INT_DECL(int) HMR0InitVM(PVMCC pVM)
1215{
1216 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
1217 AssertCompile(sizeof(pVM->hmr0.s) <= sizeof(pVM->hmr0.padding));
1218 AssertCompile(sizeof(pVM->aCpus[0].hm.s) <= sizeof(pVM->aCpus[0].hm.padding));
1219 AssertCompile(sizeof(pVM->aCpus[0].hmr0.s) <= sizeof(pVM->aCpus[0].hmr0.padding));
1220 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1221
1222 /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1223 if (ASMAtomicReadBool(&g_fHmSuspended))
1224 return VERR_HM_SUSPEND_PENDING;
1225
1226 /*
1227 * Copy globals to the VM structure.
1228 */
1229 Assert(!(pVM->hm.s.vmx.fSupported && pVM->hm.s.svm.fSupported));
1230 if (pVM->hm.s.vmx.fSupported)
1231 {
1232 pVM->hmr0.s.vmx.fUsePreemptTimer = pVM->hm.s.vmx.fUsePreemptTimerCfg && g_fHmVmxUsePreemptTimer;
1233 pVM->hm.s.vmx.fUsePreemptTimerCfg = pVM->hmr0.s.vmx.fUsePreemptTimer;
1234 pVM->hm.s.vmx.cPreemptTimerShift = g_cHmVmxPreemptTimerShift;
1235 pVM->hm.s.ForR3.vmx.u64HostCr4 = g_uHmVmxHostCr4;
1236 pVM->hm.s.ForR3.vmx.u64HostMsrEfer = g_uHmVmxHostMsrEfer;
1237 pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl = g_uHmVmxHostSmmMonitorCtl;
1238 pVM->hm.s.ForR3.vmx.u64HostFeatCtrl = g_HmMsrs.u.vmx.u64FeatCtrl;
1239 HMGetVmxMsrsFromHwvirtMsrs(&g_HmMsrs, &pVM->hm.s.ForR3.vmx.Msrs);
1240 /* If you need to tweak host MSRs for testing VMX R0 code, do it here. */
1241
1242 /* Enable VPID if supported and configured. */
1243 if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1244 pVM->hm.s.ForR3.vmx.fVpid = pVM->hmr0.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid; /* Can be overridden by CFGM in HMR3Init(). */
1245
1246 /* Use VMCS shadowing if supported. */
1247 pVM->hmr0.s.vmx.fUseVmcsShadowing = pVM->cpum.ro.GuestFeatures.fVmx
1248 && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1249 pVM->hm.s.ForR3.vmx.fUseVmcsShadowing = pVM->hmr0.s.vmx.fUseVmcsShadowing;
1250
1251 /* Use the VMCS controls for swapping the EFER MSR if supported. */
1252 pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer = g_fHmVmxSupportsVmcsEfer;
1253
1254#if 0
1255 /* Enable APIC register virtualization and virtual-interrupt delivery if supported. */
1256 if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1257 && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1258 pVM->hm.s.fVirtApicRegs = true;
1259
1260 /* Enable posted-interrupt processing if supported. */
1261 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1262 * here. */
1263 if ( (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1264 && (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1265 pVM->hm.s.fPostedIntrs = true;
1266#endif
1267 }
1268 else if (pVM->hm.s.svm.fSupported)
1269 {
1270 pVM->hm.s.ForR3.svm.u32Rev = g_uHmSvmRev;
1271 pVM->hm.s.ForR3.svm.fFeatures = g_fHmSvmFeatures;
1272 pVM->hm.s.ForR3.svm.u64MsrHwcr = g_HmMsrs.u.svm.u64MsrHwcr;
1273 /* If you need to tweak host MSRs for testing SVM R0 code, do it here. */
1274 }
1275 pVM->hm.s.ForR3.rcInit = g_rcHmInit;
1276 pVM->hm.s.ForR3.uMaxAsid = g_uHmMaxAsid;
1277
1278 /*
1279 * Set default maximum inner loops in ring-0 before returning to ring-3.
1280 * Can be overriden using CFGM.
1281 */
1282 uint32_t cMaxResumeLoops = pVM->hm.s.cMaxResumeLoopsCfg;
1283 if (!cMaxResumeLoops)
1284 {
1285 cMaxResumeLoops = 1024;
1286 if (RTThreadPreemptIsPendingTrusty())
1287 cMaxResumeLoops = 8192;
1288 }
1289 else if (cMaxResumeLoops > 16384)
1290 cMaxResumeLoops = 16384;
1291 else if (cMaxResumeLoops < 32)
1292 cMaxResumeLoops = 32;
1293 pVM->hm.s.cMaxResumeLoopsCfg = pVM->hmr0.s.cMaxResumeLoops = cMaxResumeLoops;
1294
1295 /*
1296 * Initialize some per-VCPU fields.
1297 */
1298 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1299 {
1300 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1301 pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1302 pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1303
1304 /* We'll aways increment this the first time (host uses ASID 0). */
1305 AssertReturn(!pVCpu->hmr0.s.uCurrentAsid, VERR_HM_IPE_3);
1306 }
1307
1308 /*
1309 * Configure defences against spectre and other CPU bugs.
1310 */
1311 uint32_t fWorldSwitcher = 0;
1312 uint32_t cLastStdLeaf = ASMCpuId_EAX(0);
1313 if (cLastStdLeaf >= 0x00000007 && RTX86IsValidStdRange(cLastStdLeaf))
1314 {
1315 uint32_t uEdx = 0;
1316 ASMCpuIdExSlow(0x00000007, 0, 0, 0, NULL, NULL, NULL, &uEdx);
1317
1318 if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB)
1319 {
1320 if (pVM->hm.s.fIbpbOnVmExit)
1321 fWorldSwitcher |= HM_WSF_IBPB_EXIT;
1322 if (pVM->hm.s.fIbpbOnVmEntry)
1323 fWorldSwitcher |= HM_WSF_IBPB_ENTRY;
1324 }
1325 if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD)
1326 {
1327 if (pVM->hm.s.fL1dFlushOnVmEntry)
1328 fWorldSwitcher |= HM_WSF_L1D_ENTRY;
1329 else if (pVM->hm.s.fL1dFlushOnSched)
1330 fWorldSwitcher |= HM_WSF_L1D_SCHED;
1331 }
1332 if (uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR)
1333 {
1334 if (pVM->hm.s.fMdsClearOnVmEntry)
1335 fWorldSwitcher |= HM_WSF_MDS_ENTRY;
1336 else if (pVM->hm.s.fMdsClearOnSched)
1337 fWorldSwitcher |= HM_WSF_MDS_SCHED;
1338 }
1339 }
1340 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1341 {
1342 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
1343 pVCpu->hmr0.s.fWorldSwitcher = fWorldSwitcher;
1344 }
1345 pVM->hm.s.ForR3.fWorldSwitcher = fWorldSwitcher;
1346
1347
1348 /*
1349 * Call the hardware specific initialization method.
1350 */
1351 return g_HmR0Ops.pfnInitVM(pVM);
1352}
1353
1354
1355/**
1356 * Does ring-0 per VM HM termination.
1357 *
1358 * @returns VBox status code.
1359 * @param pVM The cross context VM structure.
1360 */
1361VMMR0_INT_DECL(int) HMR0TermVM(PVMCC pVM)
1362{
1363 Log(("HMR0TermVM: %p\n", pVM));
1364 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1365
1366 /*
1367 * Call the hardware specific method.
1368 *
1369 * Note! We might be preparing for a suspend, so the pfnTermVM() functions should probably not
1370 * mess with VT-x/AMD-V features on the CPU, currently all they do is free memory so this is safe.
1371 */
1372 return g_HmR0Ops.pfnTermVM(pVM);
1373}
1374
1375
1376/**
1377 * Sets up a VT-x or AMD-V session.
1378 *
1379 * This is mostly about setting up the hardware VM state.
1380 *
1381 * @returns VBox status code.
1382 * @param pVM The cross context VM structure.
1383 */
1384VMMR0_INT_DECL(int) HMR0SetupVM(PVMCC pVM)
1385{
1386 Log(("HMR0SetupVM: %p\n", pVM));
1387 AssertReturn(pVM, VERR_INVALID_PARAMETER);
1388
1389 /* Make sure we don't touch HM after we've disabled HM in preparation of a suspend. */
1390 AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1391
1392 /* On first entry we'll sync everything. */
1393 VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1394
1395 /*
1396 * Call the hardware specific setup VM method. This requires the CPU to be
1397 * enabled for AMD-V/VT-x and preemption to be prevented.
1398 */
1399 RTTHREADPREEMPTSTATE PreemptState = RTTHREADPREEMPTSTATE_INITIALIZER;
1400 RTThreadPreemptDisable(&PreemptState);
1401 RTCPUID const idCpu = RTMpCpuId();
1402
1403 /* Enable VT-x or AMD-V if local init is required. */
1404 int rc;
1405 if (!g_fHmGlobalInit)
1406 {
1407 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
1408 rc = hmR0EnableCpu(pVM, idCpu);
1409 if (RT_FAILURE(rc))
1410 {
1411 RTThreadPreemptRestore(&PreemptState);
1412 return rc;
1413 }
1414 }
1415
1416 /* Setup VT-x or AMD-V. */
1417 rc = g_HmR0Ops.pfnSetupVM(pVM);
1418
1419 /* Disable VT-x or AMD-V if local init was done before. */
1420 if (!g_fHmGlobalInit)
1421 {
1422 Assert(!g_fHmVmxSupported || !g_fHmVmxUsingSUPR0EnableVTx);
1423 int rc2 = hmR0DisableCpu(idCpu);
1424 AssertRC(rc2);
1425 }
1426
1427 RTThreadPreemptRestore(&PreemptState);
1428 return rc;
1429}
1430
1431
1432/**
1433 * Notification callback before an assertion longjump and guru mediation.
1434 *
1435 * @returns VBox status code.
1436 * @param pVCpu The cross context virtual CPU structure.
1437 * @param pvUser User argument, currently unused, NULL.
1438 */
1439static DECLCALLBACK(int) hmR0AssertionCallback(PVMCPUCC pVCpu, void *pvUser)
1440{
1441 RT_NOREF(pvUser);
1442 Assert(pVCpu);
1443 Assert(g_HmR0Ops.pfnAssertionCallback);
1444 return g_HmR0Ops.pfnAssertionCallback(pVCpu);
1445}
1446
1447
1448/**
1449 * Turns on HM on the CPU if necessary and initializes the bare minimum state
1450 * required for entering HM context.
1451 *
1452 * @returns VBox status code.
1453 * @param pVCpu The cross context virtual CPU structure.
1454 *
1455 * @remarks No-long-jump zone!!!
1456 */
1457VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu)
1458{
1459 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1460
1461 int rc = VINF_SUCCESS;
1462 RTCPUID const idCpu = RTMpCpuId();
1463 PHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1464 AssertPtr(pHostCpu);
1465
1466 /* Enable VT-x or AMD-V if local init is required, or enable if it's a freshly onlined CPU. */
1467 if (!pHostCpu->fConfigured)
1468 rc = hmR0EnableCpu(pVCpu->CTX_SUFF(pVM), idCpu);
1469
1470 /* Register a callback to fire prior to performing a longjmp to ring-3 so HM can disable VT-x/AMD-V if needed. */
1471 VMMR0AssertionSetNotification(pVCpu, hmR0AssertionCallback, NULL /*pvUser*/);
1472
1473 /* Reload host-state (back from ring-3/migrated CPUs) and shared guest/host bits. */
1474 if (g_fHmVmxSupported)
1475 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE;
1476 else
1477 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE;
1478
1479 Assert(pHostCpu->idCpu == idCpu && pHostCpu->idCpu != NIL_RTCPUID);
1480 pVCpu->hmr0.s.idEnteredCpu = idCpu;
1481 return rc;
1482}
1483
1484
1485/**
1486 * Enters the VT-x or AMD-V session.
1487 *
1488 * @returns VBox status code.
1489 * @param pVCpu The cross context virtual CPU structure.
1490 *
1491 * @remarks This is called with preemption disabled.
1492 */
1493VMMR0_INT_DECL(int) HMR0Enter(PVMCPUCC pVCpu)
1494{
1495 /* Make sure we can't enter a session after we've disabled HM in preparation of a suspend. */
1496 AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1497 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1498
1499 /* Load the bare minimum state required for entering HM. */
1500 int rc = hmR0EnterCpu(pVCpu);
1501 if (RT_SUCCESS(rc))
1502 {
1503 if (g_fHmVmxSupported)
1504 Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE))
1505 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE));
1506 else
1507 Assert( (pVCpu->hm.s.fCtxChanged & (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE))
1508 == (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE));
1509
1510 /* Keep track of the CPU owning the VMCS for debugging scheduling weirdness and ring-3 calls. */
1511 rc = g_HmR0Ops.pfnEnterSession(pVCpu);
1512 AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1513
1514 /* Exports the host-state as we may be resuming code after a longjmp and quite
1515 possibly now be scheduled on a different CPU. */
1516 rc = g_HmR0Ops.pfnExportHostState(pVCpu);
1517 AssertMsgRCReturnStmt(rc, ("rc=%Rrc pVCpu=%p\n", rc, pVCpu), pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID, rc);
1518 }
1519 return rc;
1520}
1521
1522
1523/**
1524 * Deinitializes the bare minimum state used for HM context and if necessary
1525 * disable HM on the CPU.
1526 *
1527 * @returns VBox status code.
1528 * @param pVCpu The cross context virtual CPU structure.
1529 *
1530 * @remarks No-long-jump zone!!!
1531 */
1532VMMR0_INT_DECL(int) HMR0LeaveCpu(PVMCPUCC pVCpu)
1533{
1534 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1535 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_HM_WRONG_CPU);
1536
1537 RTCPUID const idCpu = RTMpCpuId();
1538 PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[idCpu];
1539
1540 if ( !g_fHmGlobalInit
1541 && pHostCpu->fConfigured)
1542 {
1543 int rc = hmR0DisableCpu(idCpu);
1544 AssertRCReturn(rc, rc);
1545 Assert(!pHostCpu->fConfigured);
1546 Assert(pHostCpu->idCpu == NIL_RTCPUID);
1547
1548 /* For obtaining a non-zero ASID/VPID on next re-entry. */
1549 pVCpu->hmr0.s.idLastCpu = NIL_RTCPUID;
1550 }
1551
1552 /* Clear it while leaving HM context, hmPokeCpuForTlbFlush() relies on this. */
1553 pVCpu->hmr0.s.idEnteredCpu = NIL_RTCPUID;
1554
1555 /* De-register the longjmp-to-ring 3 callback now that we have reliquished hardware resources. */
1556 VMMR0AssertionRemoveNotification(pVCpu);
1557 return VINF_SUCCESS;
1558}
1559
1560
1561/**
1562 * Thread-context hook for HM.
1563 *
1564 * This is used together with RTThreadCtxHookCreate() on platforms which
1565 * supports it, and directly from VMMR0EmtPrepareForBlocking() and
1566 * VMMR0EmtResumeAfterBlocking() on platforms which don't.
1567 *
1568 * @param enmEvent The thread-context event.
1569 * @param pvUser Opaque pointer to the VMCPU.
1570 */
1571VMMR0_INT_DECL(void) HMR0ThreadCtxCallback(RTTHREADCTXEVENT enmEvent, void *pvUser)
1572{
1573 PVMCPUCC pVCpu = (PVMCPUCC)pvUser;
1574 Assert(pVCpu);
1575 Assert(g_HmR0Ops.pfnThreadCtxCallback);
1576
1577 g_HmR0Ops.pfnThreadCtxCallback(enmEvent, pVCpu, g_fHmGlobalInit);
1578}
1579
1580
1581/**
1582 * Runs guest code in a hardware accelerated VM.
1583 *
1584 * @returns Strict VBox status code. (VBOXSTRICTRC isn't used because it's
1585 * called from setjmp assembly.)
1586 * @param pVM The cross context VM structure.
1587 * @param pVCpu The cross context virtual CPU structure.
1588 *
1589 * @remarks Can be called with preemption enabled if thread-context hooks are
1590 * used!!!
1591 */
1592VMMR0_INT_DECL(int) HMR0RunGuestCode(PVMCC pVM, PVMCPUCC pVCpu)
1593{
1594 RT_NOREF(pVM);
1595
1596#ifdef VBOX_STRICT
1597 /* With thread-context hooks we would be running this code with preemption enabled. */
1598 if (!RTThreadPreemptIsEnabled(NIL_RTTHREAD))
1599 {
1600 PCHMPHYSCPU pHostCpu = &g_aHmCpuInfo[RTMpCpuId()];
1601 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL));
1602 Assert(pHostCpu->fConfigured);
1603 AssertReturn(!ASMAtomicReadBool(&g_fHmSuspended), VERR_HM_SUSPEND_PENDING);
1604 }
1605#endif
1606
1607 VBOXSTRICTRC rcStrict = g_HmR0Ops.pfnRunGuestCode(pVCpu);
1608 return VBOXSTRICTRC_VAL(rcStrict);
1609}
1610
1611
1612/**
1613 * Notification from CPUM that it has unloaded the guest FPU/SSE/AVX state from
1614 * the host CPU and that guest access to it must be intercepted.
1615 *
1616 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1617 */
1618VMMR0_INT_DECL(void) HMR0NotifyCpumUnloadedGuestFpuState(PVMCPUCC pVCpu)
1619{
1620 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_CR0);
1621}
1622
1623
1624/**
1625 * Notification from CPUM that it has modified the host CR0 (because of FPU).
1626 *
1627 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1628 */
1629VMMR0_INT_DECL(void) HMR0NotifyCpumModifiedHostCr0(PVMCPUCC pVCpu)
1630{
1631 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_HOST_CONTEXT);
1632}
1633
1634
1635/**
1636 * Returns suspend status of the host.
1637 *
1638 * @returns Suspend pending or not.
1639 */
1640VMMR0_INT_DECL(bool) HMR0SuspendPending(void)
1641{
1642 return ASMAtomicReadBool(&g_fHmSuspended);
1643}
1644
1645
1646/**
1647 * Invalidates a guest page from the host TLB.
1648 *
1649 * @param pVCpu The cross context virtual CPU structure.
1650 * @param GCVirt Page to invalidate.
1651 */
1652VMMR0_INT_DECL(int) HMR0InvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
1653{
1654 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1655 if (pVM->hm.s.vmx.fSupported)
1656 return VMXR0InvalidatePage(pVCpu, GCVirt);
1657 return SVMR0InvalidatePage(pVCpu, GCVirt);
1658}
1659
1660
1661/**
1662 * Returns the cpu structure for the current cpu.
1663 * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
1664 *
1665 * @returns The cpu structure pointer.
1666 */
1667VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void)
1668{
1669 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
1670 RTCPUID const idCpu = RTMpCpuId();
1671 Assert(idCpu < RT_ELEMENTS(g_aHmCpuInfo));
1672 return &g_aHmCpuInfo[idCpu];
1673}
1674
1675
1676/**
1677 * Interface for importing state on demand (used by IEM).
1678 *
1679 * @returns VBox status code.
1680 * @param pVCpu The cross context CPU structure.
1681 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1682 */
1683VMMR0_INT_DECL(int) HMR0ImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1684{
1685 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1686 return VMXR0ImportStateOnDemand(pVCpu, fWhat);
1687 return SVMR0ImportStateOnDemand(pVCpu, fWhat);
1688}
1689
1690
1691/**
1692 * Gets HM VM-exit auxiliary information.
1693 *
1694 * @returns VBox status code.
1695 * @param pVCpu The cross context CPU structure.
1696 * @param pHmExitAux Where to store the auxiliary info.
1697 * @param fWhat What to get, see HMVMX_READ_XXX. This is ignored/unused
1698 * on AMD-V.
1699 *
1700 * @remarks Currently this works only when executing a nested-guest using
1701 * hardware-assisted execution as it's where the auxiliary information is
1702 * required outside of HM. In the future we can make this available while
1703 * executing a regular (non-nested) guest if necessary.
1704 */
1705VMMR0_INT_DECL(int) HMR0GetExitAuxInfo(PVMCPUCC pVCpu, PHMEXITAUX pHmExitAux, uint32_t fWhat)
1706{
1707 Assert(pHmExitAux);
1708 Assert(!(fWhat & ~HMVMX_READ_VALID_MASK));
1709 if (pVCpu->CTX_SUFF(pVM)->hm.s.vmx.fSupported)
1710 return VMXR0GetExitAuxInfo(pVCpu, &pHmExitAux->Vmx, fWhat);
1711 return SVMR0GetExitAuxInfo(pVCpu, &pHmExitAux->Svm);
1712}
1713
1714
1715#ifdef VBOX_STRICT
1716
1717/**
1718 * Dumps a descriptor.
1719 *
1720 * @param pDesc Descriptor to dump.
1721 * @param Sel The selector.
1722 * @param pszSel The name of the selector.
1723 */
1724VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszSel)
1725{
1726 /*
1727 * Make variable description string.
1728 */
1729 static struct
1730 {
1731 unsigned cch;
1732 const char *psz;
1733 } const s_aTypes[32] =
1734 {
1735# define STRENTRY(str) { sizeof(str) - 1, str }
1736
1737 /* system */
1738# if HC_ARCH_BITS == 64
1739 STRENTRY("Reserved0 "), /* 0x00 */
1740 STRENTRY("Reserved1 "), /* 0x01 */
1741 STRENTRY("LDT "), /* 0x02 */
1742 STRENTRY("Reserved3 "), /* 0x03 */
1743 STRENTRY("Reserved4 "), /* 0x04 */
1744 STRENTRY("Reserved5 "), /* 0x05 */
1745 STRENTRY("Reserved6 "), /* 0x06 */
1746 STRENTRY("Reserved7 "), /* 0x07 */
1747 STRENTRY("Reserved8 "), /* 0x08 */
1748 STRENTRY("TSS64Avail "), /* 0x09 */
1749 STRENTRY("ReservedA "), /* 0x0a */
1750 STRENTRY("TSS64Busy "), /* 0x0b */
1751 STRENTRY("Call64 "), /* 0x0c */
1752 STRENTRY("ReservedD "), /* 0x0d */
1753 STRENTRY("Int64 "), /* 0x0e */
1754 STRENTRY("Trap64 "), /* 0x0f */
1755# else
1756 STRENTRY("Reserved0 "), /* 0x00 */
1757 STRENTRY("TSS16Avail "), /* 0x01 */
1758 STRENTRY("LDT "), /* 0x02 */
1759 STRENTRY("TSS16Busy "), /* 0x03 */
1760 STRENTRY("Call16 "), /* 0x04 */
1761 STRENTRY("Task "), /* 0x05 */
1762 STRENTRY("Int16 "), /* 0x06 */
1763 STRENTRY("Trap16 "), /* 0x07 */
1764 STRENTRY("Reserved8 "), /* 0x08 */
1765 STRENTRY("TSS32Avail "), /* 0x09 */
1766 STRENTRY("ReservedA "), /* 0x0a */
1767 STRENTRY("TSS32Busy "), /* 0x0b */
1768 STRENTRY("Call32 "), /* 0x0c */
1769 STRENTRY("ReservedD "), /* 0x0d */
1770 STRENTRY("Int32 "), /* 0x0e */
1771 STRENTRY("Trap32 "), /* 0x0f */
1772# endif
1773 /* non system */
1774 STRENTRY("DataRO "), /* 0x10 */
1775 STRENTRY("DataRO Accessed "), /* 0x11 */
1776 STRENTRY("DataRW "), /* 0x12 */
1777 STRENTRY("DataRW Accessed "), /* 0x13 */
1778 STRENTRY("DataDownRO "), /* 0x14 */
1779 STRENTRY("DataDownRO Accessed "), /* 0x15 */
1780 STRENTRY("DataDownRW "), /* 0x16 */
1781 STRENTRY("DataDownRW Accessed "), /* 0x17 */
1782 STRENTRY("CodeEO "), /* 0x18 */
1783 STRENTRY("CodeEO Accessed "), /* 0x19 */
1784 STRENTRY("CodeER "), /* 0x1a */
1785 STRENTRY("CodeER Accessed "), /* 0x1b */
1786 STRENTRY("CodeConfEO "), /* 0x1c */
1787 STRENTRY("CodeConfEO Accessed "), /* 0x1d */
1788 STRENTRY("CodeConfER "), /* 0x1e */
1789 STRENTRY("CodeConfER Accessed ") /* 0x1f */
1790# undef SYSENTRY
1791 };
1792# define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
1793 char szMsg[128];
1794 char *psz = &szMsg[0];
1795 unsigned i = pDesc->Gen.u1DescType << 4 | pDesc->Gen.u4Type;
1796 memcpy(psz, s_aTypes[i].psz, s_aTypes[i].cch);
1797 psz += s_aTypes[i].cch;
1798
1799 if (pDesc->Gen.u1Present)
1800 ADD_STR(psz, "Present ");
1801 else
1802 ADD_STR(psz, "Not-Present ");
1803# if HC_ARCH_BITS == 64
1804 if (pDesc->Gen.u1Long)
1805 ADD_STR(psz, "64-bit ");
1806 else
1807 ADD_STR(psz, "Comp ");
1808# else
1809 if (pDesc->Gen.u1Granularity)
1810 ADD_STR(psz, "Page ");
1811 if (pDesc->Gen.u1DefBig)
1812 ADD_STR(psz, "32-bit ");
1813 else
1814 ADD_STR(psz, "16-bit ");
1815# endif
1816# undef ADD_STR
1817 *psz = '\0';
1818
1819 /*
1820 * Limit and Base and format the output.
1821 */
1822#ifdef LOG_ENABLED
1823 uint32_t u32Limit = X86DESC_LIMIT_G(pDesc);
1824
1825# if HC_ARCH_BITS == 64
1826 uint64_t const u64Base = X86DESC64_BASE(pDesc);
1827 Log((" %s { %#04x - %#RX64 %#RX64 - base=%#RX64 limit=%#08x dpl=%d } %s\n", pszSel,
1828 Sel, pDesc->au64[0], pDesc->au64[1], u64Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1829# else
1830 uint32_t const u32Base = X86DESC_BASE(pDesc);
1831 Log((" %s { %#04x - %#08x %#08x - base=%#08x limit=%#08x dpl=%d } %s\n", pszSel,
1832 Sel, pDesc->au32[0], pDesc->au32[1], u32Base, u32Limit, pDesc->Gen.u2Dpl, szMsg));
1833# endif
1834#else
1835 NOREF(Sel); NOREF(pszSel);
1836#endif
1837}
1838
1839
1840/**
1841 * Formats a full register dump.
1842 *
1843 * @param pVCpu The cross context virtual CPU structure.
1844 * @param fFlags The dumping flags (HM_DUMP_REG_FLAGS_XXX).
1845 */
1846VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags)
1847{
1848 /*
1849 * Format the flags.
1850 */
1851 static struct
1852 {
1853 const char *pszSet;
1854 const char *pszClear;
1855 uint32_t fFlag;
1856 } const s_aFlags[] =
1857 {
1858 { "vip", NULL, X86_EFL_VIP },
1859 { "vif", NULL, X86_EFL_VIF },
1860 { "ac", NULL, X86_EFL_AC },
1861 { "vm", NULL, X86_EFL_VM },
1862 { "rf", NULL, X86_EFL_RF },
1863 { "nt", NULL, X86_EFL_NT },
1864 { "ov", "nv", X86_EFL_OF },
1865 { "dn", "up", X86_EFL_DF },
1866 { "ei", "di", X86_EFL_IF },
1867 { "tf", NULL, X86_EFL_TF },
1868 { "nt", "pl", X86_EFL_SF },
1869 { "nz", "zr", X86_EFL_ZF },
1870 { "ac", "na", X86_EFL_AF },
1871 { "po", "pe", X86_EFL_PF },
1872 { "cy", "nc", X86_EFL_CF },
1873 };
1874 char szEFlags[80];
1875 char *psz = szEFlags;
1876 PCCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
1877 uint32_t fEFlags = pCtx->eflags.u;
1878 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1879 {
1880 const char *pszAdd = s_aFlags[i].fFlag & fEFlags ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1881 if (pszAdd)
1882 {
1883 strcpy(psz, pszAdd);
1884 psz += strlen(pszAdd);
1885 *psz++ = ' ';
1886 }
1887 }
1888 psz[-1] = '\0';
1889
1890 if (fFlags & HM_DUMP_REG_FLAGS_GPRS)
1891 {
1892 /*
1893 * Format the registers.
1894 */
1895 if (CPUMIsGuestIn64BitCode(pVCpu))
1896 Log(("rax=%016RX64 rbx=%016RX64 rcx=%016RX64 rdx=%016RX64\n"
1897 "rsi=%016RX64 rdi=%016RX64 r8 =%016RX64 r9 =%016RX64\n"
1898 "r10=%016RX64 r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1899 "r14=%016RX64 r15=%016RX64\n"
1900 "rip=%016RX64 rsp=%016RX64 rbp=%016RX64 iopl=%d %*s\n"
1901 "cs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1902 "ds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1903 "es={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1904 "fs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1905 "gs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1906 "ss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1907 "cr0=%016RX64 cr2=%016RX64 cr3=%016RX64 cr4=%016RX64\n"
1908 "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64 dr3=%016RX64\n"
1909 "dr4=%016RX64 dr5=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
1910 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1911 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1912 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1913 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1914 ,
1915 pCtx->rax, pCtx->rbx, pCtx->rcx, pCtx->rdx, pCtx->rsi, pCtx->rdi,
1916 pCtx->r8, pCtx->r9, pCtx->r10, pCtx->r11, pCtx->r12, pCtx->r13,
1917 pCtx->r14, pCtx->r15,
1918 pCtx->rip, pCtx->rsp, pCtx->rbp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
1919 pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1920 pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1921 pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1922 pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1923 pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1924 pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1925 pCtx->cr0, pCtx->cr2, pCtx->cr3, pCtx->cr4,
1926 pCtx->dr[0], pCtx->dr[1], pCtx->dr[2], pCtx->dr[3],
1927 pCtx->dr[4], pCtx->dr[5], pCtx->dr[6], pCtx->dr[7],
1928 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
1929 pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1930 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1931 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1932 else
1933 Log(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
1934 "eip=%08x esp=%08x ebp=%08x iopl=%d %*s\n"
1935 "cs={%04x base=%016RX64 limit=%08x flags=%08x} dr0=%08RX64 dr1=%08RX64\n"
1936 "ds={%04x base=%016RX64 limit=%08x flags=%08x} dr2=%08RX64 dr3=%08RX64\n"
1937 "es={%04x base=%016RX64 limit=%08x flags=%08x} dr4=%08RX64 dr5=%08RX64\n"
1938 "fs={%04x base=%016RX64 limit=%08x flags=%08x} dr6=%08RX64 dr7=%08RX64\n"
1939 "gs={%04x base=%016RX64 limit=%08x flags=%08x} cr0=%08RX64 cr2=%08RX64\n"
1940 "ss={%04x base=%016RX64 limit=%08x flags=%08x} cr3=%08RX64 cr4=%08RX64\n"
1941 "gdtr=%016RX64:%04x idtr=%016RX64:%04x eflags=%08x\n"
1942 "ldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1943 "tr ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1944 "SysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1945 ,
1946 pCtx->eax, pCtx->ebx, pCtx->ecx, pCtx->edx, pCtx->esi, pCtx->edi,
1947 pCtx->eip, pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(fEFlags), 31, szEFlags,
1948 pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pCtx->dr[0], pCtx->dr[1],
1949 pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pCtx->dr[2], pCtx->dr[3],
1950 pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pCtx->dr[4], pCtx->dr[5],
1951 pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pCtx->dr[6], pCtx->dr[7],
1952 pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pCtx->cr0, pCtx->cr2,
1953 pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pCtx->cr3, pCtx->cr4,
1954 pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, fEFlags,
1955 pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1956 pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1957 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp));
1958 }
1959
1960 if (fFlags & HM_DUMP_REG_FLAGS_FPU)
1961 {
1962 PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
1963 Log(("FPU:\n"
1964 "FCW=%04x FSW=%04x FTW=%02x\n"
1965 "FOP=%04x FPUIP=%08x CS=%04x Rsrvd1=%04x\n"
1966 "FPUDP=%04x DS=%04x Rsvrd2=%04x MXCSR=%08x MXCSR_MASK=%08x\n"
1967 ,
1968 pFpuCtx->FCW, pFpuCtx->FSW, pFpuCtx->FTW,
1969 pFpuCtx->FOP, pFpuCtx->FPUIP, pFpuCtx->CS, pFpuCtx->Rsrvd1,
1970 pFpuCtx->FPUDP, pFpuCtx->DS, pFpuCtx->Rsrvd2,
1971 pFpuCtx->MXCSR, pFpuCtx->MXCSR_MASK));
1972 NOREF(pFpuCtx);
1973 }
1974
1975 if (fFlags & HM_DUMP_REG_FLAGS_MSRS)
1976 Log(("MSR:\n"
1977 "EFER =%016RX64\n"
1978 "PAT =%016RX64\n"
1979 "STAR =%016RX64\n"
1980 "CSTAR =%016RX64\n"
1981 "LSTAR =%016RX64\n"
1982 "SFMASK =%016RX64\n"
1983 "KERNELGSBASE =%016RX64\n",
1984 pCtx->msrEFER,
1985 pCtx->msrPAT,
1986 pCtx->msrSTAR,
1987 pCtx->msrCSTAR,
1988 pCtx->msrLSTAR,
1989 pCtx->msrSFMASK,
1990 pCtx->msrKERNELGSBASE));
1991}
1992
1993#endif /* VBOX_STRICT */
1994
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