VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp@ 74795

Last change on this file since 74795 was 74789, checked in by vboxsync, 6 years ago

vm.h,VMM,REM: s/VMCPU_FF_IS_PENDING/VMCPU_FF_IS_ANY_SET/g to emphasize the plurality of the flags argument and encourage using VMCPU_FF_IS_SET. bugref:9180
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1/* $Id: TRPMAll.cpp 74789 2018-10-12 10:34:32Z vboxsync $ */
2/** @file
3 * TRPM - Trap Monitor - Any Context.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_TRPM
23#include <VBox/vmm/trpm.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/patm.h>
28#include <VBox/vmm/selm.h>
29#include <VBox/vmm/stam.h>
30#include <VBox/vmm/dbgf.h>
31#include "TRPMInternal.h"
32#include <VBox/vmm/vm.h>
33#include <VBox/err.h>
34#include <VBox/vmm/em.h>
35#include <VBox/log.h>
36#include <iprt/assert.h>
37#include <iprt/asm.h>
38#include <iprt/asm-amd64-x86.h>
39#include <iprt/param.h>
40#include <iprt/x86.h>
41
42
43
44#if defined(TRPM_TRACK_GUEST_IDT_CHANGES) && !defined(IN_RING0)
45/**
46 * @callback_method_impl{FNPGMVIRTPFHANDLER,
47 * \#PF Handler callback for virtual access handler ranges.}
48 *
49 * Important to realize that a physical page in a range can have aliases, and
50 * for ALL and WRITE handlers these will also trigger.
51 */
52PGM_ALL_CB2_DECL(VBOXSTRICTRC)
53trpmGuestIDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
54 PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
55{
56 Assert(enmAccessType == PGMACCESSTYPE_WRITE); NOREF(enmAccessType);
57 Log(("trpmGuestIDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf)); NOREF(GCPtr); NOREF(cbBuf);
58 NOREF(pvPtr); NOREF(pvUser); NOREF(pvBuf); NOREF(enmOrigin); NOREF(pvUser); RT_NOREF_PV(pVM);
59 Assert(VM_IS_RAW_MODE_ENABLED(pVM));
60
61 /** @todo Check which IDT entry and keep the update cost low in TRPMR3SyncIDT() and CSAMCheckGates(). */
62 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
63# ifdef IN_RC
64 STAM_COUNTER_INC(&pVM->trpm.s.StatRCWriteGuestIDTFault);
65# endif
66 return VINF_PGM_HANDLER_DO_DEFAULT;
67}
68#endif /* TRPM_TRACK_GUEST_IDT_CHANGES && !IN_RING0 */
69
70
71/**
72 * Query info about the current active trap/interrupt.
73 * If no trap is active active an error code is returned.
74 *
75 * @returns VBox status code.
76 * @param pVCpu The cross context virtual CPU structure.
77 * @param pu8TrapNo Where to store the trap number.
78 * @param penmType Where to store the trap type
79 */
80VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *penmType)
81{
82 /*
83 * Check if we have a trap at present.
84 */
85 if (pVCpu->trpm.s.uActiveVector != ~0U)
86 {
87 if (pu8TrapNo)
88 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
89 if (penmType)
90 *penmType = pVCpu->trpm.s.enmActiveType;
91 return VINF_SUCCESS;
92 }
93
94 return VERR_TRPM_NO_ACTIVE_TRAP;
95}
96
97
98/**
99 * Gets the trap number for the current trap.
100 *
101 * The caller is responsible for making sure there is an active trap which
102 * takes an error code when making this request.
103 *
104 * @returns The current trap number.
105 * @param pVCpu The cross context virtual CPU structure.
106 */
107VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu)
108{
109 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
110 return (uint8_t)pVCpu->trpm.s.uActiveVector;
111}
112
113
114/**
115 * Gets the error code for the current trap.
116 *
117 * The caller is responsible for making sure there is an active trap which
118 * takes an error code when making this request.
119 *
120 * @returns Error code.
121 * @param pVCpu The cross context virtual CPU structure.
122 */
123VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu)
124{
125 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
126#ifdef VBOX_STRICT
127 switch (pVCpu->trpm.s.uActiveVector)
128 {
129 case X86_XCPT_TS:
130 case X86_XCPT_NP:
131 case X86_XCPT_SS:
132 case X86_XCPT_GP:
133 case X86_XCPT_PF:
134 case X86_XCPT_AC:
135 case X86_XCPT_DF:
136 break;
137 default:
138 AssertMsgFailed(("This trap (%#x) doesn't have any error code\n", pVCpu->trpm.s.uActiveVector));
139 break;
140 }
141#endif
142 return pVCpu->trpm.s.uActiveErrorCode;
143}
144
145
146/**
147 * Gets the fault address for the current trap.
148 *
149 * The caller is responsible for making sure there is an active trap 0x0e when
150 * making this request.
151 *
152 * @returns Fault address associated with the trap.
153 * @param pVCpu The cross context virtual CPU structure.
154 */
155VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu)
156{
157 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
158 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_PF, ("Not page-fault trap!\n"));
159 return pVCpu->trpm.s.uActiveCR2;
160}
161
162
163/**
164 * Gets the instruction-length for the current trap (only relevant for software
165 * interrupts and software exceptions \#BP and \#OF).
166 *
167 * The caller is responsible for making sure there is an active trap 0x0e when
168 * making this request.
169 *
170 * @returns Fault address associated with the trap.
171 * @param pVCpu The cross context virtual CPU structure.
172 */
173VMMDECL(uint8_t) TRPMGetInstrLength(PVMCPU pVCpu)
174{
175 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
176 return pVCpu->trpm.s.cbInstr;
177}
178
179
180/**
181 * Clears the current active trap/exception/interrupt.
182 *
183 * The caller is responsible for making sure there is an active trap
184 * when making this request.
185 *
186 * @returns VBox status code.
187 * @param pVCpu The cross context virtual CPU structure.
188 */
189VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu)
190{
191 /*
192 * Cannot reset non-existing trap!
193 */
194 if (pVCpu->trpm.s.uActiveVector == ~0U)
195 {
196 AssertMsgFailed(("No active trap!\n"));
197 return VERR_TRPM_NO_ACTIVE_TRAP;
198 }
199
200 /*
201 * Reset it.
202 */
203 pVCpu->trpm.s.uActiveVector = ~0U;
204 return VINF_SUCCESS;
205}
206
207
208/**
209 * Assert trap/exception/interrupt.
210 *
211 * The caller is responsible for making sure there is no active trap
212 * when making this request.
213 *
214 * @returns VBox status code.
215 * @param pVCpu The cross context virtual CPU structure.
216 * @param u8TrapNo The trap vector to assert.
217 * @param enmType Trap type.
218 */
219VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType)
220{
221 Log2(("TRPMAssertTrap: u8TrapNo=%02x type=%d\n", u8TrapNo, enmType));
222
223 /*
224 * Cannot assert a trap when one is already active.
225 */
226 if (pVCpu->trpm.s.uActiveVector != ~0U)
227 {
228 AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
229 return VERR_TRPM_ACTIVE_TRAP;
230 }
231
232 pVCpu->trpm.s.uActiveVector = u8TrapNo;
233 pVCpu->trpm.s.enmActiveType = enmType;
234 pVCpu->trpm.s.uActiveErrorCode = ~(RTGCUINT)0;
235 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
236 pVCpu->trpm.s.cbInstr = UINT8_MAX;
237 return VINF_SUCCESS;
238}
239
240
241/**
242 * Assert a page-fault exception.
243 *
244 * The caller is responsible for making sure there is no active trap
245 * when making this request.
246 *
247 * @returns VBox status code.
248 * @param pVCpu The cross context virtual CPU structure.
249 * @param uCR2 The new fault address.
250 * @param uErrorCode The error code for the page-fault.
251 */
252VMMDECL(int) TRPMAssertXcptPF(PVMCPU pVCpu, RTGCUINTPTR uCR2, RTGCUINT uErrorCode)
253{
254 Log2(("TRPMAssertXcptPF: uCR2=%RGv uErrorCode=%RGv\n", uCR2, uErrorCode)); /** @todo RTGCUINT to be fixed. */
255
256 /*
257 * Cannot assert a trap when one is already active.
258 */
259 if (pVCpu->trpm.s.uActiveVector != ~0U)
260 {
261 AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
262 return VERR_TRPM_ACTIVE_TRAP;
263 }
264
265 pVCpu->trpm.s.uActiveVector = X86_XCPT_PF;
266 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
267 pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
268 pVCpu->trpm.s.uActiveCR2 = uCR2;
269 pVCpu->trpm.s.cbInstr = UINT8_MAX;
270 return VINF_SUCCESS;
271}
272
273
274/**
275 * Sets the error code of the current trap.
276 * (This function is for use in trap handlers and such.)
277 *
278 * The caller is responsible for making sure there is an active trap
279 * which takes an errorcode when making this request.
280 *
281 * @param pVCpu The cross context virtual CPU structure.
282 * @param uErrorCode The new error code.
283 */
284VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode)
285{
286 Log2(("TRPMSetErrorCode: uErrorCode=%RGv\n", uErrorCode)); /** @todo RTGCUINT mess! */
287 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
288 pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
289#ifdef VBOX_STRICT
290 switch (pVCpu->trpm.s.uActiveVector)
291 {
292 case X86_XCPT_TS: case X86_XCPT_NP: case X86_XCPT_SS: case X86_XCPT_GP: case X86_XCPT_PF:
293 AssertMsg(uErrorCode != ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
294 break;
295 case X86_XCPT_AC: case X86_XCPT_DF:
296 AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
297 break;
298 default:
299 AssertMsg(uErrorCode == ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
300 break;
301 }
302#endif
303}
304
305
306/**
307 * Sets the fault address of the current \#PF trap. (This function is for use in
308 * trap handlers and such.)
309 *
310 * The caller is responsible for making sure there is an active trap 0e
311 * when making this request.
312 *
313 * @param pVCpu The cross context virtual CPU structure.
314 * @param uCR2 The new fault address (cr2 register).
315 */
316VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPTR uCR2)
317{
318 Log2(("TRPMSetFaultAddress: uCR2=%RGv\n", uCR2));
319 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
320 AssertMsg(pVCpu->trpm.s.uActiveVector == X86_XCPT_PF, ("Not trap 0e!\n"));
321 pVCpu->trpm.s.uActiveCR2 = uCR2;
322}
323
324
325/**
326 * Sets the instruction-length of the current trap (relevant for software
327 * interrupts and software exceptions like \#BP, \#OF).
328 *
329 * The caller is responsible for making sure there is an active trap 0e
330 * when making this request.
331 *
332 * @param pVCpu The cross context virtual CPU structure.
333 * @param cbInstr The instruction length.
334 */
335VMMDECL(void) TRPMSetInstrLength(PVMCPU pVCpu, uint8_t cbInstr)
336{
337 Log2(("TRPMSetInstrLength: cbInstr=%u\n", cbInstr));
338 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
339 AssertMsg( pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT
340 || ( pVCpu->trpm.s.enmActiveType == TRPM_TRAP
341 && ( pVCpu->trpm.s.uActiveVector == X86_XCPT_BP
342 || pVCpu->trpm.s.uActiveVector == X86_XCPT_OF)),
343 ("Invalid trap type %#x\n", pVCpu->trpm.s.enmActiveType));
344 pVCpu->trpm.s.cbInstr = cbInstr;
345}
346
347
348/**
349 * Checks if the current active trap/interrupt/exception/fault/whatever is a software
350 * interrupt or not.
351 *
352 * The caller is responsible for making sure there is an active trap
353 * when making this request.
354 *
355 * @returns true if software interrupt, false if not.
356 *
357 * @param pVCpu The cross context virtual CPU structure.
358 */
359VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu)
360{
361 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
362 return (pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT);
363}
364
365
366/**
367 * Check if there is an active trap.
368 *
369 * @returns true if trap active, false if not.
370 * @param pVCpu The cross context virtual CPU structure.
371 */
372VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu)
373{
374 return pVCpu->trpm.s.uActiveVector != ~0U;
375}
376
377
378/**
379 * Query all info about the current active trap/interrupt.
380 * If no trap is active active an error code is returned.
381 *
382 * @returns VBox status code.
383 * @param pVCpu The cross context virtual CPU structure.
384 * @param pu8TrapNo Where to store the trap number.
385 * @param pEnmType Where to store the trap type
386 * @param puErrorCode Where to store the error code associated with some traps.
387 * ~0U is stored if the trap has no error code.
388 * @param puCR2 Where to store the CR2 associated with a trap 0E.
389 * @param pcbInstr Where to store the instruction-length
390 * associated with some traps.
391 */
392VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, PRTGCUINT puErrorCode, PRTGCUINTPTR puCR2,
393 uint8_t *pcbInstr)
394{
395 /*
396 * Check if we have a trap at present.
397 */
398 if (pVCpu->trpm.s.uActiveVector == ~0U)
399 return VERR_TRPM_NO_ACTIVE_TRAP;
400
401 if (pu8TrapNo)
402 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
403 if (pEnmType)
404 *pEnmType = pVCpu->trpm.s.enmActiveType;
405 if (puErrorCode)
406 *puErrorCode = pVCpu->trpm.s.uActiveErrorCode;
407 if (puCR2)
408 *puCR2 = pVCpu->trpm.s.uActiveCR2;
409 if (pcbInstr)
410 *pcbInstr = pVCpu->trpm.s.cbInstr;
411 return VINF_SUCCESS;
412}
413
414
415/**
416 * Save the active trap.
417 *
418 * This routine useful when doing try/catch in the hypervisor.
419 * Any function which uses temporary trap handlers should
420 * probably also use this facility to save the original trap.
421 *
422 * @param pVCpu The cross context virtual CPU structure.
423 */
424VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu)
425{
426 pVCpu->trpm.s.uSavedVector = pVCpu->trpm.s.uActiveVector;
427 pVCpu->trpm.s.enmSavedType = pVCpu->trpm.s.enmActiveType;
428 pVCpu->trpm.s.uSavedErrorCode = pVCpu->trpm.s.uActiveErrorCode;
429 pVCpu->trpm.s.uSavedCR2 = pVCpu->trpm.s.uActiveCR2;
430 pVCpu->trpm.s.cbSavedInstr = pVCpu->trpm.s.cbInstr;
431}
432
433
434/**
435 * Restore a saved trap.
436 *
437 * Multiple restores of a saved trap is possible.
438 *
439 * @param pVCpu The cross context virtual CPU structure.
440 */
441VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu)
442{
443 pVCpu->trpm.s.uActiveVector = pVCpu->trpm.s.uSavedVector;
444 pVCpu->trpm.s.enmActiveType = pVCpu->trpm.s.enmSavedType;
445 pVCpu->trpm.s.uActiveErrorCode = pVCpu->trpm.s.uSavedErrorCode;
446 pVCpu->trpm.s.uActiveCR2 = pVCpu->trpm.s.uSavedCR2;
447 pVCpu->trpm.s.cbInstr = pVCpu->trpm.s.cbSavedInstr;
448}
449
450
451#ifdef VBOX_WITH_RAW_MODE_NOT_R0
452/**
453 * Forward trap or interrupt to the guest's handler
454 *
455 *
456 * @returns VBox status code.
457 * or does not return at all (when the trap is actually forwarded)
458 *
459 * @param pVCpu The cross context virtual CPU structure.
460 * @param pRegFrame Pointer to the register frame for the trap.
461 * @param iGate Trap or interrupt gate number
462 * @param cbInstr Instruction size (only relevant for software interrupts)
463 * @param enmError TRPM_TRAP_HAS_ERRORCODE or TRPM_TRAP_NO_ERRORCODE.
464 * @param enmType TRPM event type
465 * @param iOrgTrap The original trap.
466 * @internal
467 */
468VMMDECL(int) TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t cbInstr,
469 TRPMERRORCODE enmError, TRPMEVENT enmType, int32_t iOrgTrap)
470{
471 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVCpu->CTX_SUFF(pVM)), VERR_TRPM_HM_IPE);
472#ifdef TRPM_FORWARD_TRAPS_IN_GC
473 PVM pVM = pVCpu->CTX_SUFF(pVM);
474 X86EFLAGS eflags;
475 Assert(pVM->cCpus == 1);
476
477 STAM_PROFILE_ADV_START(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
478
479# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
480 if (pRegFrame->eflags.Bits.u1VM)
481 Log(("TRPMForwardTrap-VM: eip=%04X:%04X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
482 else
483 Log(("TRPMForwardTrap: eip=%04X:%08X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
484
485 switch (iGate) {
486 case X86_XCPT_PF:
487 if (pRegFrame->eip == pVCpu->trpm.s.uActiveCR2)
488 {
489 RTGCPTR pCallerGC;
490# ifdef IN_RC
491 int rc = MMGCRamRead(pVM, &pCallerGC, (void *)pRegFrame->esp, sizeof(pCallerGC));
492# else
493 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &pCallerGC, (RTGCPTR)pRegFrame->esp, sizeof(pCallerGC));
494# endif
495 if (RT_SUCCESS(rc))
496 Log(("TRPMForwardTrap: caller=%RGv\n", pCallerGC));
497 }
498 RT_FALL_THRU();
499 case X86_XCPT_DF:
500 case X86_XCPT_TS:
501 case X86_XCPT_NP:
502 case X86_XCPT_SS:
503 case X86_XCPT_GP:
504 case X86_XCPT_AC:
505 Assert(enmError == TRPM_TRAP_HAS_ERRORCODE || enmType == TRPM_SOFTWARE_INT);
506 break;
507
508 default:
509 Assert(enmError == TRPM_TRAP_NO_ERRORCODE);
510 break;
511 }
512# endif /* VBOX_STRICT || LOG_ENABLED */
513#ifdef IN_RC
514 AssertReturn(CPUMIsGuestInRawMode(pVCpu), VINF_EM_RESCHEDULE);
515#endif
516
517 /* Retrieve the eflags including the virtualized bits. */
518 /* Note: hackish as the cpumctxcore structure doesn't contain the right value */
519 eflags.u32 = CPUMRawGetEFlags(pVCpu);
520
521 /* VMCPU_FF_INHIBIT_INTERRUPTS should be cleared upfront or don't call this function at all for dispatching hardware interrupts. */
522 Assert(enmType != TRPM_HARDWARE_INT || !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
523
524 /*
525 * If it's a real guest trap and the guest's page fault handler is marked as safe for GC execution, then we call it directly.
526 * Well, only if the IF flag is set.
527 */
528 /** @todo if the trap handler was modified and marked invalid, then we should *now* go back to the host context and install a new patch. */
529 if ( pVM->trpm.s.aGuestTrapHandler[iGate]
530 && (eflags.Bits.u1IF)
531#ifndef VBOX_RAW_V86
532 && !(eflags.Bits.u1VM) /** @todo implement when needed (illegal for same privilege level transfers). */
533#endif
534 && !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
535 )
536 {
537 uint16_t cbIDT;
538 RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
539 uint32_t cpl;
540 VBOXIDTE GuestIdte;
541 RTGCPTR pIDTEntry;
542 int rc;
543
544 Assert(PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame)));
545 Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
546
547 if (GCPtrIDT && iGate * sizeof(VBOXIDTE) >= cbIDT)
548 goto failure;
549
550 /* Get the current privilege level. */
551 cpl = CPUMGetGuestCPL(pVCpu);
552
553 /*
554 * BIG TODO: The checks are not complete. see trap and interrupt dispatching section in Intel docs for details
555 * All very obscure, but still necessary.
556 * Currently only some CS & TSS selector checks are missing.
557 *
558 */
559 pIDTEntry = (RTGCPTR)((RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate);
560#ifdef IN_RC
561 rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
562#else
563 rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
564#endif
565 if (RT_FAILURE(rc))
566 {
567 /* The page might be out of sync. */ /** @todo might cross a page boundary) */
568 Log(("Page %RGv out of sync -> prefetch and try again\n", pIDTEntry));
569 rc = PGMPrefetchPage(pVCpu, pIDTEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
570 if (rc != VINF_SUCCESS)
571 {
572 Log(("TRPMForwardTrap: PGMPrefetchPage failed with rc=%Rrc\n", rc));
573 goto failure;
574 }
575#ifdef IN_RC
576 rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
577#else
578 rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
579#endif
580 }
581 if ( RT_SUCCESS(rc)
582 && GuestIdte.Gen.u1Present
583 && (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
584 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0)
585 && (GuestIdte.Gen.u16SegSel & 0xfffc) /* must not be zero */
586 && (enmType == TRPM_TRAP || enmType == TRPM_HARDWARE_INT || cpl <= GuestIdte.Gen.u2DPL) /* CPL <= DPL if software int */
587 )
588 {
589 RTGCPTR pHandler, dummy;
590 RTGCPTR pTrapStackGC;
591
592 pHandler = (RTGCPTR)VBOXIDTE_OFFSET(GuestIdte);
593
594 /* Note: SELMValidateAndConvertCSAddr checks for code type, memory type, selector validity. */
595 /** @todo dpl <= cpl else GPF */
596
597 /* Note: don't use current eflags as we might be in V86 mode and the IDT always contains protected mode selectors */
598 X86EFLAGS fakeflags;
599 fakeflags.u32 = 0;
600
601 rc = SELMValidateAndConvertCSAddr(pVCpu, fakeflags, 0, GuestIdte.Gen.u16SegSel, NULL, pHandler, &dummy);
602 if (rc == VINF_SUCCESS)
603 {
604 VBOXGDTR gdtr = {0, 0};
605 bool fConforming = false;
606 int idx = 0;
607 uint32_t dpl;
608 uint32_t ss_r0;
609 uint32_t esp_r0;
610 X86DESC Desc;
611 RTGCPTR pGdtEntry;
612
613 CPUMGetGuestGDTR(pVCpu, &gdtr);
614 Assert(gdtr.pGdt && gdtr.cbGdt > GuestIdte.Gen.u16SegSel);
615
616 if (!gdtr.pGdt)
617 goto failure;
618
619 pGdtEntry = gdtr.pGdt + (GuestIdte.Gen.u16SegSel >> X86_SEL_SHIFT) * sizeof(X86DESC);
620#ifdef IN_RC
621 rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
622#else
623 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
624#endif
625 if (RT_FAILURE(rc))
626 {
627 /* The page might be out of sync. */ /** @todo might cross a page boundary) */
628 Log(("Page %RGv out of sync -> prefetch and try again\n", pGdtEntry));
629 rc = PGMPrefetchPage(pVCpu, pGdtEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
630 if (rc != VINF_SUCCESS)
631 {
632 Log(("PGMPrefetchPage failed with rc=%Rrc\n", rc));
633 goto failure;
634 }
635#ifdef IN_RC
636 rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
637#else
638 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
639#endif
640 if (RT_FAILURE(rc))
641 {
642 Log(("MMGCRamRead failed with %Rrc\n", rc));
643 goto failure;
644 }
645 }
646
647 if (Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
648 {
649 Log(("Conforming code selector\n"));
650 fConforming = true;
651 }
652 /** @todo check descriptor type!! */
653
654 dpl = Desc.Gen.u2Dpl;
655
656 if (!fConforming && dpl < cpl) /* to inner privilege level */
657 {
658 rc = SELMGetRing1Stack(pVM, &ss_r0, &esp_r0);
659 if (RT_FAILURE(rc))
660 goto failure;
661
662 Assert((ss_r0 & X86_SEL_RPL) == 1);
663
664 if ( !esp_r0
665 || !ss_r0
666 || (ss_r0 & X86_SEL_RPL) != ((dpl == 0) ? 1 : dpl)
667 || SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
668 (PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS
669 )
670 {
671 Log(("Invalid ring 0 stack %04X:%08RX32\n", ss_r0, esp_r0));
672 goto failure;
673 }
674 }
675 else
676 if (fConforming || dpl == cpl) /* to the same privilege level */
677 {
678 ss_r0 = pRegFrame->ss.Sel;
679 esp_r0 = pRegFrame->esp;
680
681 if ( eflags.Bits.u1VM /* illegal */
682 || SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
683 (PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS)
684 {
685 AssertMsgFailed(("Invalid stack %04X:%08RX32??? (VM=%d)\n", ss_r0, esp_r0, eflags.Bits.u1VM));
686 goto failure;
687 }
688 }
689 else
690 {
691 Log(("Invalid cpl-dpl combo %d vs %d\n", cpl, dpl));
692 goto failure;
693 }
694 /*
695 * Build trap stack frame on guest handler's stack
696 */
697 uint32_t *pTrapStack;
698#ifdef IN_RC
699 Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) != 0);
700 /* Check maximum amount we need (10 when executing in V86 mode) */
701 rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)pTrapStackGC - 10*sizeof(uint32_t), 10 * sizeof(uint32_t), X86_PTE_RW);
702 pTrapStack = (uint32_t *)(uintptr_t)pTrapStackGC;
703#else
704 Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) == 0 || (pRegFrame->ss.Sel & X86_SEL_RPL) == 3 || (EMIsRawRing1Enabled(pVM) && (pRegFrame->ss.Sel & X86_SEL_RPL) == 1));
705 /* Check maximum amount we need (10 when executing in V86 mode) */
706 if ((pTrapStackGC >> PAGE_SHIFT) != ((pTrapStackGC - 10*sizeof(uint32_t)) >> PAGE_SHIFT)) /* fail if we cross a page boundary */
707 goto failure;
708 PGMPAGEMAPLOCK PageMappingLock;
709 rc = PGMPhysGCPtr2CCPtr(pVCpu, pTrapStackGC, (void **)&pTrapStack, &PageMappingLock);
710 if (RT_FAILURE(rc))
711 {
712 AssertRC(rc);
713 goto failure;
714 }
715#endif
716 if (rc == VINF_SUCCESS)
717 {
718 /** if eflags.Bits.u1VM then push gs, fs, ds, es */
719 if (eflags.Bits.u1VM)
720 {
721 Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
722 pTrapStack[--idx] = pRegFrame->gs.Sel;
723 pTrapStack[--idx] = pRegFrame->fs.Sel;
724 pTrapStack[--idx] = pRegFrame->ds.Sel;
725 pTrapStack[--idx] = pRegFrame->es.Sel;
726
727 /* clear ds, es, fs & gs in current context */
728 pRegFrame->ds.Sel = pRegFrame->es.Sel = pRegFrame->fs.Sel = pRegFrame->gs.Sel = 0;
729 }
730 else
731 Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
732
733 if (!fConforming && dpl < cpl)
734 {
735#ifdef IN_RC /* Only in RC we still see tracing of our ring modifications. */
736 if ( (pRegFrame->ss.Sel & X86_SEL_RPL) == 1
737 && !eflags.Bits.u1VM)
738 pTrapStack[--idx] = pRegFrame->ss.Sel & ~1; /* Mask away traces of raw ring 0 execution (ring 1). */
739 else if ( EMIsRawRing1Enabled(pVM)
740 && (pRegFrame->ss.Sel & X86_SEL_RPL) == 2)
741 pTrapStack[--idx] = (pRegFrame->ss.Sel & ~2) | 1; /* Mask away traces of raw ring 1 execution (ring 2). */
742 else
743#endif /* IN_RC */
744 pTrapStack[--idx] = pRegFrame->ss.Sel;
745
746 pTrapStack[--idx] = pRegFrame->esp;
747 }
748
749 /* Note: We use the eflags copy, that includes the virtualized bits! */
750 /* Note: Not really necessary as we grab include those bits in the trap/irq handler trampoline */
751 pTrapStack[--idx] = eflags.u32;
752
753#ifdef IN_RC /* Only in RC mode we still see tracing of our ring modifications */
754 if ( (pRegFrame->cs.Sel & X86_SEL_RPL) == 1
755 && !eflags.Bits.u1VM)
756 pTrapStack[--idx] = pRegFrame->cs.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */
757 else if ( EMIsRawRing1Enabled(pVM)
758 && (pRegFrame->cs.Sel & X86_SEL_RPL) == 2)
759 pTrapStack[--idx] = (pRegFrame->cs.Sel & ~2) | 1; /* Mask away traces of raw ring 1 execution (ring 2). */
760 else
761#endif /* IN_RC */
762 pTrapStack[--idx] = pRegFrame->cs.Sel;
763
764 if (enmType == TRPM_SOFTWARE_INT)
765 {
766 Assert(cbInstr);
767 pTrapStack[--idx] = pRegFrame->eip + cbInstr; /* return address = next instruction */
768 }
769 else
770 pTrapStack[--idx] = pRegFrame->eip;
771
772 if (enmError == TRPM_TRAP_HAS_ERRORCODE)
773 {
774 pTrapStack[--idx] = pVCpu->trpm.s.uActiveErrorCode;
775 }
776
777 Assert(esp_r0 > -idx*sizeof(uint32_t));
778 /* Adjust ESP accordingly */
779 esp_r0 += idx*sizeof(uint32_t);
780
781 /* Mask away dangerous flags for the trap/interrupt handler. */
782 eflags.u32 &= ~(X86_EFL_TF | X86_EFL_VM | X86_EFL_RF | X86_EFL_NT);
783#ifdef DEBUG
784 if (DBGFIsStepping(pVCpu))
785 eflags.u32 |= X86_EFL_TF;
786#endif
787
788 /* Turn off interrupts for interrupt gates. */
789 if (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
790 eflags.Bits.u1IF = 0;
791
792 CPUMRawSetEFlags(pVCpu, eflags.u32);
793
794#ifdef DEBUG
795 for (int j = idx; j < 0; j++)
796 LogFlow(("Stack %RRv pos %02d: %08x\n", &pTrapStack[j], j, pTrapStack[j]));
797
798 Log4(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
799 "eip=%08x esp=%08x ebp=%08x iopl=%d\n"
800 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n",
801 pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx, pRegFrame->esi, pRegFrame->edi,
802 pRegFrame->eip, pRegFrame->esp, pRegFrame->ebp, eflags.Bits.u2IOPL,
803 pRegFrame->cs.Sel, pRegFrame->ds.Sel, pRegFrame->es.Sel,
804 pRegFrame->fs.Sel, pRegFrame->gs.Sel, eflags.u32));
805#endif
806
807 Log(("TRPM: PATM Handler %RRv Adjusted stack %08X new EFLAGS=%08X/%08x idx=%d dpl=%d cpl=%d\n",
808 pVM->trpm.s.aGuestTrapHandler[iGate], esp_r0, eflags.u32, CPUMRawGetEFlags(pVCpu), idx, dpl, cpl));
809
810 /* Make sure the internal guest context structure is up-to-date. */
811 if (iGate == X86_XCPT_PF)
812 CPUMSetGuestCR2(pVCpu, pVCpu->trpm.s.uActiveCR2);
813
814#ifdef IN_RC
815 /* paranoia */
816 Assert(pRegFrame->eflags.Bits.u1IF == 1);
817 eflags.Bits.u1IF = 1;
818 Assert(pRegFrame->eflags.Bits.u2IOPL == 0);
819 eflags.Bits.u2IOPL = 0;
820
821 Assert(eflags.Bits.u1IF);
822 Assert(eflags.Bits.u2IOPL == 0);
823 STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF(paStatForwardedIRQ)[iGate]);
824 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
825 if (iOrgTrap >= 0 && iOrgTrap < (int)RT_ELEMENTS(pVM->trpm.s.aStatGCTraps))
826 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[iOrgTrap], o);
827
828 PGMRZDynMapReleaseAutoSet(pVCpu);
829 CPUMGCCallGuestTrapHandler(pRegFrame, GuestIdte.Gen.u16SegSel | 1, pVM->trpm.s.aGuestTrapHandler[iGate],
830 eflags.u32, ss_r0, (RTRCPTR)esp_r0);
831 /* does not return */
832#else
833
834 Assert(!CPUMIsGuestInRawMode(pVCpu));
835 pRegFrame->eflags.u32 = eflags.u32;
836 pRegFrame->eip = pVM->trpm.s.aGuestTrapHandler[iGate];
837 pRegFrame->cs.Sel = GuestIdte.Gen.u16SegSel;
838 pRegFrame->esp = esp_r0;
839 pRegFrame->ss.Sel = ss_r0 & ~X86_SEL_RPL; /* set rpl to ring 0 */
840 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
841 PGMPhysReleasePageMappingLock(pVM, &PageMappingLock);
842 NOREF(iOrgTrap);
843 return VINF_SUCCESS;
844#endif
845 }
846 else
847 Log(("TRAP%02X: PGMVerifyAccess %RGv failed with %Rrc -> forward to REM\n", iGate, pTrapStackGC, rc));
848 }
849 else
850 Log(("SELMValidateAndConvertCSAddr failed with %Rrc\n", rc));
851 }
852 else
853 Log(("MMRamRead %RGv size %d failed with %Rrc\n", (RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate, sizeof(GuestIdte), rc));
854 }
855 else
856 {
857 Log(("Refused to forward trap: eflags=%08x IF=%d\n", eflags.u32, eflags.Bits.u1IF));
858#ifdef VBOX_WITH_STATISTICS
859 if (pVM->trpm.s.aGuestTrapHandler[iGate] == TRPM_INVALID_HANDLER)
860 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
861 else if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
862 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailPatchAddr);
863#endif
864 }
865failure:
866 STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF_Z(StatForwardFail));
867 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
868
869 Log(("TRAP%02X: forwarding to REM (ss rpl=%d eflags=%08X VMIF=%d handler=%08X\n", iGate, pRegFrame->ss.Sel & X86_SEL_RPL, pRegFrame->eflags.u32, PATMAreInterruptsEnabledByCtx(pVM, CPUMCTX_FROM_CORE(pRegFrame)), pVM->trpm.s.aGuestTrapHandler[iGate]));
870#endif
871 return VINF_EM_RAW_GUEST_TRAP;
872}
873#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
874
875
876/**
877 * Raises a cpu exception which doesn't take an error code.
878 *
879 * This function may or may not dispatch the exception before returning.
880 *
881 * @returns VBox status code fit for scheduling.
882 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
883 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
884 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
885 *
886 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
887 * @param pCtxCore The CPU context core.
888 * @param enmXcpt The exception.
889 */
890VMMDECL(int) TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt)
891{
892 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt));
893 NOREF(pCtxCore);
894/** @todo dispatch the trap. */
895 pVCpu->trpm.s.uActiveVector = enmXcpt;
896 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
897 pVCpu->trpm.s.uActiveErrorCode = 0xdeadbeef;
898 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
899 pVCpu->trpm.s.cbInstr = UINT8_MAX;
900 return VINF_EM_RAW_GUEST_TRAP;
901}
902
903
904/**
905 * Raises a cpu exception with an errorcode.
906 *
907 * This function may or may not dispatch the exception before returning.
908 *
909 * @returns VBox status code fit for scheduling.
910 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
911 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
912 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
913 *
914 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
915 * @param pCtxCore The CPU context core.
916 * @param enmXcpt The exception.
917 * @param uErr The error code.
918 */
919VMMDECL(int) TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr)
920{
921 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr));
922 NOREF(pCtxCore);
923/** @todo dispatch the trap. */
924 pVCpu->trpm.s.uActiveVector = enmXcpt;
925 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
926 pVCpu->trpm.s.uActiveErrorCode = uErr;
927 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
928 pVCpu->trpm.s.cbInstr = UINT8_MAX;
929 return VINF_EM_RAW_GUEST_TRAP;
930}
931
932
933/**
934 * Raises a cpu exception with an errorcode and CR2.
935 *
936 * This function may or may not dispatch the exception before returning.
937 *
938 * @returns VBox status code fit for scheduling.
939 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
940 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
941 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
942 *
943 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
944 * @param pCtxCore The CPU context core.
945 * @param enmXcpt The exception.
946 * @param uErr The error code.
947 * @param uCR2 The CR2 value.
948 */
949VMMDECL(int) TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2)
950{
951 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr, uCR2));
952 NOREF(pCtxCore);
953/** @todo dispatch the trap. */
954 pVCpu->trpm.s.uActiveVector = enmXcpt;
955 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
956 pVCpu->trpm.s.uActiveErrorCode = uErr;
957 pVCpu->trpm.s.uActiveCR2 = uCR2;
958 pVCpu->trpm.s.cbInstr = UINT8_MAX;
959 return VINF_EM_RAW_GUEST_TRAP;
960}
961
962
963#ifdef VBOX_WITH_RAW_MODE
964/**
965 * Clear guest trap/interrupt gate handler
966 *
967 * @returns VBox status code.
968 * @param pVM The cross context VM structure.
969 * @param iTrap Interrupt/trap number.
970 */
971VMMDECL(int) trpmClearGuestTrapHandler(PVM pVM, unsigned iTrap)
972{
973 AssertReturn(VM_IS_RAW_MODE_ENABLED(pVM), VERR_TRPM_HM_IPE);
974 AssertMsgReturn(iTrap < RT_ELEMENTS(pVM->trpm.s.aIdt), ("Illegal gate number %d!\n", iTrap), VERR_INVALID_PARAMETER);
975
976 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
977# ifdef IN_RING3
978 trpmR3ClearPassThroughHandler(pVM, iTrap);
979# else
980 AssertFailed();
981# endif
982
983 pVM->trpm.s.aGuestTrapHandler[iTrap] = TRPM_INVALID_HANDLER;
984 return VINF_SUCCESS;
985}
986#endif /* VBOX_WITH_RAW_MODE */
987
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