VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/TRPMAll.cpp@ 43667

Last change on this file since 43667 was 42776, checked in by vboxsync, 12 years ago

TRPMForwardTrap: Logging/Assertions.
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1/* $Id: TRPMAll.cpp 42776 2012-08-11 20:21:47Z vboxsync $ */
2/** @file
3 * TRPM - Trap Monitor - Any Context.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_TRPM
23#include <VBox/vmm/trpm.h>
24#include <VBox/vmm/pgm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/patm.h>
27#include <VBox/vmm/selm.h>
28#include <VBox/vmm/stam.h>
29#include "TRPMInternal.h"
30#include <VBox/vmm/vm.h>
31#include <VBox/err.h>
32#include <VBox/vmm/em.h>
33#include <VBox/log.h>
34#include <iprt/assert.h>
35#include <iprt/asm.h>
36#include <iprt/asm-amd64-x86.h>
37#include <iprt/param.h>
38#include <iprt/x86.h>
39#include "internal/pgm.h"
40
41
42
43/**
44 * Query info about the current active trap/interrupt.
45 * If no trap is active active an error code is returned.
46 *
47 * @returns VBox status code.
48 * @param pVCpu Pointer to the VMCPU.
49 * @param pu8TrapNo Where to store the trap number.
50 * @param pEnmType Where to store the trap type
51 */
52VMMDECL(int) TRPMQueryTrap(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType)
53{
54 /*
55 * Check if we have a trap at present.
56 */
57 if (pVCpu->trpm.s.uActiveVector != ~0U)
58 {
59 if (pu8TrapNo)
60 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
61 if (pEnmType)
62 *pEnmType = pVCpu->trpm.s.enmActiveType;
63 return VINF_SUCCESS;
64 }
65
66 return VERR_TRPM_NO_ACTIVE_TRAP;
67}
68
69
70/**
71 * Gets the trap number for the current trap.
72 *
73 * The caller is responsible for making sure there is an active trap which
74 * takes an error code when making this request.
75 *
76 * @returns The current trap number.
77 * @param pVCpu Pointer to the VMCPU.
78 */
79VMMDECL(uint8_t) TRPMGetTrapNo(PVMCPU pVCpu)
80{
81 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
82 return (uint8_t)pVCpu->trpm.s.uActiveVector;
83}
84
85
86/**
87 * Gets the error code for the current trap.
88 *
89 * The caller is responsible for making sure there is an active trap which
90 * takes an error code when making this request.
91 *
92 * @returns Error code.
93 * @param pVCpu Pointer to the VMCPU.
94 */
95VMMDECL(RTGCUINT) TRPMGetErrorCode(PVMCPU pVCpu)
96{
97 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
98#ifdef VBOX_STRICT
99 switch (pVCpu->trpm.s.uActiveVector)
100 {
101 case 0x0a:
102 case 0x0b:
103 case 0x0c:
104 case 0x0d:
105 case 0x0e:
106 case 0x11:
107 case 0x08:
108 break;
109 default:
110 AssertMsgFailed(("This trap (%#x) doesn't have any error code\n", pVCpu->trpm.s.uActiveVector));
111 break;
112 }
113#endif
114 return pVCpu->trpm.s.uActiveErrorCode;
115}
116
117
118/**
119 * Gets the fault address for the current trap.
120 *
121 * The caller is responsible for making sure there is an active trap 0x0e when
122 * making this request.
123 *
124 * @returns Fault address associated with the trap.
125 * @param pVCpu Pointer to the VMCPU.
126 */
127VMMDECL(RTGCUINTPTR) TRPMGetFaultAddress(PVMCPU pVCpu)
128{
129 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
130 AssertMsg(pVCpu->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n"));
131 return pVCpu->trpm.s.uActiveCR2;
132}
133
134
135/**
136 * Clears the current active trap/exception/interrupt.
137 *
138 * The caller is responsible for making sure there is an active trap
139 * when making this request.
140 *
141 * @returns VBox status code.
142 * @param pVCpu Pointer to the VMCPU.
143 */
144VMMDECL(int) TRPMResetTrap(PVMCPU pVCpu)
145{
146 /*
147 * Cannot reset non-existing trap!
148 */
149 if (pVCpu->trpm.s.uActiveVector == ~0U)
150 {
151 AssertMsgFailed(("No active trap!\n"));
152 return VERR_TRPM_NO_ACTIVE_TRAP;
153 }
154
155 /*
156 * Reset it.
157 */
158 pVCpu->trpm.s.uActiveVector = ~0U;
159 return VINF_SUCCESS;
160}
161
162
163/**
164 * Assert trap/exception/interrupt.
165 *
166 * The caller is responsible for making sure there is no active trap
167 * when making this request.
168 *
169 * @returns VBox status code.
170 * @param pVCpu Pointer to the VMCPU.
171 * @param u8TrapNo The trap vector to assert.
172 * @param enmType Trap type.
173 */
174VMMDECL(int) TRPMAssertTrap(PVMCPU pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType)
175{
176 Log2(("TRPMAssertTrap: u8TrapNo=%02x type=%d\n", u8TrapNo, enmType));
177
178 /*
179 * Cannot assert a trap when one is already active.
180 */
181 if (pVCpu->trpm.s.uActiveVector != ~0U)
182 {
183 AssertMsgFailed(("CPU%d: Active trap %#x\n", pVCpu->idCpu, pVCpu->trpm.s.uActiveVector));
184 return VERR_TRPM_ACTIVE_TRAP;
185 }
186
187 pVCpu->trpm.s.uActiveVector = u8TrapNo;
188 pVCpu->trpm.s.enmActiveType = enmType;
189 pVCpu->trpm.s.uActiveErrorCode = ~(RTGCUINT)0;
190 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
191 return VINF_SUCCESS;
192}
193
194
195/**
196 * Sets the error code of the current trap.
197 * (This function is for use in trap handlers and such.)
198 *
199 * The caller is responsible for making sure there is an active trap
200 * which takes an errorcode when making this request.
201 *
202 * @param pVCpu Pointer to the VMCPU.
203 * @param uErrorCode The new error code.
204 */
205VMMDECL(void) TRPMSetErrorCode(PVMCPU pVCpu, RTGCUINT uErrorCode)
206{
207 Log2(("TRPMSetErrorCode: uErrorCode=%RGv\n", uErrorCode)); /** @todo RTGCUINT mess! */
208 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
209 pVCpu->trpm.s.uActiveErrorCode = uErrorCode;
210#ifdef VBOX_STRICT
211 switch (pVCpu->trpm.s.uActiveVector)
212 {
213 case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e:
214 AssertMsg(uErrorCode != ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
215 break;
216 case 0x11: case 0x08:
217 AssertMsg(uErrorCode == 0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
218 break;
219 default:
220 AssertMsg(uErrorCode == ~(RTGCUINT)0, ("Invalid uErrorCode=%#x u8TrapNo=%d\n", uErrorCode, pVCpu->trpm.s.uActiveVector));
221 break;
222 }
223#endif
224}
225
226
227/**
228 * Sets the error code of the current trap.
229 * (This function is for use in trap handlers and such.)
230 *
231 * The caller is responsible for making sure there is an active trap 0e
232 * when making this request.
233 *
234 * @param pVCpu Pointer to the VMCPU.
235 * @param uCR2 The new fault address (cr2 register).
236 */
237VMMDECL(void) TRPMSetFaultAddress(PVMCPU pVCpu, RTGCUINTPTR uCR2)
238{
239 Log2(("TRPMSetFaultAddress: uCR2=%RGv\n", uCR2));
240 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
241 AssertMsg(pVCpu->trpm.s.uActiveVector == 0xe, ("Not trap 0e!\n"));
242 pVCpu->trpm.s.uActiveCR2 = uCR2;
243}
244
245
246/**
247 * Checks if the current active trap/interrupt/exception/fault/whatever is a software
248 * interrupt or not.
249 *
250 * The caller is responsible for making sure there is an active trap
251 * when making this request.
252 *
253 * @returns true if software interrupt, false if not.
254 *
255 * @param pVCpu Pointer to the VMCPU.
256 */
257VMMDECL(bool) TRPMIsSoftwareInterrupt(PVMCPU pVCpu)
258{
259 AssertMsg(pVCpu->trpm.s.uActiveVector != ~0U, ("No active trap!\n"));
260 return (pVCpu->trpm.s.enmActiveType == TRPM_SOFTWARE_INT);
261}
262
263
264/**
265 * Check if there is an active trap.
266 *
267 * @returns true if trap active, false if not.
268 * @param pVCpu Pointer to the VMCPU.
269 */
270VMMDECL(bool) TRPMHasTrap(PVMCPU pVCpu)
271{
272 return pVCpu->trpm.s.uActiveVector != ~0U;
273}
274
275
276/**
277 * Query all info about the current active trap/interrupt.
278 * If no trap is active active an error code is returned.
279 *
280 * @returns VBox status code.
281 * @param pVCpu Pointer to the VMCPU.
282 * @param pu8TrapNo Where to store the trap number.
283 * @param pEnmType Where to store the trap type
284 * @param puErrorCode Where to store the error code associated with some traps.
285 * ~0U is stored if the trap has no error code.
286 * @param puCR2 Where to store the CR2 associated with a trap 0E.
287 */
288VMMDECL(int) TRPMQueryTrapAll(PVMCPU pVCpu, uint8_t *pu8TrapNo, TRPMEVENT *pEnmType, PRTGCUINT puErrorCode, PRTGCUINTPTR puCR2)
289{
290 /*
291 * Check if we have a trap at present.
292 */
293 if (pVCpu->trpm.s.uActiveVector == ~0U)
294 return VERR_TRPM_NO_ACTIVE_TRAP;
295
296 if (pu8TrapNo)
297 *pu8TrapNo = (uint8_t)pVCpu->trpm.s.uActiveVector;
298 if (pEnmType)
299 *pEnmType = pVCpu->trpm.s.enmActiveType;
300 if (puErrorCode)
301 *puErrorCode = pVCpu->trpm.s.uActiveErrorCode;
302 if (puCR2)
303 *puCR2 = pVCpu->trpm.s.uActiveCR2;
304
305 return VINF_SUCCESS;
306}
307
308
309/**
310 * Save the active trap.
311 *
312 * This routine useful when doing try/catch in the hypervisor.
313 * Any function which uses temporary trap handlers should
314 * probably also use this facility to save the original trap.
315 *
316 * @param pVM Pointer to the VM.
317 */
318VMMDECL(void) TRPMSaveTrap(PVMCPU pVCpu)
319{
320 pVCpu->trpm.s.uSavedVector = pVCpu->trpm.s.uActiveVector;
321 pVCpu->trpm.s.enmSavedType = pVCpu->trpm.s.enmActiveType;
322 pVCpu->trpm.s.uSavedErrorCode = pVCpu->trpm.s.uActiveErrorCode;
323 pVCpu->trpm.s.uSavedCR2 = pVCpu->trpm.s.uActiveCR2;
324}
325
326
327/**
328 * Restore a saved trap.
329 *
330 * Multiple restores of a saved trap is possible.
331 *
332 * @param pVM Pointer to the VM.
333 */
334VMMDECL(void) TRPMRestoreTrap(PVMCPU pVCpu)
335{
336 pVCpu->trpm.s.uActiveVector = pVCpu->trpm.s.uSavedVector;
337 pVCpu->trpm.s.enmActiveType = pVCpu->trpm.s.enmSavedType;
338 pVCpu->trpm.s.uActiveErrorCode = pVCpu->trpm.s.uSavedErrorCode;
339 pVCpu->trpm.s.uActiveCR2 = pVCpu->trpm.s.uSavedCR2;
340}
341
342
343#ifdef VBOX_WITH_RAW_MODE_NOT_R0
344/**
345 * Forward trap or interrupt to the guest's handler
346 *
347 *
348 * @returns VBox status code.
349 * or does not return at all (when the trap is actually forwarded)
350 *
351 * @param pVM Pointer to the VM.
352 * @param pRegFrame Pointer to the register frame for the trap.
353 * @param iGate Trap or interrupt gate number
354 * @param cbInstr Instruction size (only relevant for software interrupts)
355 * @param enmError TRPM_TRAP_HAS_ERRORCODE or TRPM_TRAP_NO_ERRORCODE.
356 * @param enmType TRPM event type
357 * @param iOrgTrap The original trap.
358 * @internal
359 */
360VMMDECL(int) TRPMForwardTrap(PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t iGate, uint32_t cbInstr,
361 TRPMERRORCODE enmError, TRPMEVENT enmType, int32_t iOrgTrap)
362{
363#ifdef TRPM_FORWARD_TRAPS_IN_GC
364 PVM pVM = pVCpu->CTX_SUFF(pVM);
365 X86EFLAGS eflags;
366 Assert(pVM->cCpus == 1);
367
368 STAM_PROFILE_ADV_START(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
369
370# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
371 if (pRegFrame->eflags.Bits.u1VM)
372 Log(("TRPMForwardTrap-VM: eip=%04X:%04X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
373 else
374 Log(("TRPMForwardTrap: eip=%04X:%08X iGate=%d\n", pRegFrame->cs.Sel, pRegFrame->eip, iGate));
375
376 switch (iGate) {
377 case X86_XCPT_PF:
378 if (pRegFrame->eip == pVCpu->trpm.s.uActiveCR2)
379 {
380 RTGCPTR pCallerGC;
381# ifdef IN_RC
382 int rc = MMGCRamRead(pVM, &pCallerGC, (void *)pRegFrame->esp, sizeof(pCallerGC));
383# else
384 int rc = PGMPhysSimpleReadGCPtr(pVCpu, &pCallerGC, (RTGCPTR)pRegFrame->esp, sizeof(pCallerGC));
385# endif
386 if (RT_SUCCESS(rc))
387 Log(("TRPMForwardTrap: caller=%RGv\n", pCallerGC));
388 }
389 /* no break */
390 case X86_XCPT_DF:
391 case X86_XCPT_TS:
392 case X86_XCPT_NP:
393 case X86_XCPT_SS:
394 case X86_XCPT_GP:
395 case X86_XCPT_AC:
396 Assert(enmError == TRPM_TRAP_HAS_ERRORCODE || enmType == TRPM_SOFTWARE_INT);
397 break;
398
399 default:
400 Assert(enmError == TRPM_TRAP_NO_ERRORCODE);
401 break;
402 }
403# endif /* VBOX_STRICT || LOG_ENABLED */
404#ifdef IN_RC
405 AssertReturn(CPUMIsGuestInRawMode(pVCpu), VINF_EM_RESCHEDULE);
406#endif
407
408 /* Retrieve the eflags including the virtualized bits. */
409 /* Note: hackish as the cpumctxcore structure doesn't contain the right value */
410 eflags.u32 = CPUMRawGetEFlags(pVCpu);
411
412 /* VMCPU_FF_INHIBIT_INTERRUPTS should be cleared upfront or don't call this function at all for dispatching hardware interrupts. */
413 Assert(enmType != TRPM_HARDWARE_INT || !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS));
414
415 /*
416 * If it's a real guest trap and the guest's page fault handler is marked as safe for GC execution, then we call it directly.
417 * Well, only if the IF flag is set.
418 */
419 /** @todo if the trap handler was modified and marked invalid, then we should *now* go back to the host context and install a new patch. */
420 if ( pVM->trpm.s.aGuestTrapHandler[iGate]
421 && (eflags.Bits.u1IF)
422#ifndef VBOX_RAW_V86
423 && !(eflags.Bits.u1VM) /** @todo implement when needed (illegal for same privilege level transfers). */
424#endif
425 && !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
426 )
427 {
428 uint16_t cbIDT;
429 RTGCPTR GCPtrIDT = (RTGCPTR)CPUMGetGuestIDTR(pVCpu, &cbIDT);
430 uint32_t cpl;
431 VBOXIDTE GuestIdte;
432 RTGCPTR pIDTEntry;
433 int rc;
434
435 Assert(PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame));
436 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
437
438 if (GCPtrIDT && iGate * sizeof(VBOXIDTE) >= cbIDT)
439 goto failure;
440
441 /* Get the current privilege level. */
442 cpl = CPUMGetGuestCPL(pVCpu);
443
444 /*
445 * BIG TODO: The checks are not complete. see trap and interrupt dispatching section in Intel docs for details
446 * All very obscure, but still necessary.
447 * Currently only some CS & TSS selector checks are missing.
448 *
449 */
450 pIDTEntry = (RTGCPTR)((RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate);
451#ifdef IN_RC
452 rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
453#else
454 rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
455#endif
456 if (RT_FAILURE(rc))
457 {
458 /* The page might be out of sync. */ /** @todo might cross a page boundary) */
459 Log(("Page %RGv out of sync -> prefetch and try again\n", pIDTEntry));
460 rc = PGMPrefetchPage(pVCpu, pIDTEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
461 if (rc != VINF_SUCCESS)
462 {
463 Log(("TRPMForwardTrap: PGMPrefetchPage failed with rc=%Rrc\n", rc));
464 goto failure;
465 }
466#ifdef IN_RC
467 rc = MMGCRamRead(pVM, &GuestIdte, (void *)(uintptr_t)pIDTEntry, sizeof(GuestIdte));
468#else
469 rc = PGMPhysSimpleReadGCPtr(pVCpu, &GuestIdte, pIDTEntry, sizeof(GuestIdte));
470#endif
471 }
472 if ( RT_SUCCESS(rc)
473 && GuestIdte.Gen.u1Present
474 && (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_TRAP_32 || GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
475 && (GuestIdte.Gen.u2DPL == 3 || GuestIdte.Gen.u2DPL == 0)
476 && (GuestIdte.Gen.u16SegSel & 0xfffc) /* must not be zero */
477 && (enmType == TRPM_TRAP || enmType == TRPM_HARDWARE_INT || cpl <= GuestIdte.Gen.u2DPL) /* CPL <= DPL if software int */
478 )
479 {
480 RTGCPTR pHandler, dummy;
481 RTGCPTR pTrapStackGC;
482
483 pHandler = (RTGCPTR)VBOXIDTE_OFFSET(GuestIdte);
484
485 /* Note: SELMValidateAndConvertCSAddr checks for code type, memory type, selector validity. */
486 /** @todo dpl <= cpl else GPF */
487
488 /* Note: don't use current eflags as we might be in V86 mode and the IDT always contains protected mode selectors */
489 X86EFLAGS fakeflags;
490 fakeflags.u32 = 0;
491
492 rc = SELMValidateAndConvertCSAddr(pVCpu, fakeflags, 0, GuestIdte.Gen.u16SegSel, NULL, pHandler, &dummy);
493 if (rc == VINF_SUCCESS)
494 {
495 VBOXGDTR gdtr = {0, 0};
496 bool fConforming = false;
497 int idx = 0;
498 uint32_t dpl;
499 uint32_t ss_r0;
500 uint32_t esp_r0;
501 X86DESC Desc;
502 RTGCPTR pGdtEntry;
503
504 CPUMGetGuestGDTR(pVCpu, &gdtr);
505 Assert(gdtr.pGdt && gdtr.cbGdt > GuestIdte.Gen.u16SegSel);
506
507 if (!gdtr.pGdt)
508 goto failure;
509
510 pGdtEntry = gdtr.pGdt + (GuestIdte.Gen.u16SegSel >> X86_SEL_SHIFT) * sizeof(X86DESC);
511#ifdef IN_RC
512 rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
513#else
514 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
515#endif
516 if (RT_FAILURE(rc))
517 {
518 /* The page might be out of sync. */ /** @todo might cross a page boundary) */
519 Log(("Page %RGv out of sync -> prefetch and try again\n", pGdtEntry));
520 rc = PGMPrefetchPage(pVCpu, pGdtEntry); /** @todo r=bird: rainy day: this isn't entirely safe because of access bit virtualiziation and CSAM. */
521 if (rc != VINF_SUCCESS)
522 {
523 Log(("PGMPrefetchPage failed with rc=%Rrc\n", rc));
524 goto failure;
525 }
526#ifdef IN_RC
527 rc = MMGCRamRead(pVM, &Desc, (void *)(uintptr_t)pGdtEntry, sizeof(Desc));
528#else
529 rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, pGdtEntry, sizeof(Desc));
530#endif
531 if (RT_FAILURE(rc))
532 {
533 Log(("MMGCRamRead failed with %Rrc\n", rc));
534 goto failure;
535 }
536 }
537
538 if (Desc.Gen.u4Type & X86_SEL_TYPE_CONF)
539 {
540 Log(("Conforming code selector\n"));
541 fConforming = true;
542 }
543 /** @todo check descriptor type!! */
544
545 dpl = Desc.Gen.u2Dpl;
546
547 if (!fConforming && dpl < cpl) /* to inner privilege level */
548 {
549 rc = SELMGetRing1Stack(pVM, &ss_r0, &esp_r0);
550 if (RT_FAILURE(rc))
551 goto failure;
552
553 Assert((ss_r0 & X86_SEL_RPL) == 1);
554
555 if ( !esp_r0
556 || !ss_r0
557 || (ss_r0 & X86_SEL_RPL) != ((dpl == 0) ? 1 : dpl)
558 || SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
559 (PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS
560 )
561 {
562 Log(("Invalid ring 0 stack %04X:%08RX32\n", ss_r0, esp_r0));
563 goto failure;
564 }
565 }
566 else
567 if (fConforming || dpl == cpl) /* to the same privilege level */
568 {
569 ss_r0 = pRegFrame->ss.Sel;
570 esp_r0 = pRegFrame->esp;
571
572 if ( eflags.Bits.u1VM /* illegal */
573 || SELMToFlatBySelEx(pVCpu, fakeflags, ss_r0, (RTGCPTR)esp_r0, SELMTOFLAT_FLAGS_CPL1,
574 (PRTGCPTR)&pTrapStackGC, NULL) != VINF_SUCCESS)
575 {
576 AssertMsgFailed(("Invalid stack %04X:%08RX32??? (VM=%d)\n", ss_r0, esp_r0, eflags.Bits.u1VM));
577 goto failure;
578 }
579 }
580 else
581 {
582 Log(("Invalid cpl-dpl combo %d vs %d\n", cpl, dpl));
583 goto failure;
584 }
585 /*
586 * Build trap stack frame on guest handler's stack
587 */
588 uint32_t *pTrapStack;
589#ifdef IN_RC
590 Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) != 0);
591 /* Check maximum amount we need (10 when executing in V86 mode) */
592 rc = PGMVerifyAccess(pVCpu, (RTGCUINTPTR)pTrapStackGC - 10*sizeof(uint32_t), 10 * sizeof(uint32_t), X86_PTE_RW);
593 pTrapStack = (uint32_t *)(uintptr_t)pTrapStackGC;
594#else
595 Assert(eflags.Bits.u1VM || (pRegFrame->ss.Sel & X86_SEL_RPL) == 0 || (pRegFrame->ss.Sel & X86_SEL_RPL) == 3);
596 /* Check maximum amount we need (10 when executing in V86 mode) */
597 if ((pTrapStackGC >> PAGE_SHIFT) != ((pTrapStackGC - 10*sizeof(uint32_t)) >> PAGE_SHIFT)) /* fail if we cross a page boundary */
598 goto failure;
599 PGMPAGEMAPLOCK PageMappingLock;
600 rc = PGMPhysGCPtr2CCPtr(pVCpu, pTrapStackGC, (void **)&pTrapStack, &PageMappingLock);
601 if (RT_FAILURE(rc))
602 {
603 AssertRC(rc);
604 goto failure;
605 }
606#endif
607 if (rc == VINF_SUCCESS)
608 {
609 /** if eflags.Bits.u1VM then push gs, fs, ds, es */
610 if (eflags.Bits.u1VM)
611 {
612 Log(("TRAP%02X: (VM) Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
613 pTrapStack[--idx] = pRegFrame->gs.Sel;
614 pTrapStack[--idx] = pRegFrame->fs.Sel;
615 pTrapStack[--idx] = pRegFrame->ds.Sel;
616 pTrapStack[--idx] = pRegFrame->es.Sel;
617
618 /* clear ds, es, fs & gs in current context */
619 pRegFrame->ds.Sel = pRegFrame->es.Sel = pRegFrame->fs.Sel = pRegFrame->gs.Sel = 0;
620 }
621 else
622 Log(("TRAP%02X: Handler %04X:%RGv Stack %04X:%08X RPL=%d CR2=%08X\n", iGate, GuestIdte.Gen.u16SegSel, pHandler, ss_r0, esp_r0, (pRegFrame->ss.Sel & X86_SEL_RPL), pVCpu->trpm.s.uActiveCR2));
623
624 if (!fConforming && dpl < cpl)
625 {
626 if ((pRegFrame->ss.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
627 pTrapStack[--idx] = pRegFrame->ss.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */
628 else
629 pTrapStack[--idx] = pRegFrame->ss.Sel;
630
631 pTrapStack[--idx] = pRegFrame->esp;
632 }
633
634 /* Note: We use the eflags copy, that includes the virtualized bits! */
635 /* Note: Not really necessary as we grab include those bits in the trap/irq handler trampoline */
636 pTrapStack[--idx] = eflags.u32;
637
638 if ((pRegFrame->cs.Sel & X86_SEL_RPL) == 1 && !eflags.Bits.u1VM)
639 pTrapStack[--idx] = pRegFrame->cs.Sel & ~1; /* Mask away traces of raw ring execution (ring 1). */
640 else
641 pTrapStack[--idx] = pRegFrame->cs.Sel;
642
643 if (enmType == TRPM_SOFTWARE_INT)
644 {
645 Assert(cbInstr);
646 pTrapStack[--idx] = pRegFrame->eip + cbInstr; /* return address = next instruction */
647 }
648 else
649 pTrapStack[--idx] = pRegFrame->eip;
650
651 if (enmError == TRPM_TRAP_HAS_ERRORCODE)
652 {
653 pTrapStack[--idx] = pVCpu->trpm.s.uActiveErrorCode;
654 }
655
656 Assert(esp_r0 > -idx*sizeof(uint32_t));
657 /* Adjust ESP accordingly */
658 esp_r0 += idx*sizeof(uint32_t);
659
660 /* Mask away dangerous flags for the trap/interrupt handler. */
661 eflags.u32 &= ~(X86_EFL_TF | X86_EFL_VM | X86_EFL_RF | X86_EFL_NT);
662
663 /* Turn off interrupts for interrupt gates. */
664 if (GuestIdte.Gen.u5Type2 == VBOX_IDTE_TYPE2_INT_32)
665 eflags.Bits.u1IF = 0;
666
667 CPUMRawSetEFlags(pVCpu, eflags.u32);
668
669#ifdef DEBUG
670 for (int j = idx; j < 0; j++)
671 Log4(("Stack %RRv pos %02d: %08x\n", &pTrapStack[j], j, pTrapStack[j]));
672
673 Log4(("eax=%08x ebx=%08x ecx=%08x edx=%08x esi=%08x edi=%08x\n"
674 "eip=%08x esp=%08x ebp=%08x iopl=%d\n"
675 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n",
676 pRegFrame->eax, pRegFrame->ebx, pRegFrame->ecx, pRegFrame->edx, pRegFrame->esi, pRegFrame->edi,
677 pRegFrame->eip, pRegFrame->esp, pRegFrame->ebp, eflags.Bits.u2IOPL,
678 pRegFrame->cs.Sel, pRegFrame->ds.Sel, pRegFrame->es.Sel,
679 pRegFrame->fs.Sel, pRegFrame->gs.Sel, eflags.u32));
680#endif
681
682 Log(("TRPM: PATM Handler %RRv Adjusted stack %08X new EFLAGS=%08X/%08x idx=%d dpl=%d cpl=%d\n",
683 pVM->trpm.s.aGuestTrapHandler[iGate], esp_r0, eflags.u32, CPUMRawGetEFlags(pVCpu), idx, dpl, cpl));
684
685 /* Make sure the internal guest context structure is up-to-date. */
686 if (iGate == X86_XCPT_PF)
687 CPUMSetGuestCR2(pVCpu, pVCpu->trpm.s.uActiveCR2);
688
689#ifdef IN_RC
690 /* paranoia */
691 Assert(pRegFrame->eflags.Bits.u1IF == 1);
692 eflags.Bits.u1IF = 1;
693 Assert(pRegFrame->eflags.Bits.u2IOPL == 0);
694 eflags.Bits.u2IOPL = 0;
695
696 Assert(eflags.Bits.u1IF);
697 Assert(eflags.Bits.u2IOPL == 0);
698 STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF(paStatForwardedIRQ)[iGate]);
699 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
700 if (iOrgTrap >= 0 && iOrgTrap < (int)RT_ELEMENTS(pVM->trpm.s.aStatGCTraps))
701 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[iOrgTrap], o);
702
703 PGMRZDynMapReleaseAutoSet(pVCpu);
704 CPUMGCCallGuestTrapHandler(pRegFrame, GuestIdte.Gen.u16SegSel | 1, pVM->trpm.s.aGuestTrapHandler[iGate],
705 eflags.u32, ss_r0, (RTRCPTR)esp_r0);
706 /* does not return */
707#else
708
709 Assert(!CPUMIsGuestInRawMode(pVCpu));
710 pRegFrame->eflags.u32 = eflags.u32;
711 pRegFrame->eip = pVM->trpm.s.aGuestTrapHandler[iGate];
712 pRegFrame->cs.Sel = GuestIdte.Gen.u16SegSel;
713 pRegFrame->esp = esp_r0;
714 pRegFrame->ss.Sel = ss_r0 & ~X86_SEL_RPL; /* set rpl to ring 0 */
715 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
716 PGMPhysReleasePageMappingLock(pVM, &PageMappingLock);
717 NOREF(iOrgTrap);
718 return VINF_SUCCESS;
719#endif
720 }
721 else
722 Log(("TRAP%02X: PGMVerifyAccess %RGv failed with %Rrc -> forward to REM\n", iGate, pTrapStackGC, rc));
723 }
724 else
725 Log(("SELMValidateAndConvertCSAddr failed with %Rrc\n", rc));
726 }
727 else
728 Log(("MMRamRead %RGv size %d failed with %Rrc\n", (RTGCUINTPTR)GCPtrIDT + sizeof(VBOXIDTE) * iGate, sizeof(GuestIdte), rc));
729 }
730 else
731 {
732 Log(("Refused to forward trap: eflags=%08x IF=%d\n", eflags.u32, eflags.Bits.u1IF));
733#ifdef VBOX_WITH_STATISTICS
734 if (pVM->trpm.s.aGuestTrapHandler[iGate] == TRPM_INVALID_HANDLER)
735 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailNoHandler);
736 else if (PATMIsPatchGCAddr(pVM, pRegFrame->eip))
737 STAM_COUNTER_INC(&pVM->trpm.s.StatForwardFailPatchAddr);
738#endif
739 }
740failure:
741 STAM_COUNTER_INC(&pVM->trpm.s.CTX_SUFF_Z(StatForwardFail));
742 STAM_PROFILE_ADV_STOP(&pVM->trpm.s.CTX_SUFF_Z(StatForwardProf), a);
743
744 Log(("TRAP%02X: forwarding to REM (ss rpl=%d eflags=%08X VMIF=%d handler=%08X\n", iGate, pRegFrame->ss.Sel & X86_SEL_RPL, pRegFrame->eflags.u32, PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame), pVM->trpm.s.aGuestTrapHandler[iGate]));
745#endif
746 return VINF_EM_RAW_GUEST_TRAP;
747}
748#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
749
750
751/**
752 * Raises a cpu exception which doesn't take an error code.
753 *
754 * This function may or may not dispatch the exception before returning.
755 *
756 * @returns VBox status code fit for scheduling.
757 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
758 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
759 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
760 *
761 * @param pVM Pointer to the VM.
762 * @param pCtxCore The CPU context core.
763 * @param enmXcpt The exception.
764 */
765VMMDECL(int) TRPMRaiseXcpt(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt)
766{
767 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt));
768/** @todo dispatch the trap. */
769 pVCpu->trpm.s.uActiveVector = enmXcpt;
770 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
771 pVCpu->trpm.s.uActiveErrorCode = 0xdeadbeef;
772 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
773 return VINF_EM_RAW_GUEST_TRAP;
774}
775
776
777/**
778 * Raises a cpu exception with an errorcode.
779 *
780 * This function may or may not dispatch the exception before returning.
781 *
782 * @returns VBox status code fit for scheduling.
783 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
784 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
785 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
786 *
787 * @param pVM Pointer to the VM.
788 * @param pCtxCore The CPU context core.
789 * @param enmXcpt The exception.
790 * @param uErr The error code.
791 */
792VMMDECL(int) TRPMRaiseXcptErr(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr)
793{
794 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr));
795/** @todo dispatch the trap. */
796 pVCpu->trpm.s.uActiveVector = enmXcpt;
797 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
798 pVCpu->trpm.s.uActiveErrorCode = uErr;
799 pVCpu->trpm.s.uActiveCR2 = 0xdeadface;
800 return VINF_EM_RAW_GUEST_TRAP;
801}
802
803
804/**
805 * Raises a cpu exception with an errorcode and CR2.
806 *
807 * This function may or may not dispatch the exception before returning.
808 *
809 * @returns VBox status code fit for scheduling.
810 * @retval VINF_EM_RAW_GUEST_TRAP if the exception was left pending.
811 * @retval VINF_TRPM_XCPT_DISPATCHED if the exception was raised and dispatched for raw-mode execution.
812 * @retval VINF_EM_RESCHEDULE_REM if the exception was dispatched and cannot be executed in raw-mode.
813 *
814 * @param pVM Pointer to the VM.
815 * @param pCtxCore The CPU context core.
816 * @param enmXcpt The exception.
817 * @param uErr The error code.
818 * @param uCR2 The CR2 value.
819 */
820VMMDECL(int) TRPMRaiseXcptErrCR2(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, X86XCPT enmXcpt, uint32_t uErr, RTGCUINTPTR uCR2)
821{
822 LogFlow(("TRPMRaiseXcptErr: cs:eip=%RTsel:%RX32 enmXcpt=%#x uErr=%RX32 uCR2=%RGv\n", pCtxCore->cs.Sel, pCtxCore->eip, enmXcpt, uErr, uCR2));
823/** @todo dispatch the trap. */
824 pVCpu->trpm.s.uActiveVector = enmXcpt;
825 pVCpu->trpm.s.enmActiveType = TRPM_TRAP;
826 pVCpu->trpm.s.uActiveErrorCode = uErr;
827 pVCpu->trpm.s.uActiveCR2 = uCR2;
828 return VINF_EM_RAW_GUEST_TRAP;
829}
830
831
832/**
833 * Clear guest trap/interrupt gate handler
834 *
835 * @returns VBox status code.
836 * @param pVM Pointer to the VM.
837 * @param iTrap Interrupt/trap number.
838 */
839VMMDECL(int) trpmClearGuestTrapHandler(PVM pVM, unsigned iTrap)
840{
841 /*
842 * Validate.
843 */
844 if (iTrap >= RT_ELEMENTS(pVM->trpm.s.aIdt))
845 {
846 AssertMsg(iTrap < TRPM_HANDLER_INT_BASE, ("Illegal gate number %d!\n", iTrap));
847 return VERR_INVALID_PARAMETER;
848 }
849
850 if (ASMBitTest(&pVM->trpm.s.au32IdtPatched[0], iTrap))
851#ifdef IN_RING3
852 trpmR3ClearPassThroughHandler(pVM, iTrap);
853#else
854 AssertFailed();
855#endif
856
857 pVM->trpm.s.aGuestTrapHandler[iTrap] = TRPM_INVALID_HANDLER;
858 return VINF_SUCCESS;
859}
860
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