[9034] | 1 | /* $Id: HMAll.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
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| 2 | /** @file
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[43387] | 3 | * HM - All contexts.
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[9034] | 4 | */
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| 5 |
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| 6 | /*
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[96407] | 7 | * Copyright (C) 2006-2022 Oracle and/or its affiliates.
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[9034] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[9034] | 26 | */
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| 27 |
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| 28 |
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[57358] | 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[43387] | 32 | #define LOG_GROUP LOG_GROUP_HM
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[73266] | 33 | #define VMCPU_INCL_CPUM_GST_CTX
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[43387] | 34 | #include <VBox/vmm/hm.h>
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[35346] | 35 | #include <VBox/vmm/pgm.h>
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[43387] | 36 | #include "HMInternal.h"
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[80268] | 37 | #include <VBox/vmm/vmcc.h>
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[43387] | 38 | #include <VBox/vmm/hm_vmx.h>
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| 39 | #include <VBox/vmm/hm_svm.h>
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[76454] | 40 | #include <iprt/errcore.h>
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[9034] | 41 | #include <VBox/log.h>
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| 42 | #include <iprt/param.h>
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| 43 | #include <iprt/assert.h>
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| 44 | #include <iprt/asm.h>
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| 45 | #include <iprt/string.h>
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[47619] | 46 | #include <iprt/thread.h>
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[37955] | 47 | #include <iprt/x86.h>
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[9034] | 48 |
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[42188] | 49 |
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[76993] | 50 | /*********************************************************************************************************************************
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| 51 | * Global Variables *
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| 52 | *********************************************************************************************************************************/
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| 53 | #define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
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| 54 | #define EXIT_REASON_NIL() NULL
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| 55 |
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| 56 | /** Exit reason descriptions for VT-x, used to describe statistics and exit
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| 57 | * history. */
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| 58 | static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
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| 59 | {
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| 60 | EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
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| 61 | EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
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| 62 | EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
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| 63 | EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
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| 64 | EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
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| 65 | EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
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| 66 | EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
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| 67 | EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
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| 68 | EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
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| 69 | EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
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| 70 | EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
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[79828] | 71 | EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instruction."),
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[76993] | 72 | EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
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| 73 | EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
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| 74 | EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
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[79828] | 75 | EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMC instruction."),
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[76993] | 76 | EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
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| 77 | EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
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| 78 | EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
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| 79 | EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
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| 80 | EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
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| 81 | EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
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| 82 | EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
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| 83 | EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
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| 84 | EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
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| 85 | EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
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| 86 | EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
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| 87 | EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
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| 88 | EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
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| 89 | EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
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| 90 | EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
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| 91 | EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
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| 92 | EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
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| 93 | EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
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| 94 | EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
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| 95 | EXIT_REASON_NIL(),
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| 96 | EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
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| 97 | EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
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| 98 | EXIT_REASON_NIL(),
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| 99 | EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
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| 100 | EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
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| 101 | EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
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| 102 | EXIT_REASON_NIL(),
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| 103 | EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
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| 104 | EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
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| 105 | EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
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| 106 | EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
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| 107 | EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
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| 108 | EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
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| 109 | EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
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| 110 | EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
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| 111 | EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
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| 112 | EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
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| 113 | EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
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| 114 | EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
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| 115 | EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
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| 116 | EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
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| 117 | EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
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| 118 | EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
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| 119 | EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
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| 120 | EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
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| 121 | EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
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| 122 | EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
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| 123 | EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
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[78650] | 124 | EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction."),
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| 125 | EXIT_REASON_NIL(),
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| 126 | EXIT_REASON(VMX_EXIT_SPP_EVENT , 66, "SPP-related event."),
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| 127 | EXIT_REASON(VMX_EXIT_UMWAIT , 67, "UMWAIT instruction."),
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| 128 | EXIT_REASON(VMX_EXIT_TPAUSE , 68, "TPAUSE instruction.")
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[76993] | 129 | };
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| 130 | /** Array index of the last valid VT-x exit reason. */
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[78650] | 131 | #define MAX_EXITREASON_VTX 68
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[76993] | 132 |
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| 133 | /** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
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| 134 | * statistics and exit history.
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| 135 | *
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| 136 | * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
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| 137 | * this array doesn't contain the entire set of exit reasons, we
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| 138 | * handle them via hmSvmGetSpecialExitReasonDesc(). */
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| 139 | static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
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| 140 | {
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[81245] | 141 | EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
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| 142 | EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
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| 143 | EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
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| 144 | EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
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| 145 | EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
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| 146 | EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
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| 147 | EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
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| 148 | EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
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| 149 | EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
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| 150 | EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
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| 151 | EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
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| 152 | EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
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| 153 | EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
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| 154 | EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
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| 155 | EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
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| 156 | EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
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| 157 | EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
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| 158 | EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
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| 159 | EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
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| 160 | EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
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| 161 | EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
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| 162 | EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
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| 163 | EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
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| 164 | EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
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| 165 | EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
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| 166 | EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
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| 167 | EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
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| 168 | EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
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| 169 | EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
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| 170 | EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
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| 171 | EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
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| 172 | EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
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| 173 | EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
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| 174 | EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
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| 175 | EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
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| 176 | EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
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| 177 | EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
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| 178 | EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
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| 179 | EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
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| 180 | EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
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| 181 | EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
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| 182 | EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
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| 183 | EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
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| 184 | EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
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| 185 | EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
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| 186 | EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
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| 187 | EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
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| 188 | EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
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| 189 | EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
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| 190 | EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
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| 191 | EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
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| 192 | EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
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| 193 | EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
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| 194 | EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
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| 195 | EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
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| 196 | EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
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| 197 | EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
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| 198 | EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
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| 199 | EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
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| 200 | EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
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| 201 | EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
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| 202 | EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
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| 203 | EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
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| 204 | EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
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| 205 | EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
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| 206 | EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
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| 207 | EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
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| 208 | EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
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| 209 | EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
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| 210 | EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
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| 211 | EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
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| 212 | EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
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| 213 | EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
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| 214 | EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
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| 215 | EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
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| 216 | EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
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| 217 | EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
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| 218 | EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
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| 219 | EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
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| 220 | EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
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| 221 | EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
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| 222 | EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
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| 223 | EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
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| 224 | EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
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| 225 | EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
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| 226 | EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
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| 227 | EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
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| 228 | EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
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| 229 | EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
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| 230 | EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
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| 231 | EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
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| 232 | EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
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| 233 | EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
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| 234 | EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
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| 235 | EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
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| 236 | EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
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| 237 | EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
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| 238 | EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
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| 239 | EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
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| 240 | EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
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| 241 | EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
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| 242 | EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE , 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
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| 243 | EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
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| 244 | EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
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| 245 | EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
|
---|
| 246 | EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
|
---|
| 247 | EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
|
---|
| 248 | EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
|
---|
| 249 | EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
|
---|
| 250 | EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
|
---|
| 251 | EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
|
---|
| 252 | EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
|
---|
| 253 | EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
|
---|
| 254 | EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
|
---|
| 255 | EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
|
---|
| 256 | EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
|
---|
| 257 | EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
|
---|
| 258 | EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
|
---|
| 259 | EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
|
---|
| 260 | EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
|
---|
| 261 | EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
|
---|
| 262 | EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
|
---|
| 263 | EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
|
---|
| 264 | EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
|
---|
| 265 | EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
|
---|
| 266 | EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
|
---|
| 267 | EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
|
---|
| 268 | EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
|
---|
| 269 | EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
|
---|
| 270 | EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
|
---|
| 271 | EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
|
---|
| 272 | EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
|
---|
| 273 | EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
|
---|
| 274 | EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
|
---|
| 275 | EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
|
---|
| 276 | EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
|
---|
| 277 | EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
|
---|
| 278 | EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
|
---|
| 279 | EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
|
---|
| 280 | EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
|
---|
| 281 | EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
|
---|
| 282 | EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
|
---|
| 283 | EXIT_REASON(SVM_EXIT_RDPRU , 142, "RDPRU instruction."),
|
---|
| 284 | EXIT_REASON(SVM_EXIT_WRITE_EFER_TRAP, 143, "Write EFER (trap-like)."),
|
---|
| 285 | EXIT_REASON(SVM_EXIT_WRITE_CR0_TRAP , 144, "Write CR0 (trap-like)."),
|
---|
| 286 | EXIT_REASON(SVM_EXIT_WRITE_CR1_TRAP , 145, "Write CR1 (trap-like)."),
|
---|
| 287 | EXIT_REASON(SVM_EXIT_WRITE_CR2_TRAP , 146, "Write CR2 (trap-like)."),
|
---|
| 288 | EXIT_REASON(SVM_EXIT_WRITE_CR3_TRAP , 147, "Write CR3 (trap-like)."),
|
---|
| 289 | EXIT_REASON(SVM_EXIT_WRITE_CR4_TRAP , 148, "Write CR4 (trap-like)."),
|
---|
| 290 | EXIT_REASON(SVM_EXIT_WRITE_CR5_TRAP , 149, "Write CR5 (trap-like)."),
|
---|
| 291 | EXIT_REASON(SVM_EXIT_WRITE_CR6_TRAP , 150, "Write CR6 (trap-like)."),
|
---|
| 292 | EXIT_REASON(SVM_EXIT_WRITE_CR7_TRAP , 151, "Write CR7 (trap-like)."),
|
---|
| 293 | EXIT_REASON(SVM_EXIT_WRITE_CR8_TRAP , 152, "Write CR8 (trap-like)."),
|
---|
| 294 | EXIT_REASON(SVM_EXIT_WRITE_CR9_TRAP , 153, "Write CR9 (trap-like)."),
|
---|
| 295 | EXIT_REASON(SVM_EXIT_WRITE_CR10_TRAP, 154, "Write CR10 (trap-like)."),
|
---|
| 296 | EXIT_REASON(SVM_EXIT_WRITE_CR11_TRAP, 155, "Write CR11 (trap-like)."),
|
---|
| 297 | EXIT_REASON(SVM_EXIT_WRITE_CR12_TRAP, 156, "Write CR12 (trap-like)."),
|
---|
| 298 | EXIT_REASON(SVM_EXIT_WRITE_CR13_TRAP, 157, "Write CR13 (trap-like)."),
|
---|
| 299 | EXIT_REASON(SVM_EXIT_WRITE_CR14_TRAP, 158, "Write CR14 (trap-like)."),
|
---|
| 300 | EXIT_REASON(SVM_EXIT_WRITE_CR15_TRAP, 159, "Write CR15 (trap-like)."),
|
---|
| 301 | EXIT_REASON_NIL() ,
|
---|
| 302 | EXIT_REASON_NIL() ,
|
---|
| 303 | EXIT_REASON_NIL() ,
|
---|
| 304 | EXIT_REASON(SVM_EXIT_MCOMMIT , 163, "MCOMMIT instruction."),
|
---|
[76993] | 305 | };
|
---|
| 306 | /** Array index of the last valid AMD-V exit reason. */
|
---|
[81245] | 307 | #define MAX_EXITREASON_AMDV 163
|
---|
[76993] | 308 |
|
---|
| 309 | /** Special exit reasons not covered in the array above. */
|
---|
| 310 | #define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
|
---|
| 311 | #define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
|
---|
| 312 | #define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
|
---|
| 313 |
|
---|
[9034] | 314 | /**
|
---|
[76993] | 315 | * Gets the SVM exit reason if it's one of the reasons not present in the @c
|
---|
| 316 | * g_apszSvmExitReasons array.
|
---|
| 317 | *
|
---|
| 318 | * @returns The exit reason or NULL if unknown.
|
---|
| 319 | * @param uExit The exit.
|
---|
| 320 | */
|
---|
| 321 | DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
|
---|
| 322 | {
|
---|
| 323 | switch (uExit)
|
---|
| 324 | {
|
---|
| 325 | case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
|
---|
| 326 | case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
|
---|
| 327 | case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
|
---|
| 328 | }
|
---|
| 329 | return EXIT_REASON_NIL();
|
---|
| 330 | }
|
---|
| 331 | #undef EXIT_REASON_NIL
|
---|
| 332 | #undef EXIT_REASON
|
---|
| 333 |
|
---|
| 334 |
|
---|
| 335 | /**
|
---|
[45701] | 336 | * Checks whether HM (VT-x/AMD-V) is being used by this VM.
|
---|
[45618] | 337 | *
|
---|
[58126] | 338 | * @retval true if used.
|
---|
| 339 | * @retval false if software virtualization (raw-mode) is used.
|
---|
[58122] | 340 | * @param pVM The cross context VM structure.
|
---|
[45618] | 341 | * @sa HMIsEnabled, HMR3IsEnabled
|
---|
| 342 | * @internal
|
---|
| 343 | */
|
---|
| 344 | VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
|
---|
| 345 | {
|
---|
[70948] | 346 | Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
|
---|
[45618] | 347 | return pVM->fHMEnabled;
|
---|
| 348 | }
|
---|
| 349 |
|
---|
| 350 |
|
---|
| 351 | /**
|
---|
[73617] | 352 | * Checks if the guest is in a suitable state for hardware-assisted execution.
|
---|
| 353 | *
|
---|
| 354 | * @returns @c true if it is suitable, @c false otherwise.
|
---|
[80281] | 355 | * @param pVM The cross context VM structure.
|
---|
[73617] | 356 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 357 | * @param pCtx Pointer to the guest CPU context.
|
---|
| 358 | *
|
---|
| 359 | * @remarks @a pCtx can be a partial context created and not necessarily the same as
|
---|
| 360 | * pVCpu->cpum.GstCtx.
|
---|
| 361 | */
|
---|
[80281] | 362 | VMMDECL(bool) HMCanExecuteGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
|
---|
[73617] | 363 | {
|
---|
| 364 | Assert(HMIsEnabled(pVM));
|
---|
| 365 |
|
---|
| 366 | #ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
|
---|
| 367 | if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
|
---|
[76797] | 368 | || CPUMIsGuestInVmxNonRootMode(pCtx))
|
---|
[73617] | 369 | {
|
---|
| 370 | LogFunc(("In nested-guest mode - returning false"));
|
---|
| 371 | return false;
|
---|
| 372 | }
|
---|
| 373 | #endif
|
---|
| 374 |
|
---|
| 375 | /* AMD-V supports real & protected mode with or without paging. */
|
---|
| 376 | if (pVM->hm.s.svm.fEnabled)
|
---|
| 377 | {
|
---|
| 378 | pVCpu->hm.s.fActive = true;
|
---|
| 379 | return true;
|
---|
| 380 | }
|
---|
| 381 |
|
---|
[80268] | 382 | bool rc = HMCanExecuteVmxGuest(pVM, pVCpu, pCtx);
|
---|
[77589] | 383 | LogFlowFunc(("returning %RTbool\n", rc));
|
---|
| 384 | return rc;
|
---|
[73617] | 385 | }
|
---|
| 386 |
|
---|
| 387 |
|
---|
| 388 | /**
|
---|
[56025] | 389 | * Queues a guest page for invalidation.
|
---|
[19910] | 390 | *
|
---|
| 391 | * @returns VBox status code.
|
---|
[58123] | 392 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[57482] | 393 | * @param GCVirt Page to invalidate.
|
---|
[19910] | 394 | */
|
---|
[43387] | 395 | static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
|
---|
[19910] | 396 | {
|
---|
| 397 | /* Nothing to do if a TLB flush is already pending */
|
---|
[46420] | 398 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
|
---|
[19910] | 399 | return;
|
---|
| 400 | VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
|
---|
[39078] | 401 | NOREF(GCVirt);
|
---|
[19910] | 402 | }
|
---|
| 403 |
|
---|
[51560] | 404 |
|
---|
[19910] | 405 | /**
|
---|
[56025] | 406 | * Invalidates a guest page.
|
---|
[9034] | 407 | *
|
---|
| 408 | * @returns VBox status code.
|
---|
[58123] | 409 | * @param pVCpu The cross context virtual CPU structure.
|
---|
[57482] | 410 | * @param GCVirt Page to invalidate.
|
---|
[9034] | 411 | */
|
---|
[80281] | 412 | VMM_INT_DECL(int) HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
|
---|
[9034] | 413 | {
|
---|
[43387] | 414 | STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
|
---|
[9034] | 415 | #ifdef IN_RING0
|
---|
[72643] | 416 | return HMR0InvalidatePage(pVCpu, GCVirt);
|
---|
[39038] | 417 | #else
|
---|
[43387] | 418 | hmQueueInvlPage(pVCpu, GCVirt);
|
---|
[9034] | 419 | return VINF_SUCCESS;
|
---|
[39038] | 420 | #endif
|
---|
[9034] | 421 | }
|
---|
| 422 |
|
---|
[51560] | 423 |
|
---|
[58123] | 424 | #ifdef IN_RING0
|
---|
[51560] | 425 |
|
---|
[23200] | 426 | /**
|
---|
[26152] | 427 | * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
|
---|
[23200] | 428 | *
|
---|
| 429 | */
|
---|
[43387] | 430 | static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
|
---|
[23200] | 431 | {
|
---|
[39078] | 432 | NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
|
---|
[23200] | 433 | return;
|
---|
| 434 | }
|
---|
| 435 |
|
---|
[57482] | 436 |
|
---|
[23200] | 437 | /**
|
---|
[37386] | 438 | * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
|
---|
[23200] | 439 | */
|
---|
[87480] | 440 | static void hmR0PokeCpu(PVMCPUCC pVCpu, RTCPUID idHostCpu)
|
---|
[23200] | 441 | {
|
---|
[87480] | 442 | uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits);
|
---|
[23366] | 443 |
|
---|
[43387] | 444 | STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
|
---|
[23200] | 445 | int rc = RTMpPokeCpu(idHostCpu);
|
---|
[43387] | 446 | STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
|
---|
[37386] | 447 |
|
---|
| 448 | /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
|
---|
| 449 | back to a less efficient implementation (broadcast). */
|
---|
[23200] | 450 | if (rc == VERR_NOT_SUPPORTED)
|
---|
[23366] | 451 | {
|
---|
[43387] | 452 | STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
|
---|
[23366] | 453 | /* synchronous. */
|
---|
[43387] | 454 | RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
|
---|
| 455 | STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
|
---|
[23366] | 456 | }
|
---|
| 457 | else
|
---|
| 458 | {
|
---|
| 459 | if (rc == VINF_SUCCESS)
|
---|
[43387] | 460 | STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
|
---|
[23366] | 461 | else
|
---|
[43387] | 462 | STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
|
---|
[26152] | 463 |
|
---|
[37389] | 464 | /** @todo If more than one CPU is going to be poked, we could optimize this
|
---|
| 465 | * operation by poking them first and wait afterwards. Would require
|
---|
| 466 | * recording who to poke and their current cWorldSwitchExits values,
|
---|
| 467 | * that's something not suitable for stack... So, pVCpu->hm.s.something
|
---|
| 468 | * then. */
|
---|
[37386] | 469 | /* Spin until the VCPU has switched back (poking is async). */
|
---|
[43387] | 470 | while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
|
---|
[87480] | 471 | && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits))
|
---|
[23366] | 472 | ASMNopPause();
|
---|
[37386] | 473 |
|
---|
[23366] | 474 | if (rc == VINF_SUCCESS)
|
---|
[43387] | 475 | STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
|
---|
[23366] | 476 | else
|
---|
[43387] | 477 | STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
|
---|
[23366] | 478 | }
|
---|
[23200] | 479 | }
|
---|
[58123] | 480 |
|
---|
[51560] | 481 | #endif /* IN_RING0 */
|
---|
[73246] | 482 |
|
---|
[65989] | 483 | /**
|
---|
| 484 | * Flushes the guest TLB.
|
---|
| 485 | *
|
---|
| 486 | * @returns VBox status code.
|
---|
| 487 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 488 | */
|
---|
[76993] | 489 | VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
|
---|
[65989] | 490 | {
|
---|
| 491 | VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
|
---|
| 492 | STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
|
---|
| 493 | return VINF_SUCCESS;
|
---|
| 494 | }
|
---|
| 495 |
|
---|
[87487] | 496 |
|
---|
[9034] | 497 | /**
|
---|
[37386] | 498 | * Poke an EMT so it can perform the appropriate TLB shootdowns.
|
---|
| 499 | *
|
---|
[58123] | 500 | * @param pVCpu The cross context virtual CPU structure of the
|
---|
| 501 | * EMT poke.
|
---|
[37386] | 502 | * @param fAccountFlushStat Whether to account the call to
|
---|
| 503 | * StatTlbShootdownFlush or StatTlbShootdown.
|
---|
| 504 | */
|
---|
[87479] | 505 | static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
|
---|
[37386] | 506 | {
|
---|
[43387] | 507 | if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
|
---|
[37386] | 508 | {
|
---|
| 509 | if (fAccountFlushStat)
|
---|
[43387] | 510 | STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
|
---|
[37386] | 511 | else
|
---|
[43387] | 512 | STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
|
---|
[37386] | 513 | #ifdef IN_RING0
|
---|
[87479] | 514 | RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
|
---|
[37386] | 515 | if (idHostCpu != NIL_RTCPUID)
|
---|
| 516 | hmR0PokeCpu(pVCpu, idHostCpu);
|
---|
| 517 | #else
|
---|
| 518 | VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
|
---|
| 519 | #endif
|
---|
| 520 | }
|
---|
| 521 | else
|
---|
[43387] | 522 | STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
|
---|
[37386] | 523 | }
|
---|
| 524 |
|
---|
| 525 |
|
---|
| 526 | /**
|
---|
[19903] | 527 | * Invalidates a guest page on all VCPUs.
|
---|
| 528 | *
|
---|
| 529 | * @returns VBox status code.
|
---|
[58122] | 530 | * @param pVM The cross context VM structure.
|
---|
[57066] | 531 | * @param GCVirt Page to invalidate.
|
---|
[19903] | 532 | */
|
---|
[80268] | 533 | VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVMCC pVM, RTGCPTR GCVirt)
|
---|
[19903] | 534 | {
|
---|
[56025] | 535 | /*
|
---|
| 536 | * The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
|
---|
| 537 | * host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
|
---|
| 538 | *
|
---|
| 539 | * This is the reason why we do not care about thread preemption here and just
|
---|
| 540 | * execute HMInvalidatePage() assuming it might be the 'right' CPU.
|
---|
| 541 | */
|
---|
[80268] | 542 | VMCPUID const idCurCpu = VMMGetCpuId(pVM);
|
---|
| 543 | STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idCurCpu)->hm.s.StatFlushPage);
|
---|
[24832] | 544 |
|
---|
[22890] | 545 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
[19910] | 546 | {
|
---|
[80281] | 547 | PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
|
---|
[19910] | 548 |
|
---|
[37386] | 549 | /* Nothing to do if a TLB flush is already pending; the VCPU should
|
---|
| 550 | have already been poked if it were active. */
|
---|
[46420] | 551 | if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
|
---|
[24833] | 552 | continue;
|
---|
| 553 |
|
---|
[19910] | 554 | if (pVCpu->idCpu == idCurCpu)
|
---|
[57066] | 555 | HMInvalidatePage(pVCpu, GCVirt);
|
---|
[19910] | 556 | else
|
---|
| 557 | {
|
---|
[57066] | 558 | hmQueueInvlPage(pVCpu, GCVirt);
|
---|
[46363] | 559 | hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
|
---|
[19910] | 560 | }
|
---|
| 561 | }
|
---|
| 562 |
|
---|
[19903] | 563 | return VINF_SUCCESS;
|
---|
| 564 | }
|
---|
| 565 |
|
---|
[23198] | 566 |
|
---|
[19903] | 567 | /**
|
---|
[46363] | 568 | * Flush the TLBs of all VCPUs.
|
---|
[19812] | 569 | *
|
---|
| 570 | * @returns VBox status code.
|
---|
[58122] | 571 | * @param pVM The cross context VM structure.
|
---|
[19812] | 572 | */
|
---|
[80268] | 573 | VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVMCC pVM)
|
---|
[19812] | 574 | {
|
---|
[22890] | 575 | if (pVM->cCpus == 1)
|
---|
[80268] | 576 | return HMFlushTlb(VMCC_GET_CPU_0(pVM));
|
---|
[19812] | 577 |
|
---|
[80268] | 578 | VMCPUID const idThisCpu = VMMGetCpuId(pVM);
|
---|
[19812] | 579 |
|
---|
[80268] | 580 | STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idThisCpu)->hm.s.StatFlushTlb);
|
---|
[24832] | 581 |
|
---|
[22890] | 582 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
|
---|
[19812] | 583 | {
|
---|
[80281] | 584 | PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
|
---|
[19812] | 585 |
|
---|
[37386] | 586 | /* Nothing to do if a TLB flush is already pending; the VCPU should
|
---|
| 587 | have already been poked if it were active. */
|
---|
[46420] | 588 | if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
|
---|
[19812] | 589 | {
|
---|
[37386] | 590 | VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
|
---|
| 591 | if (idThisCpu != idCpu)
|
---|
[46363] | 592 | hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
|
---|
[19812] | 593 | }
|
---|
| 594 | }
|
---|
[37386] | 595 |
|
---|
[19812] | 596 | return VINF_SUCCESS;
|
---|
| 597 | }
|
---|
[58123] | 598 |
|
---|
[37386] | 599 |
|
---|
[19812] | 600 | /**
|
---|
[65989] | 601 | * Invalidates a guest page by physical address.
|
---|
| 602 | *
|
---|
| 603 | * @returns VBox status code.
|
---|
| 604 | * @param pVM The cross context VM structure.
|
---|
| 605 | * @param GCPhys Page to invalidate.
|
---|
| 606 | *
|
---|
| 607 | * @remarks Assumes the current instruction references this physical page
|
---|
| 608 | * though a virtual address!
|
---|
| 609 | */
|
---|
[80268] | 610 | VMM_INT_DECL(int) HMInvalidatePhysPage(PVMCC pVM, RTGCPHYS GCPhys)
|
---|
[65989] | 611 | {
|
---|
| 612 | if (!HMIsNestedPagingActive(pVM))
|
---|
| 613 | return VINF_SUCCESS;
|
---|
| 614 |
|
---|
[72643] | 615 | /*
|
---|
| 616 | * AMD-V: Doesn't support invalidation with guest physical addresses.
|
---|
| 617 | *
|
---|
| 618 | * VT-x: Doesn't support invalidation with guest physical addresses.
|
---|
| 619 | * INVVPID instruction takes only a linear address while invept only flushes by EPT
|
---|
| 620 | * not individual addresses.
|
---|
| 621 | *
|
---|
| 622 | * We update the force flag and flush before the next VM-entry, see @bugref{6568}.
|
---|
| 623 | */
|
---|
| 624 | RT_NOREF(GCPhys);
|
---|
| 625 | /** @todo Remove or figure out to way to update the Phys STAT counter. */
|
---|
| 626 | /* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
|
---|
[76993] | 627 | return HMFlushTlbOnAllVCpus(pVM);
|
---|
[65989] | 628 | }
|
---|
| 629 |
|
---|
| 630 |
|
---|
| 631 | /**
|
---|
[51981] | 632 | * Checks if nested paging is enabled.
|
---|
[9034] | 633 | *
|
---|
[51981] | 634 | * @returns true if nested paging is active, false otherwise.
|
---|
[58122] | 635 | * @param pVM The cross context VM structure.
|
---|
[54878] | 636 | *
|
---|
| 637 | * @remarks Works before hmR3InitFinalizeR0.
|
---|
[9034] | 638 | */
|
---|
[87515] | 639 | VMM_INT_DECL(bool) HMIsNestedPagingActive(PVMCC pVM)
|
---|
[9034] | 640 | {
|
---|
[87515] | 641 | return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING);
|
---|
[9034] | 642 | }
|
---|
| 643 |
|
---|
[51981] | 644 |
|
---|
[10822] | 645 | /**
|
---|
[54878] | 646 | * Checks if both nested paging and unhampered guest execution are enabled.
|
---|
| 647 | *
|
---|
[56034] | 648 | * The almost complete guest execution in hardware is only applicable to VT-x.
|
---|
[54878] | 649 | *
|
---|
| 650 | * @returns true if we have both enabled, otherwise false.
|
---|
[58122] | 651 | * @param pVM The cross context VM structure.
|
---|
[54878] | 652 | *
|
---|
| 653 | * @remarks Works before hmR3InitFinalizeR0.
|
---|
| 654 | */
|
---|
[87515] | 655 | VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVMCC pVM)
|
---|
[54878] | 656 | {
|
---|
| 657 | return HMIsEnabled(pVM)
|
---|
[87515] | 658 | && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING)
|
---|
[87547] | 659 | && ( CTX_EXPR(pVM->hm.s.vmx.fUnrestrictedGuestCfg, pVM->hmr0.s.vmx.fUnrestrictedGuest, RT_NOTHING)
|
---|
[54878] | 660 | || pVM->hm.s.svm.fSupported);
|
---|
| 661 | }
|
---|
| 662 |
|
---|
| 663 |
|
---|
| 664 | /**
|
---|
[72343] | 665 | * Checks if this VM is using HM and is long-mode capable.
|
---|
[52419] | 666 | *
|
---|
[72343] | 667 | * Use VMR3IsLongModeAllowed() instead of this, when possible.
|
---|
| 668 | *
|
---|
[52419] | 669 | * @returns true if long mode is allowed, false otherwise.
|
---|
[58126] | 670 | * @param pVM The cross context VM structure.
|
---|
[72343] | 671 | * @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
|
---|
[52419] | 672 | */
|
---|
[87518] | 673 | VMM_INT_DECL(bool) HMIsLongModeAllowed(PVMCC pVM)
|
---|
[52419] | 674 | {
|
---|
[87518] | 675 | return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fAllow64BitGuestsCfg, pVM->hmr0.s.fAllow64BitGuests, RT_NOTHING);
|
---|
[52419] | 676 | }
|
---|
| 677 |
|
---|
| 678 |
|
---|
| 679 | /**
|
---|
[73389] | 680 | * Checks if MSR bitmaps are active. It is assumed that when it's available
|
---|
[51981] | 681 | * it will be used as well.
|
---|
| 682 | *
|
---|
| 683 | * @returns true if MSR bitmaps are available, false otherwise.
|
---|
[58122] | 684 | * @param pVM The cross context VM structure.
|
---|
[51981] | 685 | */
|
---|
[73389] | 686 | VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
|
---|
[51981] | 687 | {
|
---|
| 688 | if (HMIsEnabled(pVM))
|
---|
| 689 | {
|
---|
| 690 | if (pVM->hm.s.svm.fSupported)
|
---|
| 691 | return true;
|
---|
| 692 |
|
---|
| 693 | if ( pVM->hm.s.vmx.fSupported
|
---|
[87563] | 694 | && ( CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1, g_HmMsrs.u.vmx.ProcCtls.n.allowed1, RT_NOTHING)
|
---|
[87543] | 695 | & VMX_PROC_CTLS_USE_MSR_BITMAPS))
|
---|
[51981] | 696 | return true;
|
---|
| 697 | }
|
---|
| 698 | return false;
|
---|
| 699 | }
|
---|
| 700 |
|
---|
| 701 |
|
---|
| 702 | /**
|
---|
[73246] | 703 | * Checks if AMD-V is active.
|
---|
[10822] | 704 | *
|
---|
[73246] | 705 | * @returns true if AMD-V is active.
|
---|
[58122] | 706 | * @param pVM The cross context VM structure.
|
---|
[73246] | 707 | *
|
---|
| 708 | * @remarks Works before hmR3InitFinalizeR0.
|
---|
[10822] | 709 | */
|
---|
[73246] | 710 | VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
|
---|
[10822] | 711 | {
|
---|
[73246] | 712 | return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
|
---|
| 713 | }
|
---|
[15159] | 714 |
|
---|
[73246] | 715 |
|
---|
| 716 | /**
|
---|
| 717 | * Checks if VT-x is active.
|
---|
| 718 | *
|
---|
[73389] | 719 | * @returns true if VT-x is active.
|
---|
[73246] | 720 | * @param pVM The cross context VM structure.
|
---|
| 721 | *
|
---|
| 722 | * @remarks Works before hmR3InitFinalizeR0.
|
---|
| 723 | */
|
---|
| 724 | VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
|
---|
| 725 | {
|
---|
[76993] | 726 | return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
|
---|
[10822] | 727 | }
|
---|
[73246] | 728 |
|
---|
[9115] | 729 |
|
---|
| 730 | /**
|
---|
[12702] | 731 | * Checks if an interrupt event is currently pending.
|
---|
[11370] | 732 | *
|
---|
| 733 | * @returns Interrupt event pending state.
|
---|
[58122] | 734 | * @param pVM The cross context VM structure.
|
---|
[11370] | 735 | */
|
---|
[80281] | 736 | VMM_INT_DECL(bool) HMHasPendingIrq(PVMCC pVM)
|
---|
[11370] | 737 | {
|
---|
[80281] | 738 | PVMCPUCC pVCpu = VMMGetCpu(pVM);
|
---|
[43387] | 739 | return !!pVCpu->hm.s.Event.fPending;
|
---|
[11370] | 740 | }
|
---|
[37386] | 741 |
|
---|
[44195] | 742 |
|
---|
| 743 | /**
|
---|
[47619] | 744 | * Sets or clears the single instruction flag.
|
---|
| 745 | *
|
---|
| 746 | * When set, HM will try its best to return to ring-3 after executing a single
|
---|
| 747 | * instruction. This can be used for debugging. See also
|
---|
| 748 | * EMR3HmSingleInstruction.
|
---|
| 749 | *
|
---|
| 750 | * @returns The old flag state.
|
---|
[58998] | 751 | * @param pVM The cross context VM structure.
|
---|
[58123] | 752 | * @param pVCpu The cross context virtual CPU structure of the calling EMT.
|
---|
| 753 | * @param fEnable The new flag state.
|
---|
[47619] | 754 | */
|
---|
[80268] | 755 | VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable)
|
---|
[47619] | 756 | {
|
---|
| 757 | VMCPU_ASSERT_EMT(pVCpu);
|
---|
| 758 | bool fOld = pVCpu->hm.s.fSingleInstruction;
|
---|
| 759 | pVCpu->hm.s.fSingleInstruction = fEnable;
|
---|
[58998] | 760 | pVCpu->hm.s.fUseDebugLoop = fEnable || pVM->hm.s.fUseDebugLoop;
|
---|
[47619] | 761 | return fOld;
|
---|
| 762 | }
|
---|
| 763 |
|
---|
[51560] | 764 |
|
---|
[73263] | 765 | /**
|
---|
| 766 | * Notification callback which is called whenever there is a chance that a CR3
|
---|
| 767 | * value might have changed.
|
---|
| 768 | *
|
---|
| 769 | * This is called by PGM.
|
---|
| 770 | *
|
---|
[73266] | 771 | * @param pVM The cross context VM structure.
|
---|
| 772 | * @param pVCpu The cross context virtual CPU structure.
|
---|
| 773 | * @param enmShadowMode New shadow paging mode.
|
---|
| 774 | * @param enmGuestMode New guest paging mode.
|
---|
[73263] | 775 | */
|
---|
[87488] | 776 | VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPUCC pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
|
---|
[73263] | 777 | {
|
---|
[80118] | 778 | #ifdef IN_RING3
|
---|
[73263] | 779 | /* Ignore page mode changes during state loading. */
|
---|
[73266] | 780 | if (VMR3GetState(pVM) == VMSTATE_LOADING)
|
---|
[73263] | 781 | return;
|
---|
[80118] | 782 | #endif
|
---|
[73263] | 783 |
|
---|
| 784 | pVCpu->hm.s.enmShadowMode = enmShadowMode;
|
---|
| 785 |
|
---|
| 786 | /*
|
---|
| 787 | * If the guest left protected mode VMX execution, we'll have to be
|
---|
| 788 | * extra careful if/when the guest switches back to protected mode.
|
---|
| 789 | */
|
---|
[87501] | 790 | if (enmGuestMode == PGMMODE_REAL)
|
---|
[78220] | 791 | {
|
---|
[87472] | 792 | PVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
|
---|
| 793 | pVmcsInfoShared->fWasInRealMode = true;
|
---|
[78220] | 794 | }
|
---|
[73263] | 795 |
|
---|
[80118] | 796 | #ifdef IN_RING0
|
---|
[73266] | 797 | /*
|
---|
| 798 | * We need to tickle SVM and VT-x state updates.
|
---|
| 799 | *
|
---|
| 800 | * Note! We could probably reduce this depending on what exactly changed.
|
---|
| 801 | */
|
---|
| 802 | if (VM_IS_HM_ENABLED(pVM))
|
---|
| 803 | {
|
---|
| 804 | CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER); /* No recursion! */
|
---|
| 805 | uint64_t fChanged = HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 | HM_CHANGED_GUEST_EFER_MSR;
|
---|
| 806 | if (pVM->hm.s.svm.fSupported)
|
---|
[78707] | 807 | fChanged |= HM_CHANGED_SVM_XCPT_INTERCEPTS;
|
---|
[73266] | 808 | else
|
---|
[78707] | 809 | fChanged |= HM_CHANGED_VMX_XCPT_INTERCEPTS | HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
|
---|
[73266] | 810 | ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
|
---|
| 811 | }
|
---|
[80118] | 812 | #endif
|
---|
[73266] | 813 |
|
---|
[76993] | 814 | Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
|
---|
[73263] | 815 | PGMGetModeName(enmShadowMode)));
|
---|
| 816 | }
|
---|
| 817 |
|
---|
[76469] | 818 |
|
---|
| 819 | /**
|
---|
| 820 | * Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
|
---|
| 821 | *
|
---|
[78245] | 822 | * This abstraction exists to insulate the support driver from including VMX
|
---|
| 823 | * structures from HM headers.
|
---|
[76469] | 824 | *
|
---|
| 825 | * @param pHwvirtMsrs The hardware-virtualization MSRs.
|
---|
| 826 | * @param pVmxMsrs Where to store the VMX MSRs.
|
---|
| 827 | */
|
---|
[76993] | 828 | VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
|
---|
[76469] | 829 | {
|
---|
| 830 | AssertReturnVoid(pHwvirtMsrs);
|
---|
| 831 | AssertReturnVoid(pVmxMsrs);
|
---|
| 832 | pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
|
---|
[87542] | 833 | pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.PinCtls.u;
|
---|
| 834 | pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.ProcCtls.u;
|
---|
| 835 | pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.ProcCtls2.u;
|
---|
| 836 | pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.ExitCtls.u;
|
---|
| 837 | pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.EntryCtls.u;
|
---|
| 838 | pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.TruePinCtls.u;
|
---|
| 839 | pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.TrueProcCtls.u;
|
---|
| 840 | pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.TrueEntryCtls.u;
|
---|
| 841 | pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.TrueExitCtls.u;
|
---|
[76469] | 842 | pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
|
---|
| 843 | pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
|
---|
| 844 | pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
|
---|
| 845 | pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
|
---|
| 846 | pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
|
---|
| 847 | pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
|
---|
| 848 | pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
|
---|
| 849 | pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
|
---|
[91037] | 850 | pVmxMsrs->u64ProcCtls3 = pHwvirtMsrs->u.vmx.u64ProcCtls3;
|
---|
[76469] | 851 | }
|
---|
| 852 |
|
---|
| 853 |
|
---|
| 854 | /**
|
---|
| 855 | * Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
|
---|
| 856 | *
|
---|
[78245] | 857 | * This abstraction exists to insulate the support driver from including SVM
|
---|
| 858 | * structures from HM headers.
|
---|
[76469] | 859 | *
|
---|
| 860 | * @param pHwvirtMsrs The hardware-virtualization MSRs.
|
---|
| 861 | * @param pSvmMsrs Where to store the SVM MSRs.
|
---|
| 862 | */
|
---|
[76993] | 863 | VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
|
---|
[76469] | 864 | {
|
---|
| 865 | AssertReturnVoid(pHwvirtMsrs);
|
---|
| 866 | AssertReturnVoid(pSvmMsrs);
|
---|
| 867 | pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
|
---|
| 868 | }
|
---|
| 869 |
|
---|
[76993] | 870 |
|
---|
| 871 | /**
|
---|
| 872 | * Gets the name of a VT-x exit code.
|
---|
| 873 | *
|
---|
| 874 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
|
---|
| 875 | * @param uExit The VT-x exit to name.
|
---|
| 876 | */
|
---|
| 877 | VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
|
---|
| 878 | {
|
---|
[80630] | 879 | uint16_t const uReason = VMX_EXIT_REASON_BASIC(uExit);
|
---|
| 880 | if (uReason <= MAX_EXITREASON_VTX)
|
---|
[76993] | 881 | {
|
---|
[80630] | 882 | Assert(uReason < RT_ELEMENTS(g_apszVmxExitReasons));
|
---|
| 883 | return g_apszVmxExitReasons[uReason];
|
---|
[76993] | 884 | }
|
---|
| 885 | return NULL;
|
---|
| 886 | }
|
---|
| 887 |
|
---|
| 888 |
|
---|
| 889 | /**
|
---|
| 890 | * Gets the name of an AMD-V exit code.
|
---|
| 891 | *
|
---|
| 892 | * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
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| 893 | * @param uExit The AMD-V exit to name.
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| 894 | */
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| 895 | VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
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| 896 | {
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| 897 | if (uExit <= MAX_EXITREASON_AMDV)
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| 898 | {
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| 899 | Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
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| 900 | return g_apszSvmExitReasons[uExit];
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| 901 | }
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| 902 | return hmSvmGetSpecialExitReasonDesc(uExit);
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| 903 | }
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| 904 |
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