VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/HMAll.cpp@ 96860

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1/* $Id: HMAll.cpp 96407 2022-08-22 17:43:14Z vboxsync $ */
2/** @file
3 * HM - All contexts.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_HM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/hm.h>
35#include <VBox/vmm/pgm.h>
36#include "HMInternal.h"
37#include <VBox/vmm/vmcc.h>
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include <iprt/errcore.h>
41#include <VBox/log.h>
42#include <iprt/param.h>
43#include <iprt/assert.h>
44#include <iprt/asm.h>
45#include <iprt/string.h>
46#include <iprt/thread.h>
47#include <iprt/x86.h>
48
49
50/*********************************************************************************************************************************
51* Global Variables *
52*********************************************************************************************************************************/
53#define EXIT_REASON(a_Def, a_Val, a_Str) #a_Def " - " #a_Val " - " a_Str
54#define EXIT_REASON_NIL() NULL
55
56/** Exit reason descriptions for VT-x, used to describe statistics and exit
57 * history. */
58static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
59{
60 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
61 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
62 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
63 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
64 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
65 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
66 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
67 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
68 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
69 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
70 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
71 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instruction."),
72 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
73 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
74 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
75 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMC instruction."),
76 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
77 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
78 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
79 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
80 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
81 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
82 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
83 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
84 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
85 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
86 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
87 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
88 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
89 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
90 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
91 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
92 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
93 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
94 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
95 EXIT_REASON_NIL(),
96 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
97 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
98 EXIT_REASON_NIL(),
99 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
100 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
101 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
104 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
105 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
106 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
107 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
108 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
109 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
110 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
111 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
112 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
113 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
114 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
115 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
116 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
117 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
118 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
119 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
120 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
121 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
122 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
123 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
124 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction."),
125 EXIT_REASON_NIL(),
126 EXIT_REASON(VMX_EXIT_SPP_EVENT , 66, "SPP-related event."),
127 EXIT_REASON(VMX_EXIT_UMWAIT , 67, "UMWAIT instruction."),
128 EXIT_REASON(VMX_EXIT_TPAUSE , 68, "TPAUSE instruction.")
129};
130/** Array index of the last valid VT-x exit reason. */
131#define MAX_EXITREASON_VTX 68
132
133/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
134 * statistics and exit history.
135 *
136 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
137 * this array doesn't contain the entire set of exit reasons, we
138 * handle them via hmSvmGetSpecialExitReasonDesc(). */
139static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
140{
141 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
142 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
143 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
144 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
145 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
146 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
147 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
148 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
149 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
150 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
151 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
152 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
153 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
154 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
155 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
156 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
160 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
161 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
162 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
163 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
164 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
165 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
166 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
167 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
168 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
169 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
170 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
171 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
173 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
174 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
175 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
176 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
177 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
178 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
179 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
180 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
181 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
182 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
183 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
184 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
185 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
186 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
187 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
188 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
192 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
193 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
194 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
195 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
196 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
197 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
198 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
199 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
200 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
201 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
202 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
203 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
205 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
206 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
207 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
208 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
209 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
210 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
211 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
212 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
213 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
214 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
215 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
216 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
217 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
218 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
219 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
220 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
221 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
222 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
223 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
224 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
225 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
226 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
227 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
228 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
229 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
230 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
231 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
232 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
233 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
234 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
235 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
236 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
237 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
238 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
239 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
240 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
241 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
242 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE , 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
243 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
244 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
245 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
246 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
247 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
248 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
249 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
250 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
251 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
252 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
253 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
254 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
255 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
256 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
257 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
258 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
259 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
260 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
261 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
262 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
263 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
264 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
265 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
266 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
267 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
268 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
269 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
270 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
271 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
272 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
273 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
274 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
275 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
276 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
277 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
278 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
279 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
280 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
281 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
282 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
283 EXIT_REASON(SVM_EXIT_RDPRU , 142, "RDPRU instruction."),
284 EXIT_REASON(SVM_EXIT_WRITE_EFER_TRAP, 143, "Write EFER (trap-like)."),
285 EXIT_REASON(SVM_EXIT_WRITE_CR0_TRAP , 144, "Write CR0 (trap-like)."),
286 EXIT_REASON(SVM_EXIT_WRITE_CR1_TRAP , 145, "Write CR1 (trap-like)."),
287 EXIT_REASON(SVM_EXIT_WRITE_CR2_TRAP , 146, "Write CR2 (trap-like)."),
288 EXIT_REASON(SVM_EXIT_WRITE_CR3_TRAP , 147, "Write CR3 (trap-like)."),
289 EXIT_REASON(SVM_EXIT_WRITE_CR4_TRAP , 148, "Write CR4 (trap-like)."),
290 EXIT_REASON(SVM_EXIT_WRITE_CR5_TRAP , 149, "Write CR5 (trap-like)."),
291 EXIT_REASON(SVM_EXIT_WRITE_CR6_TRAP , 150, "Write CR6 (trap-like)."),
292 EXIT_REASON(SVM_EXIT_WRITE_CR7_TRAP , 151, "Write CR7 (trap-like)."),
293 EXIT_REASON(SVM_EXIT_WRITE_CR8_TRAP , 152, "Write CR8 (trap-like)."),
294 EXIT_REASON(SVM_EXIT_WRITE_CR9_TRAP , 153, "Write CR9 (trap-like)."),
295 EXIT_REASON(SVM_EXIT_WRITE_CR10_TRAP, 154, "Write CR10 (trap-like)."),
296 EXIT_REASON(SVM_EXIT_WRITE_CR11_TRAP, 155, "Write CR11 (trap-like)."),
297 EXIT_REASON(SVM_EXIT_WRITE_CR12_TRAP, 156, "Write CR12 (trap-like)."),
298 EXIT_REASON(SVM_EXIT_WRITE_CR13_TRAP, 157, "Write CR13 (trap-like)."),
299 EXIT_REASON(SVM_EXIT_WRITE_CR14_TRAP, 158, "Write CR14 (trap-like)."),
300 EXIT_REASON(SVM_EXIT_WRITE_CR15_TRAP, 159, "Write CR15 (trap-like)."),
301 EXIT_REASON_NIL() ,
302 EXIT_REASON_NIL() ,
303 EXIT_REASON_NIL() ,
304 EXIT_REASON(SVM_EXIT_MCOMMIT , 163, "MCOMMIT instruction."),
305};
306/** Array index of the last valid AMD-V exit reason. */
307#define MAX_EXITREASON_AMDV 163
308
309/** Special exit reasons not covered in the array above. */
310#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
311#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
312#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
313
314/**
315 * Gets the SVM exit reason if it's one of the reasons not present in the @c
316 * g_apszSvmExitReasons array.
317 *
318 * @returns The exit reason or NULL if unknown.
319 * @param uExit The exit.
320 */
321DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
322{
323 switch (uExit)
324 {
325 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
326 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
327 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
328 }
329 return EXIT_REASON_NIL();
330}
331#undef EXIT_REASON_NIL
332#undef EXIT_REASON
333
334
335/**
336 * Checks whether HM (VT-x/AMD-V) is being used by this VM.
337 *
338 * @retval true if used.
339 * @retval false if software virtualization (raw-mode) is used.
340 * @param pVM The cross context VM structure.
341 * @sa HMIsEnabled, HMR3IsEnabled
342 * @internal
343 */
344VMMDECL(bool) HMIsEnabledNotMacro(PVM pVM)
345{
346 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
347 return pVM->fHMEnabled;
348}
349
350
351/**
352 * Checks if the guest is in a suitable state for hardware-assisted execution.
353 *
354 * @returns @c true if it is suitable, @c false otherwise.
355 * @param pVM The cross context VM structure.
356 * @param pVCpu The cross context virtual CPU structure.
357 * @param pCtx Pointer to the guest CPU context.
358 *
359 * @remarks @a pCtx can be a partial context created and not necessarily the same as
360 * pVCpu->cpum.GstCtx.
361 */
362VMMDECL(bool) HMCanExecuteGuest(PVMCC pVM, PVMCPUCC pVCpu, PCCPUMCTX pCtx)
363{
364 Assert(HMIsEnabled(pVM));
365
366#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
367 if ( CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
368 || CPUMIsGuestInVmxNonRootMode(pCtx))
369 {
370 LogFunc(("In nested-guest mode - returning false"));
371 return false;
372 }
373#endif
374
375 /* AMD-V supports real & protected mode with or without paging. */
376 if (pVM->hm.s.svm.fEnabled)
377 {
378 pVCpu->hm.s.fActive = true;
379 return true;
380 }
381
382 bool rc = HMCanExecuteVmxGuest(pVM, pVCpu, pCtx);
383 LogFlowFunc(("returning %RTbool\n", rc));
384 return rc;
385}
386
387
388/**
389 * Queues a guest page for invalidation.
390 *
391 * @returns VBox status code.
392 * @param pVCpu The cross context virtual CPU structure.
393 * @param GCVirt Page to invalidate.
394 */
395static void hmQueueInvlPage(PVMCPU pVCpu, RTGCPTR GCVirt)
396{
397 /* Nothing to do if a TLB flush is already pending */
398 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
399 return;
400 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
401 NOREF(GCVirt);
402}
403
404
405/**
406 * Invalidates a guest page.
407 *
408 * @returns VBox status code.
409 * @param pVCpu The cross context virtual CPU structure.
410 * @param GCVirt Page to invalidate.
411 */
412VMM_INT_DECL(int) HMInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCVirt)
413{
414 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
415#ifdef IN_RING0
416 return HMR0InvalidatePage(pVCpu, GCVirt);
417#else
418 hmQueueInvlPage(pVCpu, GCVirt);
419 return VINF_SUCCESS;
420#endif
421}
422
423
424#ifdef IN_RING0
425
426/**
427 * Dummy RTMpOnSpecific handler since RTMpPokeCpu couldn't be used.
428 *
429 */
430static DECLCALLBACK(void) hmFlushHandler(RTCPUID idCpu, void *pvUser1, void *pvUser2)
431{
432 NOREF(idCpu); NOREF(pvUser1); NOREF(pvUser2);
433 return;
434}
435
436
437/**
438 * Wrapper for RTMpPokeCpu to deal with VERR_NOT_SUPPORTED.
439 */
440static void hmR0PokeCpu(PVMCPUCC pVCpu, RTCPUID idHostCpu)
441{
442 uint32_t cWorldSwitchExits = ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits);
443
444 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatPoke, x);
445 int rc = RTMpPokeCpu(idHostCpu);
446 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatPoke, x);
447
448 /* Not implemented on some platforms (Darwin, Linux kernel < 2.6.19); fall
449 back to a less efficient implementation (broadcast). */
450 if (rc == VERR_NOT_SUPPORTED)
451 {
452 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
453 /* synchronous. */
454 RTMpOnSpecific(idHostCpu, hmFlushHandler, 0, 0);
455 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
456 }
457 else
458 {
459 if (rc == VINF_SUCCESS)
460 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPoke, z);
461 else
462 STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatSpinPokeFailed, z);
463
464/** @todo If more than one CPU is going to be poked, we could optimize this
465 * operation by poking them first and wait afterwards. Would require
466 * recording who to poke and their current cWorldSwitchExits values,
467 * that's something not suitable for stack... So, pVCpu->hm.s.something
468 * then. */
469 /* Spin until the VCPU has switched back (poking is async). */
470 while ( ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush)
471 && cWorldSwitchExits == ASMAtomicUoReadU32(&pVCpu->hmr0.s.cWorldSwitchExits))
472 ASMNopPause();
473
474 if (rc == VINF_SUCCESS)
475 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPoke, z);
476 else
477 STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatSpinPokeFailed, z);
478 }
479}
480
481#endif /* IN_RING0 */
482
483/**
484 * Flushes the guest TLB.
485 *
486 * @returns VBox status code.
487 * @param pVCpu The cross context virtual CPU structure.
488 */
489VMM_INT_DECL(int) HMFlushTlb(PVMCPU pVCpu)
490{
491 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
492 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbManual);
493 return VINF_SUCCESS;
494}
495
496
497/**
498 * Poke an EMT so it can perform the appropriate TLB shootdowns.
499 *
500 * @param pVCpu The cross context virtual CPU structure of the
501 * EMT poke.
502 * @param fAccountFlushStat Whether to account the call to
503 * StatTlbShootdownFlush or StatTlbShootdown.
504 */
505static void hmPokeCpuForTlbFlush(PVMCPUCC pVCpu, bool fAccountFlushStat)
506{
507 if (ASMAtomicUoReadBool(&pVCpu->hm.s.fCheckedTLBFlush))
508 {
509 if (fAccountFlushStat)
510 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdownFlush);
511 else
512 STAM_COUNTER_INC(&pVCpu->hm.s.StatTlbShootdown);
513#ifdef IN_RING0
514 RTCPUID idHostCpu = pVCpu->hmr0.s.idEnteredCpu;
515 if (idHostCpu != NIL_RTCPUID)
516 hmR0PokeCpu(pVCpu, idHostCpu);
517#else
518 VMR3NotifyCpuFFU(pVCpu->pUVCpu, VMNOTIFYFF_FLAGS_POKE);
519#endif
520 }
521 else
522 STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushPageManual);
523}
524
525
526/**
527 * Invalidates a guest page on all VCPUs.
528 *
529 * @returns VBox status code.
530 * @param pVM The cross context VM structure.
531 * @param GCVirt Page to invalidate.
532 */
533VMM_INT_DECL(int) HMInvalidatePageOnAllVCpus(PVMCC pVM, RTGCPTR GCVirt)
534{
535 /*
536 * The VT-x/AMD-V code will be flushing TLB each time a VCPU migrates to a different
537 * host CPU, see hmR0VmxFlushTaggedTlbBoth() and hmR0SvmFlushTaggedTlb().
538 *
539 * This is the reason why we do not care about thread preemption here and just
540 * execute HMInvalidatePage() assuming it might be the 'right' CPU.
541 */
542 VMCPUID const idCurCpu = VMMGetCpuId(pVM);
543 STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idCurCpu)->hm.s.StatFlushPage);
544
545 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
546 {
547 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
548
549 /* Nothing to do if a TLB flush is already pending; the VCPU should
550 have already been poked if it were active. */
551 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
552 continue;
553
554 if (pVCpu->idCpu == idCurCpu)
555 HMInvalidatePage(pVCpu, GCVirt);
556 else
557 {
558 hmQueueInvlPage(pVCpu, GCVirt);
559 hmPokeCpuForTlbFlush(pVCpu, false /* fAccountFlushStat */);
560 }
561 }
562
563 return VINF_SUCCESS;
564}
565
566
567/**
568 * Flush the TLBs of all VCPUs.
569 *
570 * @returns VBox status code.
571 * @param pVM The cross context VM structure.
572 */
573VMM_INT_DECL(int) HMFlushTlbOnAllVCpus(PVMCC pVM)
574{
575 if (pVM->cCpus == 1)
576 return HMFlushTlb(VMCC_GET_CPU_0(pVM));
577
578 VMCPUID const idThisCpu = VMMGetCpuId(pVM);
579
580 STAM_COUNTER_INC(&VMCC_GET_CPU(pVM, idThisCpu)->hm.s.StatFlushTlb);
581
582 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
583 {
584 PVMCPUCC pVCpu = VMCC_GET_CPU(pVM, idCpu);
585
586 /* Nothing to do if a TLB flush is already pending; the VCPU should
587 have already been poked if it were active. */
588 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH))
589 {
590 VMCPU_FF_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
591 if (idThisCpu != idCpu)
592 hmPokeCpuForTlbFlush(pVCpu, true /* fAccountFlushStat */);
593 }
594 }
595
596 return VINF_SUCCESS;
597}
598
599
600/**
601 * Invalidates a guest page by physical address.
602 *
603 * @returns VBox status code.
604 * @param pVM The cross context VM structure.
605 * @param GCPhys Page to invalidate.
606 *
607 * @remarks Assumes the current instruction references this physical page
608 * though a virtual address!
609 */
610VMM_INT_DECL(int) HMInvalidatePhysPage(PVMCC pVM, RTGCPHYS GCPhys)
611{
612 if (!HMIsNestedPagingActive(pVM))
613 return VINF_SUCCESS;
614
615 /*
616 * AMD-V: Doesn't support invalidation with guest physical addresses.
617 *
618 * VT-x: Doesn't support invalidation with guest physical addresses.
619 * INVVPID instruction takes only a linear address while invept only flushes by EPT
620 * not individual addresses.
621 *
622 * We update the force flag and flush before the next VM-entry, see @bugref{6568}.
623 */
624 RT_NOREF(GCPhys);
625 /** @todo Remove or figure out to way to update the Phys STAT counter. */
626 /* STAM_COUNTER_INC(&pVCpu->hm.s.StatFlushTlbInvlpgPhys); */
627 return HMFlushTlbOnAllVCpus(pVM);
628}
629
630
631/**
632 * Checks if nested paging is enabled.
633 *
634 * @returns true if nested paging is active, false otherwise.
635 * @param pVM The cross context VM structure.
636 *
637 * @remarks Works before hmR3InitFinalizeR0.
638 */
639VMM_INT_DECL(bool) HMIsNestedPagingActive(PVMCC pVM)
640{
641 return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING);
642}
643
644
645/**
646 * Checks if both nested paging and unhampered guest execution are enabled.
647 *
648 * The almost complete guest execution in hardware is only applicable to VT-x.
649 *
650 * @returns true if we have both enabled, otherwise false.
651 * @param pVM The cross context VM structure.
652 *
653 * @remarks Works before hmR3InitFinalizeR0.
654 */
655VMM_INT_DECL(bool) HMAreNestedPagingAndFullGuestExecEnabled(PVMCC pVM)
656{
657 return HMIsEnabled(pVM)
658 && CTX_EXPR(pVM->hm.s.fNestedPagingCfg, pVM->hmr0.s.fNestedPaging, RT_NOTHING)
659 && ( CTX_EXPR(pVM->hm.s.vmx.fUnrestrictedGuestCfg, pVM->hmr0.s.vmx.fUnrestrictedGuest, RT_NOTHING)
660 || pVM->hm.s.svm.fSupported);
661}
662
663
664/**
665 * Checks if this VM is using HM and is long-mode capable.
666 *
667 * Use VMR3IsLongModeAllowed() instead of this, when possible.
668 *
669 * @returns true if long mode is allowed, false otherwise.
670 * @param pVM The cross context VM structure.
671 * @sa VMR3IsLongModeAllowed, NEMHCIsLongModeAllowed
672 */
673VMM_INT_DECL(bool) HMIsLongModeAllowed(PVMCC pVM)
674{
675 return HMIsEnabled(pVM) && CTX_EXPR(pVM->hm.s.fAllow64BitGuestsCfg, pVM->hmr0.s.fAllow64BitGuests, RT_NOTHING);
676}
677
678
679/**
680 * Checks if MSR bitmaps are active. It is assumed that when it's available
681 * it will be used as well.
682 *
683 * @returns true if MSR bitmaps are available, false otherwise.
684 * @param pVM The cross context VM structure.
685 */
686VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
687{
688 if (HMIsEnabled(pVM))
689 {
690 if (pVM->hm.s.svm.fSupported)
691 return true;
692
693 if ( pVM->hm.s.vmx.fSupported
694 && ( CTX_EXPR(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1, g_HmMsrs.u.vmx.ProcCtls.n.allowed1, RT_NOTHING)
695 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
696 return true;
697 }
698 return false;
699}
700
701
702/**
703 * Checks if AMD-V is active.
704 *
705 * @returns true if AMD-V is active.
706 * @param pVM The cross context VM structure.
707 *
708 * @remarks Works before hmR3InitFinalizeR0.
709 */
710VMM_INT_DECL(bool) HMIsSvmActive(PVM pVM)
711{
712 return pVM->hm.s.svm.fSupported && HMIsEnabled(pVM);
713}
714
715
716/**
717 * Checks if VT-x is active.
718 *
719 * @returns true if VT-x is active.
720 * @param pVM The cross context VM structure.
721 *
722 * @remarks Works before hmR3InitFinalizeR0.
723 */
724VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
725{
726 return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
727}
728
729
730/**
731 * Checks if an interrupt event is currently pending.
732 *
733 * @returns Interrupt event pending state.
734 * @param pVM The cross context VM structure.
735 */
736VMM_INT_DECL(bool) HMHasPendingIrq(PVMCC pVM)
737{
738 PVMCPUCC pVCpu = VMMGetCpu(pVM);
739 return !!pVCpu->hm.s.Event.fPending;
740}
741
742
743/**
744 * Sets or clears the single instruction flag.
745 *
746 * When set, HM will try its best to return to ring-3 after executing a single
747 * instruction. This can be used for debugging. See also
748 * EMR3HmSingleInstruction.
749 *
750 * @returns The old flag state.
751 * @param pVM The cross context VM structure.
752 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
753 * @param fEnable The new flag state.
754 */
755VMM_INT_DECL(bool) HMSetSingleInstruction(PVMCC pVM, PVMCPUCC pVCpu, bool fEnable)
756{
757 VMCPU_ASSERT_EMT(pVCpu);
758 bool fOld = pVCpu->hm.s.fSingleInstruction;
759 pVCpu->hm.s.fSingleInstruction = fEnable;
760 pVCpu->hm.s.fUseDebugLoop = fEnable || pVM->hm.s.fUseDebugLoop;
761 return fOld;
762}
763
764
765/**
766 * Notification callback which is called whenever there is a chance that a CR3
767 * value might have changed.
768 *
769 * This is called by PGM.
770 *
771 * @param pVM The cross context VM structure.
772 * @param pVCpu The cross context virtual CPU structure.
773 * @param enmShadowMode New shadow paging mode.
774 * @param enmGuestMode New guest paging mode.
775 */
776VMM_INT_DECL(void) HMHCChangedPagingMode(PVM pVM, PVMCPUCC pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
777{
778#ifdef IN_RING3
779 /* Ignore page mode changes during state loading. */
780 if (VMR3GetState(pVM) == VMSTATE_LOADING)
781 return;
782#endif
783
784 pVCpu->hm.s.enmShadowMode = enmShadowMode;
785
786 /*
787 * If the guest left protected mode VMX execution, we'll have to be
788 * extra careful if/when the guest switches back to protected mode.
789 */
790 if (enmGuestMode == PGMMODE_REAL)
791 {
792 PVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
793 pVmcsInfoShared->fWasInRealMode = true;
794 }
795
796#ifdef IN_RING0
797 /*
798 * We need to tickle SVM and VT-x state updates.
799 *
800 * Note! We could probably reduce this depending on what exactly changed.
801 */
802 if (VM_IS_HM_ENABLED(pVM))
803 {
804 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER); /* No recursion! */
805 uint64_t fChanged = HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 | HM_CHANGED_GUEST_EFER_MSR;
806 if (pVM->hm.s.svm.fSupported)
807 fChanged |= HM_CHANGED_SVM_XCPT_INTERCEPTS;
808 else
809 fChanged |= HM_CHANGED_VMX_XCPT_INTERCEPTS | HM_CHANGED_VMX_ENTRY_EXIT_CTLS;
810 ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, fChanged);
811 }
812#endif
813
814 Log4(("HMHCChangedPagingMode: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
815 PGMGetModeName(enmShadowMode)));
816}
817
818
819/**
820 * Gets VMX MSRs from the provided hardware-virtualization MSRs struct.
821 *
822 * This abstraction exists to insulate the support driver from including VMX
823 * structures from HM headers.
824 *
825 * @param pHwvirtMsrs The hardware-virtualization MSRs.
826 * @param pVmxMsrs Where to store the VMX MSRs.
827 */
828VMM_INT_DECL(void) HMGetVmxMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PVMXMSRS pVmxMsrs)
829{
830 AssertReturnVoid(pHwvirtMsrs);
831 AssertReturnVoid(pVmxMsrs);
832 pVmxMsrs->u64Basic = pHwvirtMsrs->u.vmx.u64Basic;
833 pVmxMsrs->PinCtls.u = pHwvirtMsrs->u.vmx.PinCtls.u;
834 pVmxMsrs->ProcCtls.u = pHwvirtMsrs->u.vmx.ProcCtls.u;
835 pVmxMsrs->ProcCtls2.u = pHwvirtMsrs->u.vmx.ProcCtls2.u;
836 pVmxMsrs->ExitCtls.u = pHwvirtMsrs->u.vmx.ExitCtls.u;
837 pVmxMsrs->EntryCtls.u = pHwvirtMsrs->u.vmx.EntryCtls.u;
838 pVmxMsrs->TruePinCtls.u = pHwvirtMsrs->u.vmx.TruePinCtls.u;
839 pVmxMsrs->TrueProcCtls.u = pHwvirtMsrs->u.vmx.TrueProcCtls.u;
840 pVmxMsrs->TrueEntryCtls.u = pHwvirtMsrs->u.vmx.TrueEntryCtls.u;
841 pVmxMsrs->TrueExitCtls.u = pHwvirtMsrs->u.vmx.TrueExitCtls.u;
842 pVmxMsrs->u64Misc = pHwvirtMsrs->u.vmx.u64Misc;
843 pVmxMsrs->u64Cr0Fixed0 = pHwvirtMsrs->u.vmx.u64Cr0Fixed0;
844 pVmxMsrs->u64Cr0Fixed1 = pHwvirtMsrs->u.vmx.u64Cr0Fixed1;
845 pVmxMsrs->u64Cr4Fixed0 = pHwvirtMsrs->u.vmx.u64Cr4Fixed0;
846 pVmxMsrs->u64Cr4Fixed1 = pHwvirtMsrs->u.vmx.u64Cr4Fixed1;
847 pVmxMsrs->u64VmcsEnum = pHwvirtMsrs->u.vmx.u64VmcsEnum;
848 pVmxMsrs->u64VmFunc = pHwvirtMsrs->u.vmx.u64VmFunc;
849 pVmxMsrs->u64EptVpidCaps = pHwvirtMsrs->u.vmx.u64EptVpidCaps;
850 pVmxMsrs->u64ProcCtls3 = pHwvirtMsrs->u.vmx.u64ProcCtls3;
851}
852
853
854/**
855 * Gets SVM MSRs from the provided hardware-virtualization MSRs struct.
856 *
857 * This abstraction exists to insulate the support driver from including SVM
858 * structures from HM headers.
859 *
860 * @param pHwvirtMsrs The hardware-virtualization MSRs.
861 * @param pSvmMsrs Where to store the SVM MSRs.
862 */
863VMM_INT_DECL(void) HMGetSvmMsrsFromHwvirtMsrs(PCSUPHWVIRTMSRS pHwvirtMsrs, PSVMMSRS pSvmMsrs)
864{
865 AssertReturnVoid(pHwvirtMsrs);
866 AssertReturnVoid(pSvmMsrs);
867 pSvmMsrs->u64MsrHwcr = pHwvirtMsrs->u.svm.u64MsrHwcr;
868}
869
870
871/**
872 * Gets the name of a VT-x exit code.
873 *
874 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
875 * @param uExit The VT-x exit to name.
876 */
877VMM_INT_DECL(const char *) HMGetVmxExitName(uint32_t uExit)
878{
879 uint16_t const uReason = VMX_EXIT_REASON_BASIC(uExit);
880 if (uReason <= MAX_EXITREASON_VTX)
881 {
882 Assert(uReason < RT_ELEMENTS(g_apszVmxExitReasons));
883 return g_apszVmxExitReasons[uReason];
884 }
885 return NULL;
886}
887
888
889/**
890 * Gets the name of an AMD-V exit code.
891 *
892 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
893 * @param uExit The AMD-V exit to name.
894 */
895VMM_INT_DECL(const char *) HMGetSvmExitName(uint32_t uExit)
896{
897 if (uExit <= MAX_EXITREASON_AMDV)
898 {
899 Assert(uExit < RT_ELEMENTS(g_apszSvmExitReasons));
900 return g_apszSvmExitReasons[uExit];
901 }
902 return hmSvmGetSpecialExitReasonDesc(uExit);
903}
904
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