[23] | 1 | /* $Id: CPUMAllRegs.cpp 43860 2012-11-12 17:12:37Z vboxsync $ */
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[1] | 2 | /** @file
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[12657] | 3 | * CPUM - CPU Monitor(/Manager) - Getters and Setters.
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[1] | 4 | */
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| 5 |
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| 6 | /*
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[41728] | 7 | * Copyright (C) 2006-2012 Oracle Corporation
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[1] | 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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[5999] | 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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[1] | 16 | */
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| 17 |
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| 18 |
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| 19 | /*******************************************************************************
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| 20 | * Header Files *
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| 21 | *******************************************************************************/
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| 22 | #define LOG_GROUP LOG_GROUP_CPUM
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[35346] | 23 | #include <VBox/vmm/cpum.h>
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| 24 | #include <VBox/vmm/patm.h>
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| 25 | #include <VBox/vmm/dbgf.h>
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| 26 | #include <VBox/vmm/pdm.h>
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| 27 | #include <VBox/vmm/pgm.h>
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| 28 | #include <VBox/vmm/mm.h>
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[42165] | 29 | #if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
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| 30 | # include <VBox/vmm/selm.h>
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| 31 | #endif
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[1] | 32 | #include "CPUMInternal.h"
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[35346] | 33 | #include <VBox/vmm/vm.h>
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[1] | 34 | #include <VBox/err.h>
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| 35 | #include <VBox/dis.h>
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| 36 | #include <VBox/log.h>
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[43387] | 37 | #include <VBox/vmm/hm.h>
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[35346] | 38 | #include <VBox/vmm/tm.h>
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[1] | 39 | #include <iprt/assert.h>
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[772] | 40 | #include <iprt/asm.h>
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[29250] | 41 | #include <iprt/asm-amd64-x86.h>
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[13960] | 42 | #ifdef IN_RING3
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| 43 | #include <iprt/thread.h>
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| 44 | #endif
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[1] | 45 |
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| 46 | /** Disable stack frame pointer generation here. */
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| 47 | #if defined(_MSC_VER) && !defined(DEBUG)
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| 48 | # pragma optimize("y", off)
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| 49 | #endif
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| 50 |
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| 51 |
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[42165] | 52 | /*******************************************************************************
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| 53 | * Defined Constants And Macros *
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| 54 | *******************************************************************************/
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[1] | 55 | /**
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[42165] | 56 | * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
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| 57 | *
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| 58 | * @returns Pointer to the Virtual CPU.
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| 59 | * @param a_pGuestCtx Pointer to the guest context.
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| 60 | */
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| 61 | #define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
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| 62 |
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| 63 | /**
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| 64 | * Lazily loads the hidden parts of a selector register when using raw-mode.
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| 65 | */
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| 66 | #if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
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[42407] | 67 | # define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
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[42165] | 68 | do \
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| 69 | { \
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[42407] | 70 | if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
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| 71 | cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
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[42165] | 72 | } while (0)
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| 73 | #else
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[42407] | 74 | # define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
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| 75 | Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
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[42165] | 76 | #endif
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| 77 |
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| 78 |
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| 79 |
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[42193] | 80 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
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[42165] | 81 |
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| 82 | /**
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| 83 | * Does the lazy hidden selector register loading.
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| 84 | *
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| 85 | * @param pVCpu The current Virtual CPU.
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| 86 | * @param pSReg The selector register to lazily load hidden parts of.
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| 87 | */
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[42407] | 88 | static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
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[42165] | 89 | {
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[42407] | 90 | Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
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[43387] | 91 | Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
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[42407] | 92 | Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
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[42165] | 93 |
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| 94 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
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| 95 | {
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| 96 | /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
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| 97 | pSReg->Attr.u = 0;
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[42407] | 98 | pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
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[42165] | 99 | pSReg->Attr.n.u1DescType = 1; /* code/data segment */
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[42407] | 100 | pSReg->Attr.n.u2Dpl = 3;
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[42165] | 101 | pSReg->Attr.n.u1Present = 1;
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| 102 | pSReg->u32Limit = 0x0000ffff;
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| 103 | pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
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| 104 | pSReg->ValidSel = pSReg->Sel;
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| 105 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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| 106 | /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
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| 107 | }
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| 108 | else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
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| 109 | {
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| 110 | /* Real mode - leave the limit and flags alone here, at least for now. */
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| 111 | pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
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| 112 | pSReg->ValidSel = pSReg->Sel;
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| 113 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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| 114 | }
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| 115 | else
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| 116 | {
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| 117 | /* Protected mode - get it from the selector descriptor tables. */
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[42427] | 118 | if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
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[42165] | 119 | {
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| 120 | Assert(!CPUMIsGuestInLongMode(pVCpu));
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| 121 | pSReg->Sel = 0;
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| 122 | pSReg->u64Base = 0;
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| 123 | pSReg->u32Limit = 0;
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| 124 | pSReg->Attr.u = 0;
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| 125 | pSReg->ValidSel = 0;
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| 126 | pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
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| 127 | /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
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| 128 | }
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| 129 | else
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| 130 | SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
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| 131 | }
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| 132 | }
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| 133 |
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| 134 |
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| 135 | /**
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| 136 | * Makes sure the hidden CS and SS selector registers are valid, loading them if
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| 137 | * necessary.
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| 138 | *
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| 139 | * @param pVCpu The current virtual CPU.
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| 140 | */
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| 141 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
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| 142 | {
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[42407] | 143 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
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| 144 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
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[42165] | 145 | }
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| 146 |
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| 147 |
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| 148 | /**
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| 149 | * Loads a the hidden parts of a selector register.
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| 150 | *
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| 151 | * @param pVCpu The current virtual CPU.
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| 152 | */
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| 153 | VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
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| 154 | {
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[42407] | 155 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
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[42165] | 156 | }
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| 157 |
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[42193] | 158 | #endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
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[42165] | 159 |
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| 160 |
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| 161 | /**
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[41931] | 162 | * Obsolete.
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[1] | 163 | *
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[41931] | 164 | * We don't support nested hypervisor context interrupts or traps. Life is much
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| 165 | * simpler when we don't. It's also slightly faster at times.
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[1] | 166 | *
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| 167 | * @param pVM Handle to the virtual machine.
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| 168 | */
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[18927] | 169 | VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
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[1] | 170 | {
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[41931] | 171 | return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
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[1] | 172 | }
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| 173 |
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| 174 |
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| 175 | /**
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[41931] | 176 | * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
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[1] | 177 | *
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[42034] | 178 | * @param pVCpu Pointer to the VMCPU.
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[1] | 179 | */
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[41931] | 180 | VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
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[1] | 181 | {
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[41931] | 182 | return &pVCpu->cpum.s.Hyper;
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[1] | 183 | }
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| 184 |
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[12657] | 185 |
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[18927] | 186 | VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
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[1] | 187 | {
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[18927] | 188 | pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
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| 189 | pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
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[1] | 190 | }
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| 191 |
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[12657] | 192 |
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[18927] | 193 | VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
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[1] | 194 | {
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[18927] | 195 | pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
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[41931] | 196 | pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
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[1] | 197 | }
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| 198 |
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[12657] | 199 |
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[18927] | 200 | VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
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[1] | 201 | {
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[18927] | 202 | pVCpu->cpum.s.Hyper.cr3 = cr3;
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[16859] | 203 |
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| 204 | #ifdef IN_RC
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| 205 | /* Update the current CR3. */
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| 206 | ASMSetCR3(cr3);
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| 207 | #endif
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[1] | 208 | }
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| 209 |
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[18927] | 210 | VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
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[16859] | 211 | {
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[18927] | 212 | return pVCpu->cpum.s.Hyper.cr3;
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[16859] | 213 | }
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[12657] | 214 |
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[16859] | 215 |
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[18927] | 216 | VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
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[1] | 217 | {
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[41931] | 218 | pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
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[1] | 219 | }
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| 220 |
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[12657] | 221 |
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[18927] | 222 | VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
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[1] | 223 | {
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[41931] | 224 | pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
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[1] | 225 | }
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| 226 |
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[12657] | 227 |
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[18927] | 228 | VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
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[1] | 229 | {
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[41931] | 230 | pVCpu->cpum.s.Hyper.es.Sel = SelES;
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[1] | 231 | }
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| 232 |
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[12657] | 233 |
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[18927] | 234 | VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
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[1] | 235 | {
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[41931] | 236 | pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
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[1] | 237 | }
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| 238 |
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[12657] | 239 |
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[18927] | 240 | VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
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[1] | 241 | {
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[41931] | 242 | pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
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[1] | 243 | }
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| 244 |
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[12657] | 245 |
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[18927] | 246 | VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
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[1] | 247 | {
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[41931] | 248 | pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
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[1] | 249 | }
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| 250 |
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[12657] | 251 |
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[18927] | 252 | VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
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[1] | 253 | {
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[41931] | 254 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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[1] | 255 | }
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| 256 |
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[12657] | 257 |
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[41976] | 258 | VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
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| 259 | {
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| 260 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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| 261 | }
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| 262 |
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| 263 |
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[18927] | 264 | VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
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[1] | 265 | {
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[41931] | 266 | pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
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[1] | 267 | return VINF_SUCCESS;
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| 268 | }
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| 269 |
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[12657] | 270 |
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[18927] | 271 | VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
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[1] | 272 | {
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[41931] | 273 | pVCpu->cpum.s.Hyper.eip = u32EIP;
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[1] | 274 | }
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| 275 |
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[12657] | 276 |
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[41976] | 277 | /**
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| 278 | * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
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| 279 | * EFLAGS and EIP prior to resuming guest execution.
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| 280 | *
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| 281 | * All general register not given as a parameter will be set to 0. The EFLAGS
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| 282 | * register will be set to sane values for C/C++ code execution with interrupts
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| 283 | * disabled and IOPL 0.
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| 284 | *
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| 285 | * @param pVCpu The current virtual CPU.
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| 286 | * @param u32EIP The EIP value.
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| 287 | * @param u32ESP The ESP value.
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| 288 | * @param u32EAX The EAX value.
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| 289 | * @param u32EDX The EDX value.
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| 290 | */
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| 291 | VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
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| 292 | {
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| 293 | pVCpu->cpum.s.Hyper.eip = u32EIP;
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| 294 | pVCpu->cpum.s.Hyper.esp = u32ESP;
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| 295 | pVCpu->cpum.s.Hyper.eax = u32EAX;
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| 296 | pVCpu->cpum.s.Hyper.edx = u32EDX;
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| 297 | pVCpu->cpum.s.Hyper.ecx = 0;
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| 298 | pVCpu->cpum.s.Hyper.ebx = 0;
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| 299 | pVCpu->cpum.s.Hyper.ebp = 0;
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| 300 | pVCpu->cpum.s.Hyper.esi = 0;
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| 301 | pVCpu->cpum.s.Hyper.edi = 0;
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| 302 | pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
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| 303 | }
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| 304 |
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| 305 |
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[18927] | 306 | VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
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[1] | 307 | {
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[41906] | 308 | pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
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[1] | 309 | }
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| 310 |
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[12657] | 311 |
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[18927] | 312 | VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
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[1] | 313 | {
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[41906] | 314 | pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
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[1] | 315 | }
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| 316 |
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[12657] | 317 |
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[18927] | 318 | VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
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[1] | 319 | {
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[18927] | 320 | pVCpu->cpum.s.Hyper.dr[0] = uDr0;
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[1] | 321 | /** @todo in GC we must load it! */
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| 322 | }
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| 323 |
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[12657] | 324 |
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[18927] | 325 | VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
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[1] | 326 | {
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[18927] | 327 | pVCpu->cpum.s.Hyper.dr[1] = uDr1;
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[1] | 328 | /** @todo in GC we must load it! */
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| 329 | }
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| 330 |
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[12657] | 331 |
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[18927] | 332 | VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
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[1] | 333 | {
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[18927] | 334 | pVCpu->cpum.s.Hyper.dr[2] = uDr2;
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[1] | 335 | /** @todo in GC we must load it! */
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| 336 | }
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| 337 |
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[12657] | 338 |
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[18927] | 339 | VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
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[1] | 340 | {
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[18927] | 341 | pVCpu->cpum.s.Hyper.dr[3] = uDr3;
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[1] | 342 | /** @todo in GC we must load it! */
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| 343 | }
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| 344 |
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[12657] | 345 |
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[18927] | 346 | VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
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[1] | 347 | {
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[18927] | 348 | pVCpu->cpum.s.Hyper.dr[6] = uDr6;
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[1] | 349 | /** @todo in GC we must load it! */
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| 350 | }
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| 351 |
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[12657] | 352 |
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[18927] | 353 | VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
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[1] | 354 | {
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[18927] | 355 | pVCpu->cpum.s.Hyper.dr[7] = uDr7;
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[1] | 356 | /** @todo in GC we must load it! */
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| 357 | }
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| 358 |
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| 359 |
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[18927] | 360 | VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
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[1] | 361 | {
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[41931] | 362 | return pVCpu->cpum.s.Hyper.cs.Sel;
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[1] | 363 | }
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| 364 |
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[12657] | 365 |
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[18927] | 366 | VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
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[1] | 367 | {
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[41931] | 368 | return pVCpu->cpum.s.Hyper.ds.Sel;
|
---|
[1] | 369 | }
|
---|
| 370 |
|
---|
[12657] | 371 |
|
---|
[18927] | 372 | VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
|
---|
[1] | 373 | {
|
---|
[41931] | 374 | return pVCpu->cpum.s.Hyper.es.Sel;
|
---|
[1] | 375 | }
|
---|
| 376 |
|
---|
[12657] | 377 |
|
---|
[18927] | 378 | VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
|
---|
[1] | 379 | {
|
---|
[41931] | 380 | return pVCpu->cpum.s.Hyper.fs.Sel;
|
---|
[1] | 381 | }
|
---|
| 382 |
|
---|
[12657] | 383 |
|
---|
[18927] | 384 | VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
|
---|
[1] | 385 | {
|
---|
[41931] | 386 | return pVCpu->cpum.s.Hyper.gs.Sel;
|
---|
[1] | 387 | }
|
---|
| 388 |
|
---|
[12657] | 389 |
|
---|
[18927] | 390 | VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
|
---|
[1] | 391 | {
|
---|
[41931] | 392 | return pVCpu->cpum.s.Hyper.ss.Sel;
|
---|
[1] | 393 | }
|
---|
| 394 |
|
---|
| 395 |
|
---|
[18927] | 396 | VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
|
---|
[1] | 397 | {
|
---|
[41931] | 398 | return pVCpu->cpum.s.Hyper.eax;
|
---|
[1] | 399 | }
|
---|
| 400 |
|
---|
| 401 |
|
---|
[18927] | 402 | VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
|
---|
[1] | 403 | {
|
---|
[41931] | 404 | return pVCpu->cpum.s.Hyper.ebx;
|
---|
[1] | 405 | }
|
---|
| 406 |
|
---|
| 407 |
|
---|
[18927] | 408 | VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
|
---|
[1] | 409 | {
|
---|
[41931] | 410 | return pVCpu->cpum.s.Hyper.ecx;
|
---|
[1] | 411 | }
|
---|
| 412 |
|
---|
| 413 |
|
---|
[18927] | 414 | VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
|
---|
[1] | 415 | {
|
---|
[41931] | 416 | return pVCpu->cpum.s.Hyper.edx;
|
---|
[1] | 417 | }
|
---|
| 418 |
|
---|
[12657] | 419 |
|
---|
[18927] | 420 | VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
|
---|
[1] | 421 | {
|
---|
[41931] | 422 | return pVCpu->cpum.s.Hyper.esi;
|
---|
[1] | 423 | }
|
---|
| 424 |
|
---|
[12657] | 425 |
|
---|
[18927] | 426 | VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
|
---|
[1] | 427 | {
|
---|
[41931] | 428 | return pVCpu->cpum.s.Hyper.edi;
|
---|
[1] | 429 | }
|
---|
| 430 |
|
---|
[12657] | 431 |
|
---|
[18927] | 432 | VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
|
---|
[1] | 433 | {
|
---|
[41931] | 434 | return pVCpu->cpum.s.Hyper.ebp;
|
---|
[1] | 435 | }
|
---|
| 436 |
|
---|
[12657] | 437 |
|
---|
[18927] | 438 | VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
|
---|
[1] | 439 | {
|
---|
[41931] | 440 | return pVCpu->cpum.s.Hyper.esp;
|
---|
[1] | 441 | }
|
---|
| 442 |
|
---|
[12657] | 443 |
|
---|
[18927] | 444 | VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
|
---|
[1] | 445 | {
|
---|
[41931] | 446 | return pVCpu->cpum.s.Hyper.eflags.u32;
|
---|
[1] | 447 | }
|
---|
| 448 |
|
---|
[12657] | 449 |
|
---|
[18927] | 450 | VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
|
---|
[1] | 451 | {
|
---|
[41931] | 452 | return pVCpu->cpum.s.Hyper.eip;
|
---|
[1] | 453 | }
|
---|
| 454 |
|
---|
[12657] | 455 |
|
---|
[18927] | 456 | VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
|
---|
[9841] | 457 | {
|
---|
[41931] | 458 | return pVCpu->cpum.s.Hyper.rip;
|
---|
[9841] | 459 | }
|
---|
| 460 |
|
---|
[12657] | 461 |
|
---|
[18927] | 462 | VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
[1] | 463 | {
|
---|
| 464 | if (pcbLimit)
|
---|
[18927] | 465 | *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
|
---|
| 466 | return pVCpu->cpum.s.Hyper.idtr.pIdt;
|
---|
[1] | 467 | }
|
---|
| 468 |
|
---|
[12657] | 469 |
|
---|
[18927] | 470 | VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
[1] | 471 | {
|
---|
| 472 | if (pcbLimit)
|
---|
[18927] | 473 | *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
|
---|
| 474 | return pVCpu->cpum.s.Hyper.gdtr.pGdt;
|
---|
[1] | 475 | }
|
---|
| 476 |
|
---|
[12657] | 477 |
|
---|
[18927] | 478 | VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
|
---|
[1] | 479 | {
|
---|
[41906] | 480 | return pVCpu->cpum.s.Hyper.ldtr.Sel;
|
---|
[1] | 481 | }
|
---|
| 482 |
|
---|
[12657] | 483 |
|
---|
[18927] | 484 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
|
---|
[1] | 485 | {
|
---|
[18927] | 486 | return pVCpu->cpum.s.Hyper.dr[0];
|
---|
[1] | 487 | }
|
---|
| 488 |
|
---|
[12657] | 489 |
|
---|
[18927] | 490 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
|
---|
[1] | 491 | {
|
---|
[18927] | 492 | return pVCpu->cpum.s.Hyper.dr[1];
|
---|
[1] | 493 | }
|
---|
| 494 |
|
---|
[12657] | 495 |
|
---|
[18927] | 496 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
|
---|
[1] | 497 | {
|
---|
[18927] | 498 | return pVCpu->cpum.s.Hyper.dr[2];
|
---|
[1] | 499 | }
|
---|
| 500 |
|
---|
[12657] | 501 |
|
---|
[18927] | 502 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
|
---|
[1] | 503 | {
|
---|
[18927] | 504 | return pVCpu->cpum.s.Hyper.dr[3];
|
---|
[1] | 505 | }
|
---|
| 506 |
|
---|
[12657] | 507 |
|
---|
[18927] | 508 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
|
---|
[1] | 509 | {
|
---|
[18927] | 510 | return pVCpu->cpum.s.Hyper.dr[6];
|
---|
[1] | 511 | }
|
---|
| 512 |
|
---|
[12657] | 513 |
|
---|
[18927] | 514 | VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
|
---|
[1] | 515 | {
|
---|
[18927] | 516 | return pVCpu->cpum.s.Hyper.dr[7];
|
---|
[1] | 517 | }
|
---|
| 518 |
|
---|
| 519 |
|
---|
| 520 | /**
|
---|
| 521 | * Gets the pointer to the internal CPUMCTXCORE structure.
|
---|
| 522 | * This is only for reading in order to save a few calls.
|
---|
| 523 | *
|
---|
[18927] | 524 | * @param pVCpu Handle to the virtual cpu.
|
---|
[1] | 525 | */
|
---|
[18927] | 526 | VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
|
---|
[1] | 527 | {
|
---|
[13975] | 528 | return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
|
---|
| 529 | }
|
---|
[1] | 530 |
|
---|
[13975] | 531 |
|
---|
[1] | 532 | /**
|
---|
[42034] | 533 | * Queries the pointer to the internal CPUMCTX structure.
|
---|
[1] | 534 | *
|
---|
[13532] | 535 | * @returns The CPUMCTX pointer.
|
---|
[18927] | 536 | * @param pVCpu Handle to the virtual cpu.
|
---|
[1] | 537 | */
|
---|
[18927] | 538 | VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
|
---|
[1] | 539 | {
|
---|
[13960] | 540 | return &pVCpu->cpum.s.Guest;
|
---|
| 541 | }
|
---|
| 542 |
|
---|
[36762] | 543 | VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
|
---|
[1] | 544 | {
|
---|
[42705] | 545 | #ifdef VBOX_WITH_IEM
|
---|
| 546 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
[43387] | 547 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
[42705] | 548 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
|
---|
| 549 | # endif
|
---|
| 550 | #endif
|
---|
[36762] | 551 | pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
|
---|
| 552 | pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
|
---|
[18927] | 553 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
|
---|
[42452] | 554 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
[1] | 555 | }
|
---|
| 556 |
|
---|
[36762] | 557 | VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
|
---|
[1] | 558 | {
|
---|
[42705] | 559 | #ifdef VBOX_WITH_IEM
|
---|
| 560 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
[43387] | 561 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
[42705] | 562 | VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
|
---|
| 563 | # endif
|
---|
| 564 | #endif
|
---|
[36762] | 565 | pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
|
---|
| 566 | pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
|
---|
[18927] | 567 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
|
---|
[42452] | 568 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
[1] | 569 | }
|
---|
| 570 |
|
---|
[18927] | 571 | VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
|
---|
[1] | 572 | {
|
---|
[42705] | 573 | #ifdef VBOX_WITH_IEM
|
---|
| 574 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
[43387] | 575 | if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
[42705] | 576 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
|
---|
| 577 | # endif
|
---|
| 578 | #endif
|
---|
[41906] | 579 | pVCpu->cpum.s.Guest.tr.Sel = tr;
|
---|
[18927] | 580 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
|
---|
[42452] | 581 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
[1] | 582 | }
|
---|
| 583 |
|
---|
[18927] | 584 | VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
|
---|
[1] | 585 | {
|
---|
[42705] | 586 | #ifdef VBOX_WITH_IEM
|
---|
| 587 | # ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
| 588 | if ( ( ldtr != 0
|
---|
| 589 | || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
|
---|
[43387] | 590 | && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
|
---|
[42705] | 591 | VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
|
---|
| 592 | # endif
|
---|
| 593 | #endif
|
---|
[42407] | 594 | pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
|
---|
| 595 | /* The caller will set more hidden bits if it has them. */
|
---|
| 596 | pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
|
---|
| 597 | pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
|
---|
[18927] | 598 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
|
---|
[42452] | 599 | return VINF_SUCCESS; /* formality, consider it void. */
|
---|
[1] | 600 | }
|
---|
| 601 |
|
---|
| 602 |
|
---|
[5389] | 603 | /**
|
---|
[5695] | 604 | * Set the guest CR0.
|
---|
| 605 | *
|
---|
| 606 | * When called in GC, the hyper CR0 may be updated if that is
|
---|
| 607 | * required. The caller only has to take special action if AM,
|
---|
| 608 | * WP, PG or PE changes.
|
---|
| 609 | *
|
---|
[5389] | 610 | * @returns VINF_SUCCESS (consider it void).
|
---|
[18927] | 611 | * @param pVCpu Handle to the virtual cpu.
|
---|
[5389] | 612 | * @param cr0 The new CR0 value.
|
---|
| 613 | */
|
---|
[18927] | 614 | VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
|
---|
[1] | 615 | {
|
---|
[13832] | 616 | #ifdef IN_RC
|
---|
[5389] | 617 | /*
|
---|
[5695] | 618 | * Check if we need to change hypervisor CR0 because
|
---|
[5389] | 619 | * of math stuff.
|
---|
| 620 | */
|
---|
[31079] | 621 | if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
|
---|
[18927] | 622 | != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
|
---|
[5389] | 623 | {
|
---|
[18927] | 624 | if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
|
---|
[5389] | 625 | {
|
---|
[5695] | 626 | /*
|
---|
| 627 | * We haven't saved the host FPU state yet, so TS and MT are both set
|
---|
[5389] | 628 | * and EM should be reflecting the guest EM (it always does this).
|
---|
| 629 | */
|
---|
[18927] | 630 | if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
|
---|
[5389] | 631 | {
|
---|
| 632 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
| 633 | AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
|
---|
[18927] | 634 | AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
|
---|
[5389] | 635 | HyperCR0 &= ~X86_CR0_EM;
|
---|
| 636 | HyperCR0 |= cr0 & X86_CR0_EM;
|
---|
| 637 | Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
|
---|
| 638 | ASMSetCR0(HyperCR0);
|
---|
| 639 | }
|
---|
[12657] | 640 | # ifdef VBOX_STRICT
|
---|
[5389] | 641 | else
|
---|
| 642 | {
|
---|
| 643 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
| 644 | AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
|
---|
[18927] | 645 | AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
|
---|
[5389] | 646 | }
|
---|
[12657] | 647 | # endif
|
---|
[5389] | 648 | }
|
---|
| 649 | else
|
---|
| 650 | {
|
---|
| 651 | /*
|
---|
[5695] | 652 | * Already saved the state, so we're just mirroring
|
---|
[5389] | 653 | * the guest flags.
|
---|
| 654 | */
|
---|
| 655 | uint32_t HyperCR0 = ASMGetCR0();
|
---|
[31079] | 656 | AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
|
---|
[18927] | 657 | == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
|
---|
| 658 | ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
|
---|
[5389] | 659 | HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
|
---|
| 660 | HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
|
---|
| 661 | Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
|
---|
| 662 | ASMSetCR0(HyperCR0);
|
---|
| 663 | }
|
---|
| 664 | }
|
---|
[13832] | 665 | #endif /* IN_RC */
|
---|
[5389] | 666 |
|
---|
[5695] | 667 | /*
|
---|
| 668 | * Check for changes causing TLB flushes (for REM).
|
---|
| 669 | * The caller is responsible for calling PGM when appropriate.
|
---|
[5389] | 670 | */
|
---|
[31079] | 671 | if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
|
---|
[18927] | 672 | != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
|
---|
| 673 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
|
---|
| 674 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
|
---|
[5389] | 675 |
|
---|
[18927] | 676 | pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
|
---|
[1] | 677 | return VINF_SUCCESS;
|
---|
| 678 | }
|
---|
| 679 |
|
---|
[12657] | 680 |
|
---|
[18927] | 681 | VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
|
---|
[1] | 682 | {
|
---|
[18927] | 683 | pVCpu->cpum.s.Guest.cr2 = cr2;
|
---|
[1] | 684 | return VINF_SUCCESS;
|
---|
| 685 | }
|
---|
| 686 |
|
---|
[12657] | 687 |
|
---|
[18927] | 688 | VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
|
---|
[1] | 689 | {
|
---|
[18927] | 690 | pVCpu->cpum.s.Guest.cr3 = cr3;
|
---|
| 691 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
|
---|
[1] | 692 | return VINF_SUCCESS;
|
---|
| 693 | }
|
---|
| 694 |
|
---|
[12657] | 695 |
|
---|
[18927] | 696 | VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
|
---|
[1] | 697 | {
|
---|
[31060] | 698 | if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
|
---|
[18927] | 699 | != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
|
---|
| 700 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
|
---|
| 701 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
|
---|
| 702 | if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
|
---|
[1] | 703 | cr4 &= ~X86_CR4_OSFSXR;
|
---|
[18927] | 704 | pVCpu->cpum.s.Guest.cr4 = cr4;
|
---|
[1] | 705 | return VINF_SUCCESS;
|
---|
| 706 | }
|
---|
| 707 |
|
---|
[12657] | 708 |
|
---|
[18927] | 709 | VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
|
---|
[1] | 710 | {
|
---|
[18927] | 711 | pVCpu->cpum.s.Guest.eflags.u32 = eflags;
|
---|
[1] | 712 | return VINF_SUCCESS;
|
---|
| 713 | }
|
---|
| 714 |
|
---|
[12657] | 715 |
|
---|
[18927] | 716 | VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
|
---|
[1] | 717 | {
|
---|
[18927] | 718 | pVCpu->cpum.s.Guest.eip = eip;
|
---|
[1] | 719 | return VINF_SUCCESS;
|
---|
| 720 | }
|
---|
| 721 |
|
---|
[12657] | 722 |
|
---|
[18927] | 723 | VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
|
---|
[1] | 724 | {
|
---|
[18927] | 725 | pVCpu->cpum.s.Guest.eax = eax;
|
---|
[1] | 726 | return VINF_SUCCESS;
|
---|
| 727 | }
|
---|
| 728 |
|
---|
[12657] | 729 |
|
---|
[18927] | 730 | VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
|
---|
[1] | 731 | {
|
---|
[18927] | 732 | pVCpu->cpum.s.Guest.ebx = ebx;
|
---|
[1] | 733 | return VINF_SUCCESS;
|
---|
| 734 | }
|
---|
| 735 |
|
---|
[12657] | 736 |
|
---|
[18927] | 737 | VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
|
---|
[1] | 738 | {
|
---|
[18927] | 739 | pVCpu->cpum.s.Guest.ecx = ecx;
|
---|
[1] | 740 | return VINF_SUCCESS;
|
---|
| 741 | }
|
---|
| 742 |
|
---|
[12657] | 743 |
|
---|
[18927] | 744 | VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
|
---|
[1] | 745 | {
|
---|
[18927] | 746 | pVCpu->cpum.s.Guest.edx = edx;
|
---|
[1] | 747 | return VINF_SUCCESS;
|
---|
| 748 | }
|
---|
| 749 |
|
---|
[12657] | 750 |
|
---|
[18927] | 751 | VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
|
---|
[1] | 752 | {
|
---|
[18927] | 753 | pVCpu->cpum.s.Guest.esp = esp;
|
---|
[1] | 754 | return VINF_SUCCESS;
|
---|
| 755 | }
|
---|
| 756 |
|
---|
[12657] | 757 |
|
---|
[18927] | 758 | VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
|
---|
[1] | 759 | {
|
---|
[18927] | 760 | pVCpu->cpum.s.Guest.ebp = ebp;
|
---|
[1] | 761 | return VINF_SUCCESS;
|
---|
| 762 | }
|
---|
| 763 |
|
---|
[12657] | 764 |
|
---|
[18927] | 765 | VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
|
---|
[1] | 766 | {
|
---|
[18927] | 767 | pVCpu->cpum.s.Guest.esi = esi;
|
---|
[1] | 768 | return VINF_SUCCESS;
|
---|
| 769 | }
|
---|
| 770 |
|
---|
[12657] | 771 |
|
---|
[18927] | 772 | VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
|
---|
[1] | 773 | {
|
---|
[18927] | 774 | pVCpu->cpum.s.Guest.edi = edi;
|
---|
[1] | 775 | return VINF_SUCCESS;
|
---|
| 776 | }
|
---|
| 777 |
|
---|
[12657] | 778 |
|
---|
[18927] | 779 | VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
|
---|
[1] | 780 | {
|
---|
[41906] | 781 | pVCpu->cpum.s.Guest.ss.Sel = ss;
|
---|
[1] | 782 | return VINF_SUCCESS;
|
---|
| 783 | }
|
---|
| 784 |
|
---|
[12657] | 785 |
|
---|
[18927] | 786 | VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
|
---|
[1] | 787 | {
|
---|
[41906] | 788 | pVCpu->cpum.s.Guest.cs.Sel = cs;
|
---|
[1] | 789 | return VINF_SUCCESS;
|
---|
| 790 | }
|
---|
| 791 |
|
---|
[12657] | 792 |
|
---|
[18927] | 793 | VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
|
---|
[1] | 794 | {
|
---|
[41906] | 795 | pVCpu->cpum.s.Guest.ds.Sel = ds;
|
---|
[1] | 796 | return VINF_SUCCESS;
|
---|
| 797 | }
|
---|
| 798 |
|
---|
[12657] | 799 |
|
---|
[18927] | 800 | VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
|
---|
[1] | 801 | {
|
---|
[41906] | 802 | pVCpu->cpum.s.Guest.es.Sel = es;
|
---|
[1] | 803 | return VINF_SUCCESS;
|
---|
| 804 | }
|
---|
| 805 |
|
---|
[12657] | 806 |
|
---|
[18927] | 807 | VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
|
---|
[1] | 808 | {
|
---|
[41906] | 809 | pVCpu->cpum.s.Guest.fs.Sel = fs;
|
---|
[1] | 810 | return VINF_SUCCESS;
|
---|
| 811 | }
|
---|
| 812 |
|
---|
[12657] | 813 |
|
---|
[18927] | 814 | VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
|
---|
[1] | 815 | {
|
---|
[41906] | 816 | pVCpu->cpum.s.Guest.gs.Sel = gs;
|
---|
[1] | 817 | return VINF_SUCCESS;
|
---|
| 818 | }
|
---|
| 819 |
|
---|
[12657] | 820 |
|
---|
[18927] | 821 | VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
|
---|
[7730] | 822 | {
|
---|
[18927] | 823 | pVCpu->cpum.s.Guest.msrEFER = val;
|
---|
[7730] | 824 | }
|
---|
[1] | 825 |
|
---|
[12657] | 826 |
|
---|
[30861] | 827 | /**
|
---|
| 828 | * Query an MSR.
|
---|
| 829 | *
|
---|
| 830 | * The caller is responsible for checking privilege if the call is the result
|
---|
[41836] | 831 | * of a RDMSR instruction. We'll do the rest.
|
---|
[30861] | 832 | *
|
---|
| 833 | * @retval VINF_SUCCESS on success.
|
---|
| 834 | * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
|
---|
| 835 | * expected to take the appropriate actions. @a *puValue is set to 0.
|
---|
[41836] | 836 | * @param pVCpu Pointer to the VMCPU.
|
---|
[30861] | 837 | * @param idMsr The MSR.
|
---|
[41836] | 838 | * @param puValue Where to return the value.
|
---|
[30861] | 839 | *
|
---|
| 840 | * @remarks This will always return the right values, even when we're in the
|
---|
| 841 | * recompiler.
|
---|
| 842 | */
|
---|
| 843 | VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
|
---|
[9852] | 844 | {
|
---|
[30861] | 845 | /*
|
---|
| 846 | * If we don't indicate MSR support in the CPUID feature bits, indicate
|
---|
| 847 | * that a #GP(0) should be raised.
|
---|
| 848 | */
|
---|
| 849 | if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
|
---|
| 850 | {
|
---|
| 851 | *puValue = 0;
|
---|
[40170] | 852 | return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
|
---|
[30861] | 853 | }
|
---|
[9852] | 854 |
|
---|
[30861] | 855 | int rc = VINF_SUCCESS;
|
---|
| 856 | uint8_t const u8Multiplier = 4;
|
---|
[9852] | 857 | switch (idMsr)
|
---|
| 858 | {
|
---|
[18082] | 859 | case MSR_IA32_TSC:
|
---|
[30861] | 860 | *puValue = TMCpuTickGet(pVCpu);
|
---|
[18082] | 861 | break;
|
---|
| 862 |
|
---|
[30861] | 863 | case MSR_IA32_APICBASE:
|
---|
[43657] | 864 | {
|
---|
| 865 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
[43667] | 866 | if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
|
---|
[43657] | 867 | && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
|
---|
[43667] | 868 | || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
|
---|
[43657] | 869 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
|
---|
[43667] | 870 | && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
|
---|
| 871 | || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
|
---|
| 872 | && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
|
---|
[43657] | 873 | {
|
---|
| 874 | *puValue = pVCpu->cpum.s.Guest.msrApicBase;
|
---|
| 875 | }
|
---|
[30861] | 876 | else
|
---|
| 877 | {
|
---|
| 878 | *puValue = 0;
|
---|
| 879 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 880 | }
|
---|
| 881 | break;
|
---|
[43657] | 882 | }
|
---|
[30861] | 883 |
|
---|
[12657] | 884 | case MSR_IA32_CR_PAT:
|
---|
[30861] | 885 | *puValue = pVCpu->cpum.s.Guest.msrPAT;
|
---|
[12657] | 886 | break;
|
---|
[9852] | 887 |
|
---|
[12657] | 888 | case MSR_IA32_SYSENTER_CS:
|
---|
[30861] | 889 | *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
|
---|
[12657] | 890 | break;
|
---|
[9852] | 891 |
|
---|
[12657] | 892 | case MSR_IA32_SYSENTER_EIP:
|
---|
[30861] | 893 | *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
|
---|
[12657] | 894 | break;
|
---|
[9852] | 895 |
|
---|
[12657] | 896 | case MSR_IA32_SYSENTER_ESP:
|
---|
[30861] | 897 | *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
|
---|
[12657] | 898 | break;
|
---|
[9852] | 899 |
|
---|
[40170] | 900 | case MSR_IA32_MTRR_CAP:
|
---|
| 901 | {
|
---|
| 902 | /* This is currently a bit weird. :-) */
|
---|
| 903 | uint8_t const cVariableRangeRegs = 0;
|
---|
| 904 | bool const fSystemManagementRangeRegisters = false;
|
---|
| 905 | bool const fFixedRangeRegisters = false;
|
---|
| 906 | bool const fWriteCombiningType = false;
|
---|
| 907 | *puValue = cVariableRangeRegs
|
---|
| 908 | | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
|
---|
| 909 | | (fWriteCombiningType ? RT_BIT_64(10) : 0)
|
---|
| 910 | | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
|
---|
| 911 | break;
|
---|
| 912 | }
|
---|
| 913 |
|
---|
| 914 | case MSR_IA32_MTRR_DEF_TYPE:
|
---|
| 915 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
|
---|
| 916 | break;
|
---|
| 917 |
|
---|
| 918 | case IA32_MTRR_FIX64K_00000:
|
---|
| 919 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
|
---|
| 920 | break;
|
---|
| 921 | case IA32_MTRR_FIX16K_80000:
|
---|
| 922 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
|
---|
| 923 | break;
|
---|
| 924 | case IA32_MTRR_FIX16K_A0000:
|
---|
| 925 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
|
---|
| 926 | break;
|
---|
| 927 | case IA32_MTRR_FIX4K_C0000:
|
---|
| 928 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
|
---|
| 929 | break;
|
---|
| 930 | case IA32_MTRR_FIX4K_C8000:
|
---|
| 931 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
|
---|
| 932 | break;
|
---|
| 933 | case IA32_MTRR_FIX4K_D0000:
|
---|
| 934 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
|
---|
| 935 | break;
|
---|
| 936 | case IA32_MTRR_FIX4K_D8000:
|
---|
| 937 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
|
---|
| 938 | break;
|
---|
| 939 | case IA32_MTRR_FIX4K_E0000:
|
---|
| 940 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
|
---|
| 941 | break;
|
---|
| 942 | case IA32_MTRR_FIX4K_E8000:
|
---|
| 943 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
|
---|
| 944 | break;
|
---|
| 945 | case IA32_MTRR_FIX4K_F0000:
|
---|
| 946 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
|
---|
| 947 | break;
|
---|
| 948 | case IA32_MTRR_FIX4K_F8000:
|
---|
| 949 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
|
---|
| 950 | break;
|
---|
| 951 |
|
---|
[12657] | 952 | case MSR_K6_EFER:
|
---|
[30861] | 953 | *puValue = pVCpu->cpum.s.Guest.msrEFER;
|
---|
[12657] | 954 | break;
|
---|
[9852] | 955 |
|
---|
[12657] | 956 | case MSR_K8_SF_MASK:
|
---|
[30861] | 957 | *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
|
---|
[12657] | 958 | break;
|
---|
[9852] | 959 |
|
---|
[12657] | 960 | case MSR_K6_STAR:
|
---|
[30861] | 961 | *puValue = pVCpu->cpum.s.Guest.msrSTAR;
|
---|
[12657] | 962 | break;
|
---|
[9852] | 963 |
|
---|
[12657] | 964 | case MSR_K8_LSTAR:
|
---|
[30861] | 965 | *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
|
---|
[12657] | 966 | break;
|
---|
[9852] | 967 |
|
---|
[12657] | 968 | case MSR_K8_CSTAR:
|
---|
[30861] | 969 | *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
|
---|
[12657] | 970 | break;
|
---|
[9852] | 971 |
|
---|
[30861] | 972 | case MSR_K8_FS_BASE:
|
---|
[41906] | 973 | *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
|
---|
[30861] | 974 | break;
|
---|
| 975 |
|
---|
| 976 | case MSR_K8_GS_BASE:
|
---|
[41906] | 977 | *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
|
---|
[30861] | 978 | break;
|
---|
| 979 |
|
---|
[12657] | 980 | case MSR_K8_KERNEL_GS_BASE:
|
---|
[30861] | 981 | *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
|
---|
[12657] | 982 | break;
|
---|
[9852] | 983 |
|
---|
[14411] | 984 | case MSR_K8_TSC_AUX:
|
---|
[40170] | 985 | *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
|
---|
[14411] | 986 | break;
|
---|
| 987 |
|
---|
[24753] | 988 | case MSR_IA32_PERF_STATUS:
|
---|
[30861] | 989 | /** @todo could really be not exactly correct, maybe use host's values */
|
---|
| 990 | *puValue = UINT64_C(1000) /* TSC increment by tick */
|
---|
| 991 | | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
|
---|
| 992 | | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
|
---|
[24753] | 993 | break;
|
---|
| 994 |
|
---|
[30861] | 995 | case MSR_IA32_FSB_CLOCK_STS:
|
---|
| 996 | /*
|
---|
[28030] | 997 | * Encoded as:
|
---|
| 998 | * 0 - 266
|
---|
| 999 | * 1 - 133
|
---|
| 1000 | * 2 - 200
|
---|
| 1001 | * 3 - return 166
|
---|
| 1002 | * 5 - return 100
|
---|
| 1003 | */
|
---|
[30861] | 1004 | *puValue = (2 << 4);
|
---|
[28030] | 1005 | break;
|
---|
| 1006 |
|
---|
[26993] | 1007 | case MSR_IA32_PLATFORM_INFO:
|
---|
[30861] | 1008 | *puValue = (u8Multiplier << 8) /* Flex ratio max */
|
---|
| 1009 | | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
|
---|
[26993] | 1010 | break;
|
---|
| 1011 |
|
---|
[28030] | 1012 | case MSR_IA32_THERM_STATUS:
|
---|
[33540] | 1013 | /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
|
---|
[39038] | 1014 | *puValue = RT_BIT(31) /* validity bit */
|
---|
| 1015 | | (UINT64_C(20) << 16) /* degrees till TCC */;
|
---|
[28030] | 1016 | break;
|
---|
| 1017 |
|
---|
[27331] | 1018 | case MSR_IA32_MISC_ENABLE:
|
---|
| 1019 | #if 0
|
---|
| 1020 | /* Needs to be tested more before enabling. */
|
---|
[30861] | 1021 | *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
|
---|
[27331] | 1022 | #else
|
---|
[36315] | 1023 | /* Currenty we don't allow guests to modify enable MSRs. */
|
---|
| 1024 | *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
|
---|
| 1025 |
|
---|
| 1026 | if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
|
---|
[36639] | 1027 |
|
---|
[36315] | 1028 | *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
|
---|
| 1029 | /** @todo: add more cpuid-controlled features this way. */
|
---|
[27331] | 1030 | #endif
|
---|
| 1031 | break;
|
---|
| 1032 |
|
---|
[30861] | 1033 | #if 0 /*def IN_RING0 */
|
---|
| 1034 | case MSR_IA32_PLATFORM_ID:
|
---|
| 1035 | case MSR_IA32_BIOS_SIGN_ID:
|
---|
| 1036 | if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
|
---|
| 1037 | {
|
---|
| 1038 | /* Available since the P6 family. VT-x implies that this feature is present. */
|
---|
| 1039 | if (idMsr == MSR_IA32_PLATFORM_ID)
|
---|
| 1040 | *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
|
---|
| 1041 | else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
|
---|
| 1042 | *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
|
---|
| 1043 | break;
|
---|
| 1044 | }
|
---|
| 1045 | /* no break */
|
---|
| 1046 | #endif
|
---|
| 1047 |
|
---|
[42640] | 1048 | /*
|
---|
| 1049 | * Intel specifics MSRs:
|
---|
| 1050 | */
|
---|
[42647] | 1051 | case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
|
---|
[42640] | 1052 | case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
|
---|
[42647] | 1053 | /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
|
---|
| 1054 | case MSR_IA32_MCP_CAP: /* fam/mod >= 6_01 */
|
---|
| 1055 | /*case MSR_IA32_MCP_STATUS: - indicated as not present in CAP */
|
---|
| 1056 | /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
|
---|
| 1057 | case MSR_IA32_MC0_CTL:
|
---|
| 1058 | case MSR_IA32_MC0_STATUS:
|
---|
[42640] | 1059 | *puValue = 0;
|
---|
| 1060 | if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
|
---|
| 1061 | {
|
---|
| 1062 | Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
|
---|
| 1063 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 1064 | }
|
---|
| 1065 | break;
|
---|
| 1066 |
|
---|
[12657] | 1067 | default:
|
---|
[42640] | 1068 | /*
|
---|
| 1069 | * Hand the X2APIC range to PDM and the APIC.
|
---|
| 1070 | */
|
---|
[30861] | 1071 | if ( idMsr >= MSR_IA32_APIC_START
|
---|
| 1072 | && idMsr < MSR_IA32_APIC_END)
|
---|
| 1073 | {
|
---|
| 1074 | rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
|
---|
| 1075 | if (RT_SUCCESS(rc))
|
---|
| 1076 | rc = VINF_SUCCESS;
|
---|
| 1077 | else
|
---|
| 1078 | {
|
---|
| 1079 | *puValue = 0;
|
---|
| 1080 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 1081 | }
|
---|
| 1082 | }
|
---|
| 1083 | else
|
---|
| 1084 | {
|
---|
| 1085 | *puValue = 0;
|
---|
| 1086 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 1087 | }
|
---|
[12657] | 1088 | break;
|
---|
[9852] | 1089 | }
|
---|
[30861] | 1090 |
|
---|
| 1091 | return rc;
|
---|
[9852] | 1092 | }
|
---|
| 1093 |
|
---|
[30861] | 1094 |
|
---|
| 1095 | /**
|
---|
| 1096 | * Sets the MSR.
|
---|
| 1097 | *
|
---|
| 1098 | * The caller is responsible for checking privilege if the call is the result
|
---|
[41836] | 1099 | * of a WRMSR instruction. We'll do the rest.
|
---|
[30861] | 1100 | *
|
---|
| 1101 | * @retval VINF_SUCCESS on success.
|
---|
| 1102 | * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
|
---|
| 1103 | * appropriate actions.
|
---|
| 1104 | *
|
---|
[41836] | 1105 | * @param pVCpu Pointer to the VMCPU.
|
---|
[30861] | 1106 | * @param idMsr The MSR id.
|
---|
| 1107 | * @param uValue The value to set.
|
---|
| 1108 | *
|
---|
| 1109 | * @remarks Everyone changing MSR values, including the recompiler, shall do it
|
---|
[41836] | 1110 | * by calling this method. This makes sure we have current values and
|
---|
[30861] | 1111 | * that we trigger all the right actions when something changes.
|
---|
| 1112 | */
|
---|
| 1113 | VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
|
---|
[14411] | 1114 | {
|
---|
[30861] | 1115 | /*
|
---|
| 1116 | * If we don't indicate MSR support in the CPUID feature bits, indicate
|
---|
| 1117 | * that a #GP(0) should be raised.
|
---|
| 1118 | */
|
---|
| 1119 | if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
|
---|
[40170] | 1120 | return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
|
---|
[30861] | 1121 |
|
---|
| 1122 | int rc = VINF_SUCCESS;
|
---|
[14411] | 1123 | switch (idMsr)
|
---|
| 1124 | {
|
---|
[30861] | 1125 | case MSR_IA32_MISC_ENABLE:
|
---|
[40170] | 1126 | pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
|
---|
[14411] | 1127 | break;
|
---|
| 1128 |
|
---|
[30861] | 1129 | case MSR_IA32_TSC:
|
---|
| 1130 | TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
|
---|
[27331] | 1131 | break;
|
---|
| 1132 |
|
---|
[30861] | 1133 | case MSR_IA32_APICBASE:
|
---|
[43657] | 1134 | rc = PDMApicSetBase(pVCpu, uValue);
|
---|
[30861] | 1135 | if (rc != VINF_SUCCESS)
|
---|
| 1136 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 1137 | break;
|
---|
| 1138 |
|
---|
| 1139 | case MSR_IA32_CR_PAT:
|
---|
| 1140 | pVCpu->cpum.s.Guest.msrPAT = uValue;
|
---|
| 1141 | break;
|
---|
| 1142 |
|
---|
| 1143 | case MSR_IA32_SYSENTER_CS:
|
---|
| 1144 | pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
|
---|
| 1145 | break;
|
---|
| 1146 |
|
---|
| 1147 | case MSR_IA32_SYSENTER_EIP:
|
---|
| 1148 | pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
|
---|
| 1149 | break;
|
---|
| 1150 |
|
---|
| 1151 | case MSR_IA32_SYSENTER_ESP:
|
---|
| 1152 | pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
|
---|
| 1153 | break;
|
---|
| 1154 |
|
---|
[40170] | 1155 | case MSR_IA32_MTRR_CAP:
|
---|
| 1156 | return VERR_CPUM_RAISE_GP_0;
|
---|
| 1157 |
|
---|
| 1158 | case MSR_IA32_MTRR_DEF_TYPE:
|
---|
| 1159 | if ( (uValue & UINT64_C(0xfffffffffffff300))
|
---|
| 1160 | || ( (uValue & 0xff) != 0
|
---|
| 1161 | && (uValue & 0xff) != 1
|
---|
| 1162 | && (uValue & 0xff) != 4
|
---|
| 1163 | && (uValue & 0xff) != 5
|
---|
| 1164 | && (uValue & 0xff) != 6) )
|
---|
| 1165 | {
|
---|
| 1166 | Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
|
---|
| 1167 | return VERR_CPUM_RAISE_GP_0;
|
---|
| 1168 | }
|
---|
| 1169 | pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
|
---|
| 1170 | break;
|
---|
| 1171 |
|
---|
| 1172 | case IA32_MTRR_FIX64K_00000:
|
---|
| 1173 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
|
---|
| 1174 | break;
|
---|
| 1175 | case IA32_MTRR_FIX16K_80000:
|
---|
| 1176 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
|
---|
| 1177 | break;
|
---|
| 1178 | case IA32_MTRR_FIX16K_A0000:
|
---|
| 1179 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
|
---|
| 1180 | break;
|
---|
| 1181 | case IA32_MTRR_FIX4K_C0000:
|
---|
| 1182 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
|
---|
| 1183 | break;
|
---|
| 1184 | case IA32_MTRR_FIX4K_C8000:
|
---|
| 1185 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
|
---|
| 1186 | break;
|
---|
| 1187 | case IA32_MTRR_FIX4K_D0000:
|
---|
| 1188 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
|
---|
| 1189 | break;
|
---|
| 1190 | case IA32_MTRR_FIX4K_D8000:
|
---|
| 1191 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
|
---|
| 1192 | break;
|
---|
| 1193 | case IA32_MTRR_FIX4K_E0000:
|
---|
| 1194 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
|
---|
| 1195 | break;
|
---|
| 1196 | case IA32_MTRR_FIX4K_E8000:
|
---|
| 1197 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
|
---|
| 1198 | break;
|
---|
| 1199 | case IA32_MTRR_FIX4K_F0000:
|
---|
| 1200 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
|
---|
| 1201 | break;
|
---|
| 1202 | case IA32_MTRR_FIX4K_F8000:
|
---|
| 1203 | pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
|
---|
| 1204 | break;
|
---|
| 1205 |
|
---|
[42640] | 1206 | /*
|
---|
| 1207 | * AMD64 MSRs.
|
---|
| 1208 | */
|
---|
[30861] | 1209 | case MSR_K6_EFER:
|
---|
| 1210 | {
|
---|
| 1211 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
| 1212 | uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
|
---|
| 1213 | uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
| 1214 | ? pVM->cpum.s.aGuestCpuIdExt[1].edx
|
---|
| 1215 | : 0;
|
---|
| 1216 | uint64_t fMask = 0;
|
---|
| 1217 |
|
---|
| 1218 | /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
|
---|
[42024] | 1219 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
|
---|
[30861] | 1220 | fMask |= MSR_K6_EFER_NXE;
|
---|
[42024] | 1221 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
|
---|
[30861] | 1222 | fMask |= MSR_K6_EFER_LME;
|
---|
[42024] | 1223 | if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
|
---|
[30861] | 1224 | fMask |= MSR_K6_EFER_SCE;
|
---|
| 1225 | if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
|
---|
| 1226 | fMask |= MSR_K6_EFER_FFXSR;
|
---|
| 1227 |
|
---|
| 1228 | /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
|
---|
| 1229 | paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
|
---|
| 1230 | if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
|
---|
| 1231 | && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
|
---|
| 1232 | {
|
---|
| 1233 | Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
|
---|
| 1234 | return VERR_CPUM_RAISE_GP_0;
|
---|
| 1235 | }
|
---|
| 1236 |
|
---|
| 1237 | /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
|
---|
| 1238 | AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
|
---|
| 1239 | ("Unexpected value %RX64\n", uValue));
|
---|
| 1240 | pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
|
---|
| 1241 |
|
---|
| 1242 | /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
|
---|
| 1243 | if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
|
---|
[30889] | 1244 | if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
|
---|
[30861] | 1245 | != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
|
---|
| 1246 | {
|
---|
| 1247 | /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
|
---|
[43387] | 1248 | HMFlushTLB(pVCpu);
|
---|
[30861] | 1249 |
|
---|
| 1250 | /* Notify PGM about NXE changes. */
|
---|
[30889] | 1251 | if ( (uOldEFER & MSR_K6_EFER_NXE)
|
---|
[30861] | 1252 | != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
|
---|
[30889] | 1253 | PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
|
---|
[30861] | 1254 | }
|
---|
| 1255 | break;
|
---|
| 1256 | }
|
---|
| 1257 |
|
---|
| 1258 | case MSR_K8_SF_MASK:
|
---|
| 1259 | pVCpu->cpum.s.Guest.msrSFMASK = uValue;
|
---|
| 1260 | break;
|
---|
| 1261 |
|
---|
| 1262 | case MSR_K6_STAR:
|
---|
| 1263 | pVCpu->cpum.s.Guest.msrSTAR = uValue;
|
---|
| 1264 | break;
|
---|
| 1265 |
|
---|
| 1266 | case MSR_K8_LSTAR:
|
---|
| 1267 | pVCpu->cpum.s.Guest.msrLSTAR = uValue;
|
---|
| 1268 | break;
|
---|
| 1269 |
|
---|
| 1270 | case MSR_K8_CSTAR:
|
---|
| 1271 | pVCpu->cpum.s.Guest.msrCSTAR = uValue;
|
---|
| 1272 | break;
|
---|
| 1273 |
|
---|
| 1274 | case MSR_K8_FS_BASE:
|
---|
[41906] | 1275 | pVCpu->cpum.s.Guest.fs.u64Base = uValue;
|
---|
[30861] | 1276 | break;
|
---|
| 1277 |
|
---|
| 1278 | case MSR_K8_GS_BASE:
|
---|
[41906] | 1279 | pVCpu->cpum.s.Guest.gs.u64Base = uValue;
|
---|
[30861] | 1280 | break;
|
---|
| 1281 |
|
---|
| 1282 | case MSR_K8_KERNEL_GS_BASE:
|
---|
| 1283 | pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
|
---|
| 1284 | break;
|
---|
| 1285 |
|
---|
| 1286 | case MSR_K8_TSC_AUX:
|
---|
[40170] | 1287 | pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
|
---|
[30861] | 1288 | break;
|
---|
| 1289 |
|
---|
[42640] | 1290 | /*
|
---|
| 1291 | * Intel specifics MSRs:
|
---|
| 1292 | */
|
---|
[42647] | 1293 | /*case MSR_IA32_PLATFORM_ID: - read-only */
|
---|
[42640] | 1294 | case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
|
---|
| 1295 | case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
|
---|
[42647] | 1296 | /*case MSR_IA32_MCP_CAP: - read-only */
|
---|
| 1297 | /*case MSR_IA32_MCP_STATUS: - read-only */
|
---|
| 1298 | /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
|
---|
| 1299 | /*case MSR_IA32_MC0_CTL: - read-only? */
|
---|
| 1300 | /*case MSR_IA32_MC0_STATUS: - read-only? */
|
---|
[42640] | 1301 | if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
|
---|
| 1302 | {
|
---|
| 1303 | Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
|
---|
| 1304 | return VERR_CPUM_RAISE_GP_0;
|
---|
| 1305 | }
|
---|
| 1306 | /* ignored */
|
---|
| 1307 | break;
|
---|
| 1308 |
|
---|
[14411] | 1309 | default:
|
---|
[42640] | 1310 | /*
|
---|
| 1311 | * Hand the X2APIC range to PDM and the APIC.
|
---|
| 1312 | */
|
---|
[30861] | 1313 | if ( idMsr >= MSR_IA32_APIC_START
|
---|
| 1314 | && idMsr < MSR_IA32_APIC_END)
|
---|
| 1315 | {
|
---|
| 1316 | rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
|
---|
| 1317 | if (rc != VINF_SUCCESS)
|
---|
| 1318 | rc = VERR_CPUM_RAISE_GP_0;
|
---|
| 1319 | }
|
---|
| 1320 | else
|
---|
| 1321 | {
|
---|
| 1322 | /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
|
---|
| 1323 | /** @todo rc = VERR_CPUM_RAISE_GP_0 */
|
---|
| 1324 | Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
|
---|
| 1325 | }
|
---|
[14411] | 1326 | break;
|
---|
| 1327 | }
|
---|
[30861] | 1328 | return rc;
|
---|
[14411] | 1329 | }
|
---|
| 1330 |
|
---|
[30861] | 1331 |
|
---|
[18927] | 1332 | VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
|
---|
[1] | 1333 | {
|
---|
| 1334 | if (pcbLimit)
|
---|
[18927] | 1335 | *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
|
---|
| 1336 | return pVCpu->cpum.s.Guest.idtr.pIdt;
|
---|
[1] | 1337 | }
|
---|
| 1338 |
|
---|
[12657] | 1339 |
|
---|
[18927] | 1340 | VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
|
---|
[1] | 1341 | {
|
---|
[17035] | 1342 | if (pHidden)
|
---|
[41906] | 1343 | *pHidden = pVCpu->cpum.s.Guest.tr;
|
---|
| 1344 | return pVCpu->cpum.s.Guest.tr.Sel;
|
---|
[1] | 1345 | }
|
---|
| 1346 |
|
---|
[12657] | 1347 |
|
---|
[18927] | 1348 | VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
|
---|
[1] | 1349 | {
|
---|
[41906] | 1350 | return pVCpu->cpum.s.Guest.cs.Sel;
|
---|
[1] | 1351 | }
|
---|
| 1352 |
|
---|
[12657] | 1353 |
|
---|
[18927] | 1354 | VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
|
---|
[1] | 1355 | {
|
---|
[41906] | 1356 | return pVCpu->cpum.s.Guest.ds.Sel;
|
---|
[1] | 1357 | }
|
---|
| 1358 |
|
---|
[12657] | 1359 |
|
---|
[18927] | 1360 | VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
|
---|
[1] | 1361 | {
|
---|
[41906] | 1362 | return pVCpu->cpum.s.Guest.es.Sel;
|
---|
[1] | 1363 | }
|
---|
| 1364 |
|
---|
[12657] | 1365 |
|
---|
[18927] | 1366 | VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
|
---|
[1] | 1367 | {
|
---|
[41906] | 1368 | return pVCpu->cpum.s.Guest.fs.Sel;
|
---|
[1] | 1369 | }
|
---|
| 1370 |
|
---|
[12657] | 1371 |
|
---|
[18927] | 1372 | VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
|
---|
[1] | 1373 | {
|
---|
[41906] | 1374 | return pVCpu->cpum.s.Guest.gs.Sel;
|
---|
[1] | 1375 | }
|
---|
| 1376 |
|
---|
[12657] | 1377 |
|
---|
[18927] | 1378 | VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
|
---|
[1] | 1379 | {
|
---|
[41906] | 1380 | return pVCpu->cpum.s.Guest.ss.Sel;
|
---|
[1] | 1381 | }
|
---|
| 1382 |
|
---|
[12657] | 1383 |
|
---|
[18927] | 1384 | VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
|
---|
[1] | 1385 | {
|
---|
[41906] | 1386 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
[1] | 1387 | }
|
---|
| 1388 |
|
---|
[12657] | 1389 |
|
---|
[42427] | 1390 | VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
|
---|
| 1391 | {
|
---|
| 1392 | *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
|
---|
| 1393 | *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
|
---|
| 1394 | return pVCpu->cpum.s.Guest.ldtr.Sel;
|
---|
| 1395 | }
|
---|
| 1396 |
|
---|
| 1397 |
|
---|
[18927] | 1398 | VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
|
---|
[1] | 1399 | {
|
---|
[18927] | 1400 | return pVCpu->cpum.s.Guest.cr0;
|
---|
[1] | 1401 | }
|
---|
| 1402 |
|
---|
[12657] | 1403 |
|
---|
[18927] | 1404 | VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
|
---|
[1] | 1405 | {
|
---|
[18927] | 1406 | return pVCpu->cpum.s.Guest.cr2;
|
---|
[1] | 1407 | }
|
---|
| 1408 |
|
---|
[12657] | 1409 |
|
---|
[18927] | 1410 | VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
|
---|
[1] | 1411 | {
|
---|
[18927] | 1412 | return pVCpu->cpum.s.Guest.cr3;
|
---|
[1] | 1413 | }
|
---|
| 1414 |
|
---|
[12657] | 1415 |
|
---|
[18927] | 1416 | VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
|
---|
[1] | 1417 | {
|
---|
[18927] | 1418 | return pVCpu->cpum.s.Guest.cr4;
|
---|
[1] | 1419 | }
|
---|
| 1420 |
|
---|
[12657] | 1421 |
|
---|
[31489] | 1422 | VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
|
---|
| 1423 | {
|
---|
| 1424 | uint64_t u64;
|
---|
[41728] | 1425 | int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
|
---|
[31489] | 1426 | if (RT_FAILURE(rc))
|
---|
| 1427 | u64 = 0;
|
---|
| 1428 | return u64;
|
---|
| 1429 | }
|
---|
| 1430 |
|
---|
| 1431 |
|
---|
[18927] | 1432 | VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
|
---|
[1] | 1433 | {
|
---|
[18927] | 1434 | *pGDTR = pVCpu->cpum.s.Guest.gdtr;
|
---|
[1] | 1435 | }
|
---|
| 1436 |
|
---|
[12657] | 1437 |
|
---|
[18927] | 1438 | VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
|
---|
[1] | 1439 | {
|
---|
[18927] | 1440 | return pVCpu->cpum.s.Guest.eip;
|
---|
[1] | 1441 | }
|
---|
| 1442 |
|
---|
[12657] | 1443 |
|
---|
[18927] | 1444 | VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
|
---|
[9841] | 1445 | {
|
---|
[18927] | 1446 | return pVCpu->cpum.s.Guest.rip;
|
---|
[9841] | 1447 | }
|
---|
| 1448 |
|
---|
[12657] | 1449 |
|
---|
[18927] | 1450 | VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
|
---|
[1] | 1451 | {
|
---|
[18927] | 1452 | return pVCpu->cpum.s.Guest.eax;
|
---|
[1] | 1453 | }
|
---|
| 1454 |
|
---|
[12657] | 1455 |
|
---|
[18927] | 1456 | VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
|
---|
[1] | 1457 | {
|
---|
[18927] | 1458 | return pVCpu->cpum.s.Guest.ebx;
|
---|
[1] | 1459 | }
|
---|
| 1460 |
|
---|
[12657] | 1461 |
|
---|
[18927] | 1462 | VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
|
---|
[1] | 1463 | {
|
---|
[18927] | 1464 | return pVCpu->cpum.s.Guest.ecx;
|
---|
[1] | 1465 | }
|
---|
| 1466 |
|
---|
[12657] | 1467 |
|
---|
[18927] | 1468 | VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
|
---|
[1] | 1469 | {
|
---|
[18927] | 1470 | return pVCpu->cpum.s.Guest.edx;
|
---|
[1] | 1471 | }
|
---|
| 1472 |
|
---|
[12657] | 1473 |
|
---|
[18927] | 1474 | VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
|
---|
[1] | 1475 | {
|
---|
[18927] | 1476 | return pVCpu->cpum.s.Guest.esi;
|
---|
[1] | 1477 | }
|
---|
| 1478 |
|
---|
[12657] | 1479 |
|
---|
[18927] | 1480 | VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
|
---|
[1] | 1481 | {
|
---|
[18927] | 1482 | return pVCpu->cpum.s.Guest.edi;
|
---|
[1] | 1483 | }
|
---|
| 1484 |
|
---|
[12657] | 1485 |
|
---|
[18927] | 1486 | VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
|
---|
[1] | 1487 | {
|
---|
[18927] | 1488 | return pVCpu->cpum.s.Guest.esp;
|
---|
[1] | 1489 | }
|
---|
| 1490 |
|
---|
[12657] | 1491 |
|
---|
[18927] | 1492 | VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
|
---|
[1] | 1493 | {
|
---|
[18927] | 1494 | return pVCpu->cpum.s.Guest.ebp;
|
---|
[1] | 1495 | }
|
---|
| 1496 |
|
---|
[12657] | 1497 |
|
---|
[18927] | 1498 | VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
|
---|
[1] | 1499 | {
|
---|
[18927] | 1500 | return pVCpu->cpum.s.Guest.eflags.u32;
|
---|
[1] | 1501 | }
|
---|
| 1502 |
|
---|
[12657] | 1503 |
|
---|
[18927] | 1504 | VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
|
---|
[1] | 1505 | {
|
---|
| 1506 | switch (iReg)
|
---|
| 1507 | {
|
---|
[41728] | 1508 | case DISCREG_CR0:
|
---|
[18927] | 1509 | *pValue = pVCpu->cpum.s.Guest.cr0;
|
---|
[1] | 1510 | break;
|
---|
[31489] | 1511 |
|
---|
[41728] | 1512 | case DISCREG_CR2:
|
---|
[18927] | 1513 | *pValue = pVCpu->cpum.s.Guest.cr2;
|
---|
[1] | 1514 | break;
|
---|
[31489] | 1515 |
|
---|
[41728] | 1516 | case DISCREG_CR3:
|
---|
[18927] | 1517 | *pValue = pVCpu->cpum.s.Guest.cr3;
|
---|
[1] | 1518 | break;
|
---|
[31489] | 1519 |
|
---|
[41728] | 1520 | case DISCREG_CR4:
|
---|
[18927] | 1521 | *pValue = pVCpu->cpum.s.Guest.cr4;
|
---|
[1] | 1522 | break;
|
---|
[31489] | 1523 |
|
---|
[41728] | 1524 | case DISCREG_CR8:
|
---|
[31489] | 1525 | {
|
---|
| 1526 | uint8_t u8Tpr;
|
---|
| 1527 | int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
|
---|
| 1528 | if (RT_FAILURE(rc))
|
---|
| 1529 | {
|
---|
| 1530 | AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
|
---|
| 1531 | *pValue = 0;
|
---|
| 1532 | return rc;
|
---|
| 1533 | }
|
---|
| 1534 | *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
|
---|
| 1535 | break;
|
---|
| 1536 | }
|
---|
| 1537 |
|
---|
[1] | 1538 | default:
|
---|
| 1539 | return VERR_INVALID_PARAMETER;
|
---|
| 1540 | }
|
---|
| 1541 | return VINF_SUCCESS;
|
---|
| 1542 | }
|
---|
| 1543 |
|
---|
[12657] | 1544 |
|
---|
[18927] | 1545 | VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
|
---|
[1] | 1546 | {
|
---|
[18927] | 1547 | return pVCpu->cpum.s.Guest.dr[0];
|
---|
[1] | 1548 | }
|
---|
| 1549 |
|
---|
[12657] | 1550 |
|
---|
[18927] | 1551 | VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
|
---|
[1] | 1552 | {
|
---|
[18927] | 1553 | return pVCpu->cpum.s.Guest.dr[1];
|
---|
[1] | 1554 | }
|
---|
| 1555 |
|
---|
[12657] | 1556 |
|
---|
[18927] | 1557 | VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
|
---|
[1] | 1558 | {
|
---|
[18927] | 1559 | return pVCpu->cpum.s.Guest.dr[2];
|
---|
[1] | 1560 | }
|
---|
| 1561 |
|
---|
[12657] | 1562 |
|
---|
[18927] | 1563 | VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
|
---|
[1] | 1564 | {
|
---|
[18927] | 1565 | return pVCpu->cpum.s.Guest.dr[3];
|
---|
[1] | 1566 | }
|
---|
| 1567 |
|
---|
[12657] | 1568 |
|
---|
[18927] | 1569 | VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
|
---|
[1] | 1570 | {
|
---|
[18927] | 1571 | return pVCpu->cpum.s.Guest.dr[6];
|
---|
[1] | 1572 | }
|
---|
| 1573 |
|
---|
[12657] | 1574 |
|
---|
[18927] | 1575 | VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
|
---|
[1] | 1576 | {
|
---|
[18927] | 1577 | return pVCpu->cpum.s.Guest.dr[7];
|
---|
[1] | 1578 | }
|
---|
| 1579 |
|
---|
[12657] | 1580 |
|
---|
[18927] | 1581 | VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
|
---|
[1] | 1582 | {
|
---|
[41728] | 1583 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
[12657] | 1584 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
| 1585 | if (iReg == 4 || iReg == 5)
|
---|
| 1586 | iReg += 2;
|
---|
[18927] | 1587 | *pValue = pVCpu->cpum.s.Guest.dr[iReg];
|
---|
[1] | 1588 | return VINF_SUCCESS;
|
---|
| 1589 | }
|
---|
| 1590 |
|
---|
[12657] | 1591 |
|
---|
[18927] | 1592 | VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
|
---|
[7730] | 1593 | {
|
---|
[18927] | 1594 | return pVCpu->cpum.s.Guest.msrEFER;
|
---|
[7730] | 1595 | }
|
---|
| 1596 |
|
---|
[12657] | 1597 |
|
---|
[1] | 1598 | /**
|
---|
[42034] | 1599 | * Gets a CPUID leaf.
|
---|
[1] | 1600 | *
|
---|
[41802] | 1601 | * @param pVCpu Pointer to the VMCPU.
|
---|
[1] | 1602 | * @param iLeaf The CPUID leaf to get.
|
---|
| 1603 | * @param pEax Where to store the EAX value.
|
---|
| 1604 | * @param pEbx Where to store the EBX value.
|
---|
| 1605 | * @param pEcx Where to store the ECX value.
|
---|
| 1606 | * @param pEdx Where to store the EDX value.
|
---|
| 1607 | */
|
---|
[19076] | 1608 | VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
|
---|
[1] | 1609 | {
|
---|
[19076] | 1610 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
| 1611 |
|
---|
[1] | 1612 | PCCPUMCPUID pCpuId;
|
---|
[11311] | 1613 | if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
|
---|
[1] | 1614 | pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
|
---|
[5285] | 1615 | else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
|
---|
[1] | 1616 | pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
|
---|
[40235] | 1617 | else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
|
---|
| 1618 | && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
|
---|
| 1619 | pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
|
---|
[5285] | 1620 | else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
|
---|
| 1621 | pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
|
---|
[1] | 1622 | else
|
---|
| 1623 | pCpuId = &pVM->cpum.s.GuestCpuIdDef;
|
---|
| 1624 |
|
---|
[25803] | 1625 | uint32_t cCurrentCacheIndex = *pEcx;
|
---|
[22037] | 1626 |
|
---|
[1] | 1627 | *pEax = pCpuId->eax;
|
---|
| 1628 | *pEbx = pCpuId->ebx;
|
---|
| 1629 | *pEcx = pCpuId->ecx;
|
---|
| 1630 | *pEdx = pCpuId->edx;
|
---|
[19076] | 1631 |
|
---|
[26648] | 1632 | if ( iLeaf == 1)
|
---|
[19076] | 1633 | {
|
---|
| 1634 | /* Bits 31-24: Initial APIC ID */
|
---|
| 1635 | Assert(pVCpu->idCpu <= 255);
|
---|
| 1636 | *pEbx |= (pVCpu->idCpu << 24);
|
---|
[22037] | 1637 | }
|
---|
| 1638 |
|
---|
[22070] | 1639 | if ( iLeaf == 4
|
---|
[25803] | 1640 | && cCurrentCacheIndex < 3
|
---|
[23794] | 1641 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
|
---|
[22037] | 1642 | {
|
---|
[25803] | 1643 | uint32_t type, level, sharing, linesize,
|
---|
| 1644 | partitions, associativity, sets, cores;
|
---|
| 1645 |
|
---|
| 1646 | /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
|
---|
| 1647 | partitions = 1;
|
---|
[25815] | 1648 | /* Those are only to shut up compiler, as they will always
|
---|
[25803] | 1649 | get overwritten, and compiler should be able to figure that out */
|
---|
| 1650 | sets = associativity = sharing = level = 1;
|
---|
| 1651 | cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
|
---|
| 1652 | switch (cCurrentCacheIndex)
|
---|
| 1653 | {
|
---|
| 1654 | case 0:
|
---|
| 1655 | type = 1;
|
---|
| 1656 | level = 1;
|
---|
| 1657 | sharing = 1;
|
---|
| 1658 | linesize = 64;
|
---|
| 1659 | associativity = 8;
|
---|
| 1660 | sets = 64;
|
---|
| 1661 | break;
|
---|
| 1662 | case 1:
|
---|
| 1663 | level = 1;
|
---|
| 1664 | type = 2;
|
---|
| 1665 | sharing = 1;
|
---|
| 1666 | linesize = 64;
|
---|
| 1667 | associativity = 8;
|
---|
| 1668 | sets = 64;
|
---|
| 1669 | break;
|
---|
[26026] | 1670 | default: /* shut up gcc.*/
|
---|
| 1671 | AssertFailed();
|
---|
[25803] | 1672 | case 2:
|
---|
| 1673 | level = 2;
|
---|
| 1674 | type = 3;
|
---|
[26673] | 1675 | sharing = cores; /* our L2 cache is modelled as shared between all cores */
|
---|
[25803] | 1676 | linesize = 64;
|
---|
| 1677 | associativity = 24;
|
---|
| 1678 | sets = 4096;
|
---|
| 1679 | break;
|
---|
| 1680 | }
|
---|
| 1681 |
|
---|
| 1682 | *pEax |= ((cores - 1) << 26) |
|
---|
| 1683 | ((sharing - 1) << 14) |
|
---|
| 1684 | (level << 5) |
|
---|
| 1685 | 1;
|
---|
| 1686 | *pEbx = (linesize - 1) |
|
---|
| 1687 | ((partitions - 1) << 12) |
|
---|
| 1688 | ((associativity - 1) << 22); /* -1 encoding */
|
---|
| 1689 | *pEcx = sets - 1;
|
---|
[19076] | 1690 | }
|
---|
| 1691 |
|
---|
[1] | 1692 | Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
|
---|
| 1693 | }
|
---|
| 1694 |
|
---|
| 1695 | /**
|
---|
| 1696 | * Gets a number of standard CPUID leafs.
|
---|
| 1697 | *
|
---|
| 1698 | * @returns Number of leafs.
|
---|
[41783] | 1699 | * @param pVM Pointer to the VM.
|
---|
[1] | 1700 | * @remark Intended for PATM.
|
---|
| 1701 | */
|
---|
[12989] | 1702 | VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
|
---|
[1] | 1703 | {
|
---|
[5285] | 1704 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
|
---|
[1] | 1705 | }
|
---|
| 1706 |
|
---|
[12657] | 1707 |
|
---|
[1] | 1708 | /**
|
---|
| 1709 | * Gets a number of extended CPUID leafs.
|
---|
| 1710 | *
|
---|
| 1711 | * @returns Number of leafs.
|
---|
[41783] | 1712 | * @param pVM Pointer to the VM.
|
---|
[1] | 1713 | * @remark Intended for PATM.
|
---|
| 1714 | */
|
---|
[12989] | 1715 | VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
|
---|
[1] | 1716 | {
|
---|
[5285] | 1717 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
|
---|
[1] | 1718 | }
|
---|
| 1719 |
|
---|
[12657] | 1720 |
|
---|
[1] | 1721 | /**
|
---|
[5285] | 1722 | * Gets a number of centaur CPUID leafs.
|
---|
| 1723 | *
|
---|
| 1724 | * @returns Number of leafs.
|
---|
[41783] | 1725 | * @param pVM Pointer to the VM.
|
---|
[5285] | 1726 | * @remark Intended for PATM.
|
---|
| 1727 | */
|
---|
[12989] | 1728 | VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
|
---|
[5285] | 1729 | {
|
---|
| 1730 | return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
|
---|
| 1731 | }
|
---|
| 1732 |
|
---|
[12657] | 1733 |
|
---|
[5285] | 1734 | /**
|
---|
[1] | 1735 | * Sets a CPUID feature bit.
|
---|
| 1736 | *
|
---|
[41783] | 1737 | * @param pVM Pointer to the VM.
|
---|
[1] | 1738 | * @param enmFeature The feature to set.
|
---|
| 1739 | */
|
---|
[12989] | 1740 | VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
[1] | 1741 | {
|
---|
| 1742 | switch (enmFeature)
|
---|
| 1743 | {
|
---|
| 1744 | /*
|
---|
| 1745 | * Set the APIC bit in both feature masks.
|
---|
| 1746 | */
|
---|
| 1747 | case CPUMCPUIDFEATURE_APIC:
|
---|
[2633] | 1748 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
[1] | 1749 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
|
---|
| 1750 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 1751 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[1] | 1752 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
|
---|
[9354] | 1753 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
|
---|
[1] | 1754 | break;
|
---|
| 1755 |
|
---|
[12971] | 1756 | /*
|
---|
| 1757 | * Set the x2APIC bit in the standard feature mask.
|
---|
[12972] | 1758 | */
|
---|
[12971] | 1759 | case CPUMCPUIDFEATURE_X2APIC:
|
---|
| 1760 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1761 | pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
|
---|
| 1762 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
|
---|
| 1763 | break;
|
---|
| 1764 |
|
---|
[771] | 1765 | /*
|
---|
[9354] | 1766 | * Set the sysenter/sysexit bit in the standard feature mask.
|
---|
[771] | 1767 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
| 1768 | */
|
---|
| 1769 | case CPUMCPUIDFEATURE_SEP:
|
---|
| 1770 | {
|
---|
[7650] | 1771 | if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
|
---|
[771] | 1772 | {
|
---|
| 1773 | AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
|
---|
| 1774 | return;
|
---|
| 1775 | }
|
---|
| 1776 |
|
---|
| 1777 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1778 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
|
---|
[9354] | 1779 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
|
---|
[771] | 1780 | break;
|
---|
| 1781 | }
|
---|
| 1782 |
|
---|
[7644] | 1783 | /*
|
---|
[9354] | 1784 | * Set the syscall/sysret bit in the extended feature mask.
|
---|
| 1785 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
| 1786 | */
|
---|
| 1787 | case CPUMCPUIDFEATURE_SYSCALL:
|
---|
| 1788 | {
|
---|
| 1789 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1790 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
|
---|
[9354] | 1791 | {
|
---|
[15390] | 1792 | #if HC_ARCH_BITS == 32
|
---|
[42024] | 1793 | /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
|
---|
[15390] | 1794 | * Even when the cpu is capable of doing so in 64 bits mode.
|
---|
| 1795 | */
|
---|
| 1796 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1797 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
|
---|
| 1798 | || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
|
---|
[15390] | 1799 | #endif
|
---|
| 1800 | {
|
---|
| 1801 | LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
|
---|
| 1802 | return;
|
---|
| 1803 | }
|
---|
[9354] | 1804 | }
|
---|
| 1805 | /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
|
---|
[42024] | 1806 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
|
---|
[9825] | 1807 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
|
---|
[9354] | 1808 | break;
|
---|
| 1809 | }
|
---|
| 1810 |
|
---|
| 1811 | /*
|
---|
[7644] | 1812 | * Set the PAE bit in both feature masks.
|
---|
| 1813 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
| 1814 | */
|
---|
| 1815 | case CPUMCPUIDFEATURE_PAE:
|
---|
| 1816 | {
|
---|
[7647] | 1817 | if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
|
---|
[7644] | 1818 | {
|
---|
[8106] | 1819 | LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
|
---|
[7644] | 1820 | return;
|
---|
| 1821 | }
|
---|
| 1822 |
|
---|
| 1823 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1824 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
|
---|
| 1825 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 1826 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[7644] | 1827 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
|
---|
[9354] | 1828 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
|
---|
[7644] | 1829 | break;
|
---|
| 1830 | }
|
---|
| 1831 |
|
---|
[7645] | 1832 | /*
|
---|
| 1833 | * Set the LONG MODE bit in the extended feature mask.
|
---|
| 1834 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
| 1835 | */
|
---|
| 1836 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
| 1837 | {
|
---|
[7646] | 1838 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1839 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
|
---|
[7645] | 1840 | {
|
---|
[9354] | 1841 | LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
|
---|
[7645] | 1842 | return;
|
---|
| 1843 | }
|
---|
| 1844 |
|
---|
[9354] | 1845 | /* Valid for both Intel and AMD. */
|
---|
[42024] | 1846 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
|
---|
[9354] | 1847 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
|
---|
[7645] | 1848 | break;
|
---|
| 1849 | }
|
---|
| 1850 |
|
---|
[9354] | 1851 | /*
|
---|
[42024] | 1852 | * Set the NX/XD bit in the extended feature mask.
|
---|
[9354] | 1853 | * Assumes the caller knows what it's doing! (host must support these)
|
---|
| 1854 | */
|
---|
[42024] | 1855 | case CPUMCPUIDFEATURE_NX:
|
---|
[9354] | 1856 | {
|
---|
| 1857 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1858 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
|
---|
[9354] | 1859 | {
|
---|
[42024] | 1860 | LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
|
---|
[9354] | 1861 | return;
|
---|
| 1862 | }
|
---|
| 1863 |
|
---|
| 1864 | /* Valid for both Intel and AMD. */
|
---|
[42024] | 1865 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
|
---|
| 1866 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
|
---|
[9354] | 1867 | break;
|
---|
| 1868 | }
|
---|
| 1869 |
|
---|
[42024] | 1870 | /*
|
---|
| 1871 | * Set the LAHF/SAHF support in 64-bit mode.
|
---|
| 1872 | * Assumes the caller knows what it's doing! (host must support this)
|
---|
| 1873 | */
|
---|
[9354] | 1874 | case CPUMCPUIDFEATURE_LAHF:
|
---|
| 1875 | {
|
---|
| 1876 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1877 | || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
|
---|
[9354] | 1878 | {
|
---|
| 1879 | LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
|
---|
| 1880 | return;
|
---|
| 1881 | }
|
---|
| 1882 |
|
---|
[42024] | 1883 | /* Valid for both Intel and AMD. */
|
---|
| 1884 | pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
|
---|
[9354] | 1885 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
|
---|
| 1886 | break;
|
---|
| 1887 | }
|
---|
| 1888 |
|
---|
[11704] | 1889 | case CPUMCPUIDFEATURE_PAT:
|
---|
| 1890 | {
|
---|
| 1891 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1892 | pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
|
---|
| 1893 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 1894 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[11704] | 1895 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
|
---|
[43151] | 1896 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
|
---|
[11704] | 1897 | break;
|
---|
| 1898 | }
|
---|
| 1899 |
|
---|
[42024] | 1900 | /*
|
---|
| 1901 | * Set the RDTSCP support bit.
|
---|
| 1902 | * Assumes the caller knows what it's doing! (host must support this)
|
---|
| 1903 | */
|
---|
[14411] | 1904 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
| 1905 | {
|
---|
| 1906 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
|
---|
[42024] | 1907 | || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
|
---|
[30164] | 1908 | || pVM->cpum.s.u8PortableCpuIdLevel > 0)
|
---|
[14411] | 1909 | {
|
---|
[30164] | 1910 | if (!pVM->cpum.s.u8PortableCpuIdLevel)
|
---|
| 1911 | LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
|
---|
[14411] | 1912 | return;
|
---|
| 1913 | }
|
---|
| 1914 |
|
---|
[42024] | 1915 | /* Valid for both Intel and AMD. */
|
---|
| 1916 | pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
|
---|
[14411] | 1917 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
|
---|
| 1918 | break;
|
---|
| 1919 | }
|
---|
| 1920 |
|
---|
[37136] | 1921 | /*
|
---|
| 1922 | * Set the Hypervisor Present bit in the standard feature mask.
|
---|
| 1923 | */
|
---|
| 1924 | case CPUMCPUIDFEATURE_HVP:
|
---|
| 1925 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1926 | pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
|
---|
| 1927 | LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
|
---|
| 1928 | break;
|
---|
| 1929 |
|
---|
[1] | 1930 | default:
|
---|
| 1931 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
| 1932 | break;
|
---|
| 1933 | }
|
---|
[22890] | 1934 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
[18927] | 1935 | {
|
---|
| 1936 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
| 1937 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
|
---|
| 1938 | }
|
---|
[1] | 1939 | }
|
---|
| 1940 |
|
---|
[12657] | 1941 |
|
---|
[1] | 1942 | /**
|
---|
[8111] | 1943 | * Queries a CPUID feature bit.
|
---|
| 1944 | *
|
---|
| 1945 | * @returns boolean for feature presence
|
---|
[41783] | 1946 | * @param pVM Pointer to the VM.
|
---|
[8111] | 1947 | * @param enmFeature The feature to query.
|
---|
| 1948 | */
|
---|
[12989] | 1949 | VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
[8111] | 1950 | {
|
---|
| 1951 | switch (enmFeature)
|
---|
| 1952 | {
|
---|
| 1953 | case CPUMCPUIDFEATURE_PAE:
|
---|
| 1954 | {
|
---|
| 1955 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 1956 | return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
|
---|
| 1957 | break;
|
---|
| 1958 | }
|
---|
| 1959 |
|
---|
[42024] | 1960 | case CPUMCPUIDFEATURE_NX:
|
---|
[30145] | 1961 | {
|
---|
| 1962 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
[42024] | 1963 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
|
---|
[30145] | 1964 | }
|
---|
| 1965 |
|
---|
[14411] | 1966 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
| 1967 | {
|
---|
| 1968 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
[42024] | 1969 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
|
---|
[14411] | 1970 | break;
|
---|
| 1971 | }
|
---|
| 1972 |
|
---|
[14704] | 1973 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
| 1974 | {
|
---|
| 1975 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
[42024] | 1976 | return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
|
---|
[14704] | 1977 | break;
|
---|
| 1978 | }
|
---|
[15416] | 1979 |
|
---|
[8111] | 1980 | default:
|
---|
| 1981 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
| 1982 | break;
|
---|
| 1983 | }
|
---|
| 1984 | return false;
|
---|
| 1985 | }
|
---|
| 1986 |
|
---|
[12657] | 1987 |
|
---|
[8111] | 1988 | /**
|
---|
[1] | 1989 | * Clears a CPUID feature bit.
|
---|
| 1990 | *
|
---|
[41783] | 1991 | * @param pVM Pointer to the VM.
|
---|
[1] | 1992 | * @param enmFeature The feature to clear.
|
---|
| 1993 | */
|
---|
[12989] | 1994 | VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
|
---|
[1] | 1995 | {
|
---|
| 1996 | switch (enmFeature)
|
---|
| 1997 | {
|
---|
| 1998 | /*
|
---|
| 1999 | * Set the APIC bit in both feature masks.
|
---|
| 2000 | */
|
---|
| 2001 | case CPUMCPUIDFEATURE_APIC:
|
---|
| 2002 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 2003 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
|
---|
[9354] | 2004 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 2005 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[1] | 2006 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
|
---|
[43151] | 2007 | Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
|
---|
[1] | 2008 | break;
|
---|
| 2009 |
|
---|
[12972] | 2010 | /*
|
---|
| 2011 | * Clear the x2APIC bit in the standard feature mask.
|
---|
| 2012 | */
|
---|
| 2013 | case CPUMCPUIDFEATURE_X2APIC:
|
---|
| 2014 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 2015 | pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
|
---|
[43151] | 2016 | LogRel(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
|
---|
[12972] | 2017 | break;
|
---|
| 2018 |
|
---|
[8110] | 2019 | case CPUMCPUIDFEATURE_PAE:
|
---|
| 2020 | {
|
---|
| 2021 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 2022 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
|
---|
| 2023 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 2024 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[8110] | 2025 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
|
---|
| 2026 | LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
|
---|
| 2027 | break;
|
---|
| 2028 | }
|
---|
| 2029 |
|
---|
[11704] | 2030 | case CPUMCPUIDFEATURE_PAT:
|
---|
| 2031 | {
|
---|
| 2032 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 2033 | pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
|
---|
| 2034 | if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
|
---|
[23794] | 2035 | && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
|
---|
[11704] | 2036 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
|
---|
| 2037 | LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
|
---|
| 2038 | break;
|
---|
| 2039 | }
|
---|
| 2040 |
|
---|
[14704] | 2041 | case CPUMCPUIDFEATURE_LONG_MODE:
|
---|
| 2042 | {
|
---|
| 2043 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
[42024] | 2044 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
|
---|
[14704] | 2045 | break;
|
---|
| 2046 | }
|
---|
| 2047 |
|
---|
| 2048 | case CPUMCPUIDFEATURE_LAHF:
|
---|
| 2049 | {
|
---|
| 2050 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
[42024] | 2051 | pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
|
---|
[14704] | 2052 | break;
|
---|
| 2053 | }
|
---|
| 2054 |
|
---|
[42033] | 2055 | case CPUMCPUIDFEATURE_RDTSCP:
|
---|
| 2056 | {
|
---|
| 2057 | if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
|
---|
| 2058 | pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
|
---|
| 2059 | LogRel(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
|
---|
| 2060 | break;
|
---|
| 2061 | }
|
---|
| 2062 |
|
---|
[37136] | 2063 | case CPUMCPUIDFEATURE_HVP:
|
---|
[40234] | 2064 | if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
|
---|
| 2065 | pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
|
---|
[37136] | 2066 | break;
|
---|
| 2067 |
|
---|
[1] | 2068 | default:
|
---|
| 2069 | AssertMsgFailed(("enmFeature=%d\n", enmFeature));
|
---|
| 2070 | break;
|
---|
| 2071 | }
|
---|
[22890] | 2072 | for (VMCPUID i = 0; i < pVM->cCpus; i++)
|
---|
[18927] | 2073 | {
|
---|
| 2074 | PVMCPU pVCpu = &pVM->aCpus[i];
|
---|
| 2075 | pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
|
---|
| 2076 | }
|
---|
[1] | 2077 | }
|
---|
| 2078 |
|
---|
[12657] | 2079 |
|
---|
[9354] | 2080 | /**
|
---|
[42034] | 2081 | * Gets the host CPU vendor.
|
---|
[23794] | 2082 | *
|
---|
[42034] | 2083 | * @returns CPU vendor.
|
---|
[41783] | 2084 | * @param pVM Pointer to the VM.
|
---|
[23794] | 2085 | */
|
---|
| 2086 | VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
|
---|
| 2087 | {
|
---|
| 2088 | return pVM->cpum.s.enmHostCpuVendor;
|
---|
| 2089 | }
|
---|
| 2090 |
|
---|
[42034] | 2091 |
|
---|
[23794] | 2092 | /**
|
---|
[42034] | 2093 | * Gets the CPU vendor.
|
---|
[9354] | 2094 | *
|
---|
[42034] | 2095 | * @returns CPU vendor.
|
---|
[41783] | 2096 | * @param pVM Pointer to the VM.
|
---|
[9354] | 2097 | */
|
---|
[23794] | 2098 | VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
|
---|
[9354] | 2099 | {
|
---|
[23794] | 2100 | return pVM->cpum.s.enmGuestCpuVendor;
|
---|
[9354] | 2101 | }
|
---|
[1] | 2102 |
|
---|
| 2103 |
|
---|
[18927] | 2104 | VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
|
---|
[1] | 2105 | {
|
---|
[18927] | 2106 | pVCpu->cpum.s.Guest.dr[0] = uDr0;
|
---|
| 2107 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2108 | }
|
---|
| 2109 |
|
---|
[12657] | 2110 |
|
---|
[18927] | 2111 | VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
|
---|
[1] | 2112 | {
|
---|
[18927] | 2113 | pVCpu->cpum.s.Guest.dr[1] = uDr1;
|
---|
| 2114 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2115 | }
|
---|
| 2116 |
|
---|
[12657] | 2117 |
|
---|
[18927] | 2118 | VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
|
---|
[1] | 2119 | {
|
---|
[18927] | 2120 | pVCpu->cpum.s.Guest.dr[2] = uDr2;
|
---|
| 2121 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2122 | }
|
---|
| 2123 |
|
---|
[12657] | 2124 |
|
---|
[18927] | 2125 | VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
|
---|
[1] | 2126 | {
|
---|
[18927] | 2127 | pVCpu->cpum.s.Guest.dr[3] = uDr3;
|
---|
| 2128 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2129 | }
|
---|
| 2130 |
|
---|
[12657] | 2131 |
|
---|
[18927] | 2132 | VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
|
---|
[1] | 2133 | {
|
---|
[18927] | 2134 | pVCpu->cpum.s.Guest.dr[6] = uDr6;
|
---|
| 2135 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2136 | }
|
---|
| 2137 |
|
---|
[12657] | 2138 |
|
---|
[18927] | 2139 | VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
|
---|
[1] | 2140 | {
|
---|
[18927] | 2141 | pVCpu->cpum.s.Guest.dr[7] = uDr7;
|
---|
| 2142 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2143 | }
|
---|
| 2144 |
|
---|
[12657] | 2145 |
|
---|
[18927] | 2146 | VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
|
---|
[1] | 2147 | {
|
---|
[41728] | 2148 | AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
|
---|
[12657] | 2149 | /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
|
---|
| 2150 | if (iReg == 4 || iReg == 5)
|
---|
| 2151 | iReg += 2;
|
---|
[18927] | 2152 | pVCpu->cpum.s.Guest.dr[iReg] = Value;
|
---|
| 2153 | return CPUMRecalcHyperDRx(pVCpu);
|
---|
[1] | 2154 | }
|
---|
| 2155 |
|
---|
| 2156 |
|
---|
| 2157 | /**
|
---|
[33540] | 2158 | * Recalculates the hypervisor DRx register values based on
|
---|
[1] | 2159 | * current guest registers and DBGF breakpoints.
|
---|
| 2160 | *
|
---|
| 2161 | * This is called whenever a guest DRx register is modified and when DBGF
|
---|
| 2162 | * sets a hardware breakpoint. In guest context this function will reload
|
---|
| 2163 | * any (hyper) DRx registers which comes out with a different value.
|
---|
| 2164 | *
|
---|
| 2165 | * @returns VINF_SUCCESS.
|
---|
[41802] | 2166 | * @param pVCpu Pointer to the VMCPU.
|
---|
[1] | 2167 | */
|
---|
[18927] | 2168 | VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
|
---|
[1] | 2169 | {
|
---|
[18927] | 2170 | PVM pVM = pVCpu->CTX_SUFF(pVM);
|
---|
| 2171 |
|
---|
[1] | 2172 | /*
|
---|
| 2173 | * Compare the DR7s first.
|
---|
| 2174 | *
|
---|
| 2175 | * We only care about the enabled flags. The GE and LE flags are always
|
---|
| 2176 | * set and we don't care if the guest doesn't set them. GD is virtualized
|
---|
| 2177 | * when we dispatch #DB, we never enable it.
|
---|
| 2178 | */
|
---|
| 2179 | const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
|
---|
| 2180 | #ifdef CPUM_VIRTUALIZE_DRX
|
---|
[18927] | 2181 | const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
|
---|
[1] | 2182 | #else
|
---|
| 2183 | const RTGCUINTREG uGstDr7 = 0;
|
---|
| 2184 | #endif
|
---|
| 2185 | if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
|
---|
| 2186 | {
|
---|
| 2187 | /*
|
---|
| 2188 | * Ok, something is enabled. Recalc each of the breakpoints.
|
---|
| 2189 | * Straight forward code, not optimized/minimized in any way.
|
---|
| 2190 | */
|
---|
| 2191 | RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
|
---|
| 2192 |
|
---|
| 2193 | /* bp 0 */
|
---|
| 2194 | RTGCUINTREG uNewDr0;
|
---|
| 2195 | if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
| 2196 | {
|
---|
| 2197 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
| 2198 | uNewDr0 = DBGFBpGetDR0(pVM);
|
---|
| 2199 | }
|
---|
| 2200 | else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
|
---|
| 2201 | {
|
---|
| 2202 | uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
|
---|
[18927] | 2203 | uNewDr0 = CPUMGetGuestDR0(pVCpu);
|
---|
[1] | 2204 | }
|
---|
| 2205 | else
|
---|
[18927] | 2206 | uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
|
---|
[1] | 2207 |
|
---|
| 2208 | /* bp 1 */
|
---|
| 2209 | RTGCUINTREG uNewDr1;
|
---|
| 2210 | if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
| 2211 | {
|
---|
| 2212 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
| 2213 | uNewDr1 = DBGFBpGetDR1(pVM);
|
---|
| 2214 | }
|
---|
| 2215 | else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
|
---|
| 2216 | {
|
---|
| 2217 | uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
|
---|
[18927] | 2218 | uNewDr1 = CPUMGetGuestDR1(pVCpu);
|
---|
[1] | 2219 | }
|
---|
| 2220 | else
|
---|
[18927] | 2221 | uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
|
---|
[1] | 2222 |
|
---|
| 2223 | /* bp 2 */
|
---|
| 2224 | RTGCUINTREG uNewDr2;
|
---|
| 2225 | if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
| 2226 | {
|
---|
| 2227 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
| 2228 | uNewDr2 = DBGFBpGetDR2(pVM);
|
---|
| 2229 | }
|
---|
| 2230 | else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
|
---|
| 2231 | {
|
---|
| 2232 | uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
|
---|
[18927] | 2233 | uNewDr2 = CPUMGetGuestDR2(pVCpu);
|
---|
[1] | 2234 | }
|
---|
| 2235 | else
|
---|
[18927] | 2236 | uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
|
---|
[1] | 2237 |
|
---|
| 2238 | /* bp 3 */
|
---|
| 2239 | RTGCUINTREG uNewDr3;
|
---|
| 2240 | if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
| 2241 | {
|
---|
| 2242 | uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
| 2243 | uNewDr3 = DBGFBpGetDR3(pVM);
|
---|
| 2244 | }
|
---|
| 2245 | else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
|
---|
| 2246 | {
|
---|
| 2247 | uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
|
---|
[18927] | 2248 | uNewDr3 = CPUMGetGuestDR3(pVCpu);
|
---|
[1] | 2249 | }
|
---|
| 2250 | else
|
---|
[18927] | 2251 | uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
|
---|
[1] | 2252 |
|
---|
| 2253 | /*
|
---|
| 2254 | * Apply the updates.
|
---|
| 2255 | */
|
---|
[13832] | 2256 | #ifdef IN_RC
|
---|
[18927] | 2257 | if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
|
---|
[1] | 2258 | {
|
---|
| 2259 | /** @todo save host DBx registers. */
|
---|
| 2260 | }
|
---|
| 2261 | #endif
|
---|
[43860] | 2262 | /** @todo Should this not be setting CPUM_USE_DEBUG_REGS_HYPER?
|
---|
| 2263 | * (CPUM_VIRTUALIZE_DRX is never defined). */
|
---|
[18927] | 2264 | pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
|
---|
| 2265 | if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
|
---|
| 2266 | CPUMSetHyperDR3(pVCpu, uNewDr3);
|
---|
| 2267 | if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
|
---|
| 2268 | CPUMSetHyperDR2(pVCpu, uNewDr2);
|
---|
| 2269 | if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
|
---|
| 2270 | CPUMSetHyperDR1(pVCpu, uNewDr1);
|
---|
| 2271 | if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
|
---|
| 2272 | CPUMSetHyperDR0(pVCpu, uNewDr0);
|
---|
| 2273 | if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
|
---|
| 2274 | CPUMSetHyperDR7(pVCpu, uNewDr7);
|
---|
[1] | 2275 | }
|
---|
| 2276 | else
|
---|
| 2277 | {
|
---|
[13832] | 2278 | #ifdef IN_RC
|
---|
[18927] | 2279 | if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
|
---|
[1] | 2280 | {
|
---|
| 2281 | /** @todo restore host DBx registers. */
|
---|
| 2282 | }
|
---|
| 2283 | #endif
|
---|
[18927] | 2284 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
|
---|
[1] | 2285 | }
|
---|
| 2286 | Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
|
---|
[18927] | 2287 | pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
|
---|
| 2288 | pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
|
---|
| 2289 | pVCpu->cpum.s.Hyper.dr[7]));
|
---|
[1] | 2290 |
|
---|
| 2291 | return VINF_SUCCESS;
|
---|
| 2292 | }
|
---|
| 2293 |
|
---|
[25835] | 2294 |
|
---|
| 2295 | /**
|
---|
| 2296 | * Tests if the guest has No-Execute Page Protection Enabled (NXE).
|
---|
| 2297 | *
|
---|
| 2298 | * @returns true if in real mode, otherwise false.
|
---|
[41803] | 2299 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2300 | */
|
---|
| 2301 | VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
|
---|
| 2302 | {
|
---|
| 2303 | return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
|
---|
| 2304 | }
|
---|
| 2305 |
|
---|
| 2306 |
|
---|
| 2307 | /**
|
---|
[25866] | 2308 | * Tests if the guest has the Page Size Extension enabled (PSE).
|
---|
| 2309 | *
|
---|
| 2310 | * @returns true if in real mode, otherwise false.
|
---|
[41803] | 2311 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25866] | 2312 | */
|
---|
| 2313 | VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
|
---|
| 2314 | {
|
---|
[26635] | 2315 | /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
|
---|
[26673] | 2316 | return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
|
---|
[25866] | 2317 | }
|
---|
| 2318 |
|
---|
| 2319 |
|
---|
| 2320 | /**
|
---|
| 2321 | * Tests if the guest has the paging enabled (PG).
|
---|
| 2322 | *
|
---|
| 2323 | * @returns true if in real mode, otherwise false.
|
---|
[41803] | 2324 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25866] | 2325 | */
|
---|
| 2326 | VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
|
---|
| 2327 | {
|
---|
| 2328 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
|
---|
| 2329 | }
|
---|
| 2330 |
|
---|
| 2331 |
|
---|
| 2332 | /**
|
---|
| 2333 | * Tests if the guest has the paging enabled (PG).
|
---|
| 2334 | *
|
---|
| 2335 | * @returns true if in real mode, otherwise false.
|
---|
[41803] | 2336 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25866] | 2337 | */
|
---|
| 2338 | VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
|
---|
| 2339 | {
|
---|
| 2340 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
|
---|
| 2341 | }
|
---|
| 2342 |
|
---|
| 2343 |
|
---|
| 2344 | /**
|
---|
[25835] | 2345 | * Tests if the guest is running in real mode or not.
|
---|
| 2346 | *
|
---|
| 2347 | * @returns true if in real mode, otherwise false.
|
---|
[41803] | 2348 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2349 | */
|
---|
| 2350 | VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
|
---|
| 2351 | {
|
---|
| 2352 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
| 2353 | }
|
---|
| 2354 |
|
---|
| 2355 |
|
---|
| 2356 | /**
|
---|
[36639] | 2357 | * Tests if the guest is running in real or virtual 8086 mode.
|
---|
| 2358 | *
|
---|
| 2359 | * @returns @c true if it is, @c false if not.
|
---|
[41803] | 2360 | * @param pVCpu Pointer to the VMCPU.
|
---|
[36639] | 2361 | */
|
---|
| 2362 | VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
|
---|
| 2363 | {
|
---|
| 2364 | return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
| 2365 | || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
|
---|
| 2366 | }
|
---|
| 2367 |
|
---|
| 2368 |
|
---|
| 2369 | /**
|
---|
[25835] | 2370 | * Tests if the guest is running in protected or not.
|
---|
| 2371 | *
|
---|
| 2372 | * @returns true if in protected mode, otherwise false.
|
---|
[41803] | 2373 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2374 | */
|
---|
| 2375 | VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
|
---|
| 2376 | {
|
---|
| 2377 | return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
|
---|
| 2378 | }
|
---|
| 2379 |
|
---|
| 2380 |
|
---|
| 2381 | /**
|
---|
| 2382 | * Tests if the guest is running in paged protected or not.
|
---|
| 2383 | *
|
---|
| 2384 | * @returns true if in paged protected mode, otherwise false.
|
---|
[41803] | 2385 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2386 | */
|
---|
| 2387 | VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
|
---|
| 2388 | {
|
---|
| 2389 | return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
|
---|
| 2390 | }
|
---|
| 2391 |
|
---|
| 2392 |
|
---|
| 2393 | /**
|
---|
| 2394 | * Tests if the guest is running in long mode or not.
|
---|
| 2395 | *
|
---|
| 2396 | * @returns true if in long mode, otherwise false.
|
---|
[41803] | 2397 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2398 | */
|
---|
| 2399 | VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
|
---|
| 2400 | {
|
---|
| 2401 | return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
|
---|
| 2402 | }
|
---|
| 2403 |
|
---|
| 2404 |
|
---|
| 2405 | /**
|
---|
| 2406 | * Tests if the guest is running in PAE mode or not.
|
---|
| 2407 | *
|
---|
| 2408 | * @returns true if in PAE mode, otherwise false.
|
---|
[41803] | 2409 | * @param pVCpu Pointer to the VMCPU.
|
---|
[25835] | 2410 | */
|
---|
| 2411 | VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
|
---|
| 2412 | {
|
---|
| 2413 | return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
|
---|
| 2414 | && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
|
---|
| 2415 | && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
|
---|
| 2416 | }
|
---|
| 2417 |
|
---|
| 2418 |
|
---|
[42165] | 2419 | /**
|
---|
| 2420 | * Tests if the guest is running in 64 bits mode or not.
|
---|
| 2421 | *
|
---|
| 2422 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
| 2423 | * @param pVCpu The current virtual CPU.
|
---|
| 2424 | */
|
---|
| 2425 | VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
|
---|
| 2426 | {
|
---|
| 2427 | if (!CPUMIsGuestInLongMode(pVCpu))
|
---|
| 2428 | return false;
|
---|
[42407] | 2429 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42165] | 2430 | return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
|
---|
| 2431 | }
|
---|
| 2432 |
|
---|
| 2433 |
|
---|
| 2434 | /**
|
---|
| 2435 | * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
|
---|
| 2436 | * registers.
|
---|
| 2437 | *
|
---|
| 2438 | * @returns true if in 64 bits protected mode, otherwise false.
|
---|
| 2439 | * @param pCtx Pointer to the current guest CPU context.
|
---|
| 2440 | */
|
---|
| 2441 | VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
|
---|
| 2442 | {
|
---|
| 2443 | return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
|
---|
| 2444 | }
|
---|
| 2445 |
|
---|
[42407] | 2446 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
| 2447 | /**
|
---|
| 2448 | *
|
---|
| 2449 | * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
|
---|
| 2450 | * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
|
---|
| 2451 | * @param pVCpu The current virtual CPU.
|
---|
| 2452 | */
|
---|
| 2453 | VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
|
---|
| 2454 | {
|
---|
| 2455 | return pVCpu->cpum.s.fRawEntered;
|
---|
| 2456 | }
|
---|
| 2457 | #endif
|
---|
[42165] | 2458 |
|
---|
[42705] | 2459 |
|
---|
[1] | 2460 | /**
|
---|
| 2461 | * Updates the EFLAGS while we're in raw-mode.
|
---|
| 2462 | *
|
---|
[41802] | 2463 | * @param pVCpu Pointer to the VMCPU.
|
---|
[41940] | 2464 | * @param fEfl The new EFLAGS value.
|
---|
[1] | 2465 | */
|
---|
[41940] | 2466 | VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
|
---|
[1] | 2467 | {
|
---|
[42705] | 2468 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
| 2469 | if (pVCpu->cpum.s.fRawEntered)
|
---|
| 2470 | PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
|
---|
| 2471 | else
|
---|
| 2472 | #endif
|
---|
[41940] | 2473 | pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
|
---|
[1] | 2474 | }
|
---|
| 2475 |
|
---|
[30263] | 2476 |
|
---|
[1] | 2477 | /**
|
---|
| 2478 | * Gets the EFLAGS while we're in raw-mode.
|
---|
| 2479 | *
|
---|
| 2480 | * @returns The eflags.
|
---|
[41940] | 2481 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
[1] | 2482 | */
|
---|
[41940] | 2483 | VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
|
---|
[1] | 2484 | {
|
---|
[42705] | 2485 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
| 2486 | if (pVCpu->cpum.s.fRawEntered)
|
---|
| 2487 | return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
|
---|
| 2488 | #endif
|
---|
[41940] | 2489 | return pVCpu->cpum.s.Guest.eflags.u32;
|
---|
[1] | 2490 | }
|
---|
| 2491 |
|
---|
| 2492 |
|
---|
| 2493 | /**
|
---|
| 2494 | * Sets the specified changed flags (CPUM_CHANGED_*).
|
---|
| 2495 | *
|
---|
[41940] | 2496 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
[1] | 2497 | */
|
---|
[18927] | 2498 | VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
|
---|
[1] | 2499 | {
|
---|
[18927] | 2500 | pVCpu->cpum.s.fChanged |= fChangedFlags;
|
---|
[1] | 2501 | }
|
---|
| 2502 |
|
---|
[12657] | 2503 |
|
---|
[1] | 2504 | /**
|
---|
| 2505 | * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
|
---|
| 2506 | * @returns true if supported.
|
---|
| 2507 | * @returns false if not supported.
|
---|
[41783] | 2508 | * @param pVM Pointer to the VM.
|
---|
[1] | 2509 | */
|
---|
[12989] | 2510 | VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
|
---|
[1] | 2511 | {
|
---|
| 2512 | return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
|
---|
| 2513 | }
|
---|
| 2514 |
|
---|
| 2515 |
|
---|
| 2516 | /**
|
---|
| 2517 | * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
|
---|
| 2518 | * @returns true if used.
|
---|
| 2519 | * @returns false if not used.
|
---|
[41783] | 2520 | * @param pVM Pointer to the VM.
|
---|
[1] | 2521 | */
|
---|
[12989] | 2522 | VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
|
---|
[1] | 2523 | {
|
---|
[18927] | 2524 | return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
|
---|
[1] | 2525 | }
|
---|
| 2526 |
|
---|
| 2527 |
|
---|
| 2528 | /**
|
---|
| 2529 | * Checks if the host OS uses the SYSCALL / SYSRET instructions.
|
---|
| 2530 | * @returns true if used.
|
---|
| 2531 | * @returns false if not used.
|
---|
[41783] | 2532 | * @param pVM Pointer to the VM.
|
---|
[1] | 2533 | */
|
---|
[12989] | 2534 | VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
|
---|
[1] | 2535 | {
|
---|
[18927] | 2536 | return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
|
---|
[1] | 2537 | }
|
---|
| 2538 |
|
---|
[12657] | 2539 | #ifndef IN_RING3
|
---|
[5695] | 2540 |
|
---|
[1] | 2541 | /**
|
---|
[42034] | 2542 | * Lazily sync in the FPU/XMM state.
|
---|
[1] | 2543 | *
|
---|
| 2544 | * @returns VBox status code.
|
---|
[41803] | 2545 | * @param pVCpu Pointer to the VMCPU.
|
---|
[1] | 2546 | */
|
---|
[18927] | 2547 | VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
|
---|
[1] | 2548 | {
|
---|
[15416] | 2549 | return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
|
---|
[1] | 2550 | }
|
---|
| 2551 |
|
---|
[5695] | 2552 | #endif /* !IN_RING3 */
|
---|
[1] | 2553 |
|
---|
| 2554 | /**
|
---|
[42034] | 2555 | * Checks if we activated the FPU/XMM state of the guest OS.
|
---|
[1] | 2556 | * @returns true if we did.
|
---|
| 2557 | * @returns false if not.
|
---|
[41802] | 2558 | * @param pVCpu Pointer to the VMCPU.
|
---|
[1] | 2559 | */
|
---|
[13960] | 2560 | VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
|
---|
[1] | 2561 | {
|
---|
[13960] | 2562 | return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
|
---|
[1] | 2563 | }
|
---|
| 2564 |
|
---|
[5695] | 2565 |
|
---|
[1] | 2566 | /**
|
---|
[42034] | 2567 | * Deactivate the FPU/XMM state of the guest OS.
|
---|
[41802] | 2568 | * @param pVCpu Pointer to the VMCPU.
|
---|
[1] | 2569 | */
|
---|
[18927] | 2570 | VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
|
---|
[1] | 2571 | {
|
---|
[18927] | 2572 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
|
---|
[1] | 2573 | }
|
---|
| 2574 |
|
---|
[5695] | 2575 |
|
---|
[1] | 2576 | /**
|
---|
[42034] | 2577 | * Checks if the guest debug state is active.
|
---|
[12578] | 2578 | *
|
---|
| 2579 | * @returns boolean
|
---|
[41800] | 2580 | * @param pVM Pointer to the VM.
|
---|
[12578] | 2581 | */
|
---|
[18927] | 2582 | VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
|
---|
[12578] | 2583 | {
|
---|
[18927] | 2584 | return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
|
---|
[12578] | 2585 | }
|
---|
| 2586 |
|
---|
[21252] | 2587 | /**
|
---|
[42034] | 2588 | * Checks if the hyper debug state is active.
|
---|
[21252] | 2589 | *
|
---|
| 2590 | * @returns boolean
|
---|
[41800] | 2591 | * @param pVM Pointer to the VM.
|
---|
[21252] | 2592 | */
|
---|
| 2593 | VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
|
---|
| 2594 | {
|
---|
| 2595 | return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
|
---|
| 2596 | }
|
---|
[12657] | 2597 |
|
---|
[21252] | 2598 |
|
---|
[12578] | 2599 | /**
|
---|
[30263] | 2600 | * Mark the guest's debug state as inactive.
|
---|
[12578] | 2601 | *
|
---|
| 2602 | * @returns boolean
|
---|
[41800] | 2603 | * @param pVM Pointer to the VM.
|
---|
[12578] | 2604 | */
|
---|
[18927] | 2605 | VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
|
---|
[12578] | 2606 | {
|
---|
[18927] | 2607 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
|
---|
[12578] | 2608 | }
|
---|
| 2609 |
|
---|
| 2610 |
|
---|
| 2611 | /**
|
---|
[30263] | 2612 | * Mark the hypervisor's debug state as inactive.
|
---|
[21252] | 2613 | *
|
---|
| 2614 | * @returns boolean
|
---|
[41800] | 2615 | * @param pVM Pointer to the VM.
|
---|
[21252] | 2616 | */
|
---|
| 2617 | VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
|
---|
| 2618 | {
|
---|
| 2619 | pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
|
---|
| 2620 | }
|
---|
| 2621 |
|
---|
[1] | 2622 |
|
---|
[1828] | 2623 | /**
|
---|
| 2624 | * Get the current privilege level of the guest.
|
---|
| 2625 | *
|
---|
[41939] | 2626 | * @returns CPL
|
---|
| 2627 | * @param pVCpu Pointer to the current virtual CPU.
|
---|
[1828] | 2628 | */
|
---|
[41939] | 2629 | VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
|
---|
[1828] | 2630 | {
|
---|
[42166] | 2631 | /*
|
---|
| 2632 | * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
|
---|
| 2633 | *
|
---|
| 2634 | * Note! We used to check CS.DPL here, assuming it was always equal to
|
---|
| 2635 | * CPL even if a conforming segment was loaded. But this truned out to
|
---|
| 2636 | * only apply to older AMD-V. With VT-x we had an ACP2 regression
|
---|
| 2637 | * during install after a far call to ring 2 with VT-x. Then on newer
|
---|
| 2638 | * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
|
---|
| 2639 | * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
|
---|
| 2640 | *
|
---|
| 2641 | * So, forget CS.DPL, always use SS.DPL.
|
---|
| 2642 | *
|
---|
| 2643 | * Note! The SS RPL is always equal to the CPL, while the CS RPL
|
---|
| 2644 | * isn't necessarily equal if the segment is conforming.
|
---|
| 2645 | * See section 4.11.1 in the AMD manual.
|
---|
| 2646 | */
|
---|
[41939] | 2647 | uint32_t uCpl;
|
---|
[42166] | 2648 | if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
|
---|
[10523] | 2649 | {
|
---|
[42166] | 2650 | if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
[31512] | 2651 | {
|
---|
[42407] | 2652 | if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
|
---|
[41939] | 2653 | uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
|
---|
[31512] | 2654 | else
|
---|
[42166] | 2655 | {
|
---|
| 2656 | uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
|
---|
[42188] | 2657 | #ifdef VBOX_WITH_RAW_MODE_NOT_R0
|
---|
[42166] | 2658 | if (uCpl == 1)
|
---|
| 2659 | uCpl = 0;
|
---|
[1828] | 2660 | #endif
|
---|
[42166] | 2661 | }
|
---|
[1969] | 2662 | }
|
---|
| 2663 | else
|
---|
[42166] | 2664 | uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
|
---|
[1828] | 2665 | }
|
---|
| 2666 | else
|
---|
[42166] | 2667 | uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
|
---|
[41939] | 2668 | return uCpl;
|
---|
[1828] | 2669 | }
|
---|
[4207] | 2670 |
|
---|
| 2671 |
|
---|
| 2672 | /**
|
---|
| 2673 | * Gets the current guest CPU mode.
|
---|
| 2674 | *
|
---|
| 2675 | * If paging mode is what you need, check out PGMGetGuestMode().
|
---|
| 2676 | *
|
---|
| 2677 | * @returns The CPU mode.
|
---|
[41802] | 2678 | * @param pVCpu Pointer to the VMCPU.
|
---|
[4207] | 2679 | */
|
---|
[18927] | 2680 | VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
|
---|
[4207] | 2681 | {
|
---|
| 2682 | CPUMMODE enmMode;
|
---|
[18927] | 2683 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
[4207] | 2684 | enmMode = CPUMMODE_REAL;
|
---|
[18927] | 2685 | else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
[4207] | 2686 | enmMode = CPUMMODE_PROTECTED;
|
---|
[9543] | 2687 | else
|
---|
| 2688 | enmMode = CPUMMODE_LONG;
|
---|
[4207] | 2689 |
|
---|
| 2690 | return enmMode;
|
---|
| 2691 | }
|
---|
[42186] | 2692 |
|
---|
| 2693 |
|
---|
| 2694 | /**
|
---|
| 2695 | * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
|
---|
| 2696 | *
|
---|
| 2697 | * @returns 16, 32 or 64.
|
---|
| 2698 | * @param pVCpu The current virtual CPU.
|
---|
| 2699 | */
|
---|
| 2700 | VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
|
---|
| 2701 | {
|
---|
| 2702 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
| 2703 | return 16;
|
---|
| 2704 |
|
---|
| 2705 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
| 2706 | {
|
---|
| 2707 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
| 2708 | return 16;
|
---|
| 2709 | }
|
---|
| 2710 |
|
---|
[42407] | 2711 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42186] | 2712 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
| 2713 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
| 2714 | return 64;
|
---|
| 2715 |
|
---|
| 2716 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
| 2717 | return 32;
|
---|
| 2718 |
|
---|
| 2719 | return 16;
|
---|
| 2720 | }
|
---|
| 2721 |
|
---|
| 2722 |
|
---|
| 2723 | VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
|
---|
| 2724 | {
|
---|
| 2725 | if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
|
---|
| 2726 | return DISCPUMODE_16BIT;
|
---|
| 2727 |
|
---|
| 2728 | if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
|
---|
| 2729 | {
|
---|
| 2730 | Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
|
---|
| 2731 | return DISCPUMODE_16BIT;
|
---|
| 2732 | }
|
---|
| 2733 |
|
---|
[42407] | 2734 | CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
|
---|
[42186] | 2735 | if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
|
---|
| 2736 | && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
|
---|
| 2737 | return DISCPUMODE_64BIT;
|
---|
| 2738 |
|
---|
| 2739 | if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
|
---|
| 2740 | return DISCPUMODE_32BIT;
|
---|
| 2741 |
|
---|
| 2742 | return DISCPUMODE_16BIT;
|
---|
| 2743 | }
|
---|
| 2744 |
|
---|