VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp@ 43860

Last change on this file since 43860 was 43860, checked in by vboxsync, 11 years ago

VMM/CPUMAllRegs: todo/question.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 77.8 KB
Line 
1/* $Id: CPUMAllRegs.cpp 43860 2012-11-12 17:12:37Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_CPUM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/patm.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/pdm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/mm.h>
29#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
30# include <VBox/vmm/selm.h>
31#endif
32#include "CPUMInternal.h"
33#include <VBox/vmm/vm.h>
34#include <VBox/err.h>
35#include <VBox/dis.h>
36#include <VBox/log.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/tm.h>
39#include <iprt/assert.h>
40#include <iprt/asm.h>
41#include <iprt/asm-amd64-x86.h>
42#ifdef IN_RING3
43#include <iprt/thread.h>
44#endif
45
46/** Disable stack frame pointer generation here. */
47#if defined(_MSC_VER) && !defined(DEBUG)
48# pragma optimize("y", off)
49#endif
50
51
52/*******************************************************************************
53* Defined Constants And Macros *
54*******************************************************************************/
55/**
56 * Converts a CPUMCPU::Guest pointer into a VMCPU pointer.
57 *
58 * @returns Pointer to the Virtual CPU.
59 * @param a_pGuestCtx Pointer to the guest context.
60 */
61#define CPUM_GUEST_CTX_TO_VMCPU(a_pGuestCtx) RT_FROM_MEMBER(a_pGuestCtx, VMCPU, cpum.s.Guest)
62
63/**
64 * Lazily loads the hidden parts of a selector register when using raw-mode.
65 */
66#if defined(VBOX_WITH_RAW_MODE) && !defined(IN_RING0)
67# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
68 do \
69 { \
70 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg)) \
71 cpumGuestLazyLoadHiddenSelectorReg(a_pVCpu, a_pSReg); \
72 } while (0)
73#else
74# define CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(a_pVCpu, a_pSReg) \
75 Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(a_pVCpu, a_pSReg));
76#endif
77
78
79
80#ifdef VBOX_WITH_RAW_MODE_NOT_R0
81
82/**
83 * Does the lazy hidden selector register loading.
84 *
85 * @param pVCpu The current Virtual CPU.
86 * @param pSReg The selector register to lazily load hidden parts of.
87 */
88static void cpumGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
89{
90 Assert(!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
91 Assert(!HMIsEnabled(pVCpu->CTX_SUFF(pVM)));
92 Assert((uintptr_t)(pSReg - &pVCpu->cpum.s.Guest.es) < X86_SREG_COUNT);
93
94 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
95 {
96 /* V8086 mode - Tightly controlled environment, no question about the limit or flags. */
97 pSReg->Attr.u = 0;
98 pSReg->Attr.n.u4Type = pSReg == &pVCpu->cpum.s.Guest.cs ? X86_SEL_TYPE_ER_ACC : X86_SEL_TYPE_RW_ACC;
99 pSReg->Attr.n.u1DescType = 1; /* code/data segment */
100 pSReg->Attr.n.u2Dpl = 3;
101 pSReg->Attr.n.u1Present = 1;
102 pSReg->u32Limit = 0x0000ffff;
103 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
104 pSReg->ValidSel = pSReg->Sel;
105 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
106 /** @todo Check what the accessed bit should be (VT-x and AMD-V). */
107 }
108 else if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
109 {
110 /* Real mode - leave the limit and flags alone here, at least for now. */
111 pSReg->u64Base = (uint32_t)pSReg->Sel << 4;
112 pSReg->ValidSel = pSReg->Sel;
113 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
114 }
115 else
116 {
117 /* Protected mode - get it from the selector descriptor tables. */
118 if (!(pSReg->Sel & X86_SEL_MASK_OFF_RPL))
119 {
120 Assert(!CPUMIsGuestInLongMode(pVCpu));
121 pSReg->Sel = 0;
122 pSReg->u64Base = 0;
123 pSReg->u32Limit = 0;
124 pSReg->Attr.u = 0;
125 pSReg->ValidSel = 0;
126 pSReg->fFlags = CPUMSELREG_FLAGS_VALID;
127 /** @todo see todo in iemHlpLoadNullDataSelectorProt. */
128 }
129 else
130 SELMLoadHiddenSelectorReg(pVCpu, &pVCpu->cpum.s.Guest, pSReg);
131 }
132}
133
134
135/**
136 * Makes sure the hidden CS and SS selector registers are valid, loading them if
137 * necessary.
138 *
139 * @param pVCpu The current virtual CPU.
140 */
141VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenCsAndSs(PVMCPU pVCpu)
142{
143 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
144 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.ss);
145}
146
147
148/**
149 * Loads a the hidden parts of a selector register.
150 *
151 * @param pVCpu The current virtual CPU.
152 */
153VMM_INT_DECL(void) CPUMGuestLazyLoadHiddenSelectorReg(PVMCPU pVCpu, PCPUMSELREG pSReg)
154{
155 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, pSReg);
156}
157
158#endif /* VBOX_WITH_RAW_MODE_NOT_R0 */
159
160
161/**
162 * Obsolete.
163 *
164 * We don't support nested hypervisor context interrupts or traps. Life is much
165 * simpler when we don't. It's also slightly faster at times.
166 *
167 * @param pVM Handle to the virtual machine.
168 */
169VMMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVMCPU pVCpu)
170{
171 return CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
172}
173
174
175/**
176 * Gets the pointer to the hypervisor CPU context structure of a virtual CPU.
177 *
178 * @param pVCpu Pointer to the VMCPU.
179 */
180VMMDECL(PCPUMCTX) CPUMGetHyperCtxPtr(PVMCPU pVCpu)
181{
182 return &pVCpu->cpum.s.Hyper;
183}
184
185
186VMMDECL(void) CPUMSetHyperGDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
187{
188 pVCpu->cpum.s.Hyper.gdtr.cbGdt = limit;
189 pVCpu->cpum.s.Hyper.gdtr.pGdt = addr;
190}
191
192
193VMMDECL(void) CPUMSetHyperIDTR(PVMCPU pVCpu, uint32_t addr, uint16_t limit)
194{
195 pVCpu->cpum.s.Hyper.idtr.cbIdt = limit;
196 pVCpu->cpum.s.Hyper.idtr.pIdt = addr;
197}
198
199
200VMMDECL(void) CPUMSetHyperCR3(PVMCPU pVCpu, uint32_t cr3)
201{
202 pVCpu->cpum.s.Hyper.cr3 = cr3;
203
204#ifdef IN_RC
205 /* Update the current CR3. */
206 ASMSetCR3(cr3);
207#endif
208}
209
210VMMDECL(uint32_t) CPUMGetHyperCR3(PVMCPU pVCpu)
211{
212 return pVCpu->cpum.s.Hyper.cr3;
213}
214
215
216VMMDECL(void) CPUMSetHyperCS(PVMCPU pVCpu, RTSEL SelCS)
217{
218 pVCpu->cpum.s.Hyper.cs.Sel = SelCS;
219}
220
221
222VMMDECL(void) CPUMSetHyperDS(PVMCPU pVCpu, RTSEL SelDS)
223{
224 pVCpu->cpum.s.Hyper.ds.Sel = SelDS;
225}
226
227
228VMMDECL(void) CPUMSetHyperES(PVMCPU pVCpu, RTSEL SelES)
229{
230 pVCpu->cpum.s.Hyper.es.Sel = SelES;
231}
232
233
234VMMDECL(void) CPUMSetHyperFS(PVMCPU pVCpu, RTSEL SelFS)
235{
236 pVCpu->cpum.s.Hyper.fs.Sel = SelFS;
237}
238
239
240VMMDECL(void) CPUMSetHyperGS(PVMCPU pVCpu, RTSEL SelGS)
241{
242 pVCpu->cpum.s.Hyper.gs.Sel = SelGS;
243}
244
245
246VMMDECL(void) CPUMSetHyperSS(PVMCPU pVCpu, RTSEL SelSS)
247{
248 pVCpu->cpum.s.Hyper.ss.Sel = SelSS;
249}
250
251
252VMMDECL(void) CPUMSetHyperESP(PVMCPU pVCpu, uint32_t u32ESP)
253{
254 pVCpu->cpum.s.Hyper.esp = u32ESP;
255}
256
257
258VMMDECL(void) CPUMSetHyperEDX(PVMCPU pVCpu, uint32_t u32ESP)
259{
260 pVCpu->cpum.s.Hyper.esp = u32ESP;
261}
262
263
264VMMDECL(int) CPUMSetHyperEFlags(PVMCPU pVCpu, uint32_t Efl)
265{
266 pVCpu->cpum.s.Hyper.eflags.u32 = Efl;
267 return VINF_SUCCESS;
268}
269
270
271VMMDECL(void) CPUMSetHyperEIP(PVMCPU pVCpu, uint32_t u32EIP)
272{
273 pVCpu->cpum.s.Hyper.eip = u32EIP;
274}
275
276
277/**
278 * Used by VMMR3RawRunGC to reinitialize the general raw-mode context registers,
279 * EFLAGS and EIP prior to resuming guest execution.
280 *
281 * All general register not given as a parameter will be set to 0. The EFLAGS
282 * register will be set to sane values for C/C++ code execution with interrupts
283 * disabled and IOPL 0.
284 *
285 * @param pVCpu The current virtual CPU.
286 * @param u32EIP The EIP value.
287 * @param u32ESP The ESP value.
288 * @param u32EAX The EAX value.
289 * @param u32EDX The EDX value.
290 */
291VMM_INT_DECL(void) CPUMSetHyperState(PVMCPU pVCpu, uint32_t u32EIP, uint32_t u32ESP, uint32_t u32EAX, uint32_t u32EDX)
292{
293 pVCpu->cpum.s.Hyper.eip = u32EIP;
294 pVCpu->cpum.s.Hyper.esp = u32ESP;
295 pVCpu->cpum.s.Hyper.eax = u32EAX;
296 pVCpu->cpum.s.Hyper.edx = u32EDX;
297 pVCpu->cpum.s.Hyper.ecx = 0;
298 pVCpu->cpum.s.Hyper.ebx = 0;
299 pVCpu->cpum.s.Hyper.ebp = 0;
300 pVCpu->cpum.s.Hyper.esi = 0;
301 pVCpu->cpum.s.Hyper.edi = 0;
302 pVCpu->cpum.s.Hyper.eflags.u = X86_EFL_1;
303}
304
305
306VMMDECL(void) CPUMSetHyperTR(PVMCPU pVCpu, RTSEL SelTR)
307{
308 pVCpu->cpum.s.Hyper.tr.Sel = SelTR;
309}
310
311
312VMMDECL(void) CPUMSetHyperLDTR(PVMCPU pVCpu, RTSEL SelLDTR)
313{
314 pVCpu->cpum.s.Hyper.ldtr.Sel = SelLDTR;
315}
316
317
318VMMDECL(void) CPUMSetHyperDR0(PVMCPU pVCpu, RTGCUINTREG uDr0)
319{
320 pVCpu->cpum.s.Hyper.dr[0] = uDr0;
321 /** @todo in GC we must load it! */
322}
323
324
325VMMDECL(void) CPUMSetHyperDR1(PVMCPU pVCpu, RTGCUINTREG uDr1)
326{
327 pVCpu->cpum.s.Hyper.dr[1] = uDr1;
328 /** @todo in GC we must load it! */
329}
330
331
332VMMDECL(void) CPUMSetHyperDR2(PVMCPU pVCpu, RTGCUINTREG uDr2)
333{
334 pVCpu->cpum.s.Hyper.dr[2] = uDr2;
335 /** @todo in GC we must load it! */
336}
337
338
339VMMDECL(void) CPUMSetHyperDR3(PVMCPU pVCpu, RTGCUINTREG uDr3)
340{
341 pVCpu->cpum.s.Hyper.dr[3] = uDr3;
342 /** @todo in GC we must load it! */
343}
344
345
346VMMDECL(void) CPUMSetHyperDR6(PVMCPU pVCpu, RTGCUINTREG uDr6)
347{
348 pVCpu->cpum.s.Hyper.dr[6] = uDr6;
349 /** @todo in GC we must load it! */
350}
351
352
353VMMDECL(void) CPUMSetHyperDR7(PVMCPU pVCpu, RTGCUINTREG uDr7)
354{
355 pVCpu->cpum.s.Hyper.dr[7] = uDr7;
356 /** @todo in GC we must load it! */
357}
358
359
360VMMDECL(RTSEL) CPUMGetHyperCS(PVMCPU pVCpu)
361{
362 return pVCpu->cpum.s.Hyper.cs.Sel;
363}
364
365
366VMMDECL(RTSEL) CPUMGetHyperDS(PVMCPU pVCpu)
367{
368 return pVCpu->cpum.s.Hyper.ds.Sel;
369}
370
371
372VMMDECL(RTSEL) CPUMGetHyperES(PVMCPU pVCpu)
373{
374 return pVCpu->cpum.s.Hyper.es.Sel;
375}
376
377
378VMMDECL(RTSEL) CPUMGetHyperFS(PVMCPU pVCpu)
379{
380 return pVCpu->cpum.s.Hyper.fs.Sel;
381}
382
383
384VMMDECL(RTSEL) CPUMGetHyperGS(PVMCPU pVCpu)
385{
386 return pVCpu->cpum.s.Hyper.gs.Sel;
387}
388
389
390VMMDECL(RTSEL) CPUMGetHyperSS(PVMCPU pVCpu)
391{
392 return pVCpu->cpum.s.Hyper.ss.Sel;
393}
394
395
396VMMDECL(uint32_t) CPUMGetHyperEAX(PVMCPU pVCpu)
397{
398 return pVCpu->cpum.s.Hyper.eax;
399}
400
401
402VMMDECL(uint32_t) CPUMGetHyperEBX(PVMCPU pVCpu)
403{
404 return pVCpu->cpum.s.Hyper.ebx;
405}
406
407
408VMMDECL(uint32_t) CPUMGetHyperECX(PVMCPU pVCpu)
409{
410 return pVCpu->cpum.s.Hyper.ecx;
411}
412
413
414VMMDECL(uint32_t) CPUMGetHyperEDX(PVMCPU pVCpu)
415{
416 return pVCpu->cpum.s.Hyper.edx;
417}
418
419
420VMMDECL(uint32_t) CPUMGetHyperESI(PVMCPU pVCpu)
421{
422 return pVCpu->cpum.s.Hyper.esi;
423}
424
425
426VMMDECL(uint32_t) CPUMGetHyperEDI(PVMCPU pVCpu)
427{
428 return pVCpu->cpum.s.Hyper.edi;
429}
430
431
432VMMDECL(uint32_t) CPUMGetHyperEBP(PVMCPU pVCpu)
433{
434 return pVCpu->cpum.s.Hyper.ebp;
435}
436
437
438VMMDECL(uint32_t) CPUMGetHyperESP(PVMCPU pVCpu)
439{
440 return pVCpu->cpum.s.Hyper.esp;
441}
442
443
444VMMDECL(uint32_t) CPUMGetHyperEFlags(PVMCPU pVCpu)
445{
446 return pVCpu->cpum.s.Hyper.eflags.u32;
447}
448
449
450VMMDECL(uint32_t) CPUMGetHyperEIP(PVMCPU pVCpu)
451{
452 return pVCpu->cpum.s.Hyper.eip;
453}
454
455
456VMMDECL(uint64_t) CPUMGetHyperRIP(PVMCPU pVCpu)
457{
458 return pVCpu->cpum.s.Hyper.rip;
459}
460
461
462VMMDECL(uint32_t) CPUMGetHyperIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
463{
464 if (pcbLimit)
465 *pcbLimit = pVCpu->cpum.s.Hyper.idtr.cbIdt;
466 return pVCpu->cpum.s.Hyper.idtr.pIdt;
467}
468
469
470VMMDECL(uint32_t) CPUMGetHyperGDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
471{
472 if (pcbLimit)
473 *pcbLimit = pVCpu->cpum.s.Hyper.gdtr.cbGdt;
474 return pVCpu->cpum.s.Hyper.gdtr.pGdt;
475}
476
477
478VMMDECL(RTSEL) CPUMGetHyperLDTR(PVMCPU pVCpu)
479{
480 return pVCpu->cpum.s.Hyper.ldtr.Sel;
481}
482
483
484VMMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVMCPU pVCpu)
485{
486 return pVCpu->cpum.s.Hyper.dr[0];
487}
488
489
490VMMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVMCPU pVCpu)
491{
492 return pVCpu->cpum.s.Hyper.dr[1];
493}
494
495
496VMMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVMCPU pVCpu)
497{
498 return pVCpu->cpum.s.Hyper.dr[2];
499}
500
501
502VMMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVMCPU pVCpu)
503{
504 return pVCpu->cpum.s.Hyper.dr[3];
505}
506
507
508VMMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVMCPU pVCpu)
509{
510 return pVCpu->cpum.s.Hyper.dr[6];
511}
512
513
514VMMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVMCPU pVCpu)
515{
516 return pVCpu->cpum.s.Hyper.dr[7];
517}
518
519
520/**
521 * Gets the pointer to the internal CPUMCTXCORE structure.
522 * This is only for reading in order to save a few calls.
523 *
524 * @param pVCpu Handle to the virtual cpu.
525 */
526VMMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVMCPU pVCpu)
527{
528 return CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
529}
530
531
532/**
533 * Queries the pointer to the internal CPUMCTX structure.
534 *
535 * @returns The CPUMCTX pointer.
536 * @param pVCpu Handle to the virtual cpu.
537 */
538VMMDECL(PCPUMCTX) CPUMQueryGuestCtxPtr(PVMCPU pVCpu)
539{
540 return &pVCpu->cpum.s.Guest;
541}
542
543VMMDECL(int) CPUMSetGuestGDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
544{
545#ifdef VBOX_WITH_IEM
546# ifdef VBOX_WITH_RAW_MODE_NOT_R0
547 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
548 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
549# endif
550#endif
551 pVCpu->cpum.s.Guest.gdtr.cbGdt = cbLimit;
552 pVCpu->cpum.s.Guest.gdtr.pGdt = GCPtrBase;
553 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GDTR;
554 return VINF_SUCCESS; /* formality, consider it void. */
555}
556
557VMMDECL(int) CPUMSetGuestIDTR(PVMCPU pVCpu, uint64_t GCPtrBase, uint16_t cbLimit)
558{
559#ifdef VBOX_WITH_IEM
560# ifdef VBOX_WITH_RAW_MODE_NOT_R0
561 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
562 VMCPU_FF_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
563# endif
564#endif
565 pVCpu->cpum.s.Guest.idtr.cbIdt = cbLimit;
566 pVCpu->cpum.s.Guest.idtr.pIdt = GCPtrBase;
567 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_IDTR;
568 return VINF_SUCCESS; /* formality, consider it void. */
569}
570
571VMMDECL(int) CPUMSetGuestTR(PVMCPU pVCpu, uint16_t tr)
572{
573#ifdef VBOX_WITH_IEM
574# ifdef VBOX_WITH_RAW_MODE_NOT_R0
575 if (!HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
576 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
577# endif
578#endif
579 pVCpu->cpum.s.Guest.tr.Sel = tr;
580 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_TR;
581 return VINF_SUCCESS; /* formality, consider it void. */
582}
583
584VMMDECL(int) CPUMSetGuestLDTR(PVMCPU pVCpu, uint16_t ldtr)
585{
586#ifdef VBOX_WITH_IEM
587# ifdef VBOX_WITH_RAW_MODE_NOT_R0
588 if ( ( ldtr != 0
589 || pVCpu->cpum.s.Guest.ldtr.Sel != 0)
590 && !HMIsEnabled(pVCpu->CTX_SUFF(pVM)))
591 VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
592# endif
593#endif
594 pVCpu->cpum.s.Guest.ldtr.Sel = ldtr;
595 /* The caller will set more hidden bits if it has them. */
596 pVCpu->cpum.s.Guest.ldtr.ValidSel = 0;
597 pVCpu->cpum.s.Guest.ldtr.fFlags = 0;
598 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_LDTR;
599 return VINF_SUCCESS; /* formality, consider it void. */
600}
601
602
603/**
604 * Set the guest CR0.
605 *
606 * When called in GC, the hyper CR0 may be updated if that is
607 * required. The caller only has to take special action if AM,
608 * WP, PG or PE changes.
609 *
610 * @returns VINF_SUCCESS (consider it void).
611 * @param pVCpu Handle to the virtual cpu.
612 * @param cr0 The new CR0 value.
613 */
614VMMDECL(int) CPUMSetGuestCR0(PVMCPU pVCpu, uint64_t cr0)
615{
616#ifdef IN_RC
617 /*
618 * Check if we need to change hypervisor CR0 because
619 * of math stuff.
620 */
621 if ( (cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
622 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)))
623 {
624 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU))
625 {
626 /*
627 * We haven't saved the host FPU state yet, so TS and MT are both set
628 * and EM should be reflecting the guest EM (it always does this).
629 */
630 if ((cr0 & X86_CR0_EM) != (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM))
631 {
632 uint32_t HyperCR0 = ASMGetCR0();
633 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
634 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
635 HyperCR0 &= ~X86_CR0_EM;
636 HyperCR0 |= cr0 & X86_CR0_EM;
637 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
638 ASMSetCR0(HyperCR0);
639 }
640# ifdef VBOX_STRICT
641 else
642 {
643 uint32_t HyperCR0 = ASMGetCR0();
644 AssertMsg((HyperCR0 & (X86_CR0_TS | X86_CR0_MP)) == (X86_CR0_TS | X86_CR0_MP), ("%#x\n", HyperCR0));
645 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVCpu->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
646 }
647# endif
648 }
649 else
650 {
651 /*
652 * Already saved the state, so we're just mirroring
653 * the guest flags.
654 */
655 uint32_t HyperCR0 = ASMGetCR0();
656 AssertMsg( (HyperCR0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP))
657 == (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)),
658 ("%#x %#x\n", HyperCR0, pVCpu->cpum.s.Guest.cr0));
659 HyperCR0 &= ~(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
660 HyperCR0 |= cr0 & (X86_CR0_TS | X86_CR0_EM | X86_CR0_MP);
661 Log(("CPUM New HyperCR0=%#x\n", HyperCR0));
662 ASMSetCR0(HyperCR0);
663 }
664 }
665#endif /* IN_RC */
666
667 /*
668 * Check for changes causing TLB flushes (for REM).
669 * The caller is responsible for calling PGM when appropriate.
670 */
671 if ( (cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE))
672 != (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG | X86_CR0_WP | X86_CR0_PE)))
673 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
674 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR0;
675
676 pVCpu->cpum.s.Guest.cr0 = cr0 | X86_CR0_ET;
677 return VINF_SUCCESS;
678}
679
680
681VMMDECL(int) CPUMSetGuestCR2(PVMCPU pVCpu, uint64_t cr2)
682{
683 pVCpu->cpum.s.Guest.cr2 = cr2;
684 return VINF_SUCCESS;
685}
686
687
688VMMDECL(int) CPUMSetGuestCR3(PVMCPU pVCpu, uint64_t cr3)
689{
690 pVCpu->cpum.s.Guest.cr3 = cr3;
691 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR3;
692 return VINF_SUCCESS;
693}
694
695
696VMMDECL(int) CPUMSetGuestCR4(PVMCPU pVCpu, uint64_t cr4)
697{
698 if ( (cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE))
699 != (pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PGE | X86_CR4_PAE | X86_CR4_PSE)))
700 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_GLOBAL_TLB_FLUSH;
701 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CR4;
702 if (!CPUMSupportsFXSR(pVCpu->CTX_SUFF(pVM)))
703 cr4 &= ~X86_CR4_OSFSXR;
704 pVCpu->cpum.s.Guest.cr4 = cr4;
705 return VINF_SUCCESS;
706}
707
708
709VMMDECL(int) CPUMSetGuestEFlags(PVMCPU pVCpu, uint32_t eflags)
710{
711 pVCpu->cpum.s.Guest.eflags.u32 = eflags;
712 return VINF_SUCCESS;
713}
714
715
716VMMDECL(int) CPUMSetGuestEIP(PVMCPU pVCpu, uint32_t eip)
717{
718 pVCpu->cpum.s.Guest.eip = eip;
719 return VINF_SUCCESS;
720}
721
722
723VMMDECL(int) CPUMSetGuestEAX(PVMCPU pVCpu, uint32_t eax)
724{
725 pVCpu->cpum.s.Guest.eax = eax;
726 return VINF_SUCCESS;
727}
728
729
730VMMDECL(int) CPUMSetGuestEBX(PVMCPU pVCpu, uint32_t ebx)
731{
732 pVCpu->cpum.s.Guest.ebx = ebx;
733 return VINF_SUCCESS;
734}
735
736
737VMMDECL(int) CPUMSetGuestECX(PVMCPU pVCpu, uint32_t ecx)
738{
739 pVCpu->cpum.s.Guest.ecx = ecx;
740 return VINF_SUCCESS;
741}
742
743
744VMMDECL(int) CPUMSetGuestEDX(PVMCPU pVCpu, uint32_t edx)
745{
746 pVCpu->cpum.s.Guest.edx = edx;
747 return VINF_SUCCESS;
748}
749
750
751VMMDECL(int) CPUMSetGuestESP(PVMCPU pVCpu, uint32_t esp)
752{
753 pVCpu->cpum.s.Guest.esp = esp;
754 return VINF_SUCCESS;
755}
756
757
758VMMDECL(int) CPUMSetGuestEBP(PVMCPU pVCpu, uint32_t ebp)
759{
760 pVCpu->cpum.s.Guest.ebp = ebp;
761 return VINF_SUCCESS;
762}
763
764
765VMMDECL(int) CPUMSetGuestESI(PVMCPU pVCpu, uint32_t esi)
766{
767 pVCpu->cpum.s.Guest.esi = esi;
768 return VINF_SUCCESS;
769}
770
771
772VMMDECL(int) CPUMSetGuestEDI(PVMCPU pVCpu, uint32_t edi)
773{
774 pVCpu->cpum.s.Guest.edi = edi;
775 return VINF_SUCCESS;
776}
777
778
779VMMDECL(int) CPUMSetGuestSS(PVMCPU pVCpu, uint16_t ss)
780{
781 pVCpu->cpum.s.Guest.ss.Sel = ss;
782 return VINF_SUCCESS;
783}
784
785
786VMMDECL(int) CPUMSetGuestCS(PVMCPU pVCpu, uint16_t cs)
787{
788 pVCpu->cpum.s.Guest.cs.Sel = cs;
789 return VINF_SUCCESS;
790}
791
792
793VMMDECL(int) CPUMSetGuestDS(PVMCPU pVCpu, uint16_t ds)
794{
795 pVCpu->cpum.s.Guest.ds.Sel = ds;
796 return VINF_SUCCESS;
797}
798
799
800VMMDECL(int) CPUMSetGuestES(PVMCPU pVCpu, uint16_t es)
801{
802 pVCpu->cpum.s.Guest.es.Sel = es;
803 return VINF_SUCCESS;
804}
805
806
807VMMDECL(int) CPUMSetGuestFS(PVMCPU pVCpu, uint16_t fs)
808{
809 pVCpu->cpum.s.Guest.fs.Sel = fs;
810 return VINF_SUCCESS;
811}
812
813
814VMMDECL(int) CPUMSetGuestGS(PVMCPU pVCpu, uint16_t gs)
815{
816 pVCpu->cpum.s.Guest.gs.Sel = gs;
817 return VINF_SUCCESS;
818}
819
820
821VMMDECL(void) CPUMSetGuestEFER(PVMCPU pVCpu, uint64_t val)
822{
823 pVCpu->cpum.s.Guest.msrEFER = val;
824}
825
826
827/**
828 * Query an MSR.
829 *
830 * The caller is responsible for checking privilege if the call is the result
831 * of a RDMSR instruction. We'll do the rest.
832 *
833 * @retval VINF_SUCCESS on success.
834 * @retval VERR_CPUM_RAISE_GP_0 on failure (invalid MSR), the caller is
835 * expected to take the appropriate actions. @a *puValue is set to 0.
836 * @param pVCpu Pointer to the VMCPU.
837 * @param idMsr The MSR.
838 * @param puValue Where to return the value.
839 *
840 * @remarks This will always return the right values, even when we're in the
841 * recompiler.
842 */
843VMMDECL(int) CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue)
844{
845 /*
846 * If we don't indicate MSR support in the CPUID feature bits, indicate
847 * that a #GP(0) should be raised.
848 */
849 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
850 {
851 *puValue = 0;
852 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
853 }
854
855 int rc = VINF_SUCCESS;
856 uint8_t const u8Multiplier = 4;
857 switch (idMsr)
858 {
859 case MSR_IA32_TSC:
860 *puValue = TMCpuTickGet(pVCpu);
861 break;
862
863 case MSR_IA32_APICBASE:
864 {
865 PVM pVM = pVCpu->CTX_SUFF(pVM);
866 if ( ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* APIC Std feature */
867 && (pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_APIC))
868 || ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001 /* APIC Ext feature (AMD) */
869 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD
870 && (pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_AMD_FEATURE_EDX_APIC))
871 || ( pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1 /* x2APIC */
872 && (pVM->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_X2APIC)))
873 {
874 *puValue = pVCpu->cpum.s.Guest.msrApicBase;
875 }
876 else
877 {
878 *puValue = 0;
879 rc = VERR_CPUM_RAISE_GP_0;
880 }
881 break;
882 }
883
884 case MSR_IA32_CR_PAT:
885 *puValue = pVCpu->cpum.s.Guest.msrPAT;
886 break;
887
888 case MSR_IA32_SYSENTER_CS:
889 *puValue = pVCpu->cpum.s.Guest.SysEnter.cs;
890 break;
891
892 case MSR_IA32_SYSENTER_EIP:
893 *puValue = pVCpu->cpum.s.Guest.SysEnter.eip;
894 break;
895
896 case MSR_IA32_SYSENTER_ESP:
897 *puValue = pVCpu->cpum.s.Guest.SysEnter.esp;
898 break;
899
900 case MSR_IA32_MTRR_CAP:
901 {
902 /* This is currently a bit weird. :-) */
903 uint8_t const cVariableRangeRegs = 0;
904 bool const fSystemManagementRangeRegisters = false;
905 bool const fFixedRangeRegisters = false;
906 bool const fWriteCombiningType = false;
907 *puValue = cVariableRangeRegs
908 | (fFixedRangeRegisters ? RT_BIT_64(8) : 0)
909 | (fWriteCombiningType ? RT_BIT_64(10) : 0)
910 | (fSystemManagementRangeRegisters ? RT_BIT_64(11) : 0);
911 break;
912 }
913
914 case MSR_IA32_MTRR_DEF_TYPE:
915 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType;
916 break;
917
918 case IA32_MTRR_FIX64K_00000:
919 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000;
920 break;
921 case IA32_MTRR_FIX16K_80000:
922 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000;
923 break;
924 case IA32_MTRR_FIX16K_A0000:
925 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000;
926 break;
927 case IA32_MTRR_FIX4K_C0000:
928 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000;
929 break;
930 case IA32_MTRR_FIX4K_C8000:
931 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000;
932 break;
933 case IA32_MTRR_FIX4K_D0000:
934 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000;
935 break;
936 case IA32_MTRR_FIX4K_D8000:
937 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000;
938 break;
939 case IA32_MTRR_FIX4K_E0000:
940 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000;
941 break;
942 case IA32_MTRR_FIX4K_E8000:
943 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000;
944 break;
945 case IA32_MTRR_FIX4K_F0000:
946 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000;
947 break;
948 case IA32_MTRR_FIX4K_F8000:
949 *puValue = pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000;
950 break;
951
952 case MSR_K6_EFER:
953 *puValue = pVCpu->cpum.s.Guest.msrEFER;
954 break;
955
956 case MSR_K8_SF_MASK:
957 *puValue = pVCpu->cpum.s.Guest.msrSFMASK;
958 break;
959
960 case MSR_K6_STAR:
961 *puValue = pVCpu->cpum.s.Guest.msrSTAR;
962 break;
963
964 case MSR_K8_LSTAR:
965 *puValue = pVCpu->cpum.s.Guest.msrLSTAR;
966 break;
967
968 case MSR_K8_CSTAR:
969 *puValue = pVCpu->cpum.s.Guest.msrCSTAR;
970 break;
971
972 case MSR_K8_FS_BASE:
973 *puValue = pVCpu->cpum.s.Guest.fs.u64Base;
974 break;
975
976 case MSR_K8_GS_BASE:
977 *puValue = pVCpu->cpum.s.Guest.gs.u64Base;
978 break;
979
980 case MSR_K8_KERNEL_GS_BASE:
981 *puValue = pVCpu->cpum.s.Guest.msrKERNELGSBASE;
982 break;
983
984 case MSR_K8_TSC_AUX:
985 *puValue = pVCpu->cpum.s.GuestMsrs.msr.TscAux;
986 break;
987
988 case MSR_IA32_PERF_STATUS:
989 /** @todo could really be not exactly correct, maybe use host's values */
990 *puValue = UINT64_C(1000) /* TSC increment by tick */
991 | ((uint64_t)u8Multiplier << 24) /* CPU multiplier (aka bus ratio) min */
992 | ((uint64_t)u8Multiplier << 40) /* CPU multiplier (aka bus ratio) max */;
993 break;
994
995 case MSR_IA32_FSB_CLOCK_STS:
996 /*
997 * Encoded as:
998 * 0 - 266
999 * 1 - 133
1000 * 2 - 200
1001 * 3 - return 166
1002 * 5 - return 100
1003 */
1004 *puValue = (2 << 4);
1005 break;
1006
1007 case MSR_IA32_PLATFORM_INFO:
1008 *puValue = (u8Multiplier << 8) /* Flex ratio max */
1009 | ((uint64_t)u8Multiplier << 40) /* Flex ratio min */;
1010 break;
1011
1012 case MSR_IA32_THERM_STATUS:
1013 /* CPU temperature relative to TCC, to actually activate, CPUID leaf 6 EAX[0] must be set */
1014 *puValue = RT_BIT(31) /* validity bit */
1015 | (UINT64_C(20) << 16) /* degrees till TCC */;
1016 break;
1017
1018 case MSR_IA32_MISC_ENABLE:
1019#if 0
1020 /* Needs to be tested more before enabling. */
1021 *puValue = pVCpu->cpum.s.GuestMsr.msr.miscEnable;
1022#else
1023 /* Currenty we don't allow guests to modify enable MSRs. */
1024 *puValue = MSR_IA32_MISC_ENABLE_FAST_STRINGS /* by default */;
1025
1026 if ((pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR) != 0)
1027
1028 *puValue |= MSR_IA32_MISC_ENABLE_MONITOR /* if mwait/monitor available */;
1029 /** @todo: add more cpuid-controlled features this way. */
1030#endif
1031 break;
1032
1033#if 0 /*def IN_RING0 */
1034 case MSR_IA32_PLATFORM_ID:
1035 case MSR_IA32_BIOS_SIGN_ID:
1036 if (CPUMGetCPUVendor(pVM) == CPUMCPUVENDOR_INTEL)
1037 {
1038 /* Available since the P6 family. VT-x implies that this feature is present. */
1039 if (idMsr == MSR_IA32_PLATFORM_ID)
1040 *puValue = ASMRdMsr(MSR_IA32_PLATFORM_ID);
1041 else if (idMsr == MSR_IA32_BIOS_SIGN_ID)
1042 *puValue = ASMRdMsr(MSR_IA32_BIOS_SIGN_ID);
1043 break;
1044 }
1045 /* no break */
1046#endif
1047
1048 /*
1049 * Intel specifics MSRs:
1050 */
1051 case MSR_IA32_PLATFORM_ID: /* fam/mod >= 6_01 */
1052 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1053 /*case MSR_IA32_BIOS_UPDT_TRIG: - write-only? */
1054 case MSR_IA32_MCP_CAP: /* fam/mod >= 6_01 */
1055 /*case MSR_IA32_MCP_STATUS: - indicated as not present in CAP */
1056 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1057 case MSR_IA32_MC0_CTL:
1058 case MSR_IA32_MC0_STATUS:
1059 *puValue = 0;
1060 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1061 {
1062 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1063 rc = VERR_CPUM_RAISE_GP_0;
1064 }
1065 break;
1066
1067 default:
1068 /*
1069 * Hand the X2APIC range to PDM and the APIC.
1070 */
1071 if ( idMsr >= MSR_IA32_APIC_START
1072 && idMsr < MSR_IA32_APIC_END)
1073 {
1074 rc = PDMApicReadMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, puValue);
1075 if (RT_SUCCESS(rc))
1076 rc = VINF_SUCCESS;
1077 else
1078 {
1079 *puValue = 0;
1080 rc = VERR_CPUM_RAISE_GP_0;
1081 }
1082 }
1083 else
1084 {
1085 *puValue = 0;
1086 rc = VERR_CPUM_RAISE_GP_0;
1087 }
1088 break;
1089 }
1090
1091 return rc;
1092}
1093
1094
1095/**
1096 * Sets the MSR.
1097 *
1098 * The caller is responsible for checking privilege if the call is the result
1099 * of a WRMSR instruction. We'll do the rest.
1100 *
1101 * @retval VINF_SUCCESS on success.
1102 * @retval VERR_CPUM_RAISE_GP_0 on failure, the caller is expected to take the
1103 * appropriate actions.
1104 *
1105 * @param pVCpu Pointer to the VMCPU.
1106 * @param idMsr The MSR id.
1107 * @param uValue The value to set.
1108 *
1109 * @remarks Everyone changing MSR values, including the recompiler, shall do it
1110 * by calling this method. This makes sure we have current values and
1111 * that we trigger all the right actions when something changes.
1112 */
1113VMMDECL(int) CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue)
1114{
1115 /*
1116 * If we don't indicate MSR support in the CPUID feature bits, indicate
1117 * that a #GP(0) should be raised.
1118 */
1119 if (!(pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_MSR))
1120 return VERR_CPUM_RAISE_GP_0; /** @todo isn't \#UD more correct if not supported? */
1121
1122 int rc = VINF_SUCCESS;
1123 switch (idMsr)
1124 {
1125 case MSR_IA32_MISC_ENABLE:
1126 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = uValue;
1127 break;
1128
1129 case MSR_IA32_TSC:
1130 TMCpuTickSet(pVCpu->CTX_SUFF(pVM), pVCpu, uValue);
1131 break;
1132
1133 case MSR_IA32_APICBASE:
1134 rc = PDMApicSetBase(pVCpu, uValue);
1135 if (rc != VINF_SUCCESS)
1136 rc = VERR_CPUM_RAISE_GP_0;
1137 break;
1138
1139 case MSR_IA32_CR_PAT:
1140 pVCpu->cpum.s.Guest.msrPAT = uValue;
1141 break;
1142
1143 case MSR_IA32_SYSENTER_CS:
1144 pVCpu->cpum.s.Guest.SysEnter.cs = uValue & 0xffff; /* 16 bits selector */
1145 break;
1146
1147 case MSR_IA32_SYSENTER_EIP:
1148 pVCpu->cpum.s.Guest.SysEnter.eip = uValue;
1149 break;
1150
1151 case MSR_IA32_SYSENTER_ESP:
1152 pVCpu->cpum.s.Guest.SysEnter.esp = uValue;
1153 break;
1154
1155 case MSR_IA32_MTRR_CAP:
1156 return VERR_CPUM_RAISE_GP_0;
1157
1158 case MSR_IA32_MTRR_DEF_TYPE:
1159 if ( (uValue & UINT64_C(0xfffffffffffff300))
1160 || ( (uValue & 0xff) != 0
1161 && (uValue & 0xff) != 1
1162 && (uValue & 0xff) != 4
1163 && (uValue & 0xff) != 5
1164 && (uValue & 0xff) != 6) )
1165 {
1166 Log(("MSR_IA32_MTRR_DEF_TYPE: #GP(0) - writing reserved value (%#llx)\n", uValue));
1167 return VERR_CPUM_RAISE_GP_0;
1168 }
1169 pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType = uValue;
1170 break;
1171
1172 case IA32_MTRR_FIX64K_00000:
1173 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000 = uValue;
1174 break;
1175 case IA32_MTRR_FIX16K_80000:
1176 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000 = uValue;
1177 break;
1178 case IA32_MTRR_FIX16K_A0000:
1179 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000 = uValue;
1180 break;
1181 case IA32_MTRR_FIX4K_C0000:
1182 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000 = uValue;
1183 break;
1184 case IA32_MTRR_FIX4K_C8000:
1185 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000 = uValue;
1186 break;
1187 case IA32_MTRR_FIX4K_D0000:
1188 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000 = uValue;
1189 break;
1190 case IA32_MTRR_FIX4K_D8000:
1191 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000 = uValue;
1192 break;
1193 case IA32_MTRR_FIX4K_E0000:
1194 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000 = uValue;
1195 break;
1196 case IA32_MTRR_FIX4K_E8000:
1197 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000 = uValue;
1198 break;
1199 case IA32_MTRR_FIX4K_F0000:
1200 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000 = uValue;
1201 break;
1202 case IA32_MTRR_FIX4K_F8000:
1203 pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000 = uValue;
1204 break;
1205
1206 /*
1207 * AMD64 MSRs.
1208 */
1209 case MSR_K6_EFER:
1210 {
1211 PVM pVM = pVCpu->CTX_SUFF(pVM);
1212 uint64_t const uOldEFER = pVCpu->cpum.s.Guest.msrEFER;
1213 uint32_t const fExtFeatures = pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1214 ? pVM->cpum.s.aGuestCpuIdExt[1].edx
1215 : 0;
1216 uint64_t fMask = 0;
1217
1218 /* Filter out those bits the guest is allowed to change. (e.g. LMA is read-only) */
1219 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_NX)
1220 fMask |= MSR_K6_EFER_NXE;
1221 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1222 fMask |= MSR_K6_EFER_LME;
1223 if (fExtFeatures & X86_CPUID_EXT_FEATURE_EDX_SYSCALL)
1224 fMask |= MSR_K6_EFER_SCE;
1225 if (fExtFeatures & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1226 fMask |= MSR_K6_EFER_FFXSR;
1227
1228 /* Check for illegal MSR_K6_EFER_LME transitions: not allowed to change LME if
1229 paging is enabled. (AMD Arch. Programmer's Manual Volume 2: Table 14-5) */
1230 if ( (uOldEFER & MSR_K6_EFER_LME) != (uValue & fMask & MSR_K6_EFER_LME)
1231 && (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG))
1232 {
1233 Log(("Illegal MSR_K6_EFER_LME change: paging is enabled!!\n"));
1234 return VERR_CPUM_RAISE_GP_0;
1235 }
1236
1237 /* There are a few more: e.g. MSR_K6_EFER_LMSLE */
1238 AssertMsg(!(uValue & ~(MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA /* ignored anyway */ | MSR_K6_EFER_SCE | MSR_K6_EFER_FFXSR)),
1239 ("Unexpected value %RX64\n", uValue));
1240 pVCpu->cpum.s.Guest.msrEFER = (uOldEFER & ~fMask) | (uValue & fMask);
1241
1242 /* AMD64 Architecture Programmer's Manual: 15.15 TLB Control; flush the TLB
1243 if MSR_K6_EFER_NXE, MSR_K6_EFER_LME or MSR_K6_EFER_LMA are changed. */
1244 if ( (uOldEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA))
1245 != (pVCpu->cpum.s.Guest.msrEFER & (MSR_K6_EFER_NXE | MSR_K6_EFER_LME | MSR_K6_EFER_LMA)))
1246 {
1247 /// @todo PGMFlushTLB(pVCpu, cr3, true /*fGlobal*/);
1248 HMFlushTLB(pVCpu);
1249
1250 /* Notify PGM about NXE changes. */
1251 if ( (uOldEFER & MSR_K6_EFER_NXE)
1252 != (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE))
1253 PGMNotifyNxeChanged(pVCpu, !(uOldEFER & MSR_K6_EFER_NXE));
1254 }
1255 break;
1256 }
1257
1258 case MSR_K8_SF_MASK:
1259 pVCpu->cpum.s.Guest.msrSFMASK = uValue;
1260 break;
1261
1262 case MSR_K6_STAR:
1263 pVCpu->cpum.s.Guest.msrSTAR = uValue;
1264 break;
1265
1266 case MSR_K8_LSTAR:
1267 pVCpu->cpum.s.Guest.msrLSTAR = uValue;
1268 break;
1269
1270 case MSR_K8_CSTAR:
1271 pVCpu->cpum.s.Guest.msrCSTAR = uValue;
1272 break;
1273
1274 case MSR_K8_FS_BASE:
1275 pVCpu->cpum.s.Guest.fs.u64Base = uValue;
1276 break;
1277
1278 case MSR_K8_GS_BASE:
1279 pVCpu->cpum.s.Guest.gs.u64Base = uValue;
1280 break;
1281
1282 case MSR_K8_KERNEL_GS_BASE:
1283 pVCpu->cpum.s.Guest.msrKERNELGSBASE = uValue;
1284 break;
1285
1286 case MSR_K8_TSC_AUX:
1287 pVCpu->cpum.s.GuestMsrs.msr.TscAux = uValue;
1288 break;
1289
1290 /*
1291 * Intel specifics MSRs:
1292 */
1293 /*case MSR_IA32_PLATFORM_ID: - read-only */
1294 case MSR_IA32_BIOS_SIGN_ID: /* fam/mod >= 6_01 */
1295 case MSR_IA32_BIOS_UPDT_TRIG: /* fam/mod >= 6_01 */
1296 /*case MSR_IA32_MCP_CAP: - read-only */
1297 /*case MSR_IA32_MCP_STATUS: - read-only */
1298 /*case MSR_IA32_MCP_CTRL: - indicated as not present in CAP */
1299 /*case MSR_IA32_MC0_CTL: - read-only? */
1300 /*case MSR_IA32_MC0_STATUS: - read-only? */
1301 if (CPUMGetGuestCpuVendor(pVCpu->CTX_SUFF(pVM)) != CPUMCPUVENDOR_INTEL)
1302 {
1303 Log(("MSR %#x is Intel, the virtual CPU isn't an Intel one -> #GP\n", idMsr));
1304 return VERR_CPUM_RAISE_GP_0;
1305 }
1306 /* ignored */
1307 break;
1308
1309 default:
1310 /*
1311 * Hand the X2APIC range to PDM and the APIC.
1312 */
1313 if ( idMsr >= MSR_IA32_APIC_START
1314 && idMsr < MSR_IA32_APIC_END)
1315 {
1316 rc = PDMApicWriteMSR(pVCpu->CTX_SUFF(pVM), pVCpu->idCpu, idMsr, uValue);
1317 if (rc != VINF_SUCCESS)
1318 rc = VERR_CPUM_RAISE_GP_0;
1319 }
1320 else
1321 {
1322 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */
1323 /** @todo rc = VERR_CPUM_RAISE_GP_0 */
1324 Log(("CPUMSetGuestMsr: Unknown MSR %#x attempted set to %#llx\n", idMsr, uValue));
1325 }
1326 break;
1327 }
1328 return rc;
1329}
1330
1331
1332VMMDECL(RTGCPTR) CPUMGetGuestIDTR(PVMCPU pVCpu, uint16_t *pcbLimit)
1333{
1334 if (pcbLimit)
1335 *pcbLimit = pVCpu->cpum.s.Guest.idtr.cbIdt;
1336 return pVCpu->cpum.s.Guest.idtr.pIdt;
1337}
1338
1339
1340VMMDECL(RTSEL) CPUMGetGuestTR(PVMCPU pVCpu, PCPUMSELREGHID pHidden)
1341{
1342 if (pHidden)
1343 *pHidden = pVCpu->cpum.s.Guest.tr;
1344 return pVCpu->cpum.s.Guest.tr.Sel;
1345}
1346
1347
1348VMMDECL(RTSEL) CPUMGetGuestCS(PVMCPU pVCpu)
1349{
1350 return pVCpu->cpum.s.Guest.cs.Sel;
1351}
1352
1353
1354VMMDECL(RTSEL) CPUMGetGuestDS(PVMCPU pVCpu)
1355{
1356 return pVCpu->cpum.s.Guest.ds.Sel;
1357}
1358
1359
1360VMMDECL(RTSEL) CPUMGetGuestES(PVMCPU pVCpu)
1361{
1362 return pVCpu->cpum.s.Guest.es.Sel;
1363}
1364
1365
1366VMMDECL(RTSEL) CPUMGetGuestFS(PVMCPU pVCpu)
1367{
1368 return pVCpu->cpum.s.Guest.fs.Sel;
1369}
1370
1371
1372VMMDECL(RTSEL) CPUMGetGuestGS(PVMCPU pVCpu)
1373{
1374 return pVCpu->cpum.s.Guest.gs.Sel;
1375}
1376
1377
1378VMMDECL(RTSEL) CPUMGetGuestSS(PVMCPU pVCpu)
1379{
1380 return pVCpu->cpum.s.Guest.ss.Sel;
1381}
1382
1383
1384VMMDECL(RTSEL) CPUMGetGuestLDTR(PVMCPU pVCpu)
1385{
1386 return pVCpu->cpum.s.Guest.ldtr.Sel;
1387}
1388
1389
1390VMMDECL(RTSEL) CPUMGetGuestLdtrEx(PVMCPU pVCpu, uint64_t *pGCPtrBase, uint32_t *pcbLimit)
1391{
1392 *pGCPtrBase = pVCpu->cpum.s.Guest.ldtr.u64Base;
1393 *pcbLimit = pVCpu->cpum.s.Guest.ldtr.u32Limit;
1394 return pVCpu->cpum.s.Guest.ldtr.Sel;
1395}
1396
1397
1398VMMDECL(uint64_t) CPUMGetGuestCR0(PVMCPU pVCpu)
1399{
1400 return pVCpu->cpum.s.Guest.cr0;
1401}
1402
1403
1404VMMDECL(uint64_t) CPUMGetGuestCR2(PVMCPU pVCpu)
1405{
1406 return pVCpu->cpum.s.Guest.cr2;
1407}
1408
1409
1410VMMDECL(uint64_t) CPUMGetGuestCR3(PVMCPU pVCpu)
1411{
1412 return pVCpu->cpum.s.Guest.cr3;
1413}
1414
1415
1416VMMDECL(uint64_t) CPUMGetGuestCR4(PVMCPU pVCpu)
1417{
1418 return pVCpu->cpum.s.Guest.cr4;
1419}
1420
1421
1422VMMDECL(uint64_t) CPUMGetGuestCR8(PVMCPU pVCpu)
1423{
1424 uint64_t u64;
1425 int rc = CPUMGetGuestCRx(pVCpu, DISCREG_CR8, &u64);
1426 if (RT_FAILURE(rc))
1427 u64 = 0;
1428 return u64;
1429}
1430
1431
1432VMMDECL(void) CPUMGetGuestGDTR(PVMCPU pVCpu, PVBOXGDTR pGDTR)
1433{
1434 *pGDTR = pVCpu->cpum.s.Guest.gdtr;
1435}
1436
1437
1438VMMDECL(uint32_t) CPUMGetGuestEIP(PVMCPU pVCpu)
1439{
1440 return pVCpu->cpum.s.Guest.eip;
1441}
1442
1443
1444VMMDECL(uint64_t) CPUMGetGuestRIP(PVMCPU pVCpu)
1445{
1446 return pVCpu->cpum.s.Guest.rip;
1447}
1448
1449
1450VMMDECL(uint32_t) CPUMGetGuestEAX(PVMCPU pVCpu)
1451{
1452 return pVCpu->cpum.s.Guest.eax;
1453}
1454
1455
1456VMMDECL(uint32_t) CPUMGetGuestEBX(PVMCPU pVCpu)
1457{
1458 return pVCpu->cpum.s.Guest.ebx;
1459}
1460
1461
1462VMMDECL(uint32_t) CPUMGetGuestECX(PVMCPU pVCpu)
1463{
1464 return pVCpu->cpum.s.Guest.ecx;
1465}
1466
1467
1468VMMDECL(uint32_t) CPUMGetGuestEDX(PVMCPU pVCpu)
1469{
1470 return pVCpu->cpum.s.Guest.edx;
1471}
1472
1473
1474VMMDECL(uint32_t) CPUMGetGuestESI(PVMCPU pVCpu)
1475{
1476 return pVCpu->cpum.s.Guest.esi;
1477}
1478
1479
1480VMMDECL(uint32_t) CPUMGetGuestEDI(PVMCPU pVCpu)
1481{
1482 return pVCpu->cpum.s.Guest.edi;
1483}
1484
1485
1486VMMDECL(uint32_t) CPUMGetGuestESP(PVMCPU pVCpu)
1487{
1488 return pVCpu->cpum.s.Guest.esp;
1489}
1490
1491
1492VMMDECL(uint32_t) CPUMGetGuestEBP(PVMCPU pVCpu)
1493{
1494 return pVCpu->cpum.s.Guest.ebp;
1495}
1496
1497
1498VMMDECL(uint32_t) CPUMGetGuestEFlags(PVMCPU pVCpu)
1499{
1500 return pVCpu->cpum.s.Guest.eflags.u32;
1501}
1502
1503
1504VMMDECL(int) CPUMGetGuestCRx(PVMCPU pVCpu, unsigned iReg, uint64_t *pValue)
1505{
1506 switch (iReg)
1507 {
1508 case DISCREG_CR0:
1509 *pValue = pVCpu->cpum.s.Guest.cr0;
1510 break;
1511
1512 case DISCREG_CR2:
1513 *pValue = pVCpu->cpum.s.Guest.cr2;
1514 break;
1515
1516 case DISCREG_CR3:
1517 *pValue = pVCpu->cpum.s.Guest.cr3;
1518 break;
1519
1520 case DISCREG_CR4:
1521 *pValue = pVCpu->cpum.s.Guest.cr4;
1522 break;
1523
1524 case DISCREG_CR8:
1525 {
1526 uint8_t u8Tpr;
1527 int rc = PDMApicGetTPR(pVCpu, &u8Tpr, NULL /*pfPending*/);
1528 if (RT_FAILURE(rc))
1529 {
1530 AssertMsg(rc == VERR_PDM_NO_APIC_INSTANCE, ("%Rrc\n", rc));
1531 *pValue = 0;
1532 return rc;
1533 }
1534 *pValue = u8Tpr >> 4; /* bits 7-4 contain the task priority that go in cr8, bits 3-0*/
1535 break;
1536 }
1537
1538 default:
1539 return VERR_INVALID_PARAMETER;
1540 }
1541 return VINF_SUCCESS;
1542}
1543
1544
1545VMMDECL(uint64_t) CPUMGetGuestDR0(PVMCPU pVCpu)
1546{
1547 return pVCpu->cpum.s.Guest.dr[0];
1548}
1549
1550
1551VMMDECL(uint64_t) CPUMGetGuestDR1(PVMCPU pVCpu)
1552{
1553 return pVCpu->cpum.s.Guest.dr[1];
1554}
1555
1556
1557VMMDECL(uint64_t) CPUMGetGuestDR2(PVMCPU pVCpu)
1558{
1559 return pVCpu->cpum.s.Guest.dr[2];
1560}
1561
1562
1563VMMDECL(uint64_t) CPUMGetGuestDR3(PVMCPU pVCpu)
1564{
1565 return pVCpu->cpum.s.Guest.dr[3];
1566}
1567
1568
1569VMMDECL(uint64_t) CPUMGetGuestDR6(PVMCPU pVCpu)
1570{
1571 return pVCpu->cpum.s.Guest.dr[6];
1572}
1573
1574
1575VMMDECL(uint64_t) CPUMGetGuestDR7(PVMCPU pVCpu)
1576{
1577 return pVCpu->cpum.s.Guest.dr[7];
1578}
1579
1580
1581VMMDECL(int) CPUMGetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t *pValue)
1582{
1583 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
1584 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
1585 if (iReg == 4 || iReg == 5)
1586 iReg += 2;
1587 *pValue = pVCpu->cpum.s.Guest.dr[iReg];
1588 return VINF_SUCCESS;
1589}
1590
1591
1592VMMDECL(uint64_t) CPUMGetGuestEFER(PVMCPU pVCpu)
1593{
1594 return pVCpu->cpum.s.Guest.msrEFER;
1595}
1596
1597
1598/**
1599 * Gets a CPUID leaf.
1600 *
1601 * @param pVCpu Pointer to the VMCPU.
1602 * @param iLeaf The CPUID leaf to get.
1603 * @param pEax Where to store the EAX value.
1604 * @param pEbx Where to store the EBX value.
1605 * @param pEcx Where to store the ECX value.
1606 * @param pEdx Where to store the EDX value.
1607 */
1608VMMDECL(void) CPUMGetGuestCpuId(PVMCPU pVCpu, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
1609{
1610 PVM pVM = pVCpu->CTX_SUFF(pVM);
1611
1612 PCCPUMCPUID pCpuId;
1613 if (iLeaf < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
1614 pCpuId = &pVM->cpum.s.aGuestCpuIdStd[iLeaf];
1615 else if (iLeaf - UINT32_C(0x80000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
1616 pCpuId = &pVM->cpum.s.aGuestCpuIdExt[iLeaf - UINT32_C(0x80000000)];
1617 else if ( iLeaf - UINT32_C(0x40000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdHyper)
1618 && (pVCpu->CTX_SUFF(pVM)->cpum.s.aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_HVP))
1619 pCpuId = &pVM->cpum.s.aGuestCpuIdHyper[iLeaf - UINT32_C(0x40000000)]; /* Only report if HVP bit set. */
1620 else if (iLeaf - UINT32_C(0xc0000000) < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
1621 pCpuId = &pVM->cpum.s.aGuestCpuIdCentaur[iLeaf - UINT32_C(0xc0000000)];
1622 else
1623 pCpuId = &pVM->cpum.s.GuestCpuIdDef;
1624
1625 uint32_t cCurrentCacheIndex = *pEcx;
1626
1627 *pEax = pCpuId->eax;
1628 *pEbx = pCpuId->ebx;
1629 *pEcx = pCpuId->ecx;
1630 *pEdx = pCpuId->edx;
1631
1632 if ( iLeaf == 1)
1633 {
1634 /* Bits 31-24: Initial APIC ID */
1635 Assert(pVCpu->idCpu <= 255);
1636 *pEbx |= (pVCpu->idCpu << 24);
1637 }
1638
1639 if ( iLeaf == 4
1640 && cCurrentCacheIndex < 3
1641 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1642 {
1643 uint32_t type, level, sharing, linesize,
1644 partitions, associativity, sets, cores;
1645
1646 /* For type: 1 - data cache, 2 - i-cache, 3 - unified */
1647 partitions = 1;
1648 /* Those are only to shut up compiler, as they will always
1649 get overwritten, and compiler should be able to figure that out */
1650 sets = associativity = sharing = level = 1;
1651 cores = pVM->cCpus > 32 ? 32 : pVM->cCpus;
1652 switch (cCurrentCacheIndex)
1653 {
1654 case 0:
1655 type = 1;
1656 level = 1;
1657 sharing = 1;
1658 linesize = 64;
1659 associativity = 8;
1660 sets = 64;
1661 break;
1662 case 1:
1663 level = 1;
1664 type = 2;
1665 sharing = 1;
1666 linesize = 64;
1667 associativity = 8;
1668 sets = 64;
1669 break;
1670 default: /* shut up gcc.*/
1671 AssertFailed();
1672 case 2:
1673 level = 2;
1674 type = 3;
1675 sharing = cores; /* our L2 cache is modelled as shared between all cores */
1676 linesize = 64;
1677 associativity = 24;
1678 sets = 4096;
1679 break;
1680 }
1681
1682 *pEax |= ((cores - 1) << 26) |
1683 ((sharing - 1) << 14) |
1684 (level << 5) |
1685 1;
1686 *pEbx = (linesize - 1) |
1687 ((partitions - 1) << 12) |
1688 ((associativity - 1) << 22); /* -1 encoding */
1689 *pEcx = sets - 1;
1690 }
1691
1692 Log2(("CPUMGetGuestCpuId: iLeaf=%#010x %RX32 %RX32 %RX32 %RX32\n", iLeaf, *pEax, *pEbx, *pEcx, *pEdx));
1693}
1694
1695/**
1696 * Gets a number of standard CPUID leafs.
1697 *
1698 * @returns Number of leafs.
1699 * @param pVM Pointer to the VM.
1700 * @remark Intended for PATM.
1701 */
1702VMMDECL(uint32_t) CPUMGetGuestCpuIdStdMax(PVM pVM)
1703{
1704 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd);
1705}
1706
1707
1708/**
1709 * Gets a number of extended CPUID leafs.
1710 *
1711 * @returns Number of leafs.
1712 * @param pVM Pointer to the VM.
1713 * @remark Intended for PATM.
1714 */
1715VMMDECL(uint32_t) CPUMGetGuestCpuIdExtMax(PVM pVM)
1716{
1717 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt);
1718}
1719
1720
1721/**
1722 * Gets a number of centaur CPUID leafs.
1723 *
1724 * @returns Number of leafs.
1725 * @param pVM Pointer to the VM.
1726 * @remark Intended for PATM.
1727 */
1728VMMDECL(uint32_t) CPUMGetGuestCpuIdCentaurMax(PVM pVM)
1729{
1730 return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
1731}
1732
1733
1734/**
1735 * Sets a CPUID feature bit.
1736 *
1737 * @param pVM Pointer to the VM.
1738 * @param enmFeature The feature to set.
1739 */
1740VMMDECL(void) CPUMSetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1741{
1742 switch (enmFeature)
1743 {
1744 /*
1745 * Set the APIC bit in both feature masks.
1746 */
1747 case CPUMCPUIDFEATURE_APIC:
1748 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1749 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_APIC;
1750 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1751 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1752 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_APIC;
1753 LogRel(("CPUMSetGuestCpuIdFeature: Enabled APIC\n"));
1754 break;
1755
1756 /*
1757 * Set the x2APIC bit in the standard feature mask.
1758 */
1759 case CPUMCPUIDFEATURE_X2APIC:
1760 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1761 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_X2APIC;
1762 LogRel(("CPUMSetGuestCpuIdFeature: Enabled x2APIC\n"));
1763 break;
1764
1765 /*
1766 * Set the sysenter/sysexit bit in the standard feature mask.
1767 * Assumes the caller knows what it's doing! (host must support these)
1768 */
1769 case CPUMCPUIDFEATURE_SEP:
1770 {
1771 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_SEP))
1772 {
1773 AssertMsgFailed(("ERROR: Can't turn on SEP when the host doesn't support it!!\n"));
1774 return;
1775 }
1776
1777 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1778 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_SEP;
1779 LogRel(("CPUMSetGuestCpuIdFeature: Enabled sysenter/exit\n"));
1780 break;
1781 }
1782
1783 /*
1784 * Set the syscall/sysret bit in the extended feature mask.
1785 * Assumes the caller knows what it's doing! (host must support these)
1786 */
1787 case CPUMCPUIDFEATURE_SYSCALL:
1788 {
1789 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1790 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1791 {
1792#if HC_ARCH_BITS == 32
1793 /* X86_CPUID_EXT_FEATURE_EDX_SYSCALL not set it seems in 32 bits mode.
1794 * Even when the cpu is capable of doing so in 64 bits mode.
1795 */
1796 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1797 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE)
1798 || !(ASMCpuId_EDX(1) & X86_CPUID_EXT_FEATURE_EDX_SYSCALL))
1799#endif
1800 {
1801 LogRel(("WARNING: Can't turn on SYSCALL/SYSRET when the host doesn't support it!!\n"));
1802 return;
1803 }
1804 }
1805 /* Valid for both Intel and AMD CPUs, although only in 64 bits mode for Intel. */
1806 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_SYSCALL;
1807 LogRel(("CPUMSetGuestCpuIdFeature: Enabled syscall/ret\n"));
1808 break;
1809 }
1810
1811 /*
1812 * Set the PAE bit in both feature masks.
1813 * Assumes the caller knows what it's doing! (host must support these)
1814 */
1815 case CPUMCPUIDFEATURE_PAE:
1816 {
1817 if (!(ASMCpuId_EDX(1) & X86_CPUID_FEATURE_EDX_PAE))
1818 {
1819 LogRel(("WARNING: Can't turn on PAE when the host doesn't support it!!\n"));
1820 return;
1821 }
1822
1823 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1824 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAE;
1825 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1826 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1827 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAE;
1828 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAE\n"));
1829 break;
1830 }
1831
1832 /*
1833 * Set the LONG MODE bit in the extended feature mask.
1834 * Assumes the caller knows what it's doing! (host must support these)
1835 */
1836 case CPUMCPUIDFEATURE_LONG_MODE:
1837 {
1838 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1839 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1840 {
1841 LogRel(("WARNING: Can't turn on LONG MODE when the host doesn't support it!!\n"));
1842 return;
1843 }
1844
1845 /* Valid for both Intel and AMD. */
1846 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
1847 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LONG MODE\n"));
1848 break;
1849 }
1850
1851 /*
1852 * Set the NX/XD bit in the extended feature mask.
1853 * Assumes the caller knows what it's doing! (host must support these)
1854 */
1855 case CPUMCPUIDFEATURE_NX:
1856 {
1857 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1858 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_NX))
1859 {
1860 LogRel(("WARNING: Can't turn on NX/XD when the host doesn't support it!!\n"));
1861 return;
1862 }
1863
1864 /* Valid for both Intel and AMD. */
1865 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_NX;
1866 LogRel(("CPUMSetGuestCpuIdFeature: Enabled NX\n"));
1867 break;
1868 }
1869
1870 /*
1871 * Set the LAHF/SAHF support in 64-bit mode.
1872 * Assumes the caller knows what it's doing! (host must support this)
1873 */
1874 case CPUMCPUIDFEATURE_LAHF:
1875 {
1876 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1877 || !(ASMCpuId_ECX(0x80000001) & X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF))
1878 {
1879 LogRel(("WARNING: Can't turn on LAHF/SAHF when the host doesn't support it!!\n"));
1880 return;
1881 }
1882
1883 /* Valid for both Intel and AMD. */
1884 pVM->cpum.s.aGuestCpuIdExt[1].ecx |= X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
1885 LogRel(("CPUMSetGuestCpuIdFeature: Enabled LAHF/SAHF\n"));
1886 break;
1887 }
1888
1889 case CPUMCPUIDFEATURE_PAT:
1890 {
1891 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1892 pVM->cpum.s.aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_PAT;
1893 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
1894 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1895 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_AMD_FEATURE_EDX_PAT;
1896 LogRel(("CPUMSetGuestCpuIdFeature: Enabled PAT\n"));
1897 break;
1898 }
1899
1900 /*
1901 * Set the RDTSCP support bit.
1902 * Assumes the caller knows what it's doing! (host must support this)
1903 */
1904 case CPUMCPUIDFEATURE_RDTSCP:
1905 {
1906 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax < 0x80000001
1907 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_RDTSCP)
1908 || pVM->cpum.s.u8PortableCpuIdLevel > 0)
1909 {
1910 if (!pVM->cpum.s.u8PortableCpuIdLevel)
1911 LogRel(("WARNING: Can't turn on RDTSCP when the host doesn't support it!!\n"));
1912 return;
1913 }
1914
1915 /* Valid for both Intel and AMD. */
1916 pVM->cpum.s.aGuestCpuIdExt[1].edx |= X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
1917 LogRel(("CPUMSetGuestCpuIdFeature: Enabled RDTSCP.\n"));
1918 break;
1919 }
1920
1921 /*
1922 * Set the Hypervisor Present bit in the standard feature mask.
1923 */
1924 case CPUMCPUIDFEATURE_HVP:
1925 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1926 pVM->cpum.s.aGuestCpuIdStd[1].ecx |= X86_CPUID_FEATURE_ECX_HVP;
1927 LogRel(("CPUMSetGuestCpuIdFeature: Enabled Hypervisor Present bit\n"));
1928 break;
1929
1930 default:
1931 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1932 break;
1933 }
1934 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1935 {
1936 PVMCPU pVCpu = &pVM->aCpus[i];
1937 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
1938 }
1939}
1940
1941
1942/**
1943 * Queries a CPUID feature bit.
1944 *
1945 * @returns boolean for feature presence
1946 * @param pVM Pointer to the VM.
1947 * @param enmFeature The feature to query.
1948 */
1949VMMDECL(bool) CPUMGetGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1950{
1951 switch (enmFeature)
1952 {
1953 case CPUMCPUIDFEATURE_PAE:
1954 {
1955 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
1956 return !!(pVM->cpum.s.aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PAE);
1957 break;
1958 }
1959
1960 case CPUMCPUIDFEATURE_NX:
1961 {
1962 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1963 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_NX);
1964 }
1965
1966 case CPUMCPUIDFEATURE_RDTSCP:
1967 {
1968 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1969 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1970 break;
1971 }
1972
1973 case CPUMCPUIDFEATURE_LONG_MODE:
1974 {
1975 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
1976 return !!(pVM->cpum.s.aGuestCpuIdExt[1].edx & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
1977 break;
1978 }
1979
1980 default:
1981 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
1982 break;
1983 }
1984 return false;
1985}
1986
1987
1988/**
1989 * Clears a CPUID feature bit.
1990 *
1991 * @param pVM Pointer to the VM.
1992 * @param enmFeature The feature to clear.
1993 */
1994VMMDECL(void) CPUMClearGuestCpuIdFeature(PVM pVM, CPUMCPUIDFEATURE enmFeature)
1995{
1996 switch (enmFeature)
1997 {
1998 /*
1999 * Set the APIC bit in both feature masks.
2000 */
2001 case CPUMCPUIDFEATURE_APIC:
2002 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2003 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_APIC;
2004 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2005 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2006 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_APIC;
2007 Log(("CPUMClearGuestCpuIdFeature: Disabled APIC\n"));
2008 break;
2009
2010 /*
2011 * Clear the x2APIC bit in the standard feature mask.
2012 */
2013 case CPUMCPUIDFEATURE_X2APIC:
2014 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2015 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_X2APIC;
2016 LogRel(("CPUMClearGuestCpuIdFeature: Disabled x2APIC\n"));
2017 break;
2018
2019 case CPUMCPUIDFEATURE_PAE:
2020 {
2021 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2022 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAE;
2023 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2024 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2025 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAE;
2026 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAE!\n"));
2027 break;
2028 }
2029
2030 case CPUMCPUIDFEATURE_PAT:
2031 {
2032 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2033 pVM->cpum.s.aGuestCpuIdStd[1].edx &= ~X86_CPUID_FEATURE_EDX_PAT;
2034 if ( pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001
2035 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
2036 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_AMD_FEATURE_EDX_PAT;
2037 LogRel(("CPUMClearGuestCpuIdFeature: Disabled PAT!\n"));
2038 break;
2039 }
2040
2041 case CPUMCPUIDFEATURE_LONG_MODE:
2042 {
2043 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2044 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_LONG_MODE;
2045 break;
2046 }
2047
2048 case CPUMCPUIDFEATURE_LAHF:
2049 {
2050 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2051 pVM->cpum.s.aGuestCpuIdExt[1].ecx &= ~X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF;
2052 break;
2053 }
2054
2055 case CPUMCPUIDFEATURE_RDTSCP:
2056 {
2057 if (pVM->cpum.s.aGuestCpuIdExt[0].eax >= 0x80000001)
2058 pVM->cpum.s.aGuestCpuIdExt[1].edx &= ~X86_CPUID_EXT_FEATURE_EDX_RDTSCP;
2059 LogRel(("CPUMClearGuestCpuIdFeature: Disabled RDTSCP!\n"));
2060 break;
2061 }
2062
2063 case CPUMCPUIDFEATURE_HVP:
2064 if (pVM->cpum.s.aGuestCpuIdStd[0].eax >= 1)
2065 pVM->cpum.s.aGuestCpuIdStd[1].ecx &= ~X86_CPUID_FEATURE_ECX_HVP;
2066 break;
2067
2068 default:
2069 AssertMsgFailed(("enmFeature=%d\n", enmFeature));
2070 break;
2071 }
2072 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2073 {
2074 PVMCPU pVCpu = &pVM->aCpus[i];
2075 pVCpu->cpum.s.fChanged |= CPUM_CHANGED_CPUID;
2076 }
2077}
2078
2079
2080/**
2081 * Gets the host CPU vendor.
2082 *
2083 * @returns CPU vendor.
2084 * @param pVM Pointer to the VM.
2085 */
2086VMMDECL(CPUMCPUVENDOR) CPUMGetHostCpuVendor(PVM pVM)
2087{
2088 return pVM->cpum.s.enmHostCpuVendor;
2089}
2090
2091
2092/**
2093 * Gets the CPU vendor.
2094 *
2095 * @returns CPU vendor.
2096 * @param pVM Pointer to the VM.
2097 */
2098VMMDECL(CPUMCPUVENDOR) CPUMGetGuestCpuVendor(PVM pVM)
2099{
2100 return pVM->cpum.s.enmGuestCpuVendor;
2101}
2102
2103
2104VMMDECL(int) CPUMSetGuestDR0(PVMCPU pVCpu, uint64_t uDr0)
2105{
2106 pVCpu->cpum.s.Guest.dr[0] = uDr0;
2107 return CPUMRecalcHyperDRx(pVCpu);
2108}
2109
2110
2111VMMDECL(int) CPUMSetGuestDR1(PVMCPU pVCpu, uint64_t uDr1)
2112{
2113 pVCpu->cpum.s.Guest.dr[1] = uDr1;
2114 return CPUMRecalcHyperDRx(pVCpu);
2115}
2116
2117
2118VMMDECL(int) CPUMSetGuestDR2(PVMCPU pVCpu, uint64_t uDr2)
2119{
2120 pVCpu->cpum.s.Guest.dr[2] = uDr2;
2121 return CPUMRecalcHyperDRx(pVCpu);
2122}
2123
2124
2125VMMDECL(int) CPUMSetGuestDR3(PVMCPU pVCpu, uint64_t uDr3)
2126{
2127 pVCpu->cpum.s.Guest.dr[3] = uDr3;
2128 return CPUMRecalcHyperDRx(pVCpu);
2129}
2130
2131
2132VMMDECL(int) CPUMSetGuestDR6(PVMCPU pVCpu, uint64_t uDr6)
2133{
2134 pVCpu->cpum.s.Guest.dr[6] = uDr6;
2135 return CPUMRecalcHyperDRx(pVCpu);
2136}
2137
2138
2139VMMDECL(int) CPUMSetGuestDR7(PVMCPU pVCpu, uint64_t uDr7)
2140{
2141 pVCpu->cpum.s.Guest.dr[7] = uDr7;
2142 return CPUMRecalcHyperDRx(pVCpu);
2143}
2144
2145
2146VMMDECL(int) CPUMSetGuestDRx(PVMCPU pVCpu, uint32_t iReg, uint64_t Value)
2147{
2148 AssertReturn(iReg <= DISDREG_DR7, VERR_INVALID_PARAMETER);
2149 /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
2150 if (iReg == 4 || iReg == 5)
2151 iReg += 2;
2152 pVCpu->cpum.s.Guest.dr[iReg] = Value;
2153 return CPUMRecalcHyperDRx(pVCpu);
2154}
2155
2156
2157/**
2158 * Recalculates the hypervisor DRx register values based on
2159 * current guest registers and DBGF breakpoints.
2160 *
2161 * This is called whenever a guest DRx register is modified and when DBGF
2162 * sets a hardware breakpoint. In guest context this function will reload
2163 * any (hyper) DRx registers which comes out with a different value.
2164 *
2165 * @returns VINF_SUCCESS.
2166 * @param pVCpu Pointer to the VMCPU.
2167 */
2168VMMDECL(int) CPUMRecalcHyperDRx(PVMCPU pVCpu)
2169{
2170 PVM pVM = pVCpu->CTX_SUFF(pVM);
2171
2172 /*
2173 * Compare the DR7s first.
2174 *
2175 * We only care about the enabled flags. The GE and LE flags are always
2176 * set and we don't care if the guest doesn't set them. GD is virtualized
2177 * when we dispatch #DB, we never enable it.
2178 */
2179 const RTGCUINTREG uDbgfDr7 = DBGFBpGetDR7(pVM);
2180#ifdef CPUM_VIRTUALIZE_DRX
2181 const RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu);
2182#else
2183 const RTGCUINTREG uGstDr7 = 0;
2184#endif
2185 if ((uGstDr7 | uDbgfDr7) & X86_DR7_ENABLED_MASK)
2186 {
2187 /*
2188 * Ok, something is enabled. Recalc each of the breakpoints.
2189 * Straight forward code, not optimized/minimized in any way.
2190 */
2191 RTGCUINTREG uNewDr7 = X86_DR7_GE | X86_DR7_LE | X86_DR7_MB1_MASK;
2192
2193 /* bp 0 */
2194 RTGCUINTREG uNewDr0;
2195 if (uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0))
2196 {
2197 uNewDr7 |= uDbgfDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2198 uNewDr0 = DBGFBpGetDR0(pVM);
2199 }
2200 else if (uGstDr7 & (X86_DR7_L0 | X86_DR7_G0))
2201 {
2202 uNewDr7 |= uGstDr7 & (X86_DR7_L0 | X86_DR7_G0 | X86_DR7_RW0_MASK | X86_DR7_LEN0_MASK);
2203 uNewDr0 = CPUMGetGuestDR0(pVCpu);
2204 }
2205 else
2206 uNewDr0 = pVCpu->cpum.s.Hyper.dr[0];
2207
2208 /* bp 1 */
2209 RTGCUINTREG uNewDr1;
2210 if (uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1))
2211 {
2212 uNewDr7 |= uDbgfDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2213 uNewDr1 = DBGFBpGetDR1(pVM);
2214 }
2215 else if (uGstDr7 & (X86_DR7_L1 | X86_DR7_G1))
2216 {
2217 uNewDr7 |= uGstDr7 & (X86_DR7_L1 | X86_DR7_G1 | X86_DR7_RW1_MASK | X86_DR7_LEN1_MASK);
2218 uNewDr1 = CPUMGetGuestDR1(pVCpu);
2219 }
2220 else
2221 uNewDr1 = pVCpu->cpum.s.Hyper.dr[1];
2222
2223 /* bp 2 */
2224 RTGCUINTREG uNewDr2;
2225 if (uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2))
2226 {
2227 uNewDr7 |= uDbgfDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2228 uNewDr2 = DBGFBpGetDR2(pVM);
2229 }
2230 else if (uGstDr7 & (X86_DR7_L2 | X86_DR7_G2))
2231 {
2232 uNewDr7 |= uGstDr7 & (X86_DR7_L2 | X86_DR7_G2 | X86_DR7_RW2_MASK | X86_DR7_LEN2_MASK);
2233 uNewDr2 = CPUMGetGuestDR2(pVCpu);
2234 }
2235 else
2236 uNewDr2 = pVCpu->cpum.s.Hyper.dr[2];
2237
2238 /* bp 3 */
2239 RTGCUINTREG uNewDr3;
2240 if (uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3))
2241 {
2242 uNewDr7 |= uDbgfDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2243 uNewDr3 = DBGFBpGetDR3(pVM);
2244 }
2245 else if (uGstDr7 & (X86_DR7_L3 | X86_DR7_G3))
2246 {
2247 uNewDr7 |= uGstDr7 & (X86_DR7_L3 | X86_DR7_G3 | X86_DR7_RW3_MASK | X86_DR7_LEN3_MASK);
2248 uNewDr3 = CPUMGetGuestDR3(pVCpu);
2249 }
2250 else
2251 uNewDr3 = pVCpu->cpum.s.Hyper.dr[3];
2252
2253 /*
2254 * Apply the updates.
2255 */
2256#ifdef IN_RC
2257 if (!(pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS))
2258 {
2259 /** @todo save host DBx registers. */
2260 }
2261#endif
2262 /** @todo Should this not be setting CPUM_USE_DEBUG_REGS_HYPER?
2263 * (CPUM_VIRTUALIZE_DRX is never defined). */
2264 pVCpu->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
2265 if (uNewDr3 != pVCpu->cpum.s.Hyper.dr[3])
2266 CPUMSetHyperDR3(pVCpu, uNewDr3);
2267 if (uNewDr2 != pVCpu->cpum.s.Hyper.dr[2])
2268 CPUMSetHyperDR2(pVCpu, uNewDr2);
2269 if (uNewDr1 != pVCpu->cpum.s.Hyper.dr[1])
2270 CPUMSetHyperDR1(pVCpu, uNewDr1);
2271 if (uNewDr0 != pVCpu->cpum.s.Hyper.dr[0])
2272 CPUMSetHyperDR0(pVCpu, uNewDr0);
2273 if (uNewDr7 != pVCpu->cpum.s.Hyper.dr[7])
2274 CPUMSetHyperDR7(pVCpu, uNewDr7);
2275 }
2276 else
2277 {
2278#ifdef IN_RC
2279 if (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS)
2280 {
2281 /** @todo restore host DBx registers. */
2282 }
2283#endif
2284 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2285 }
2286 Log2(("CPUMRecalcHyperDRx: fUseFlags=%#x %RGr %RGr %RGr %RGr %RGr %RGr\n",
2287 pVCpu->cpum.s.fUseFlags, pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1],
2288 pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3], pVCpu->cpum.s.Hyper.dr[6],
2289 pVCpu->cpum.s.Hyper.dr[7]));
2290
2291 return VINF_SUCCESS;
2292}
2293
2294
2295/**
2296 * Tests if the guest has No-Execute Page Protection Enabled (NXE).
2297 *
2298 * @returns true if in real mode, otherwise false.
2299 * @param pVCpu Pointer to the VMCPU.
2300 */
2301VMMDECL(bool) CPUMIsGuestNXEnabled(PVMCPU pVCpu)
2302{
2303 return !!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE);
2304}
2305
2306
2307/**
2308 * Tests if the guest has the Page Size Extension enabled (PSE).
2309 *
2310 * @returns true if in real mode, otherwise false.
2311 * @param pVCpu Pointer to the VMCPU.
2312 */
2313VMMDECL(bool) CPUMIsGuestPageSizeExtEnabled(PVMCPU pVCpu)
2314{
2315 /* PAE or AMD64 implies support for big pages regardless of CR4.PSE */
2316 return !!(pVCpu->cpum.s.Guest.cr4 & (X86_CR4_PSE | X86_CR4_PAE));
2317}
2318
2319
2320/**
2321 * Tests if the guest has the paging enabled (PG).
2322 *
2323 * @returns true if in real mode, otherwise false.
2324 * @param pVCpu Pointer to the VMCPU.
2325 */
2326VMMDECL(bool) CPUMIsGuestPagingEnabled(PVMCPU pVCpu)
2327{
2328 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PG);
2329}
2330
2331
2332/**
2333 * Tests if the guest has the paging enabled (PG).
2334 *
2335 * @returns true if in real mode, otherwise false.
2336 * @param pVCpu Pointer to the VMCPU.
2337 */
2338VMMDECL(bool) CPUMIsGuestR0WriteProtEnabled(PVMCPU pVCpu)
2339{
2340 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_WP);
2341}
2342
2343
2344/**
2345 * Tests if the guest is running in real mode or not.
2346 *
2347 * @returns true if in real mode, otherwise false.
2348 * @param pVCpu Pointer to the VMCPU.
2349 */
2350VMMDECL(bool) CPUMIsGuestInRealMode(PVMCPU pVCpu)
2351{
2352 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2353}
2354
2355
2356/**
2357 * Tests if the guest is running in real or virtual 8086 mode.
2358 *
2359 * @returns @c true if it is, @c false if not.
2360 * @param pVCpu Pointer to the VMCPU.
2361 */
2362VMMDECL(bool) CPUMIsGuestInRealOrV86Mode(PVMCPU pVCpu)
2363{
2364 return !(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2365 || pVCpu->cpum.s.Guest.eflags.Bits.u1VM; /** @todo verify that this cannot be set in long mode. */
2366}
2367
2368
2369/**
2370 * Tests if the guest is running in protected or not.
2371 *
2372 * @returns true if in protected mode, otherwise false.
2373 * @param pVCpu Pointer to the VMCPU.
2374 */
2375VMMDECL(bool) CPUMIsGuestInProtectedMode(PVMCPU pVCpu)
2376{
2377 return !!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE);
2378}
2379
2380
2381/**
2382 * Tests if the guest is running in paged protected or not.
2383 *
2384 * @returns true if in paged protected mode, otherwise false.
2385 * @param pVCpu Pointer to the VMCPU.
2386 */
2387VMMDECL(bool) CPUMIsGuestInPagedProtectedMode(PVMCPU pVCpu)
2388{
2389 return (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG);
2390}
2391
2392
2393/**
2394 * Tests if the guest is running in long mode or not.
2395 *
2396 * @returns true if in long mode, otherwise false.
2397 * @param pVCpu Pointer to the VMCPU.
2398 */
2399VMMDECL(bool) CPUMIsGuestInLongMode(PVMCPU pVCpu)
2400{
2401 return (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
2402}
2403
2404
2405/**
2406 * Tests if the guest is running in PAE mode or not.
2407 *
2408 * @returns true if in PAE mode, otherwise false.
2409 * @param pVCpu Pointer to the VMCPU.
2410 */
2411VMMDECL(bool) CPUMIsGuestInPAEMode(PVMCPU pVCpu)
2412{
2413 return (pVCpu->cpum.s.Guest.cr4 & X86_CR4_PAE)
2414 && (pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PE | X86_CR0_PG)) == (X86_CR0_PE | X86_CR0_PG)
2415 && !(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA);
2416}
2417
2418
2419/**
2420 * Tests if the guest is running in 64 bits mode or not.
2421 *
2422 * @returns true if in 64 bits protected mode, otherwise false.
2423 * @param pVCpu The current virtual CPU.
2424 */
2425VMMDECL(bool) CPUMIsGuestIn64BitCode(PVMCPU pVCpu)
2426{
2427 if (!CPUMIsGuestInLongMode(pVCpu))
2428 return false;
2429 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2430 return pVCpu->cpum.s.Guest.cs.Attr.n.u1Long;
2431}
2432
2433
2434/**
2435 * Helper for CPUMIsGuestIn64BitCodeEx that handles lazy resolving of hidden CS
2436 * registers.
2437 *
2438 * @returns true if in 64 bits protected mode, otherwise false.
2439 * @param pCtx Pointer to the current guest CPU context.
2440 */
2441VMM_INT_DECL(bool) CPUMIsGuestIn64BitCodeSlow(PCPUMCTX pCtx)
2442{
2443 return CPUMIsGuestIn64BitCode(CPUM_GUEST_CTX_TO_VMCPU(pCtx));
2444}
2445
2446#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2447/**
2448 *
2449 * @returns @c true if we've entered raw-mode and selectors with RPL=1 are
2450 * really RPL=0, @c false if we've not (RPL=1 really is RPL=1).
2451 * @param pVCpu The current virtual CPU.
2452 */
2453VMM_INT_DECL(bool) CPUMIsGuestInRawMode(PVMCPU pVCpu)
2454{
2455 return pVCpu->cpum.s.fRawEntered;
2456}
2457#endif
2458
2459
2460/**
2461 * Updates the EFLAGS while we're in raw-mode.
2462 *
2463 * @param pVCpu Pointer to the VMCPU.
2464 * @param fEfl The new EFLAGS value.
2465 */
2466VMMDECL(void) CPUMRawSetEFlags(PVMCPU pVCpu, uint32_t fEfl)
2467{
2468#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2469 if (pVCpu->cpum.s.fRawEntered)
2470 PATMRawSetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest), fEfl);
2471 else
2472#endif
2473 pVCpu->cpum.s.Guest.eflags.u32 = fEfl;
2474}
2475
2476
2477/**
2478 * Gets the EFLAGS while we're in raw-mode.
2479 *
2480 * @returns The eflags.
2481 * @param pVCpu Pointer to the current virtual CPU.
2482 */
2483VMMDECL(uint32_t) CPUMRawGetEFlags(PVMCPU pVCpu)
2484{
2485#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2486 if (pVCpu->cpum.s.fRawEntered)
2487 return PATMRawGetEFlags(pVCpu->CTX_SUFF(pVM), CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
2488#endif
2489 return pVCpu->cpum.s.Guest.eflags.u32;
2490}
2491
2492
2493/**
2494 * Sets the specified changed flags (CPUM_CHANGED_*).
2495 *
2496 * @param pVCpu Pointer to the current virtual CPU.
2497 */
2498VMMDECL(void) CPUMSetChangedFlags(PVMCPU pVCpu, uint32_t fChangedFlags)
2499{
2500 pVCpu->cpum.s.fChanged |= fChangedFlags;
2501}
2502
2503
2504/**
2505 * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
2506 * @returns true if supported.
2507 * @returns false if not supported.
2508 * @param pVM Pointer to the VM.
2509 */
2510VMMDECL(bool) CPUMSupportsFXSR(PVM pVM)
2511{
2512 return pVM->cpum.s.CPUFeatures.edx.u1FXSR != 0;
2513}
2514
2515
2516/**
2517 * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
2518 * @returns true if used.
2519 * @returns false if not used.
2520 * @param pVM Pointer to the VM.
2521 */
2522VMMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM)
2523{
2524 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSENTER) != 0;
2525}
2526
2527
2528/**
2529 * Checks if the host OS uses the SYSCALL / SYSRET instructions.
2530 * @returns true if used.
2531 * @returns false if not used.
2532 * @param pVM Pointer to the VM.
2533 */
2534VMMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM)
2535{
2536 return (pVM->cpum.s.fHostUseFlags & CPUM_USE_SYSCALL) != 0;
2537}
2538
2539#ifndef IN_RING3
2540
2541/**
2542 * Lazily sync in the FPU/XMM state.
2543 *
2544 * @returns VBox status code.
2545 * @param pVCpu Pointer to the VMCPU.
2546 */
2547VMMDECL(int) CPUMHandleLazyFPU(PVMCPU pVCpu)
2548{
2549 return cpumHandleLazyFPUAsm(&pVCpu->cpum.s);
2550}
2551
2552#endif /* !IN_RING3 */
2553
2554/**
2555 * Checks if we activated the FPU/XMM state of the guest OS.
2556 * @returns true if we did.
2557 * @returns false if not.
2558 * @param pVCpu Pointer to the VMCPU.
2559 */
2560VMMDECL(bool) CPUMIsGuestFPUStateActive(PVMCPU pVCpu)
2561{
2562 return (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU) != 0;
2563}
2564
2565
2566/**
2567 * Deactivate the FPU/XMM state of the guest OS.
2568 * @param pVCpu Pointer to the VMCPU.
2569 */
2570VMMDECL(void) CPUMDeactivateGuestFPUState(PVMCPU pVCpu)
2571{
2572 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU;
2573}
2574
2575
2576/**
2577 * Checks if the guest debug state is active.
2578 *
2579 * @returns boolean
2580 * @param pVM Pointer to the VM.
2581 */
2582VMMDECL(bool) CPUMIsGuestDebugStateActive(PVMCPU pVCpu)
2583{
2584 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS) != 0;
2585}
2586
2587/**
2588 * Checks if the hyper debug state is active.
2589 *
2590 * @returns boolean
2591 * @param pVM Pointer to the VM.
2592 */
2593VMMDECL(bool) CPUMIsHyperDebugStateActive(PVMCPU pVCpu)
2594{
2595 return (pVCpu->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS_HYPER) != 0;
2596}
2597
2598
2599/**
2600 * Mark the guest's debug state as inactive.
2601 *
2602 * @returns boolean
2603 * @param pVM Pointer to the VM.
2604 */
2605VMMDECL(void) CPUMDeactivateGuestDebugState(PVMCPU pVCpu)
2606{
2607 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
2608}
2609
2610
2611/**
2612 * Mark the hypervisor's debug state as inactive.
2613 *
2614 * @returns boolean
2615 * @param pVM Pointer to the VM.
2616 */
2617VMMDECL(void) CPUMDeactivateHyperDebugState(PVMCPU pVCpu)
2618{
2619 pVCpu->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS_HYPER;
2620}
2621
2622
2623/**
2624 * Get the current privilege level of the guest.
2625 *
2626 * @returns CPL
2627 * @param pVCpu Pointer to the current virtual CPU.
2628 */
2629VMMDECL(uint32_t) CPUMGetGuestCPL(PVMCPU pVCpu)
2630{
2631 /*
2632 * CPL can reliably be found in SS.DPL (hidden regs valid) or SS if not.
2633 *
2634 * Note! We used to check CS.DPL here, assuming it was always equal to
2635 * CPL even if a conforming segment was loaded. But this truned out to
2636 * only apply to older AMD-V. With VT-x we had an ACP2 regression
2637 * during install after a far call to ring 2 with VT-x. Then on newer
2638 * AMD-V CPUs we have to move the VMCB.guest.u8CPL into cs.Attr.n.u2Dpl
2639 * as well as ss.Attr.n.u2Dpl to make this (and other) code work right.
2640 *
2641 * So, forget CS.DPL, always use SS.DPL.
2642 *
2643 * Note! The SS RPL is always equal to the CPL, while the CS RPL
2644 * isn't necessarily equal if the segment is conforming.
2645 * See section 4.11.1 in the AMD manual.
2646 */
2647 uint32_t uCpl;
2648 if (pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE)
2649 {
2650 if (!pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2651 {
2652 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pVCpu->cpum.s.Guest.ss))
2653 uCpl = pVCpu->cpum.s.Guest.ss.Attr.n.u2Dpl;
2654 else
2655 {
2656 uCpl = (pVCpu->cpum.s.Guest.ss.Sel & X86_SEL_RPL);
2657#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2658 if (uCpl == 1)
2659 uCpl = 0;
2660#endif
2661 }
2662 }
2663 else
2664 uCpl = 3; /* V86 has CPL=3; REM doesn't set DPL=3 in V8086 mode. See @bugref{5130}. */
2665 }
2666 else
2667 uCpl = 0; /* Real mode is zero; CPL set to 3 for VT-x real-mode emulation. */
2668 return uCpl;
2669}
2670
2671
2672/**
2673 * Gets the current guest CPU mode.
2674 *
2675 * If paging mode is what you need, check out PGMGetGuestMode().
2676 *
2677 * @returns The CPU mode.
2678 * @param pVCpu Pointer to the VMCPU.
2679 */
2680VMMDECL(CPUMMODE) CPUMGetGuestMode(PVMCPU pVCpu)
2681{
2682 CPUMMODE enmMode;
2683 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2684 enmMode = CPUMMODE_REAL;
2685 else if (!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2686 enmMode = CPUMMODE_PROTECTED;
2687 else
2688 enmMode = CPUMMODE_LONG;
2689
2690 return enmMode;
2691}
2692
2693
2694/**
2695 * Figure whether the CPU is currently executing 16, 32 or 64 bit code.
2696 *
2697 * @returns 16, 32 or 64.
2698 * @param pVCpu The current virtual CPU.
2699 */
2700VMMDECL(uint32_t) CPUMGetGuestCodeBits(PVMCPU pVCpu)
2701{
2702 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2703 return 16;
2704
2705 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2706 {
2707 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2708 return 16;
2709 }
2710
2711 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2712 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2713 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2714 return 64;
2715
2716 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2717 return 32;
2718
2719 return 16;
2720}
2721
2722
2723VMMDECL(DISCPUMODE) CPUMGetGuestDisMode(PVMCPU pVCpu)
2724{
2725 if (!(pVCpu->cpum.s.Guest.cr0 & X86_CR0_PE))
2726 return DISCPUMODE_16BIT;
2727
2728 if (pVCpu->cpum.s.Guest.eflags.Bits.u1VM)
2729 {
2730 Assert(!(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA));
2731 return DISCPUMODE_16BIT;
2732 }
2733
2734 CPUMSELREG_LAZY_LOAD_HIDDEN_PARTS(pVCpu, &pVCpu->cpum.s.Guest.cs);
2735 if ( pVCpu->cpum.s.Guest.cs.Attr.n.u1Long
2736 && (pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
2737 return DISCPUMODE_64BIT;
2738
2739 if (pVCpu->cpum.s.Guest.cs.Attr.n.u1DefBig)
2740 return DISCPUMODE_32BIT;
2741
2742 return DISCPUMODE_16BIT;
2743}
2744
Note: See TracBrowser for help on using the repository browser.

© 2023 Oracle
Contact – Privacy policy – Terms of Use