[33687] | 1 | /* $Id: BusAssignmentManager.cpp 70238 2017-12-20 11:55:05Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VirtualBox bus slots assignment manager
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| 4 | */
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| 5 |
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| 6 | /*
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[69500] | 7 | * Copyright (C) 2010-2017 Oracle Corporation
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[33687] | 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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[67914] | 17 |
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| 18 | #define LOG_GROUP LOG_GROUP_MAIN
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| 19 | #include "LoggingNew.h"
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| 20 |
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[33687] | 21 | #include "BusAssignmentManager.h"
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| 22 |
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| 23 | #include <iprt/asm.h>
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[34123] | 24 | #include <iprt/string.h>
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[33687] | 25 |
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[35346] | 26 | #include <VBox/vmm/cfgm.h>
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[34331] | 27 | #include <VBox/com/array.h>
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[33687] | 28 |
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| 29 | #include <map>
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[33690] | 30 | #include <vector>
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[33722] | 31 | #include <algorithm>
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[33687] | 32 |
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[33722] | 33 | struct DeviceAssignmentRule
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| 34 | {
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[70238] | 35 | const char *pszName;
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[33722] | 36 | int iBus;
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| 37 | int iDevice;
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| 38 | int iFn;
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| 39 | int iPriority;
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| 40 | };
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| 41 |
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| 42 | struct DeviceAliasRule
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| 43 | {
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[70238] | 44 | const char *pszDevName;
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| 45 | const char *pszDevAlias;
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[33722] | 46 | };
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| 47 |
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| 48 | /* Those rules define PCI slots assignment */
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[68371] | 49 | /** @note
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| 50 | * The EFI takes assumptions about PCI slot assignments which are different
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| 51 | * from the following tables in certain cases, for example the IDE device
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| 52 | * is assumed to be 00:01.1! */
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[33722] | 53 |
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[34014] | 54 | /* Device Bus Device Function Priority */
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[34013] | 55 |
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[33722] | 56 | /* Generic rules */
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| 57 | static const DeviceAssignmentRule aGenericRules[] =
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| 58 | {
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| 59 | /* VGA controller */
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| 60 | {"vga", 0, 2, 0, 0},
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| 61 |
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| 62 | /* VMM device */
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| 63 | {"VMMDev", 0, 4, 0, 0},
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| 64 |
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| 65 | /* Audio controllers */
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| 66 | {"ichac97", 0, 5, 0, 0},
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| 67 | {"hda", 0, 5, 0, 0},
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| 68 |
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| 69 | /* Storage controllers */
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[34013] | 70 | {"lsilogic", 0, 20, 0, 1},
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| 71 | {"buslogic", 0, 21, 0, 1},
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| 72 | {"lsilogicsas", 0, 22, 0, 1},
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[57524] | 73 | {"nvme", 0, 14, 0, 1},
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[33722] | 74 |
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| 75 | /* USB controllers */
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| 76 | {"usb-ohci", 0, 6, 0, 0},
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| 77 | {"usb-ehci", 0, 11, 0, 0},
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[50721] | 78 | {"usb-xhci", 0, 12, 0, 0},
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[33722] | 79 |
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| 80 | /* ACPI controller */
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| 81 | {"acpi", 0, 7, 0, 0},
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| 82 |
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| 83 | /* Network controllers */
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| 84 | /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
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[47223] | 85 | * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
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| 86 | * swap places, i.e. the first card goes to ID 17=0x11. */
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[34013] | 87 | {"nic", 0, 3, 0, 1},
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| 88 | {"nic", 0, 8, 0, 1},
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| 89 | {"nic", 0, 9, 0, 1},
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| 90 | {"nic", 0, 10, 0, 1},
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| 91 | {"nic", 0, 16, 0, 1},
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| 92 | {"nic", 0, 17, 0, 1},
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| 93 | {"nic", 0, 18, 0, 1},
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| 94 | {"nic", 0, 19, 0, 1},
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[33722] | 95 |
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| 96 | /* ISA/LPC controller */
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| 97 | {"lpc", 0, 31, 0, 0},
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| 98 |
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| 99 | { NULL, -1, -1, -1, 0}
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| 100 | };
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| 101 |
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| 102 | /* PIIX3 chipset rules */
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| 103 | static const DeviceAssignmentRule aPiix3Rules[] =
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| 104 | {
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| 105 | {"piix3ide", 0, 1, 1, 0},
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[42826] | 106 | {"ahci", 0, 13, 0, 1},
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[33722] | 107 | {"pcibridge", 0, 24, 0, 0},
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| 108 | {"pcibridge", 0, 25, 0, 0},
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| 109 | { NULL, -1, -1, -1, 0}
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| 110 | };
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| 111 |
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| 112 |
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| 113 | /* ICH9 chipset rules */
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| 114 | static const DeviceAssignmentRule aIch9Rules[] =
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| 115 | {
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| 116 | /* Host Controller */
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| 117 | {"i82801", 0, 30, 0, 0},
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| 118 |
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| 119 | /* Those are functions of LPC at 00:1e:00 */
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| 120 | /**
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| 121 | * Please note, that for devices being functions, like we do here, device 0
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| 122 | * must be multifunction, i.e. have header type 0x80. Our LPC device is.
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| 123 | * Alternative approach is to assign separate slot to each device.
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| 124 | */
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[34266] | 125 | {"piix3ide", 0, 31, 1, 2},
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| 126 | {"ahci", 0, 31, 2, 2},
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| 127 | {"smbus", 0, 31, 3, 2},
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| 128 | {"usb-ohci", 0, 31, 4, 2},
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| 129 | {"usb-ehci", 0, 31, 5, 2},
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| 130 | {"thermal", 0, 31, 6, 2},
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[33722] | 131 |
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| 132 | /* to make sure rule never used before rules assigning devices on it */
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| 133 | {"ich9pcibridge", 0, 24, 0, 10},
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| 134 | {"ich9pcibridge", 0, 25, 0, 10},
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[70238] | 135 | {"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
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| 136 | {"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
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| 137 | {"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
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| 138 | {"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
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| 139 | {"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
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| 140 | {"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
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| 141 | {"ich9pcibridge", 8, 24, 0, 6},
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| 142 | {"ich9pcibridge", 8, 25, 0, 6},
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| 143 | {"ich9pcibridge", 10, 24, 0, 5},
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| 144 | {"ich9pcibridge", 10, 25, 0, 5},
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[33907] | 145 |
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| 146 | /* Storage controllers */
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| 147 | {"ahci", 1, 0, 0, 0},
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| 148 | {"ahci", 1, 1, 0, 0},
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| 149 | {"ahci", 1, 2, 0, 0},
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| 150 | {"ahci", 1, 3, 0, 0},
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| 151 | {"ahci", 1, 4, 0, 0},
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| 152 | {"ahci", 1, 5, 0, 0},
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| 153 | {"ahci", 1, 6, 0, 0},
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| 154 | {"lsilogic", 1, 7, 0, 0},
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| 155 | {"lsilogic", 1, 8, 0, 0},
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| 156 | {"lsilogic", 1, 9, 0, 0},
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| 157 | {"lsilogic", 1, 10, 0, 0},
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| 158 | {"lsilogic", 1, 11, 0, 0},
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| 159 | {"lsilogic", 1, 12, 0, 0},
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| 160 | {"lsilogic", 1, 13, 0, 0},
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| 161 | {"buslogic", 1, 14, 0, 0},
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| 162 | {"buslogic", 1, 15, 0, 0},
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| 163 | {"buslogic", 1, 16, 0, 0},
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| 164 | {"buslogic", 1, 17, 0, 0},
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| 165 | {"buslogic", 1, 18, 0, 0},
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| 166 | {"buslogic", 1, 19, 0, 0},
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| 167 | {"buslogic", 1, 20, 0, 0},
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| 168 | {"lsilogicsas", 1, 21, 0, 0},
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| 169 | {"lsilogicsas", 1, 26, 0, 0},
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| 170 | {"lsilogicsas", 1, 27, 0, 0},
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| 171 | {"lsilogicsas", 1, 28, 0, 0},
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| 172 | {"lsilogicsas", 1, 29, 0, 0},
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| 173 | {"lsilogicsas", 1, 30, 0, 0},
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| 174 | {"lsilogicsas", 1, 31, 0, 0},
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| 175 |
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| 176 | /* NICs */
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| 177 | {"nic", 2, 0, 0, 0},
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| 178 | {"nic", 2, 1, 0, 0},
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| 179 | {"nic", 2, 2, 0, 0},
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| 180 | {"nic", 2, 3, 0, 0},
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| 181 | {"nic", 2, 4, 0, 0},
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| 182 | {"nic", 2, 5, 0, 0},
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| 183 | {"nic", 2, 6, 0, 0},
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| 184 | {"nic", 2, 7, 0, 0},
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| 185 | {"nic", 2, 8, 0, 0},
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| 186 | {"nic", 2, 9, 0, 0},
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| 187 | {"nic", 2, 10, 0, 0},
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| 188 | {"nic", 2, 11, 0, 0},
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| 189 | {"nic", 2, 12, 0, 0},
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| 190 | {"nic", 2, 13, 0, 0},
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| 191 | {"nic", 2, 14, 0, 0},
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| 192 | {"nic", 2, 15, 0, 0},
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| 193 | {"nic", 2, 16, 0, 0},
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| 194 | {"nic", 2, 17, 0, 0},
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| 195 | {"nic", 2, 18, 0, 0},
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| 196 | {"nic", 2, 19, 0, 0},
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| 197 | {"nic", 2, 20, 0, 0},
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| 198 | {"nic", 2, 21, 0, 0},
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| 199 | {"nic", 2, 26, 0, 0},
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| 200 | {"nic", 2, 27, 0, 0},
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| 201 | {"nic", 2, 28, 0, 0},
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| 202 | {"nic", 2, 29, 0, 0},
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| 203 | {"nic", 2, 30, 0, 0},
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| 204 | {"nic", 2, 31, 0, 0},
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| 205 |
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[63747] | 206 | /* Storage controller #2 (NVMe) */
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| 207 | {"nvme", 3, 0, 0, 0},
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| 208 | {"nvme", 3, 1, 0, 0},
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| 209 | {"nvme", 3, 2, 0, 0},
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| 210 | {"nvme", 3, 3, 0, 0},
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| 211 | {"nvme", 3, 4, 0, 0},
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| 212 | {"nvme", 3, 5, 0, 0},
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| 213 | {"nvme", 3, 6, 0, 0},
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| 214 |
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[33722] | 215 | { NULL, -1, -1, -1, 0}
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| 216 | };
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| 217 |
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| 218 | /* Aliasing rules */
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| 219 | static const DeviceAliasRule aDeviceAliases[] =
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| 220 | {
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[33907] | 221 | {"e1000", "nic"},
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| 222 | {"pcnet", "nic"},
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| 223 | {"virtio-net", "nic"},
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| 224 | {"ahci", "storage"},
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| 225 | {"lsilogic", "storage"},
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| 226 | {"buslogic", "storage"},
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[57524] | 227 | {"lsilogicsas", "storage"},
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| 228 | {"nvme", "storage"}
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[33722] | 229 | };
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| 230 |
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[33687] | 231 | struct BusAssignmentManager::State
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| 232 | {
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[42551] | 233 | struct PCIDeviceRecord
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[33687] | 234 | {
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[36107] | 235 | char szDevName[32];
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[42551] | 236 | PCIBusAddress HostAddress;
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[33688] | 237 |
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[70238] | 238 | PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
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[36107] | 239 | {
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| 240 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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| 241 | this->HostAddress = aHostAddress;
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| 242 | }
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| 243 |
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[70238] | 244 | PCIDeviceRecord(const char *pszName)
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[33688] | 245 | {
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[36107] | 246 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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[33688] | 247 | }
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[33690] | 248 |
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[42551] | 249 | bool operator<(const PCIDeviceRecord &a) const
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[33690] | 250 | {
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[34123] | 251 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
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[33690] | 252 | }
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| 253 |
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[42551] | 254 | bool operator==(const PCIDeviceRecord &a) const
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[33690] | 255 | {
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[34123] | 256 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
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[33690] | 257 | }
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[33687] | 258 | };
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| 259 |
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[61009] | 260 | typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
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[42551] | 261 | typedef std::vector<PCIBusAddress> PCIAddrList;
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[61009] | 262 | typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
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| 263 | typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
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[33687] | 264 |
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| 265 | volatile int32_t cRefCnt;
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| 266 | ChipsetType_T mChipsetType;
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[70238] | 267 | const char * mpszBridgeName;
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[42551] | 268 | PCIMap mPCIMap;
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| 269 | ReversePCIMap mReversePCIMap;
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[33687] | 270 |
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| 271 | State()
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[70238] | 272 | : cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge")
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[33687] | 273 | {}
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| 274 | ~State()
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| 275 | {}
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| 276 |
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| 277 | HRESULT init(ChipsetType_T chipsetType);
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| 278 |
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[70238] | 279 | HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
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| 280 | HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
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[42551] | 281 | bool checkAvailable(PCIBusAddress& Address);
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[70238] | 282 | bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
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[33722] | 283 |
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[70238] | 284 | const char *findAlias(const char *pszName);
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| 285 | void addMatchingRules(const char *pszName, PCIRulesList& aList);
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[61009] | 286 | void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
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[33687] | 287 | };
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| 288 |
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| 289 | HRESULT BusAssignmentManager::State::init(ChipsetType_T chipsetType)
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| 290 | {
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| 291 | mChipsetType = chipsetType;
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[70238] | 292 | switch (chipsetType)
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| 293 | {
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| 294 | case ChipsetType_PIIX3:
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| 295 | mpszBridgeName = "pcibridge";
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| 296 | break;
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| 297 | case ChipsetType_ICH9:
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| 298 | mpszBridgeName = "ich9pcibridge";
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| 299 | break;
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| 300 | default:
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| 301 | mpszBridgeName = "unknownbridge";
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| 302 | AssertFailed();
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| 303 | break;
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| 304 | }
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[33687] | 305 | return S_OK;
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| 306 | }
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| 307 |
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[70238] | 308 | HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
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[33688] | 309 | {
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[42551] | 310 | PCIDeviceRecord devRec(pszName, HostAddress);
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[33690] | 311 |
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| 312 | /* Remember address -> device mapping */
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[42551] | 313 | mPCIMap.insert(PCIMap::value_type(Address, devRec));
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[33690] | 314 |
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[42551] | 315 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
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| 316 | if (it == mReversePCIMap.end())
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[33690] | 317 | {
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[42551] | 318 | mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
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| 319 | it = mReversePCIMap.find(devRec);
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[33690] | 320 | }
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| 321 |
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| 322 | /* Remember device name -> addresses mapping */
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| 323 | it->second.push_back(Address);
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| 324 |
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[33688] | 325 | return S_OK;
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| 326 | }
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| 327 |
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[70238] | 328 | bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
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[33690] | 329 | {
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[42551] | 330 | PCIDeviceRecord devRec(pszDevName);
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[33690] | 331 |
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[42551] | 332 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
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| 333 | if (it == mReversePCIMap.end())
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[33690] | 334 | return false;
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| 335 |
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| 336 | if (iInstance >= (int)it->second.size())
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| 337 | return false;
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| 338 |
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| 339 | Address = it->second[iInstance];
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| 340 | return true;
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| 341 | }
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| 342 |
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[70238] | 343 | void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
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[33722] | 344 | {
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| 345 | size_t iRuleset, iRule;
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[70238] | 346 | const DeviceAssignmentRule *aArrays[2] = {aGenericRules, NULL};
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[33722] | 347 |
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| 348 | switch (mChipsetType)
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| 349 | {
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| 350 | case ChipsetType_PIIX3:
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| 351 | aArrays[1] = aPiix3Rules;
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| 352 | break;
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| 353 | case ChipsetType_ICH9:
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| 354 | aArrays[1] = aIch9Rules;
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| 355 | break;
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| 356 | default:
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[70238] | 357 | AssertFailed();
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[33722] | 358 | break;
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| 359 | }
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| 360 |
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| 361 | for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
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| 362 | {
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| 363 | if (aArrays[iRuleset] == NULL)
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| 364 | continue;
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| 365 |
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| 366 | for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
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| 367 | {
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[34123] | 368 | if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
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[33722] | 369 | aList.push_back(&aArrays[iRuleset][iRule]);
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| 370 | }
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| 371 | }
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| 372 | }
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| 373 |
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[70238] | 374 | const char *BusAssignmentManager::State::findAlias(const char *pszDev)
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[33722] | 375 | {
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| 376 | for (size_t iAlias = 0; iAlias < RT_ELEMENTS(aDeviceAliases); iAlias++)
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| 377 | {
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| 378 | if (strcmp(pszDev, aDeviceAliases[iAlias].pszDevName) == 0)
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| 379 | return aDeviceAliases[iAlias].pszDevAlias;
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| 380 | }
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| 381 | return NULL;
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| 382 | }
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| 383 |
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[70238] | 384 | static bool RuleComparator(const DeviceAssignmentRule *r1, const DeviceAssignmentRule *r2)
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[33722] | 385 | {
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| 386 | return (r1->iPriority > r2->iPriority);
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| 387 | }
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| 388 |
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[70238] | 389 | HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
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[33687] | 390 | {
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[42551] | 391 | PCIRulesList matchingRules;
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[33722] | 392 |
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| 393 | addMatchingRules(pszName, matchingRules);
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[70238] | 394 | const char *pszAlias = findAlias(pszName);
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[33722] | 395 | if (pszAlias)
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| 396 | addMatchingRules(pszAlias, matchingRules);
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| 397 |
|
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| 398 | AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
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| 399 |
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[34266] | 400 | stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
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[33722] | 401 |
|
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| 402 | for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
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| 403 | {
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[70238] | 404 | const DeviceAssignmentRule *rule = matchingRules[iRule];
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[33722] | 405 |
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[36630] | 406 | Address.miBus = rule->iBus;
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| 407 | Address.miDevice = rule->iDevice;
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| 408 | Address.miFn = rule->iFn;
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[33722] | 409 |
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| 410 | if (checkAvailable(Address))
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| 411 | return S_OK;
|
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| 412 | }
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[70238] | 413 | AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
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[33722] | 414 |
|
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| 415 | return E_INVALIDARG;
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[33687] | 416 | }
|
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| 417 |
|
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[42551] | 418 | bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
|
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[33687] | 419 | {
|
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[42551] | 420 | PCIMap::const_iterator it = mPCIMap.find(Address);
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[33688] | 421 |
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[42551] | 422 | return (it == mPCIMap.end());
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[33687] | 423 | }
|
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| 424 |
|
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[61009] | 425 | void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
|
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[34331] | 426 | {
|
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[51612] | 427 | aAttached.resize(mPCIMap.size());
|
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[34331] | 428 |
|
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[51612] | 429 | size_t i = 0;
|
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[61009] | 430 | PCIDeviceInfo dev;
|
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[51612] | 431 | for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
|
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[34331] | 432 | {
|
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[61009] | 433 | dev.strDeviceName = it->second.szDevName;
|
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| 434 | dev.guestAddress = it->first;
|
---|
| 435 | dev.hostAddress = it->second.HostAddress;
|
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| 436 | aAttached[i] = dev;
|
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[34331] | 437 | }
|
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| 438 | }
|
---|
| 439 |
|
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[33687] | 440 | BusAssignmentManager::BusAssignmentManager()
|
---|
| 441 | : pState(NULL)
|
---|
| 442 | {
|
---|
| 443 | pState = new State();
|
---|
| 444 | Assert(pState);
|
---|
| 445 | }
|
---|
| 446 |
|
---|
| 447 | BusAssignmentManager::~BusAssignmentManager()
|
---|
| 448 | {
|
---|
| 449 | if (pState)
|
---|
| 450 | {
|
---|
| 451 | delete pState;
|
---|
| 452 | pState = NULL;
|
---|
| 453 | }
|
---|
| 454 | }
|
---|
| 455 |
|
---|
[70238] | 456 | BusAssignmentManager *BusAssignmentManager::createInstance(ChipsetType_T chipsetType)
|
---|
[33687] | 457 | {
|
---|
[70238] | 458 | BusAssignmentManager *pInstance = new BusAssignmentManager();
|
---|
[34331] | 459 | pInstance->pState->init(chipsetType);
|
---|
| 460 | Assert(pInstance);
|
---|
[33687] | 461 | return pInstance;
|
---|
| 462 | }
|
---|
| 463 |
|
---|
| 464 | void BusAssignmentManager::AddRef()
|
---|
| 465 | {
|
---|
| 466 | ASMAtomicIncS32(&pState->cRefCnt);
|
---|
| 467 | }
|
---|
| 468 | void BusAssignmentManager::Release()
|
---|
| 469 | {
|
---|
[34044] | 470 | if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
|
---|
[33687] | 471 | delete this;
|
---|
| 472 | }
|
---|
| 473 |
|
---|
[70238] | 474 | DECLINLINE(HRESULT) InsertConfigInteger(PCFGMNODE pCfg, const char *pszName, uint64_t u64)
|
---|
[33687] | 475 | {
|
---|
| 476 | int vrc = CFGMR3InsertInteger(pCfg, pszName, u64);
|
---|
| 477 | if (RT_FAILURE(vrc))
|
---|
| 478 | return E_INVALIDARG;
|
---|
| 479 |
|
---|
| 480 | return S_OK;
|
---|
| 481 | }
|
---|
| 482 |
|
---|
[70238] | 483 | DECLINLINE(HRESULT) InsertConfigNode(PCFGMNODE pNode, const char *pcszName, PCFGMNODE *ppChild)
|
---|
| 484 | {
|
---|
| 485 | int vrc = CFGMR3InsertNode(pNode, pcszName, ppChild);
|
---|
| 486 | if (RT_FAILURE(vrc))
|
---|
| 487 | return E_INVALIDARG;
|
---|
| 488 |
|
---|
| 489 | return S_OK;
|
---|
| 490 | }
|
---|
| 491 |
|
---|
| 492 |
|
---|
| 493 | HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
|
---|
[36107] | 494 | PCFGMNODE pCfg,
|
---|
[42551] | 495 | PCIBusAddress& GuestAddress,
|
---|
| 496 | PCIBusAddress HostAddress,
|
---|
[36107] | 497 | bool fGuestAddressRequired)
|
---|
[33687] | 498 | {
|
---|
| 499 | HRESULT rc = S_OK;
|
---|
| 500 |
|
---|
[36107] | 501 | if (!GuestAddress.valid())
|
---|
| 502 | rc = pState->autoAssign(pszDevName, GuestAddress);
|
---|
[33687] | 503 | else
|
---|
| 504 | {
|
---|
[36107] | 505 | bool fAvailable = pState->checkAvailable(GuestAddress);
|
---|
[33687] | 506 |
|
---|
| 507 | if (!fAvailable)
|
---|
| 508 | {
|
---|
[36107] | 509 | if (fGuestAddressRequired)
|
---|
[33964] | 510 | rc = E_ACCESSDENIED;
|
---|
[33687] | 511 | else
|
---|
[36107] | 512 | rc = pState->autoAssign(pszDevName, GuestAddress);
|
---|
[33687] | 513 | }
|
---|
| 514 | }
|
---|
| 515 |
|
---|
| 516 | if (FAILED(rc))
|
---|
| 517 | return rc;
|
---|
| 518 |
|
---|
[36107] | 519 | Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
|
---|
[33687] | 520 |
|
---|
[36107] | 521 | rc = pState->record(pszDevName, GuestAddress, HostAddress);
|
---|
[33688] | 522 | if (FAILED(rc))
|
---|
| 523 | return rc;
|
---|
| 524 |
|
---|
[36630] | 525 | rc = InsertConfigInteger(pCfg, "PCIBusNo", GuestAddress.miBus);
|
---|
[33687] | 526 | if (FAILED(rc))
|
---|
| 527 | return rc;
|
---|
[36630] | 528 | rc = InsertConfigInteger(pCfg, "PCIDeviceNo", GuestAddress.miDevice);
|
---|
[33687] | 529 | if (FAILED(rc))
|
---|
| 530 | return rc;
|
---|
[36630] | 531 | rc = InsertConfigInteger(pCfg, "PCIFunctionNo", GuestAddress.miFn);
|
---|
[33687] | 532 | if (FAILED(rc))
|
---|
| 533 | return rc;
|
---|
| 534 |
|
---|
[70238] | 535 | /* Check if the bus is still unknown, i.e. the bridge to it is missing */
|
---|
| 536 | if ( GuestAddress.miBus > 0
|
---|
| 537 | && !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
|
---|
| 538 | {
|
---|
| 539 | PCFGMNODE pDevices = CFGMR3GetParent(CFGMR3GetParent(pCfg));
|
---|
| 540 | AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
|
---|
| 541 | PCFGMNODE pBridges = CFGMR3GetChild(pDevices, "ich9pcibridge");
|
---|
| 542 | AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
|
---|
| 543 |
|
---|
| 544 | /* Device should be on a not yet existing bus, add it automatically */
|
---|
| 545 | for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
|
---|
| 546 | {
|
---|
| 547 | if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
|
---|
| 548 | {
|
---|
| 549 | PCIBusAddress BridgeGuestAddress;
|
---|
| 550 | rc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
|
---|
| 551 | if (FAILED(rc))
|
---|
| 552 | return rc;
|
---|
| 553 | if (BridgeGuestAddress.miBus > iBridge)
|
---|
| 554 | AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
|
---|
| 555 |
|
---|
| 556 | PCFGMNODE pInst;
|
---|
| 557 | InsertConfigNode(pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
|
---|
| 558 | InsertConfigInteger(pInst, "Trusted", 1);
|
---|
| 559 | rc = assignPCIDevice(pState->mpszBridgeName, pInst);
|
---|
| 560 | if (FAILED(rc))
|
---|
| 561 | return rc;
|
---|
| 562 | }
|
---|
| 563 | }
|
---|
| 564 | }
|
---|
| 565 |
|
---|
[33687] | 566 | return S_OK;
|
---|
| 567 | }
|
---|
[33690] | 568 |
|
---|
| 569 |
|
---|
[70238] | 570 | bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
|
---|
[33690] | 571 | {
|
---|
[42551] | 572 | return pState->findPCIAddress(pszDevName, iInstance, Address);
|
---|
[33690] | 573 | }
|
---|
[61009] | 574 | void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
|
---|
[34331] | 575 | {
|
---|
[51612] | 576 | pState->listAttachedPCIDevices(aAttached);
|
---|
[34331] | 577 | }
|
---|