[33687] | 1 | /* $Id: BusAssignmentManager.cpp 101473 2023-10-17 11:54:45Z vboxsync $ */
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| 2 | /** @file
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| 3 | * VirtualBox bus slots assignment manager
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| 4 | */
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| 5 |
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| 6 | /*
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[98103] | 7 | * Copyright (C) 2010-2023 Oracle and/or its affiliates.
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[33687] | 8 | *
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[96407] | 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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[33687] | 26 | */
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[67914] | 27 |
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[93444] | 28 |
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| 29 | /*********************************************************************************************************************************
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| 30 | * Header Files *
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| 31 | *********************************************************************************************************************************/
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[67914] | 32 | #define LOG_GROUP LOG_GROUP_MAIN
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| 33 | #include "LoggingNew.h"
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| 34 |
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[33687] | 35 | #include "BusAssignmentManager.h"
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| 36 |
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| 37 | #include <iprt/asm.h>
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[34123] | 38 | #include <iprt/string.h>
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[33687] | 39 |
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[35346] | 40 | #include <VBox/vmm/cfgm.h>
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[93444] | 41 | #include <VBox/vmm/vmmr3vtable.h>
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[34331] | 42 | #include <VBox/com/array.h>
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[33687] | 43 |
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| 44 | #include <map>
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[33690] | 45 | #include <vector>
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[33722] | 46 | #include <algorithm>
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[33687] | 47 |
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[93444] | 48 |
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| 49 | /*********************************************************************************************************************************
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| 50 | * Structures and Typedefs *
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| 51 | *********************************************************************************************************************************/
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[33722] | 52 | struct DeviceAssignmentRule
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| 53 | {
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[70238] | 54 | const char *pszName;
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[33722] | 55 | int iBus;
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| 56 | int iDevice;
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| 57 | int iFn;
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| 58 | int iPriority;
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| 59 | };
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| 60 |
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| 61 | struct DeviceAliasRule
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| 62 | {
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[70238] | 63 | const char *pszDevName;
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| 64 | const char *pszDevAlias;
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[33722] | 65 | };
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| 66 |
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[93444] | 67 |
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| 68 | /*********************************************************************************************************************************
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| 69 | * Global Variables *
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| 70 | *********************************************************************************************************************************/
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[33722] | 71 | /* Those rules define PCI slots assignment */
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[68371] | 72 | /** @note
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| 73 | * The EFI takes assumptions about PCI slot assignments which are different
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| 74 | * from the following tables in certain cases, for example the IDE device
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| 75 | * is assumed to be 00:01.1! */
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[33722] | 76 |
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[34014] | 77 | /* Device Bus Device Function Priority */
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[34013] | 78 |
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[33722] | 79 | /* Generic rules */
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[85011] | 80 | static const DeviceAssignmentRule g_aGenericRules[] =
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[33722] | 81 | {
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| 82 | /* VGA controller */
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| 83 | {"vga", 0, 2, 0, 0},
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| 84 |
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| 85 | /* VMM device */
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| 86 | {"VMMDev", 0, 4, 0, 0},
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| 87 |
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| 88 | /* Audio controllers */
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| 89 | {"ichac97", 0, 5, 0, 0},
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| 90 | {"hda", 0, 5, 0, 0},
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| 91 |
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| 92 | /* Storage controllers */
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[34013] | 93 | {"buslogic", 0, 21, 0, 1},
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| 94 | {"lsilogicsas", 0, 22, 0, 1},
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[57524] | 95 | {"nvme", 0, 14, 0, 1},
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[78509] | 96 | {"virtio-scsi", 0, 15, 0, 1},
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[33722] | 97 |
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| 98 | /* USB controllers */
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| 99 | {"usb-ohci", 0, 6, 0, 0},
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| 100 | {"usb-ehci", 0, 11, 0, 0},
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[50721] | 101 | {"usb-xhci", 0, 12, 0, 0},
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[33722] | 102 |
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| 103 | /* ACPI controller */
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[79674] | 104 | #if 0
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| 105 | // It really should be this for 440FX chipset (part of PIIX4 actually)
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| 106 | {"acpi", 0, 1, 3, 0},
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| 107 | #else
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[33722] | 108 | {"acpi", 0, 7, 0, 0},
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[79674] | 109 | #endif
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[33722] | 110 |
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| 111 | /* Network controllers */
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| 112 | /* the first network card gets the PCI ID 3, the next 3 gets 8..10,
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[47223] | 113 | * next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
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| 114 | * swap places, i.e. the first card goes to ID 17=0x11. */
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[34013] | 115 | {"nic", 0, 3, 0, 1},
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| 116 | {"nic", 0, 8, 0, 1},
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| 117 | {"nic", 0, 9, 0, 1},
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| 118 | {"nic", 0, 10, 0, 1},
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| 119 | {"nic", 0, 16, 0, 1},
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| 120 | {"nic", 0, 17, 0, 1},
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| 121 | {"nic", 0, 18, 0, 1},
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| 122 | {"nic", 0, 19, 0, 1},
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[33722] | 123 |
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| 124 | /* ISA/LPC controller */
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| 125 | {"lpc", 0, 31, 0, 0},
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| 126 |
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| 127 | { NULL, -1, -1, -1, 0}
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| 128 | };
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| 129 |
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| 130 | /* PIIX3 chipset rules */
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[85011] | 131 | static const DeviceAssignmentRule g_aPiix3Rules[] =
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[33722] | 132 | {
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| 133 | {"piix3ide", 0, 1, 1, 0},
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[42826] | 134 | {"ahci", 0, 13, 0, 1},
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[85007] | 135 | {"lsilogic", 0, 20, 0, 1},
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[33722] | 136 | {"pcibridge", 0, 24, 0, 0},
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| 137 | {"pcibridge", 0, 25, 0, 0},
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| 138 | { NULL, -1, -1, -1, 0}
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| 139 | };
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| 140 |
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| 141 |
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| 142 | /* ICH9 chipset rules */
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[85011] | 143 | static const DeviceAssignmentRule g_aIch9Rules[] =
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[33722] | 144 | {
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| 145 | /* Host Controller */
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| 146 | {"i82801", 0, 30, 0, 0},
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| 147 |
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| 148 | /* Those are functions of LPC at 00:1e:00 */
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| 149 | /**
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| 150 | * Please note, that for devices being functions, like we do here, device 0
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| 151 | * must be multifunction, i.e. have header type 0x80. Our LPC device is.
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| 152 | * Alternative approach is to assign separate slot to each device.
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| 153 | */
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[34266] | 154 | {"piix3ide", 0, 31, 1, 2},
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| 155 | {"ahci", 0, 31, 2, 2},
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| 156 | {"smbus", 0, 31, 3, 2},
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| 157 | {"usb-ohci", 0, 31, 4, 2},
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| 158 | {"usb-ehci", 0, 31, 5, 2},
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| 159 | {"thermal", 0, 31, 6, 2},
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[33722] | 160 |
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| 161 | /* to make sure rule never used before rules assigning devices on it */
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| 162 | {"ich9pcibridge", 0, 24, 0, 10},
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| 163 | {"ich9pcibridge", 0, 25, 0, 10},
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[70238] | 164 | {"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
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| 165 | {"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
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| 166 | {"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
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| 167 | {"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
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| 168 | {"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
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| 169 | {"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
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| 170 | {"ich9pcibridge", 8, 24, 0, 6},
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| 171 | {"ich9pcibridge", 8, 25, 0, 6},
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| 172 | {"ich9pcibridge", 10, 24, 0, 5},
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| 173 | {"ich9pcibridge", 10, 25, 0, 5},
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[33907] | 174 |
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| 175 | /* Storage controllers */
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| 176 | {"ahci", 1, 0, 0, 0},
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| 177 | {"ahci", 1, 1, 0, 0},
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| 178 | {"ahci", 1, 2, 0, 0},
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| 179 | {"ahci", 1, 3, 0, 0},
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| 180 | {"ahci", 1, 4, 0, 0},
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| 181 | {"ahci", 1, 5, 0, 0},
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| 182 | {"ahci", 1, 6, 0, 0},
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| 183 | {"lsilogic", 1, 7, 0, 0},
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| 184 | {"lsilogic", 1, 8, 0, 0},
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| 185 | {"lsilogic", 1, 9, 0, 0},
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| 186 | {"lsilogic", 1, 10, 0, 0},
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| 187 | {"lsilogic", 1, 11, 0, 0},
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| 188 | {"lsilogic", 1, 12, 0, 0},
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| 189 | {"lsilogic", 1, 13, 0, 0},
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| 190 | {"buslogic", 1, 14, 0, 0},
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| 191 | {"buslogic", 1, 15, 0, 0},
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| 192 | {"buslogic", 1, 16, 0, 0},
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| 193 | {"buslogic", 1, 17, 0, 0},
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| 194 | {"buslogic", 1, 18, 0, 0},
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| 195 | {"buslogic", 1, 19, 0, 0},
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| 196 | {"buslogic", 1, 20, 0, 0},
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| 197 | {"lsilogicsas", 1, 21, 0, 0},
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| 198 | {"lsilogicsas", 1, 26, 0, 0},
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| 199 | {"lsilogicsas", 1, 27, 0, 0},
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| 200 | {"lsilogicsas", 1, 28, 0, 0},
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| 201 | {"lsilogicsas", 1, 29, 0, 0},
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| 202 | {"lsilogicsas", 1, 30, 0, 0},
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| 203 | {"lsilogicsas", 1, 31, 0, 0},
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| 204 |
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| 205 | /* NICs */
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| 206 | {"nic", 2, 0, 0, 0},
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| 207 | {"nic", 2, 1, 0, 0},
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| 208 | {"nic", 2, 2, 0, 0},
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| 209 | {"nic", 2, 3, 0, 0},
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| 210 | {"nic", 2, 4, 0, 0},
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| 211 | {"nic", 2, 5, 0, 0},
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| 212 | {"nic", 2, 6, 0, 0},
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| 213 | {"nic", 2, 7, 0, 0},
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| 214 | {"nic", 2, 8, 0, 0},
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| 215 | {"nic", 2, 9, 0, 0},
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| 216 | {"nic", 2, 10, 0, 0},
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| 217 | {"nic", 2, 11, 0, 0},
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| 218 | {"nic", 2, 12, 0, 0},
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| 219 | {"nic", 2, 13, 0, 0},
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| 220 | {"nic", 2, 14, 0, 0},
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| 221 | {"nic", 2, 15, 0, 0},
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| 222 | {"nic", 2, 16, 0, 0},
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| 223 | {"nic", 2, 17, 0, 0},
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| 224 | {"nic", 2, 18, 0, 0},
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| 225 | {"nic", 2, 19, 0, 0},
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| 226 | {"nic", 2, 20, 0, 0},
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| 227 | {"nic", 2, 21, 0, 0},
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| 228 | {"nic", 2, 26, 0, 0},
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| 229 | {"nic", 2, 27, 0, 0},
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| 230 | {"nic", 2, 28, 0, 0},
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| 231 | {"nic", 2, 29, 0, 0},
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| 232 | {"nic", 2, 30, 0, 0},
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| 233 | {"nic", 2, 31, 0, 0},
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| 234 |
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[78509] | 235 | /* Storage controller #2 (NVMe, virtio-scsi) */
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[63747] | 236 | {"nvme", 3, 0, 0, 0},
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| 237 | {"nvme", 3, 1, 0, 0},
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| 238 | {"nvme", 3, 2, 0, 0},
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| 239 | {"nvme", 3, 3, 0, 0},
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| 240 | {"nvme", 3, 4, 0, 0},
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| 241 | {"nvme", 3, 5, 0, 0},
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| 242 | {"nvme", 3, 6, 0, 0},
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[78509] | 243 | {"virtio-scsi", 3, 7, 0, 0},
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| 244 | {"virtio-scsi", 3, 8, 0, 0},
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| 245 | {"virtio-scsi", 3, 9, 0, 0},
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| 246 | {"virtio-scsi", 3, 10, 0, 0},
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| 247 | {"virtio-scsi", 3, 11, 0, 0},
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| 248 | {"virtio-scsi", 3, 12, 0, 0},
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| 249 | {"virtio-scsi", 3, 13, 0, 0},
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[63747] | 250 |
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[33722] | 251 | { NULL, -1, -1, -1, 0}
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| 252 | };
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| 253 |
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[85007] | 254 |
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[101473] | 255 | /* Virtual Armv8 platform chipset rules */
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| 256 | static const DeviceAssignmentRule g_aArmv8Rules[] =
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| 257 | {
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| 258 | /* VGA controller */
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| 259 | {"vga", 0, 0, 0, 0},
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| 260 |
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| 261 | /* VMM device */
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| 262 | {"VMMDev", 0, 1, 0, 0},
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| 263 |
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| 264 | /* Audio controllers */
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| 265 | {"ichac97", 0, 2, 0, 0},
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| 266 | {"hda", 0, 2, 0, 0},
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| 267 |
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| 268 | /* Storage controllers */
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| 269 | {"virtio-scsi", 0, 3, 0, 1},
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| 270 | {"nvme", 0, 4, 0, 1},
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| 271 | {"ahci", 0, 16, 0, 1},
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| 272 | {"lsilogicsas", 0, 17, 0, 1},
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| 273 |
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| 274 | /* USB controllers */
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| 275 | {"usb-ehci", 0, 5, 0, 0},
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| 276 | {"usb-xhci", 0, 6, 0, 0},
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| 277 | {"usb-ohci", 0, 7, 0, 0},
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| 278 |
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| 279 | /* Network controllers */
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| 280 | {"nic", 0, 8, 0, 1},
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| 281 | {"nic", 0, 9, 0, 1},
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| 282 | {"nic", 0, 10, 0, 1},
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| 283 | {"nic", 0, 11, 0, 1},
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| 284 | {"nic", 0, 12, 0, 1},
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| 285 | {"nic", 0, 13, 0, 1},
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| 286 | {"nic", 0, 14, 0, 1},
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| 287 | {"nic", 0, 15, 0, 1},
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| 288 |
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| 289 | { NULL, -1, -1, -1, 0}
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| 290 | };
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| 291 |
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| 292 |
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[85007] | 293 | #ifdef VBOX_WITH_IOMMU_AMD
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| 294 | /*
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| 295 | * AMD IOMMU and LSI Logic controller rules.
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| 296 | *
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| 297 | * Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
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| 298 | * conflicts with the SB I/O APIC, we assign the LSI Logic controller
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| 299 | * to device number 23 when the VM is configured for an AMD IOMMU.
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| 300 | */
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[88333] | 301 | static const DeviceAssignmentRule g_aIch9IommuAmdRules[] =
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[85007] | 302 | {
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| 303 | /* AMD IOMMU. */
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[86733] | 304 | {"iommu-amd", 0, 0, 0, 0},
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[85007] | 305 | /* AMD IOMMU: Reserved for southbridge I/O APIC. */
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| 306 | {"sb-ioapic", 0, 20, 0, 0},
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| 307 |
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| 308 | /* Storage controller */
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| 309 | {"lsilogic", 0, 23, 0, 1},
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| 310 | { NULL, -1, -1, -1, 0}
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| 311 | };
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| 312 | #endif
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| 313 |
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[88333] | 314 | #ifdef VBOX_WITH_IOMMU_INTEL
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| 315 | /*
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| 316 | * Intel IOMMU.
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| 317 | * The VT-d misc, address remapping, system management device is
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[88484] | 318 | * located at BDF 0:5:0 on real hardware but we use 0:1:0 since that
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| 319 | * slot isn't used for anything else.
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| 320 | *
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| 321 | * While we could place the I/O APIC anywhere, we keep it consistent
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| 322 | * with the AMD IOMMU and we assign the LSI Logic controller to
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| 323 | * device number 23 (and I/O APIC at device 20).
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[88333] | 324 | */
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| 325 | static const DeviceAssignmentRule g_aIch9IommuIntelRules[] =
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| 326 | {
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| 327 | /* Intel IOMMU. */
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[88484] | 328 | {"iommu-intel", 0, 1, 0, 0},
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| 329 | /* Intel IOMMU: Reserved for I/O APIC. */
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| 330 | {"sb-ioapic", 0, 20, 0, 0},
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[88333] | 331 |
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| 332 | /* Storage controller */
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[88484] | 333 | {"lsilogic", 0, 23, 0, 1},
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[88333] | 334 | { NULL, -1, -1, -1, 0}
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| 335 | };
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| 336 | #endif
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| 337 |
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[85007] | 338 | /* LSI Logic Controller. */
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[85011] | 339 | static const DeviceAssignmentRule g_aIch9LsiRules[] =
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[85007] | 340 | {
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| 341 | /* Storage controller */
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| 342 | {"lsilogic", 0, 20, 0, 1},
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| 343 | { NULL, -1, -1, -1, 0}
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| 344 | };
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| 345 |
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[33722] | 346 | /* Aliasing rules */
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[85011] | 347 | static const DeviceAliasRule g_aDeviceAliases[] =
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[33722] | 348 | {
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[33907] | 349 | {"e1000", "nic"},
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| 350 | {"pcnet", "nic"},
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| 351 | {"virtio-net", "nic"},
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| 352 | {"ahci", "storage"},
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| 353 | {"lsilogic", "storage"},
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| 354 | {"buslogic", "storage"},
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[57524] | 355 | {"lsilogicsas", "storage"},
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[78509] | 356 | {"nvme", "storage"},
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| 357 | {"virtio-scsi", "storage"}
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[33722] | 358 | };
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| 359 |
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[93444] | 360 |
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| 361 |
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| 362 | /**
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| 363 | * Bus assignment manage state data.
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| 364 | * @internal
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| 365 | */
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[33687] | 366 | struct BusAssignmentManager::State
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| 367 | {
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[42551] | 368 | struct PCIDeviceRecord
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[33687] | 369 | {
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[36107] | 370 | char szDevName[32];
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[42551] | 371 | PCIBusAddress HostAddress;
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[33688] | 372 |
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[70238] | 373 | PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
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[36107] | 374 | {
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| 375 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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| 376 | this->HostAddress = aHostAddress;
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| 377 | }
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| 378 |
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[70238] | 379 | PCIDeviceRecord(const char *pszName)
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[33688] | 380 | {
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[36107] | 381 | RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
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[33688] | 382 | }
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[33690] | 383 |
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[42551] | 384 | bool operator<(const PCIDeviceRecord &a) const
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[33690] | 385 | {
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[34123] | 386 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
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[33690] | 387 | }
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| 388 |
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[42551] | 389 | bool operator==(const PCIDeviceRecord &a) const
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[33690] | 390 | {
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[34123] | 391 | return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
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[33690] | 392 | }
|
---|
[33687] | 393 | };
|
---|
| 394 |
|
---|
[61009] | 395 | typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
|
---|
[42551] | 396 | typedef std::vector<PCIBusAddress> PCIAddrList;
|
---|
[61009] | 397 | typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
|
---|
| 398 | typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
|
---|
[33687] | 399 |
|
---|
| 400 | volatile int32_t cRefCnt;
|
---|
| 401 | ChipsetType_T mChipsetType;
|
---|
[70238] | 402 | const char * mpszBridgeName;
|
---|
[87242] | 403 | IommuType_T mIommuType;
|
---|
[42551] | 404 | PCIMap mPCIMap;
|
---|
| 405 | ReversePCIMap mReversePCIMap;
|
---|
[93444] | 406 | PCVMMR3VTABLE mpVMM;
|
---|
[33687] | 407 |
|
---|
| 408 | State()
|
---|
[93444] | 409 | : cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge"), mpVMM(NULL)
|
---|
[33687] | 410 | {}
|
---|
| 411 | ~State()
|
---|
| 412 | {}
|
---|
| 413 |
|
---|
[93444] | 414 | HRESULT init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType);
|
---|
[33687] | 415 |
|
---|
[70238] | 416 | HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
|
---|
| 417 | HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
|
---|
[42551] | 418 | bool checkAvailable(PCIBusAddress& Address);
|
---|
[70238] | 419 | bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
|
---|
[33722] | 420 |
|
---|
[70238] | 421 | const char *findAlias(const char *pszName);
|
---|
| 422 | void addMatchingRules(const char *pszName, PCIRulesList& aList);
|
---|
[61009] | 423 | void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
|
---|
[33687] | 424 | };
|
---|
| 425 |
|
---|
[93444] | 426 |
|
---|
| 427 | HRESULT BusAssignmentManager::State::init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
|
---|
[33687] | 428 | {
|
---|
[93444] | 429 | mpVMM = pVMM;
|
---|
| 430 |
|
---|
[88333] | 431 | if (iommuType != IommuType_None)
|
---|
| 432 | {
|
---|
| 433 | #if defined(VBOX_WITH_IOMMU_AMD) && defined(VBOX_WITH_IOMMU_INTEL)
|
---|
| 434 | Assert(iommuType == IommuType_AMD || iommuType == IommuType_Intel);
|
---|
| 435 | #elif defined(VBOX_WITH_IOMMU_AMD)
|
---|
| 436 | Assert(iommuType == IommuType_AMD);
|
---|
| 437 | #elif defined(VBOX_WITH_IOMMU_INTEL)
|
---|
| 438 | Assert(iommuType == IommuType_Intel);
|
---|
| 439 | #endif
|
---|
| 440 | }
|
---|
[87242] | 441 |
|
---|
[33687] | 442 | mChipsetType = chipsetType;
|
---|
[87242] | 443 | mIommuType = iommuType;
|
---|
[70238] | 444 | switch (chipsetType)
|
---|
| 445 | {
|
---|
| 446 | case ChipsetType_PIIX3:
|
---|
| 447 | mpszBridgeName = "pcibridge";
|
---|
| 448 | break;
|
---|
| 449 | case ChipsetType_ICH9:
|
---|
[101473] | 450 | case ChipsetType_ARMv8Virtual:
|
---|
[70238] | 451 | mpszBridgeName = "ich9pcibridge";
|
---|
| 452 | break;
|
---|
| 453 | default:
|
---|
| 454 | mpszBridgeName = "unknownbridge";
|
---|
| 455 | AssertFailed();
|
---|
| 456 | break;
|
---|
| 457 | }
|
---|
[33687] | 458 | return S_OK;
|
---|
| 459 | }
|
---|
| 460 |
|
---|
[70238] | 461 | HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
|
---|
[33688] | 462 | {
|
---|
[42551] | 463 | PCIDeviceRecord devRec(pszName, HostAddress);
|
---|
[33690] | 464 |
|
---|
| 465 | /* Remember address -> device mapping */
|
---|
[42551] | 466 | mPCIMap.insert(PCIMap::value_type(Address, devRec));
|
---|
[33690] | 467 |
|
---|
[42551] | 468 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
|
---|
| 469 | if (it == mReversePCIMap.end())
|
---|
[33690] | 470 | {
|
---|
[42551] | 471 | mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
|
---|
| 472 | it = mReversePCIMap.find(devRec);
|
---|
[33690] | 473 | }
|
---|
| 474 |
|
---|
| 475 | /* Remember device name -> addresses mapping */
|
---|
| 476 | it->second.push_back(Address);
|
---|
| 477 |
|
---|
[33688] | 478 | return S_OK;
|
---|
| 479 | }
|
---|
| 480 |
|
---|
[85007] | 481 | bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
|
---|
[33690] | 482 | {
|
---|
[42551] | 483 | PCIDeviceRecord devRec(pszDevName);
|
---|
[33690] | 484 |
|
---|
[42551] | 485 | ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
|
---|
| 486 | if (it == mReversePCIMap.end())
|
---|
[33690] | 487 | return false;
|
---|
| 488 |
|
---|
| 489 | if (iInstance >= (int)it->second.size())
|
---|
| 490 | return false;
|
---|
| 491 |
|
---|
| 492 | Address = it->second[iInstance];
|
---|
| 493 | return true;
|
---|
| 494 | }
|
---|
| 495 |
|
---|
[70238] | 496 | void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
|
---|
[33722] | 497 | {
|
---|
| 498 | size_t iRuleset, iRule;
|
---|
[85011] | 499 | const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
|
---|
[33722] | 500 |
|
---|
| 501 | switch (mChipsetType)
|
---|
| 502 | {
|
---|
| 503 | case ChipsetType_PIIX3:
|
---|
[85011] | 504 | aArrays[1] = g_aPiix3Rules;
|
---|
[33722] | 505 | break;
|
---|
| 506 | case ChipsetType_ICH9:
|
---|
[85007] | 507 | {
|
---|
[85011] | 508 | aArrays[1] = g_aIch9Rules;
|
---|
[85007] | 509 | #ifdef VBOX_WITH_IOMMU_AMD
|
---|
[87242] | 510 | if (mIommuType == IommuType_AMD)
|
---|
[88333] | 511 | aArrays[2] = g_aIch9IommuAmdRules;
|
---|
[85007] | 512 | else
|
---|
| 513 | #endif
|
---|
[88333] | 514 | #ifdef VBOX_WITH_IOMMU_INTEL
|
---|
| 515 | if (mIommuType == IommuType_Intel)
|
---|
| 516 | aArrays[2] = g_aIch9IommuIntelRules;
|
---|
| 517 | else
|
---|
| 518 | #endif
|
---|
[85007] | 519 | {
|
---|
[85011] | 520 | aArrays[2] = g_aIch9LsiRules;
|
---|
[85007] | 521 | }
|
---|
[33722] | 522 | break;
|
---|
[85007] | 523 | }
|
---|
[101473] | 524 | case ChipsetType_ARMv8Virtual:
|
---|
| 525 | aArrays[0] = g_aArmv8Rules;
|
---|
| 526 | break;
|
---|
[33722] | 527 | default:
|
---|
[70238] | 528 | AssertFailed();
|
---|
[33722] | 529 | break;
|
---|
| 530 | }
|
---|
| 531 |
|
---|
| 532 | for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
|
---|
| 533 | {
|
---|
| 534 | if (aArrays[iRuleset] == NULL)
|
---|
| 535 | continue;
|
---|
| 536 |
|
---|
| 537 | for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
|
---|
| 538 | {
|
---|
[34123] | 539 | if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
|
---|
[33722] | 540 | aList.push_back(&aArrays[iRuleset][iRule]);
|
---|
| 541 | }
|
---|
| 542 | }
|
---|
| 543 | }
|
---|
| 544 |
|
---|
[70238] | 545 | const char *BusAssignmentManager::State::findAlias(const char *pszDev)
|
---|
[33722] | 546 | {
|
---|
[85011] | 547 | for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
|
---|
[33722] | 548 | {
|
---|
[85011] | 549 | if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
|
---|
| 550 | return g_aDeviceAliases[iAlias].pszDevAlias;
|
---|
[33722] | 551 | }
|
---|
| 552 | return NULL;
|
---|
| 553 | }
|
---|
| 554 |
|
---|
[70238] | 555 | static bool RuleComparator(const DeviceAssignmentRule *r1, const DeviceAssignmentRule *r2)
|
---|
[33722] | 556 | {
|
---|
| 557 | return (r1->iPriority > r2->iPriority);
|
---|
| 558 | }
|
---|
| 559 |
|
---|
[70238] | 560 | HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
|
---|
[33687] | 561 | {
|
---|
[42551] | 562 | PCIRulesList matchingRules;
|
---|
[33722] | 563 |
|
---|
[85007] | 564 | addMatchingRules(pszName, matchingRules);
|
---|
[70238] | 565 | const char *pszAlias = findAlias(pszName);
|
---|
[33722] | 566 | if (pszAlias)
|
---|
| 567 | addMatchingRules(pszAlias, matchingRules);
|
---|
| 568 |
|
---|
| 569 | AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
|
---|
| 570 |
|
---|
[34266] | 571 | stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
|
---|
[33722] | 572 |
|
---|
| 573 | for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
|
---|
| 574 | {
|
---|
[70238] | 575 | const DeviceAssignmentRule *rule = matchingRules[iRule];
|
---|
[33722] | 576 |
|
---|
[36630] | 577 | Address.miBus = rule->iBus;
|
---|
| 578 | Address.miDevice = rule->iDevice;
|
---|
| 579 | Address.miFn = rule->iFn;
|
---|
[33722] | 580 |
|
---|
| 581 | if (checkAvailable(Address))
|
---|
| 582 | return S_OK;
|
---|
| 583 | }
|
---|
[70238] | 584 | AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
|
---|
[33722] | 585 |
|
---|
| 586 | return E_INVALIDARG;
|
---|
[33687] | 587 | }
|
---|
| 588 |
|
---|
[42551] | 589 | bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
|
---|
[33687] | 590 | {
|
---|
[42551] | 591 | PCIMap::const_iterator it = mPCIMap.find(Address);
|
---|
[33688] | 592 |
|
---|
[42551] | 593 | return (it == mPCIMap.end());
|
---|
[33687] | 594 | }
|
---|
| 595 |
|
---|
[61009] | 596 | void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
|
---|
[34331] | 597 | {
|
---|
[51612] | 598 | aAttached.resize(mPCIMap.size());
|
---|
[34331] | 599 |
|
---|
[51612] | 600 | size_t i = 0;
|
---|
[61009] | 601 | PCIDeviceInfo dev;
|
---|
[51612] | 602 | for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
|
---|
[34331] | 603 | {
|
---|
[61009] | 604 | dev.strDeviceName = it->second.szDevName;
|
---|
| 605 | dev.guestAddress = it->first;
|
---|
| 606 | dev.hostAddress = it->second.HostAddress;
|
---|
| 607 | aAttached[i] = dev;
|
---|
[34331] | 608 | }
|
---|
| 609 | }
|
---|
| 610 |
|
---|
[33687] | 611 | BusAssignmentManager::BusAssignmentManager()
|
---|
| 612 | : pState(NULL)
|
---|
| 613 | {
|
---|
| 614 | pState = new State();
|
---|
| 615 | Assert(pState);
|
---|
| 616 | }
|
---|
| 617 |
|
---|
| 618 | BusAssignmentManager::~BusAssignmentManager()
|
---|
| 619 | {
|
---|
| 620 | if (pState)
|
---|
| 621 | {
|
---|
| 622 | delete pState;
|
---|
| 623 | pState = NULL;
|
---|
| 624 | }
|
---|
| 625 | }
|
---|
| 626 |
|
---|
[93444] | 627 | BusAssignmentManager *BusAssignmentManager::createInstance(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
|
---|
[33687] | 628 | {
|
---|
[70238] | 629 | BusAssignmentManager *pInstance = new BusAssignmentManager();
|
---|
[93444] | 630 | pInstance->pState->init(pVMM, chipsetType, iommuType);
|
---|
[34331] | 631 | Assert(pInstance);
|
---|
[33687] | 632 | return pInstance;
|
---|
| 633 | }
|
---|
| 634 |
|
---|
| 635 | void BusAssignmentManager::AddRef()
|
---|
| 636 | {
|
---|
| 637 | ASMAtomicIncS32(&pState->cRefCnt);
|
---|
| 638 | }
|
---|
[93444] | 639 |
|
---|
[33687] | 640 | void BusAssignmentManager::Release()
|
---|
| 641 | {
|
---|
[34044] | 642 | if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
|
---|
[33687] | 643 | delete this;
|
---|
| 644 | }
|
---|
| 645 |
|
---|
[93444] | 646 | DECLINLINE(HRESULT) InsertConfigInteger(PCVMMR3VTABLE pVMM, PCFGMNODE pCfg, const char *pszName, uint64_t u64)
|
---|
[33687] | 647 | {
|
---|
[93444] | 648 | int vrc = pVMM->pfnCFGMR3InsertInteger(pCfg, pszName, u64);
|
---|
[33687] | 649 | if (RT_FAILURE(vrc))
|
---|
| 650 | return E_INVALIDARG;
|
---|
| 651 |
|
---|
| 652 | return S_OK;
|
---|
| 653 | }
|
---|
| 654 |
|
---|
[93444] | 655 | DECLINLINE(HRESULT) InsertConfigNode(PCVMMR3VTABLE pVMM, PCFGMNODE pNode, const char *pcszName, PCFGMNODE *ppChild)
|
---|
[70238] | 656 | {
|
---|
[93444] | 657 | int vrc = pVMM->pfnCFGMR3InsertNode(pNode, pcszName, ppChild);
|
---|
[70238] | 658 | if (RT_FAILURE(vrc))
|
---|
| 659 | return E_INVALIDARG;
|
---|
| 660 |
|
---|
| 661 | return S_OK;
|
---|
| 662 | }
|
---|
| 663 |
|
---|
| 664 |
|
---|
| 665 | HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
|
---|
[36107] | 666 | PCFGMNODE pCfg,
|
---|
[42551] | 667 | PCIBusAddress& GuestAddress,
|
---|
| 668 | PCIBusAddress HostAddress,
|
---|
[36107] | 669 | bool fGuestAddressRequired)
|
---|
[33687] | 670 | {
|
---|
[94920] | 671 | HRESULT hrc = S_OK;
|
---|
[33687] | 672 |
|
---|
[36107] | 673 | if (!GuestAddress.valid())
|
---|
[94920] | 674 | hrc = pState->autoAssign(pszDevName, GuestAddress);
|
---|
[33687] | 675 | else
|
---|
| 676 | {
|
---|
[36107] | 677 | bool fAvailable = pState->checkAvailable(GuestAddress);
|
---|
[33687] | 678 |
|
---|
| 679 | if (!fAvailable)
|
---|
| 680 | {
|
---|
[36107] | 681 | if (fGuestAddressRequired)
|
---|
[94920] | 682 | hrc = E_ACCESSDENIED;
|
---|
[33687] | 683 | else
|
---|
[94920] | 684 | hrc = pState->autoAssign(pszDevName, GuestAddress);
|
---|
[33687] | 685 | }
|
---|
| 686 | }
|
---|
| 687 |
|
---|
[94920] | 688 | if (FAILED(hrc))
|
---|
| 689 | return hrc;
|
---|
[33687] | 690 |
|
---|
[36107] | 691 | Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
|
---|
[33687] | 692 |
|
---|
[94920] | 693 | hrc = pState->record(pszDevName, GuestAddress, HostAddress);
|
---|
| 694 | if (FAILED(hrc))
|
---|
| 695 | return hrc;
|
---|
[33688] | 696 |
|
---|
[93444] | 697 | PCVMMR3VTABLE const pVMM = pState->mpVMM;
|
---|
[85007] | 698 | if (pCfg)
|
---|
| 699 | {
|
---|
[94920] | 700 | hrc = InsertConfigInteger(pVMM, pCfg, "PCIBusNo", GuestAddress.miBus);
|
---|
| 701 | if (FAILED(hrc))
|
---|
| 702 | return hrc;
|
---|
| 703 | hrc = InsertConfigInteger(pVMM, pCfg, "PCIDeviceNo", GuestAddress.miDevice);
|
---|
| 704 | if (FAILED(hrc))
|
---|
| 705 | return hrc;
|
---|
| 706 | hrc = InsertConfigInteger(pVMM, pCfg, "PCIFunctionNo", GuestAddress.miFn);
|
---|
| 707 | if (FAILED(hrc))
|
---|
| 708 | return hrc;
|
---|
[85007] | 709 | }
|
---|
[33687] | 710 |
|
---|
[70238] | 711 | /* Check if the bus is still unknown, i.e. the bridge to it is missing */
|
---|
| 712 | if ( GuestAddress.miBus > 0
|
---|
| 713 | && !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
|
---|
| 714 | {
|
---|
[93444] | 715 | PCFGMNODE pDevices = pVMM->pfnCFGMR3GetParent(pVMM->pfnCFGMR3GetParent(pCfg));
|
---|
[70238] | 716 | AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
|
---|
[93444] | 717 | PCFGMNODE pBridges = pVMM->pfnCFGMR3GetChild(pDevices, "ich9pcibridge");
|
---|
[70238] | 718 | AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
|
---|
| 719 |
|
---|
| 720 | /* Device should be on a not yet existing bus, add it automatically */
|
---|
| 721 | for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
|
---|
| 722 | {
|
---|
| 723 | if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
|
---|
| 724 | {
|
---|
| 725 | PCIBusAddress BridgeGuestAddress;
|
---|
[94920] | 726 | hrc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
|
---|
| 727 | if (FAILED(hrc))
|
---|
| 728 | return hrc;
|
---|
[70238] | 729 | if (BridgeGuestAddress.miBus > iBridge)
|
---|
| 730 | AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
|
---|
| 731 |
|
---|
| 732 | PCFGMNODE pInst;
|
---|
[93444] | 733 | InsertConfigNode(pVMM, pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
|
---|
| 734 | InsertConfigInteger(pVMM, pInst, "Trusted", 1);
|
---|
[94920] | 735 | hrc = assignPCIDevice(pState->mpszBridgeName, pInst);
|
---|
| 736 | if (FAILED(hrc))
|
---|
| 737 | return hrc;
|
---|
[70238] | 738 | }
|
---|
| 739 | }
|
---|
| 740 | }
|
---|
| 741 |
|
---|
[33687] | 742 | return S_OK;
|
---|
| 743 | }
|
---|
[33690] | 744 |
|
---|
| 745 |
|
---|
[70238] | 746 | bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
|
---|
[33690] | 747 | {
|
---|
[42551] | 748 | return pState->findPCIAddress(pszDevName, iInstance, Address);
|
---|
[33690] | 749 | }
|
---|
[61009] | 750 | void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
|
---|
[34331] | 751 | {
|
---|
[51612] | 752 | pState->listAttachedPCIDevices(aAttached);
|
---|
[34331] | 753 | }
|
---|