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BusAssignmentManager.cpp

Last change on this file was 101480, checked in by vboxsync, 7 months ago
Main/src-all,Main/src-client: Add support for PCI bridges for the Armv8 virtual platform and add interrupt descriptors for all slots in the FDT, bugref:10528
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File size: 27.0 KB

Rev	Line
[33687]	1	/* $Id: BusAssignmentManager.cpp 101480 2023-10-17 14:39:59Z vboxsync $ */
	2	/** @file
	3	* VirtualBox bus slots assignment manager
	4	*/
	5
	6	/*
[98103]	7	* Copyright (C) 2010-2023 Oracle and/or its affiliates.
[33687]	8	*
[96407]	9	* This file is part of VirtualBox base platform packages, as
	10	* available from https://www.virtualbox.org.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* as published by the Free Software Foundation, in version 3 of the
	15	* License.
	16	*
	17	* This program is distributed in the hope that it will be useful, but
	18	* WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	20	* General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, see <https://www.gnu.org/licenses>.
	24	*
	25	* SPDX-License-Identifier: GPL-3.0-only
[33687]	26	*/
[67914]	27
[93444]	28
	29	/*********************************************************************************************************************************
	30	* Header Files *
	31	*********************************************************************************************************************************/
[67914]	32	#define LOG_GROUP LOG_GROUP_MAIN
	33	#include "LoggingNew.h"
	34
[33687]	35	#include "BusAssignmentManager.h"
	36
	37	#include <iprt/asm.h>
[34123]	38	#include <iprt/string.h>
[33687]	39
[35346]	40	#include <VBox/vmm/cfgm.h>
[93444]	41	#include <VBox/vmm/vmmr3vtable.h>
[34331]	42	#include <VBox/com/array.h>
[33687]	43
	44	#include <map>
[33690]	45	#include <vector>
[33722]	46	#include <algorithm>
[33687]	47
[93444]	48
	49	/*********************************************************************************************************************************
	50	* Structures and Typedefs *
	51	*********************************************************************************************************************************/
[33722]	52	struct DeviceAssignmentRule
	53	{
[70238]	54	const char *pszName;
[33722]	55	int iBus;
	56	int iDevice;
	57	int iFn;
	58	int iPriority;
	59	};
	60
	61	struct DeviceAliasRule
	62	{
[70238]	63	const char *pszDevName;
	64	const char *pszDevAlias;
[33722]	65	};
	66
[93444]	67
	68	/*********************************************************************************************************************************
	69	* Global Variables *
	70	*********************************************************************************************************************************/
[33722]	71	/* Those rules define PCI slots assignment */
[68371]	72	/** @note
	73	* The EFI takes assumptions about PCI slot assignments which are different
	74	* from the following tables in certain cases, for example the IDE device
	75	* is assumed to be 00:01.1! */
[33722]	76
[34014]	77	/* Device Bus Device Function Priority */
[34013]	78
[33722]	79	/* Generic rules */
[85011]	80	static const DeviceAssignmentRule g_aGenericRules[] =
[33722]	81	{
	82	/* VGA controller */
	83	{"vga", 0, 2, 0, 0},
	84
	85	/* VMM device */
	86	{"VMMDev", 0, 4, 0, 0},
	87
	88	/* Audio controllers */
	89	{"ichac97", 0, 5, 0, 0},
	90	{"hda", 0, 5, 0, 0},
	91
	92	/* Storage controllers */
[34013]	93	{"buslogic", 0, 21, 0, 1},
	94	{"lsilogicsas", 0, 22, 0, 1},
[57524]	95	{"nvme", 0, 14, 0, 1},
[78509]	96	{"virtio-scsi", 0, 15, 0, 1},
[33722]	97
	98	/* USB controllers */
	99	{"usb-ohci", 0, 6, 0, 0},
	100	{"usb-ehci", 0, 11, 0, 0},
[50721]	101	{"usb-xhci", 0, 12, 0, 0},
[33722]	102
	103	/* ACPI controller */
[79674]	104	#if 0
	105	// It really should be this for 440FX chipset (part of PIIX4 actually)
	106	{"acpi", 0, 1, 3, 0},
	107	#else
[33722]	108	{"acpi", 0, 7, 0, 0},
[79674]	109	#endif
[33722]	110
	111	/* Network controllers */
	112	/* the first network card gets the PCI ID 3, the next 3 gets 8..10,
[47223]	113	* next 4 get 16..19. In "VMWare compatibility" mode the IDs 3 and 17
	114	* swap places, i.e. the first card goes to ID 17=0x11. */
[34013]	115	{"nic", 0, 3, 0, 1},
	116	{"nic", 0, 8, 0, 1},
	117	{"nic", 0, 9, 0, 1},
	118	{"nic", 0, 10, 0, 1},
	119	{"nic", 0, 16, 0, 1},
	120	{"nic", 0, 17, 0, 1},
	121	{"nic", 0, 18, 0, 1},
	122	{"nic", 0, 19, 0, 1},
[33722]	123
	124	/* ISA/LPC controller */
	125	{"lpc", 0, 31, 0, 0},
	126
	127	{ NULL, -1, -1, -1, 0}
	128	};
	129
	130	/* PIIX3 chipset rules */
[85011]	131	static const DeviceAssignmentRule g_aPiix3Rules[] =
[33722]	132	{
	133	{"piix3ide", 0, 1, 1, 0},
[42826]	134	{"ahci", 0, 13, 0, 1},
[85007]	135	{"lsilogic", 0, 20, 0, 1},
[33722]	136	{"pcibridge", 0, 24, 0, 0},
	137	{"pcibridge", 0, 25, 0, 0},
	138	{ NULL, -1, -1, -1, 0}
	139	};
	140
	141
	142	/* ICH9 chipset rules */
[85011]	143	static const DeviceAssignmentRule g_aIch9Rules[] =
[33722]	144	{
	145	/* Host Controller */
	146	{"i82801", 0, 30, 0, 0},
	147
	148	/* Those are functions of LPC at 00:1e:00 */
	149	/**
	150	* Please note, that for devices being functions, like we do here, device 0
	151	* must be multifunction, i.e. have header type 0x80. Our LPC device is.
	152	* Alternative approach is to assign separate slot to each device.
	153	*/
[34266]	154	{"piix3ide", 0, 31, 1, 2},
	155	{"ahci", 0, 31, 2, 2},
	156	{"smbus", 0, 31, 3, 2},
	157	{"usb-ohci", 0, 31, 4, 2},
	158	{"usb-ehci", 0, 31, 5, 2},
	159	{"thermal", 0, 31, 6, 2},
[33722]	160
	161	/* to make sure rule never used before rules assigning devices on it */
	162	{"ich9pcibridge", 0, 24, 0, 10},
	163	{"ich9pcibridge", 0, 25, 0, 10},
[70238]	164	{"ich9pcibridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
	165	{"ich9pcibridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
	166	{"ich9pcibridge", 4, 24, 0, 8}, /* places), so make sure that nested */
	167	{"ich9pcibridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
	168	{"ich9pcibridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
	169	{"ich9pcibridge", 6, 25, 0, 7}, /* everything before starting the VM. */
	170	{"ich9pcibridge", 8, 24, 0, 6},
	171	{"ich9pcibridge", 8, 25, 0, 6},
	172	{"ich9pcibridge", 10, 24, 0, 5},
	173	{"ich9pcibridge", 10, 25, 0, 5},
[33907]	174
	175	/* Storage controllers */
	176	{"ahci", 1, 0, 0, 0},
	177	{"ahci", 1, 1, 0, 0},
	178	{"ahci", 1, 2, 0, 0},
	179	{"ahci", 1, 3, 0, 0},
	180	{"ahci", 1, 4, 0, 0},
	181	{"ahci", 1, 5, 0, 0},
	182	{"ahci", 1, 6, 0, 0},
	183	{"lsilogic", 1, 7, 0, 0},
	184	{"lsilogic", 1, 8, 0, 0},
	185	{"lsilogic", 1, 9, 0, 0},
	186	{"lsilogic", 1, 10, 0, 0},
	187	{"lsilogic", 1, 11, 0, 0},
	188	{"lsilogic", 1, 12, 0, 0},
	189	{"lsilogic", 1, 13, 0, 0},
	190	{"buslogic", 1, 14, 0, 0},
	191	{"buslogic", 1, 15, 0, 0},
	192	{"buslogic", 1, 16, 0, 0},
	193	{"buslogic", 1, 17, 0, 0},
	194	{"buslogic", 1, 18, 0, 0},
	195	{"buslogic", 1, 19, 0, 0},
	196	{"buslogic", 1, 20, 0, 0},
	197	{"lsilogicsas", 1, 21, 0, 0},
	198	{"lsilogicsas", 1, 26, 0, 0},
	199	{"lsilogicsas", 1, 27, 0, 0},
	200	{"lsilogicsas", 1, 28, 0, 0},
	201	{"lsilogicsas", 1, 29, 0, 0},
	202	{"lsilogicsas", 1, 30, 0, 0},
	203	{"lsilogicsas", 1, 31, 0, 0},
	204
	205	/* NICs */
	206	{"nic", 2, 0, 0, 0},
	207	{"nic", 2, 1, 0, 0},
	208	{"nic", 2, 2, 0, 0},
	209	{"nic", 2, 3, 0, 0},
	210	{"nic", 2, 4, 0, 0},
	211	{"nic", 2, 5, 0, 0},
	212	{"nic", 2, 6, 0, 0},
	213	{"nic", 2, 7, 0, 0},
	214	{"nic", 2, 8, 0, 0},
	215	{"nic", 2, 9, 0, 0},
	216	{"nic", 2, 10, 0, 0},
	217	{"nic", 2, 11, 0, 0},
	218	{"nic", 2, 12, 0, 0},
	219	{"nic", 2, 13, 0, 0},
	220	{"nic", 2, 14, 0, 0},
	221	{"nic", 2, 15, 0, 0},
	222	{"nic", 2, 16, 0, 0},
	223	{"nic", 2, 17, 0, 0},
	224	{"nic", 2, 18, 0, 0},
	225	{"nic", 2, 19, 0, 0},
	226	{"nic", 2, 20, 0, 0},
	227	{"nic", 2, 21, 0, 0},
	228	{"nic", 2, 26, 0, 0},
	229	{"nic", 2, 27, 0, 0},
	230	{"nic", 2, 28, 0, 0},
	231	{"nic", 2, 29, 0, 0},
	232	{"nic", 2, 30, 0, 0},
	233	{"nic", 2, 31, 0, 0},
	234
[78509]	235	/* Storage controller #2 (NVMe, virtio-scsi) */
[63747]	236	{"nvme", 3, 0, 0, 0},
	237	{"nvme", 3, 1, 0, 0},
	238	{"nvme", 3, 2, 0, 0},
	239	{"nvme", 3, 3, 0, 0},
	240	{"nvme", 3, 4, 0, 0},
	241	{"nvme", 3, 5, 0, 0},
	242	{"nvme", 3, 6, 0, 0},
[78509]	243	{"virtio-scsi", 3, 7, 0, 0},
	244	{"virtio-scsi", 3, 8, 0, 0},
	245	{"virtio-scsi", 3, 9, 0, 0},
	246	{"virtio-scsi", 3, 10, 0, 0},
	247	{"virtio-scsi", 3, 11, 0, 0},
	248	{"virtio-scsi", 3, 12, 0, 0},
	249	{"virtio-scsi", 3, 13, 0, 0},
[63747]	250
[33722]	251	{ NULL, -1, -1, -1, 0}
	252	};
	253
[85007]	254
[101473]	255	/* Virtual Armv8 platform chipset rules */
	256	static const DeviceAssignmentRule g_aArmv8Rules[] =
	257	{
	258	/* VGA controller */
	259	{"vga", 0, 0, 0, 0},
	260
	261	/* VMM device */
	262	{"VMMDev", 0, 1, 0, 0},
	263
	264	/* Audio controllers */
	265	{"ichac97", 0, 2, 0, 0},
	266	{"hda", 0, 2, 0, 0},
	267
	268	/* Storage controllers */
	269	{"virtio-scsi", 0, 3, 0, 1},
	270	{"nvme", 0, 4, 0, 1},
	271	{"ahci", 0, 16, 0, 1},
	272	{"lsilogicsas", 0, 17, 0, 1},
	273
	274	/* USB controllers */
	275	{"usb-ehci", 0, 5, 0, 0},
	276	{"usb-xhci", 0, 6, 0, 0},
	277	{"usb-ohci", 0, 7, 0, 0},
	278
	279	/* Network controllers */
	280	{"nic", 0, 8, 0, 1},
	281	{"nic", 0, 9, 0, 1},
	282	{"nic", 0, 10, 0, 1},
	283	{"nic", 0, 11, 0, 1},
	284	{"nic", 0, 12, 0, 1},
	285	{"nic", 0, 13, 0, 1},
	286	{"nic", 0, 14, 0, 1},
	287	{"nic", 0, 15, 0, 1},
	288
[101480]	289	/* to make sure rule never used before rules assigning devices on it */
	290	{"pci-generic-ecam-bridge", 0, 24, 0, 10},
	291	{"pci-generic-ecam-bridge", 0, 25, 0, 10},
	292	{"pci-generic-ecam-bridge", 2, 24, 0, 9}, /* Bridges must be instantiated depth */
	293	{"pci-generic-ecam-bridge", 2, 25, 0, 9}, /* first (assumption in PDM and other */
	294	{"pci-generic-ecam-bridge", 4, 24, 0, 8}, /* places), so make sure that nested */
	295	{"pci-generic-ecam-bridge", 4, 25, 0, 8}, /* bridges are added to the last bridge */
	296	{"pci-generic-ecam-bridge", 6, 24, 0, 7}, /* only, avoiding the need to re-sort */
	297	{"pci-generic-ecam-bridge", 6, 25, 0, 7}, /* everything before starting the VM. */
	298	{"pci-generic-ecam-bridge", 8, 24, 0, 6},
	299	{"pci-generic-ecam-bridge", 8, 25, 0, 6},
	300	{"pci-generic-ecam-bridge", 10, 24, 0, 5},
	301	{"pci-generic-ecam-bridge", 10, 25, 0, 5},
	302
	303	/* Storage controllers */
	304	{"ahci", 1, 0, 0, 0},
	305	{"ahci", 1, 1, 0, 0},
	306	{"ahci", 1, 2, 0, 0},
	307	{"ahci", 1, 3, 0, 0},
	308	{"ahci", 1, 4, 0, 0},
	309	{"ahci", 1, 5, 0, 0},
	310	{"ahci", 1, 6, 0, 0},
	311	{"lsilogic", 1, 7, 0, 0},
	312	{"lsilogic", 1, 8, 0, 0},
	313	{"lsilogic", 1, 9, 0, 0},
	314	{"lsilogic", 1, 10, 0, 0},
	315	{"lsilogic", 1, 11, 0, 0},
	316	{"lsilogic", 1, 12, 0, 0},
	317	{"lsilogic", 1, 13, 0, 0},
	318	{"buslogic", 1, 14, 0, 0},
	319	{"buslogic", 1, 15, 0, 0},
	320	{"buslogic", 1, 16, 0, 0},
	321	{"buslogic", 1, 17, 0, 0},
	322	{"buslogic", 1, 18, 0, 0},
	323	{"buslogic", 1, 19, 0, 0},
	324	{"buslogic", 1, 20, 0, 0},
	325	{"lsilogicsas", 1, 21, 0, 0},
	326	{"lsilogicsas", 1, 26, 0, 0},
	327	{"lsilogicsas", 1, 27, 0, 0},
	328	{"lsilogicsas", 1, 28, 0, 0},
	329	{"lsilogicsas", 1, 29, 0, 0},
	330	{"lsilogicsas", 1, 30, 0, 0},
	331	{"lsilogicsas", 1, 31, 0, 0},
	332
	333	/* NICs */
	334	{"nic", 2, 0, 0, 0},
	335	{"nic", 2, 1, 0, 0},
	336	{"nic", 2, 2, 0, 0},
	337	{"nic", 2, 3, 0, 0},
	338	{"nic", 2, 4, 0, 0},
	339	{"nic", 2, 5, 0, 0},
	340	{"nic", 2, 6, 0, 0},
	341	{"nic", 2, 7, 0, 0},
	342	{"nic", 2, 8, 0, 0},
	343	{"nic", 2, 9, 0, 0},
	344	{"nic", 2, 10, 0, 0},
	345	{"nic", 2, 11, 0, 0},
	346	{"nic", 2, 12, 0, 0},
	347	{"nic", 2, 13, 0, 0},
	348	{"nic", 2, 14, 0, 0},
	349	{"nic", 2, 15, 0, 0},
	350	{"nic", 2, 16, 0, 0},
	351	{"nic", 2, 17, 0, 0},
	352	{"nic", 2, 18, 0, 0},
	353	{"nic", 2, 19, 0, 0},
	354	{"nic", 2, 20, 0, 0},
	355	{"nic", 2, 21, 0, 0},
	356	{"nic", 2, 26, 0, 0},
	357	{"nic", 2, 27, 0, 0},
	358	{"nic", 2, 28, 0, 0},
	359	{"nic", 2, 29, 0, 0},
	360	{"nic", 2, 30, 0, 0},
	361	{"nic", 2, 31, 0, 0},
	362
	363	/* Storage controller #2 (NVMe, virtio-scsi) */
	364	{"nvme", 3, 0, 0, 0},
	365	{"nvme", 3, 1, 0, 0},
	366	{"nvme", 3, 2, 0, 0},
	367	{"nvme", 3, 3, 0, 0},
	368	{"nvme", 3, 4, 0, 0},
	369	{"nvme", 3, 5, 0, 0},
	370	{"nvme", 3, 6, 0, 0},
	371	{"virtio-scsi", 3, 7, 0, 0},
	372	{"virtio-scsi", 3, 8, 0, 0},
	373	{"virtio-scsi", 3, 9, 0, 0},
	374	{"virtio-scsi", 3, 10, 0, 0},
	375	{"virtio-scsi", 3, 11, 0, 0},
	376	{"virtio-scsi", 3, 12, 0, 0},
	377	{"virtio-scsi", 3, 13, 0, 0},
	378
[101473]	379	{ NULL, -1, -1, -1, 0}
	380	};
	381
	382
[85007]	383	#ifdef VBOX_WITH_IOMMU_AMD
	384	/*
	385	* AMD IOMMU and LSI Logic controller rules.
	386	*
	387	* Since the PCI slot (BDF=00:20.0) of the LSI Logic controller
	388	* conflicts with the SB I/O APIC, we assign the LSI Logic controller
	389	* to device number 23 when the VM is configured for an AMD IOMMU.
	390	*/
[88333]	391	static const DeviceAssignmentRule g_aIch9IommuAmdRules[] =
[85007]	392	{
	393	/* AMD IOMMU. */
[86733]	394	{"iommu-amd", 0, 0, 0, 0},
[85007]	395	/* AMD IOMMU: Reserved for southbridge I/O APIC. */
	396	{"sb-ioapic", 0, 20, 0, 0},
	397
	398	/* Storage controller */
	399	{"lsilogic", 0, 23, 0, 1},
	400	{ NULL, -1, -1, -1, 0}
	401	};
	402	#endif
	403
[88333]	404	#ifdef VBOX_WITH_IOMMU_INTEL
	405	/*
	406	* Intel IOMMU.
	407	* The VT-d misc, address remapping, system management device is
[88484]	408	* located at BDF 0:5:0 on real hardware but we use 0:1:0 since that
	409	* slot isn't used for anything else.
	410	*
	411	* While we could place the I/O APIC anywhere, we keep it consistent
	412	* with the AMD IOMMU and we assign the LSI Logic controller to
	413	* device number 23 (and I/O APIC at device 20).
[88333]	414	*/
	415	static const DeviceAssignmentRule g_aIch9IommuIntelRules[] =
	416	{
	417	/* Intel IOMMU. */
[88484]	418	{"iommu-intel", 0, 1, 0, 0},
	419	/* Intel IOMMU: Reserved for I/O APIC. */
	420	{"sb-ioapic", 0, 20, 0, 0},
[88333]	421
	422	/* Storage controller */
[88484]	423	{"lsilogic", 0, 23, 0, 1},
[88333]	424	{ NULL, -1, -1, -1, 0}
	425	};
	426	#endif
	427
[85007]	428	/* LSI Logic Controller. */
[85011]	429	static const DeviceAssignmentRule g_aIch9LsiRules[] =
[85007]	430	{
	431	/* Storage controller */
	432	{"lsilogic", 0, 20, 0, 1},
	433	{ NULL, -1, -1, -1, 0}
	434	};
	435
[33722]	436	/* Aliasing rules */
[85011]	437	static const DeviceAliasRule g_aDeviceAliases[] =
[33722]	438	{
[33907]	439	{"e1000", "nic"},
	440	{"pcnet", "nic"},
	441	{"virtio-net", "nic"},
	442	{"ahci", "storage"},
	443	{"lsilogic", "storage"},
	444	{"buslogic", "storage"},
[57524]	445	{"lsilogicsas", "storage"},
[78509]	446	{"nvme", "storage"},
	447	{"virtio-scsi", "storage"}
[33722]	448	};
	449
[93444]	450
	451
	452	/**
	453	* Bus assignment manage state data.
	454	* @internal
	455	*/
[33687]	456	struct BusAssignmentManager::State
	457	{
[42551]	458	struct PCIDeviceRecord
[33687]	459	{
[36107]	460	char szDevName[32];
[42551]	461	PCIBusAddress HostAddress;
[33688]	462
[70238]	463	PCIDeviceRecord(const char *pszName, PCIBusAddress aHostAddress)
[36107]	464	{
	465	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
	466	this->HostAddress = aHostAddress;
	467	}
	468
[70238]	469	PCIDeviceRecord(const char *pszName)
[33688]	470	{
[36107]	471	RTStrCopy(this->szDevName, sizeof(szDevName), pszName);
[33688]	472	}
[33690]	473
[42551]	474	bool operator<(const PCIDeviceRecord &a) const
[33690]	475	{
[34123]	476	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) < 0;
[33690]	477	}
	478
[42551]	479	bool operator==(const PCIDeviceRecord &a) const
[33690]	480	{
[34123]	481	return RTStrNCmp(szDevName, a.szDevName, sizeof(szDevName)) == 0;
[33690]	482	}
[33687]	483	};
	484
[61009]	485	typedef std::map<PCIBusAddress,PCIDeviceRecord> PCIMap;
[42551]	486	typedef std::vector<PCIBusAddress> PCIAddrList;
[61009]	487	typedef std::vector<const DeviceAssignmentRule *> PCIRulesList;
	488	typedef std::map<PCIDeviceRecord,PCIAddrList> ReversePCIMap;
[33687]	489
	490	volatile int32_t cRefCnt;
	491	ChipsetType_T mChipsetType;
[70238]	492	const char * mpszBridgeName;
[87242]	493	IommuType_T mIommuType;
[42551]	494	PCIMap mPCIMap;
	495	ReversePCIMap mReversePCIMap;
[93444]	496	PCVMMR3VTABLE mpVMM;
[33687]	497
	498	State()
[93444]	499	: cRefCnt(1), mChipsetType(ChipsetType_Null), mpszBridgeName("unknownbridge"), mpVMM(NULL)
[33687]	500	{}
	501	~State()
	502	{}
	503
[93444]	504	HRESULT init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType);
[33687]	505
[70238]	506	HRESULT record(const char *pszName, PCIBusAddress& GuestAddress, PCIBusAddress HostAddress);
	507	HRESULT autoAssign(const char *pszName, PCIBusAddress& Address);
[42551]	508	bool checkAvailable(PCIBusAddress& Address);
[70238]	509	bool findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address);
[33722]	510
[70238]	511	const char findAlias(const char pszName);
	512	void addMatchingRules(const char *pszName, PCIRulesList& aList);
[61009]	513	void listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached);
[33687]	514	};
	515
[93444]	516
	517	HRESULT BusAssignmentManager::State::init(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
[33687]	518	{
[93444]	519	mpVMM = pVMM;
	520
[88333]	521	if (iommuType != IommuType_None)
	522	{
	523	#if defined(VBOX_WITH_IOMMU_AMD) && defined(VBOX_WITH_IOMMU_INTEL)
	524	Assert(iommuType == IommuType_AMD \|\| iommuType == IommuType_Intel);
	525	#elif defined(VBOX_WITH_IOMMU_AMD)
	526	Assert(iommuType == IommuType_AMD);
	527	#elif defined(VBOX_WITH_IOMMU_INTEL)
	528	Assert(iommuType == IommuType_Intel);
	529	#endif
	530	}
[87242]	531
[33687]	532	mChipsetType = chipsetType;
[87242]	533	mIommuType = iommuType;
[70238]	534	switch (chipsetType)
	535	{
	536	case ChipsetType_PIIX3:
	537	mpszBridgeName = "pcibridge";
	538	break;
	539	case ChipsetType_ICH9:
	540	mpszBridgeName = "ich9pcibridge";
	541	break;
[101480]	542	case ChipsetType_ARMv8Virtual:
	543	mpszBridgeName = "pci-generic-ecam-bridge";
	544	break;
[70238]	545	default:
	546	mpszBridgeName = "unknownbridge";
	547	AssertFailed();
	548	break;
	549	}
[33687]	550	return S_OK;
	551	}
	552
[70238]	553	HRESULT BusAssignmentManager::State::record(const char *pszName, PCIBusAddress& Address, PCIBusAddress HostAddress)
[33688]	554	{
[42551]	555	PCIDeviceRecord devRec(pszName, HostAddress);
[33690]	556
	557	/* Remember address -> device mapping */
[42551]	558	mPCIMap.insert(PCIMap::value_type(Address, devRec));
[33690]	559
[42551]	560	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
	561	if (it == mReversePCIMap.end())
[33690]	562	{
[42551]	563	mReversePCIMap.insert(ReversePCIMap::value_type(devRec, PCIAddrList()));
	564	it = mReversePCIMap.find(devRec);
[33690]	565	}
	566
	567	/* Remember device name -> addresses mapping */
	568	it->second.push_back(Address);
	569
[33688]	570	return S_OK;
	571	}
	572
[85007]	573	bool BusAssignmentManager::State::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
[33690]	574	{
[42551]	575	PCIDeviceRecord devRec(pszDevName);
[33690]	576
[42551]	577	ReversePCIMap::iterator it = mReversePCIMap.find(devRec);
	578	if (it == mReversePCIMap.end())
[33690]	579	return false;
	580
	581	if (iInstance >= (int)it->second.size())
	582	return false;
	583
	584	Address = it->second[iInstance];
	585	return true;
	586	}
	587
[70238]	588	void BusAssignmentManager::State::addMatchingRules(const char *pszName, PCIRulesList& aList)
[33722]	589	{
	590	size_t iRuleset, iRule;
[85011]	591	const DeviceAssignmentRule *aArrays[3] = {g_aGenericRules, NULL, NULL};
[33722]	592
	593	switch (mChipsetType)
	594	{
	595	case ChipsetType_PIIX3:
[85011]	596	aArrays[1] = g_aPiix3Rules;
[33722]	597	break;
	598	case ChipsetType_ICH9:
[85007]	599	{
[85011]	600	aArrays[1] = g_aIch9Rules;
[85007]	601	#ifdef VBOX_WITH_IOMMU_AMD
[87242]	602	if (mIommuType == IommuType_AMD)
[88333]	603	aArrays[2] = g_aIch9IommuAmdRules;
[85007]	604	else
	605	#endif
[88333]	606	#ifdef VBOX_WITH_IOMMU_INTEL
	607	if (mIommuType == IommuType_Intel)
	608	aArrays[2] = g_aIch9IommuIntelRules;
	609	else
	610	#endif
[85007]	611	{
[85011]	612	aArrays[2] = g_aIch9LsiRules;
[85007]	613	}
[33722]	614	break;
[85007]	615	}
[101473]	616	case ChipsetType_ARMv8Virtual:
	617	aArrays[0] = g_aArmv8Rules;
	618	break;
[33722]	619	default:
[70238]	620	AssertFailed();
[33722]	621	break;
	622	}
	623
	624	for (iRuleset = 0; iRuleset < RT_ELEMENTS(aArrays); iRuleset++)
	625	{
	626	if (aArrays[iRuleset] == NULL)
	627	continue;
	628
	629	for (iRule = 0; aArrays[iRuleset][iRule].pszName != NULL; iRule++)
	630	{
[34123]	631	if (RTStrCmp(pszName, aArrays[iRuleset][iRule].pszName) == 0)
[33722]	632	aList.push_back(&aArrays[iRuleset][iRule]);
	633	}
	634	}
	635	}
	636
[70238]	637	const char BusAssignmentManager::State::findAlias(const char pszDev)
[33722]	638	{
[85011]	639	for (size_t iAlias = 0; iAlias < RT_ELEMENTS(g_aDeviceAliases); iAlias++)
[33722]	640	{
[85011]	641	if (strcmp(pszDev, g_aDeviceAliases[iAlias].pszDevName) == 0)
	642	return g_aDeviceAliases[iAlias].pszDevAlias;
[33722]	643	}
	644	return NULL;
	645	}
	646
[70238]	647	static bool RuleComparator(const DeviceAssignmentRule r1, const DeviceAssignmentRule r2)
[33722]	648	{
	649	return (r1->iPriority > r2->iPriority);
	650	}
	651
[70238]	652	HRESULT BusAssignmentManager::State::autoAssign(const char *pszName, PCIBusAddress& Address)
[33687]	653	{
[42551]	654	PCIRulesList matchingRules;
[33722]	655
[85007]	656	addMatchingRules(pszName, matchingRules);
[70238]	657	const char *pszAlias = findAlias(pszName);
[33722]	658	if (pszAlias)
	659	addMatchingRules(pszAlias, matchingRules);
	660
	661	AssertMsg(matchingRules.size() > 0, ("No rule for %s(%s)\n", pszName, pszAlias));
	662
[34266]	663	stable_sort(matchingRules.begin(), matchingRules.end(), RuleComparator);
[33722]	664
	665	for (size_t iRule = 0; iRule < matchingRules.size(); iRule++)
	666	{
[70238]	667	const DeviceAssignmentRule *rule = matchingRules[iRule];
[33722]	668
[36630]	669	Address.miBus = rule->iBus;
	670	Address.miDevice = rule->iDevice;
	671	Address.miFn = rule->iFn;
[33722]	672
	673	if (checkAvailable(Address))
	674	return S_OK;
	675	}
[70238]	676	AssertLogRelMsgFailed(("BusAssignmentManager: All possible candidate positions for %s exhausted\n", pszName));
[33722]	677
	678	return E_INVALIDARG;
[33687]	679	}
	680
[42551]	681	bool BusAssignmentManager::State::checkAvailable(PCIBusAddress& Address)
[33687]	682	{
[42551]	683	PCIMap::const_iterator it = mPCIMap.find(Address);
[33688]	684
[42551]	685	return (it == mPCIMap.end());
[33687]	686	}
	687
[61009]	688	void BusAssignmentManager::State::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
[34331]	689	{
[51612]	690	aAttached.resize(mPCIMap.size());
[34331]	691
[51612]	692	size_t i = 0;
[61009]	693	PCIDeviceInfo dev;
[51612]	694	for (PCIMap::const_iterator it = mPCIMap.begin(); it != mPCIMap.end(); ++it, ++i)
[34331]	695	{
[61009]	696	dev.strDeviceName = it->second.szDevName;
	697	dev.guestAddress = it->first;
	698	dev.hostAddress = it->second.HostAddress;
	699	aAttached[i] = dev;
[34331]	700	}
	701	}
	702
[33687]	703	BusAssignmentManager::BusAssignmentManager()
	704	: pState(NULL)
	705	{
	706	pState = new State();
	707	Assert(pState);
	708	}
	709
	710	BusAssignmentManager::~BusAssignmentManager()
	711	{
	712	if (pState)
	713	{
	714	delete pState;
	715	pState = NULL;
	716	}
	717	}
	718
[93444]	719	BusAssignmentManager *BusAssignmentManager::createInstance(PCVMMR3VTABLE pVMM, ChipsetType_T chipsetType, IommuType_T iommuType)
[33687]	720	{
[70238]	721	BusAssignmentManager *pInstance = new BusAssignmentManager();
[93444]	722	pInstance->pState->init(pVMM, chipsetType, iommuType);
[34331]	723	Assert(pInstance);
[33687]	724	return pInstance;
	725	}
	726
	727	void BusAssignmentManager::AddRef()
	728	{
	729	ASMAtomicIncS32(&pState->cRefCnt);
	730	}
[93444]	731
[33687]	732	void BusAssignmentManager::Release()
	733	{
[34044]	734	if (ASMAtomicDecS32(&pState->cRefCnt) == 0)
[33687]	735	delete this;
	736	}
	737
[93444]	738	DECLINLINE(HRESULT) InsertConfigInteger(PCVMMR3VTABLE pVMM, PCFGMNODE pCfg, const char *pszName, uint64_t u64)
[33687]	739	{
[93444]	740	int vrc = pVMM->pfnCFGMR3InsertInteger(pCfg, pszName, u64);
[33687]	741	if (RT_FAILURE(vrc))
	742	return E_INVALIDARG;
	743
	744	return S_OK;
	745	}
	746
[93444]	747	DECLINLINE(HRESULT) InsertConfigNode(PCVMMR3VTABLE pVMM, PCFGMNODE pNode, const char pcszName, PCFGMNODE ppChild)
[70238]	748	{
[93444]	749	int vrc = pVMM->pfnCFGMR3InsertNode(pNode, pcszName, ppChild);
[70238]	750	if (RT_FAILURE(vrc))
	751	return E_INVALIDARG;
	752
	753	return S_OK;
	754	}
	755
	756
	757	HRESULT BusAssignmentManager::assignPCIDeviceImpl(const char *pszDevName,
[36107]	758	PCFGMNODE pCfg,
[42551]	759	PCIBusAddress& GuestAddress,
	760	PCIBusAddress HostAddress,
[36107]	761	bool fGuestAddressRequired)
[33687]	762	{
[94920]	763	HRESULT hrc = S_OK;
[33687]	764
[36107]	765	if (!GuestAddress.valid())
[94920]	766	hrc = pState->autoAssign(pszDevName, GuestAddress);
[33687]	767	else
	768	{
[36107]	769	bool fAvailable = pState->checkAvailable(GuestAddress);
[33687]	770
	771	if (!fAvailable)
	772	{
[36107]	773	if (fGuestAddressRequired)
[94920]	774	hrc = E_ACCESSDENIED;
[33687]	775	else
[94920]	776	hrc = pState->autoAssign(pszDevName, GuestAddress);
[33687]	777	}
	778	}
	779
[94920]	780	if (FAILED(hrc))
	781	return hrc;
[33687]	782
[36107]	783	Assert(GuestAddress.valid() && pState->checkAvailable(GuestAddress));
[33687]	784
[94920]	785	hrc = pState->record(pszDevName, GuestAddress, HostAddress);
	786	if (FAILED(hrc))
	787	return hrc;
[33688]	788
[93444]	789	PCVMMR3VTABLE const pVMM = pState->mpVMM;
[85007]	790	if (pCfg)
	791	{
[94920]	792	hrc = InsertConfigInteger(pVMM, pCfg, "PCIBusNo", GuestAddress.miBus);
	793	if (FAILED(hrc))
	794	return hrc;
	795	hrc = InsertConfigInteger(pVMM, pCfg, "PCIDeviceNo", GuestAddress.miDevice);
	796	if (FAILED(hrc))
	797	return hrc;
	798	hrc = InsertConfigInteger(pVMM, pCfg, "PCIFunctionNo", GuestAddress.miFn);
	799	if (FAILED(hrc))
	800	return hrc;
[85007]	801	}
[33687]	802
[70238]	803	/* Check if the bus is still unknown, i.e. the bridge to it is missing */
	804	if ( GuestAddress.miBus > 0
	805	&& !hasPCIDevice(pState->mpszBridgeName, GuestAddress.miBus - 1))
	806	{
[93444]	807	PCFGMNODE pDevices = pVMM->pfnCFGMR3GetParent(pVMM->pfnCFGMR3GetParent(pCfg));
[70238]	808	AssertLogRelMsgReturn(pDevices, ("BusAssignmentManager: cannot find base device configuration\n"), E_UNEXPECTED);
[101480]	809	PCFGMNODE pBridges = pVMM->pfnCFGMR3GetChild(pDevices, pState->mpszBridgeName);
[70238]	810	AssertLogRelMsgReturn(pBridges, ("BusAssignmentManager: cannot find bridge configuration base\n"), E_UNEXPECTED);
	811
	812	/* Device should be on a not yet existing bus, add it automatically */
	813	for (int iBridge = 0; iBridge <= GuestAddress.miBus - 1; iBridge++)
	814	{
	815	if (!hasPCIDevice(pState->mpszBridgeName, iBridge))
	816	{
	817	PCIBusAddress BridgeGuestAddress;
[94920]	818	hrc = pState->autoAssign(pState->mpszBridgeName, BridgeGuestAddress);
	819	if (FAILED(hrc))
	820	return hrc;
[70238]	821	if (BridgeGuestAddress.miBus > iBridge)
	822	AssertLogRelMsgFailedReturn(("BusAssignmentManager: cannot create bridge for bus %i because the possible parent bus positions are exhausted\n", iBridge + 1), E_UNEXPECTED);
	823
	824	PCFGMNODE pInst;
[93444]	825	InsertConfigNode(pVMM, pBridges, Utf8StrFmt("%d", iBridge).c_str(), &pInst);
	826	InsertConfigInteger(pVMM, pInst, "Trusted", 1);
[94920]	827	hrc = assignPCIDevice(pState->mpszBridgeName, pInst);
	828	if (FAILED(hrc))
	829	return hrc;
[70238]	830	}
	831	}
	832	}
	833
[33687]	834	return S_OK;
	835	}
[33690]	836
	837
[70238]	838	bool BusAssignmentManager::findPCIAddress(const char *pszDevName, int iInstance, PCIBusAddress& Address)
[33690]	839	{
[42551]	840	return pState->findPCIAddress(pszDevName, iInstance, Address);
[33690]	841	}
[61009]	842	void BusAssignmentManager::listAttachedPCIDevices(std::vector<PCIDeviceInfo> &aAttached)
[34331]	843	{
[51612]	844	pState->listAttachedPCIDevices(aAttached);
[34331]	845	}

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source: vbox/trunk/src/VBox/Main/src-client/BusAssignmentManager.cpp

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