VirtualBox

source: vbox/trunk/src/VBox/Devices/PC/DevDMA.cpp@ 40754

Last change on this file since 40754 was 38221, checked in by vboxsync, 13 years ago

Fixed assertion.
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File size: 30.9 KB
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1/* $Id: DevDMA.cpp 38221 2011-07-28 14:11:14Z vboxsync $ */
2/** @file
3 * DevDMA - DMA Controller Device.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 * --------------------------------------------------------------------
17 *
18 * This code is loosely based on:
19 *
20 * QEMU DMA emulation
21 *
22 * Copyright (c) 2003 Vassili Karpov (malc)
23 *
24 * Permission is hereby granted, free of charge, to any person obtaining a copy
25 * of this software and associated documentation files (the "Software"), to deal
26 * in the Software without restriction, including without limitation the rights
27 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
28 * copies of the Software, and to permit persons to whom the Software is
29 * furnished to do so, subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice shall be included in
32 * all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
35 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
36 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
38 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
39 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
40 * THE SOFTWARE.
41 */
42
43/*******************************************************************************
44* Header Files *
45*******************************************************************************/
46#define LOG_GROUP LOG_GROUP_DEV_DMA
47#include <VBox/vmm/pdmdev.h>
48#include <VBox/err.h>
49
50#include <VBox/log.h>
51#include <iprt/assert.h>
52#include <iprt/string.h>
53
54#include <stdio.h>
55#include <stdlib.h>
56
57#include "VBoxDD.h"
58
59
60/* DMA Overview and notes
61 *
62 * Modern PCs typically emulate AT-compatible DMA. The IBM PC/AT used dual
63 * cascaded 8237A DMA controllers, augmented with a 74LS612 memory mapper.
64 * The 8237As are 8-bit parts, only capable of addressing up to 64KB; the
65 * 74LS612 extends addressing to 24 bits. That leads to well known and
66 * inconvenient DMA limitations:
67 * - DMA can only access physical memory under the 16MB line
68 * - DMA transfers must occur within a 64KB/128KB 'page'
69 *
70 * The 16-bit DMA controller added in the PC/AT shifts all 8237A addresses
71 * left by one, including the control registers addresses. The DMA register
72 * offsets (except for the page registers) are therefore "double spaced".
73 *
74 * Due to the address shifting, the DMA controller decodes more addresses
75 * than are usually documented, with aliasing. See the ICH8 datasheet.
76 *
77 * In the IBM PC and PC/XT, DMA channel 0 was used for memory refresh, thus
78 * preventing the use of memory-to-memory DMA transfers (which use channels
79 * 0 and 1). In the PC/AT, memory-to-memory DMA was theoretically possible.
80 * However, it would transfer a single byte at a time, while the CPU can
81 * transfer two (on a 286) or four (on a 386+) bytes at a time. On many
82 * compatibles, memory-to-memory DMA is not even implemented at all, and
83 * therefore has no practical use.
84 *
85 * Auto-init mode is handled implicitly; a device's transfer handler may
86 * return an end count lower than the start count.
87 *
88 * Naming convention: 'channel' refers to a system-wide DMA channel (0-7)
89 * while 'chidx' refers to a DMA channel index within a controller (0-3).
90 *
91 * References:
92 * - IBM Personal Computer AT Technical Reference, 1984
93 * - Intel 8237A-5 Datasheet, 1993
94 * - Frank van Gilluwe, The Undocumented PC, 1994
95 * - OPTi 82C206 Data Book, 1996 (or Chips & Tech 82C206)
96 * - Intel ICH8 Datasheet, 2007
97 */
98
99
100/* Saved state versions. */
101#define DMA_SAVESTATE_OLD 1 /* The original saved state. */
102#define DMA_SAVESTATE_CURRENT 2 /* The new and improved saved state. */
103
104/* State information for a single DMA channel. */
105typedef struct {
106 void *pvUser; /* User specific context. */
107 PFNDMATRANSFERHANDLER pfnXferHandler; /* Transfer handler for channel. */
108 uint16_t u16BaseAddr; /* Base address for transfers. */
109 uint16_t u16BaseCount; /* Base count for transfers. */
110 uint16_t u16CurAddr; /* Current address. */
111 uint16_t u16CurCount; /* Current count. */
112 uint8_t u8Mode; /* Channel mode. */
113} DMAChannel;
114
115/* State information for a DMA controller (DMA8 or DMA16). */
116typedef struct {
117 DMAChannel ChState[4]; /* Per-channel state. */
118 uint8_t au8Page[8]; /* Page registers (A16-A23). */
119 uint8_t au8PageHi[8]; /* High page registers (A24-A31). */
120 uint8_t u8Command; /* Command register. */
121 uint8_t u8Status; /* Status register. */
122 uint8_t u8Mask; /* Mask register. */
123 uint8_t u8Temp; /* Temporary (mem/mem) register. */
124 uint8_t u8ModeCtr; /* Mode register counter for reads. */
125 bool bHiByte; /* Byte pointer (T/F -> high/low). */
126 uint32_t is16bit; /* True for 16-bit DMA. */
127} DMAControl;
128
129/* Complete DMA state information. */
130typedef struct {
131 PPDMDEVINS pDevIns; /* Device instance. */
132 PCPDMDMACHLP pHlp; /* PDM DMA helpers. */
133 DMAControl DMAC[2]; /* Two DMA controllers. */
134} DMAState;
135
136/* DMA command register bits. */
137enum {
138 CMD_MEMTOMEM = 0x01, /* Enable mem-to-mem trasfers. */
139 CMD_ADRHOLD = 0x02, /* Address hold for mem-to-mem. */
140 CMD_DISABLE = 0x04, /* Disable controller. */
141 CMD_COMPRTIME = 0x08, /* Compressed timing. */
142 CMD_ROTPRIO = 0x10, /* Rotating priority. */
143 CMD_EXTWR = 0x20, /* Extended write. */
144 CMD_DREQHI = 0x40, /* DREQ is active high if set. */
145 CMD_DACKHI = 0x80, /* DACK is active high if set. */
146 CMD_UNSUPPORTED = CMD_MEMTOMEM | CMD_ADRHOLD | CMD_COMPRTIME
147 | CMD_EXTWR | CMD_DREQHI | CMD_DACKHI
148};
149
150/* DMA control register offsets for read accesses. */
151enum {
152 CTL_R_STAT, /* Read status registers. */
153 CTL_R_DMAREQ, /* Read DRQ register. */
154 CTL_R_CMD, /* Read command register. */
155 CTL_R_MODE, /* Read mode register. */
156 CTL_R_SETBPTR, /* Set byte pointer flip-flop. */
157 CTL_R_TEMP, /* Read temporary register. */
158 CTL_R_CLRMODE, /* Clear mode register counter. */
159 CTL_R_MASK /* Read all DRQ mask bits. */
160};
161
162/* DMA control register offsets for read accesses. */
163enum {
164 CTL_W_CMD, /* Write command register. */
165 CTL_W_DMAREQ, /* Write DRQ register. */
166 CTL_W_MASKONE, /* Write single DRQ mask bit. */
167 CTL_W_MODE, /* Write mode register. */
168 CTL_W_CLRBPTR, /* Clear byte pointer flip-flop. */
169 CTL_W_MASTRCLR, /* Master clear. */
170 CTL_W_CLRMASK, /* Clear all DRQ mask bits. */
171 CTL_W_MASK /* Write all DRQ mask bits. */
172};
173
174/* Convert DMA channel number (0-7) to controller number (0-1). */
175#define DMACH2C(c) (c < 4 ? 0 : 1)
176
177static int dmaChannelMap[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
178/* Map a DMA page register offset (0-7) to channel index (0-3). */
179#define DMAPG2CX(c) (dmaChannelMap[c])
180
181static int dmaMapChannel[4] = {7, 3, 1, 2};
182/* Map a channel index (0-3) to DMA page register offset (0-7). */
183#define DMACX2PG(c) (dmaMapChannel[c])
184/* Map a channel number (0-7) to DMA page register offset (0-7). */
185#define DMACH2PG(c) (dmaMapChannel[c & 3])
186
187/* Test the decrement bit of mode register. */
188#define IS_MODE_DEC(c) ((c) & 0x20)
189/* Test the auto-init bit of mode register. */
190#define IS_MODE_AI(c) ((c) & 0x10)
191
192/* Perform a master clear (reset) on a DMA controller. */
193static void dmaClear(DMAControl *dc)
194{
195 dc->u8Command = 0;
196 dc->u8Status = 0;
197 dc->u8Temp = 0;
198 dc->u8ModeCtr = 0;
199 dc->bHiByte = false;
200 dc->u8Mask = ~0;
201}
202
203/* Read the byte pointer and flip it. */
204static inline bool dmaReadBytePtr(DMAControl *dc)
205{
206 bool bHighByte;
207
208 bHighByte = !!dc->bHiByte;
209 dc->bHiByte ^= 1;
210 return bHighByte;
211}
212
213/* DMA address registers writes and reads. */
214
215static DECLCALLBACK(int) dmaWriteAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
216 uint32_t u32, unsigned cb)
217{
218 if (cb == 1)
219 {
220 DMAControl *dc = (DMAControl *)pvUser;
221 DMAChannel *ch;
222 int chidx, reg, is_count;
223
224 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
225 reg = (port >> dc->is16bit) & 0x0f;
226 chidx = reg >> 1;
227 is_count = reg & 1;
228 ch = &dc->ChState[chidx];
229 if (dmaReadBytePtr(dc))
230 {
231 /* Write the high byte. */
232 if (is_count)
233 ch->u16BaseCount = RT_MAKE_U16(ch->u16BaseCount, u32);
234 else
235 ch->u16BaseAddr = RT_MAKE_U16(ch->u16BaseAddr, u32);
236
237 ch->u16CurCount = 0;
238 ch->u16CurAddr = ch->u16BaseAddr;
239 }
240 else
241 {
242 /* Write the low byte. */
243 if (is_count)
244 ch->u16BaseCount = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseCount));
245 else
246 ch->u16BaseAddr = RT_MAKE_U16(u32, RT_HIBYTE(ch->u16BaseAddr));
247 }
248 Log2(("dmaWriteAddr: port %#06x, chidx %d, data %#02x\n",
249 port, chidx, u32));
250 }
251 else
252 {
253 /* Likely a guest bug. */
254 Log(("Bad size write to count register %#x (size %d, data %#x)\n",
255 port, cb, u32));
256 }
257 return VINF_SUCCESS;
258}
259
260static DECLCALLBACK(int) dmaReadAddr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
261 uint32_t *pu32, unsigned cb)
262{
263 if (cb == 1)
264 {
265 DMAControl *dc = (DMAControl *)pvUser;
266 DMAChannel *ch;
267 int chidx, reg, val, dir;
268 int bptr;
269
270 reg = (port >> dc->is16bit) & 0x0f;
271 chidx = reg >> 1;
272 ch = &dc->ChState[chidx];
273
274 dir = IS_MODE_DEC(ch->u8Mode) ? -1 : 1;
275 if (reg & 1)
276 val = ch->u16BaseCount - ch->u16CurCount;
277 else
278 val = ch->u16CurAddr + ch->u16CurCount * dir;
279
280 bptr = dmaReadBytePtr(dc);
281 *pu32 = RT_LOBYTE(val >> (bptr * 8));
282
283 Log(("Count read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
284 return VINF_SUCCESS;
285 }
286 else
287 return VERR_IOM_IOPORT_UNUSED;
288}
289
290/* DMA control registers writes and reads. */
291
292static DECLCALLBACK(int) dmaWriteCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
293 uint32_t u32, unsigned cb)
294{
295 if (cb == 1)
296 {
297 DMAControl *dc = (DMAControl *)pvUser;
298 int chidx = 0;
299 int reg;
300
301 reg = ((port >> dc->is16bit) & 0x0f) - 8;
302 Assert((reg >= CTL_W_CMD && reg <= CTL_W_MASK));
303 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
304
305 switch (reg) {
306 case CTL_W_CMD:
307 /* Unsupported commands are entirely ignored. */
308 if (u32 & CMD_UNSUPPORTED)
309 {
310 Log(("DMA command %#x is not supported, ignoring!\n", u32));
311 break;
312 }
313 dc->u8Command = u32;
314 break;
315 case CTL_W_DMAREQ:
316 chidx = u32 & 3;
317 if (u32 & 4)
318 dc->u8Status |= 1 << (chidx + 4);
319 else
320 dc->u8Status &= ~(1 << (chidx + 4));
321 dc->u8Status &= ~(1 << chidx); /* Clear TC for channel. */
322 break;
323 case CTL_W_MASKONE:
324 chidx = u32 & 3;
325 if (u32 & 4)
326 dc->u8Mask |= 1 << chidx;
327 else
328 dc->u8Mask &= ~(1 << chidx);
329 break;
330 case CTL_W_MODE:
331 {
332 int op, opmode;
333
334 chidx = u32 & 3;
335 op = (u32 >> 2) & 3;
336 opmode = (u32 >> 6) & 3;
337 Log2(("chidx %d, op %d, %sauto-init, %screment, opmode %d\n",
338 chidx, op, IS_MODE_AI(u32) ? "" : "no ",
339 IS_MODE_DEC(u32) ? "de" : "in", opmode));
340
341 dc->ChState[chidx].u8Mode = u32;
342 break;
343 }
344 case CTL_W_CLRBPTR:
345 dc->bHiByte = false;
346 break;
347 case CTL_W_MASTRCLR:
348 dmaClear(dc);
349 break;
350 case CTL_W_CLRMASK:
351 dc->u8Mask = 0;
352 break;
353 case CTL_W_MASK:
354 dc->u8Mask = u32;
355 break;
356 default:
357 Assert(0);
358 break;
359 }
360 Log(("dmaWriteCtl: port %#06x, chidx %d, data %#02x\n",
361 port, chidx, u32));
362 }
363 else
364 {
365 /* Likely a guest bug. */
366 Log(("Bad size write to controller register %#x (size %d, data %#x)\n",
367 port, cb, u32));
368 }
369 return VINF_SUCCESS;
370}
371
372static DECLCALLBACK(int) dmaReadCtl(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
373 uint32_t *pu32, unsigned cb)
374{
375 if (cb == 1)
376 {
377 DMAControl *dc = (DMAControl *)pvUser;
378 uint8_t val = 0;
379 int reg;
380
381 reg = ((port >> dc->is16bit) & 0x0f) - 8;
382 Assert((reg >= CTL_R_STAT && reg <= CTL_R_MASK));
383
384 switch (reg) {
385 case CTL_R_STAT:
386 val = dc->u8Status;
387 dc->u8Status &= 0xf0; /* A read clears all TCs. */
388 break;
389 case CTL_R_DMAREQ:
390 val = (dc->u8Status >> 4) | 0xf0;
391 break;
392 case CTL_R_CMD:
393 val = dc->u8Command;
394 break;
395 case CTL_R_MODE:
396 val = dc->ChState[dc->u8ModeCtr].u8Mode | 3;
397 dc->u8ModeCtr = (dc->u8ModeCtr + 1) & 3;
398 case CTL_R_SETBPTR:
399 dc->bHiByte = true;
400 break;
401 case CTL_R_TEMP:
402 val = dc->u8Temp;
403 break;
404 case CTL_R_CLRMODE:
405 dc->u8ModeCtr = 0;
406 break;
407 case CTL_R_MASK:
408 val = dc->u8Mask;
409 break;
410 default:
411 Assert(0);
412 break;
413 }
414
415 Log(("Ctrl read: port %#06x, reg %#04x, data %#x\n", port, reg, val));
416 *pu32 = val;
417
418 return VINF_SUCCESS;
419 }
420 else
421 return VERR_IOM_IOPORT_UNUSED;
422}
423
424/* DMA page registers. There are 16 R/W page registers for compatibility with
425 * the IBM PC/AT; only some of those registers are used for DMA. The page register
426 * accessible via port 80h may be read to insert small delays or used as a scratch
427 * register by a BIOS.
428 */
429static DECLCALLBACK(int) dmaReadPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
430 uint32_t *pu32, unsigned cb)
431{
432 DMAControl *dc = (DMAControl *)pvUser;
433 int reg;
434
435 if (cb == 1)
436 {
437 reg = port & 7;
438 *pu32 = dc->au8Page[reg];
439 Log2(("Read %#x (byte) from page register %#x (channel %d)\n",
440 *pu32, port, DMAPG2CX(reg)));
441 return VINF_SUCCESS;
442 }
443 else if (cb == 2)
444 {
445 reg = port & 7;
446 *pu32 = dc->au8Page[reg] | (dc->au8Page[(reg + 1) & 7] << 8);
447 Log2(("Read %#x (word) from page register %#x (channel %d)\n",
448 *pu32, port, DMAPG2CX(reg)));
449 return VINF_SUCCESS;
450 }
451 else
452 return VERR_IOM_IOPORT_UNUSED;
453}
454
455static DECLCALLBACK(int) dmaWritePage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
456 uint32_t u32, unsigned cb)
457{
458 DMAControl *dc = (DMAControl *)pvUser;
459 int reg;
460
461 if (cb == 1)
462 {
463 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
464 reg = port & 7;
465 dc->au8Page[reg] = u32;
466 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
467 Log2(("Wrote %#x to page register %#x (channel %d)\n",
468 u32, port, DMAPG2CX(reg)));
469 }
470 else if (cb == 2)
471 {
472 Assert(!(u32 & ~0xffff)); /* Check for garbage in high bits. */
473 reg = port & 7;
474 dc->au8Page[reg] = u32;
475 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
476 reg = (port + 1) & 7;
477 dc->au8Page[reg] = u32 >> 8;
478 dc->au8PageHi[reg] = 0; /* Corresponding high page cleared. */
479 }
480 else
481 {
482 /* Likely a guest bug. */
483 Log(("Bad size write to page register %#x (size %d, data %#x)\n",
484 port, cb, u32));
485 }
486 return VINF_SUCCESS;
487}
488
489/* EISA style high page registers, for extending the DMA addresses to cover
490 * the entire 32-bit address space.
491 */
492static DECLCALLBACK(int) dmaReadHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
493 uint32_t *pu32, unsigned cb)
494{
495 if (cb == 1)
496 {
497 DMAControl *dc = (DMAControl *)pvUser;
498 int reg;
499
500 reg = port & 7;
501 *pu32 = dc->au8PageHi[reg];
502 Log2(("Read %#x to from high page register %#x (channel %d)\n",
503 *pu32, port, DMAPG2CX(reg)));
504 return VINF_SUCCESS;
505 }
506 else
507 return VERR_IOM_IOPORT_UNUSED;
508}
509
510static DECLCALLBACK(int) dmaWriteHiPage(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port,
511 uint32_t u32, unsigned cb)
512{
513 if (cb == 1)
514 {
515 DMAControl *dc = (DMAControl *)pvUser;
516 int reg;
517
518 Assert(!(u32 & ~0xff)); /* Check for garbage in high bits. */
519 reg = port & 7;
520 dc->au8PageHi[reg] = u32;
521 Log2(("Wrote %#x to high page register %#x (channel %d)\n",
522 u32, port, DMAPG2CX(reg)));
523 }
524 else
525 {
526 /* Likely a guest bug. */
527 Log(("Bad size write to high page register %#x (size %d, data %#x)\n",
528 port, cb, u32));
529 }
530 return VINF_SUCCESS;
531}
532
533/* Perform any pending transfers on a single DMA channel. */
534static void dmaRunChannel(DMAState *s, int ctlidx, int chidx)
535{
536 DMAControl *dc = &s->DMAC[ctlidx];
537 DMAChannel *ch = &dc->ChState[chidx];
538 uint32_t start_cnt, end_cnt;
539 int opmode;
540
541 opmode = (ch->u8Mode >> 6) & 3;
542
543 Log3(("DMA address %screment, mode %d\n",
544 IS_MODE_DEC(ch->u8Mode) ? "de" : "in",
545 ch->u8Mode >> 6));
546
547 /* Addresses and counts are shifted for 16-bit channels. */
548 start_cnt = ch->u16CurCount << dc->is16bit;
549 end_cnt = ch->pfnXferHandler(s->pDevIns, ch->pvUser, (ctlidx * 4) + chidx,
550 start_cnt, (ch->u16BaseCount + 1) << dc->is16bit);
551 ch->u16CurCount = end_cnt >> dc->is16bit;
552 Log3(("DMA position %d, size %d\n", end_cnt, (ch->u16BaseCount + 1) << dc->is16bit));
553}
554
555static bool dmaRun(PPDMDEVINS pDevIns)
556{
557 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
558 DMAControl *dc;
559 int ctlidx, chidx, mask;
560
561 /* Run all controllers and channels. */
562 for (ctlidx = 0; ctlidx < 2; ++ctlidx)
563 {
564 dc = &s->DMAC[ctlidx];
565
566 /* If controller is disabled, don't even bother. */
567 if (dc->u8Command & CMD_DISABLE)
568 continue;
569
570 for (chidx = 0; chidx < 4; ++chidx)
571 {
572 mask = 1 << chidx;
573 if (!(dc->u8Mask & mask) && (dc->u8Status & (mask << 4)))
574 dmaRunChannel(s, ctlidx, chidx);
575 }
576 }
577 return 0;
578}
579
580static void dmaRegister(PPDMDEVINS pDevIns, unsigned channel,
581 PFNDMATRANSFERHANDLER handler, void *pvUser)
582{
583 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
584 DMAChannel *ch = &s->DMAC[DMACH2C(channel)].ChState[channel & 3];
585
586 LogFlow(("dmaRegister: s=%p channel=%u XferHandler=%p pvUser=%p\n",
587 s, channel, handler, pvUser));
588
589 ch->pfnXferHandler = handler;
590 ch->pvUser = pvUser;
591}
592
593/* Reverse the order of bytes in a memory buffer. */
594static void dmaReverseBuf8(void *buf, unsigned len)
595{
596 uint8_t *pBeg, *pEnd;
597 uint8_t temp;
598
599 pBeg = (uint8_t *)buf;
600 pEnd = pBeg + len - 1;
601 for (len = len / 2; len; --len)
602 {
603 temp = *pBeg;
604 *pBeg++ = *pEnd;
605 *pEnd-- = temp;
606 }
607}
608
609/* Reverse the order of words in a memory buffer. */
610static void dmaReverseBuf16(void *buf, unsigned len)
611{
612 uint16_t *pBeg, *pEnd;
613 uint16_t temp;
614
615 Assert(!(len & 1));
616 len /= 2; /* Convert to word count. */
617 pBeg = (uint16_t *)buf;
618 pEnd = pBeg + len - 1;
619 for (len = len / 2; len; --len)
620 {
621 temp = *pBeg;
622 *pBeg++ = *pEnd;
623 *pEnd-- = temp;
624 }
625}
626
627static uint32_t dmaReadMemory(PPDMDEVINS pDevIns, unsigned channel,
628 void *buf, uint32_t pos, uint32_t len)
629{
630 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
631 DMAControl *dc = &s->DMAC[DMACH2C(channel)];
632 DMAChannel *ch = &dc->ChState[channel & 3];
633 uint32_t page, pagehi;
634 uint32_t addr;
635
636 LogFlow(("dmaReadMemory: s=%p channel=%u buf=%p pos=%u len=%u\n",
637 s, channel, buf, pos, len));
638
639 /* Build the address for this transfer. */
640 page = dc->au8Page[DMACH2PG(channel)] & ~dc->is16bit;
641 pagehi = dc->au8PageHi[DMACH2PG(channel)];
642 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
643
644 if (IS_MODE_DEC(ch->u8Mode))
645 {
646 PDMDevHlpPhysRead(s->pDevIns, addr - pos - len, buf, len);
647 if (dc->is16bit)
648 dmaReverseBuf16(buf, len);
649 else
650 dmaReverseBuf8(buf, len);
651 }
652 else
653 PDMDevHlpPhysRead(s->pDevIns, addr + pos, buf, len);
654
655 return len;
656}
657
658static uint32_t dmaWriteMemory(PPDMDEVINS pDevIns, unsigned channel,
659 const void *buf, uint32_t pos, uint32_t len)
660{
661 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
662 DMAControl *dc = &s->DMAC[DMACH2C(channel)];
663 DMAChannel *ch = &dc->ChState[channel & 3];
664 uint32_t page, pagehi;
665 uint32_t addr;
666
667 LogFlow(("dmaWriteMemory: s=%p channel=%u buf=%p pos=%u len=%u\n",
668 s, channel, buf, pos, len));
669
670 /* Build the address for this transfer. */
671 page = dc->au8Page[DMACH2PG(channel)] & ~dc->is16bit;
672 pagehi = dc->au8PageHi[DMACH2PG(channel)];
673 addr = (pagehi << 24) | (page << 16) | (ch->u16CurAddr << dc->is16bit);
674
675 if (IS_MODE_DEC(ch->u8Mode))
676 {
677 //@todo: This would need a temporary buffer.
678 Assert(0);
679#if 0
680 if (dc->is16bit)
681 dmaReverseBuf16(buf, len);
682 else
683 dmaReverseBuf8(buf, len);
684#endif
685 PDMDevHlpPhysWrite(s->pDevIns, addr - pos - len, buf, len);
686 }
687 else
688 PDMDevHlpPhysWrite(s->pDevIns, addr + pos, buf, len);
689
690 return len;
691}
692
693static void dmaSetDREQ(PPDMDEVINS pDevIns, unsigned channel, unsigned level)
694{
695 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
696 DMAControl *dc = &s->DMAC[DMACH2C(channel)];
697 int chidx;
698
699 LogFlow(("dmaSetDREQ: s=%p channel=%u level=%u\n", s, channel, level));
700
701 chidx = channel & 3;
702 if (level)
703 dc->u8Status |= 1 << (chidx + 4);
704 else
705 dc->u8Status &= ~(1 << (chidx + 4));
706}
707
708static uint8_t dmaGetChannelMode(PPDMDEVINS pDevIns, unsigned channel)
709{
710 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
711
712 LogFlow(("dmaGetChannelMode: s=%p channel=%u\n", s, channel));
713
714 return s->DMAC[DMACH2C(channel)].ChState[channel & 3].u8Mode;
715}
716
717static void dmaReset(PPDMDEVINS pDevIns)
718{
719 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
720
721 LogFlow(("dmaReset: s=%p\n", s));
722
723 /* NB: The page and address registers are unaffected by a reset
724 * and in an undefined state after power-up.
725 */
726 dmaClear(&s->DMAC[0]);
727 dmaClear(&s->DMAC[1]);
728}
729
730/* Register DMA I/O port handlers. */
731static void dmaIORegister(PPDMDEVINS pDevIns, bool bHighPage)
732{
733 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
734 DMAControl *dc8;
735 DMAControl *dc16;
736
737 dc8 = &s->DMAC[0];
738 dc16 = &s->DMAC[1];
739
740 dc8->is16bit = false;
741 dc16->is16bit = true;
742
743 /* Base and current address for each channel. */
744 PDMDevHlpIOPortRegister(s->pDevIns, 0x00, 8, dc8,
745 dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA8 Address");
746 PDMDevHlpIOPortRegister(s->pDevIns, 0xC0, 16, dc16,
747 dmaWriteAddr, dmaReadAddr, NULL, NULL, "DMA16 Address");
748 /* Control registers for both DMA controllers. */
749 PDMDevHlpIOPortRegister(s->pDevIns, 0x08, 8, dc8,
750 dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA8 Control");
751 PDMDevHlpIOPortRegister(s->pDevIns, 0xD0, 16, dc16,
752 dmaWriteCtl, dmaReadCtl, NULL, NULL, "DMA16 Control");
753 /* Page registers for each channel (plus a few unused ones). */
754 PDMDevHlpIOPortRegister(s->pDevIns, 0x80, 8, dc8,
755 dmaWritePage, dmaReadPage, NULL, NULL, "DMA8 Page");
756 PDMDevHlpIOPortRegister(s->pDevIns, 0x88, 8, dc16,
757 dmaWritePage, dmaReadPage, NULL, NULL, "DMA16 Page");
758 /* Optional EISA style high page registers (address bits 24-31). */
759 if (bHighPage)
760 {
761 PDMDevHlpIOPortRegister(s->pDevIns, 0x480, 8, dc8,
762 dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA8 Page High");
763 PDMDevHlpIOPortRegister(s->pDevIns, 0x488, 8, dc16,
764 dmaWriteHiPage, dmaReadHiPage, NULL, NULL, "DMA16 Page High");
765 }
766}
767
768static void dmaSaveController(PSSMHANDLE pSSMHandle, DMAControl *dc)
769{
770 int chidx;
771
772 /* Save controller state... */
773 SSMR3PutU8(pSSMHandle, dc->u8Command);
774 SSMR3PutU8(pSSMHandle, dc->u8Mask);
775 SSMR3PutU8(pSSMHandle, dc->bHiByte);
776 SSMR3PutU32(pSSMHandle, dc->is16bit);
777 SSMR3PutU8(pSSMHandle, dc->u8Status);
778 SSMR3PutU8(pSSMHandle, dc->u8Temp);
779 SSMR3PutU8(pSSMHandle, dc->u8ModeCtr);
780 SSMR3PutMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
781 SSMR3PutMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
782
783 /* ...and all four of its channels. */
784 for (chidx = 0; chidx < 4; ++chidx)
785 {
786 DMAChannel *ch = &dc->ChState[chidx];
787
788 SSMR3PutU16(pSSMHandle, ch->u16CurAddr);
789 SSMR3PutU16(pSSMHandle, ch->u16CurCount);
790 SSMR3PutU16(pSSMHandle, ch->u16BaseAddr);
791 SSMR3PutU16(pSSMHandle, ch->u16BaseCount);
792 SSMR3PutU8(pSSMHandle, ch->u8Mode);
793 }
794}
795
796static int dmaLoadController(PSSMHANDLE pSSMHandle, DMAControl *dc, int version)
797{
798 uint8_t u8val;
799 uint32_t u32val;
800 int chidx;
801
802 SSMR3GetU8(pSSMHandle, &dc->u8Command);
803 SSMR3GetU8(pSSMHandle, &dc->u8Mask);
804 SSMR3GetU8(pSSMHandle, &u8val);
805 dc->bHiByte = !!u8val;
806 SSMR3GetU32(pSSMHandle, &dc->is16bit);
807 if (version > DMA_SAVESTATE_OLD)
808 {
809 SSMR3GetU8(pSSMHandle, &dc->u8Status);
810 SSMR3GetU8(pSSMHandle, &dc->u8Temp);
811 SSMR3GetU8(pSSMHandle, &dc->u8ModeCtr);
812 SSMR3GetMem(pSSMHandle, &dc->au8Page, sizeof(dc->au8Page));
813 SSMR3GetMem(pSSMHandle, &dc->au8PageHi, sizeof(dc->au8PageHi));
814 }
815
816 for (chidx = 0; chidx < 4; ++chidx)
817 {
818 DMAChannel *ch = &dc->ChState[chidx];
819
820 if (version == DMA_SAVESTATE_OLD)
821 {
822 /* Convert from 17-bit to 16-bit format. */
823 SSMR3GetU32(pSSMHandle, &u32val);
824 ch->u16CurAddr = u32val >> dc->is16bit;
825 SSMR3GetU32(pSSMHandle, &u32val);
826 ch->u16CurCount = u32val >> dc->is16bit;
827 }
828 else
829 {
830 SSMR3GetU16(pSSMHandle, &ch->u16CurAddr);
831 SSMR3GetU16(pSSMHandle, &ch->u16CurCount);
832 }
833 SSMR3GetU16(pSSMHandle, &ch->u16BaseAddr);
834 SSMR3GetU16(pSSMHandle, &ch->u16BaseCount);
835 SSMR3GetU8(pSSMHandle, &ch->u8Mode);
836 /* Convert from old save state. */
837 if (version == DMA_SAVESTATE_OLD)
838 {
839 /* Remap page register contents. */
840 SSMR3GetU8(pSSMHandle, &u8val);
841 dc->au8Page[DMACX2PG(chidx)] = u8val;
842 SSMR3GetU8(pSSMHandle, &u8val);
843 dc->au8PageHi[DMACX2PG(chidx)] = u8val;
844 /* Throw away dack, eop. */
845 SSMR3GetU8(pSSMHandle, &u8val);
846 SSMR3GetU8(pSSMHandle, &u8val);
847 }
848 }
849 return 0;
850}
851
852static DECLCALLBACK(int) dmaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
853{
854 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
855
856 dmaSaveController(pSSMHandle, &s->DMAC[0]);
857 dmaSaveController(pSSMHandle, &s->DMAC[1]);
858 return VINF_SUCCESS;
859}
860
861static DECLCALLBACK(int) dmaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle,
862 uint32_t uVersion, uint32_t uPass)
863{
864 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
865
866 AssertMsgReturn(uVersion <= DMA_SAVESTATE_CURRENT, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
867 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
868
869 dmaLoadController(pSSMHandle, &s->DMAC[0], uVersion);
870 return dmaLoadController(pSSMHandle, &s->DMAC[1], uVersion);
871}
872
873/**
874 * @interface_method_impl{PDMDEVREG,pfnConstruct}
875 */
876static DECLCALLBACK(int) dmaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
877{
878 DMAState *s = PDMINS_2_DATA(pDevIns, DMAState *);
879 bool bHighPage = false;
880 PDMDMACREG reg;
881 int rc;
882
883 s->pDevIns = pDevIns;
884
885 /*
886 * Validate configuration.
887 */
888 if (!CFGMR3AreValuesValid(pCfg, "\0")) /* "HighPageEnable\0")) */
889 return VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES;
890
891#if 0
892 rc = CFGMR3QueryBool(pCfg, "HighPageEnable", &bHighPage);
893 if (RT_FAILURE (rc))
894 return rc;
895#endif
896
897 dmaIORegister(pDevIns, bHighPage);
898 dmaReset(pDevIns);
899
900 reg.u32Version = PDM_DMACREG_VERSION;
901 reg.pfnRun = dmaRun;
902 reg.pfnRegister = dmaRegister;
903 reg.pfnReadMemory = dmaReadMemory;
904 reg.pfnWriteMemory = dmaWriteMemory;
905 reg.pfnSetDREQ = dmaSetDREQ;
906 reg.pfnGetChannelMode = dmaGetChannelMode;
907
908 rc = PDMDevHlpDMACRegister(pDevIns, &reg, &s->pHlp);
909 if (RT_FAILURE (rc))
910 return rc;
911
912 rc = PDMDevHlpSSMRegister(pDevIns, DMA_SAVESTATE_CURRENT, sizeof(*s),
913 dmaSaveExec, dmaLoadExec);
914 if (RT_FAILURE(rc))
915 return rc;
916
917 return VINF_SUCCESS;
918}
919
920/**
921 * The device registration structure.
922 */
923const PDMDEVREG g_DeviceDMA =
924{
925 /* u32Version */
926 PDM_DEVREG_VERSION,
927 /* szName */
928 "8237A",
929 /* szRCMod */
930 "",
931 /* szR0Mod */
932 "",
933 /* pszDescription */
934 "DMA Controller Device",
935 /* fFlags */
936 PDM_DEVREG_FLAGS_DEFAULT_BITS,
937 /* fClass */
938 PDM_DEVREG_CLASS_DMA,
939 /* cMaxInstances */
940 1,
941 /* cbInstance */
942 sizeof(DMAState),
943 /* pfnConstruct */
944 dmaConstruct,
945 /* pfnDestruct */
946 NULL,
947 /* pfnRelocate */
948 NULL,
949 /* pfnIOCtl */
950 NULL,
951 /* pfnPowerOn */
952 NULL,
953 /* pfnReset */
954 dmaReset,
955 /* pfnSuspend */
956 NULL,
957 /* pfnResume */
958 NULL,
959 /* pfnAttach */
960 NULL,
961 /* pfnDetach */
962 NULL,
963 /* pfnQueryInterface. */
964 NULL,
965 /* pfnInitComplete */
966 NULL,
967 /* pfnPowerOff */
968 NULL,
969 /* pfnSoftReset */
970 NULL,
971 /* u32VersionEnd */
972 PDM_DEVREG_VERSION
973};
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