VirtualBox

source: vbox/trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.h@ 82781

Last change on this file since 82781 was 82114, checked in by vboxsync, 4 years ago

DevVGA: Splitting up the VMSVGASTATE structure. bugref:9218
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1/* $Id: DevVGA-SVGA.h 82114 2019-11-22 23:05:31Z vboxsync $ */
2/** @file
3 * VMware SVGA device
4 */
5/*
6 * Copyright (C) 2013-2019 Oracle Corporation
7 *
8 * This file is part of VirtualBox Open Source Edition (OSE), as
9 * available from http://www.virtualbox.org. This file is free software;
10 * you can redistribute it and/or modify it under the terms of the GNU
11 * General Public License (GPL) as published by the Free Software
12 * Foundation, in version 2 as it comes in the "COPYING" file of the
13 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15 */
16
17#ifndef VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h
18#define VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h
19#ifndef RT_WITHOUT_PRAGMA_ONCE
20# pragma once
21#endif
22
23#ifndef VBOX_WITH_VMSVGA
24# error "VBOX_WITH_VMSVGA is not defined"
25#endif
26
27#include <VBox/vmm/pdmthread.h>
28
29#include "vmsvga/svga3d_reg.h"
30
31/** Default FIFO size. */
32#define VMSVGA_FIFO_SIZE _2M
33/** The old FIFO size. */
34#define VMSVGA_FIFO_SIZE_OLD _128K
35
36/** Default scratch region size. */
37#define VMSVGA_SCRATCH_SIZE 0x100
38/** Surface memory available to the guest. */
39#define VMSVGA_SURFACE_SIZE (512*1024*1024)
40/** Maximum GMR pages. */
41#define VMSVGA_MAX_GMR_PAGES 0x100000
42/** Maximum nr of GMR ids. */
43#define VMSVGA_MAX_GMR_IDS _8K
44/** Maximum number of GMR descriptors. */
45#define VMSVGA_MAX_GMR_DESC_LOOP_COUNT VMSVGA_MAX_GMR_PAGES
46
47#define VMSVGA_VAL_UNINITIALIZED (unsigned)-1
48
49/** For validating X and width values.
50 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
51#define VMSVGA_MAX_X _1M
52/** For validating Y and height values.
53 * The code assumes it's at least an order of magnitude less than UINT32_MAX. */
54#define VMSVGA_MAX_Y _1M
55
56/* u32ActionFlags */
57#define VMSVGA_ACTION_CHANGEMODE_BIT 0
58#define VMSVGA_ACTION_CHANGEMODE RT_BIT(VMSVGA_ACTION_CHANGEMODE_BIT)
59
60
61#ifdef DEBUG
62/* Enable to log FIFO register accesses. */
63//# define DEBUG_FIFO_ACCESS
64/* Enable to log GMR page accesses. */
65//# define DEBUG_GMR_ACCESS
66#endif
67
68#define VMSVGA_FIFO_EXTCMD_NONE 0
69#define VMSVGA_FIFO_EXTCMD_TERMINATE 1
70#define VMSVGA_FIFO_EXTCMD_SAVESTATE 2
71#define VMSVGA_FIFO_EXTCMD_LOADSTATE 3
72#define VMSVGA_FIFO_EXTCMD_RESET 4
73#define VMSVGA_FIFO_EXTCMD_UPDATE_SURFACE_HEAP_BUFFERS 5
74
75/** Size of the region to backup when switching into svga mode. */
76#define VMSVGA_VGA_FB_BACKUP_SIZE _512K
77
78/** @def VMSVGA_WITH_VGA_FB_BACKUP
79 * Enables correct VGA MMIO read/write handling when VMSVGA is enabled. It
80 * is SLOW and probably not entirely right, but it helps with getting 3dmark
81 * output and other stuff. */
82#define VMSVGA_WITH_VGA_FB_BACKUP 1
83
84/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
85 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3) */
86#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
87# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3 1
88#else
89# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RING3
90#endif
91
92/** @def VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
93 * defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3) */
94#if (defined(VMSVGA_WITH_VGA_FB_BACKUP) && !defined(IN_RING3)) || defined(DOXYGEN_RUNNING)
95# define VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ 1
96#else
97# undef VMSVGA_WITH_VGA_FB_BACKUP_AND_IN_RZ
98#endif
99
100
101typedef struct
102{
103 PSSMHANDLE pSSM;
104 uint32_t uVersion;
105 uint32_t uPass;
106} VMSVGA_STATE_LOAD;
107typedef VMSVGA_STATE_LOAD *PVMSVGA_STATE_LOAD;
108
109/** Host screen viewport.
110 * (4th quadrant with negated Y values - usual Windows and X11 world view.) */
111typedef struct VMSVGAVIEWPORT
112{
113 uint32_t x; /**< x coordinate (left). */
114 uint32_t y; /**< y coordinate (top). */
115 uint32_t cx; /**< width. */
116 uint32_t cy; /**< height. */
117 /** Right side coordinate (exclusive). Same as x + cx. */
118 uint32_t xRight;
119 /** First quadrant low y coordinate.
120 * Same as y + cy - 1 in window coordinates. */
121 uint32_t yLowWC;
122 /** First quadrant high y coordinate (exclusive) - yLowWC + cy.
123 * Same as y - 1 in window coordinates. */
124 uint32_t yHighWC;
125 /** Alignment padding. */
126 uint32_t uAlignment;
127} VMSVGAVIEWPORT;
128
129/**
130 * Screen object state.
131 */
132typedef struct VMSVGASCREENOBJECT
133{
134 /** SVGA_SCREEN_* flags. */
135 uint32_t fuScreen;
136 /** The screen object id. */
137 uint32_t idScreen;
138 /** The screen dimensions. */
139 int32_t xOrigin;
140 int32_t yOrigin;
141 uint32_t cWidth;
142 uint32_t cHeight;
143 /** Offset of the screen buffer in the guest VRAM. */
144 uint32_t offVRAM;
145 /** Scanline pitch. */
146 uint32_t cbPitch;
147 /** Bits per pixel. */
148 uint32_t cBpp;
149 bool fDefined;
150 bool fModified;
151} VMSVGASCREENOBJECT;
152
153/** Pointer to the private VMSVGA ring-3 state structure.
154 * @todo Still not entirely satisfired with the type name, but better than
155 * the previous lower/upper case only distinction. */
156typedef struct VMSVGAR3STATE *PVMSVGAR3STATE;
157/** Pointer to the private (implementation specific) VMSVGA3d state. */
158typedef struct VMSVGA3DSTATE *PVMSVGA3DSTATE;
159
160
161/**
162 * The VMSVGA device state.
163 *
164 * This instantatiated as VGASTATE::svga.
165 */
166typedef struct VMSVGAState
167{
168 /** Guest physical address of the FIFO memory range. */
169 RTGCPHYS GCPhysFIFO;
170 /** Size in bytes of the FIFO memory range.
171 * This may be smaller than cbFIFOConfig after restoring an old VM state. */
172 uint32_t cbFIFO;
173 /** The configured FIFO size. */
174 uint32_t cbFIFOConfig;
175 /** SVGA id. */
176 uint32_t u32SVGAId;
177 /** SVGA extensions enabled or not. */
178 uint32_t fEnabled;
179 /** SVGA memory area configured status. */
180 uint32_t fConfigured;
181 /** Device is busy handling FIFO requests (VMSVGA_BUSY_F_FIFO,
182 * VMSVGA_BUSY_F_EMT_FORCE). */
183 uint32_t volatile fBusy;
184#define VMSVGA_BUSY_F_FIFO RT_BIT_32(0) /**< The normal true/false busy FIFO bit. */
185#define VMSVGA_BUSY_F_EMT_FORCE RT_BIT_32(1) /**< Bit preventing race status flickering when EMT kicks the FIFO thread. */
186 /** Traces (dirty page detection) enabled or not. */
187 uint32_t fTraces;
188 /** Guest OS identifier. */
189 uint32_t u32GuestId;
190 /** Scratch region size (VMSVGAState::au32ScratchRegion). */
191 uint32_t cScratchRegion;
192 /** Irq status. */
193 uint32_t u32IrqStatus;
194 /** Irq mask. */
195 uint32_t u32IrqMask;
196 /** Pitch lock. */
197 uint32_t u32PitchLock;
198 /** Current GMR id. (SVGA_REG_GMR_ID) */
199 uint32_t u32CurrentGMRId;
200 /** Register caps. */
201 uint32_t u32RegCaps;
202 uint32_t Padding0; /* Used to be I/O port base address. */
203 /** Port io index register. */
204 uint32_t u32IndexReg;
205 /** FIFO request semaphore. */
206 SUPSEMEVENT hFIFORequestSem;
207 /** The last seen SVGA_FIFO_CURSOR_COUNT value.
208 * Used by the FIFO thread and its watchdog. */
209 uint32_t uLastCursorUpdateCount;
210 /** Indicates that the FIFO thread is sleeping and might need waking up. */
211 bool volatile fFIFOThreadSleeping;
212 /** The legacy GFB mode registers. If used, they correspond to screen 0. */
213 /** True when the guest modifies the GFB mode registers. */
214 bool fGFBRegisters;
215 bool afPadding[2];
216 uint32_t uWidth;
217 uint32_t uHeight;
218 uint32_t uBpp;
219 uint32_t cbScanline;
220 /** Maximum width supported. */
221 uint32_t u32MaxWidth;
222 /** Maximum height supported. */
223 uint32_t u32MaxHeight;
224 /** Viewport rectangle, i.e. what's currently visible of the target host
225 * window. This is usually (0,0)(uWidth,uHeight), but if the window is
226 * shrunk and scrolling applied, both the origin and size may differ. */
227 VMSVGAVIEWPORT viewport;
228 /** Action flags */
229 uint32_t u32ActionFlags;
230 /** SVGA 3d extensions enabled or not. */
231 bool f3DEnabled;
232 /** VRAM page monitoring enabled or not. */
233 bool fVRAMTracking;
234 /** External command to be executed in the FIFO thread. */
235 uint8_t volatile u8FIFOExtCommand;
236 /** Set by vmsvgaR3RunExtCmdOnFifoThread when it temporarily resumes the FIFO
237 * thread and does not want it do anything but the command. */
238 bool volatile fFifoExtCommandWakeup;
239#ifdef DEBUG_GMR_ACCESS
240 /** GMR debug access handler type handle. */
241 PGMPHYSHANDLERTYPE hGmrAccessHandlerType;
242#endif
243#if defined(VMSVGA_USE_FIFO_ACCESS_HANDLER) || defined(DEBUG_FIFO_ACCESS)
244 /** FIFO debug access handler type handle. */
245 PGMPHYSHANDLERTYPE hFifoAccessHandlerType;
246#elif defined(DEBUG_GMR_ACCESS)
247 uint32_t uPadding1;
248#endif
249 /** Number of GMRs. */
250 uint32_t cGMR;
251 uint32_t uScreenOffset; /* Used only for loading older saved states. */
252
253 /** Scratch array.
254 * Putting this at the end since it's big it probably not . */
255 uint32_t au32ScratchRegion[VMSVGA_SCRATCH_SIZE];
256
257 STAMCOUNTER StatRegBitsPerPixelWr;
258 STAMCOUNTER StatRegBusyWr;
259 STAMCOUNTER StatRegCursorXxxxWr;
260 STAMCOUNTER StatRegDepthWr;
261 STAMCOUNTER StatRegDisplayHeightWr;
262 STAMCOUNTER StatRegDisplayIdWr;
263 STAMCOUNTER StatRegDisplayIsPrimaryWr;
264 STAMCOUNTER StatRegDisplayPositionXWr;
265 STAMCOUNTER StatRegDisplayPositionYWr;
266 STAMCOUNTER StatRegDisplayWidthWr;
267 STAMCOUNTER StatRegEnableWr;
268 STAMCOUNTER StatRegGmrIdWr;
269 STAMCOUNTER StatRegGuestIdWr;
270 STAMCOUNTER StatRegHeightWr;
271 STAMCOUNTER StatRegIdWr;
272 STAMCOUNTER StatRegIrqMaskWr;
273 STAMCOUNTER StatRegNumDisplaysWr;
274 STAMCOUNTER StatRegNumGuestDisplaysWr;
275 STAMCOUNTER StatRegPaletteWr;
276 STAMCOUNTER StatRegPitchLockWr;
277 STAMCOUNTER StatRegPseudoColorWr;
278 STAMCOUNTER StatRegReadOnlyWr;
279 STAMCOUNTER StatRegScratchWr;
280 STAMCOUNTER StatRegSyncWr;
281 STAMCOUNTER StatRegTopWr;
282 STAMCOUNTER StatRegTracesWr;
283 STAMCOUNTER StatRegUnknownWr;
284 STAMCOUNTER StatRegWidthWr;
285
286 STAMCOUNTER StatRegBitsPerPixelRd;
287 STAMCOUNTER StatRegBlueMaskRd;
288 STAMCOUNTER StatRegBusyRd;
289 STAMCOUNTER StatRegBytesPerLineRd;
290 STAMCOUNTER StatRegCapabilitesRd;
291 STAMCOUNTER StatRegConfigDoneRd;
292 STAMCOUNTER StatRegCursorXxxxRd;
293 STAMCOUNTER StatRegDepthRd;
294 STAMCOUNTER StatRegDisplayHeightRd;
295 STAMCOUNTER StatRegDisplayIdRd;
296 STAMCOUNTER StatRegDisplayIsPrimaryRd;
297 STAMCOUNTER StatRegDisplayPositionXRd;
298 STAMCOUNTER StatRegDisplayPositionYRd;
299 STAMCOUNTER StatRegDisplayWidthRd;
300 STAMCOUNTER StatRegEnableRd;
301 STAMCOUNTER StatRegFbOffsetRd;
302 STAMCOUNTER StatRegFbSizeRd;
303 STAMCOUNTER StatRegFbStartRd;
304 STAMCOUNTER StatRegGmrIdRd;
305 STAMCOUNTER StatRegGmrMaxDescriptorLengthRd;
306 STAMCOUNTER StatRegGmrMaxIdsRd;
307 STAMCOUNTER StatRegGmrsMaxPagesRd;
308 STAMCOUNTER StatRegGreenMaskRd;
309 STAMCOUNTER StatRegGuestIdRd;
310 STAMCOUNTER StatRegHeightRd;
311 STAMCOUNTER StatRegHostBitsPerPixelRd;
312 STAMCOUNTER StatRegIdRd;
313 STAMCOUNTER StatRegIrqMaskRd;
314 STAMCOUNTER StatRegMaxHeightRd;
315 STAMCOUNTER StatRegMaxWidthRd;
316 STAMCOUNTER StatRegMemorySizeRd;
317 STAMCOUNTER StatRegMemRegsRd;
318 STAMCOUNTER StatRegMemSizeRd;
319 STAMCOUNTER StatRegMemStartRd;
320 STAMCOUNTER StatRegNumDisplaysRd;
321 STAMCOUNTER StatRegNumGuestDisplaysRd;
322 STAMCOUNTER StatRegPaletteRd;
323 STAMCOUNTER StatRegPitchLockRd;
324 STAMCOUNTER StatRegPsuedoColorRd;
325 STAMCOUNTER StatRegRedMaskRd;
326 STAMCOUNTER StatRegScratchRd;
327 STAMCOUNTER StatRegScratchSizeRd;
328 STAMCOUNTER StatRegSyncRd;
329 STAMCOUNTER StatRegTopRd;
330 STAMCOUNTER StatRegTracesRd;
331 STAMCOUNTER StatRegUnknownRd;
332 STAMCOUNTER StatRegVramSizeRd;
333 STAMCOUNTER StatRegWidthRd;
334 STAMCOUNTER StatRegWriteOnlyRd;
335} VMSVGAState, VMSVGASTATE;
336
337
338/**
339 * The VMSVGA device state for ring-3
340 *
341 * This instantatiated as VGASTATER3::svga.
342 */
343typedef struct VMSVGASTATER3
344{
345 /** The R3 FIFO pointer. */
346 R3PTRTYPE(uint32_t *) pau32FIFO;
347 /** R3 Opaque pointer to svga state. */
348 R3PTRTYPE(PVMSVGAR3STATE) pSvgaR3State;
349 /** R3 Opaque pointer to 3d state. */
350 R3PTRTYPE(PVMSVGA3DSTATE) p3dState;
351 /** The separate VGA frame buffer in svga mode.
352 * Unlike the the boch-based VGA device implementation, VMSVGA seems to have a
353 * separate frame buffer for VGA and allows concurrent use of both. The SVGA
354 * SDK is making use of this to do VGA text output while testing other things in
355 * SVGA mode, displaying the result by switching back to VGA text mode. So,
356 * when entering SVGA mode we copy the first part of the frame buffer here and
357 * direct VGA accesses here instead. It is copied back when leaving SVGA mode. */
358 R3PTRTYPE(uint8_t *) pbVgaFrameBufferR3;
359 /** R3 Opaque pointer to an external fifo cmd parameter. */
360 R3PTRTYPE(void * volatile) pvFIFOExtCmdParam;
361
362 /** FIFO external command semaphore. */
363 R3PTRTYPE(RTSEMEVENT) hFIFOExtCmdSem;
364 /** FIFO IO Thread. */
365 R3PTRTYPE(PPDMTHREAD) pFIFOIOThread;
366} VMSVGASTATER3;
367
368
369/**
370 * The VMSVGA device state for ring-0
371 *
372 * This instantatiated as VGASTATER0::svga.
373 */
374typedef struct VMSVGASTATER0
375{
376 /** The R0 FIFO pointer.
377 * @note This only points to the _first_ _page_ of the FIFO! */
378 R0PTRTYPE(uint32_t *) pau32FIFO;
379} VMSVGASTATER0;
380
381
382typedef struct VGAState *PVGASTATE;
383typedef struct VGASTATER3 *PVGASTATER3;
384typedef struct VGASTATER0 *PVGASTATER0;
385typedef struct VGASTATERC *PVGASTATERC;
386typedef CTX_SUFF(PVGASTATE) PVGASTATECC;
387
388DECLCALLBACK(int) vmsvgaR3PciIORegionFifoMapUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
389 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType);
390DECLCALLBACK(VBOXSTRICTRC) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t *pu32, unsigned cb);
391DECLCALLBACK(VBOXSTRICTRC) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT offPort, uint32_t u32, unsigned cb);
392
393DECLCALLBACK(void) vmsvgaR3PortSetViewport(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId,
394 uint32_t x, uint32_t y, uint32_t cx, uint32_t cy);
395
396int vmsvgaR3Init(PPDMDEVINS pDevIns);
397int vmsvgaR3Reset(PPDMDEVINS pDevIns);
398int vmsvgaR3Destruct(PPDMDEVINS pDevIns);
399int vmsvgaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
400int vmsvgaR3LoadDone(PPDMDEVINS pDevIns);
401int vmsvgaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
402DECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns);
403DECLCALLBACK(void) vmsvgaR3PowerOff(PPDMDEVINS pDevIns);
404void vmsvgaR3FifoWatchdogTimer(PPDMDEVINS pDevIns, PVGASTATE pThis, PVGASTATECC pThisCC);
405
406#ifdef IN_RING3
407VMSVGASCREENOBJECT *vmsvgaR3GetScreenObject(PVGASTATECC pThisCC, uint32_t idScreen);
408int vmsvgaR3UpdateScreen(PVGASTATECC pThisCC, VMSVGASCREENOBJECT *pScreen, int x, int y, int w, int h);
409#endif
410
411int vmsvgaR3GmrTransfer(PVGASTATE pThis, PVGASTATECC pThisCC, const SVGA3dTransferType enmTransferType,
412 uint8_t *pbHstBuf, uint32_t cbHstBuf, uint32_t offHst, int32_t cbHstPitch,
413 SVGAGuestPtr gstPtr, uint32_t offGst, int32_t cbGstPitch,
414 uint32_t cbWidth, uint32_t cHeight);
415
416void vmsvgaR3ClipCopyBox(const SVGA3dSize *pSizeSrc, const SVGA3dSize *pSizeDest, SVGA3dCopyBox *pBox);
417void vmsvgaR3ClipBox(const SVGA3dSize *pSize, SVGA3dBox *pBox);
418void vmsvgaR3ClipRect(SVGASignedRect const *pBound, SVGASignedRect *pRect);
419
420#endif /* !VBOX_INCLUDED_SRC_Graphics_DevVGA_SVGA_h */
421
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