VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 99901

Last change on this file since 99901 was 99556, checked in by vboxsync, 13 months ago

include/iprt/x86.h: Add definitions for Intels CET
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
9 *
10 * This file is part of VirtualBox base platform packages, as
11 * available from https://www.virtualbox.org.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation, in version 3 of the
16 * License.
17 *
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see <https://www.gnu.org/licenses>.
25 *
26 * The contents of this file may alternatively be used under the terms
27 * of the Common Development and Distribution License Version 1.0
28 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29 * in the VirtualBox distribution, in which case the provisions of the
30 * CDDL are applicable instead of those of the GPL.
31 *
32 * You may elect to license modified versions of this file under the
33 * terms and conditions of either the GPL or the CDDL or both.
34 *
35 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36 */
37
38#ifndef IPRT_INCLUDED_x86_h
39#define IPRT_INCLUDED_x86_h
40#ifndef RT_WITHOUT_PRAGMA_ONCE
41# pragma once
42#endif
43
44#ifndef VBOX_FOR_DTRACE_LIB
45# include <iprt/types.h>
46# include <iprt/assert.h>
47#else
48# pragma D depends_on library vbox-types.d
49#endif
50
51/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52 * defining MSR_IA32_FLUSH_CMD */
53#ifdef RT_OS_SOLARIS
54# undef CS
55# undef DS
56# undef MSR_IA32_FLUSH_CMD
57#endif
58
59/** @defgroup grp_rt_x86 x86 Types and Definitions
60 * @ingroup grp_rt
61 * @{
62 */
63
64#ifndef VBOX_FOR_DTRACE_LIB
65/**
66 * EFLAGS Bits.
67 */
68typedef struct X86EFLAGSBITS
69{
70 /** Bit 0 - CF - Carry flag - Status flag. */
71 unsigned u1CF : 1;
72 /** Bit 1 - 1 - Reserved flag. */
73 unsigned u1Reserved0 : 1;
74 /** Bit 2 - PF - Parity flag - Status flag. */
75 unsigned u1PF : 1;
76 /** Bit 3 - 0 - Reserved flag. */
77 unsigned u1Reserved1 : 1;
78 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
79 unsigned u1AF : 1;
80 /** Bit 5 - 0 - Reserved flag. */
81 unsigned u1Reserved2 : 1;
82 /** Bit 6 - ZF - Zero flag - Status flag. */
83 unsigned u1ZF : 1;
84 /** Bit 7 - SF - Signed flag - Status flag. */
85 unsigned u1SF : 1;
86 /** Bit 8 - TF - Trap flag - System flag. */
87 unsigned u1TF : 1;
88 /** Bit 9 - IF - Interrupt flag - System flag. */
89 unsigned u1IF : 1;
90 /** Bit 10 - DF - Direction flag - Control flag. */
91 unsigned u1DF : 1;
92 /** Bit 11 - OF - Overflow flag - Status flag. */
93 unsigned u1OF : 1;
94 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
95 unsigned u2IOPL : 2;
96 /** Bit 14 - NT - Nested task flag - System flag. */
97 unsigned u1NT : 1;
98 /** Bit 15 - 0 - Reserved flag. */
99 unsigned u1Reserved3 : 1;
100 /** Bit 16 - RF - Resume flag - System flag. */
101 unsigned u1RF : 1;
102 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
103 unsigned u1VM : 1;
104 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
105 unsigned u1AC : 1;
106 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
107 unsigned u1VIF : 1;
108 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
109 unsigned u1VIP : 1;
110 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
111 unsigned u1ID : 1;
112 /** Bit 22-31 - 0 - Reserved flag. */
113 unsigned u10Reserved4 : 10;
114} X86EFLAGSBITS;
115/** Pointer to EFLAGS bits. */
116typedef X86EFLAGSBITS *PX86EFLAGSBITS;
117/** Pointer to const EFLAGS bits. */
118typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
119#endif /* !VBOX_FOR_DTRACE_LIB */
120
121/**
122 * EFLAGS.
123 */
124typedef union X86EFLAGS
125{
126 /** The plain unsigned view. */
127 uint32_t u;
128#ifndef VBOX_FOR_DTRACE_LIB
129 /** The bitfield view. */
130 X86EFLAGSBITS Bits;
131#endif
132 /** The 8-bit view. */
133 uint8_t au8[4];
134 /** The 16-bit view. */
135 uint16_t au16[2];
136 /** The 32-bit view. */
137 uint32_t au32[1];
138 /** The 32-bit view. */
139 uint32_t u32;
140} X86EFLAGS;
141/** Pointer to EFLAGS. */
142typedef X86EFLAGS *PX86EFLAGS;
143/** Pointer to const EFLAGS. */
144typedef const X86EFLAGS *PCX86EFLAGS;
145
146/**
147 * RFLAGS (32 upper bits are reserved).
148 */
149typedef union X86RFLAGS
150{
151 /** The plain unsigned view. */
152 uint64_t u;
153#ifndef VBOX_FOR_DTRACE_LIB
154 /** The bitfield view. */
155 X86EFLAGSBITS Bits;
156#endif
157 /** The 8-bit view. */
158 uint8_t au8[8];
159 /** The 16-bit view. */
160 uint16_t au16[4];
161 /** The 32-bit view. */
162 uint32_t au32[2];
163 /** The 64-bit view. */
164 uint64_t au64[1];
165 /** The 64-bit view. */
166 uint64_t u64;
167} X86RFLAGS;
168/** Pointer to RFLAGS. */
169typedef X86RFLAGS *PX86RFLAGS;
170/** Pointer to const RFLAGS. */
171typedef const X86RFLAGS *PCX86RFLAGS;
172
173
174/** @name EFLAGS
175 * @{
176 */
177/** Bit 0 - CF - Carry flag - Status flag. */
178#define X86_EFL_CF RT_BIT_32(0)
179#define X86_EFL_CF_BIT 0
180/** Bit 1 - Reserved, reads as 1. */
181#define X86_EFL_1 RT_BIT_32(1)
182/** Bit 2 - PF - Parity flag - Status flag. */
183#define X86_EFL_PF RT_BIT_32(2)
184#define X86_EFL_PF_BIT 2
185/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
186#define X86_EFL_AF RT_BIT_32(4)
187#define X86_EFL_AF_BIT 4
188/** Bit 6 - ZF - Zero flag - Status flag. */
189#define X86_EFL_ZF RT_BIT_32(6)
190#define X86_EFL_ZF_BIT 6
191/** Bit 7 - SF - Signed flag - Status flag. */
192#define X86_EFL_SF RT_BIT_32(7)
193#define X86_EFL_SF_BIT 7
194/** Bit 8 - TF - Trap flag - System flag. */
195#define X86_EFL_TF RT_BIT_32(8)
196#define X86_EFL_TF_BIT 8
197/** Bit 9 - IF - Interrupt flag - System flag. */
198#define X86_EFL_IF RT_BIT_32(9)
199#define X86_EFL_IF_BIT 9
200/** Bit 10 - DF - Direction flag - Control flag. */
201#define X86_EFL_DF RT_BIT_32(10)
202#define X86_EFL_DF_BIT 10
203/** Bit 11 - OF - Overflow flag - Status flag. */
204#define X86_EFL_OF RT_BIT_32(11)
205#define X86_EFL_OF_BIT 11
206/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
207#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
208/** Bit 14 - NT - Nested task flag - System flag. */
209#define X86_EFL_NT RT_BIT_32(14)
210#define X86_EFL_NT_BIT 14
211/** Bit 16 - RF - Resume flag - System flag. */
212#define X86_EFL_RF RT_BIT_32(16)
213#define X86_EFL_RF_BIT 16
214/** Bit 17 - VM - Virtual 8086 mode - System flag. */
215#define X86_EFL_VM RT_BIT_32(17)
216#define X86_EFL_VM_BIT 17
217/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
218#define X86_EFL_AC RT_BIT_32(18)
219#define X86_EFL_AC_BIT 18
220/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
221#define X86_EFL_VIF RT_BIT_32(19)
222#define X86_EFL_VIF_BIT 19
223/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
224#define X86_EFL_VIP RT_BIT_32(20)
225#define X86_EFL_VIP_BIT 20
226/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
227#define X86_EFL_ID RT_BIT_32(21)
228#define X86_EFL_ID_BIT 21
229/** All live bits. */
230#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
231/** Read as 1 bits. */
232#define X86_EFL_RA1_MASK RT_BIT_32(1)
233/** Read as 0 bits, excluding bits 31:22.
234 * Bits 3, 5, 15, and 22 thru 31. */
235#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
236/** Read as 0 bits, excluding bits 31:22.
237 * Bits 3, 5 and 15. */
238#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
239/** IOPL shift. */
240#define X86_EFL_IOPL_SHIFT 12
241/** The IOPL level from the flags. */
242#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
243/** Bits restored by popf */
244#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
245 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
246/** Bits restored by popf */
247#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
248 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
249/** The status bits commonly updated by arithmetic instructions. */
250#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
251/** @} */
252
253
254/** CPUID Feature information - ECX.
255 * CPUID query with EAX=1.
256 */
257#ifndef VBOX_FOR_DTRACE_LIB
258typedef struct X86CPUIDFEATECX
259{
260 /** Bit 0 - SSE3 - Supports SSE3 or not. */
261 unsigned u1SSE3 : 1;
262 /** Bit 1 - PCLMULQDQ. */
263 unsigned u1PCLMULQDQ : 1;
264 /** Bit 2 - DS Area 64-bit layout. */
265 unsigned u1DTE64 : 1;
266 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
267 unsigned u1Monitor : 1;
268 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
269 unsigned u1CPLDS : 1;
270 /** Bit 5 - VMX - Virtual Machine Technology. */
271 unsigned u1VMX : 1;
272 /** Bit 6 - SMX: Safer Mode Extensions. */
273 unsigned u1SMX : 1;
274 /** Bit 7 - EST - Enh. SpeedStep Tech. */
275 unsigned u1EST : 1;
276 /** Bit 8 - TM2 - Terminal Monitor 2. */
277 unsigned u1TM2 : 1;
278 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
279 unsigned u1SSSE3 : 1;
280 /** Bit 10 - CNTX-ID - L1 Context ID. */
281 unsigned u1CNTXID : 1;
282 /** Bit 11 - Reserved. */
283 unsigned u1Reserved1 : 1;
284 /** Bit 12 - FMA. */
285 unsigned u1FMA : 1;
286 /** Bit 13 - CX16 - CMPXCHG16B. */
287 unsigned u1CX16 : 1;
288 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
289 unsigned u1TPRUpdate : 1;
290 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
291 unsigned u1PDCM : 1;
292 /** Bit 16 - Reserved. */
293 unsigned u1Reserved2 : 1;
294 /** Bit 17 - PCID - Process-context identifiers. */
295 unsigned u1PCID : 1;
296 /** Bit 18 - Direct Cache Access. */
297 unsigned u1DCA : 1;
298 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
299 unsigned u1SSE4_1 : 1;
300 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
301 unsigned u1SSE4_2 : 1;
302 /** Bit 21 - x2APIC. */
303 unsigned u1x2APIC : 1;
304 /** Bit 22 - MOVBE - Supports MOVBE. */
305 unsigned u1MOVBE : 1;
306 /** Bit 23 - POPCNT - Supports POPCNT. */
307 unsigned u1POPCNT : 1;
308 /** Bit 24 - TSC-Deadline. */
309 unsigned u1TSCDEADLINE : 1;
310 /** Bit 25 - AES. */
311 unsigned u1AES : 1;
312 /** Bit 26 - XSAVE - Supports XSAVE. */
313 unsigned u1XSAVE : 1;
314 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
315 unsigned u1OSXSAVE : 1;
316 /** Bit 28 - AVX - Supports AVX instruction extensions. */
317 unsigned u1AVX : 1;
318 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
319 unsigned u1F16C : 1;
320 /** Bit 30 - RDRAND - Supports RDRAND. */
321 unsigned u1RDRAND : 1;
322 /** Bit 31 - Hypervisor present (we're a guest). */
323 unsigned u1HVP : 1;
324} X86CPUIDFEATECX;
325#else /* VBOX_FOR_DTRACE_LIB */
326typedef uint32_t X86CPUIDFEATECX;
327#endif /* VBOX_FOR_DTRACE_LIB */
328/** Pointer to CPUID Feature Information - ECX. */
329typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
330/** Pointer to const CPUID Feature Information - ECX. */
331typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
332
333
334/** CPUID Feature Information - EDX.
335 * CPUID query with EAX=1.
336 */
337#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
338typedef struct X86CPUIDFEATEDX
339{
340 /** Bit 0 - FPU - x87 FPU on Chip. */
341 unsigned u1FPU : 1;
342 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
343 unsigned u1VME : 1;
344 /** Bit 2 - DE - Debugging extensions. */
345 unsigned u1DE : 1;
346 /** Bit 3 - PSE - Page Size Extension. */
347 unsigned u1PSE : 1;
348 /** Bit 4 - TSC - Time Stamp Counter. */
349 unsigned u1TSC : 1;
350 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
351 unsigned u1MSR : 1;
352 /** Bit 6 - PAE - Physical Address Extension. */
353 unsigned u1PAE : 1;
354 /** Bit 7 - MCE - Machine Check Exception. */
355 unsigned u1MCE : 1;
356 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
357 unsigned u1CX8 : 1;
358 /** Bit 9 - APIC - APIC On-Chip. */
359 unsigned u1APIC : 1;
360 /** Bit 10 - Reserved. */
361 unsigned u1Reserved1 : 1;
362 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
363 unsigned u1SEP : 1;
364 /** Bit 12 - MTRR - Memory Type Range Registers. */
365 unsigned u1MTRR : 1;
366 /** Bit 13 - PGE - PTE Global Bit. */
367 unsigned u1PGE : 1;
368 /** Bit 14 - MCA - Machine Check Architecture. */
369 unsigned u1MCA : 1;
370 /** Bit 15 - CMOV - Conditional Move Instructions. */
371 unsigned u1CMOV : 1;
372 /** Bit 16 - PAT - Page Attribute Table. */
373 unsigned u1PAT : 1;
374 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
375 unsigned u1PSE36 : 1;
376 /** Bit 18 - PSN - Processor Serial Number. */
377 unsigned u1PSN : 1;
378 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
379 unsigned u1CLFSH : 1;
380 /** Bit 20 - Reserved. */
381 unsigned u1Reserved2 : 1;
382 /** Bit 21 - DS - Debug Store. */
383 unsigned u1DS : 1;
384 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
385 unsigned u1ACPI : 1;
386 /** Bit 23 - MMX - Intel MMX 'Technology'. */
387 unsigned u1MMX : 1;
388 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
389 unsigned u1FXSR : 1;
390 /** Bit 25 - SSE - SSE Support. */
391 unsigned u1SSE : 1;
392 /** Bit 26 - SSE2 - SSE2 Support. */
393 unsigned u1SSE2 : 1;
394 /** Bit 27 - SS - Self Snoop. */
395 unsigned u1SS : 1;
396 /** Bit 28 - HTT - Hyper-Threading Technology. */
397 unsigned u1HTT : 1;
398 /** Bit 29 - TM - Thermal Monitor. */
399 unsigned u1TM : 1;
400 /** Bit 30 - Reserved - . */
401 unsigned u1Reserved3 : 1;
402 /** Bit 31 - PBE - Pending Break Enabled. */
403 unsigned u1PBE : 1;
404} X86CPUIDFEATEDX;
405#else /* VBOX_FOR_DTRACE_LIB */
406typedef uint32_t X86CPUIDFEATEDX;
407#endif /* VBOX_FOR_DTRACE_LIB */
408/** Pointer to CPUID Feature Information - EDX. */
409typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
410/** Pointer to const CPUID Feature Information - EDX. */
411typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
412
413/** @name CPUID Vendor information.
414 * CPUID query with EAX=0.
415 * @{
416 */
417#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
418#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
419#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
420
421#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
422#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
423#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
424
425#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
426#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
427#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
428
429#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
430#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
431#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
432
433#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
434#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
435#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
436/** @} */
437
438
439/** @name CPUID Feature information.
440 * CPUID query with EAX=1.
441 * @{
442 */
443/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
444#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
445/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
446#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
447/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
448#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
449/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
450#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
451/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
452#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
453/** ECX Bit 5 - VMX - Virtual Machine Technology. */
454#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
455/** ECX Bit 6 - SMX - Safer Mode Extensions. */
456#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
457/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
458#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
459/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
460#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
461/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
462#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
463/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
464#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
465/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
466 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
467#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
468/** ECX Bit 12 - FMA. */
469#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
470/** ECX Bit 13 - CX16 - CMPXCHG16B. */
471#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
472/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
473#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
474/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
475#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
476/** ECX Bit 17 - PCID - Process-context identifiers. */
477#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
478/** ECX Bit 18 - DCA - Direct Cache Access. */
479#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
480/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
481#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
482/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
483#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
484/** ECX Bit 21 - x2APIC support. */
485#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
486/** ECX Bit 22 - MOVBE instruction. */
487#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
488/** ECX Bit 23 - POPCNT instruction. */
489#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
490/** ECX Bir 24 - TSC-Deadline. */
491#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
492/** ECX Bit 25 - AES instructions. */
493#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
494/** ECX Bit 26 - XSAVE instruction. */
495#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
496/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
497#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
498/** ECX Bit 28 - AVX. */
499#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
500/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
501#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
502/** ECX Bit 30 - RDRAND instruction. */
503#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
504/** ECX Bit 31 - Hypervisor Present (software only). */
505#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
506
507
508/** Bit 0 - FPU - x87 FPU on Chip. */
509#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
510/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
511#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
512/** Bit 2 - DE - Debugging extensions. */
513#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
514/** Bit 3 - PSE - Page Size Extension. */
515#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
516#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
517/** Bit 4 - TSC - Time Stamp Counter. */
518#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
519/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
520#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
521/** Bit 6 - PAE - Physical Address Extension. */
522#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
523#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
524/** Bit 7 - MCE - Machine Check Exception. */
525#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
526/** Bit 8 - CX8 - CMPXCHG8B instruction. */
527#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
528/** Bit 9 - APIC - APIC On-Chip. */
529#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
530/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
531#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
532/** Bit 12 - MTRR - Memory Type Range Registers. */
533#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
534/** Bit 13 - PGE - PTE Global Bit. */
535#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
536/** Bit 14 - MCA - Machine Check Architecture. */
537#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
538/** Bit 15 - CMOV - Conditional Move Instructions. */
539#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
540/** Bit 16 - PAT - Page Attribute Table. */
541#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
542/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
543#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
544/** Bit 18 - PSN - Processor Serial Number. */
545#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
546/** Bit 19 - CLFSH - CLFLUSH Instruction. */
547#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
548/** Bit 21 - DS - Debug Store. */
549#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
550/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
551#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
552/** Bit 23 - MMX - Intel MMX Technology. */
553#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
554/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
555#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
556/** Bit 25 - SSE - SSE Support. */
557#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
558/** Bit 26 - SSE2 - SSE2 Support. */
559#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
560/** Bit 27 - SS - Self Snoop. */
561#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
562/** Bit 28 - HTT - Hyper-Threading Technology. */
563#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
564/** Bit 29 - TM - Therm. Monitor. */
565#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
566/** Bit 31 - PBE - Pending Break Enabled. */
567#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
568/** @} */
569
570/** @name CPUID mwait/monitor information.
571 * CPUID query with EAX=5.
572 * @{
573 */
574/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
575#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
576/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
577#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
578/** @} */
579
580
581/** @name CPUID Structured Extended Feature information.
582 * CPUID query with EAX=7.
583 * @{
584 */
585/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
586#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
587/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
588#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
589/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
590#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
591/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
592#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
593/** EBX Bit 4 - HLE - Hardware Lock Elision. */
594#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
595/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
596#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
597/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
598#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
599/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
600#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
601/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
602#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
603/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
604#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
605/** EBX Bit 10 - INVPCID - Supports INVPCID. */
606#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
607/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
608#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
609/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
610#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
611/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
612#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
613/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
614#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
615/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
616#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
617/** EBX Bit 16 - AVX512F - Supports AVX512F. */
618#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
619/** EBX Bit 18 - RDSEED - Supports RDSEED. */
620#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
621/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
622#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
623/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
624#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
625/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
626#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
627/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
628#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
629/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
630#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
631/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
632#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
633/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
634#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
635/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
636#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
637
638/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
639#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
640/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
641#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
642/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
643#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
644/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
645#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
646/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
647#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
648/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
649#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
650/** ECX Bit 22 - RDPID - Support pread process ID. */
651#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
652/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
653#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
654
655/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
656#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
657/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
658#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
659/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
660 * IBPB command in IA32_PRED_CMD. */
661#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
662/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
663#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
664/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
665#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
666/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
667#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
668/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
669#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
670
671/** @} */
672
673
674/** @name CPUID Extended Feature information.
675 * CPUID query with EAX=0x80000001.
676 * @{
677 */
678/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
679#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
680
681/** EDX Bit 11 - SYSCALL/SYSRET. */
682#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
683/** EDX Bit 20 - No-Execute/Execute-Disable. */
684#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
685/** EDX Bit 26 - 1 GB large page. */
686#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
687/** EDX Bit 27 - RDTSCP. */
688#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
689/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
690#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
691/** @}*/
692
693/** @name CPUID AMD Feature information.
694 * CPUID query with EAX=0x80000001.
695 * @{
696 */
697/** Bit 0 - FPU - x87 FPU on Chip. */
698#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
699/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
700#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
701/** Bit 2 - DE - Debugging extensions. */
702#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
703/** Bit 3 - PSE - Page Size Extension. */
704#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
705/** Bit 4 - TSC - Time Stamp Counter. */
706#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
707/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
708#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
709/** Bit 6 - PAE - Physical Address Extension. */
710#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
711/** Bit 7 - MCE - Machine Check Exception. */
712#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
713/** Bit 8 - CX8 - CMPXCHG8B instruction. */
714#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
715/** Bit 9 - APIC - APIC On-Chip. */
716#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
717/** Bit 12 - MTRR - Memory Type Range Registers. */
718#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
719/** Bit 13 - PGE - PTE Global Bit. */
720#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
721/** Bit 14 - MCA - Machine Check Architecture. */
722#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
723/** Bit 15 - CMOV - Conditional Move Instructions. */
724#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
725/** Bit 16 - PAT - Page Attribute Table. */
726#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
727/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
728#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
729/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
730#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
731/** Bit 23 - MMX - Intel MMX Technology. */
732#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
733/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
734#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
735/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
736#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
737/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
738#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
739/** Bit 31 - 3DNOW - AMD 3DNow. */
740#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
741
742/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
743#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
744/** Bit 2 - SVM - AMD VM extensions. */
745#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
746/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
747#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
748/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
749#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
750/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
751#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
752/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
753#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
754/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
755#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
756/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
757#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
758/** Bit 9 - OSVW - AMD OS visible workaround. */
759#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
760/** Bit 10 - IBS - Instruct based sampling. */
761#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
762/** Bit 11 - XOP - Extended operation support (see APM6). */
763#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
764/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
765#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
766/** Bit 13 - WDT - AMD Watchdog timer support. */
767#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
768/** Bit 15 - LWP - Lightweight profiling support. */
769#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
770/** Bit 16 - FMA4 - Four operand FMA instruction support. */
771#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
772/** Bit 19 - NodeId - Indicates support for
773 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
774#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
775/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
776#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
777/** Bit 22 - TopologyExtensions - . */
778#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
779/** @} */
780
781
782/** @name CPUID AMD Feature information.
783 * CPUID query with EAX=0x80000007.
784 * @{
785 */
786/** Bit 0 - TS - Temperature Sensor. */
787#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
788/** Bit 1 - FID - Frequency ID Control. */
789#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
790/** Bit 2 - VID - Voltage ID Control. */
791#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
792/** Bit 3 - TTP - THERMTRIP. */
793#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
794/** Bit 4 - TM - Hardware Thermal Control. */
795#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
796/** Bit 5 - STC - Software Thermal Control. */
797#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
798/** Bit 6 - MC - 100 Mhz Multiplier Control. */
799#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
800/** Bit 7 - HWPSTATE - Hardware P-State Control. */
801#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
802/** Bit 8 - TSCINVAR - TSC Invariant. */
803#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
804/** Bit 9 - CPB - TSC Invariant. */
805#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
806/** Bit 10 - EffFreqRO - MPERF/APERF. */
807#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
808/** Bit 11 - PFI - Processor feedback interface (see EAX). */
809#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
810/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
811#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
812/** @} */
813
814
815/** @name CPUID AMD extended feature extensions ID (EBX).
816 * CPUID query with EAX=0x80000008.
817 * @{
818 */
819/** Bit 0 - CLZERO - Clear zero instruction. */
820#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
821/** Bit 1 - IRPerf - Instructions retired count support. */
822#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
823/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
824#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
825/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
826#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
827/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
828#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
829/* AMD pipeline length: 9 feature bits ;-) */
830/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
831#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
832/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
833#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
834/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
835#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
836/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
837#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
838/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
839#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
840/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
841#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
842/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
843#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
844/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
845#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
846/** Bit 26 - Speculative Store Bypass Disable not required. */
847#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
848/** @} */
849
850
851/** @name CPUID AMD SVM Feature information.
852 * CPUID query with EAX=0x8000000a.
853 * @{
854 */
855/** Bit 0 - NP - Nested Paging supported. */
856#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
857/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
858#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
859/** Bit 2 - SVML - SVM locking bit supported. */
860#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
861/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
862#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
863/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
864#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
865/** Bit 5 - VmcbClean - Support VMCB clean bits. */
866#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
867/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
868 * VMCB.TLB_Control is supported. */
869#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
870/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
871#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
872/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
873#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
874/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
875 * intercept filter cycle count threshold. */
876#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
877/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
878#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
879/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
880#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
881/** Bit 16 - VGIF - Supports virtualized GIF. */
882#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
883/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
884#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
885/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
886#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
887/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
888#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
889/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
890#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
891/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
892#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
893/** @} */
894
895
896/** @name CR0
897 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
898 * reserved flags.
899 * @{ */
900/** Bit 0 - PE - Protection Enabled */
901#define X86_CR0_PE RT_BIT_32(0)
902#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
903/** Bit 1 - MP - Monitor Coprocessor */
904#define X86_CR0_MP RT_BIT_32(1)
905#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
906/** Bit 2 - EM - Emulation. */
907#define X86_CR0_EM RT_BIT_32(2)
908#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
909/** Bit 3 - TS - Task Switch. */
910#define X86_CR0_TS RT_BIT_32(3)
911#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
912/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
913#define X86_CR0_ET RT_BIT_32(4)
914#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
915/** Bit 5 - NE - Numeric error (486+). */
916#define X86_CR0_NE RT_BIT_32(5)
917#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
918/** Bit 16 - WP - Write Protect (486+). */
919#define X86_CR0_WP RT_BIT_32(16)
920#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
921/** Bit 18 - AM - Alignment Mask (486+). */
922#define X86_CR0_AM RT_BIT_32(18)
923#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
924/** Bit 29 - NW - Not Write-though (486+). */
925#define X86_CR0_NW RT_BIT_32(29)
926#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
927/** Bit 30 - WP - Cache Disable (486+). */
928#define X86_CR0_CD RT_BIT_32(30)
929#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
930/** Bit 31 - PG - Paging. */
931#define X86_CR0_PG RT_BIT_32(31)
932#define X86_CR0_PAGING RT_BIT_32(31)
933#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
934/** @} */
935
936
937/** @name CR3
938 * @{ */
939/** Bit 3 - PWT - Page-level Writes Transparent. */
940#define X86_CR3_PWT RT_BIT_32(3)
941/** Bit 4 - PCD - Page-level Cache Disable. */
942#define X86_CR3_PCD RT_BIT_32(4)
943/** Bits 12-31 - - Page directory page number. */
944#define X86_CR3_PAGE_MASK (0xfffff000)
945/** Bits 5-31 - - PAE Page directory page number. */
946#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
947/** Bits 12-51 - - AMD64 PML4 page number.
948 * @note This is a maxed out mask, the actual acceptable CR3 value can
949 * be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
950#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
951/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
952 * @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
953 * be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
954#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
955/** @} */
956
957
958/** @name CR4
959 * @{ */
960/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
961#define X86_CR4_VME RT_BIT_32(0)
962/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
963#define X86_CR4_PVI RT_BIT_32(1)
964/** Bit 2 - TSD - Time Stamp Disable. */
965#define X86_CR4_TSD RT_BIT_32(2)
966/** Bit 3 - DE - Debugging Extensions. */
967#define X86_CR4_DE RT_BIT_32(3)
968/** Bit 4 - PSE - Page Size Extension. */
969#define X86_CR4_PSE RT_BIT_32(4)
970/** Bit 5 - PAE - Physical Address Extension. */
971#define X86_CR4_PAE RT_BIT_32(5)
972/** Bit 6 - MCE - Machine-Check Enable. */
973#define X86_CR4_MCE RT_BIT_32(6)
974/** Bit 7 - PGE - Page Global Enable. */
975#define X86_CR4_PGE RT_BIT_32(7)
976/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
977#define X86_CR4_PCE RT_BIT_32(8)
978/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
979#define X86_CR4_OSFXSR RT_BIT_32(9)
980/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
981#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
982/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
983#define X86_CR4_UMIP RT_BIT_32(11)
984/** Bit 13 - VMXE - VMX mode is enabled. */
985#define X86_CR4_VMXE RT_BIT_32(13)
986/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
987#define X86_CR4_SMXE RT_BIT_32(14)
988/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
989#define X86_CR4_FSGSBASE RT_BIT_32(16)
990/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
991#define X86_CR4_PCIDE RT_BIT_32(17)
992/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
993 * extended states. */
994#define X86_CR4_OSXSAVE RT_BIT_32(18)
995/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
996#define X86_CR4_SMEP RT_BIT_32(20)
997/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
998#define X86_CR4_SMAP RT_BIT_32(21)
999/** Bit 22 - PKE - Protection Key Enable. */
1000#define X86_CR4_PKE RT_BIT_32(22)
1001/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1002#define X86_CR4_CET RT_BIT_32(23)
1003/** @} */
1004
1005
1006/** @name DR6
1007 * @{ */
1008/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1009#define X86_DR6_B0 RT_BIT_32(0)
1010/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1011#define X86_DR6_B1 RT_BIT_32(1)
1012/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1013#define X86_DR6_B2 RT_BIT_32(2)
1014/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1015#define X86_DR6_B3 RT_BIT_32(3)
1016/** Mask of all the Bx bits. */
1017#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1018/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1019#define X86_DR6_BD RT_BIT_32(13)
1020/** Bit 14 - BS - Single step */
1021#define X86_DR6_BS RT_BIT_32(14)
1022/** Bit 15 - BT - Task switch. (TSS T bit.) */
1023#define X86_DR6_BT RT_BIT_32(15)
1024/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1025#define X86_DR6_RTM RT_BIT_32(16)
1026/** Value of DR6 after powerup/reset. */
1027#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1028/** Bits which must be 1s in DR6. */
1029#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1030/** Bits which must be 1s in DR6, when RTM is supported. */
1031#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1032/** Bits which must be 0s in DR6. */
1033#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1034/** Bits which must be 0s on writes to DR6. */
1035#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1036/** @} */
1037
1038/** Get the DR6.Bx bit for a the given breakpoint. */
1039#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1040
1041
1042/** @name DR7
1043 * @{ */
1044/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1045#define X86_DR7_L0 RT_BIT_32(0)
1046/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1047#define X86_DR7_G0 RT_BIT_32(1)
1048/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1049#define X86_DR7_L1 RT_BIT_32(2)
1050/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1051#define X86_DR7_G1 RT_BIT_32(3)
1052/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1053#define X86_DR7_L2 RT_BIT_32(4)
1054/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1055#define X86_DR7_G2 RT_BIT_32(5)
1056/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1057#define X86_DR7_L3 RT_BIT_32(6)
1058/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1059#define X86_DR7_G3 RT_BIT_32(7)
1060/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1061#define X86_DR7_LE RT_BIT_32(8)
1062/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1063#define X86_DR7_GE RT_BIT_32(9)
1064
1065/** L0, L1, L2, and L3. */
1066#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1067/** L0, L1, L2, and L3. */
1068#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1069
1070/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1071 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1072#define X86_DR7_RTM RT_BIT_32(11)
1073/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1074 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1075 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1076 * instruction is executed.
1077 * @see http://www.rcollins.org/secrets/DR7.html */
1078#define X86_DR7_ICE_IR RT_BIT_32(12)
1079/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1080 * any DR register is accessed. */
1081#define X86_DR7_GD RT_BIT_32(13)
1082/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1083 * Pentium. */
1084#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1085/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1086#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1087/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1088#define X86_DR7_RW0_MASK (3 << 16)
1089/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1090#define X86_DR7_LEN0_MASK (3 << 18)
1091/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1092#define X86_DR7_RW1_MASK (3 << 20)
1093/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1094#define X86_DR7_LEN1_MASK (3 << 22)
1095/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1096#define X86_DR7_RW2_MASK (3 << 24)
1097/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1098#define X86_DR7_LEN2_MASK (3 << 26)
1099/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1100#define X86_DR7_RW3_MASK (3 << 28)
1101/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1102#define X86_DR7_LEN3_MASK (3 << 30)
1103
1104/** Bits which reads as 1s. */
1105#define X86_DR7_RA1_MASK RT_BIT_32(10)
1106/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1107#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1108/** Bits which must be 0s when writing to DR7. */
1109#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1110
1111/** Calcs the L bit of Nth breakpoint.
1112 * @param iBp The breakpoint number [0..3].
1113 */
1114#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1115
1116/** Calcs the G bit of Nth breakpoint.
1117 * @param iBp The breakpoint number [0..3].
1118 */
1119#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1120
1121/** Calcs the L and G bits of Nth breakpoint.
1122 * @param iBp The breakpoint number [0..3].
1123 */
1124#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1125
1126/** @name Read/Write values.
1127 * @{ */
1128/** Break on instruction fetch only. */
1129#define X86_DR7_RW_EO UINT32_C(0)
1130/** Break on write only. */
1131#define X86_DR7_RW_WO UINT32_C(1)
1132/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1133#define X86_DR7_RW_IO UINT32_C(2)
1134/** Break on read or write (but not instruction fetches). */
1135#define X86_DR7_RW_RW UINT32_C(3)
1136/** @} */
1137
1138/** Shifts a X86_DR7_RW_* value to its right place.
1139 * @param iBp The breakpoint number [0..3].
1140 * @param fRw One of the X86_DR7_RW_* value.
1141 */
1142#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1143
1144/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1145 * one of the X86_DR7_RW_XXX constants).
1146 *
1147 * @returns X86_DR7_RW_XXX
1148 * @param uDR7 DR7 value
1149 * @param iBp The breakpoint number [0..3].
1150 */
1151#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1152
1153/** R/W0, R/W1, R/W2, and R/W3. */
1154#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1155
1156#ifndef VBOX_FOR_DTRACE_LIB
1157/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1158 * @note This does not check if it's enabled. */
1159# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1160/** Checks if an instruction breakpoint is enabled and configured correctly.
1161 * @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1162# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1163 ( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1164/** Checks if there are any instruction fetch breakpoint types configured in the
1165 * RW and LEN registers.
1166 * @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1167# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1168 ( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1169 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1170 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1171 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1172
1173/** Checks if there are any I/O breakpoint types configured in the RW
1174 * registers. Does NOT check if these are enabled, sorry. */
1175# define X86_DR7_ANY_RW_IO(uDR7) \
1176 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1177 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1178AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1179AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1180AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1181AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1182AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1183AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1184AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1185AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1186AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1187
1188#endif /* !VBOX_FOR_DTRACE_LIB */
1189
1190/** @name Length values.
1191 * @{ */
1192#define X86_DR7_LEN_BYTE UINT32_C(0)
1193#define X86_DR7_LEN_WORD UINT32_C(1)
1194#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1195#define X86_DR7_LEN_DWORD UINT32_C(3)
1196/** @} */
1197
1198/** Shifts a X86_DR7_LEN_* value to its right place.
1199 * @param iBp The breakpoint number [0..3].
1200 * @param cb One of the X86_DR7_LEN_* values.
1201 */
1202#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1203
1204/** Fetch the breakpoint length bits from the DR7 value.
1205 * @param uDR7 DR7 value
1206 * @param iBp The breakpoint number [0..3].
1207 */
1208#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1209
1210/** Mask used to check if any breakpoints are enabled. */
1211#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1212
1213/** LEN0, LEN1, LEN2, and LEN3. */
1214#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1215/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1216#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1217
1218/** Value of DR7 after powerup/reset. */
1219#define X86_DR7_INIT_VAL 0x400
1220/** @} */
1221
1222
1223/** @name Machine Specific Registers
1224 * @{
1225 */
1226/** Machine check address register (P5). */
1227#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1228/** Machine check type register (P5). */
1229#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1230/** Time Stamp Counter. */
1231#define MSR_IA32_TSC 0x10
1232#define MSR_IA32_CESR UINT32_C(0x00000011)
1233#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1234#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1235
1236#define MSR_IA32_PLATFORM_ID 0x17
1237
1238#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1239# define MSR_IA32_APICBASE 0x1b
1240/** Local APIC enabled. */
1241# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1242/** X2APIC enabled (requires the EN bit to be set). */
1243# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1244/** The processor is the boot strap processor (BSP). */
1245# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1246/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1247 * width. */
1248# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1249/** The default physical base address of the APIC. */
1250# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1251/** Gets the physical base address from the MSR. */
1252# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1253#endif
1254
1255/** Undocumented intel MSR for reporting thread and core counts.
1256 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1257 * first 16 bits is the thread count. The next 16 bits the core count, except
1258 * on Westmere where it seems it's only the next 4 bits for some reason. */
1259#define MSR_CORE_THREAD_COUNT 0x35
1260
1261/** CPU Feature control. */
1262#define MSR_IA32_FEATURE_CONTROL 0x3A
1263/** Feature control - Lock MSR from writes (R/W0). */
1264#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1265/** Feature control - Enable VMX inside SMX operation (R/WL). */
1266#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1267/** Feature control - Enable VMX outside SMX operation (R/WL). */
1268#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1269/** Feature control - SENTER local functions enable (R/WL). */
1270#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1271#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1272#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1273#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1274#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1275#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1276#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1277/** Feature control - SENTER global enable (R/WL). */
1278#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1279/** Feature control - SGX launch control enable (R/WL). */
1280#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1281/** Feature control - SGX global enable (R/WL). */
1282#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1283/** Feature control - LMCE on (R/WL). */
1284#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1285
1286/** Per-processor TSC adjust MSR. */
1287#define MSR_IA32_TSC_ADJUST 0x3B
1288
1289/** Spectre control register.
1290 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1291#define MSR_IA32_SPEC_CTRL 0x48
1292/** IBRS - Indirect branch restricted speculation. */
1293#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1294/** STIBP - Single thread indirect branch predictors. */
1295#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1296/** SSBD - Speculative Store Bypass Disable. */
1297#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1298
1299/** Prediction command register.
1300 * Write only, logical processor scope, no state since write only. */
1301#define MSR_IA32_PRED_CMD 0x49
1302/** IBPB - Indirect branch prediction barrie when written as 1. */
1303#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1304
1305/** BIOS update trigger (microcode update). */
1306#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1307
1308/** BIOS update signature (microcode). */
1309#define MSR_IA32_BIOS_SIGN_ID 0x8B
1310
1311/** SMM monitor control. */
1312#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1313/** SMM control - Valid. */
1314#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1315/** SMM control - VMXOFF unblocks SMI. */
1316#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1317/** SMM control - MSEG base physical address. */
1318#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1319
1320/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1321#define MSR_IA32_SMBASE 0x9E
1322
1323/** General performance counter no. 0. */
1324#define MSR_IA32_PMC0 0xC1
1325/** General performance counter no. 1. */
1326#define MSR_IA32_PMC1 0xC2
1327/** General performance counter no. 2. */
1328#define MSR_IA32_PMC2 0xC3
1329/** General performance counter no. 3. */
1330#define MSR_IA32_PMC3 0xC4
1331/** General performance counter no. 4. */
1332#define MSR_IA32_PMC4 0xC5
1333/** General performance counter no. 5. */
1334#define MSR_IA32_PMC5 0xC6
1335/** General performance counter no. 6. */
1336#define MSR_IA32_PMC6 0xC7
1337/** General performance counter no. 7. */
1338#define MSR_IA32_PMC7 0xC8
1339
1340/** Nehalem power control. */
1341#define MSR_IA32_PLATFORM_INFO 0xCE
1342
1343/** Get FSB clock status (Intel-specific). */
1344#define MSR_IA32_FSB_CLOCK_STS 0xCD
1345
1346/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1347#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1348
1349/** C0 Maximum Frequency Clock Count */
1350#define MSR_IA32_MPERF 0xE7
1351/** C0 Actual Frequency Clock Count */
1352#define MSR_IA32_APERF 0xE8
1353
1354/** MTRR Capabilities. */
1355#define MSR_IA32_MTRR_CAP 0xFE
1356
1357/** Architecture capabilities (bugfixes). */
1358#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1359/** CPU is no subject to meltdown problems. */
1360#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1361/** CPU has better IBRS and you can leave it on all the time. */
1362#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1363/** CPU has return stack buffer (RSB) override. */
1364#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1365/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1366 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1367#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1368/** CPU does not suffer from MDS issues. */
1369#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1370
1371/** Flush command register. */
1372#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1373/** Flush the level 1 data cache when this bit is written. */
1374#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1375
1376/** Cache control/info. */
1377#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1378
1379#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1380/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1381 * R0 SS == CS + 8
1382 * R3 CS == CS + 16
1383 * R3 SS == CS + 24
1384 */
1385#define MSR_IA32_SYSENTER_CS 0x174
1386/** SYSENTER_ESP - the R0 ESP. */
1387#define MSR_IA32_SYSENTER_ESP 0x175
1388/** SYSENTER_EIP - the R0 EIP. */
1389#define MSR_IA32_SYSENTER_EIP 0x176
1390#endif
1391
1392/** Machine Check Global Capabilities Register. */
1393#define MSR_IA32_MCG_CAP 0x179
1394/** Machine Check Global Status Register. */
1395#define MSR_IA32_MCG_STATUS 0x17A
1396/** Machine Check Global Control Register. */
1397#define MSR_IA32_MCG_CTRL 0x17B
1398
1399/** Page Attribute Table. */
1400#define MSR_IA32_CR_PAT 0x277
1401/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1402 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1403#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1404
1405/** Performance event select MSRs. (Intel only) */
1406#define MSR_IA32_PERFEVTSEL0 0x186
1407#define MSR_IA32_PERFEVTSEL1 0x187
1408#define MSR_IA32_PERFEVTSEL2 0x188
1409#define MSR_IA32_PERFEVTSEL3 0x189
1410
1411/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1412 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1413 * holds a ratio that Apple takes for TSC granularity.
1414 *
1415 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1416#define MSR_FLEX_RATIO 0x194
1417/** Performance state value and starting with Intel core more.
1418 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1419#define MSR_IA32_PERF_STATUS 0x198
1420#define MSR_IA32_PERF_CTL 0x199
1421#define MSR_IA32_THERM_STATUS 0x19c
1422
1423/** Offcore response event select registers. */
1424#define MSR_OFFCORE_RSP_0 0x1a6
1425#define MSR_OFFCORE_RSP_1 0x1a7
1426
1427/** Enable misc. processor features (R/W). */
1428#define MSR_IA32_MISC_ENABLE 0x1A0
1429/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1430#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1431/** Automatic Thermal Control Circuit Enable (R/W). */
1432#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1433/** Performance Monitoring Available (R). */
1434#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1435/** Branch Trace Storage Unavailable (R/O). */
1436#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1437/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1438#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1439/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1440#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1441/** If MONITOR/MWAIT is supported (R/W). */
1442#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1443/** Limit CPUID Maxval to 3 leafs (R/W). */
1444#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1445/** When set to 1, xTPR messages are disabled (R/W). */
1446#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1447/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1448#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1449
1450/** Trace/Profile Resource Control (R/W) */
1451#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1452/** Last branch record. */
1453#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1454/** Branch trace flag (single step on branches). */
1455#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1456/** Performance monitoring pin control (AMD only). */
1457#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1458#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1459#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1460#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1461/** Trace message enable (Intel only). */
1462#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1463/** Branch trace store (Intel only). */
1464#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1465/** Branch trace interrupt (Intel only). */
1466#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1467/** Branch trace off in privileged code (Intel only). */
1468#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1469/** Branch trace off in user code (Intel only). */
1470#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1471/** Freeze LBR on PMI flag (Intel only). */
1472#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1473/** Freeze PERFMON on PMI flag (Intel only). */
1474#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1475/** Freeze while SMM enabled (Intel only). */
1476#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1477/** Advanced debugging of RTM regions (Intel only). */
1478#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1479/** Debug control MSR valid bits (Intel only). */
1480#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1481 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1482 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1483 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1484 | MSR_IA32_DEBUGCTL_RTM)
1485
1486/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1487 * @{ */
1488#define MSR_P4_LASTBRANCH_0 0x1db
1489#define MSR_P4_LASTBRANCH_1 0x1dc
1490#define MSR_P4_LASTBRANCH_2 0x1dd
1491#define MSR_P4_LASTBRANCH_3 0x1de
1492
1493/** LBR Top-of-stack MSR (index to most recent record). */
1494#define MSR_P4_LASTBRANCH_TOS 0x1da
1495/** @} */
1496
1497/** @name Last branch registers for Core 2 and related Xeons.
1498 * @{ */
1499#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1500#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1501#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1502#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1503
1504#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1505#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1506#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1507#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1508
1509/** LBR Top-of-stack MSR (index to most recent record). */
1510#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1511/** @} */
1512
1513/** @name Last branch registers.
1514 * @{ */
1515#define MSR_LASTBRANCH_0_FROM_IP 0x680
1516#define MSR_LASTBRANCH_1_FROM_IP 0x681
1517#define MSR_LASTBRANCH_2_FROM_IP 0x682
1518#define MSR_LASTBRANCH_3_FROM_IP 0x683
1519#define MSR_LASTBRANCH_4_FROM_IP 0x684
1520#define MSR_LASTBRANCH_5_FROM_IP 0x685
1521#define MSR_LASTBRANCH_6_FROM_IP 0x686
1522#define MSR_LASTBRANCH_7_FROM_IP 0x687
1523#define MSR_LASTBRANCH_8_FROM_IP 0x688
1524#define MSR_LASTBRANCH_9_FROM_IP 0x689
1525#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1526#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1527#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1528#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1529#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1530#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1531#define MSR_LASTBRANCH_16_FROM_IP 0x690
1532#define MSR_LASTBRANCH_17_FROM_IP 0x691
1533#define MSR_LASTBRANCH_18_FROM_IP 0x692
1534#define MSR_LASTBRANCH_19_FROM_IP 0x693
1535#define MSR_LASTBRANCH_20_FROM_IP 0x694
1536#define MSR_LASTBRANCH_21_FROM_IP 0x695
1537#define MSR_LASTBRANCH_22_FROM_IP 0x696
1538#define MSR_LASTBRANCH_23_FROM_IP 0x697
1539#define MSR_LASTBRANCH_24_FROM_IP 0x698
1540#define MSR_LASTBRANCH_25_FROM_IP 0x699
1541#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1542#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1543#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1544#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1545#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1546#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1547
1548#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1549#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1550#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1551#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1552#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1553#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1554#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1555#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1556#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1557#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1558#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1559#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1560#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1561#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1562#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1563#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1564#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1565#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1566#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1567#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1568#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1569#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1570#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1571#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1572#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1573#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1574#define MSR_LASTBRANCH_26_TO_IP 0x6da
1575#define MSR_LASTBRANCH_27_TO_IP 0x6db
1576#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1577#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1578#define MSR_LASTBRANCH_30_TO_IP 0x6de
1579#define MSR_LASTBRANCH_31_TO_IP 0x6df
1580
1581#define MSR_LASTBRANCH_0_INFO 0xdc0
1582#define MSR_LASTBRANCH_1_INFO 0xdc1
1583#define MSR_LASTBRANCH_2_INFO 0xdc2
1584#define MSR_LASTBRANCH_3_INFO 0xdc3
1585#define MSR_LASTBRANCH_4_INFO 0xdc4
1586#define MSR_LASTBRANCH_5_INFO 0xdc5
1587#define MSR_LASTBRANCH_6_INFO 0xdc6
1588#define MSR_LASTBRANCH_7_INFO 0xdc7
1589#define MSR_LASTBRANCH_8_INFO 0xdc8
1590#define MSR_LASTBRANCH_9_INFO 0xdc9
1591#define MSR_LASTBRANCH_10_INFO 0xdca
1592#define MSR_LASTBRANCH_11_INFO 0xdcb
1593#define MSR_LASTBRANCH_12_INFO 0xdcc
1594#define MSR_LASTBRANCH_13_INFO 0xdcd
1595#define MSR_LASTBRANCH_14_INFO 0xdce
1596#define MSR_LASTBRANCH_15_INFO 0xdcf
1597#define MSR_LASTBRANCH_16_INFO 0xdd0
1598#define MSR_LASTBRANCH_17_INFO 0xdd1
1599#define MSR_LASTBRANCH_18_INFO 0xdd2
1600#define MSR_LASTBRANCH_19_INFO 0xdd3
1601#define MSR_LASTBRANCH_20_INFO 0xdd4
1602#define MSR_LASTBRANCH_21_INFO 0xdd5
1603#define MSR_LASTBRANCH_22_INFO 0xdd6
1604#define MSR_LASTBRANCH_23_INFO 0xdd7
1605#define MSR_LASTBRANCH_24_INFO 0xdd8
1606#define MSR_LASTBRANCH_25_INFO 0xdd9
1607#define MSR_LASTBRANCH_26_INFO 0xdda
1608#define MSR_LASTBRANCH_27_INFO 0xddb
1609#define MSR_LASTBRANCH_28_INFO 0xddc
1610#define MSR_LASTBRANCH_29_INFO 0xddd
1611#define MSR_LASTBRANCH_30_INFO 0xdde
1612#define MSR_LASTBRANCH_31_INFO 0xddf
1613
1614/** LBR branch tracking selection MSR. */
1615#define MSR_LASTBRANCH_SELECT 0x1c8
1616/** LBR Top-of-stack MSR (index to most recent record). */
1617#define MSR_LASTBRANCH_TOS 0x1c9
1618/** @} */
1619
1620/** @name Last event record registers.
1621 * @{ */
1622/** Last event record source IP register. */
1623#define MSR_LER_FROM_IP 0x1dd
1624/** Last event record destination IP register. */
1625#define MSR_LER_TO_IP 0x1de
1626/** @} */
1627
1628/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1629#define MSR_IA32_TSX_CTRL 0x122
1630
1631/** Variable range MTRRs.
1632 * @{ */
1633#define MSR_IA32_MTRR_PHYSBASE0 0x200
1634#define MSR_IA32_MTRR_PHYSMASK0 0x201
1635#define MSR_IA32_MTRR_PHYSBASE1 0x202
1636#define MSR_IA32_MTRR_PHYSMASK1 0x203
1637#define MSR_IA32_MTRR_PHYSBASE2 0x204
1638#define MSR_IA32_MTRR_PHYSMASK2 0x205
1639#define MSR_IA32_MTRR_PHYSBASE3 0x206
1640#define MSR_IA32_MTRR_PHYSMASK3 0x207
1641#define MSR_IA32_MTRR_PHYSBASE4 0x208
1642#define MSR_IA32_MTRR_PHYSMASK4 0x209
1643#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1644#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1645#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1646#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1647#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1648#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1649#define MSR_IA32_MTRR_PHYSBASE8 0x210
1650#define MSR_IA32_MTRR_PHYSMASK8 0x211
1651#define MSR_IA32_MTRR_PHYSBASE9 0x212
1652#define MSR_IA32_MTRR_PHYSMASK9 0x213
1653/** @} */
1654
1655/** Fixed range MTRRs.
1656 * @{ */
1657#define MSR_IA32_MTRR_FIX64K_00000 0x250
1658#define MSR_IA32_MTRR_FIX16K_80000 0x258
1659#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1660#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1661#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1662#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1663#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1664#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1665#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1666#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1667#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1668/** @} */
1669
1670/** MTRR Default Range. */
1671#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1672
1673/** Global performance counter control facilities (Intel only). */
1674#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1675#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1676#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1677
1678/** Precise Event Based sampling (Intel only). */
1679#define MSR_IA32_PEBS_ENABLE 0x3F1
1680
1681#define MSR_IA32_MC0_CTL 0x400
1682#define MSR_IA32_MC0_STATUS 0x401
1683
1684/** Basic VMX information. */
1685#define MSR_IA32_VMX_BASIC 0x480
1686/** Allowed settings for pin-based VM execution controls. */
1687#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1688/** Allowed settings for proc-based VM execution controls. */
1689#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1690/** Allowed settings for the VM-exit controls. */
1691#define MSR_IA32_VMX_EXIT_CTLS 0x483
1692/** Allowed settings for the VM-entry controls. */
1693#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1694/** Misc VMX info. */
1695#define MSR_IA32_VMX_MISC 0x485
1696/** Fixed cleared bits in CR0. */
1697#define MSR_IA32_VMX_CR0_FIXED0 0x486
1698/** Fixed set bits in CR0. */
1699#define MSR_IA32_VMX_CR0_FIXED1 0x487
1700/** Fixed cleared bits in CR4. */
1701#define MSR_IA32_VMX_CR4_FIXED0 0x488
1702/** Fixed set bits in CR4. */
1703#define MSR_IA32_VMX_CR4_FIXED1 0x489
1704/** Information for enumerating fields in the VMCS. */
1705#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1706/** Allowed settings for secondary processor-based VM-execution controls. */
1707#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1708/** EPT capabilities. */
1709#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1710/** Allowed settings of all pin-based VM execution controls. */
1711#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1712/** Allowed settings of all proc-based VM execution controls. */
1713#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1714/** Allowed settings of all VMX exit controls. */
1715#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1716/** Allowed settings of all VMX entry controls. */
1717#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1718/** Allowed settings for the VM-function controls. */
1719#define MSR_IA32_VMX_VMFUNC 0x491
1720/** Tertiary processor-based VM execution controls. */
1721#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1722/** Secondary VM-exit controls. */
1723#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1724
1725/** Intel PT - Enable and control for trace packet generation. */
1726#define MSR_IA32_RTIT_CTL 0x570
1727
1728/** DS Save Area (R/W). */
1729#define MSR_IA32_DS_AREA 0x600
1730/** Running Average Power Limit (RAPL) power units. */
1731#define MSR_RAPL_POWER_UNIT 0x606
1732/** Package C3 Interrupt Response Limit. */
1733#define MSR_PKGC3_IRTL 0x60a
1734/** Package C6/C7S Interrupt Response Limit 1. */
1735#define MSR_PKGC_IRTL1 0x60b
1736/** Package C6/C7S Interrupt Response Limit 2. */
1737#define MSR_PKGC_IRTL2 0x60c
1738/** Package C2 Residency Counter. */
1739#define MSR_PKG_C2_RESIDENCY 0x60d
1740/** PKG RAPL Power Limit Control. */
1741#define MSR_PKG_POWER_LIMIT 0x610
1742/** PKG Energy Status. */
1743#define MSR_PKG_ENERGY_STATUS 0x611
1744/** PKG Perf Status. */
1745#define MSR_PKG_PERF_STATUS 0x613
1746/** PKG RAPL Parameters. */
1747#define MSR_PKG_POWER_INFO 0x614
1748/** DRAM RAPL Power Limit Control. */
1749#define MSR_DRAM_POWER_LIMIT 0x618
1750/** DRAM Energy Status. */
1751#define MSR_DRAM_ENERGY_STATUS 0x619
1752/** DRAM Performance Throttling Status. */
1753#define MSR_DRAM_PERF_STATUS 0x61b
1754/** DRAM RAPL Parameters. */
1755#define MSR_DRAM_POWER_INFO 0x61c
1756/** Package C10 Residency Counter. */
1757#define MSR_PKG_C10_RESIDENCY 0x632
1758/** PP0 Energy Status. */
1759#define MSR_PP0_ENERGY_STATUS 0x639
1760/** PP1 Energy Status. */
1761#define MSR_PP1_ENERGY_STATUS 0x641
1762/** Turbo Activation Ratio. */
1763#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1764/** Core Performance Limit Reasons. */
1765#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1766
1767/** Userspace Control flow Enforcement Technology setting. */
1768#define MSR_IA32_U_CET 0x6a0
1769/** Supervisor space Control flow Enforcement Technology setting. */
1770#define MSR_IA32_S_CET 0x6a2
1771/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1772 * @{ */
1773/** Enables the Shadow stack. */
1774# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1775/** Enables WRSS{D,Q}W instructions. */
1776# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1777/** Enables indirect branch tracking. */
1778# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1779/** Enable legacy compatibility treatment for indirect branch tracking. */
1780# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1781/** Enables the use of no-track prefix for indirect branch tracking. */
1782# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1783/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1784# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1785/** Suppresses indirect branch tracking. */
1786# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
1787/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
1788# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
1789/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
1790 * on a ENDBRANCH instruction. */
1791# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
1792/** @} */
1793
1794/** X2APIC MSR range start. */
1795#define MSR_IA32_X2APIC_START 0x800
1796/** X2APIC MSR - APIC ID Register. */
1797#define MSR_IA32_X2APIC_ID 0x802
1798/** X2APIC MSR - APIC Version Register. */
1799#define MSR_IA32_X2APIC_VERSION 0x803
1800/** X2APIC MSR - Task Priority Register. */
1801#define MSR_IA32_X2APIC_TPR 0x808
1802/** X2APIC MSR - Processor Priority register. */
1803#define MSR_IA32_X2APIC_PPR 0x80A
1804/** X2APIC MSR - End Of Interrupt register. */
1805#define MSR_IA32_X2APIC_EOI 0x80B
1806/** X2APIC MSR - Logical Destination Register. */
1807#define MSR_IA32_X2APIC_LDR 0x80D
1808/** X2APIC MSR - Spurious Interrupt Vector Register. */
1809#define MSR_IA32_X2APIC_SVR 0x80F
1810/** X2APIC MSR - In-service Register (bits 31:0). */
1811#define MSR_IA32_X2APIC_ISR0 0x810
1812/** X2APIC MSR - In-service Register (bits 63:32). */
1813#define MSR_IA32_X2APIC_ISR1 0x811
1814/** X2APIC MSR - In-service Register (bits 95:64). */
1815#define MSR_IA32_X2APIC_ISR2 0x812
1816/** X2APIC MSR - In-service Register (bits 127:96). */
1817#define MSR_IA32_X2APIC_ISR3 0x813
1818/** X2APIC MSR - In-service Register (bits 159:128). */
1819#define MSR_IA32_X2APIC_ISR4 0x814
1820/** X2APIC MSR - In-service Register (bits 191:160). */
1821#define MSR_IA32_X2APIC_ISR5 0x815
1822/** X2APIC MSR - In-service Register (bits 223:192). */
1823#define MSR_IA32_X2APIC_ISR6 0x816
1824/** X2APIC MSR - In-service Register (bits 255:224). */
1825#define MSR_IA32_X2APIC_ISR7 0x817
1826/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1827#define MSR_IA32_X2APIC_TMR0 0x818
1828/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1829#define MSR_IA32_X2APIC_TMR1 0x819
1830/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1831#define MSR_IA32_X2APIC_TMR2 0x81A
1832/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1833#define MSR_IA32_X2APIC_TMR3 0x81B
1834/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1835#define MSR_IA32_X2APIC_TMR4 0x81C
1836/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1837#define MSR_IA32_X2APIC_TMR5 0x81D
1838/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1839#define MSR_IA32_X2APIC_TMR6 0x81E
1840/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1841#define MSR_IA32_X2APIC_TMR7 0x81F
1842/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1843#define MSR_IA32_X2APIC_IRR0 0x820
1844/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1845#define MSR_IA32_X2APIC_IRR1 0x821
1846/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1847#define MSR_IA32_X2APIC_IRR2 0x822
1848/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1849#define MSR_IA32_X2APIC_IRR3 0x823
1850/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1851#define MSR_IA32_X2APIC_IRR4 0x824
1852/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1853#define MSR_IA32_X2APIC_IRR5 0x825
1854/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1855#define MSR_IA32_X2APIC_IRR6 0x826
1856/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1857#define MSR_IA32_X2APIC_IRR7 0x827
1858/** X2APIC MSR - Error Status Register. */
1859#define MSR_IA32_X2APIC_ESR 0x828
1860/** X2APIC MSR - LVT CMCI Register. */
1861#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1862/** X2APIC MSR - Interrupt Command Register. */
1863#define MSR_IA32_X2APIC_ICR 0x830
1864/** X2APIC MSR - LVT Timer Register. */
1865#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1866/** X2APIC MSR - LVT Thermal Sensor Register. */
1867#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1868/** X2APIC MSR - LVT Performance Counter Register. */
1869#define MSR_IA32_X2APIC_LVT_PERF 0x834
1870/** X2APIC MSR - LVT LINT0 Register. */
1871#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1872/** X2APIC MSR - LVT LINT1 Register. */
1873#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1874/** X2APIC MSR - LVT Error Register . */
1875#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1876/** X2APIC MSR - Timer Initial Count Register. */
1877#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1878/** X2APIC MSR - Timer Current Count Register. */
1879#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1880/** X2APIC MSR - Timer Divide Configuration Register. */
1881#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1882/** X2APIC MSR - Self IPI. */
1883#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1884/** X2APIC MSR range end. */
1885#define MSR_IA32_X2APIC_END 0x8FF
1886/** X2APIC MSR - LVT start range. */
1887#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1888/** X2APIC MSR - LVT end range (inclusive). */
1889#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1890
1891/** K6 EFER - Extended Feature Enable Register. */
1892#define MSR_K6_EFER UINT32_C(0xc0000080)
1893/** @todo document EFER */
1894/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1895#define MSR_K6_EFER_SCE RT_BIT_32(0)
1896/** Bit 8 - LME - Long mode enabled. (R/W) */
1897#define MSR_K6_EFER_LME RT_BIT_32(8)
1898#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1899/** Bit 10 - LMA - Long mode active. (R) */
1900#define MSR_K6_EFER_LMA RT_BIT_32(10)
1901#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1902/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1903#define MSR_K6_EFER_NXE RT_BIT_32(11)
1904#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1905/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1906#define MSR_K6_EFER_SVME RT_BIT_32(12)
1907/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1908#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1909/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1910#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1911/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1912#define MSR_K6_EFER_TCE RT_BIT_32(15)
1913/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1914#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1915
1916/** K6 STAR - SYSCALL/RET targets. */
1917#define MSR_K6_STAR UINT32_C(0xc0000081)
1918/** Shift value for getting the SYSRET CS and SS value. */
1919#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1920/** Shift value for getting the SYSCALL CS and SS value. */
1921#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1922/** Selector mask for use after shifting. */
1923#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1924/** The mask which give the SYSCALL EIP. */
1925#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1926/** K6 WHCR - Write Handling Control Register. */
1927#define MSR_K6_WHCR UINT32_C(0xc0000082)
1928/** K6 UWCCR - UC/WC Cacheability Control Register. */
1929#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1930/** K6 PSOR - Processor State Observability Register. */
1931#define MSR_K6_PSOR UINT32_C(0xc0000087)
1932/** K6 PFIR - Page Flush/Invalidate Register. */
1933#define MSR_K6_PFIR UINT32_C(0xc0000088)
1934
1935/** Performance counter MSRs. (AMD only) */
1936#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1937#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1938#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1939#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1940#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1941#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1942#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1943#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1944
1945/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1946#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1947/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1948#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1949/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1950#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1951/** K8 FS.base - The 64-bit base FS register. */
1952#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1953/** K8 GS.base - The 64-bit base GS register. */
1954#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1955/** K8 KernelGSbase - Used with SWAPGS. */
1956#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1957/** K8 TSC_AUX - Used with RDTSCP. */
1958#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1959#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1960#define MSR_K8_HWCR UINT32_C(0xc0010015)
1961#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1962#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1963#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1964#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1965#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1966#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1967
1968/** SMM MSRs. */
1969#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1970#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1971#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1972
1973/** North bridge config? See BIOS & Kernel dev guides for
1974 * details. */
1975#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1976
1977/** Hypertransport interrupt pending register.
1978 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1979#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1980
1981/** SVM Control. */
1982#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1983/** Disables HDT (Hardware Debug Tool) and certain internal debug
1984 * features. */
1985#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1986/** If set, non-intercepted INIT signals are converted to \#SX
1987 * exceptions. */
1988#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1989/** Disables A20 masking. */
1990#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1991/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1992#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1993/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1994 * clear, EFER.SVME can be written normally. */
1995#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1996
1997#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1998#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1999/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2000 * host state during world switch. */
2001#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2002
2003/** Virtualized speculation control for AMD processors.
2004 *
2005 * Unified interface among different CPU generations.
2006 * The VMM will set any architectural MSRs based on the CPU.
2007 * See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2008 * (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2009#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2010/** Speculative Store Bypass Disable. */
2011# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2012
2013/** @} */
2014
2015
2016/** @name Page Table / Directory / Directory Pointers / L4.
2017 * @{
2018 */
2019
2020/** Page table/directory entry as an unsigned integer. */
2021typedef uint32_t X86PGUINT;
2022/** Pointer to a page table/directory table entry as an unsigned integer. */
2023typedef X86PGUINT *PX86PGUINT;
2024/** Pointer to an const page table/directory table entry as an unsigned integer. */
2025typedef X86PGUINT const *PCX86PGUINT;
2026
2027/** Number of entries in a 32-bit PT/PD. */
2028#define X86_PG_ENTRIES 1024
2029
2030
2031/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2032typedef uint64_t X86PGPAEUINT;
2033/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2034typedef X86PGPAEUINT *PX86PGPAEUINT;
2035/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2036typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2037
2038/** Number of entries in a PAE PT/PD. */
2039#define X86_PG_PAE_ENTRIES 512
2040/** Number of entries in a PAE PDPT. */
2041#define X86_PG_PAE_PDPE_ENTRIES 4
2042
2043/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2044#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2045/** Number of entries in an AMD64 PDPT.
2046 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2047#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2048
2049/** The size of a default page. */
2050#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2051/** The page shift of a default page. */
2052#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2053/** The default page offset mask. */
2054#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2055/** The default page base mask for virtual addresses. */
2056#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2057/** The default page base mask for virtual addresses - 32bit version. */
2058#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2059
2060/** The size of a 4KB page. */
2061#define X86_PAGE_4K_SIZE _4K
2062/** The page shift of a 4KB page. */
2063#define X86_PAGE_4K_SHIFT 12
2064/** The 4KB page offset mask. */
2065#define X86_PAGE_4K_OFFSET_MASK 0xfff
2066/** The 4KB page base mask for virtual addresses. */
2067#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2068/** The 4KB page base mask for virtual addresses - 32bit version. */
2069#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2070
2071/** The size of a 2MB page. */
2072#define X86_PAGE_2M_SIZE _2M
2073/** The page shift of a 2MB page. */
2074#define X86_PAGE_2M_SHIFT 21
2075/** The 2MB page offset mask. */
2076#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2077/** The 2MB page base mask for virtual addresses. */
2078#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2079/** The 2MB page base mask for virtual addresses - 32bit version. */
2080#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2081
2082/** The size of a 4MB page. */
2083#define X86_PAGE_4M_SIZE _4M
2084/** The page shift of a 4MB page. */
2085#define X86_PAGE_4M_SHIFT 22
2086/** The 4MB page offset mask. */
2087#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2088/** The 4MB page base mask for virtual addresses. */
2089#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2090/** The 4MB page base mask for virtual addresses - 32bit version. */
2091#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2092
2093/** The size of a 1GB page. */
2094#define X86_PAGE_1G_SIZE _1G
2095/** The page shift of a 1GB page. */
2096#define X86_PAGE_1G_SHIFT 30
2097/** The 1GB page offset mask. */
2098#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2099/** The 1GB page base mask for virtual addresses. */
2100#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2101
2102/**
2103 * Check if the given address is canonical.
2104 */
2105#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2106
2107/**
2108 * Gets the page base mask given the page shift.
2109 */
2110#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2111
2112/**
2113 * Gets the page offset mask given the page shift.
2114 */
2115#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2116
2117
2118/** @name Page Table Entry
2119 * @{
2120 */
2121/** Bit 0 - P - Present bit. */
2122#define X86_PTE_BIT_P 0
2123/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2124#define X86_PTE_BIT_RW 1
2125/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2126#define X86_PTE_BIT_US 2
2127/** Bit 3 - PWT - Page level write thru bit. */
2128#define X86_PTE_BIT_PWT 3
2129/** Bit 4 - PCD - Page level cache disable bit. */
2130#define X86_PTE_BIT_PCD 4
2131/** Bit 5 - A - Access bit. */
2132#define X86_PTE_BIT_A 5
2133/** Bit 6 - D - Dirty bit. */
2134#define X86_PTE_BIT_D 6
2135/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2136#define X86_PTE_BIT_PAT 7
2137/** Bit 8 - G - Global flag. */
2138#define X86_PTE_BIT_G 8
2139/** Bits 63 - NX - PAE/LM - No execution flag. */
2140#define X86_PTE_PAE_BIT_NX 63
2141
2142/** Bit 0 - P - Present bit mask. */
2143#define X86_PTE_P RT_BIT_32(0)
2144/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2145#define X86_PTE_RW RT_BIT_32(1)
2146/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2147#define X86_PTE_US RT_BIT_32(2)
2148/** Bit 3 - PWT - Page level write thru bit mask. */
2149#define X86_PTE_PWT RT_BIT_32(3)
2150/** Bit 4 - PCD - Page level cache disable bit mask. */
2151#define X86_PTE_PCD RT_BIT_32(4)
2152/** Bit 5 - A - Access bit mask. */
2153#define X86_PTE_A RT_BIT_32(5)
2154/** Bit 6 - D - Dirty bit mask. */
2155#define X86_PTE_D RT_BIT_32(6)
2156/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2157#define X86_PTE_PAT RT_BIT_32(7)
2158/** Bit 8 - G - Global bit mask. */
2159#define X86_PTE_G RT_BIT_32(8)
2160
2161/** Bits 9-11 - - Available for use to system software. */
2162#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2163/** Bits 12-31 - - Physical Page number of the next level. */
2164#define X86_PTE_PG_MASK ( 0xfffff000 )
2165
2166/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2167#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2168/** Bits 63 - NX - PAE/LM - No execution flag. */
2169#define X86_PTE_PAE_NX RT_BIT_64(63)
2170/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2171#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2172/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2173#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2174/** No bits - - LM - MBZ bits when NX is active. */
2175#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2176/** Bits 63 - - LM - MBZ bits when no NX. */
2177#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2178
2179/**
2180 * Page table entry.
2181 */
2182typedef struct X86PTEBITS
2183{
2184 /** Flags whether(=1) or not the page is present. */
2185 uint32_t u1Present : 1;
2186 /** Read(=0) / Write(=1) flag. */
2187 uint32_t u1Write : 1;
2188 /** User(=1) / Supervisor (=0) flag. */
2189 uint32_t u1User : 1;
2190 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2191 uint32_t u1WriteThru : 1;
2192 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2193 uint32_t u1CacheDisable : 1;
2194 /** Accessed flag.
2195 * Indicates that the page have been read or written to. */
2196 uint32_t u1Accessed : 1;
2197 /** Dirty flag.
2198 * Indicates that the page has been written to. */
2199 uint32_t u1Dirty : 1;
2200 /** Reserved / If PAT enabled, bit 2 of the index. */
2201 uint32_t u1PAT : 1;
2202 /** Global flag. (Ignored in all but final level.) */
2203 uint32_t u1Global : 1;
2204 /** Available for use to system software. */
2205 uint32_t u3Available : 3;
2206 /** Physical Page number of the next level. */
2207 uint32_t u20PageNo : 20;
2208} X86PTEBITS;
2209#ifndef VBOX_FOR_DTRACE_LIB
2210AssertCompileSize(X86PTEBITS, 4);
2211#endif
2212/** Pointer to a page table entry. */
2213typedef X86PTEBITS *PX86PTEBITS;
2214/** Pointer to a const page table entry. */
2215typedef const X86PTEBITS *PCX86PTEBITS;
2216
2217/**
2218 * Page table entry.
2219 */
2220typedef union X86PTE
2221{
2222 /** Unsigned integer view */
2223 X86PGUINT u;
2224#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2225 /** Bit field view. */
2226 X86PTEBITS n;
2227#endif
2228 /** 32-bit view. */
2229 uint32_t au32[1];
2230 /** 16-bit view. */
2231 uint16_t au16[2];
2232 /** 8-bit view. */
2233 uint8_t au8[4];
2234} X86PTE;
2235#ifndef VBOX_FOR_DTRACE_LIB
2236AssertCompileSize(X86PTE, 4);
2237#endif
2238/** Pointer to a page table entry. */
2239typedef X86PTE *PX86PTE;
2240/** Pointer to a const page table entry. */
2241typedef const X86PTE *PCX86PTE;
2242
2243
2244/**
2245 * PAE page table entry.
2246 */
2247typedef struct X86PTEPAEBITS
2248{
2249 /** Flags whether(=1) or not the page is present. */
2250 uint32_t u1Present : 1;
2251 /** Read(=0) / Write(=1) flag. */
2252 uint32_t u1Write : 1;
2253 /** User(=1) / Supervisor(=0) flag. */
2254 uint32_t u1User : 1;
2255 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2256 uint32_t u1WriteThru : 1;
2257 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2258 uint32_t u1CacheDisable : 1;
2259 /** Accessed flag.
2260 * Indicates that the page have been read or written to. */
2261 uint32_t u1Accessed : 1;
2262 /** Dirty flag.
2263 * Indicates that the page has been written to. */
2264 uint32_t u1Dirty : 1;
2265 /** Reserved / If PAT enabled, bit 2 of the index. */
2266 uint32_t u1PAT : 1;
2267 /** Global flag. (Ignored in all but final level.) */
2268 uint32_t u1Global : 1;
2269 /** Available for use to system software. */
2270 uint32_t u3Available : 3;
2271 /** Physical Page number of the next level - Low Part. Don't use this. */
2272 uint32_t u20PageNoLow : 20;
2273 /** Physical Page number of the next level - High Part. Don't use this. */
2274 uint32_t u20PageNoHigh : 20;
2275 /** MBZ bits */
2276 uint32_t u11Reserved : 11;
2277 /** No Execute flag. */
2278 uint32_t u1NoExecute : 1;
2279} X86PTEPAEBITS;
2280#ifndef VBOX_FOR_DTRACE_LIB
2281AssertCompileSize(X86PTEPAEBITS, 8);
2282#endif
2283/** Pointer to a page table entry. */
2284typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2285/** Pointer to a page table entry. */
2286typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2287
2288/**
2289 * PAE Page table entry.
2290 */
2291typedef union X86PTEPAE
2292{
2293 /** Unsigned integer view */
2294 X86PGPAEUINT u;
2295#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2296 /** Bit field view. */
2297 X86PTEPAEBITS n;
2298#endif
2299 /** 32-bit view. */
2300 uint32_t au32[2];
2301 /** 16-bit view. */
2302 uint16_t au16[4];
2303 /** 8-bit view. */
2304 uint8_t au8[8];
2305} X86PTEPAE;
2306#ifndef VBOX_FOR_DTRACE_LIB
2307AssertCompileSize(X86PTEPAE, 8);
2308#endif
2309/** Pointer to a PAE page table entry. */
2310typedef X86PTEPAE *PX86PTEPAE;
2311/** Pointer to a const PAE page table entry. */
2312typedef const X86PTEPAE *PCX86PTEPAE;
2313/** @} */
2314
2315/**
2316 * Page table.
2317 */
2318typedef struct X86PT
2319{
2320 /** PTE Array. */
2321 X86PTE a[X86_PG_ENTRIES];
2322} X86PT;
2323#ifndef VBOX_FOR_DTRACE_LIB
2324AssertCompileSize(X86PT, 4096);
2325#endif
2326/** Pointer to a page table. */
2327typedef X86PT *PX86PT;
2328/** Pointer to a const page table. */
2329typedef const X86PT *PCX86PT;
2330
2331/** The page shift to get the PT index. */
2332#define X86_PT_SHIFT 12
2333/** The PT index mask (apply to a shifted page address). */
2334#define X86_PT_MASK 0x3ff
2335
2336
2337/**
2338 * Page directory.
2339 */
2340typedef struct X86PTPAE
2341{
2342 /** PTE Array. */
2343 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2344} X86PTPAE;
2345#ifndef VBOX_FOR_DTRACE_LIB
2346AssertCompileSize(X86PTPAE, 4096);
2347#endif
2348/** Pointer to a page table. */
2349typedef X86PTPAE *PX86PTPAE;
2350/** Pointer to a const page table. */
2351typedef const X86PTPAE *PCX86PTPAE;
2352
2353/** The page shift to get the PA PTE index. */
2354#define X86_PT_PAE_SHIFT 12
2355/** The PAE PT index mask (apply to a shifted page address). */
2356#define X86_PT_PAE_MASK 0x1ff
2357
2358
2359/** @name 4KB Page Directory Entry
2360 * @{
2361 */
2362/** Bit 0 - P - Present bit. */
2363#define X86_PDE_P RT_BIT_32(0)
2364/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2365#define X86_PDE_RW RT_BIT_32(1)
2366/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2367#define X86_PDE_US RT_BIT_32(2)
2368/** Bit 3 - PWT - Page level write thru bit. */
2369#define X86_PDE_PWT RT_BIT_32(3)
2370/** Bit 4 - PCD - Page level cache disable bit. */
2371#define X86_PDE_PCD RT_BIT_32(4)
2372/** Bit 5 - A - Access bit. */
2373#define X86_PDE_A RT_BIT_32(5)
2374/** Bit 7 - PS - Page size attribute.
2375 * Clear mean 4KB pages, set means large pages (2/4MB). */
2376#define X86_PDE_PS RT_BIT_32(7)
2377/** Bits 9-11 - - Available for use to system software. */
2378#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2379/** Bits 12-31 - - Physical Page number of the next level. */
2380#define X86_PDE_PG_MASK ( 0xfffff000 )
2381
2382/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2383#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2384/** Bits 63 - NX - PAE/LM - No execution flag. */
2385#define X86_PDE_PAE_NX RT_BIT_64(63)
2386/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2387#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2388/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2389#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2390/** Bit 7 - - LM - MBZ bits when NX is active. */
2391#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2392/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2393#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2394
2395/**
2396 * Page directory entry.
2397 */
2398typedef struct X86PDEBITS
2399{
2400 /** Flags whether(=1) or not the page is present. */
2401 uint32_t u1Present : 1;
2402 /** Read(=0) / Write(=1) flag. */
2403 uint32_t u1Write : 1;
2404 /** User(=1) / Supervisor (=0) flag. */
2405 uint32_t u1User : 1;
2406 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2407 uint32_t u1WriteThru : 1;
2408 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2409 uint32_t u1CacheDisable : 1;
2410 /** Accessed flag.
2411 * Indicates that the page has been read or written to. */
2412 uint32_t u1Accessed : 1;
2413 /** Reserved / Ignored (dirty bit). */
2414 uint32_t u1Reserved0 : 1;
2415 /** Size bit if PSE is enabled - in any event it's 0. */
2416 uint32_t u1Size : 1;
2417 /** Reserved / Ignored (global bit). */
2418 uint32_t u1Reserved1 : 1;
2419 /** Available for use to system software. */
2420 uint32_t u3Available : 3;
2421 /** Physical Page number of the next level. */
2422 uint32_t u20PageNo : 20;
2423} X86PDEBITS;
2424#ifndef VBOX_FOR_DTRACE_LIB
2425AssertCompileSize(X86PDEBITS, 4);
2426#endif
2427/** Pointer to a page directory entry. */
2428typedef X86PDEBITS *PX86PDEBITS;
2429/** Pointer to a const page directory entry. */
2430typedef const X86PDEBITS *PCX86PDEBITS;
2431
2432
2433/**
2434 * PAE page directory entry.
2435 */
2436typedef struct X86PDEPAEBITS
2437{
2438 /** Flags whether(=1) or not the page is present. */
2439 uint32_t u1Present : 1;
2440 /** Read(=0) / Write(=1) flag. */
2441 uint32_t u1Write : 1;
2442 /** User(=1) / Supervisor (=0) flag. */
2443 uint32_t u1User : 1;
2444 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2445 uint32_t u1WriteThru : 1;
2446 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2447 uint32_t u1CacheDisable : 1;
2448 /** Accessed flag.
2449 * Indicates that the page has been read or written to. */
2450 uint32_t u1Accessed : 1;
2451 /** Reserved / Ignored (dirty bit). */
2452 uint32_t u1Reserved0 : 1;
2453 /** Size bit if PSE is enabled - in any event it's 0. */
2454 uint32_t u1Size : 1;
2455 /** Reserved / Ignored (global bit). / */
2456 uint32_t u1Reserved1 : 1;
2457 /** Available for use to system software. */
2458 uint32_t u3Available : 3;
2459 /** Physical Page number of the next level - Low Part. Don't use! */
2460 uint32_t u20PageNoLow : 20;
2461 /** Physical Page number of the next level - High Part. Don't use! */
2462 uint32_t u20PageNoHigh : 20;
2463 /** MBZ bits */
2464 uint32_t u11Reserved : 11;
2465 /** No Execute flag. */
2466 uint32_t u1NoExecute : 1;
2467} X86PDEPAEBITS;
2468#ifndef VBOX_FOR_DTRACE_LIB
2469AssertCompileSize(X86PDEPAEBITS, 8);
2470#endif
2471/** Pointer to a page directory entry. */
2472typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2473/** Pointer to a const page directory entry. */
2474typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2475
2476/** @} */
2477
2478
2479/** @name 2/4MB Page Directory Entry
2480 * @{
2481 */
2482/** Bit 0 - P - Present bit. */
2483#define X86_PDE4M_P RT_BIT_32(0)
2484/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2485#define X86_PDE4M_RW RT_BIT_32(1)
2486/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2487#define X86_PDE4M_US RT_BIT_32(2)
2488/** Bit 3 - PWT - Page level write thru bit. */
2489#define X86_PDE4M_PWT RT_BIT_32(3)
2490/** Bit 4 - PCD - Page level cache disable bit. */
2491#define X86_PDE4M_PCD RT_BIT_32(4)
2492/** Bit 5 - A - Access bit. */
2493#define X86_PDE4M_A RT_BIT_32(5)
2494/** Bit 6 - D - Dirty bit. */
2495#define X86_PDE4M_D RT_BIT_32(6)
2496/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2497#define X86_PDE4M_PS RT_BIT_32(7)
2498/** Bit 8 - G - Global flag. */
2499#define X86_PDE4M_G RT_BIT_32(8)
2500/** Bits 9-11 - AVL - Available for use to system software. */
2501#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2502/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2503#define X86_PDE4M_PAT RT_BIT_32(12)
2504/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2505#define X86_PDE4M_PAT_SHIFT (12 - 7)
2506/** Bits 22-31 - - Physical Page number. */
2507#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2508/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2509#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2510/** The number of bits to the high part of the page number. */
2511#define X86_PDE4M_PG_HIGH_SHIFT 19
2512/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2513#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2514
2515/** Bits 21-51 - - PAE/LM - Physical Page number.
2516 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2517#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2518/** Bits 63 - NX - PAE/LM - No execution flag. */
2519#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2520/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2521#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2522/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2523#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2524/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2525#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2526/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2527#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2528
2529/**
2530 * 4MB page directory entry.
2531 */
2532typedef struct X86PDE4MBITS
2533{
2534 /** Flags whether(=1) or not the page is present. */
2535 uint32_t u1Present : 1;
2536 /** Read(=0) / Write(=1) flag. */
2537 uint32_t u1Write : 1;
2538 /** User(=1) / Supervisor (=0) flag. */
2539 uint32_t u1User : 1;
2540 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2541 uint32_t u1WriteThru : 1;
2542 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2543 uint32_t u1CacheDisable : 1;
2544 /** Accessed flag.
2545 * Indicates that the page have been read or written to. */
2546 uint32_t u1Accessed : 1;
2547 /** Dirty flag.
2548 * Indicates that the page has been written to. */
2549 uint32_t u1Dirty : 1;
2550 /** Page size flag - always 1 for 4MB entries. */
2551 uint32_t u1Size : 1;
2552 /** Global flag. */
2553 uint32_t u1Global : 1;
2554 /** Available for use to system software. */
2555 uint32_t u3Available : 3;
2556 /** Reserved / If PAT enabled, bit 2 of the index. */
2557 uint32_t u1PAT : 1;
2558 /** Bits 32-39 of the page number on AMD64.
2559 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2560 uint32_t u8PageNoHigh : 8;
2561 /** Reserved. */
2562 uint32_t u1Reserved : 1;
2563 /** Physical Page number of the page. */
2564 uint32_t u10PageNo : 10;
2565} X86PDE4MBITS;
2566#ifndef VBOX_FOR_DTRACE_LIB
2567AssertCompileSize(X86PDE4MBITS, 4);
2568#endif
2569/** Pointer to a page table entry. */
2570typedef X86PDE4MBITS *PX86PDE4MBITS;
2571/** Pointer to a const page table entry. */
2572typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2573
2574
2575/**
2576 * 2MB PAE page directory entry.
2577 */
2578typedef struct X86PDE2MPAEBITS
2579{
2580 /** Flags whether(=1) or not the page is present. */
2581 uint32_t u1Present : 1;
2582 /** Read(=0) / Write(=1) flag. */
2583 uint32_t u1Write : 1;
2584 /** User(=1) / Supervisor(=0) flag. */
2585 uint32_t u1User : 1;
2586 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2587 uint32_t u1WriteThru : 1;
2588 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2589 uint32_t u1CacheDisable : 1;
2590 /** Accessed flag.
2591 * Indicates that the page have been read or written to. */
2592 uint32_t u1Accessed : 1;
2593 /** Dirty flag.
2594 * Indicates that the page has been written to. */
2595 uint32_t u1Dirty : 1;
2596 /** Page size flag - always 1 for 2MB entries. */
2597 uint32_t u1Size : 1;
2598 /** Global flag. */
2599 uint32_t u1Global : 1;
2600 /** Available for use to system software. */
2601 uint32_t u3Available : 3;
2602 /** Reserved / If PAT enabled, bit 2 of the index. */
2603 uint32_t u1PAT : 1;
2604 /** Reserved. */
2605 uint32_t u9Reserved : 9;
2606 /** Physical Page number of the next level - Low part. Don't use! */
2607 uint32_t u10PageNoLow : 10;
2608 /** Physical Page number of the next level - High part. Don't use! */
2609 uint32_t u20PageNoHigh : 20;
2610 /** MBZ bits */
2611 uint32_t u11Reserved : 11;
2612 /** No Execute flag. */
2613 uint32_t u1NoExecute : 1;
2614} X86PDE2MPAEBITS;
2615#ifndef VBOX_FOR_DTRACE_LIB
2616AssertCompileSize(X86PDE2MPAEBITS, 8);
2617#endif
2618/** Pointer to a 2MB PAE page table entry. */
2619typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2620/** Pointer to a 2MB PAE page table entry. */
2621typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2622
2623/** @} */
2624
2625/**
2626 * Page directory entry.
2627 */
2628typedef union X86PDE
2629{
2630 /** Unsigned integer view. */
2631 X86PGUINT u;
2632#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2633 /** Normal view. */
2634 X86PDEBITS n;
2635 /** 4MB view (big). */
2636 X86PDE4MBITS b;
2637#endif
2638 /** 8 bit unsigned integer view. */
2639 uint8_t au8[4];
2640 /** 16 bit unsigned integer view. */
2641 uint16_t au16[2];
2642 /** 32 bit unsigned integer view. */
2643 uint32_t au32[1];
2644} X86PDE;
2645#ifndef VBOX_FOR_DTRACE_LIB
2646AssertCompileSize(X86PDE, 4);
2647#endif
2648/** Pointer to a page directory entry. */
2649typedef X86PDE *PX86PDE;
2650/** Pointer to a const page directory entry. */
2651typedef const X86PDE *PCX86PDE;
2652
2653/**
2654 * PAE page directory entry.
2655 */
2656typedef union X86PDEPAE
2657{
2658 /** Unsigned integer view. */
2659 X86PGPAEUINT u;
2660#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2661 /** Normal view. */
2662 X86PDEPAEBITS n;
2663 /** 2MB page view (big). */
2664 X86PDE2MPAEBITS b;
2665#endif
2666 /** 8 bit unsigned integer view. */
2667 uint8_t au8[8];
2668 /** 16 bit unsigned integer view. */
2669 uint16_t au16[4];
2670 /** 32 bit unsigned integer view. */
2671 uint32_t au32[2];
2672} X86PDEPAE;
2673#ifndef VBOX_FOR_DTRACE_LIB
2674AssertCompileSize(X86PDEPAE, 8);
2675#endif
2676/** Pointer to a page directory entry. */
2677typedef X86PDEPAE *PX86PDEPAE;
2678/** Pointer to a const page directory entry. */
2679typedef const X86PDEPAE *PCX86PDEPAE;
2680
2681/**
2682 * Page directory.
2683 */
2684typedef struct X86PD
2685{
2686 /** PDE Array. */
2687 X86PDE a[X86_PG_ENTRIES];
2688} X86PD;
2689#ifndef VBOX_FOR_DTRACE_LIB
2690AssertCompileSize(X86PD, 4096);
2691#endif
2692/** Pointer to a page directory. */
2693typedef X86PD *PX86PD;
2694/** Pointer to a const page directory. */
2695typedef const X86PD *PCX86PD;
2696
2697/** The page shift to get the PD index. */
2698#define X86_PD_SHIFT 22
2699/** The PD index mask (apply to a shifted page address). */
2700#define X86_PD_MASK 0x3ff
2701
2702
2703/**
2704 * PAE page directory.
2705 */
2706typedef struct X86PDPAE
2707{
2708 /** PDE Array. */
2709 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2710} X86PDPAE;
2711#ifndef VBOX_FOR_DTRACE_LIB
2712AssertCompileSize(X86PDPAE, 4096);
2713#endif
2714/** Pointer to a PAE page directory. */
2715typedef X86PDPAE *PX86PDPAE;
2716/** Pointer to a const PAE page directory. */
2717typedef const X86PDPAE *PCX86PDPAE;
2718
2719/** The page shift to get the PAE PD index. */
2720#define X86_PD_PAE_SHIFT 21
2721/** The PAE PD index mask (apply to a shifted page address). */
2722#define X86_PD_PAE_MASK 0x1ff
2723
2724
2725/** @name Page Directory Pointer Table Entry (PAE)
2726 * @{
2727 */
2728/** Bit 0 - P - Present bit. */
2729#define X86_PDPE_P RT_BIT_32(0)
2730/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2731#define X86_PDPE_RW RT_BIT_32(1)
2732/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2733#define X86_PDPE_US RT_BIT_32(2)
2734/** Bit 3 - PWT - Page level write thru bit. */
2735#define X86_PDPE_PWT RT_BIT_32(3)
2736/** Bit 4 - PCD - Page level cache disable bit. */
2737#define X86_PDPE_PCD RT_BIT_32(4)
2738/** Bit 5 - A - Access bit. Long Mode only. */
2739#define X86_PDPE_A RT_BIT_32(5)
2740/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2741#define X86_PDPE_LM_PS RT_BIT_32(7)
2742/** Bits 9-11 - - Available for use to system software. */
2743#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2744/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2745#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2746/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2747#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2748/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2749#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2750/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2751#define X86_PDPE_LM_NX RT_BIT_64(63)
2752/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2753#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2754/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2755#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2756/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2757#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2758/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2759#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2760
2761
2762/**
2763 * Page directory pointer table entry.
2764 */
2765typedef struct X86PDPEBITS
2766{
2767 /** Flags whether(=1) or not the page is present. */
2768 uint32_t u1Present : 1;
2769 /** Chunk of reserved bits. */
2770 uint32_t u2Reserved : 2;
2771 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2772 uint32_t u1WriteThru : 1;
2773 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2774 uint32_t u1CacheDisable : 1;
2775 /** Chunk of reserved bits. */
2776 uint32_t u4Reserved : 4;
2777 /** Available for use to system software. */
2778 uint32_t u3Available : 3;
2779 /** Physical Page number of the next level - Low Part. Don't use! */
2780 uint32_t u20PageNoLow : 20;
2781 /** Physical Page number of the next level - High Part. Don't use! */
2782 uint32_t u20PageNoHigh : 20;
2783 /** MBZ bits */
2784 uint32_t u12Reserved : 12;
2785} X86PDPEBITS;
2786#ifndef VBOX_FOR_DTRACE_LIB
2787AssertCompileSize(X86PDPEBITS, 8);
2788#endif
2789/** Pointer to a page directory pointer table entry. */
2790typedef X86PDPEBITS *PX86PTPEBITS;
2791/** Pointer to a const page directory pointer table entry. */
2792typedef const X86PDPEBITS *PCX86PTPEBITS;
2793
2794/**
2795 * Page directory pointer table entry. AMD64 version
2796 */
2797typedef struct X86PDPEAMD64BITS
2798{
2799 /** Flags whether(=1) or not the page is present. */
2800 uint32_t u1Present : 1;
2801 /** Read(=0) / Write(=1) flag. */
2802 uint32_t u1Write : 1;
2803 /** User(=1) / Supervisor (=0) flag. */
2804 uint32_t u1User : 1;
2805 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2806 uint32_t u1WriteThru : 1;
2807 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2808 uint32_t u1CacheDisable : 1;
2809 /** Accessed flag.
2810 * Indicates that the page have been read or written to. */
2811 uint32_t u1Accessed : 1;
2812 /** Chunk of reserved bits. */
2813 uint32_t u3Reserved : 3;
2814 /** Available for use to system software. */
2815 uint32_t u3Available : 3;
2816 /** Physical Page number of the next level - Low Part. Don't use! */
2817 uint32_t u20PageNoLow : 20;
2818 /** Physical Page number of the next level - High Part. Don't use! */
2819 uint32_t u20PageNoHigh : 20;
2820 /** MBZ bits */
2821 uint32_t u11Reserved : 11;
2822 /** No Execute flag. */
2823 uint32_t u1NoExecute : 1;
2824} X86PDPEAMD64BITS;
2825#ifndef VBOX_FOR_DTRACE_LIB
2826AssertCompileSize(X86PDPEAMD64BITS, 8);
2827#endif
2828/** Pointer to a page directory pointer table entry. */
2829typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2830/** Pointer to a const page directory pointer table entry. */
2831typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2832
2833/**
2834 * Page directory pointer table entry for 1GB page. (AMD64 only)
2835 */
2836typedef struct X86PDPE1GB
2837{
2838 /** 0: Flags whether(=1) or not the page is present. */
2839 uint32_t u1Present : 1;
2840 /** 1: Read(=0) / Write(=1) flag. */
2841 uint32_t u1Write : 1;
2842 /** 2: User(=1) / Supervisor (=0) flag. */
2843 uint32_t u1User : 1;
2844 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2845 uint32_t u1WriteThru : 1;
2846 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2847 uint32_t u1CacheDisable : 1;
2848 /** 5: Accessed flag.
2849 * Indicates that the page have been read or written to. */
2850 uint32_t u1Accessed : 1;
2851 /** 6: Dirty flag for 1GB pages. */
2852 uint32_t u1Dirty : 1;
2853 /** 7: Indicates 1GB page if set. */
2854 uint32_t u1Size : 1;
2855 /** 8: Global 1GB page. */
2856 uint32_t u1Global: 1;
2857 /** 9-11: Available for use to system software. */
2858 uint32_t u3Available : 3;
2859 /** 12: PAT bit for 1GB page. */
2860 uint32_t u1PAT : 1;
2861 /** 13-29: MBZ bits. */
2862 uint32_t u17Reserved : 17;
2863 /** 30-31: Physical page number - Low Part. Don't use! */
2864 uint32_t u2PageNoLow : 2;
2865 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2866 uint32_t u20PageNoHigh : 20;
2867 /** 52-62: MBZ bits */
2868 uint32_t u11Reserved : 11;
2869 /** 63: No Execute flag. */
2870 uint32_t u1NoExecute : 1;
2871} X86PDPE1GB;
2872#ifndef VBOX_FOR_DTRACE_LIB
2873AssertCompileSize(X86PDPE1GB, 8);
2874#endif
2875/** Pointer to a page directory pointer table entry for a 1GB page. */
2876typedef X86PDPE1GB *PX86PDPE1GB;
2877/** Pointer to a const page directory pointer table entry for a 1GB page. */
2878typedef const X86PDPE1GB *PCX86PDPE1GB;
2879
2880/**
2881 * Page directory pointer table entry.
2882 */
2883typedef union X86PDPE
2884{
2885 /** Unsigned integer view. */
2886 X86PGPAEUINT u;
2887#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2888 /** Normal view. */
2889 X86PDPEBITS n;
2890 /** AMD64 view. */
2891 X86PDPEAMD64BITS lm;
2892 /** AMD64 big view. */
2893 X86PDPE1GB b;
2894#endif
2895 /** 8 bit unsigned integer view. */
2896 uint8_t au8[8];
2897 /** 16 bit unsigned integer view. */
2898 uint16_t au16[4];
2899 /** 32 bit unsigned integer view. */
2900 uint32_t au32[2];
2901} X86PDPE;
2902#ifndef VBOX_FOR_DTRACE_LIB
2903AssertCompileSize(X86PDPE, 8);
2904#endif
2905/** Pointer to a page directory pointer table entry. */
2906typedef X86PDPE *PX86PDPE;
2907/** Pointer to a const page directory pointer table entry. */
2908typedef const X86PDPE *PCX86PDPE;
2909
2910
2911/**
2912 * Page directory pointer table.
2913 */
2914typedef struct X86PDPT
2915{
2916 /** PDE Array. */
2917 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2918} X86PDPT;
2919#ifndef VBOX_FOR_DTRACE_LIB
2920AssertCompileSize(X86PDPT, 4096);
2921#endif
2922/** Pointer to a page directory pointer table. */
2923typedef X86PDPT *PX86PDPT;
2924/** Pointer to a const page directory pointer table. */
2925typedef const X86PDPT *PCX86PDPT;
2926
2927/** The page shift to get the PDPT index. */
2928#define X86_PDPT_SHIFT 30
2929/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2930#define X86_PDPT_MASK_PAE 0x3
2931/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2932#define X86_PDPT_MASK_AMD64 0x1ff
2933
2934/** @} */
2935
2936
2937/** @name Page Map Level-4 Entry (Long Mode PAE)
2938 * @{
2939 */
2940/** Bit 0 - P - Present bit. */
2941#define X86_PML4E_P RT_BIT_32(0)
2942/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2943#define X86_PML4E_RW RT_BIT_32(1)
2944/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2945#define X86_PML4E_US RT_BIT_32(2)
2946/** Bit 3 - PWT - Page level write thru bit. */
2947#define X86_PML4E_PWT RT_BIT_32(3)
2948/** Bit 4 - PCD - Page level cache disable bit. */
2949#define X86_PML4E_PCD RT_BIT_32(4)
2950/** Bit 5 - A - Access bit. */
2951#define X86_PML4E_A RT_BIT_32(5)
2952/** Bits 9-11 - - Available for use to system software. */
2953#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2954/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2955#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2956/** Bits 8, 7 - - MBZ bits when NX is active. */
2957#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2958/** Bits 63, 7 - - MBZ bits when no NX. */
2959#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2960/** Bits 63 - NX - PAE - No execution flag. */
2961#define X86_PML4E_NX RT_BIT_64(63)
2962
2963/**
2964 * Page Map Level-4 Entry
2965 */
2966typedef struct X86PML4EBITS
2967{
2968 /** Flags whether(=1) or not the page is present. */
2969 uint32_t u1Present : 1;
2970 /** Read(=0) / Write(=1) flag. */
2971 uint32_t u1Write : 1;
2972 /** User(=1) / Supervisor (=0) flag. */
2973 uint32_t u1User : 1;
2974 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2975 uint32_t u1WriteThru : 1;
2976 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2977 uint32_t u1CacheDisable : 1;
2978 /** Accessed flag.
2979 * Indicates that the page have been read or written to. */
2980 uint32_t u1Accessed : 1;
2981 /** Chunk of reserved bits. */
2982 uint32_t u3Reserved : 3;
2983 /** Available for use to system software. */
2984 uint32_t u3Available : 3;
2985 /** Physical Page number of the next level - Low Part. Don't use! */
2986 uint32_t u20PageNoLow : 20;
2987 /** Physical Page number of the next level - High Part. Don't use! */
2988 uint32_t u20PageNoHigh : 20;
2989 /** MBZ bits */
2990 uint32_t u11Reserved : 11;
2991 /** No Execute flag. */
2992 uint32_t u1NoExecute : 1;
2993} X86PML4EBITS;
2994#ifndef VBOX_FOR_DTRACE_LIB
2995AssertCompileSize(X86PML4EBITS, 8);
2996#endif
2997/** Pointer to a page map level-4 entry. */
2998typedef X86PML4EBITS *PX86PML4EBITS;
2999/** Pointer to a const page map level-4 entry. */
3000typedef const X86PML4EBITS *PCX86PML4EBITS;
3001
3002/**
3003 * Page Map Level-4 Entry.
3004 */
3005typedef union X86PML4E
3006{
3007 /** Unsigned integer view. */
3008 X86PGPAEUINT u;
3009#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3010 /** Normal view. */
3011 X86PML4EBITS n;
3012#endif
3013 /** 8 bit unsigned integer view. */
3014 uint8_t au8[8];
3015 /** 16 bit unsigned integer view. */
3016 uint16_t au16[4];
3017 /** 32 bit unsigned integer view. */
3018 uint32_t au32[2];
3019} X86PML4E;
3020#ifndef VBOX_FOR_DTRACE_LIB
3021AssertCompileSize(X86PML4E, 8);
3022#endif
3023/** Pointer to a page map level-4 entry. */
3024typedef X86PML4E *PX86PML4E;
3025/** Pointer to a const page map level-4 entry. */
3026typedef const X86PML4E *PCX86PML4E;
3027
3028
3029/**
3030 * Page Map Level-4.
3031 */
3032typedef struct X86PML4
3033{
3034 /** PDE Array. */
3035 X86PML4E a[X86_PG_PAE_ENTRIES];
3036} X86PML4;
3037#ifndef VBOX_FOR_DTRACE_LIB
3038AssertCompileSize(X86PML4, 4096);
3039#endif
3040/** Pointer to a page map level-4. */
3041typedef X86PML4 *PX86PML4;
3042/** Pointer to a const page map level-4. */
3043typedef const X86PML4 *PCX86PML4;
3044
3045/** The page shift to get the PML4 index. */
3046#define X86_PML4_SHIFT 39
3047/** The PML4 index mask (apply to a shifted page address). */
3048#define X86_PML4_MASK 0x1ff
3049
3050/** @} */
3051
3052/** @} */
3053
3054/**
3055 * Intel PCID invalidation types.
3056 */
3057/** Individual address invalidation. */
3058#define X86_INVPCID_TYPE_INDV_ADDR 0
3059/** Single-context invalidation. */
3060#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3061/** All-context including globals invalidation. */
3062#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3063/** All-context excluding globals invalidation. */
3064#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3065/** The maximum valid invalidation type value. */
3066#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3067
3068
3069/** @name Special FPU integer values.
3070 * @{ */
3071#define X86_FPU_INT64_INDEFINITE INT64_MIN
3072#define X86_FPU_INT32_INDEFINITE INT32_MIN
3073#define X86_FPU_INT16_INDEFINITE INT16_MIN
3074/** @} */
3075
3076/**
3077 * 32-bit protected mode FSTENV image.
3078 */
3079typedef struct X86FSTENV32P
3080{
3081 uint16_t FCW; /**< 0x00 */
3082 uint16_t padding1; /**< 0x02 */
3083 uint16_t FSW; /**< 0x04 */
3084 uint16_t padding2; /**< 0x06 */
3085 uint16_t FTW; /**< 0x08 */
3086 uint16_t padding3; /**< 0x0a */
3087 uint32_t FPUIP; /**< 0x0c */
3088 uint16_t FPUCS; /**< 0x10 */
3089 uint16_t FOP; /**< 0x12 */
3090 uint32_t FPUDP; /**< 0x14 */
3091 uint16_t FPUDS; /**< 0x18 */
3092 uint16_t padding4; /**< 0x1a */
3093} X86FSTENV32P;
3094#ifndef VBOX_FOR_DTRACE_LIB
3095AssertCompileSize(X86FSTENV32P, 0x1c);
3096#endif
3097/** Pointer to a 32-bit protected mode FSTENV image. */
3098typedef X86FSTENV32P *PX86FSTENV32P;
3099/** Pointer to a const 32-bit protected mode FSTENV image. */
3100typedef X86FSTENV32P const *PCX86FSTENV32P;
3101
3102
3103/**
3104 * 80-bit MMX/FPU register type.
3105 */
3106typedef struct X86FPUMMX
3107{
3108 uint8_t reg[10];
3109} X86FPUMMX;
3110#ifndef VBOX_FOR_DTRACE_LIB
3111AssertCompileSize(X86FPUMMX, 10);
3112#endif
3113/** Pointer to a 80-bit MMX/FPU register type. */
3114typedef X86FPUMMX *PX86FPUMMX;
3115/** Pointer to a const 80-bit MMX/FPU register type. */
3116typedef const X86FPUMMX *PCX86FPUMMX;
3117
3118/** FPU (x87) register. */
3119typedef union X86FPUREG
3120{
3121 /** MMX view. */
3122 uint64_t mmx;
3123 /** FPU view - todo. */
3124 X86FPUMMX fpu;
3125 /** Extended precision floating point view. */
3126 RTFLOAT80U r80;
3127 /** Extended precision floating point view v2 */
3128 RTFLOAT80U2 r80Ex;
3129 /** 8-bit view. */
3130 uint8_t au8[16];
3131 /** 16-bit view. */
3132 uint16_t au16[8];
3133 /** 32-bit view. */
3134 uint32_t au32[4];
3135 /** 64-bit view. */
3136 uint64_t au64[2];
3137 /** 128-bit view. (yeah, very helpful) */
3138 uint128_t au128[1];
3139} X86FPUREG;
3140#ifndef VBOX_FOR_DTRACE_LIB
3141AssertCompileSize(X86FPUREG, 16);
3142#endif
3143/** Pointer to a FPU register. */
3144typedef X86FPUREG *PX86FPUREG;
3145/** Pointer to a const FPU register. */
3146typedef X86FPUREG const *PCX86FPUREG;
3147
3148/** FPU (x87) register - v2 with correct size. */
3149#pragma pack(1)
3150typedef union X86FPUREG2
3151{
3152 /** MMX view. */
3153 uint64_t mmx;
3154 /** FPU view - todo. */
3155 X86FPUMMX fpu;
3156 /** Extended precision floating point view. */
3157 RTFLOAT80U r80;
3158 /** 8-bit view. */
3159 uint8_t au8[10];
3160 /** 16-bit view. */
3161 uint16_t au16[5];
3162 /** 32-bit view. */
3163 uint32_t au32[2];
3164 /** 64-bit view. */
3165 uint64_t au64[1];
3166} X86FPUREG2;
3167#pragma pack()
3168#ifndef VBOX_FOR_DTRACE_LIB
3169AssertCompileSize(X86FPUREG2, 10);
3170#endif
3171/** Pointer to a FPU register - v2. */
3172typedef X86FPUREG2 *PX86FPUREG2;
3173/** Pointer to a const FPU register - v2. */
3174typedef X86FPUREG2 const *PCX86FPUREG2;
3175
3176/**
3177 * XMM register union.
3178 */
3179typedef union X86XMMREG
3180{
3181 /** XMM Register view. */
3182 uint128_t xmm;
3183 /** 8-bit view. */
3184 uint8_t au8[16];
3185 /** 16-bit view. */
3186 uint16_t au16[8];
3187 /** 32-bit view. */
3188 uint32_t au32[4];
3189 /** 64-bit view. */
3190 uint64_t au64[2];
3191 /** Signed 8-bit view. */
3192 int8_t ai8[16];
3193 /** Signed 16-bit view. */
3194 int16_t ai16[8];
3195 /** Signed 32-bit view. */
3196 int32_t ai32[4];
3197 /** Signed 64-bit view. */
3198 int64_t ai64[2];
3199 /** 128-bit view. (yeah, very helpful) */
3200 uint128_t au128[1];
3201 /** Single precision floating point view. */
3202 RTFLOAT32U ar32[4];
3203 /** Double precision floating point view. */
3204 RTFLOAT64U ar64[2];
3205#ifndef VBOX_FOR_DTRACE_LIB
3206 /** Confusing nested 128-bit union view (this is what xmm should've been). */
3207 RTUINT128U uXmm;
3208#endif
3209} X86XMMREG;
3210#ifndef VBOX_FOR_DTRACE_LIB
3211AssertCompileSize(X86XMMREG, 16);
3212#endif
3213/** Pointer to an XMM register state. */
3214typedef X86XMMREG *PX86XMMREG;
3215/** Pointer to a const XMM register state. */
3216typedef X86XMMREG const *PCX86XMMREG;
3217
3218/**
3219 * YMM register union.
3220 */
3221typedef union X86YMMREG
3222{
3223 /** YMM register view. */
3224 RTUINT256U ymm;
3225 /** 8-bit view. */
3226 uint8_t au8[32];
3227 /** 16-bit view. */
3228 uint16_t au16[16];
3229 /** 32-bit view. */
3230 uint32_t au32[8];
3231 /** 64-bit view. */
3232 uint64_t au64[4];
3233 /** 128-bit view. (yeah, very helpful) */
3234 uint128_t au128[2];
3235 /** Single precision floating point view. */
3236 RTFLOAT32U ar32[8];
3237 /** Double precision floating point view. */
3238 RTFLOAT64U ar64[4];
3239 /** XMM sub register view. */
3240 X86XMMREG aXmm[2];
3241} X86YMMREG;
3242#ifndef VBOX_FOR_DTRACE_LIB
3243AssertCompileSize(X86YMMREG, 32);
3244#endif
3245/** Pointer to an YMM register state. */
3246typedef X86YMMREG *PX86YMMREG;
3247/** Pointer to a const YMM register state. */
3248typedef X86YMMREG const *PCX86YMMREG;
3249
3250/**
3251 * ZMM register union.
3252 */
3253typedef union X86ZMMREG
3254{
3255 /** 8-bit view. */
3256 uint8_t au8[64];
3257 /** 16-bit view. */
3258 uint16_t au16[32];
3259 /** 32-bit view. */
3260 uint32_t au32[16];
3261 /** 64-bit view. */
3262 uint64_t au64[8];
3263 /** 128-bit view. (yeah, very helpful) */
3264 uint128_t au128[4];
3265 /** Single precision floating point view. */
3266 RTFLOAT32U ar32[16];
3267 /** Double precision floating point view. */
3268 RTFLOAT64U ar64[8];
3269 /** XMM sub register view. */
3270 X86XMMREG aXmm[4];
3271 /** YMM sub register view. */
3272 X86YMMREG aYmm[2];
3273} X86ZMMREG;
3274#ifndef VBOX_FOR_DTRACE_LIB
3275AssertCompileSize(X86ZMMREG, 64);
3276#endif
3277/** Pointer to an ZMM register state. */
3278typedef X86ZMMREG *PX86ZMMREG;
3279/** Pointer to a const ZMM register state. */
3280typedef X86ZMMREG const *PCX86ZMMREG;
3281
3282
3283/**
3284 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3285 */
3286#pragma pack(1)
3287typedef struct X86FPUSTATE
3288{
3289 /** 0x00 - Control word. */
3290 uint16_t FCW;
3291 /** 0x02 - Alignment word */
3292 uint16_t Dummy1;
3293 /** 0x04 - Status word. */
3294 uint16_t FSW;
3295 /** 0x06 - Alignment word */
3296 uint16_t Dummy2;
3297 /** 0x08 - Tag word */
3298 uint16_t FTW;
3299 /** 0x0a - Alignment word */
3300 uint16_t Dummy3;
3301
3302 /** 0x0c - Instruction pointer. */
3303 uint32_t FPUIP;
3304 /** 0x10 - Code selector. */
3305 uint16_t CS;
3306 /** 0x12 - Opcode. */
3307 uint16_t FOP;
3308 /** 0x14 - Data pointer. */
3309 uint32_t FPUOO;
3310 /** 0x18 - FOS. */
3311 uint16_t FPUOS;
3312 /** 0x0a - Alignment word */
3313 uint16_t Dummy4;
3314 /** 0x1c - FPU register. */
3315 X86FPUREG2 regs[8];
3316} X86FPUSTATE;
3317#pragma pack()
3318AssertCompileSize(X86FPUSTATE, 108);
3319/** Pointer to a FPU state. */
3320typedef X86FPUSTATE *PX86FPUSTATE;
3321/** Pointer to a const FPU state. */
3322typedef const X86FPUSTATE *PCX86FPUSTATE;
3323
3324/**
3325 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3326 */
3327#pragma pack(1)
3328typedef struct X86FXSTATE
3329{
3330 /** 0x00 - Control word. */
3331 uint16_t FCW;
3332 /** 0x02 - Status word. */
3333 uint16_t FSW;
3334 /** 0x04 - Tag word. (The upper byte is always zero.) */
3335 uint16_t FTW;
3336 /** 0x06 - Opcode. */
3337 uint16_t FOP;
3338 /** 0x08 - Instruction pointer. */
3339 uint32_t FPUIP;
3340 /** 0x0c - Code selector. */
3341 uint16_t CS;
3342 uint16_t Rsrvd1;
3343 /** 0x10 - Data pointer. */
3344 uint32_t FPUDP;
3345 /** 0x14 - Data segment */
3346 uint16_t DS;
3347 /** 0x16 */
3348 uint16_t Rsrvd2;
3349 /** 0x18 */
3350 uint32_t MXCSR;
3351 /** 0x1c */
3352 uint32_t MXCSR_MASK;
3353 /** 0x20 - FPU registers. */
3354 X86FPUREG aRegs[8];
3355 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3356 X86XMMREG aXMM[16];
3357 /* - offset 416 - */
3358 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3359 /* - offset 464 - Software usable reserved bits. */
3360 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3361} X86FXSTATE;
3362#pragma pack()
3363/** Pointer to a FPU Extended state. */
3364typedef X86FXSTATE *PX86FXSTATE;
3365/** Pointer to a const FPU Extended state. */
3366typedef const X86FXSTATE *PCX86FXSTATE;
3367
3368/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3369 * magic. Don't forget to update x86.mac if you change this! */
3370#define X86_OFF_FXSTATE_RSVD 0x1d0
3371/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3372 * forget to update x86.mac if you change this!
3373 * @todo r=bird: This has nothing what-so-ever to do here.... */
3374#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3375#ifndef VBOX_FOR_DTRACE_LIB
3376AssertCompileSize(X86FXSTATE, 512);
3377AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3378#endif
3379
3380/** @name FPU status word flags.
3381 * @{ */
3382/** Exception Flag: Invalid operation. */
3383#define X86_FSW_IE RT_BIT_32(0)
3384#define X86_FSW_IE_BIT 0
3385/** Exception Flag: Denormalized operand. */
3386#define X86_FSW_DE RT_BIT_32(1)
3387#define X86_FSW_DE_BIT 1
3388/** Exception Flag: Zero divide. */
3389#define X86_FSW_ZE RT_BIT_32(2)
3390#define X86_FSW_ZE_BIT 2
3391/** Exception Flag: Overflow. */
3392#define X86_FSW_OE RT_BIT_32(3)
3393#define X86_FSW_OE_BIT 3
3394/** Exception Flag: Underflow. */
3395#define X86_FSW_UE RT_BIT_32(4)
3396#define X86_FSW_UE_BIT 4
3397/** Exception Flag: Precision. */
3398#define X86_FSW_PE RT_BIT_32(5)
3399#define X86_FSW_PE_BIT 5
3400/** Stack fault. */
3401#define X86_FSW_SF RT_BIT_32(6)
3402#define X86_FSW_SF_BIT 6
3403/** Error summary status. */
3404#define X86_FSW_ES RT_BIT_32(7)
3405#define X86_FSW_ES_BIT 7
3406/** Mask of exceptions flags, excluding the summary bit. */
3407#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3408/** Mask of exceptions flags, including the summary bit. */
3409#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3410/** Condition code 0. */
3411#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3412#define X86_FSW_C0_BIT 8
3413/** Condition code 1. */
3414#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3415#define X86_FSW_C1_BIT 9
3416/** Condition code 2. */
3417#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3418#define X86_FSW_C2_BIT 10
3419/** Top of the stack mask. */
3420#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3421/** TOP shift value. */
3422#define X86_FSW_TOP_SHIFT 11
3423/** Mask for getting TOP value after shifting it right. */
3424#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3425/** Get the TOP value. */
3426#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3427/** Get the TOP value offsetted by a_iSt (0-7). */
3428#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3429/** Condition code 3. */
3430#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3431#define X86_FSW_C3_BIT 14
3432/** Mask of exceptions flags, including the summary bit. */
3433#define X86_FSW_C_MASK UINT16_C(0x4700)
3434/** FPU busy. */
3435#define X86_FSW_B RT_BIT_32(15)
3436/** For use with FPREM and FPREM1. */
3437#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3438 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3439 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3440 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3441/** For use with FPREM and FPREM1. */
3442#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3443 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3444 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3445 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3446/** @} */
3447
3448
3449/** @name FPU control word flags.
3450 * @{ */
3451/** Exception Mask: Invalid operation. */
3452#define X86_FCW_IM RT_BIT_32(0)
3453#define X86_FCW_IM_BIT 0
3454/** Exception Mask: Denormalized operand. */
3455#define X86_FCW_DM RT_BIT_32(1)
3456#define X86_FCW_DM_BIT 1
3457/** Exception Mask: Zero divide. */
3458#define X86_FCW_ZM RT_BIT_32(2)
3459#define X86_FCW_ZM_BIT 2
3460/** Exception Mask: Overflow. */
3461#define X86_FCW_OM RT_BIT_32(3)
3462#define X86_FCW_OM_BIT 3
3463/** Exception Mask: Underflow. */
3464#define X86_FCW_UM RT_BIT_32(4)
3465#define X86_FCW_UM_BIT 4
3466/** Exception Mask: Precision. */
3467#define X86_FCW_PM RT_BIT_32(5)
3468#define X86_FCW_PM_BIT 5
3469/** Mask all exceptions, the value typically loaded (by for instance fninit).
3470 * @remarks This includes reserved bit 6. */
3471#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3472/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3473#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3474/** Precision control mask. */
3475#define X86_FCW_PC_MASK UINT16_C(0x0300)
3476/** Precision control shift. */
3477#define X86_FCW_PC_SHIFT 8
3478/** Precision control: 24-bit. */
3479#define X86_FCW_PC_24 UINT16_C(0x0000)
3480/** Precision control: Reserved. */
3481#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3482/** Precision control: 53-bit. */
3483#define X86_FCW_PC_53 UINT16_C(0x0200)
3484/** Precision control: 64-bit. */
3485#define X86_FCW_PC_64 UINT16_C(0x0300)
3486/** Rounding control mask. */
3487#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3488/** Rounding control shift. */
3489#define X86_FCW_RC_SHIFT 10
3490/** Rounding control: To nearest. */
3491#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3492/** Rounding control: Down. */
3493#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3494/** Rounding control: Up. */
3495#define X86_FCW_RC_UP UINT16_C(0x0800)
3496/** Rounding control: Towards zero. */
3497#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3498/** Infinity control mask - obsolete, 8087 & 287 only. */
3499#define X86_FCW_IC_MASK UINT16_C(0x1000)
3500/** Infinity control: Affine - positive infinity is distictly different from
3501 * negative infinity.
3502 * @note 8087, 287 only */
3503#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3504/** Infinity control: Projective - positive and negative infinity are the
3505 * same (sign ignored).
3506 * @note 8087, 287 only */
3507#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3508/** Bits which should be zero, apparently. */
3509#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3510/** @} */
3511
3512/** @name SSE MXCSR
3513 * @{ */
3514/** Exception Flag: Invalid operation. */
3515#define X86_MXCSR_IE RT_BIT_32(0)
3516/** Exception Flag: Denormalized operand. */
3517#define X86_MXCSR_DE RT_BIT_32(1)
3518/** Exception Flag: Zero divide. */
3519#define X86_MXCSR_ZE RT_BIT_32(2)
3520/** Exception Flag: Overflow. */
3521#define X86_MXCSR_OE RT_BIT_32(3)
3522/** Exception Flag: Underflow. */
3523#define X86_MXCSR_UE RT_BIT_32(4)
3524/** Exception Flag: Precision. */
3525#define X86_MXCSR_PE RT_BIT_32(5)
3526/** Exception Flags: mask */
3527#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3528
3529/** Denormals are zero. */
3530#define X86_MXCSR_DAZ RT_BIT_32(6)
3531
3532/** Exception Mask: Invalid operation. */
3533#define X86_MXCSR_IM RT_BIT_32(7)
3534/** Exception Mask: Denormalized operand. */
3535#define X86_MXCSR_DM RT_BIT_32(8)
3536/** Exception Mask: Zero divide. */
3537#define X86_MXCSR_ZM RT_BIT_32(9)
3538/** Exception Mask: Overflow. */
3539#define X86_MXCSR_OM RT_BIT_32(10)
3540/** Exception Mask: Underflow. */
3541#define X86_MXCSR_UM RT_BIT_32(11)
3542/** Exception Mask: Precision. */
3543#define X86_MXCSR_PM RT_BIT_32(12)
3544/** Exception Mask: mask. */
3545#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3546/** Exception Mask: shift. */
3547#define X86_MXCSR_XCPT_MASK_SHIFT 7
3548
3549/** Rounding control mask. */
3550#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3551/** Rounding control shift. */
3552#define X86_MXCSR_RC_SHIFT 13
3553/** Rounding control: To nearest. */
3554#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3555/** Rounding control: Down. */
3556#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3557/** Rounding control: Up. */
3558#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3559/** Rounding control: Towards zero. */
3560#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3561
3562/** Flush-to-zero for masked underflow. */
3563#define X86_MXCSR_FZ RT_BIT_32(15)
3564
3565/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3566#define X86_MXCSR_MM RT_BIT_32(17)
3567/** Bits which should be zero, apparently. */
3568#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3569/** @} */
3570
3571/**
3572 * XSAVE header.
3573 */
3574typedef struct X86XSAVEHDR
3575{
3576 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3577 uint64_t bmXState;
3578 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3579 uint64_t bmXComp;
3580 /** Reserved for furture extensions, probably MBZ. */
3581 uint64_t au64Reserved[6];
3582} X86XSAVEHDR;
3583#ifndef VBOX_FOR_DTRACE_LIB
3584AssertCompileSize(X86XSAVEHDR, 64);
3585#endif
3586/** Pointer to an XSAVE header. */
3587typedef X86XSAVEHDR *PX86XSAVEHDR;
3588/** Pointer to a const XSAVE header. */
3589typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3590
3591
3592/**
3593 * The high 128-bit YMM register state (XSAVE_C_YMM).
3594 * (The lower 128-bits being in X86FXSTATE.)
3595 */
3596typedef struct X86XSAVEYMMHI
3597{
3598 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3599 X86XMMREG aYmmHi[16];
3600} X86XSAVEYMMHI;
3601#ifndef VBOX_FOR_DTRACE_LIB
3602AssertCompileSize(X86XSAVEYMMHI, 256);
3603#endif
3604/** Pointer to a high 128-bit YMM register state. */
3605typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3606/** Pointer to a const high 128-bit YMM register state. */
3607typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3608
3609/**
3610 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3611 */
3612typedef struct X86XSAVEBNDREGS
3613{
3614 /** Array of registers (BND0...BND3). */
3615 struct
3616 {
3617 /** Lower bound. */
3618 uint64_t uLowerBound;
3619 /** Upper bound. */
3620 uint64_t uUpperBound;
3621 } aRegs[4];
3622} X86XSAVEBNDREGS;
3623#ifndef VBOX_FOR_DTRACE_LIB
3624AssertCompileSize(X86XSAVEBNDREGS, 64);
3625#endif
3626/** Pointer to a MPX bound register state. */
3627typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3628/** Pointer to a const MPX bound register state. */
3629typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3630
3631/**
3632 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3633 */
3634typedef struct X86XSAVEBNDCFG
3635{
3636 uint64_t fConfig;
3637 uint64_t fStatus;
3638} X86XSAVEBNDCFG;
3639#ifndef VBOX_FOR_DTRACE_LIB
3640AssertCompileSize(X86XSAVEBNDCFG, 16);
3641#endif
3642/** Pointer to a MPX bound config and status register state. */
3643typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3644/** Pointer to a const MPX bound config and status register state. */
3645typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3646
3647/**
3648 * AVX-512 opmask state (XSAVE_C_OPMASK).
3649 */
3650typedef struct X86XSAVEOPMASK
3651{
3652 /** The K0..K7 values. */
3653 uint64_t aKRegs[8];
3654} X86XSAVEOPMASK;
3655#ifndef VBOX_FOR_DTRACE_LIB
3656AssertCompileSize(X86XSAVEOPMASK, 64);
3657#endif
3658/** Pointer to a AVX-512 opmask state. */
3659typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3660/** Pointer to a const AVX-512 opmask state. */
3661typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3662
3663/**
3664 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3665 */
3666typedef struct X86XSAVEZMMHI256
3667{
3668 /** Upper 256-bits of ZMM0-15. */
3669 X86YMMREG aHi256Regs[16];
3670} X86XSAVEZMMHI256;
3671#ifndef VBOX_FOR_DTRACE_LIB
3672AssertCompileSize(X86XSAVEZMMHI256, 512);
3673#endif
3674/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3675typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3676/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3677typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3678
3679/**
3680 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3681 */
3682typedef struct X86XSAVEZMM16HI
3683{
3684 /** ZMM16 thru ZMM31. */
3685 X86ZMMREG aRegs[16];
3686} X86XSAVEZMM16HI;
3687#ifndef VBOX_FOR_DTRACE_LIB
3688AssertCompileSize(X86XSAVEZMM16HI, 1024);
3689#endif
3690/** Pointer to a state comprising ZMM16-32. */
3691typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3692/** Pointer to a const state comprising ZMM16-32. */
3693typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3694
3695/**
3696 * AMD Light weight profiling state (XSAVE_C_LWP).
3697 *
3698 * We probably won't play with this as AMD seems to be dropping from their "zen"
3699 * processor micro architecture.
3700 */
3701typedef struct X86XSAVELWP
3702{
3703 /** Details when needed. */
3704 uint64_t auLater[128/8];
3705} X86XSAVELWP;
3706#ifndef VBOX_FOR_DTRACE_LIB
3707AssertCompileSize(X86XSAVELWP, 128);
3708#endif
3709
3710
3711/**
3712 * x86 FPU/SSE/AVX/XXXX state.
3713 *
3714 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3715 * changes to this structure.
3716 */
3717typedef struct X86XSAVEAREA
3718{
3719 /** The x87 and SSE region (or legacy region if you like). */
3720 X86FXSTATE x87;
3721 /** The XSAVE header. */
3722 X86XSAVEHDR Hdr;
3723 /** Beyond the header, there isn't really a fixed layout, but we can
3724 generally assume the YMM (AVX) register extensions are present and
3725 follows immediately. */
3726 union
3727 {
3728 /** The high 128-bit AVX registers for easy access by IEM.
3729 * @note This ASSUMES they will always be here... */
3730 X86XSAVEYMMHI YmmHi;
3731
3732 /** This is a typical layout on intel CPUs (good for debuggers). */
3733 struct
3734 {
3735 X86XSAVEYMMHI YmmHi;
3736 X86XSAVEBNDREGS BndRegs;
3737 X86XSAVEBNDCFG BndCfg;
3738 uint8_t abFudgeToMatchDocs[0xB0];
3739 X86XSAVEOPMASK Opmask;
3740 X86XSAVEZMMHI256 ZmmHi256;
3741 X86XSAVEZMM16HI Zmm16Hi;
3742 } Intel;
3743
3744 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3745 struct
3746 {
3747 X86XSAVEYMMHI YmmHi;
3748 X86XSAVELWP Lwp;
3749 } AmdBd;
3750
3751 /** To enbling static deployments that have a reasonable chance of working for
3752 * the next 3-6 CPU generations without running short on space, we allocate a
3753 * lot of extra space here, making the structure a round 8KB in size. This
3754 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3755 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3756 uint8_t ab[8192 - 512 - 64];
3757 } u;
3758} X86XSAVEAREA;
3759#ifndef VBOX_FOR_DTRACE_LIB
3760AssertCompileSize(X86XSAVEAREA, 8192);
3761AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3762AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3763AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3764AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3765AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3766AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3767AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3768AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3769#endif
3770/** Pointer to a XSAVE area. */
3771typedef X86XSAVEAREA *PX86XSAVEAREA;
3772/** Pointer to a const XSAVE area. */
3773typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3774
3775
3776/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3777 * @{ */
3778/** Bit 0 - x87 - Legacy FPU state (bit number) */
3779#define XSAVE_C_X87_BIT 0
3780/** Bit 0 - x87 - Legacy FPU state. */
3781#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3782/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3783#define XSAVE_C_SSE_BIT 1
3784/** Bit 1 - SSE - 128-bit SSE state. */
3785#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3786/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3787#define XSAVE_C_YMM_BIT 2
3788/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3789#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3790/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3791#define XSAVE_C_BNDREGS_BIT 3
3792/** Bit 3 - BNDREGS - MPX bound register state. */
3793#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3794/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3795#define XSAVE_C_BNDCSR_BIT 4
3796/** Bit 4 - BNDCSR - MPX bound config and status state. */
3797#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3798/** Bit 5 - Opmask - opmask state (bit number). */
3799#define XSAVE_C_OPMASK_BIT 5
3800/** Bit 5 - Opmask - opmask state. */
3801#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3802/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3803#define XSAVE_C_ZMM_HI256_BIT 6
3804/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3805#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3806/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3807#define XSAVE_C_ZMM_16HI_BIT 7
3808/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3809#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3810/** Bit 9 - PKRU - Protection-key state (bit number). */
3811#define XSAVE_C_PKRU_BIT 9
3812/** Bit 9 - PKRU - Protection-key state. */
3813#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3814/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3815#define XSAVE_C_LWP_BIT 62
3816/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3817#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3818/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3819#define XSAVE_C_X_BIT 63
3820/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3821#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3822/** @} */
3823
3824
3825
3826/** @name Selector Descriptor
3827 * @{
3828 */
3829
3830#ifndef VBOX_FOR_DTRACE_LIB
3831/**
3832 * Descriptor attributes (as seen by VT-x).
3833 */
3834typedef struct X86DESCATTRBITS
3835{
3836 /** 00 - Segment Type. */
3837 unsigned u4Type : 4;
3838 /** 04 - Descriptor Type. System(=0) or code/data selector */
3839 unsigned u1DescType : 1;
3840 /** 05 - Descriptor Privilege level. */
3841 unsigned u2Dpl : 2;
3842 /** 07 - Flags selector present(=1) or not. */
3843 unsigned u1Present : 1;
3844 /** 08 - Segment limit 16-19. */
3845 unsigned u4LimitHigh : 4;
3846 /** 0c - Available for system software. */
3847 unsigned u1Available : 1;
3848 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3849 unsigned u1Long : 1;
3850 /** 0e - This flags meaning depends on the segment type. Try make sense out
3851 * of the intel manual yourself. */
3852 unsigned u1DefBig : 1;
3853 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3854 * clear byte. */
3855 unsigned u1Granularity : 1;
3856 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3857 unsigned u1Unusable : 1;
3858} X86DESCATTRBITS;
3859#endif /* !VBOX_FOR_DTRACE_LIB */
3860
3861/** @name X86DESCATTR masks
3862 * @{ */
3863#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3864#define X86DESCATTR_DT UINT32_C(0x00000010)
3865#define X86DESCATTR_DPL UINT32_C(0x00000060)
3866#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3867#define X86DESCATTR_P UINT32_C(0x00000080)
3868#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3869#define X86DESCATTR_AVL UINT32_C(0x00001000)
3870#define X86DESCATTR_L UINT32_C(0x00002000)
3871#define X86DESCATTR_D UINT32_C(0x00004000)
3872#define X86DESCATTR_G UINT32_C(0x00008000)
3873#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3874/** @} */
3875
3876#pragma pack(1)
3877typedef union X86DESCATTR
3878{
3879 /** Unsigned integer view. */
3880 uint32_t u;
3881#ifndef VBOX_FOR_DTRACE_LIB
3882 /** Normal view. */
3883 X86DESCATTRBITS n;
3884#endif
3885} X86DESCATTR;
3886#pragma pack()
3887/** Pointer to descriptor attributes. */
3888typedef X86DESCATTR *PX86DESCATTR;
3889/** Pointer to const descriptor attributes. */
3890typedef const X86DESCATTR *PCX86DESCATTR;
3891
3892#ifndef VBOX_FOR_DTRACE_LIB
3893
3894/**
3895 * Generic descriptor table entry
3896 */
3897#pragma pack(1)
3898typedef struct X86DESCGENERIC
3899{
3900 /** 00 - Limit - Low word. */
3901 unsigned u16LimitLow : 16;
3902 /** 10 - Base address - low word.
3903 * Don't try set this to 24 because MSC is doing stupid things then. */
3904 unsigned u16BaseLow : 16;
3905 /** 20 - Base address - first 8 bits of high word. */
3906 unsigned u8BaseHigh1 : 8;
3907 /** 28 - Segment Type. */
3908 unsigned u4Type : 4;
3909 /** 2c - Descriptor Type. System(=0) or code/data selector */
3910 unsigned u1DescType : 1;
3911 /** 2d - Descriptor Privilege level. */
3912 unsigned u2Dpl : 2;
3913 /** 2f - Flags selector present(=1) or not. */
3914 unsigned u1Present : 1;
3915 /** 30 - Segment limit 16-19. */
3916 unsigned u4LimitHigh : 4;
3917 /** 34 - Available for system software. */
3918 unsigned u1Available : 1;
3919 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3920 unsigned u1Long : 1;
3921 /** 36 - This flags meaning depends on the segment type. Try make sense out
3922 * of the intel manual yourself. */
3923 unsigned u1DefBig : 1;
3924 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3925 * clear byte. */
3926 unsigned u1Granularity : 1;
3927 /** 38 - Base address - highest 8 bits. */
3928 unsigned u8BaseHigh2 : 8;
3929} X86DESCGENERIC;
3930#pragma pack()
3931/** Pointer to a generic descriptor entry. */
3932typedef X86DESCGENERIC *PX86DESCGENERIC;
3933/** Pointer to a const generic descriptor entry. */
3934typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3935
3936/** @name Bit offsets of X86DESCGENERIC members.
3937 * @{*/
3938#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3939#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3940#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3941#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3942#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3943#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3944#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3945#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3946#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3947#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3948#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3949#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3950#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3951/** @} */
3952
3953
3954/** @name LAR mask
3955 * @{ */
3956#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3957#define X86LAR_F_DT UINT16_C( 0x1000)
3958#define X86LAR_F_DPL UINT16_C( 0x6000)
3959#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3960#define X86LAR_F_P UINT16_C( 0x8000)
3961#define X86LAR_F_AVL UINT32_C(0x00100000)
3962#define X86LAR_F_L UINT32_C(0x00200000)
3963#define X86LAR_F_D UINT32_C(0x00400000)
3964#define X86LAR_F_G UINT32_C(0x00800000)
3965/** @} */
3966
3967
3968/**
3969 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3970 */
3971typedef struct X86DESCGATE
3972{
3973 /** 00 - Target code segment offset - Low word.
3974 * Ignored if task-gate. */
3975 unsigned u16OffsetLow : 16;
3976 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3977 * TSS selector if task-gate. */
3978 unsigned u16Sel : 16;
3979 /** 20 - Number of parameters for a call-gate.
3980 * Ignored if interrupt-, trap- or task-gate. */
3981 unsigned u5ParmCount : 5;
3982 /** 25 - Reserved / ignored. */
3983 unsigned u3Reserved : 3;
3984 /** 28 - Segment Type. */
3985 unsigned u4Type : 4;
3986 /** 2c - Descriptor Type (0 = system). */
3987 unsigned u1DescType : 1;
3988 /** 2d - Descriptor Privilege level. */
3989 unsigned u2Dpl : 2;
3990 /** 2f - Flags selector present(=1) or not. */
3991 unsigned u1Present : 1;
3992 /** 30 - Target code segment offset - High word.
3993 * Ignored if task-gate. */
3994 unsigned u16OffsetHigh : 16;
3995} X86DESCGATE;
3996/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3997typedef X86DESCGATE *PX86DESCGATE;
3998/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3999typedef const X86DESCGATE *PCX86DESCGATE;
4000
4001#endif /* VBOX_FOR_DTRACE_LIB */
4002
4003/**
4004 * Descriptor table entry.
4005 */
4006#pragma pack(1)
4007typedef union X86DESC
4008{
4009#ifndef VBOX_FOR_DTRACE_LIB
4010 /** Generic descriptor view. */
4011 X86DESCGENERIC Gen;
4012 /** Gate descriptor view. */
4013 X86DESCGATE Gate;
4014#endif
4015
4016 /** 8 bit unsigned integer view. */
4017 uint8_t au8[8];
4018 /** 16 bit unsigned integer view. */
4019 uint16_t au16[4];
4020 /** 32 bit unsigned integer view. */
4021 uint32_t au32[2];
4022 /** 64 bit unsigned integer view. */
4023 uint64_t au64[1];
4024 /** Unsigned integer view. */
4025 uint64_t u;
4026} X86DESC;
4027#ifndef VBOX_FOR_DTRACE_LIB
4028AssertCompileSize(X86DESC, 8);
4029#endif
4030#pragma pack()
4031/** Pointer to descriptor table entry. */
4032typedef X86DESC *PX86DESC;
4033/** Pointer to const descriptor table entry. */
4034typedef const X86DESC *PCX86DESC;
4035
4036/** @def X86DESC_BASE
4037 * Return the base address of a descriptor.
4038 */
4039#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
4040 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4041 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4042 | ( (a_pDesc)->Gen.u16BaseLow ) )
4043
4044/** @def X86DESC_LIMIT
4045 * Return the limit of a descriptor.
4046 */
4047#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
4048 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4049 | ( (a_pDesc)->Gen.u16LimitLow ) )
4050
4051/** @def X86DESC_LIMIT_G
4052 * Return the limit of a descriptor with the granularity bit taken into account.
4053 * @returns Selector limit (uint32_t).
4054 * @param a_pDesc Pointer to the descriptor.
4055 */
4056#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
4057 ( (a_pDesc)->Gen.u1Granularity \
4058 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
4059 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
4060 )
4061
4062/** @def X86DESC_GET_HID_ATTR
4063 * Get the descriptor attributes for the hidden register.
4064 */
4065#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
4066 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4067
4068#ifndef VBOX_FOR_DTRACE_LIB
4069
4070/**
4071 * 64 bits generic descriptor table entry
4072 * Note: most of these bits have no meaning in long mode.
4073 */
4074#pragma pack(1)
4075typedef struct X86DESC64GENERIC
4076{
4077 /** Limit - Low word - *IGNORED*. */
4078 uint32_t u16LimitLow : 16;
4079 /** Base address - low word. - *IGNORED*
4080 * Don't try set this to 24 because MSC is doing stupid things then. */
4081 uint32_t u16BaseLow : 16;
4082 /** Base address - first 8 bits of high word. - *IGNORED* */
4083 uint32_t u8BaseHigh1 : 8;
4084 /** Segment Type. */
4085 uint32_t u4Type : 4;
4086 /** Descriptor Type. System(=0) or code/data selector */
4087 uint32_t u1DescType : 1;
4088 /** Descriptor Privilege level. */
4089 uint32_t u2Dpl : 2;
4090 /** Flags selector present(=1) or not. */
4091 uint32_t u1Present : 1;
4092 /** Segment limit 16-19. - *IGNORED* */
4093 uint32_t u4LimitHigh : 4;
4094 /** Available for system software. - *IGNORED* */
4095 uint32_t u1Available : 1;
4096 /** Long mode flag. */
4097 uint32_t u1Long : 1;
4098 /** This flags meaning depends on the segment type. Try make sense out
4099 * of the intel manual yourself. */
4100 uint32_t u1DefBig : 1;
4101 /** Granularity of the limit. If set 4KB granularity is used, if
4102 * clear byte. - *IGNORED* */
4103 uint32_t u1Granularity : 1;
4104 /** Base address - highest 8 bits. - *IGNORED* */
4105 uint32_t u8BaseHigh2 : 8;
4106 /** Base address - bits 63-32. */
4107 uint32_t u32BaseHigh3 : 32;
4108 uint32_t u8Reserved : 8;
4109 uint32_t u5Zeros : 5;
4110 uint32_t u19Reserved : 19;
4111} X86DESC64GENERIC;
4112#pragma pack()
4113/** Pointer to a generic descriptor entry. */
4114typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4115/** Pointer to a const generic descriptor entry. */
4116typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4117
4118/**
4119 * System descriptor table entry (64 bits)
4120 *
4121 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4122 */
4123#pragma pack(1)
4124typedef struct X86DESC64SYSTEM
4125{
4126 /** Limit - Low word. */
4127 uint32_t u16LimitLow : 16;
4128 /** Base address - low word.
4129 * Don't try set this to 24 because MSC is doing stupid things then. */
4130 uint32_t u16BaseLow : 16;
4131 /** Base address - first 8 bits of high word. */
4132 uint32_t u8BaseHigh1 : 8;
4133 /** Segment Type. */
4134 uint32_t u4Type : 4;
4135 /** Descriptor Type. System(=0) or code/data selector */
4136 uint32_t u1DescType : 1;
4137 /** Descriptor Privilege level. */
4138 uint32_t u2Dpl : 2;
4139 /** Flags selector present(=1) or not. */
4140 uint32_t u1Present : 1;
4141 /** Segment limit 16-19. */
4142 uint32_t u4LimitHigh : 4;
4143 /** Available for system software. */
4144 uint32_t u1Available : 1;
4145 /** Reserved - 0. */
4146 uint32_t u1Reserved : 1;
4147 /** This flags meaning depends on the segment type. Try make sense out
4148 * of the intel manual yourself. */
4149 uint32_t u1DefBig : 1;
4150 /** Granularity of the limit. If set 4KB granularity is used, if
4151 * clear byte. */
4152 uint32_t u1Granularity : 1;
4153 /** Base address - bits 31-24. */
4154 uint32_t u8BaseHigh2 : 8;
4155 /** Base address - bits 63-32. */
4156 uint32_t u32BaseHigh3 : 32;
4157 uint32_t u8Reserved : 8;
4158 uint32_t u5Zeros : 5;
4159 uint32_t u19Reserved : 19;
4160} X86DESC64SYSTEM;
4161#pragma pack()
4162/** Pointer to a system descriptor entry. */
4163typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4164/** Pointer to a const system descriptor entry. */
4165typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4166
4167/**
4168 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4169 */
4170typedef struct X86DESC64GATE
4171{
4172 /** Target code segment offset - Low word. */
4173 uint32_t u16OffsetLow : 16;
4174 /** Target code segment selector. */
4175 uint32_t u16Sel : 16;
4176 /** Interrupt stack table for interrupt- and trap-gates.
4177 * Ignored by call-gates. */
4178 uint32_t u3IST : 3;
4179 /** Reserved / ignored. */
4180 uint32_t u5Reserved : 5;
4181 /** Segment Type. */
4182 uint32_t u4Type : 4;
4183 /** Descriptor Type (0 = system). */
4184 uint32_t u1DescType : 1;
4185 /** Descriptor Privilege level. */
4186 uint32_t u2Dpl : 2;
4187 /** Flags selector present(=1) or not. */
4188 uint32_t u1Present : 1;
4189 /** Target code segment offset - High word.
4190 * Ignored if task-gate. */
4191 uint32_t u16OffsetHigh : 16;
4192 /** Target code segment offset - Top dword.
4193 * Ignored if task-gate. */
4194 uint32_t u32OffsetTop : 32;
4195 /** Reserved / ignored / must be zero.
4196 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4197 uint32_t u32Reserved : 32;
4198} X86DESC64GATE;
4199AssertCompileSize(X86DESC64GATE, 16);
4200/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4201typedef X86DESC64GATE *PX86DESC64GATE;
4202/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4203typedef const X86DESC64GATE *PCX86DESC64GATE;
4204
4205#endif /* VBOX_FOR_DTRACE_LIB */
4206
4207/**
4208 * Descriptor table entry.
4209 */
4210#pragma pack(1)
4211typedef union X86DESC64
4212{
4213#ifndef VBOX_FOR_DTRACE_LIB
4214 /** Generic descriptor view. */
4215 X86DESC64GENERIC Gen;
4216 /** System descriptor view. */
4217 X86DESC64SYSTEM System;
4218 /** Gate descriptor view. */
4219 X86DESC64GATE Gate;
4220#endif
4221
4222 /** 8 bit unsigned integer view. */
4223 uint8_t au8[16];
4224 /** 16 bit unsigned integer view. */
4225 uint16_t au16[8];
4226 /** 32 bit unsigned integer view. */
4227 uint32_t au32[4];
4228 /** 64 bit unsigned integer view. */
4229 uint64_t au64[2];
4230} X86DESC64;
4231#ifndef VBOX_FOR_DTRACE_LIB
4232AssertCompileSize(X86DESC64, 16);
4233#endif
4234#pragma pack()
4235/** Pointer to descriptor table entry. */
4236typedef X86DESC64 *PX86DESC64;
4237/** Pointer to const descriptor table entry. */
4238typedef const X86DESC64 *PCX86DESC64;
4239
4240/** @def X86DESC64_BASE
4241 * Return the base of a 64-bit descriptor.
4242 */
4243#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
4244 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4245 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4246 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4247 | ( (a_pDesc)->Gen.u16BaseLow ) )
4248
4249
4250
4251/** @name Host system descriptor table entry - Use with care!
4252 * @{ */
4253/** Host system descriptor table entry. */
4254#if HC_ARCH_BITS == 64
4255typedef X86DESC64 X86DESCHC;
4256#else
4257typedef X86DESC X86DESCHC;
4258#endif
4259/** Pointer to a host system descriptor table entry. */
4260#if HC_ARCH_BITS == 64
4261typedef PX86DESC64 PX86DESCHC;
4262#else
4263typedef PX86DESC PX86DESCHC;
4264#endif
4265/** Pointer to a const host system descriptor table entry. */
4266#if HC_ARCH_BITS == 64
4267typedef PCX86DESC64 PCX86DESCHC;
4268#else
4269typedef PCX86DESC PCX86DESCHC;
4270#endif
4271/** @} */
4272
4273
4274/** @name Selector Descriptor Types.
4275 * @{
4276 */
4277
4278/** @name Non-System Selector Types.
4279 * @{ */
4280/** Code(=set)/Data(=clear) bit. */
4281#define X86_SEL_TYPE_CODE 8
4282/** Memory(=set)/System(=clear) bit. */
4283#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4284/** Accessed bit. */
4285#define X86_SEL_TYPE_ACCESSED 1
4286/** Expand down bit (for data selectors only). */
4287#define X86_SEL_TYPE_DOWN 4
4288/** Conforming bit (for code selectors only). */
4289#define X86_SEL_TYPE_CONF 4
4290/** Write bit (for data selectors only). */
4291#define X86_SEL_TYPE_WRITE 2
4292/** Read bit (for code selectors only). */
4293#define X86_SEL_TYPE_READ 2
4294/** The bit number of the code segment read bit (relative to u4Type). */
4295#define X86_SEL_TYPE_READ_BIT 1
4296
4297/** Read only selector type. */
4298#define X86_SEL_TYPE_RO 0
4299/** Accessed read only selector type. */
4300#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
4301/** Read write selector type. */
4302#define X86_SEL_TYPE_RW 2
4303/** Accessed read write selector type. */
4304#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
4305/** Expand down read only selector type. */
4306#define X86_SEL_TYPE_RO_DOWN 4
4307/** Accessed expand down read only selector type. */
4308#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
4309/** Expand down read write selector type. */
4310#define X86_SEL_TYPE_RW_DOWN 6
4311/** Accessed expand down read write selector type. */
4312#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
4313/** Execute only selector type. */
4314#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
4315/** Accessed execute only selector type. */
4316#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4317/** Execute and read selector type. */
4318#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
4319/** Accessed execute and read selector type. */
4320#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4321/** Conforming execute only selector type. */
4322#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
4323/** Accessed Conforming execute only selector type. */
4324#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4325/** Conforming execute and write selector type. */
4326#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
4327/** Accessed Conforming execute and write selector type. */
4328#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4329/** @} */
4330
4331
4332/** @name System Selector Types.
4333 * @{ */
4334/** The TSS busy bit mask. */
4335#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4336
4337/** Undefined system selector type. */
4338#define X86_SEL_TYPE_SYS_UNDEFINED 0
4339/** 286 TSS selector. */
4340#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4341/** LDT selector. */
4342#define X86_SEL_TYPE_SYS_LDT 2
4343/** 286 TSS selector - Busy. */
4344#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4345/** 286 Callgate selector. */
4346#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4347/** Taskgate selector. */
4348#define X86_SEL_TYPE_SYS_TASK_GATE 5
4349/** 286 Interrupt gate selector. */
4350#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4351/** 286 Trapgate selector. */
4352#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4353/** Undefined system selector. */
4354#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4355/** 386 TSS selector. */
4356#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4357/** Undefined system selector. */
4358#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4359/** 386 TSS selector - Busy. */
4360#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4361/** 386 Callgate selector. */
4362#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4363/** Undefined system selector. */
4364#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4365/** 386 Interruptgate selector. */
4366#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4367/** 386 Trapgate selector. */
4368#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4369/** @} */
4370
4371/** @name AMD64 System Selector Types.
4372 * @{ */
4373/** LDT selector. */
4374#define AMD64_SEL_TYPE_SYS_LDT 2
4375/** TSS selector - Busy. */
4376#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4377/** TSS selector - Busy. */
4378#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4379/** Callgate selector. */
4380#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4381/** Interruptgate selector. */
4382#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4383/** Trapgate selector. */
4384#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4385/** @} */
4386
4387/** @} */
4388
4389
4390/** @name Descriptor Table Entry Flag Masks.
4391 * These are for the 2nd 32-bit word of a descriptor.
4392 * @{ */
4393/** Bits 8-11 - TYPE - Descriptor type mask. */
4394#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4395/** Bit 12 - S - System (=0) or Code/Data (=1). */
4396#define X86_DESC_S RT_BIT_32(12)
4397/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4398#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4399/** Bit 15 - P - Present. */
4400#define X86_DESC_P RT_BIT_32(15)
4401/** Bit 20 - AVL - Available for system software. */
4402#define X86_DESC_AVL RT_BIT_32(20)
4403/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4404#define X86_DESC_DB RT_BIT_32(22)
4405/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4406 * used, if clear byte. */
4407#define X86_DESC_G RT_BIT_32(23)
4408/** @} */
4409
4410/** @} */
4411
4412
4413/** @name Task Segments.
4414 * @{
4415 */
4416
4417/**
4418 * The minimum TSS descriptor limit for 286 tasks.
4419 */
4420#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4421
4422/**
4423 * The minimum TSS descriptor segment limit for 386 tasks.
4424 */
4425#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4426
4427/**
4428 * 16-bit Task Segment (TSS).
4429 */
4430#pragma pack(1)
4431typedef struct X86TSS16
4432{
4433 /** Back link to previous task. (static) */
4434 RTSEL selPrev;
4435 /** Ring-0 stack pointer. (static) */
4436 uint16_t sp0;
4437 /** Ring-0 stack segment. (static) */
4438 RTSEL ss0;
4439 /** Ring-1 stack pointer. (static) */
4440 uint16_t sp1;
4441 /** Ring-1 stack segment. (static) */
4442 RTSEL ss1;
4443 /** Ring-2 stack pointer. (static) */
4444 uint16_t sp2;
4445 /** Ring-2 stack segment. (static) */
4446 RTSEL ss2;
4447 /** IP before task switch. */
4448 uint16_t ip;
4449 /** FLAGS before task switch. */
4450 uint16_t flags;
4451 /** AX before task switch. */
4452 uint16_t ax;
4453 /** CX before task switch. */
4454 uint16_t cx;
4455 /** DX before task switch. */
4456 uint16_t dx;
4457 /** BX before task switch. */
4458 uint16_t bx;
4459 /** SP before task switch. */
4460 uint16_t sp;
4461 /** BP before task switch. */
4462 uint16_t bp;
4463 /** SI before task switch. */
4464 uint16_t si;
4465 /** DI before task switch. */
4466 uint16_t di;
4467 /** ES before task switch. */
4468 RTSEL es;
4469 /** CS before task switch. */
4470 RTSEL cs;
4471 /** SS before task switch. */
4472 RTSEL ss;
4473 /** DS before task switch. */
4474 RTSEL ds;
4475 /** LDTR before task switch. */
4476 RTSEL selLdt;
4477} X86TSS16;
4478#ifndef VBOX_FOR_DTRACE_LIB
4479AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4480#endif
4481#pragma pack()
4482/** Pointer to a 16-bit task segment. */
4483typedef X86TSS16 *PX86TSS16;
4484/** Pointer to a const 16-bit task segment. */
4485typedef const X86TSS16 *PCX86TSS16;
4486
4487
4488/**
4489 * 32-bit Task Segment (TSS).
4490 */
4491#pragma pack(1)
4492typedef struct X86TSS32
4493{
4494 /** Back link to previous task. (static) */
4495 RTSEL selPrev;
4496 uint16_t padding1;
4497 /** Ring-0 stack pointer. (static) */
4498 uint32_t esp0;
4499 /** Ring-0 stack segment. (static) */
4500 RTSEL ss0;
4501 uint16_t padding_ss0;
4502 /** Ring-1 stack pointer. (static) */
4503 uint32_t esp1;
4504 /** Ring-1 stack segment. (static) */
4505 RTSEL ss1;
4506 uint16_t padding_ss1;
4507 /** Ring-2 stack pointer. (static) */
4508 uint32_t esp2;
4509 /** Ring-2 stack segment. (static) */
4510 RTSEL ss2;
4511 uint16_t padding_ss2;
4512 /** Page directory for the task. (static) */
4513 uint32_t cr3;
4514 /** EIP before task switch. */
4515 uint32_t eip;
4516 /** EFLAGS before task switch. */
4517 uint32_t eflags;
4518 /** EAX before task switch. */
4519 uint32_t eax;
4520 /** ECX before task switch. */
4521 uint32_t ecx;
4522 /** EDX before task switch. */
4523 uint32_t edx;
4524 /** EBX before task switch. */
4525 uint32_t ebx;
4526 /** ESP before task switch. */
4527 uint32_t esp;
4528 /** EBP before task switch. */
4529 uint32_t ebp;
4530 /** ESI before task switch. */
4531 uint32_t esi;
4532 /** EDI before task switch. */
4533 uint32_t edi;
4534 /** ES before task switch. */
4535 RTSEL es;
4536 uint16_t padding_es;
4537 /** CS before task switch. */
4538 RTSEL cs;
4539 uint16_t padding_cs;
4540 /** SS before task switch. */
4541 RTSEL ss;
4542 uint16_t padding_ss;
4543 /** DS before task switch. */
4544 RTSEL ds;
4545 uint16_t padding_ds;
4546 /** FS before task switch. */
4547 RTSEL fs;
4548 uint16_t padding_fs;
4549 /** GS before task switch. */
4550 RTSEL gs;
4551 uint16_t padding_gs;
4552 /** LDTR before task switch. */
4553 RTSEL selLdt;
4554 uint16_t padding_ldt;
4555 /** Debug trap flag */
4556 uint16_t fDebugTrap;
4557 /** Offset relative to the TSS of the start of the I/O Bitmap
4558 * and the end of the interrupt redirection bitmap. */
4559 uint16_t offIoBitmap;
4560} X86TSS32;
4561#pragma pack()
4562/** Pointer to task segment. */
4563typedef X86TSS32 *PX86TSS32;
4564/** Pointer to const task segment. */
4565typedef const X86TSS32 *PCX86TSS32;
4566#ifndef VBOX_FOR_DTRACE_LIB
4567AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4568AssertCompileMemberOffset(X86TSS32, cr3, 28);
4569AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4570#endif
4571
4572/**
4573 * 64-bit Task segment.
4574 */
4575#pragma pack(1)
4576typedef struct X86TSS64
4577{
4578 /** Reserved. */
4579 uint32_t u32Reserved;
4580 /** Ring-0 stack pointer. (static) */
4581 uint64_t rsp0;
4582 /** Ring-1 stack pointer. (static) */
4583 uint64_t rsp1;
4584 /** Ring-2 stack pointer. (static) */
4585 uint64_t rsp2;
4586 /** Reserved. */
4587 uint32_t u32Reserved2[2];
4588 /* IST */
4589 uint64_t ist1;
4590 uint64_t ist2;
4591 uint64_t ist3;
4592 uint64_t ist4;
4593 uint64_t ist5;
4594 uint64_t ist6;
4595 uint64_t ist7;
4596 /* Reserved. */
4597 uint16_t u16Reserved[5];
4598 /** Offset relative to the TSS of the start of the I/O Bitmap
4599 * and the end of the interrupt redirection bitmap. */
4600 uint16_t offIoBitmap;
4601} X86TSS64;
4602#pragma pack()
4603/** Pointer to a 64-bit task segment. */
4604typedef X86TSS64 *PX86TSS64;
4605/** Pointer to a const 64-bit task segment. */
4606typedef const X86TSS64 *PCX86TSS64;
4607#ifndef VBOX_FOR_DTRACE_LIB
4608AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4609#endif
4610
4611/** @} */
4612
4613
4614/** @name Selectors.
4615 * @{
4616 */
4617
4618/**
4619 * The shift used to convert a selector from and to index an index (C).
4620 */
4621#define X86_SEL_SHIFT 3
4622
4623/**
4624 * The mask used to mask off the table indicator and RPL of an selector.
4625 */
4626#define X86_SEL_MASK 0xfff8U
4627
4628/**
4629 * The mask used to mask off the RPL of an selector.
4630 * This is suitable for checking for NULL selectors.
4631 */
4632#define X86_SEL_MASK_OFF_RPL 0xfffcU
4633
4634/**
4635 * The bit indicating that a selector is in the LDT and not in the GDT.
4636 */
4637#define X86_SEL_LDT 0x0004U
4638
4639/**
4640 * The bit mask for getting the RPL of a selector.
4641 */
4642#define X86_SEL_RPL 0x0003U
4643
4644/**
4645 * The mask covering both RPL and LDT.
4646 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4647 * checks.
4648 */
4649#define X86_SEL_RPL_LDT 0x0007U
4650
4651/** @} */
4652
4653
4654/**
4655 * x86 Exceptions/Faults/Traps.
4656 */
4657typedef enum X86XCPT
4658{
4659 /** \#DE - Divide error. */
4660 X86_XCPT_DE = 0x00,
4661 /** \#DB - Debug event (single step, DRx, ..) */
4662 X86_XCPT_DB = 0x01,
4663 /** NMI - Non-Maskable Interrupt */
4664 X86_XCPT_NMI = 0x02,
4665 /** \#BP - Breakpoint (INT3). */
4666 X86_XCPT_BP = 0x03,
4667 /** \#OF - Overflow (INTO). */
4668 X86_XCPT_OF = 0x04,
4669 /** \#BR - Bound range exceeded (BOUND). */
4670 X86_XCPT_BR = 0x05,
4671 /** \#UD - Undefined opcode. */
4672 X86_XCPT_UD = 0x06,
4673 /** \#NM - Device not available (math coprocessor device). */
4674 X86_XCPT_NM = 0x07,
4675 /** \#DF - Double fault. */
4676 X86_XCPT_DF = 0x08,
4677 /** ??? - Coprocessor segment overrun (obsolete). */
4678 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4679 /** \#TS - Taskswitch (TSS). */
4680 X86_XCPT_TS = 0x0a,
4681 /** \#NP - Segment no present. */
4682 X86_XCPT_NP = 0x0b,
4683 /** \#SS - Stack segment fault. */
4684 X86_XCPT_SS = 0x0c,
4685 /** \#GP - General protection fault. */
4686 X86_XCPT_GP = 0x0d,
4687 /** \#PF - Page fault. */
4688 X86_XCPT_PF = 0x0e,
4689 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4690 /** \#MF - Math fault (FPU). */
4691 X86_XCPT_MF = 0x10,
4692 /** \#AC - Alignment check. */
4693 X86_XCPT_AC = 0x11,
4694 /** \#MC - Machine check. */
4695 X86_XCPT_MC = 0x12,
4696 /** \#XF - SIMD Floating-Point Exception. */
4697 X86_XCPT_XF = 0x13,
4698 /** \#VE - Virtualization Exception (Intel only). */
4699 X86_XCPT_VE = 0x14,
4700 /** \#CP - Control Protection Exception (Intel only). */
4701 X86_XCPT_CP = 0x15,
4702 /** \#VC - VMM Communication Exception (AMD only). */
4703 X86_XCPT_VC = 0x1d,
4704 /** \#SX - Security Exception (AMD only). */
4705 X86_XCPT_SX = 0x1e
4706} X86XCPT;
4707/** Pointer to a x86 exception code. */
4708typedef X86XCPT *PX86XCPT;
4709/** Pointer to a const x86 exception code. */
4710typedef const X86XCPT *PCX86XCPT;
4711/** The last valid (currently reserved) exception value. */
4712#define X86_XCPT_LAST 0x1f
4713
4714
4715/** @name Trap Error Codes
4716 * @{
4717 */
4718/** External indicator. */
4719#define X86_TRAP_ERR_EXTERNAL 1
4720/** IDT indicator. */
4721#define X86_TRAP_ERR_IDT 2
4722/** Descriptor table indicator - If set LDT, if clear GDT. */
4723#define X86_TRAP_ERR_TI 4
4724/** Mask for getting the selector. */
4725#define X86_TRAP_ERR_SEL_MASK 0xfff8
4726/** Shift for getting the selector table index (C type index). */
4727#define X86_TRAP_ERR_SEL_SHIFT 3
4728/** @} */
4729
4730
4731/** @name \#PF Trap Error Codes
4732 * @{
4733 */
4734/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4735#define X86_TRAP_PF_P RT_BIT_32(0)
4736/** Bit 1 - R/W - Read (clear) or write (set) access. */
4737#define X86_TRAP_PF_RW RT_BIT_32(1)
4738/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4739#define X86_TRAP_PF_US RT_BIT_32(2)
4740/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4741#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4742/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4743#define X86_TRAP_PF_ID RT_BIT_32(4)
4744/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4745#define X86_TRAP_PF_PK RT_BIT_32(5)
4746/** @} */
4747
4748#pragma pack(1)
4749/**
4750 * 16-bit IDTR.
4751 */
4752typedef struct X86IDTR16
4753{
4754 /** Offset. */
4755 uint16_t offSel;
4756 /** Selector. */
4757 uint16_t uSel;
4758} X86IDTR16, *PX86IDTR16;
4759#pragma pack()
4760
4761#pragma pack(1)
4762/**
4763 * 32-bit IDTR/GDTR.
4764 */
4765typedef struct X86XDTR32
4766{
4767 /** Size of the descriptor table. */
4768 uint16_t cb;
4769 /** Address of the descriptor table. */
4770#ifndef VBOX_FOR_DTRACE_LIB
4771 uint32_t uAddr;
4772#else
4773 uint16_t au16Addr[2];
4774#endif
4775} X86XDTR32, *PX86XDTR32;
4776#pragma pack()
4777
4778#pragma pack(1)
4779/**
4780 * 64-bit IDTR/GDTR.
4781 */
4782typedef struct X86XDTR64
4783{
4784 /** Size of the descriptor table. */
4785 uint16_t cb;
4786 /** Address of the descriptor table. */
4787#ifndef VBOX_FOR_DTRACE_LIB
4788 uint64_t uAddr;
4789#else
4790 uint16_t au16Addr[4];
4791#endif
4792} X86XDTR64, *PX86XDTR64;
4793#pragma pack()
4794
4795
4796/** @name ModR/M
4797 * @{ */
4798#define X86_MODRM_RM_MASK UINT8_C(0x07)
4799#define X86_MODRM_REG_MASK UINT8_C(0x38)
4800#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4801#define X86_MODRM_REG_SHIFT 3
4802#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4803#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4804#define X86_MODRM_MOD_SHIFT 6
4805#ifndef VBOX_FOR_DTRACE_LIB
4806AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4807AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4808AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4809/** @def X86_MODRM_MAKE
4810 * @param a_Mod The mod value (0..3).
4811 * @param a_Reg The register value (0..7).
4812 * @param a_RegMem The register or memory value (0..7). */
4813# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4814#endif
4815/** @} */
4816
4817/** @name SIB
4818 * @{ */
4819#define X86_SIB_BASE_MASK UINT8_C(0x07)
4820#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4821#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4822#define X86_SIB_INDEX_SHIFT 3
4823#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4824#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4825#define X86_SIB_SCALE_SHIFT 6
4826#ifndef VBOX_FOR_DTRACE_LIB
4827AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4828AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4829AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4830#endif
4831/** @} */
4832
4833/** @name General register indexes.
4834 * @{ */
4835#define X86_GREG_xAX 0
4836#define X86_GREG_xCX 1
4837#define X86_GREG_xDX 2
4838#define X86_GREG_xBX 3
4839#define X86_GREG_xSP 4
4840#define X86_GREG_xBP 5
4841#define X86_GREG_xSI 6
4842#define X86_GREG_xDI 7
4843#define X86_GREG_x8 8
4844#define X86_GREG_x9 9
4845#define X86_GREG_x10 10
4846#define X86_GREG_x11 11
4847#define X86_GREG_x12 12
4848#define X86_GREG_x13 13
4849#define X86_GREG_x14 14
4850#define X86_GREG_x15 15
4851/** @} */
4852/** General register count. */
4853#define X86_GREG_COUNT 16
4854
4855/** @name X86_SREG_XXX - Segment register indexes.
4856 * @{ */
4857#define X86_SREG_ES 0
4858#define X86_SREG_CS 1
4859#define X86_SREG_SS 2
4860#define X86_SREG_DS 3
4861#define X86_SREG_FS 4
4862#define X86_SREG_GS 5
4863/** @} */
4864/** Segment register count. */
4865#define X86_SREG_COUNT 6
4866
4867
4868/** @name X86_OP_XXX - Prefixes
4869 * @{ */
4870#define X86_OP_PRF_CS UINT8_C(0x2e)
4871#define X86_OP_PRF_SS UINT8_C(0x36)
4872#define X86_OP_PRF_DS UINT8_C(0x3e)
4873#define X86_OP_PRF_ES UINT8_C(0x26)
4874#define X86_OP_PRF_FS UINT8_C(0x64)
4875#define X86_OP_PRF_GS UINT8_C(0x65)
4876#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4877#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4878#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4879#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4880#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4881#define X86_OP_REX_B UINT8_C(0x41)
4882#define X86_OP_REX_X UINT8_C(0x42)
4883#define X86_OP_REX_R UINT8_C(0x44)
4884#define X86_OP_REX_W UINT8_C(0x48)
4885/** @} */
4886
4887
4888/** @} */
4889
4890#endif /* !IPRT_INCLUDED_x86_h */
4891
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