VirtualBox

source: vbox/trunk/include/iprt/x86.h

Last change on this file was 103929, checked in by vboxsync, 8 weeks ago

iprt/x86.h: Added X86_OP_VEX3_BYTE1_MAKE(). bugref:9898
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
9 *
10 * This file is part of VirtualBox base platform packages, as
11 * available from https://www.virtualbox.org.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation, in version 3 of the
16 * License.
17 *
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, see <https://www.gnu.org/licenses>.
25 *
26 * The contents of this file may alternatively be used under the terms
27 * of the Common Development and Distribution License Version 1.0
28 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29 * in the VirtualBox distribution, in which case the provisions of the
30 * CDDL are applicable instead of those of the GPL.
31 *
32 * You may elect to license modified versions of this file under the
33 * terms and conditions of either the GPL or the CDDL or both.
34 *
35 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36 */
37
38#ifndef IPRT_INCLUDED_x86_h
39#define IPRT_INCLUDED_x86_h
40#ifndef RT_WITHOUT_PRAGMA_ONCE
41# pragma once
42#endif
43
44#ifndef VBOX_FOR_DTRACE_LIB
45# ifndef __ASSEMBLER__
46# include <iprt/types.h>
47# include <iprt/assert.h>
48# else
49# include <iprt/stdint.h>
50# include <iprt/assertcompile.h>
51# endif
52#else
53# pragma D depends_on library vbox-types.d
54#endif
55
56/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
57 * defining MSR_IA32_FLUSH_CMD and MSR_AMD_VIRT_SPEC_CTL */
58#ifdef RT_OS_SOLARIS
59# undef CS
60# undef DS
61# undef MSR_IA32_FLUSH_CMD
62# undef MSR_AMD_VIRT_SPEC_CTL
63#endif
64
65/** @defgroup grp_rt_x86 x86 Types and Definitions
66 * @ingroup grp_rt
67 * @{
68 */
69
70#ifndef __ASSEMBLER__
71
72# ifndef VBOX_FOR_DTRACE_LIB
73/**
74 * EFLAGS Bits.
75 */
76typedef struct X86EFLAGSBITS
77{
78 /** Bit 0 - CF - Carry flag - Status flag. */
79 unsigned u1CF : 1;
80 /** Bit 1 - 1 - Reserved flag. */
81 unsigned u1Reserved0 : 1;
82 /** Bit 2 - PF - Parity flag - Status flag. */
83 unsigned u1PF : 1;
84 /** Bit 3 - 0 - Reserved flag. */
85 unsigned u1Reserved1 : 1;
86 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
87 unsigned u1AF : 1;
88 /** Bit 5 - 0 - Reserved flag. */
89 unsigned u1Reserved2 : 1;
90 /** Bit 6 - ZF - Zero flag - Status flag. */
91 unsigned u1ZF : 1;
92 /** Bit 7 - SF - Signed flag - Status flag. */
93 unsigned u1SF : 1;
94 /** Bit 8 - TF - Trap flag - System flag. */
95 unsigned u1TF : 1;
96 /** Bit 9 - IF - Interrupt flag - System flag. */
97 unsigned u1IF : 1;
98 /** Bit 10 - DF - Direction flag - Control flag. */
99 unsigned u1DF : 1;
100 /** Bit 11 - OF - Overflow flag - Status flag. */
101 unsigned u1OF : 1;
102 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
103 unsigned u2IOPL : 2;
104 /** Bit 14 - NT - Nested task flag - System flag. */
105 unsigned u1NT : 1;
106 /** Bit 15 - 0 - Reserved flag. */
107 unsigned u1Reserved3 : 1;
108 /** Bit 16 - RF - Resume flag - System flag. */
109 unsigned u1RF : 1;
110 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
111 unsigned u1VM : 1;
112 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
113 unsigned u1AC : 1;
114 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
115 unsigned u1VIF : 1;
116 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
117 unsigned u1VIP : 1;
118 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
119 unsigned u1ID : 1;
120 /** Bit 22-31 - 0 - Reserved flag. */
121 unsigned u10Reserved4 : 10;
122} X86EFLAGSBITS;
123/** Pointer to EFLAGS bits. */
124typedef X86EFLAGSBITS *PX86EFLAGSBITS;
125/** Pointer to const EFLAGS bits. */
126typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
127# endif /* !VBOX_FOR_DTRACE_LIB */
128
129/**
130 * EFLAGS.
131 */
132typedef union X86EFLAGS
133{
134 /** The plain unsigned view. */
135 uint32_t u;
136# ifndef VBOX_FOR_DTRACE_LIB
137 /** The bitfield view. */
138 X86EFLAGSBITS Bits;
139# endif
140 /** The 8-bit view. */
141 uint8_t au8[4];
142 /** The 16-bit view. */
143 uint16_t au16[2];
144 /** The 32-bit view. */
145 uint32_t au32[1];
146 /** The 32-bit view. */
147 uint32_t u32;
148} X86EFLAGS;
149/** Pointer to EFLAGS. */
150typedef X86EFLAGS *PX86EFLAGS;
151/** Pointer to const EFLAGS. */
152typedef const X86EFLAGS *PCX86EFLAGS;
153
154/**
155 * RFLAGS (32 upper bits are reserved).
156 */
157typedef union X86RFLAGS
158{
159 /** The plain unsigned view. */
160 uint64_t u;
161# ifndef VBOX_FOR_DTRACE_LIB
162 /** The bitfield view. */
163 X86EFLAGSBITS Bits;
164# endif
165 /** The 8-bit view. */
166 uint8_t au8[8];
167 /** The 16-bit view. */
168 uint16_t au16[4];
169 /** The 32-bit view. */
170 uint32_t au32[2];
171 /** The 64-bit view. */
172 uint64_t au64[1];
173 /** The 64-bit view. */
174 uint64_t u64;
175} X86RFLAGS;
176/** Pointer to RFLAGS. */
177typedef X86RFLAGS *PX86RFLAGS;
178/** Pointer to const RFLAGS. */
179typedef const X86RFLAGS *PCX86RFLAGS;
180
181#endif /* !__ASSEMBLER__ */
182
183
184/** @name EFLAGS
185 * @{
186 */
187/** Bit 0 - CF - Carry flag - Status flag. */
188#define X86_EFL_CF RT_BIT_32(0)
189#define X86_EFL_CF_BIT 0
190/** Bit 1 - Reserved, reads as 1. */
191#define X86_EFL_1 RT_BIT_32(1)
192/** Bit 2 - PF - Parity flag - Status flag. */
193#define X86_EFL_PF RT_BIT_32(2)
194#define X86_EFL_PF_BIT 2
195/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
196#define X86_EFL_AF RT_BIT_32(4)
197#define X86_EFL_AF_BIT 4
198/** Bit 6 - ZF - Zero flag - Status flag. */
199#define X86_EFL_ZF RT_BIT_32(6)
200#define X86_EFL_ZF_BIT 6
201/** Bit 7 - SF - Signed flag - Status flag. */
202#define X86_EFL_SF RT_BIT_32(7)
203#define X86_EFL_SF_BIT 7
204/** Bit 8 - TF - Trap flag - System flag. */
205#define X86_EFL_TF RT_BIT_32(8)
206#define X86_EFL_TF_BIT 8
207/** Bit 9 - IF - Interrupt flag - System flag. */
208#define X86_EFL_IF RT_BIT_32(9)
209#define X86_EFL_IF_BIT 9
210/** Bit 10 - DF - Direction flag - Control flag. */
211#define X86_EFL_DF RT_BIT_32(10)
212#define X86_EFL_DF_BIT 10
213/** Bit 11 - OF - Overflow flag - Status flag. */
214#define X86_EFL_OF RT_BIT_32(11)
215#define X86_EFL_OF_BIT 11
216/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
217#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
218/** Bit 14 - NT - Nested task flag - System flag. */
219#define X86_EFL_NT RT_BIT_32(14)
220#define X86_EFL_NT_BIT 14
221/** Bit 16 - RF - Resume flag - System flag. */
222#define X86_EFL_RF RT_BIT_32(16)
223#define X86_EFL_RF_BIT 16
224/** Bit 17 - VM - Virtual 8086 mode - System flag. */
225#define X86_EFL_VM RT_BIT_32(17)
226#define X86_EFL_VM_BIT 17
227/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
228#define X86_EFL_AC RT_BIT_32(18)
229#define X86_EFL_AC_BIT 18
230/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
231#define X86_EFL_VIF RT_BIT_32(19)
232#define X86_EFL_VIF_BIT 19
233/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
234#define X86_EFL_VIP RT_BIT_32(20)
235#define X86_EFL_VIP_BIT 20
236/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
237#define X86_EFL_ID RT_BIT_32(21)
238#define X86_EFL_ID_BIT 21
239/** All live bits. */
240#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
241/** Read as 1 bits. */
242#define X86_EFL_RA1_MASK RT_BIT_32(1)
243/** Read as 0 bits, excluding bits 31:22.
244 * Bits 3, 5, 15, and 22 thru 31. */
245#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
246/** Read as 0 bits, excluding bits 31:22.
247 * Bits 3, 5 and 15. */
248#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
249/** IOPL shift. */
250#define X86_EFL_IOPL_SHIFT 12
251/** The IOPL level from the flags. */
252#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
253/** Bits restored by popf */
254#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
255 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
256/** Bits restored by popf */
257#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
258 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
259/** The status bits commonly updated by arithmetic instructions. */
260#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
261/** @} */
262
263
264#ifndef __ASSEMBLER__
265
266/** CPUID Feature information - ECX.
267 * CPUID query with EAX=1.
268 */
269# ifndef VBOX_FOR_DTRACE_LIB
270typedef struct X86CPUIDFEATECX
271{
272 /** Bit 0 - SSE3 - Supports SSE3 or not. */
273 unsigned u1SSE3 : 1;
274 /** Bit 1 - PCLMULQDQ. */
275 unsigned u1PCLMULQDQ : 1;
276 /** Bit 2 - DS Area 64-bit layout. */
277 unsigned u1DTE64 : 1;
278 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
279 unsigned u1Monitor : 1;
280 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
281 unsigned u1CPLDS : 1;
282 /** Bit 5 - VMX - Virtual Machine Technology. */
283 unsigned u1VMX : 1;
284 /** Bit 6 - SMX: Safer Mode Extensions. */
285 unsigned u1SMX : 1;
286 /** Bit 7 - EST - Enh. SpeedStep Tech. */
287 unsigned u1EST : 1;
288 /** Bit 8 - TM2 - Terminal Monitor 2. */
289 unsigned u1TM2 : 1;
290 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
291 unsigned u1SSSE3 : 1;
292 /** Bit 10 - CNTX-ID - L1 Context ID. */
293 unsigned u1CNTXID : 1;
294 /** Bit 11 - Reserved. */
295 unsigned u1Reserved1 : 1;
296 /** Bit 12 - FMA. */
297 unsigned u1FMA : 1;
298 /** Bit 13 - CX16 - CMPXCHG16B. */
299 unsigned u1CX16 : 1;
300 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
301 unsigned u1TPRUpdate : 1;
302 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
303 unsigned u1PDCM : 1;
304 /** Bit 16 - Reserved. */
305 unsigned u1Reserved2 : 1;
306 /** Bit 17 - PCID - Process-context identifiers. */
307 unsigned u1PCID : 1;
308 /** Bit 18 - Direct Cache Access. */
309 unsigned u1DCA : 1;
310 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
311 unsigned u1SSE4_1 : 1;
312 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
313 unsigned u1SSE4_2 : 1;
314 /** Bit 21 - x2APIC. */
315 unsigned u1x2APIC : 1;
316 /** Bit 22 - MOVBE - Supports MOVBE. */
317 unsigned u1MOVBE : 1;
318 /** Bit 23 - POPCNT - Supports POPCNT. */
319 unsigned u1POPCNT : 1;
320 /** Bit 24 - TSC-Deadline. */
321 unsigned u1TSCDEADLINE : 1;
322 /** Bit 25 - AES. */
323 unsigned u1AES : 1;
324 /** Bit 26 - XSAVE - Supports XSAVE. */
325 unsigned u1XSAVE : 1;
326 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
327 unsigned u1OSXSAVE : 1;
328 /** Bit 28 - AVX - Supports AVX instruction extensions. */
329 unsigned u1AVX : 1;
330 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
331 unsigned u1F16C : 1;
332 /** Bit 30 - RDRAND - Supports RDRAND. */
333 unsigned u1RDRAND : 1;
334 /** Bit 31 - Hypervisor present (we're a guest). */
335 unsigned u1HVP : 1;
336} X86CPUIDFEATECX;
337# else /* VBOX_FOR_DTRACE_LIB */
338typedef uint32_t X86CPUIDFEATECX;
339# endif /* VBOX_FOR_DTRACE_LIB */
340/** Pointer to CPUID Feature Information - ECX. */
341typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
342/** Pointer to const CPUID Feature Information - ECX. */
343typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
344
345
346/** CPUID Feature Information - EDX.
347 * CPUID query with EAX=1.
348 */
349# ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
350typedef struct X86CPUIDFEATEDX
351{
352 /** Bit 0 - FPU - x87 FPU on Chip. */
353 unsigned u1FPU : 1;
354 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
355 unsigned u1VME : 1;
356 /** Bit 2 - DE - Debugging extensions. */
357 unsigned u1DE : 1;
358 /** Bit 3 - PSE - Page Size Extension. */
359 unsigned u1PSE : 1;
360 /** Bit 4 - TSC - Time Stamp Counter. */
361 unsigned u1TSC : 1;
362 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
363 unsigned u1MSR : 1;
364 /** Bit 6 - PAE - Physical Address Extension. */
365 unsigned u1PAE : 1;
366 /** Bit 7 - MCE - Machine Check Exception. */
367 unsigned u1MCE : 1;
368 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
369 unsigned u1CX8 : 1;
370 /** Bit 9 - APIC - APIC On-Chip. */
371 unsigned u1APIC : 1;
372 /** Bit 10 - Reserved. */
373 unsigned u1Reserved1 : 1;
374 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
375 unsigned u1SEP : 1;
376 /** Bit 12 - MTRR - Memory Type Range Registers. */
377 unsigned u1MTRR : 1;
378 /** Bit 13 - PGE - PTE Global Bit. */
379 unsigned u1PGE : 1;
380 /** Bit 14 - MCA - Machine Check Architecture. */
381 unsigned u1MCA : 1;
382 /** Bit 15 - CMOV - Conditional Move Instructions. */
383 unsigned u1CMOV : 1;
384 /** Bit 16 - PAT - Page Attribute Table. */
385 unsigned u1PAT : 1;
386 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
387 unsigned u1PSE36 : 1;
388 /** Bit 18 - PSN - Processor Serial Number. */
389 unsigned u1PSN : 1;
390 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
391 unsigned u1CLFSH : 1;
392 /** Bit 20 - Reserved. */
393 unsigned u1Reserved2 : 1;
394 /** Bit 21 - DS - Debug Store. */
395 unsigned u1DS : 1;
396 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
397 unsigned u1ACPI : 1;
398 /** Bit 23 - MMX - Intel MMX 'Technology'. */
399 unsigned u1MMX : 1;
400 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401 unsigned u1FXSR : 1;
402 /** Bit 25 - SSE - SSE Support. */
403 unsigned u1SSE : 1;
404 /** Bit 26 - SSE2 - SSE2 Support. */
405 unsigned u1SSE2 : 1;
406 /** Bit 27 - SS - Self Snoop. */
407 unsigned u1SS : 1;
408 /** Bit 28 - HTT - Hyper-Threading Technology. */
409 unsigned u1HTT : 1;
410 /** Bit 29 - TM - Thermal Monitor. */
411 unsigned u1TM : 1;
412 /** Bit 30 - Reserved - . */
413 unsigned u1Reserved3 : 1;
414 /** Bit 31 - PBE - Pending Break Enabled. */
415 unsigned u1PBE : 1;
416} X86CPUIDFEATEDX;
417# else /* VBOX_FOR_DTRACE_LIB */
418typedef uint32_t X86CPUIDFEATEDX;
419# endif /* VBOX_FOR_DTRACE_LIB */
420/** Pointer to CPUID Feature Information - EDX. */
421typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
422/** Pointer to const CPUID Feature Information - EDX. */
423typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
424
425#endif /* !__ASSEMBLER__ */
426
427
428/** @name CPUID Vendor information.
429 * CPUID query with EAX=0.
430 * @{
431 */
432#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
433#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
434#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
435
436#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
437#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
438#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
439
440#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
441#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
442#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
443
444#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
445#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
446#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
447
448#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
449#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
450#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
451/** @} */
452
453
454/** @name CPUID Feature information.
455 * CPUID query with EAX=1.
456 * @{
457 */
458/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
459#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
460/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
461#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
462/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
463#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
464/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
465#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
466/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
467#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
468/** ECX Bit 5 - VMX - Virtual Machine Technology. */
469#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
470/** ECX Bit 6 - SMX - Safer Mode Extensions. */
471#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
472/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
473#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
474/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
475#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
476/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
477#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
478/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
479#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
480/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
481 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
482#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
483/** ECX Bit 12 - FMA. */
484#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
485/** ECX Bit 13 - CX16 - CMPXCHG16B. */
486#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
487/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
489/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
490#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
491/** ECX Bit 17 - PCID - Process-context identifiers. */
492#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
493/** ECX Bit 18 - DCA - Direct Cache Access. */
494#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
495/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
496#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
497/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
498#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
499/** ECX Bit 21 - x2APIC support. */
500#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
501/** ECX Bit 22 - MOVBE instruction. */
502#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
503/** ECX Bit 23 - POPCNT instruction. */
504#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
505/** ECX Bir 24 - TSC-Deadline. */
506#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
507/** ECX Bit 25 - AES instructions. */
508#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
509/** ECX Bit 26 - XSAVE instruction. */
510#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
511/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
512#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
513/** ECX Bit 28 - AVX. */
514#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
515/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
516#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
517/** ECX Bit 30 - RDRAND instruction. */
518#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
519/** ECX Bit 31 - Hypervisor Present (software only). */
520#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
521
522
523/** Bit 0 - FPU - x87 FPU on Chip. */
524#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
525/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
526#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
527/** Bit 2 - DE - Debugging extensions. */
528#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
529/** Bit 3 - PSE - Page Size Extension. */
530#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
531#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
532/** Bit 4 - TSC - Time Stamp Counter. */
533#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
534/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
535#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
536/** Bit 6 - PAE - Physical Address Extension. */
537#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
538#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
539/** Bit 7 - MCE - Machine Check Exception. */
540#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
541/** Bit 8 - CX8 - CMPXCHG8B instruction. */
542#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
543/** Bit 9 - APIC - APIC On-Chip. */
544#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
545/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
546#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
547/** Bit 12 - MTRR - Memory Type Range Registers. */
548#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
549/** Bit 13 - PGE - PTE Global Bit. */
550#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
551/** Bit 14 - MCA - Machine Check Architecture. */
552#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
553/** Bit 15 - CMOV - Conditional Move Instructions. */
554#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
555/** Bit 16 - PAT - Page Attribute Table. */
556#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
557/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
558#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
559/** Bit 18 - PSN - Processor Serial Number. */
560#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
561/** Bit 19 - CLFSH - CLFLUSH Instruction. */
562#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
563/** Bit 21 - DS - Debug Store. */
564#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
565/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
566#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
567/** Bit 23 - MMX - Intel MMX Technology. */
568#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
569/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
570#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
571/** Bit 25 - SSE - SSE Support. */
572#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
573/** Bit 26 - SSE2 - SSE2 Support. */
574#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
575/** Bit 27 - SS - Self Snoop. */
576#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
577/** Bit 28 - HTT - Hyper-Threading Technology. */
578#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
579/** Bit 29 - TM - Therm. Monitor. */
580#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
581/** Bit 31 - PBE - Pending Break Enabled. */
582#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
583/** @} */
584
585/** @name CPUID mwait/monitor information.
586 * CPUID query with EAX=5.
587 * @{
588 */
589/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
590#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
591/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
592#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
593/** @} */
594
595
596/** @name CPUID Thermal and Power Management information.
597 * Generally Intel only unless noted otherwise.
598 * CPUID query with EAX=5. @{
599 */
600/** EAX Bit 0 - DTS - Supports Digital Temperature Sensor. */
601#define X86_CPUID_POWER_EAX_DTS RT_BIT_32(0)
602/** EAX Bit 1 - TURBOBOOST - Intel Turbo Boost available. */
603#define X86_CPUID_POWER_EAX_TURBOBOOST RT_BIT_32(1)
604/** EAX Bit 2 - ARAT - Always Running APIC Timer. Intel and AMD. */
605#define X86_CPUID_POWER_EAX_ARAT RT_BIT_32(2)
606/** EAX Bit 4 - PLN - Power Limit Notifications supported. */
607#define X86_CPUID_POWER_EAX_PLN RT_BIT_32(4)
608/** EAX Bit 5 - ECMD - Clock modulation duty cycle extension supported. */
609#define X86_CPUID_POWER_EAX_ECMD RT_BIT_32(5)
610/** EAX Bit 6 - PTM - Package Thermal Management supported. */
611#define X86_CPUID_POWER_EAX_PTM RT_BIT_32(6)
612/** EAX Bit 7 - HWP - HWP base MSRs supported. */
613#define X86_CPUID_POWER_EAX_HWP RT_BIT_32(7)
614/** EAX Bit 8 - HWP_NOTIFY - HWP notification MSR supported. */
615#define X86_CPUID_POWER_EAX_HWP_NOTIFY RT_BIT_32(8)
616/** EAX Bit 9 - HWP_ACT_WIN - HWP activity window MSR bits supported. */
617#define X86_CPUID_POWER_EAX_HWP_ACT_WIN RT_BIT_32(9)
618/** EAX Bit 10 - HWP_NRG_PP - HWP energy performae preference MSR bits supported. */
619#define X86_CPUID_POWER_EAX_HWP_NRG_PP RT_BIT_32(10)
620/** EAX Bit 11 - HWP_PLR - HWP package level request MSR supported. */
621#define X86_CPUID_POWER_EAX_HWP_PLR RT_BIT_32(11)
622/** EAX Bit 13 - HDC - HDC base MSRs supported. */
623#define X86_CPUID_POWER_EAX_HDC RT_BIT_32(13)
624/** EAX Bit 14 - TBM30 - Turbo Boost Max Technology 3.0 supported. */
625#define X86_CPUID_POWER_EAX_TBM30 RT_BIT_32(14)
626/** EAX Bit 15 - HWP_HPC - HWP Highest Performance change supported. */
627#define X86_CPUID_POWER_EAX_HWP_HPC RT_BIT_32(15)
628/** EAX Bit 16 - HWP_PECI - HWP PECI override supported. */
629#define X86_CPUID_POWER_EAX_HWP_PECI RT_BIT_32(16)
630/** EAX Bit 17 - HWP_FLEX - Flexible HWP supported. */
631#define X86_CPUID_POWER_EAX_HWP_FLEX RT_BIT_32(17)
632
633/** ECX Bit 1 - HCFC - Hardware Coordintion Feedback Capability supported. Intel and AMD. */
634#define X86_CPUID_POWER_ECX_HCFC RT_BIT_32(0)
635/** @} */
636
637
638/** @name CPUID Structured Extended Feature information.
639 * CPUID query with EAX=7.
640 * @{
641 */
642/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
643#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
644/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
645#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
646/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
647#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
648/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
649#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
650/** EBX Bit 4 - HLE - Hardware Lock Elision. */
651#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
652/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
653#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
654/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
655#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
656/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
657#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
658/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
659#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
660/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
661#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
662/** EBX Bit 10 - INVPCID - Supports INVPCID. */
663#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
664/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
665#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
666/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
667#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
668/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
669#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
670/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
671#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
672/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
673#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
674/** EBX Bit 16 - AVX512F - Supports AVX512F. */
675#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
676/** EBX Bit 18 - RDSEED - Supports RDSEED. */
677#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
678/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
679#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
680/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
681#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
682/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
683#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
684/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
685#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
686/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
687#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
688/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
689#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
690/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
691#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
692/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
693#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
694
695/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
696#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
697/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
698#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
699/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
700#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
701/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
702#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
703/** ECX Bit 7 - CET_SS - Supports CET shadow stack features. */
704#define X86_CPUID_STEXT_FEATURE_ECX_CET_SS RT_BIT_32(7)
705/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
706#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
707/** ECX Bit 22 - RDPID - Support pread process ID. */
708#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
709/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
710#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
711
712/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
713#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
714/** EDX Bit 20 - CET_IBT - Supports CET indirect branch tracking features. */
715#define X86_CPUID_STEXT_FEATURE_EDX_CET_IBT RT_BIT_32(20)
716/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
717 * IBPB command in IA32_PRED_CMD. */
718#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
719/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
720#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
721/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
722#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
723/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
724#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
725/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
726#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP RT_BIT_32(30)
727/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
728#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
729
730/** @} */
731
732
733/** @name CPUID Extended Feature information.
734 * CPUID query with EAX=0x80000001.
735 * @{
736 */
737/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
738#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
739
740/** EDX Bit 11 - SYSCALL/SYSRET. */
741#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
742/** EDX Bit 20 - No-Execute/Execute-Disable. */
743#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
744/** EDX Bit 26 - 1 GB large page. */
745#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
746/** EDX Bit 27 - RDTSCP. */
747#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
748/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
749#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
750/** @}*/
751
752/** @name CPUID AMD Feature information.
753 * CPUID query with EAX=0x80000001.
754 * @{
755 */
756/** Bit 0 - FPU - x87 FPU on Chip. */
757#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
758/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
759#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
760/** Bit 2 - DE - Debugging extensions. */
761#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
762/** Bit 3 - PSE - Page Size Extension. */
763#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
764/** Bit 4 - TSC - Time Stamp Counter. */
765#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
766/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
767#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
768/** Bit 6 - PAE - Physical Address Extension. */
769#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
770/** Bit 7 - MCE - Machine Check Exception. */
771#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
772/** Bit 8 - CX8 - CMPXCHG8B instruction. */
773#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
774/** Bit 9 - APIC - APIC On-Chip. */
775#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
776/** Bit 12 - MTRR - Memory Type Range Registers. */
777#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
778/** Bit 13 - PGE - PTE Global Bit. */
779#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
780/** Bit 14 - MCA - Machine Check Architecture. */
781#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
782/** Bit 15 - CMOV - Conditional Move Instructions. */
783#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
784/** Bit 16 - PAT - Page Attribute Table. */
785#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
786/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
787#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
788/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
789#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
790/** Bit 23 - MMX - Intel MMX Technology. */
791#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
792/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
793#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
794/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
795#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
796/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
797#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
798/** Bit 31 - 3DNOW - AMD 3DNow. */
799#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
800
801/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
802#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
803/** Bit 2 - SVM - AMD VM extensions. */
804#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
805/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
806#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
807/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
808#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
809/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
810#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
811/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
812#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
813/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
814#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
815/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
816#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
817/** Bit 9 - OSVW - AMD OS visible workaround. */
818#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
819/** Bit 10 - IBS - Instruct based sampling. */
820#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
821/** Bit 11 - XOP - Extended operation support (see APM6). */
822#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
823/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
824#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
825/** Bit 13 - WDT - AMD Watchdog timer support. */
826#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
827/** Bit 15 - LWP - Lightweight profiling support. */
828#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
829/** Bit 16 - FMA4 - Four operand FMA instruction support. */
830#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
831/** Bit 19 - NodeId - Indicates support for
832 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
833#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
834/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
835#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
836/** Bit 22 - TopologyExtensions - . */
837#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
838/** @} */
839
840
841/** @name CPUID AMD Feature information.
842 * CPUID query with EAX=0x80000007.
843 * @{
844 */
845/** Bit 0 - TS - Temperature Sensor. */
846#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
847/** Bit 1 - FID - Frequency ID Control. */
848#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
849/** Bit 2 - VID - Voltage ID Control. */
850#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
851/** Bit 3 - TTP - THERMTRIP. */
852#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
853/** Bit 4 - TM - Hardware Thermal Control. */
854#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
855/** Bit 5 - STC - Software Thermal Control. */
856#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
857/** Bit 6 - MC - 100 Mhz Multiplier Control. */
858#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
859/** Bit 7 - HWPSTATE - Hardware P-State Control. */
860#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
861/** Bit 8 - TSCINVAR - TSC Invariant. */
862#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
863/** Bit 9 - CPB - TSC Invariant. */
864#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
865/** Bit 10 - EffFreqRO - MPERF/APERF. */
866#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
867/** Bit 11 - PFI - Processor feedback interface (see EAX). */
868#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
869/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
870#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
871/** @} */
872
873
874/** @name CPUID AMD extended feature extensions ID (EBX).
875 * CPUID query with EAX=0x80000008.
876 * @{
877 */
878/** Bit 0 - CLZERO - Clear zero instruction. */
879#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
880/** Bit 1 - IRPerf - Instructions retired count support. */
881#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
882/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
883#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
884/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
885#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
886/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
887#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
888/* AMD pipeline length: 9 feature bits ;-) */
889/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
890#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
891/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
892#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
893/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
894#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
895/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
896#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
897/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
898#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
899/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
900#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
901/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
902#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
903/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
904#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
905/** Bit 26 - Speculative Store Bypass Disable not required. */
906#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
907/** @} */
908
909
910/** @name CPUID AMD SVM Feature information.
911 * CPUID query with EAX=0x8000000a.
912 * @{
913 */
914/** Bit 0 - NP - Nested Paging supported. */
915#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
916/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
917#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
918/** Bit 2 - SVML - SVM locking bit supported. */
919#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
920/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
921#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
922/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
923#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
924/** Bit 5 - VmcbClean - Support VMCB clean bits. */
925#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
926/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
927 * VMCB.TLB_Control is supported. */
928#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
929/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
930#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
931/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
932#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
933/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
934 * intercept filter cycle count threshold. */
935#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
936/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
937#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
938/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
939#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
940/** Bit 16 - VGIF - Supports virtualized GIF. */
941#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
942/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
943#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
944/** Bit 18 - X2AVIC - Supports Advanced Virtual Interrupt Controller in x2APIC
945 * mode. */
946#define X86_CPUID_SVM_FEATURE_EDX_X2AVIC RT_BIT(18)
947/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
948#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
949/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
950#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
951/** Bit 21 - ROGPT - Read-Only Guest Page Table. */
952#define X86_CPUID_SVM_FEATURE_EDX_ROGPT RT_BIT(21)
953/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
954#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
955/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
956#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
957/** Bit 25 - TlbiCtl - Supports virtual NMIs. */
958#define X86_CPUID_SVM_FEATURE_EDX_VNMI RT_BIT(25)
959/** Bit 26 - TlbiCtl - Supports IBS virtualization. */
960#define X86_CPUID_SVM_FEATURE_EDX_IBS_VIRT RT_BIT(26)
961/** Bit 27 - TlbiCtl - Supports extended LVT AVIC access changes. */
962#define X86_CPUID_SVM_FEATURE_EDX_EXT_LVT_AVIC_ACCESS_CHG RT_BIT(27)
963/** Bit 28 - TlbiCtl - Supports guest VMCB address check. */
964#define X86_CPUID_SVM_FEATURE_EDX_NST_VIRT_VMCB_ADDR_CHK RT_BIT(28)
965/** Bit 29 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
966#define X86_CPUID_SVM_FEATURE_EDX_BUS_LOCK_THRESHOLD RT_BIT(29)
967
968/** @} */
969
970
971/** @name CR0
972 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
973 * reserved flags.
974 * @{ */
975/** Bit 0 - PE - Protection Enabled */
976#define X86_CR0_PE RT_BIT_32(0)
977#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
978#define X86_CR0_PE_BIT 0
979/** Bit 1 - MP - Monitor Coprocessor */
980#define X86_CR0_MP RT_BIT_32(1)
981#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
982#define X86_CR0_MP_BIT 1
983/** Bit 2 - EM - Emulation. */
984#define X86_CR0_EM RT_BIT_32(2)
985#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
986#define X86_CR0_EM_BIT 2
987/** Bit 3 - TS - Task Switch. */
988#define X86_CR0_TS RT_BIT_32(3)
989#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
990#define X86_CR0_TS_BIT 3
991/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
992#define X86_CR0_ET RT_BIT_32(4)
993#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
994#define X86_CR0_ET_BIT 4
995/** Bit 5 - NE - Numeric error (486+). */
996#define X86_CR0_NE RT_BIT_32(5)
997#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
998#define X86_CR0_NE_BIT 5
999/** Bit 16 - WP - Write Protect (486+). */
1000#define X86_CR0_WP RT_BIT_32(16)
1001#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
1002#define X86_CR0_WP_BIT 16
1003/** Bit 18 - AM - Alignment Mask (486+). */
1004#define X86_CR0_AM RT_BIT_32(18)
1005#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
1006#define X86_CR0_AM_BIT 18
1007/** Bit 29 - NW - Not Write-though (486+). */
1008#define X86_CR0_NW RT_BIT_32(29)
1009#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
1010#define X86_CR0_NW_BIT 29
1011/** Bit 30 - WP - Cache Disable (486+). */
1012#define X86_CR0_CD RT_BIT_32(30)
1013#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
1014#define X86_CR0_CD_BIT 30
1015/** Bit 31 - PG - Paging. */
1016#define X86_CR0_PG RT_BIT_32(31)
1017#define X86_CR0_PAGING RT_BIT_32(31)
1018#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
1019/** @} */
1020
1021
1022/** @name CR3
1023 * @{ */
1024/** Bit 3 - PWT - Page-level Writes Transparent. */
1025#define X86_CR3_PWT RT_BIT_32(3)
1026#define X86_CR3_PWT_BIT 3
1027/** Bit 4 - PCD - Page-level Cache Disable. */
1028#define X86_CR3_PCD RT_BIT_32(4)
1029#define X86_CR3_PCD_BIT 4
1030/** Bits 12-31 - - Page directory page number. */
1031#define X86_CR3_PAGE_MASK (0xfffff000)
1032/** Bits 5-31 - - PAE Page directory page number. */
1033#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
1034/** Bits 12-51 - - AMD64 PML4 page number.
1035 * @note This is a maxed out mask, the actual acceptable CR3 value can
1036 * be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1037#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
1038/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
1039 * @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
1040 * be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
1041#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
1042/** @} */
1043
1044
1045/** @name CR4
1046 * @{ */
1047/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
1048#define X86_CR4_VME RT_BIT_32(0)
1049#define X86_CR4_VME_BIT 0
1050/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
1051#define X86_CR4_PVI RT_BIT_32(1)
1052#define X86_CR4_PVI_BIT 1
1053/** Bit 2 - TSD - Time Stamp Disable. */
1054#define X86_CR4_TSD RT_BIT_32(2)
1055#define X86_CR4_TSD_BIT 2
1056/** Bit 3 - DE - Debugging Extensions. */
1057#define X86_CR4_DE RT_BIT_32(3)
1058#define X86_CR4_DE_BIT 3
1059/** Bit 4 - PSE - Page Size Extension. */
1060#define X86_CR4_PSE RT_BIT_32(4)
1061#define X86_CR4_PSE_BIT 4
1062/** Bit 5 - PAE - Physical Address Extension. */
1063#define X86_CR4_PAE RT_BIT_32(5)
1064#define X86_CR4_PAE_BIT 5
1065/** Bit 6 - MCE - Machine-Check Enable. */
1066#define X86_CR4_MCE RT_BIT_32(6)
1067#define X86_CR4_MCE_BIT 6
1068/** Bit 7 - PGE - Page Global Enable. */
1069#define X86_CR4_PGE RT_BIT_32(7)
1070#define X86_CR4_PGE_BIT 7
1071/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
1072#define X86_CR4_PCE RT_BIT_32(8)
1073#define X86_CR4_PCE_BIT 8
1074/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
1075#define X86_CR4_OSFXSR RT_BIT_32(9)
1076#define X86_CR4_OSFXSR_BIT 9
1077/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
1078#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
1079#define X86_CR4_OSXMMEEXCPT_BIT 10
1080/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
1081#define X86_CR4_UMIP RT_BIT_32(11)
1082#define X86_CR4_UMIP_BIT 11
1083/** Bit 13 - VMXE - VMX mode is enabled. */
1084#define X86_CR4_VMXE RT_BIT_32(13)
1085#define X86_CR4_VMXE_BIT 13
1086/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
1087#define X86_CR4_SMXE RT_BIT_32(14)
1088#define X86_CR4_SMXE_BIT 14
1089/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
1090#define X86_CR4_FSGSBASE RT_BIT_32(16)
1091#define X86_CR4_FSGSBASE_BIT 16
1092/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
1093#define X86_CR4_PCIDE RT_BIT_32(17)
1094#define X86_CR4_PCIDE_BIT 17
1095/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
1096 * extended states. */
1097#define X86_CR4_OSXSAVE RT_BIT_32(18)
1098#define X86_CR4_OSXSAVE_BIT 18
1099/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
1100#define X86_CR4_SMEP RT_BIT_32(20)
1101#define X86_CR4_SMEP_BIt 20
1102/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
1103#define X86_CR4_SMAP RT_BIT_32(21)
1104#define X86_CR4_SMAP_BIT 21
1105/** Bit 22 - PKE - Protection Key Enable. */
1106#define X86_CR4_PKE RT_BIT_32(22)
1107#define X86_CR4_PKE_BIT 22
1108/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
1109#define X86_CR4_CET RT_BIT_32(23)
1110#define X86_CR4_CET_BIT 23
1111/** @} */
1112
1113
1114/** @name DR6
1115 * @{ */
1116/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1117#define X86_DR6_B0 RT_BIT_32(0)
1118/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1119#define X86_DR6_B1 RT_BIT_32(1)
1120/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1121#define X86_DR6_B2 RT_BIT_32(2)
1122/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1123#define X86_DR6_B3 RT_BIT_32(3)
1124/** Mask of all the Bx bits. */
1125#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1126/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1127#define X86_DR6_BD RT_BIT_32(13)
1128/** Bit 14 - BS - Single step */
1129#define X86_DR6_BS RT_BIT_32(14)
1130/** Bit 15 - BT - Task switch. (TSS T bit.) */
1131#define X86_DR6_BT RT_BIT_32(15)
1132/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1133#define X86_DR6_RTM RT_BIT_32(16)
1134/** Value of DR6 after powerup/reset. */
1135#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1136/** Bits which must be 1s in DR6. */
1137#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1138/** Bits which must be 1s in DR6, when RTM is supported. */
1139#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1140/** Bits which must be 0s in DR6. */
1141#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1142/** Bits which must be 0s on writes to DR6. */
1143#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1144/** @} */
1145
1146/** Get the DR6.Bx bit for a the given breakpoint. */
1147#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1148
1149
1150/** @name DR7
1151 * @{ */
1152/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1153#define X86_DR7_L0 RT_BIT_32(0)
1154/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1155#define X86_DR7_G0 RT_BIT_32(1)
1156/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1157#define X86_DR7_L1 RT_BIT_32(2)
1158/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1159#define X86_DR7_G1 RT_BIT_32(3)
1160/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1161#define X86_DR7_L2 RT_BIT_32(4)
1162/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1163#define X86_DR7_G2 RT_BIT_32(5)
1164/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1165#define X86_DR7_L3 RT_BIT_32(6)
1166/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1167#define X86_DR7_G3 RT_BIT_32(7)
1168/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1169#define X86_DR7_LE RT_BIT_32(8)
1170/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1171#define X86_DR7_GE RT_BIT_32(9)
1172
1173/** L0, L1, L2, and L3. */
1174#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1175/** L0, L1, L2, and L3. */
1176#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1177
1178/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1179 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1180#define X86_DR7_RTM RT_BIT_32(11)
1181/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1182 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1183 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1184 * instruction is executed.
1185 * @see http://www.rcollins.org/secrets/DR7.html */
1186#define X86_DR7_ICE_IR RT_BIT_32(12)
1187/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1188 * any DR register is accessed. */
1189#define X86_DR7_GD RT_BIT_32(13)
1190/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1191 * Pentium. */
1192#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1193/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1194#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1195/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1196#define X86_DR7_RW0_MASK (3 << 16)
1197/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1198#define X86_DR7_LEN0_MASK (3 << 18)
1199/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1200#define X86_DR7_RW1_MASK (3 << 20)
1201/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1202#define X86_DR7_LEN1_MASK (3 << 22)
1203/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1204#define X86_DR7_RW2_MASK (3 << 24)
1205/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1206#define X86_DR7_LEN2_MASK (3 << 26)
1207/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1208#define X86_DR7_RW3_MASK (3 << 28)
1209/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1210#define X86_DR7_LEN3_MASK (3 << 30)
1211
1212/** Bits which reads as 1s. */
1213#define X86_DR7_RA1_MASK RT_BIT_32(10)
1214/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1215#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1216/** Bits which must be 0s when writing to DR7. */
1217#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1218
1219/** Calcs the L bit of Nth breakpoint.
1220 * @param iBp The breakpoint number [0..3].
1221 */
1222#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1223
1224/** Calcs the G bit of Nth breakpoint.
1225 * @param iBp The breakpoint number [0..3].
1226 */
1227#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1228
1229/** Calcs the L and G bits of Nth breakpoint.
1230 * @param iBp The breakpoint number [0..3].
1231 */
1232#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1233
1234/** @name Read/Write values.
1235 * @{ */
1236/** Break on instruction fetch only. */
1237#define X86_DR7_RW_EO UINT32_C(0)
1238/** Break on write only. */
1239#define X86_DR7_RW_WO UINT32_C(1)
1240/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1241#define X86_DR7_RW_IO UINT32_C(2)
1242/** Break on read or write (but not instruction fetches). */
1243#define X86_DR7_RW_RW UINT32_C(3)
1244/** @} */
1245
1246/** Shifts a X86_DR7_RW_* value to its right place.
1247 * @param iBp The breakpoint number [0..3].
1248 * @param fRw One of the X86_DR7_RW_* value.
1249 */
1250#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1251
1252/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1253 * one of the X86_DR7_RW_XXX constants).
1254 *
1255 * @returns X86_DR7_RW_XXX
1256 * @param uDR7 DR7 value
1257 * @param iBp The breakpoint number [0..3].
1258 */
1259#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1260
1261/** R/W0, R/W1, R/W2, and R/W3. */
1262#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1263
1264#ifndef VBOX_FOR_DTRACE_LIB
1265/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1266 * @note This does not check if it's enabled. */
1267# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1268/** Checks if an instruction breakpoint is enabled and configured correctly.
1269 * @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1270# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1271 ( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1272/** Checks if there are any instruction fetch breakpoint types configured in the
1273 * RW and LEN registers.
1274 * @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1275# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1276 ( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1277 || (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1278 || (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1279 || (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1280
1281/** Checks if there are any I/O breakpoint types configured in the RW
1282 * registers. Does NOT check if these are enabled, sorry. */
1283# define X86_DR7_ANY_RW_IO(uDR7) \
1284 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1285 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1286AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1287AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1288AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1289AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1290AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1291AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1292AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1293AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1294AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1295
1296#endif /* !VBOX_FOR_DTRACE_LIB */
1297
1298/** @name Length values.
1299 * @{ */
1300#define X86_DR7_LEN_BYTE UINT32_C(0)
1301#define X86_DR7_LEN_WORD UINT32_C(1)
1302#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1303#define X86_DR7_LEN_DWORD UINT32_C(3)
1304/** @} */
1305
1306/** Shifts a X86_DR7_LEN_* value to its right place.
1307 * @param iBp The breakpoint number [0..3].
1308 * @param cb One of the X86_DR7_LEN_* values.
1309 */
1310#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1311
1312/** Fetch the breakpoint length bits from the DR7 value.
1313 * @param uDR7 DR7 value
1314 * @param iBp The breakpoint number [0..3].
1315 */
1316#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1317
1318/** Mask used to check if any breakpoints are enabled. */
1319#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1320
1321/** LEN0, LEN1, LEN2, and LEN3. */
1322#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1323/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1324#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1325
1326/** Value of DR7 after powerup/reset. */
1327#define X86_DR7_INIT_VAL 0x400
1328/** @} */
1329
1330
1331/** @name Machine Specific Registers
1332 * @{
1333 */
1334/** Machine check address register (P5). */
1335#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1336/** Machine check type register (P5). */
1337#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1338/** Time Stamp Counter. */
1339#define MSR_IA32_TSC 0x10
1340#define MSR_IA32_CESR UINT32_C(0x00000011)
1341#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1342#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1343
1344#define MSR_IA32_PLATFORM_ID 0x17
1345
1346#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1347# define MSR_IA32_APICBASE 0x1b
1348/** Local APIC enabled. */
1349# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1350/** X2APIC enabled (requires the EN bit to be set). */
1351# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1352/** The processor is the boot strap processor (BSP). */
1353# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1354/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1355 * width. */
1356# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1357/** The default physical base address of the APIC. */
1358# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1359/** Gets the physical base address from the MSR. */
1360# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1361#endif
1362
1363/** Memory Control (Intel-specific). */
1364#define MSR_MEMORY_CTRL 0x33
1365/** Memory Control - UC-store throttle. */
1366#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE RT_BIT_64(27)
1367/** Memory Control - UC-lock disable. */
1368#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE RT_BIT_64(28)
1369/** Memory Control - Split-lock disable. */
1370#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE RT_BIT_64(29)
1371
1372/** Undocumented intel MSR for reporting thread and core counts.
1373 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1374 * first 16 bits is the thread count. The next 16 bits the core count, except
1375 * on Westmere where it seems it's only the next 4 bits for some reason. */
1376#define MSR_CORE_THREAD_COUNT 0x35
1377
1378/** CPU Feature control. */
1379#define MSR_IA32_FEATURE_CONTROL 0x3A
1380/** Feature control - Lock MSR from writes (R/W0). */
1381#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1382/** Feature control - Enable VMX inside SMX operation (R/WL). */
1383#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1384/** Feature control - Enable VMX outside SMX operation (R/WL). */
1385#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1386/** Feature control - SENTER local functions enable (R/WL). */
1387#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1388#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1389#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1390#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1391#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1392#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1393#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1394/** Feature control - SENTER global enable (R/WL). */
1395#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1396/** Feature control - SGX launch control enable (R/WL). */
1397#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1398/** Feature control - SGX global enable (R/WL). */
1399#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1400/** Feature control - LMCE on (R/WL). */
1401#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1402
1403/** Per-processor TSC adjust MSR. */
1404#define MSR_IA32_TSC_ADJUST 0x3B
1405
1406/** Spectre control register.
1407 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1408#define MSR_IA32_SPEC_CTRL 0x48
1409/** IBRS - Indirect branch restricted speculation. */
1410#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1411/** STIBP - Single thread indirect branch predictors. */
1412#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1413/** SSBD - Speculative Store Bypass Disable. */
1414#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1415
1416/** Prediction command register.
1417 * Write only, logical processor scope, no state since write only. */
1418#define MSR_IA32_PRED_CMD 0x49
1419/** IBPB - Indirect branch prediction barrie when written as 1. */
1420#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1421
1422/** BIOS update trigger (microcode update). */
1423#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1424
1425/** BIOS update signature (microcode). */
1426#define MSR_IA32_BIOS_SIGN_ID 0x8B
1427
1428/** SMM monitor control. */
1429#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1430/** SMM control - Valid. */
1431#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1432/** SMM control - VMXOFF unblocks SMI. */
1433#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1434/** SMM control - MSEG base physical address. */
1435#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1436
1437/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1438#define MSR_IA32_SMBASE 0x9E
1439
1440/** General performance counter no. 0. */
1441#define MSR_IA32_PMC0 0xC1
1442/** General performance counter no. 1. */
1443#define MSR_IA32_PMC1 0xC2
1444/** General performance counter no. 2. */
1445#define MSR_IA32_PMC2 0xC3
1446/** General performance counter no. 3. */
1447#define MSR_IA32_PMC3 0xC4
1448/** General performance counter no. 4. */
1449#define MSR_IA32_PMC4 0xC5
1450/** General performance counter no. 5. */
1451#define MSR_IA32_PMC5 0xC6
1452/** General performance counter no. 6. */
1453#define MSR_IA32_PMC6 0xC7
1454/** General performance counter no. 7. */
1455#define MSR_IA32_PMC7 0xC8
1456
1457/** Nehalem power control. */
1458#define MSR_IA32_PLATFORM_INFO 0xCE
1459
1460/** Core Capabilities (Intel-specific). */
1461#define MSR_IA32_CORE_CAPABILITIES 0xCF
1462/** STLB QoS feature supported. */
1463#define MSR_IA32_CORE_CAP_STLB_QOS RT_BIT_64(0)
1464/** FUSA feature supported. */
1465#define MSR_IA32_CORE_CAP_FUSA RT_BIT_64(2)
1466/** RSM instruction only allowed in CPL 0. */
1467#define MSR_IA32_CORE_CAP_RSM_CPL0 RT_BIT_64(3)
1468/** UC lock disable supported. */
1469#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE RT_BIT_64(4)
1470/** Split-lock disable supported. */
1471#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE RT_BIT_64(5)
1472/** Snoop filter QoS Mask MSRs supported. */
1473#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS RT_BIT_64(6)
1474/** UC store throttling supported. */
1475#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE RT_BIT_64(7)
1476
1477/** Get FSB clock status (Intel-specific). */
1478#define MSR_IA32_FSB_CLOCK_STS 0xCD
1479
1480/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1481#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1482
1483/** C0 Maximum Frequency Clock Count */
1484#define MSR_IA32_MPERF 0xE7
1485/** C0 Actual Frequency Clock Count */
1486#define MSR_IA32_APERF 0xE8
1487
1488/** MTRR Capabilities. */
1489#define MSR_IA32_MTRR_CAP 0xFE
1490/** Bits 0-7 - VCNT - Variable range registers count. */
1491#define MSR_IA32_MTRR_CAP_VCNT_MASK UINT64_C(0x00000000000000ff)
1492/** Bit 8 - FIX - Fixed range registers supported. */
1493#define MSR_IA32_MTRR_CAP_FIX RT_BIT_64(8)
1494/** Bit 10 - WC - Write-Combining memory type supported. */
1495#define MSR_IA32_MTRR_CAP_WC RT_BIT_64(10)
1496/** Bit 11 - SMRR - System Management Range Register supported. */
1497#define MSR_IA32_MTRR_CAP_SMRR RT_BIT_64(11)
1498/** Bit 12 - PRMRR - Processor Reserved Memory Range Register supported. */
1499#define MSR_IA32_MTRR_CAP_PRMRR RT_BIT_64(12)
1500
1501
1502#ifndef __ASSEMBLER__
1503/**
1504 * Variable-range MTRR MSR pair.
1505 */
1506typedef struct X86MTRRVAR
1507{
1508 uint64_t MtrrPhysBase; /**< IA32_MTRR_PHYSBASEn */
1509 uint64_t MtrrPhysMask; /**< IA32_MTRR_PHYSMASKn */
1510} X86MTRRVAR;
1511# ifndef VBOX_FOR_DTRACE_LIB
1512AssertCompileSize(X86MTRRVAR, 16);
1513# endif
1514/** Pointer to a variable-range MTRR MSR pair. */
1515typedef X86MTRRVAR *PX86MTRRVAR;
1516/** Pointer to a const variable-range MTRR MSR pair. */
1517typedef const X86MTRRVAR *PCX86MTRRVAR;
1518#endif /* __ASSEMBLER__ */
1519
1520
1521/** Memory types that can be encoded in MTRRs.
1522 * @{ */
1523/** Uncacheable. */
1524#define X86_MTRR_MT_UC 0
1525/** Write Combining. */
1526#define X86_MTRR_MT_WC 1
1527/** Write-through. */
1528#define X86_MTRR_MT_WT 4
1529/** Write-protected. */
1530#define X86_MTRR_MT_WP 5
1531/** Writeback. */
1532#define X86_MTRR_MT_WB 6
1533/** @}*/
1534
1535/** Architecture capabilities (bugfixes). */
1536#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1537/** CPU is no subject to meltdown problems. */
1538#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1539/** CPU has better IBRS and you can leave it on all the time. */
1540#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1541/** CPU has return stack buffer (RSB) override. */
1542#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1543/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1544 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1545#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1546/** CPU does not suffer from MDS issues. */
1547#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1548
1549/** Flush command register. */
1550#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1551/** Flush the level 1 data cache when this bit is written. */
1552#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1553
1554/** Cache control/info. */
1555#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1556
1557#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1558/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1559 * R0 SS == CS + 8
1560 * R3 CS == CS + 16
1561 * R3 SS == CS + 24
1562 */
1563#define MSR_IA32_SYSENTER_CS 0x174
1564/** SYSENTER_ESP - the R0 ESP. */
1565#define MSR_IA32_SYSENTER_ESP 0x175
1566/** SYSENTER_EIP - the R0 EIP. */
1567#define MSR_IA32_SYSENTER_EIP 0x176
1568#endif
1569
1570/** Machine Check Global Capabilities Register. */
1571#define MSR_IA32_MCG_CAP 0x179
1572/** Machine Check Global Status Register. */
1573#define MSR_IA32_MCG_STATUS 0x17A
1574/** Machine Check Global Control Register. */
1575#define MSR_IA32_MCG_CTRL 0x17B
1576
1577/** Page Attribute Table. */
1578#define MSR_IA32_CR_PAT 0x277
1579/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1580 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1581#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1582
1583/** Memory types that can be encoded in the IA32_PAT MSR.
1584 * @{ */
1585/** Uncacheable. */
1586#define MSR_IA32_PAT_MT_UC 0
1587/** Write Combining. */
1588#define MSR_IA32_PAT_MT_WC 1
1589/** Reserved value 2. */
1590#define MSR_IA32_PAT_MT_RSVD_2 2
1591/** Reserved value 3. */
1592#define MSR_IA32_PAT_MT_RSVD_3 3
1593/** Write-through. */
1594#define MSR_IA32_PAT_MT_WT 4
1595/** Write-protected. */
1596#define MSR_IA32_PAT_MT_WP 5
1597/** Writeback. */
1598#define MSR_IA32_PAT_MT_WB 6
1599/** Uncached (UC-). */
1600#define MSR_IA32_PAT_MT_UCD 7
1601/** @}*/
1602
1603
1604/** Performance event select MSRs. (Intel only) */
1605#define MSR_IA32_PERFEVTSEL0 0x186
1606#define MSR_IA32_PERFEVTSEL1 0x187
1607#define MSR_IA32_PERFEVTSEL2 0x188
1608#define MSR_IA32_PERFEVTSEL3 0x189
1609
1610/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1611 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1612 * holds a ratio that Apple takes for TSC granularity.
1613 *
1614 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1615#define MSR_FLEX_RATIO 0x194
1616/** Performance state value and starting with Intel core more.
1617 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1618#define MSR_IA32_PERF_STATUS 0x198
1619#define MSR_IA32_PERF_CTL 0x199
1620#define MSR_IA32_THERM_STATUS 0x19c
1621
1622/** Offcore response event select registers. */
1623#define MSR_OFFCORE_RSP_0 0x1a6
1624#define MSR_OFFCORE_RSP_1 0x1a7
1625
1626/** Enable misc. processor features (R/W). */
1627#define MSR_IA32_MISC_ENABLE 0x1A0
1628/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1629#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1630/** Automatic Thermal Control Circuit Enable (R/W). */
1631#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1632/** Performance Monitoring Available (R). */
1633#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1634/** Branch Trace Storage Unavailable (R/O). */
1635#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1636/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1637#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1638/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1639#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1640/** If MONITOR/MWAIT is supported (R/W). */
1641#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1642/** Limit CPUID Maxval to 3 leafs (R/W). */
1643#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1644/** When set to 1, xTPR messages are disabled (R/W). */
1645#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1646/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1647#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1648
1649/** Trace/Profile Resource Control (R/W) */
1650#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1651/** Last branch record. */
1652#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1653/** Branch trace flag (single step on branches). */
1654#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1655/** Performance monitoring pin control (AMD only). */
1656#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1657#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1658#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1659#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1660/** Trace message enable (Intel only). */
1661#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1662/** Branch trace store (Intel only). */
1663#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1664/** Branch trace interrupt (Intel only). */
1665#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1666/** Branch trace off in privileged code (Intel only). */
1667#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1668/** Branch trace off in user code (Intel only). */
1669#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1670/** Freeze LBR on PMI flag (Intel only). */
1671#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1672/** Freeze PERFMON on PMI flag (Intel only). */
1673#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1674/** Freeze while SMM enabled (Intel only). */
1675#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1676/** Advanced debugging of RTM regions (Intel only). */
1677#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1678/** Debug control MSR valid bits (Intel only). */
1679#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1680 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1681 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1682 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1683 | MSR_IA32_DEBUGCTL_RTM)
1684
1685/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1686 * @{ */
1687#define MSR_P4_LASTBRANCH_0 0x1db
1688#define MSR_P4_LASTBRANCH_1 0x1dc
1689#define MSR_P4_LASTBRANCH_2 0x1dd
1690#define MSR_P4_LASTBRANCH_3 0x1de
1691
1692/** LBR Top-of-stack MSR (index to most recent record). */
1693#define MSR_P4_LASTBRANCH_TOS 0x1da
1694/** @} */
1695
1696/** @name Last branch registers for Core 2 and related Xeons.
1697 * @{ */
1698#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1699#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1700#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1701#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1702
1703#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1704#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1705#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1706#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1707
1708/** LBR Top-of-stack MSR (index to most recent record). */
1709#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1710/** @} */
1711
1712/** @name Last branch registers.
1713 * @{ */
1714#define MSR_LASTBRANCH_0_FROM_IP 0x680
1715#define MSR_LASTBRANCH_1_FROM_IP 0x681
1716#define MSR_LASTBRANCH_2_FROM_IP 0x682
1717#define MSR_LASTBRANCH_3_FROM_IP 0x683
1718#define MSR_LASTBRANCH_4_FROM_IP 0x684
1719#define MSR_LASTBRANCH_5_FROM_IP 0x685
1720#define MSR_LASTBRANCH_6_FROM_IP 0x686
1721#define MSR_LASTBRANCH_7_FROM_IP 0x687
1722#define MSR_LASTBRANCH_8_FROM_IP 0x688
1723#define MSR_LASTBRANCH_9_FROM_IP 0x689
1724#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1725#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1726#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1727#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1728#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1729#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1730#define MSR_LASTBRANCH_16_FROM_IP 0x690
1731#define MSR_LASTBRANCH_17_FROM_IP 0x691
1732#define MSR_LASTBRANCH_18_FROM_IP 0x692
1733#define MSR_LASTBRANCH_19_FROM_IP 0x693
1734#define MSR_LASTBRANCH_20_FROM_IP 0x694
1735#define MSR_LASTBRANCH_21_FROM_IP 0x695
1736#define MSR_LASTBRANCH_22_FROM_IP 0x696
1737#define MSR_LASTBRANCH_23_FROM_IP 0x697
1738#define MSR_LASTBRANCH_24_FROM_IP 0x698
1739#define MSR_LASTBRANCH_25_FROM_IP 0x699
1740#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1741#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1742#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1743#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1744#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1745#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1746
1747#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1748#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1749#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1750#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1751#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1752#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1753#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1754#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1755#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1756#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1757#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1758#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1759#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1760#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1761#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1762#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1763#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1764#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1765#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1766#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1767#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1768#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1769#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1770#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1771#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1772#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1773#define MSR_LASTBRANCH_26_TO_IP 0x6da
1774#define MSR_LASTBRANCH_27_TO_IP 0x6db
1775#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1776#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1777#define MSR_LASTBRANCH_30_TO_IP 0x6de
1778#define MSR_LASTBRANCH_31_TO_IP 0x6df
1779
1780#define MSR_LASTBRANCH_0_INFO 0xdc0
1781#define MSR_LASTBRANCH_1_INFO 0xdc1
1782#define MSR_LASTBRANCH_2_INFO 0xdc2
1783#define MSR_LASTBRANCH_3_INFO 0xdc3
1784#define MSR_LASTBRANCH_4_INFO 0xdc4
1785#define MSR_LASTBRANCH_5_INFO 0xdc5
1786#define MSR_LASTBRANCH_6_INFO 0xdc6
1787#define MSR_LASTBRANCH_7_INFO 0xdc7
1788#define MSR_LASTBRANCH_8_INFO 0xdc8
1789#define MSR_LASTBRANCH_9_INFO 0xdc9
1790#define MSR_LASTBRANCH_10_INFO 0xdca
1791#define MSR_LASTBRANCH_11_INFO 0xdcb
1792#define MSR_LASTBRANCH_12_INFO 0xdcc
1793#define MSR_LASTBRANCH_13_INFO 0xdcd
1794#define MSR_LASTBRANCH_14_INFO 0xdce
1795#define MSR_LASTBRANCH_15_INFO 0xdcf
1796#define MSR_LASTBRANCH_16_INFO 0xdd0
1797#define MSR_LASTBRANCH_17_INFO 0xdd1
1798#define MSR_LASTBRANCH_18_INFO 0xdd2
1799#define MSR_LASTBRANCH_19_INFO 0xdd3
1800#define MSR_LASTBRANCH_20_INFO 0xdd4
1801#define MSR_LASTBRANCH_21_INFO 0xdd5
1802#define MSR_LASTBRANCH_22_INFO 0xdd6
1803#define MSR_LASTBRANCH_23_INFO 0xdd7
1804#define MSR_LASTBRANCH_24_INFO 0xdd8
1805#define MSR_LASTBRANCH_25_INFO 0xdd9
1806#define MSR_LASTBRANCH_26_INFO 0xdda
1807#define MSR_LASTBRANCH_27_INFO 0xddb
1808#define MSR_LASTBRANCH_28_INFO 0xddc
1809#define MSR_LASTBRANCH_29_INFO 0xddd
1810#define MSR_LASTBRANCH_30_INFO 0xdde
1811#define MSR_LASTBRANCH_31_INFO 0xddf
1812
1813/** LBR branch tracking selection MSR. */
1814#define MSR_LASTBRANCH_SELECT 0x1c8
1815/** LBR Top-of-stack MSR (index to most recent record). */
1816#define MSR_LASTBRANCH_TOS 0x1c9
1817/** @} */
1818
1819/** @name Last event record registers.
1820 * @{ */
1821/** Last event record source IP register. */
1822#define MSR_LER_FROM_IP 0x1dd
1823/** Last event record destination IP register. */
1824#define MSR_LER_TO_IP 0x1de
1825/** @} */
1826
1827/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1828#define MSR_IA32_TSX_CTRL 0x122
1829
1830/** Variable range MTRRs.
1831 * @{ */
1832#define MSR_IA32_MTRR_PHYSBASE0 0x200
1833#define MSR_IA32_MTRR_PHYSMASK0 0x201
1834#define MSR_IA32_MTRR_PHYSBASE1 0x202
1835#define MSR_IA32_MTRR_PHYSMASK1 0x203
1836#define MSR_IA32_MTRR_PHYSBASE2 0x204
1837#define MSR_IA32_MTRR_PHYSMASK2 0x205
1838#define MSR_IA32_MTRR_PHYSBASE3 0x206
1839#define MSR_IA32_MTRR_PHYSMASK3 0x207
1840#define MSR_IA32_MTRR_PHYSBASE4 0x208
1841#define MSR_IA32_MTRR_PHYSMASK4 0x209
1842#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1843#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1844#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1845#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1846#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1847#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1848#define MSR_IA32_MTRR_PHYSBASE8 0x210
1849#define MSR_IA32_MTRR_PHYSMASK8 0x211
1850#define MSR_IA32_MTRR_PHYSBASE9 0x212
1851#define MSR_IA32_MTRR_PHYSMASK9 0x213
1852/** @} */
1853
1854/** Fixed range MTRRs.
1855 * @{ */
1856#define MSR_IA32_MTRR_FIX64K_00000 0x250
1857#define MSR_IA32_MTRR_FIX16K_80000 0x258
1858#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1859#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1860#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1861#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1862#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1863#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1864#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1865#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1866#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1867/** @} */
1868
1869/** MTRR Default Type.
1870 * @{ */
1871#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1872#define MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK 0xFF
1873#define MSR_IA32_MTRR_DEF_TYPE_FIXED_EN RT_BIT_64(10)
1874#define MSR_IA32_MTRR_DEF_TYPE_MTRR_EN RT_BIT_64(11)
1875#define MSR_IA32_MTRR_DEF_TYPE_VALID_MASK ( MSR_IA32_MTRR_DEF_TYPE_DEF_MT_MASK \
1876 | MSR_IA32_MTRR_DEF_TYPE_FIXED_EN \
1877 | MSR_IA32_MTRR_DEF_TYPE_MTRR_EN)
1878/** @} */
1879
1880/** Variable-range MTRR physical mask valid. */
1881#define MSR_IA32_MTRR_PHYSMASK_VALID RT_BIT_64(11)
1882
1883/** Variable-range MTRR memory type mask. */
1884#define MSR_IA32_MTRR_PHYSBASE_MT_MASK UINT64_C(0xff)
1885
1886/** Global performance counter control facilities (Intel only). */
1887#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1888#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1889#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1890
1891/** Precise Event Based sampling (Intel only). */
1892#define MSR_IA32_PEBS_ENABLE 0x3F1
1893
1894#define MSR_IA32_MC0_CTL 0x400
1895#define MSR_IA32_MC0_STATUS 0x401
1896
1897/** Basic VMX information. */
1898#define MSR_IA32_VMX_BASIC 0x480
1899/** Allowed settings for pin-based VM execution controls. */
1900#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1901/** Allowed settings for proc-based VM execution controls. */
1902#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1903/** Allowed settings for the VM-exit controls. */
1904#define MSR_IA32_VMX_EXIT_CTLS 0x483
1905/** Allowed settings for the VM-entry controls. */
1906#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1907/** Misc VMX info. */
1908#define MSR_IA32_VMX_MISC 0x485
1909/** Fixed cleared bits in CR0. */
1910#define MSR_IA32_VMX_CR0_FIXED0 0x486
1911/** Fixed set bits in CR0. */
1912#define MSR_IA32_VMX_CR0_FIXED1 0x487
1913/** Fixed cleared bits in CR4. */
1914#define MSR_IA32_VMX_CR4_FIXED0 0x488
1915/** Fixed set bits in CR4. */
1916#define MSR_IA32_VMX_CR4_FIXED1 0x489
1917/** Information for enumerating fields in the VMCS. */
1918#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1919/** Allowed settings for secondary processor-based VM-execution controls. */
1920#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1921/** EPT capabilities. */
1922#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1923/** Allowed settings of all pin-based VM execution controls. */
1924#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1925/** Allowed settings of all proc-based VM execution controls. */
1926#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1927/** Allowed settings of all VMX exit controls. */
1928#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1929/** Allowed settings of all VMX entry controls. */
1930#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1931/** Allowed settings for the VM-function controls. */
1932#define MSR_IA32_VMX_VMFUNC 0x491
1933/** Tertiary processor-based VM execution controls. */
1934#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1935/** Secondary VM-exit controls. */
1936#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1937
1938/** Intel PT - Enable and control for trace packet generation. */
1939#define MSR_IA32_RTIT_CTL 0x570
1940
1941/** DS Save Area (R/W). */
1942#define MSR_IA32_DS_AREA 0x600
1943/** Running Average Power Limit (RAPL) power units. */
1944#define MSR_RAPL_POWER_UNIT 0x606
1945/** Package C3 Interrupt Response Limit. */
1946#define MSR_PKGC3_IRTL 0x60a
1947/** Package C6/C7S Interrupt Response Limit 1. */
1948#define MSR_PKGC_IRTL1 0x60b
1949/** Package C6/C7S Interrupt Response Limit 2. */
1950#define MSR_PKGC_IRTL2 0x60c
1951/** Package C2 Residency Counter. */
1952#define MSR_PKG_C2_RESIDENCY 0x60d
1953/** PKG RAPL Power Limit Control. */
1954#define MSR_PKG_POWER_LIMIT 0x610
1955/** PKG Energy Status. */
1956#define MSR_PKG_ENERGY_STATUS 0x611
1957/** PKG Perf Status. */
1958#define MSR_PKG_PERF_STATUS 0x613
1959/** PKG RAPL Parameters. */
1960#define MSR_PKG_POWER_INFO 0x614
1961/** DRAM RAPL Power Limit Control. */
1962#define MSR_DRAM_POWER_LIMIT 0x618
1963/** DRAM Energy Status. */
1964#define MSR_DRAM_ENERGY_STATUS 0x619
1965/** DRAM Performance Throttling Status. */
1966#define MSR_DRAM_PERF_STATUS 0x61b
1967/** DRAM RAPL Parameters. */
1968#define MSR_DRAM_POWER_INFO 0x61c
1969/** Package C10 Residency Counter. */
1970#define MSR_PKG_C10_RESIDENCY 0x632
1971/** PP0 Energy Status. */
1972#define MSR_PP0_ENERGY_STATUS 0x639
1973/** PP1 Energy Status. */
1974#define MSR_PP1_ENERGY_STATUS 0x641
1975/** Turbo Activation Ratio. */
1976#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1977/** Core Performance Limit Reasons. */
1978#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1979
1980/** Userspace Control flow Enforcement Technology setting. */
1981#define MSR_IA32_U_CET 0x6a0
1982/** Supervisor space Control flow Enforcement Technology setting. */
1983#define MSR_IA32_S_CET 0x6a2
1984/** @name Bit fields for both MSR_IA32_U_CET and MSR_IA32_S_CET
1985 * @{ */
1986/** Enables the Shadow stack. */
1987# define MSR_IA32_CET_SH_STK_EN RT_BIT_64(0)
1988/** Enables WRSS{D,Q}W instructions. */
1989# define MSR_IA32_CET_WR_SHSTK_EN RT_BIT_64(1)
1990/** Enables indirect branch tracking. */
1991# define MSR_IA32_CET_ENDBR_EN RT_BIT_64(2)
1992/** Enable legacy compatibility treatment for indirect branch tracking. */
1993# define MSR_IA32_CET_LEG_IW_EN RT_BIT_64(3)
1994/** Enables the use of no-track prefix for indirect branch tracking. */
1995# define MSR_IA32_CET_NO_TRACK_EN RT_BIT_64(4)
1996/** Disables suppression of CET indirect branch tracking on legacy compatibility. */
1997# define MSR_IA32_CET_SUPPRESS_DIS RT_BIT_64(5)
1998/** Suppresses indirect branch tracking. */
1999# define MSR_IA32_CET_SUPPRESS RT_BIT_64(10)
2000/** Returns the value of the indirect branch tracking state machine: IDLE(0), WAIT_FOR_ENDBRANCH(1). */
2001# define MSR_IA32_CET_TRACKER RT_BIT_64(11)
2002/** Linear address of memory containing a bitmap indicating valid pages as CALL/JMP targets not landing
2003 * on a ENDBRANCH instruction. */
2004# define MSR_IA32_CET_EB_LEG_BITMAP_BASE UINT64_C(0xfffffffffffff000)
2005/** @} */
2006
2007/** X2APIC MSR range start. */
2008#define MSR_IA32_X2APIC_START 0x800
2009/** X2APIC MSR - APIC ID Register. */
2010#define MSR_IA32_X2APIC_ID 0x802
2011/** X2APIC MSR - APIC Version Register. */
2012#define MSR_IA32_X2APIC_VERSION 0x803
2013/** X2APIC MSR - Task Priority Register. */
2014#define MSR_IA32_X2APIC_TPR 0x808
2015/** X2APIC MSR - Processor Priority register. */
2016#define MSR_IA32_X2APIC_PPR 0x80A
2017/** X2APIC MSR - End Of Interrupt register. */
2018#define MSR_IA32_X2APIC_EOI 0x80B
2019/** X2APIC MSR - Logical Destination Register. */
2020#define MSR_IA32_X2APIC_LDR 0x80D
2021/** X2APIC MSR - Spurious Interrupt Vector Register. */
2022#define MSR_IA32_X2APIC_SVR 0x80F
2023/** X2APIC MSR - In-service Register (bits 31:0). */
2024#define MSR_IA32_X2APIC_ISR0 0x810
2025/** X2APIC MSR - In-service Register (bits 63:32). */
2026#define MSR_IA32_X2APIC_ISR1 0x811
2027/** X2APIC MSR - In-service Register (bits 95:64). */
2028#define MSR_IA32_X2APIC_ISR2 0x812
2029/** X2APIC MSR - In-service Register (bits 127:96). */
2030#define MSR_IA32_X2APIC_ISR3 0x813
2031/** X2APIC MSR - In-service Register (bits 159:128). */
2032#define MSR_IA32_X2APIC_ISR4 0x814
2033/** X2APIC MSR - In-service Register (bits 191:160). */
2034#define MSR_IA32_X2APIC_ISR5 0x815
2035/** X2APIC MSR - In-service Register (bits 223:192). */
2036#define MSR_IA32_X2APIC_ISR6 0x816
2037/** X2APIC MSR - In-service Register (bits 255:224). */
2038#define MSR_IA32_X2APIC_ISR7 0x817
2039/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
2040#define MSR_IA32_X2APIC_TMR0 0x818
2041/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
2042#define MSR_IA32_X2APIC_TMR1 0x819
2043/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
2044#define MSR_IA32_X2APIC_TMR2 0x81A
2045/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
2046#define MSR_IA32_X2APIC_TMR3 0x81B
2047/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
2048#define MSR_IA32_X2APIC_TMR4 0x81C
2049/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
2050#define MSR_IA32_X2APIC_TMR5 0x81D
2051/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
2052#define MSR_IA32_X2APIC_TMR6 0x81E
2053/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
2054#define MSR_IA32_X2APIC_TMR7 0x81F
2055/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
2056#define MSR_IA32_X2APIC_IRR0 0x820
2057/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
2058#define MSR_IA32_X2APIC_IRR1 0x821
2059/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
2060#define MSR_IA32_X2APIC_IRR2 0x822
2061/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
2062#define MSR_IA32_X2APIC_IRR3 0x823
2063/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
2064#define MSR_IA32_X2APIC_IRR4 0x824
2065/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
2066#define MSR_IA32_X2APIC_IRR5 0x825
2067/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
2068#define MSR_IA32_X2APIC_IRR6 0x826
2069/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
2070#define MSR_IA32_X2APIC_IRR7 0x827
2071/** X2APIC MSR - Error Status Register. */
2072#define MSR_IA32_X2APIC_ESR 0x828
2073/** X2APIC MSR - LVT CMCI Register. */
2074#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
2075/** X2APIC MSR - Interrupt Command Register. */
2076#define MSR_IA32_X2APIC_ICR 0x830
2077/** X2APIC MSR - LVT Timer Register. */
2078#define MSR_IA32_X2APIC_LVT_TIMER 0x832
2079/** X2APIC MSR - LVT Thermal Sensor Register. */
2080#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
2081/** X2APIC MSR - LVT Performance Counter Register. */
2082#define MSR_IA32_X2APIC_LVT_PERF 0x834
2083/** X2APIC MSR - LVT LINT0 Register. */
2084#define MSR_IA32_X2APIC_LVT_LINT0 0x835
2085/** X2APIC MSR - LVT LINT1 Register. */
2086#define MSR_IA32_X2APIC_LVT_LINT1 0x836
2087/** X2APIC MSR - LVT Error Register . */
2088#define MSR_IA32_X2APIC_LVT_ERROR 0x837
2089/** X2APIC MSR - Timer Initial Count Register. */
2090#define MSR_IA32_X2APIC_TIMER_ICR 0x838
2091/** X2APIC MSR - Timer Current Count Register. */
2092#define MSR_IA32_X2APIC_TIMER_CCR 0x839
2093/** X2APIC MSR - Timer Divide Configuration Register. */
2094#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
2095/** X2APIC MSR - Self IPI. */
2096#define MSR_IA32_X2APIC_SELF_IPI 0x83F
2097/** X2APIC MSR range end. */
2098#define MSR_IA32_X2APIC_END 0x8FF
2099/** X2APIC MSR - LVT start range. */
2100#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
2101/** X2APIC MSR - LVT end range (inclusive). */
2102#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
2103
2104/** K6 EFER - Extended Feature Enable Register. */
2105#define MSR_K6_EFER UINT32_C(0xc0000080)
2106/** @todo document EFER */
2107/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
2108#define MSR_K6_EFER_SCE RT_BIT_32(0)
2109/** Bit 8 - LME - Long mode enabled. (R/W) */
2110#define MSR_K6_EFER_LME RT_BIT_32(8)
2111#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
2112/** Bit 10 - LMA - Long mode active. (R) */
2113#define MSR_K6_EFER_LMA RT_BIT_32(10)
2114#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
2115/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
2116#define MSR_K6_EFER_NXE RT_BIT_32(11)
2117#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
2118/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
2119#define MSR_K6_EFER_SVME RT_BIT_32(12)
2120/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
2121#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
2122/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
2123#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
2124/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
2125#define MSR_K6_EFER_TCE RT_BIT_32(15)
2126/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
2127#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
2128
2129/** K6 STAR - SYSCALL/RET targets. */
2130#define MSR_K6_STAR UINT32_C(0xc0000081)
2131/** Shift value for getting the SYSRET CS and SS value. */
2132#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
2133/** Shift value for getting the SYSCALL CS and SS value. */
2134#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
2135/** Selector mask for use after shifting. */
2136#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
2137/** The mask which give the SYSCALL EIP. */
2138#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
2139/** K6 WHCR - Write Handling Control Register. */
2140#define MSR_K6_WHCR UINT32_C(0xc0000082)
2141/** K6 UWCCR - UC/WC Cacheability Control Register. */
2142#define MSR_K6_UWCCR UINT32_C(0xc0000085)
2143/** K6 PSOR - Processor State Observability Register. */
2144#define MSR_K6_PSOR UINT32_C(0xc0000087)
2145/** K6 PFIR - Page Flush/Invalidate Register. */
2146#define MSR_K6_PFIR UINT32_C(0xc0000088)
2147
2148/** Performance counter MSRs. (AMD only) */
2149#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
2150#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
2151#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
2152#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
2153#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
2154#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
2155#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
2156#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
2157
2158/** K8 LSTAR - Long mode SYSCALL target (RIP). */
2159#define MSR_K8_LSTAR UINT32_C(0xc0000082)
2160/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
2161#define MSR_K8_CSTAR UINT32_C(0xc0000083)
2162/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
2163#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
2164/** K8 FS.base - The 64-bit base FS register. */
2165#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
2166/** K8 GS.base - The 64-bit base GS register. */
2167#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
2168/** K8 KernelGSbase - Used with SWAPGS. */
2169#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
2170/** K8 TSC_AUX - Used with RDTSCP. */
2171#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
2172#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
2173#define MSR_K8_HWCR UINT32_C(0xc0010015)
2174#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
2175#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
2176#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
2177#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
2178#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
2179#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
2180
2181/** SMM MSRs. */
2182#define MSR_K7_SMBASE UINT32_C(0xc0010111)
2183#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
2184#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
2185
2186/** North bridge config? See BIOS & Kernel dev guides for
2187 * details. */
2188#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
2189
2190/** Hypertransport interrupt pending register.
2191 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
2192#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
2193
2194/** SVM Control. */
2195#define MSR_K8_VM_CR UINT32_C(0xc0010114)
2196/** Disables HDT (Hardware Debug Tool) and certain internal debug
2197 * features. */
2198#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
2199/** If set, non-intercepted INIT signals are converted to \#SX
2200 * exceptions. */
2201#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
2202/** Disables A20 masking. */
2203#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
2204/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
2205#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
2206/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
2207 * clear, EFER.SVME can be written normally. */
2208#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
2209
2210#define MSR_K8_IGNNE UINT32_C(0xc0010115)
2211#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
2212/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
2213 * host state during world switch. */
2214#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
2215
2216/** Virtualized speculation control for AMD processors.
2217 *
2218 * Unified interface among different CPU generations.
2219 * The VMM will set any architectural MSRs based on the CPU.
2220 * See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
2221 * (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
2222#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
2223/** Speculative Store Bypass Disable. */
2224# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
2225
2226/** @} */
2227
2228
2229/** @name Page Table / Directory / Directory Pointers / L4.
2230 * @{
2231 */
2232
2233#ifndef __ASSEMBLER__
2234/** Page table/directory entry as an unsigned integer. */
2235typedef uint32_t X86PGUINT;
2236/** Pointer to a page table/directory table entry as an unsigned integer. */
2237typedef X86PGUINT *PX86PGUINT;
2238/** Pointer to an const page table/directory table entry as an unsigned integer. */
2239typedef X86PGUINT const *PCX86PGUINT;
2240#endif
2241
2242/** Number of entries in a 32-bit PT/PD. */
2243#define X86_PG_ENTRIES 1024
2244
2245
2246#ifndef __ASSEMBLER__
2247/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2248typedef uint64_t X86PGPAEUINT;
2249/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2250typedef X86PGPAEUINT *PX86PGPAEUINT;
2251/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2252typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2253#endif
2254
2255/** Number of entries in a PAE PT/PD. */
2256#define X86_PG_PAE_ENTRIES 512
2257/** Number of entries in a PAE PDPT. */
2258#define X86_PG_PAE_PDPE_ENTRIES 4
2259
2260/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2261#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2262/** Number of entries in an AMD64 PDPT.
2263 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2264#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2265
2266/** The size of a default page. */
2267#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2268/** The page shift of a default page. */
2269#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2270/** The default page offset mask. */
2271#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2272/** The default page base mask for virtual addresses. */
2273#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2274/** The default page base mask for virtual addresses - 32bit version. */
2275#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2276
2277/** The size of a 4KB page. */
2278#define X86_PAGE_4K_SIZE _4K
2279/** The page shift of a 4KB page. */
2280#define X86_PAGE_4K_SHIFT 12
2281/** The 4KB page offset mask. */
2282#define X86_PAGE_4K_OFFSET_MASK 0xfff
2283/** The 4KB page base mask for virtual addresses. */
2284#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2285/** The 4KB page base mask for virtual addresses - 32bit version. */
2286#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2287
2288/** The size of a 2MB page. */
2289#define X86_PAGE_2M_SIZE _2M
2290/** The page shift of a 2MB page. */
2291#define X86_PAGE_2M_SHIFT 21
2292/** The 2MB page offset mask. */
2293#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2294/** The 2MB page base mask for virtual addresses. */
2295#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2296/** The 2MB page base mask for virtual addresses - 32bit version. */
2297#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2298
2299/** The size of a 4MB page. */
2300#define X86_PAGE_4M_SIZE _4M
2301/** The page shift of a 4MB page. */
2302#define X86_PAGE_4M_SHIFT 22
2303/** The 4MB page offset mask. */
2304#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2305/** The 4MB page base mask for virtual addresses. */
2306#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2307/** The 4MB page base mask for virtual addresses - 32bit version. */
2308#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2309
2310/** The size of a 1GB page. */
2311#define X86_PAGE_1G_SIZE _1G
2312/** The page shift of a 1GB page. */
2313#define X86_PAGE_1G_SHIFT 30
2314/** The 1GB page offset mask. */
2315#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2316/** The 1GB page base mask for virtual addresses. */
2317#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2318
2319/**
2320 * Check if the given address is canonical.
2321 */
2322#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2323
2324/**
2325 * Gets the page base mask given the page shift.
2326 */
2327#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2328
2329/**
2330 * Gets the page offset mask given the page shift.
2331 */
2332#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2333
2334
2335/** @name Page Table Entry
2336 * @{
2337 */
2338/** Bit 0 - P - Present bit. */
2339#define X86_PTE_BIT_P 0
2340/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2341#define X86_PTE_BIT_RW 1
2342/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2343#define X86_PTE_BIT_US 2
2344/** Bit 3 - PWT - Page level write thru bit. */
2345#define X86_PTE_BIT_PWT 3
2346/** Bit 4 - PCD - Page level cache disable bit. */
2347#define X86_PTE_BIT_PCD 4
2348/** Bit 5 - A - Access bit. */
2349#define X86_PTE_BIT_A 5
2350/** Bit 6 - D - Dirty bit. */
2351#define X86_PTE_BIT_D 6
2352/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2353#define X86_PTE_BIT_PAT 7
2354/** Bit 8 - G - Global flag. */
2355#define X86_PTE_BIT_G 8
2356/** Bits 63 - NX - PAE/LM - No execution flag. */
2357#define X86_PTE_PAE_BIT_NX 63
2358
2359/** Bit 0 - P - Present bit mask. */
2360#define X86_PTE_P RT_BIT_32(0)
2361/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2362#define X86_PTE_RW RT_BIT_32(1)
2363/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2364#define X86_PTE_US RT_BIT_32(2)
2365/** Bit 3 - PWT - Page level write thru bit mask. */
2366#define X86_PTE_PWT RT_BIT_32(3)
2367/** Bit 4 - PCD - Page level cache disable bit mask. */
2368#define X86_PTE_PCD RT_BIT_32(4)
2369/** Bit 5 - A - Access bit mask. */
2370#define X86_PTE_A RT_BIT_32(5)
2371/** Bit 6 - D - Dirty bit mask. */
2372#define X86_PTE_D RT_BIT_32(6)
2373/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2374#define X86_PTE_PAT RT_BIT_32(7)
2375/** Bit 8 - G - Global bit mask. */
2376#define X86_PTE_G RT_BIT_32(8)
2377
2378/** Bits 9-11 - - Available for use to system software. */
2379#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2380/** Bits 12-31 - - Physical Page number of the next level. */
2381#define X86_PTE_PG_MASK ( 0xfffff000 )
2382
2383/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2384#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2385/** Bits 63 - NX - PAE/LM - No execution flag. */
2386#define X86_PTE_PAE_NX RT_BIT_64(63)
2387/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2388#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2389/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2390#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2391/** No bits - - LM - MBZ bits when NX is active. */
2392#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2393/** Bits 63 - - LM - MBZ bits when no NX. */
2394#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2395
2396#ifndef __ASSEMBLER__
2397
2398/**
2399 * Page table entry.
2400 */
2401typedef struct X86PTEBITS
2402{
2403 /** Flags whether(=1) or not the page is present. */
2404 uint32_t u1Present : 1;
2405 /** Read(=0) / Write(=1) flag. */
2406 uint32_t u1Write : 1;
2407 /** User(=1) / Supervisor (=0) flag. */
2408 uint32_t u1User : 1;
2409 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2410 uint32_t u1WriteThru : 1;
2411 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2412 uint32_t u1CacheDisable : 1;
2413 /** Accessed flag.
2414 * Indicates that the page have been read or written to. */
2415 uint32_t u1Accessed : 1;
2416 /** Dirty flag.
2417 * Indicates that the page has been written to. */
2418 uint32_t u1Dirty : 1;
2419 /** Reserved / If PAT enabled, bit 2 of the index. */
2420 uint32_t u1PAT : 1;
2421 /** Global flag. (Ignored in all but final level.) */
2422 uint32_t u1Global : 1;
2423 /** Available for use to system software. */
2424 uint32_t u3Available : 3;
2425 /** Physical Page number of the next level. */
2426 uint32_t u20PageNo : 20;
2427} X86PTEBITS;
2428# ifndef VBOX_FOR_DTRACE_LIB
2429AssertCompileSize(X86PTEBITS, 4);
2430# endif
2431/** Pointer to a page table entry. */
2432typedef X86PTEBITS *PX86PTEBITS;
2433/** Pointer to a const page table entry. */
2434typedef const X86PTEBITS *PCX86PTEBITS;
2435
2436/**
2437 * Page table entry.
2438 */
2439typedef union X86PTE
2440{
2441 /** Unsigned integer view */
2442 X86PGUINT u;
2443# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2444 /** Bit field view. */
2445 X86PTEBITS n;
2446# endif
2447 /** 32-bit view. */
2448 uint32_t au32[1];
2449 /** 16-bit view. */
2450 uint16_t au16[2];
2451 /** 8-bit view. */
2452 uint8_t au8[4];
2453} X86PTE;
2454# ifndef VBOX_FOR_DTRACE_LIB
2455AssertCompileSize(X86PTE, 4);
2456# endif
2457/** Pointer to a page table entry. */
2458typedef X86PTE *PX86PTE;
2459/** Pointer to a const page table entry. */
2460typedef const X86PTE *PCX86PTE;
2461
2462
2463/**
2464 * PAE page table entry.
2465 */
2466typedef struct X86PTEPAEBITS
2467{
2468 /** Flags whether(=1) or not the page is present. */
2469 uint32_t u1Present : 1;
2470 /** Read(=0) / Write(=1) flag. */
2471 uint32_t u1Write : 1;
2472 /** User(=1) / Supervisor(=0) flag. */
2473 uint32_t u1User : 1;
2474 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2475 uint32_t u1WriteThru : 1;
2476 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2477 uint32_t u1CacheDisable : 1;
2478 /** Accessed flag.
2479 * Indicates that the page have been read or written to. */
2480 uint32_t u1Accessed : 1;
2481 /** Dirty flag.
2482 * Indicates that the page has been written to. */
2483 uint32_t u1Dirty : 1;
2484 /** Reserved / If PAT enabled, bit 2 of the index. */
2485 uint32_t u1PAT : 1;
2486 /** Global flag. (Ignored in all but final level.) */
2487 uint32_t u1Global : 1;
2488 /** Available for use to system software. */
2489 uint32_t u3Available : 3;
2490 /** Physical Page number of the next level - Low Part. Don't use this. */
2491 uint32_t u20PageNoLow : 20;
2492 /** Physical Page number of the next level - High Part. Don't use this. */
2493 uint32_t u20PageNoHigh : 20;
2494 /** MBZ bits */
2495 uint32_t u11Reserved : 11;
2496 /** No Execute flag. */
2497 uint32_t u1NoExecute : 1;
2498} X86PTEPAEBITS;
2499# ifndef VBOX_FOR_DTRACE_LIB
2500AssertCompileSize(X86PTEPAEBITS, 8);
2501# endif
2502/** Pointer to a page table entry. */
2503typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2504/** Pointer to a page table entry. */
2505typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2506
2507/**
2508 * PAE Page table entry.
2509 */
2510typedef union X86PTEPAE
2511{
2512 /** Unsigned integer view */
2513 X86PGPAEUINT u;
2514# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2515 /** Bit field view. */
2516 X86PTEPAEBITS n;
2517# endif
2518 /** 32-bit view. */
2519 uint32_t au32[2];
2520 /** 16-bit view. */
2521 uint16_t au16[4];
2522 /** 8-bit view. */
2523 uint8_t au8[8];
2524} X86PTEPAE;
2525# ifndef VBOX_FOR_DTRACE_LIB
2526AssertCompileSize(X86PTEPAE, 8);
2527# endif
2528/** Pointer to a PAE page table entry. */
2529typedef X86PTEPAE *PX86PTEPAE;
2530/** Pointer to a const PAE page table entry. */
2531typedef const X86PTEPAE *PCX86PTEPAE;
2532/** @} */
2533
2534/**
2535 * Page table.
2536 */
2537typedef struct X86PT
2538{
2539 /** PTE Array. */
2540 X86PTE a[X86_PG_ENTRIES];
2541} X86PT;
2542# ifndef VBOX_FOR_DTRACE_LIB
2543AssertCompileSize(X86PT, 4096);
2544# endif
2545/** Pointer to a page table. */
2546typedef X86PT *PX86PT;
2547/** Pointer to a const page table. */
2548typedef const X86PT *PCX86PT;
2549
2550#endif /* !__ASSEMBLER__ */
2551
2552/** The page shift to get the PT index. */
2553#define X86_PT_SHIFT 12
2554/** The PT index mask (apply to a shifted page address). */
2555#define X86_PT_MASK 0x3ff
2556
2557
2558#ifndef __ASSEMBLER__
2559/**
2560 * Page directory.
2561 */
2562typedef struct X86PTPAE
2563{
2564 /** PTE Array. */
2565 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2566} X86PTPAE;
2567# ifndef VBOX_FOR_DTRACE_LIB
2568AssertCompileSize(X86PTPAE, 4096);
2569# endif
2570/** Pointer to a page table. */
2571typedef X86PTPAE *PX86PTPAE;
2572/** Pointer to a const page table. */
2573typedef const X86PTPAE *PCX86PTPAE;
2574#endif /* !__ASSEMBLY__ */
2575
2576/** The page shift to get the PA PTE index. */
2577#define X86_PT_PAE_SHIFT 12
2578/** The PAE PT index mask (apply to a shifted page address). */
2579#define X86_PT_PAE_MASK 0x1ff
2580
2581
2582/** @name 4KB Page Directory Entry
2583 * @{
2584 */
2585/** Bit 0 - P - Present bit. */
2586#define X86_PDE_P RT_BIT_32(0)
2587/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2588#define X86_PDE_RW RT_BIT_32(1)
2589/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2590#define X86_PDE_US RT_BIT_32(2)
2591/** Bit 3 - PWT - Page level write thru bit. */
2592#define X86_PDE_PWT RT_BIT_32(3)
2593/** Bit 4 - PCD - Page level cache disable bit. */
2594#define X86_PDE_PCD RT_BIT_32(4)
2595/** Bit 5 - A - Access bit. */
2596#define X86_PDE_A RT_BIT_32(5)
2597/** Bit 7 - PS - Page size attribute.
2598 * Clear mean 4KB pages, set means large pages (2/4MB). */
2599#define X86_PDE_PS RT_BIT_32(7)
2600/** Bits 9-11 - - Available for use to system software. */
2601#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2602/** Bits 12-31 - - Physical Page number of the next level. */
2603#define X86_PDE_PG_MASK ( 0xfffff000 )
2604
2605/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2606#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2607/** Bits 63 - NX - PAE/LM - No execution flag. */
2608#define X86_PDE_PAE_NX RT_BIT_64(63)
2609/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2610#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2611/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2612#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2613/** Bit 7 - - LM - MBZ bits when NX is active. */
2614#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2615/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2616#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2617
2618#ifndef __ASSEMBLER__
2619
2620/**
2621 * Page directory entry.
2622 */
2623typedef struct X86PDEBITS
2624{
2625 /** Flags whether(=1) or not the page is present. */
2626 uint32_t u1Present : 1;
2627 /** Read(=0) / Write(=1) flag. */
2628 uint32_t u1Write : 1;
2629 /** User(=1) / Supervisor (=0) flag. */
2630 uint32_t u1User : 1;
2631 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2632 uint32_t u1WriteThru : 1;
2633 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2634 uint32_t u1CacheDisable : 1;
2635 /** Accessed flag.
2636 * Indicates that the page has been read or written to. */
2637 uint32_t u1Accessed : 1;
2638 /** Reserved / Ignored (dirty bit). */
2639 uint32_t u1Reserved0 : 1;
2640 /** Size bit if PSE is enabled - in any event it's 0. */
2641 uint32_t u1Size : 1;
2642 /** Reserved / Ignored (global bit). */
2643 uint32_t u1Reserved1 : 1;
2644 /** Available for use to system software. */
2645 uint32_t u3Available : 3;
2646 /** Physical Page number of the next level. */
2647 uint32_t u20PageNo : 20;
2648} X86PDEBITS;
2649# ifndef VBOX_FOR_DTRACE_LIB
2650AssertCompileSize(X86PDEBITS, 4);
2651# endif
2652/** Pointer to a page directory entry. */
2653typedef X86PDEBITS *PX86PDEBITS;
2654/** Pointer to a const page directory entry. */
2655typedef const X86PDEBITS *PCX86PDEBITS;
2656
2657
2658/**
2659 * PAE page directory entry.
2660 */
2661typedef struct X86PDEPAEBITS
2662{
2663 /** Flags whether(=1) or not the page is present. */
2664 uint32_t u1Present : 1;
2665 /** Read(=0) / Write(=1) flag. */
2666 uint32_t u1Write : 1;
2667 /** User(=1) / Supervisor (=0) flag. */
2668 uint32_t u1User : 1;
2669 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2670 uint32_t u1WriteThru : 1;
2671 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2672 uint32_t u1CacheDisable : 1;
2673 /** Accessed flag.
2674 * Indicates that the page has been read or written to. */
2675 uint32_t u1Accessed : 1;
2676 /** Reserved / Ignored (dirty bit). */
2677 uint32_t u1Reserved0 : 1;
2678 /** Size bit if PSE is enabled - in any event it's 0. */
2679 uint32_t u1Size : 1;
2680 /** Reserved / Ignored (global bit). / */
2681 uint32_t u1Reserved1 : 1;
2682 /** Available for use to system software. */
2683 uint32_t u3Available : 3;
2684 /** Physical Page number of the next level - Low Part. Don't use! */
2685 uint32_t u20PageNoLow : 20;
2686 /** Physical Page number of the next level - High Part. Don't use! */
2687 uint32_t u20PageNoHigh : 20;
2688 /** MBZ bits */
2689 uint32_t u11Reserved : 11;
2690 /** No Execute flag. */
2691 uint32_t u1NoExecute : 1;
2692} X86PDEPAEBITS;
2693# ifndef VBOX_FOR_DTRACE_LIB
2694AssertCompileSize(X86PDEPAEBITS, 8);
2695# endif
2696/** Pointer to a page directory entry. */
2697typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2698/** Pointer to a const page directory entry. */
2699typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2700
2701#endif /* !__ASSEMBLER__ */
2702
2703/** @} */
2704
2705
2706/** @name 2/4MB Page Directory Entry
2707 * @{
2708 */
2709/** Bit 0 - P - Present bit. */
2710#define X86_PDE4M_P RT_BIT_32(0)
2711/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2712#define X86_PDE4M_RW RT_BIT_32(1)
2713/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2714#define X86_PDE4M_US RT_BIT_32(2)
2715/** Bit 3 - PWT - Page level write thru bit. */
2716#define X86_PDE4M_PWT RT_BIT_32(3)
2717/** Bit 4 - PCD - Page level cache disable bit. */
2718#define X86_PDE4M_PCD RT_BIT_32(4)
2719/** Bit 5 - A - Access bit. */
2720#define X86_PDE4M_A RT_BIT_32(5)
2721/** Bit 6 - D - Dirty bit. */
2722#define X86_PDE4M_D RT_BIT_32(6)
2723/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2724#define X86_PDE4M_PS RT_BIT_32(7)
2725/** Bit 8 - G - Global flag. */
2726#define X86_PDE4M_G RT_BIT_32(8)
2727/** Bits 9-11 - AVL - Available for use to system software. */
2728#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2729/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2730#define X86_PDE4M_PAT RT_BIT_32(12)
2731/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2732#define X86_PDE4M_PAT_SHIFT (12 - 7)
2733/** Bits 22-31 - - Physical Page number. */
2734#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2735/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2736#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2737/** The number of bits to the high part of the page number. */
2738#define X86_PDE4M_PG_HIGH_SHIFT 19
2739/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2740#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2741
2742/** Bits 21-51 - - PAE/LM - Physical Page number.
2743 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2744#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2745/** Bits 63 - NX - PAE/LM - No execution flag. */
2746#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2747/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2748#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2749/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2750#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2751/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2752#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2753/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2754#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2755
2756#ifndef __ASSEMBLER__
2757
2758/**
2759 * 4MB page directory entry.
2760 */
2761typedef struct X86PDE4MBITS
2762{
2763 /** Flags whether(=1) or not the page is present. */
2764 uint32_t u1Present : 1;
2765 /** Read(=0) / Write(=1) flag. */
2766 uint32_t u1Write : 1;
2767 /** User(=1) / Supervisor (=0) flag. */
2768 uint32_t u1User : 1;
2769 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2770 uint32_t u1WriteThru : 1;
2771 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2772 uint32_t u1CacheDisable : 1;
2773 /** Accessed flag.
2774 * Indicates that the page have been read or written to. */
2775 uint32_t u1Accessed : 1;
2776 /** Dirty flag.
2777 * Indicates that the page has been written to. */
2778 uint32_t u1Dirty : 1;
2779 /** Page size flag - always 1 for 4MB entries. */
2780 uint32_t u1Size : 1;
2781 /** Global flag. */
2782 uint32_t u1Global : 1;
2783 /** Available for use to system software. */
2784 uint32_t u3Available : 3;
2785 /** Reserved / If PAT enabled, bit 2 of the index. */
2786 uint32_t u1PAT : 1;
2787 /** Bits 32-39 of the page number on AMD64.
2788 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2789 uint32_t u8PageNoHigh : 8;
2790 /** Reserved. */
2791 uint32_t u1Reserved : 1;
2792 /** Physical Page number of the page. */
2793 uint32_t u10PageNo : 10;
2794} X86PDE4MBITS;
2795# ifndef VBOX_FOR_DTRACE_LIB
2796AssertCompileSize(X86PDE4MBITS, 4);
2797# endif
2798/** Pointer to a page table entry. */
2799typedef X86PDE4MBITS *PX86PDE4MBITS;
2800/** Pointer to a const page table entry. */
2801typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2802
2803
2804/**
2805 * 2MB PAE page directory entry.
2806 */
2807typedef struct X86PDE2MPAEBITS
2808{
2809 /** Flags whether(=1) or not the page is present. */
2810 uint32_t u1Present : 1;
2811 /** Read(=0) / Write(=1) flag. */
2812 uint32_t u1Write : 1;
2813 /** User(=1) / Supervisor(=0) flag. */
2814 uint32_t u1User : 1;
2815 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2816 uint32_t u1WriteThru : 1;
2817 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2818 uint32_t u1CacheDisable : 1;
2819 /** Accessed flag.
2820 * Indicates that the page have been read or written to. */
2821 uint32_t u1Accessed : 1;
2822 /** Dirty flag.
2823 * Indicates that the page has been written to. */
2824 uint32_t u1Dirty : 1;
2825 /** Page size flag - always 1 for 2MB entries. */
2826 uint32_t u1Size : 1;
2827 /** Global flag. */
2828 uint32_t u1Global : 1;
2829 /** Available for use to system software. */
2830 uint32_t u3Available : 3;
2831 /** Reserved / If PAT enabled, bit 2 of the index. */
2832 uint32_t u1PAT : 1;
2833 /** Reserved. */
2834 uint32_t u9Reserved : 9;
2835 /** Physical Page number of the next level - Low part. Don't use! */
2836 uint32_t u10PageNoLow : 10;
2837 /** Physical Page number of the next level - High part. Don't use! */
2838 uint32_t u20PageNoHigh : 20;
2839 /** MBZ bits */
2840 uint32_t u11Reserved : 11;
2841 /** No Execute flag. */
2842 uint32_t u1NoExecute : 1;
2843} X86PDE2MPAEBITS;
2844# ifndef VBOX_FOR_DTRACE_LIB
2845AssertCompileSize(X86PDE2MPAEBITS, 8);
2846# endif
2847/** Pointer to a 2MB PAE page table entry. */
2848typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2849/** Pointer to a 2MB PAE page table entry. */
2850typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2851
2852#endif /* !__ASSEMBLER__ */
2853
2854/** @} */
2855
2856#ifndef __ASSEMBLER__
2857
2858/**
2859 * Page directory entry.
2860 */
2861typedef union X86PDE
2862{
2863 /** Unsigned integer view. */
2864 X86PGUINT u;
2865# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2866 /** Normal view. */
2867 X86PDEBITS n;
2868 /** 4MB view (big). */
2869 X86PDE4MBITS b;
2870# endif
2871 /** 8 bit unsigned integer view. */
2872 uint8_t au8[4];
2873 /** 16 bit unsigned integer view. */
2874 uint16_t au16[2];
2875 /** 32 bit unsigned integer view. */
2876 uint32_t au32[1];
2877} X86PDE;
2878# ifndef VBOX_FOR_DTRACE_LIB
2879AssertCompileSize(X86PDE, 4);
2880# endif
2881/** Pointer to a page directory entry. */
2882typedef X86PDE *PX86PDE;
2883/** Pointer to a const page directory entry. */
2884typedef const X86PDE *PCX86PDE;
2885
2886/**
2887 * PAE page directory entry.
2888 */
2889typedef union X86PDEPAE
2890{
2891 /** Unsigned integer view. */
2892 X86PGPAEUINT u;
2893# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2894 /** Normal view. */
2895 X86PDEPAEBITS n;
2896 /** 2MB page view (big). */
2897 X86PDE2MPAEBITS b;
2898# endif
2899 /** 8 bit unsigned integer view. */
2900 uint8_t au8[8];
2901 /** 16 bit unsigned integer view. */
2902 uint16_t au16[4];
2903 /** 32 bit unsigned integer view. */
2904 uint32_t au32[2];
2905} X86PDEPAE;
2906# ifndef VBOX_FOR_DTRACE_LIB
2907AssertCompileSize(X86PDEPAE, 8);
2908# endif
2909/** Pointer to a page directory entry. */
2910typedef X86PDEPAE *PX86PDEPAE;
2911/** Pointer to a const page directory entry. */
2912typedef const X86PDEPAE *PCX86PDEPAE;
2913
2914/**
2915 * Page directory.
2916 */
2917typedef struct X86PD
2918{
2919 /** PDE Array. */
2920 X86PDE a[X86_PG_ENTRIES];
2921} X86PD;
2922# ifndef VBOX_FOR_DTRACE_LIB
2923AssertCompileSize(X86PD, 4096);
2924# endif
2925/** Pointer to a page directory. */
2926typedef X86PD *PX86PD;
2927/** Pointer to a const page directory. */
2928typedef const X86PD *PCX86PD;
2929
2930#endif /* !__ASSEMBLER__ */
2931
2932/** The page shift to get the PD index. */
2933#define X86_PD_SHIFT 22
2934/** The PD index mask (apply to a shifted page address). */
2935#define X86_PD_MASK 0x3ff
2936
2937
2938#ifndef __ASSEMBLER__
2939/**
2940 * PAE page directory.
2941 */
2942typedef struct X86PDPAE
2943{
2944 /** PDE Array. */
2945 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2946} X86PDPAE;
2947# ifndef VBOX_FOR_DTRACE_LIB
2948AssertCompileSize(X86PDPAE, 4096);
2949# endif
2950/** Pointer to a PAE page directory. */
2951typedef X86PDPAE *PX86PDPAE;
2952/** Pointer to a const PAE page directory. */
2953typedef const X86PDPAE *PCX86PDPAE;
2954#endif /* !__ASSEMBLER__ */
2955
2956/** The page shift to get the PAE PD index. */
2957#define X86_PD_PAE_SHIFT 21
2958/** The PAE PD index mask (apply to a shifted page address). */
2959#define X86_PD_PAE_MASK 0x1ff
2960
2961
2962/** @name Page Directory Pointer Table Entry (PAE)
2963 * @{
2964 */
2965/** Bit 0 - P - Present bit. */
2966#define X86_PDPE_P RT_BIT_32(0)
2967/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2968#define X86_PDPE_RW RT_BIT_32(1)
2969/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2970#define X86_PDPE_US RT_BIT_32(2)
2971/** Bit 3 - PWT - Page level write thru bit. */
2972#define X86_PDPE_PWT RT_BIT_32(3)
2973/** Bit 4 - PCD - Page level cache disable bit. */
2974#define X86_PDPE_PCD RT_BIT_32(4)
2975/** Bit 5 - A - Access bit. Long Mode only. */
2976#define X86_PDPE_A RT_BIT_32(5)
2977/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2978#define X86_PDPE_LM_PS RT_BIT_32(7)
2979/** Bits 9-11 - - Available for use to system software. */
2980#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2981/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2982#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2983/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2984#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2985/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2986#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2987/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2988#define X86_PDPE_LM_NX RT_BIT_64(63)
2989/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2990#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2991/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2992#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2993/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2994#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2995/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2996#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2997
2998#ifndef __ASSEMBLER__
2999
3000/**
3001 * Page directory pointer table entry.
3002 */
3003typedef struct X86PDPEBITS
3004{
3005 /** Flags whether(=1) or not the page is present. */
3006 uint32_t u1Present : 1;
3007 /** Chunk of reserved bits. */
3008 uint32_t u2Reserved : 2;
3009 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
3010 uint32_t u1WriteThru : 1;
3011 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3012 uint32_t u1CacheDisable : 1;
3013 /** Chunk of reserved bits. */
3014 uint32_t u4Reserved : 4;
3015 /** Available for use to system software. */
3016 uint32_t u3Available : 3;
3017 /** Physical Page number of the next level - Low Part. Don't use! */
3018 uint32_t u20PageNoLow : 20;
3019 /** Physical Page number of the next level - High Part. Don't use! */
3020 uint32_t u20PageNoHigh : 20;
3021 /** MBZ bits */
3022 uint32_t u12Reserved : 12;
3023} X86PDPEBITS;
3024# ifndef VBOX_FOR_DTRACE_LIB
3025AssertCompileSize(X86PDPEBITS, 8);
3026# endif
3027/** Pointer to a page directory pointer table entry. */
3028typedef X86PDPEBITS *PX86PTPEBITS;
3029/** Pointer to a const page directory pointer table entry. */
3030typedef const X86PDPEBITS *PCX86PTPEBITS;
3031
3032/**
3033 * Page directory pointer table entry. AMD64 version
3034 */
3035typedef struct X86PDPEAMD64BITS
3036{
3037 /** Flags whether(=1) or not the page is present. */
3038 uint32_t u1Present : 1;
3039 /** Read(=0) / Write(=1) flag. */
3040 uint32_t u1Write : 1;
3041 /** User(=1) / Supervisor (=0) flag. */
3042 uint32_t u1User : 1;
3043 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
3044 uint32_t u1WriteThru : 1;
3045 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3046 uint32_t u1CacheDisable : 1;
3047 /** Accessed flag.
3048 * Indicates that the page have been read or written to. */
3049 uint32_t u1Accessed : 1;
3050 /** Chunk of reserved bits. */
3051 uint32_t u3Reserved : 3;
3052 /** Available for use to system software. */
3053 uint32_t u3Available : 3;
3054 /** Physical Page number of the next level - Low Part. Don't use! */
3055 uint32_t u20PageNoLow : 20;
3056 /** Physical Page number of the next level - High Part. Don't use! */
3057 uint32_t u20PageNoHigh : 20;
3058 /** MBZ bits */
3059 uint32_t u11Reserved : 11;
3060 /** No Execute flag. */
3061 uint32_t u1NoExecute : 1;
3062} X86PDPEAMD64BITS;
3063# ifndef VBOX_FOR_DTRACE_LIB
3064AssertCompileSize(X86PDPEAMD64BITS, 8);
3065# endif
3066/** Pointer to a page directory pointer table entry. */
3067typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
3068/** Pointer to a const page directory pointer table entry. */
3069typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
3070
3071/**
3072 * Page directory pointer table entry for 1GB page. (AMD64 only)
3073 */
3074typedef struct X86PDPE1GB
3075{
3076 /** 0: Flags whether(=1) or not the page is present. */
3077 uint32_t u1Present : 1;
3078 /** 1: Read(=0) / Write(=1) flag. */
3079 uint32_t u1Write : 1;
3080 /** 2: User(=1) / Supervisor (=0) flag. */
3081 uint32_t u1User : 1;
3082 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
3083 uint32_t u1WriteThru : 1;
3084 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
3085 uint32_t u1CacheDisable : 1;
3086 /** 5: Accessed flag.
3087 * Indicates that the page have been read or written to. */
3088 uint32_t u1Accessed : 1;
3089 /** 6: Dirty flag for 1GB pages. */
3090 uint32_t u1Dirty : 1;
3091 /** 7: Indicates 1GB page if set. */
3092 uint32_t u1Size : 1;
3093 /** 8: Global 1GB page. */
3094 uint32_t u1Global: 1;
3095 /** 9-11: Available for use to system software. */
3096 uint32_t u3Available : 3;
3097 /** 12: PAT bit for 1GB page. */
3098 uint32_t u1PAT : 1;
3099 /** 13-29: MBZ bits. */
3100 uint32_t u17Reserved : 17;
3101 /** 30-31: Physical page number - Low Part. Don't use! */
3102 uint32_t u2PageNoLow : 2;
3103 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
3104 uint32_t u20PageNoHigh : 20;
3105 /** 52-62: MBZ bits */
3106 uint32_t u11Reserved : 11;
3107 /** 63: No Execute flag. */
3108 uint32_t u1NoExecute : 1;
3109} X86PDPE1GB;
3110# ifndef VBOX_FOR_DTRACE_LIB
3111AssertCompileSize(X86PDPE1GB, 8);
3112# endif
3113/** Pointer to a page directory pointer table entry for a 1GB page. */
3114typedef X86PDPE1GB *PX86PDPE1GB;
3115/** Pointer to a const page directory pointer table entry for a 1GB page. */
3116typedef const X86PDPE1GB *PCX86PDPE1GB;
3117
3118/**
3119 * Page directory pointer table entry.
3120 */
3121typedef union X86PDPE
3122{
3123 /** Unsigned integer view. */
3124 X86PGPAEUINT u;
3125# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3126 /** Normal view. */
3127 X86PDPEBITS n;
3128 /** AMD64 view. */
3129 X86PDPEAMD64BITS lm;
3130 /** AMD64 big view. */
3131 X86PDPE1GB b;
3132# endif
3133 /** 8 bit unsigned integer view. */
3134 uint8_t au8[8];
3135 /** 16 bit unsigned integer view. */
3136 uint16_t au16[4];
3137 /** 32 bit unsigned integer view. */
3138 uint32_t au32[2];
3139} X86PDPE;
3140# ifndef VBOX_FOR_DTRACE_LIB
3141AssertCompileSize(X86PDPE, 8);
3142# endif
3143/** Pointer to a page directory pointer table entry. */
3144typedef X86PDPE *PX86PDPE;
3145/** Pointer to a const page directory pointer table entry. */
3146typedef const X86PDPE *PCX86PDPE;
3147
3148
3149/**
3150 * Page directory pointer table.
3151 */
3152typedef struct X86PDPT
3153{
3154 /** PDE Array. */
3155 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
3156} X86PDPT;
3157# ifndef VBOX_FOR_DTRACE_LIB
3158AssertCompileSize(X86PDPT, 4096);
3159# endif
3160/** Pointer to a page directory pointer table. */
3161typedef X86PDPT *PX86PDPT;
3162/** Pointer to a const page directory pointer table. */
3163typedef const X86PDPT *PCX86PDPT;
3164
3165#endif /* !__ASSEMBLER__ */
3166
3167/** The page shift to get the PDPT index. */
3168#define X86_PDPT_SHIFT 30
3169/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
3170#define X86_PDPT_MASK_PAE 0x3
3171/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
3172#define X86_PDPT_MASK_AMD64 0x1ff
3173
3174/** @} */
3175
3176
3177/** @name Page Map Level-4 Entry (Long Mode PAE)
3178 * @{
3179 */
3180/** Bit 0 - P - Present bit. */
3181#define X86_PML4E_P RT_BIT_32(0)
3182/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
3183#define X86_PML4E_RW RT_BIT_32(1)
3184/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
3185#define X86_PML4E_US RT_BIT_32(2)
3186/** Bit 3 - PWT - Page level write thru bit. */
3187#define X86_PML4E_PWT RT_BIT_32(3)
3188/** Bit 4 - PCD - Page level cache disable bit. */
3189#define X86_PML4E_PCD RT_BIT_32(4)
3190/** Bit 5 - A - Access bit. */
3191#define X86_PML4E_A RT_BIT_32(5)
3192/** Bits 9-11 - - Available for use to system software. */
3193#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3194/** Bits 12-51 - - PAE - Physical Page number of the next level. */
3195#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
3196/** Bits 8, 7 - - MBZ bits when NX is active. */
3197#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
3198/** Bits 63, 7 - - MBZ bits when no NX. */
3199#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
3200/** Bits 63 - NX - PAE - No execution flag. */
3201#define X86_PML4E_NX RT_BIT_64(63)
3202
3203#ifndef __ASSEMBLER__
3204
3205/**
3206 * Page Map Level-4 Entry
3207 */
3208typedef struct X86PML4EBITS
3209{
3210 /** Flags whether(=1) or not the page is present. */
3211 uint32_t u1Present : 1;
3212 /** Read(=0) / Write(=1) flag. */
3213 uint32_t u1Write : 1;
3214 /** User(=1) / Supervisor (=0) flag. */
3215 uint32_t u1User : 1;
3216 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
3217 uint32_t u1WriteThru : 1;
3218 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
3219 uint32_t u1CacheDisable : 1;
3220 /** Accessed flag.
3221 * Indicates that the page have been read or written to. */
3222 uint32_t u1Accessed : 1;
3223 /** Chunk of reserved bits. */
3224 uint32_t u3Reserved : 3;
3225 /** Available for use to system software. */
3226 uint32_t u3Available : 3;
3227 /** Physical Page number of the next level - Low Part. Don't use! */
3228 uint32_t u20PageNoLow : 20;
3229 /** Physical Page number of the next level - High Part. Don't use! */
3230 uint32_t u20PageNoHigh : 20;
3231 /** MBZ bits */
3232 uint32_t u11Reserved : 11;
3233 /** No Execute flag. */
3234 uint32_t u1NoExecute : 1;
3235} X86PML4EBITS;
3236# ifndef VBOX_FOR_DTRACE_LIB
3237AssertCompileSize(X86PML4EBITS, 8);
3238# endif
3239/** Pointer to a page map level-4 entry. */
3240typedef X86PML4EBITS *PX86PML4EBITS;
3241/** Pointer to a const page map level-4 entry. */
3242typedef const X86PML4EBITS *PCX86PML4EBITS;
3243
3244/**
3245 * Page Map Level-4 Entry.
3246 */
3247typedef union X86PML4E
3248{
3249 /** Unsigned integer view. */
3250 X86PGPAEUINT u;
3251# ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
3252 /** Normal view. */
3253 X86PML4EBITS n;
3254# endif
3255 /** 8 bit unsigned integer view. */
3256 uint8_t au8[8];
3257 /** 16 bit unsigned integer view. */
3258 uint16_t au16[4];
3259 /** 32 bit unsigned integer view. */
3260 uint32_t au32[2];
3261} X86PML4E;
3262# ifndef VBOX_FOR_DTRACE_LIB
3263AssertCompileSize(X86PML4E, 8);
3264# endif
3265/** Pointer to a page map level-4 entry. */
3266typedef X86PML4E *PX86PML4E;
3267/** Pointer to a const page map level-4 entry. */
3268typedef const X86PML4E *PCX86PML4E;
3269
3270
3271/**
3272 * Page Map Level-4.
3273 */
3274typedef struct X86PML4
3275{
3276 /** PDE Array. */
3277 X86PML4E a[X86_PG_PAE_ENTRIES];
3278} X86PML4;
3279# ifndef VBOX_FOR_DTRACE_LIB
3280AssertCompileSize(X86PML4, 4096);
3281# endif
3282/** Pointer to a page map level-4. */
3283typedef X86PML4 *PX86PML4;
3284/** Pointer to a const page map level-4. */
3285typedef const X86PML4 *PCX86PML4;
3286
3287#endif /* !__ASSEMBLER__ */
3288
3289/** The page shift to get the PML4 index. */
3290#define X86_PML4_SHIFT 39
3291/** The PML4 index mask (apply to a shifted page address). */
3292#define X86_PML4_MASK 0x1ff
3293
3294/** @} */
3295
3296/** @} */
3297
3298/**
3299 * Intel PCID invalidation types.
3300 */
3301/** Individual address invalidation. */
3302#define X86_INVPCID_TYPE_INDV_ADDR 0
3303/** Single-context invalidation. */
3304#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3305/** All-context including globals invalidation. */
3306#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3307/** All-context excluding globals invalidation. */
3308#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3309/** The maximum valid invalidation type value. */
3310#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3311
3312
3313/** @name Special FPU integer values.
3314 * @{ */
3315#define X86_FPU_INT64_INDEFINITE INT64_MIN
3316#define X86_FPU_INT32_INDEFINITE INT32_MIN
3317#define X86_FPU_INT16_INDEFINITE INT16_MIN
3318/** @} */
3319
3320#ifndef __ASSEMBLER__
3321
3322/**
3323 * 32-bit protected mode FSTENV image.
3324 */
3325typedef struct X86FSTENV32P
3326{
3327 uint16_t FCW; /**< 0x00 */
3328 uint16_t padding1; /**< 0x02 */
3329 uint16_t FSW; /**< 0x04 */
3330 uint16_t padding2; /**< 0x06 */
3331 uint16_t FTW; /**< 0x08 */
3332 uint16_t padding3; /**< 0x0a */
3333 uint32_t FPUIP; /**< 0x0c */
3334 uint16_t FPUCS; /**< 0x10 */
3335 uint16_t FOP; /**< 0x12 */
3336 uint32_t FPUDP; /**< 0x14 */
3337 uint16_t FPUDS; /**< 0x18 */
3338 uint16_t padding4; /**< 0x1a */
3339} X86FSTENV32P;
3340# ifndef VBOX_FOR_DTRACE_LIB
3341AssertCompileSize(X86FSTENV32P, 0x1c);
3342# endif
3343/** Pointer to a 32-bit protected mode FSTENV image. */
3344typedef X86FSTENV32P *PX86FSTENV32P;
3345/** Pointer to a const 32-bit protected mode FSTENV image. */
3346typedef X86FSTENV32P const *PCX86FSTENV32P;
3347
3348
3349/**
3350 * 80-bit MMX/FPU register type.
3351 */
3352typedef struct X86FPUMMX
3353{
3354 uint8_t reg[10];
3355} X86FPUMMX;
3356# ifndef VBOX_FOR_DTRACE_LIB
3357AssertCompileSize(X86FPUMMX, 10);
3358# endif
3359/** Pointer to a 80-bit MMX/FPU register type. */
3360typedef X86FPUMMX *PX86FPUMMX;
3361/** Pointer to a const 80-bit MMX/FPU register type. */
3362typedef const X86FPUMMX *PCX86FPUMMX;
3363
3364/** FPU (x87) register. */
3365typedef union X86FPUREG
3366{
3367 /** MMX view. */
3368 uint64_t mmx;
3369 /** FPU view - todo. */
3370 X86FPUMMX fpu;
3371 /** Extended precision floating point view. */
3372 RTFLOAT80U r80;
3373 /** Extended precision floating point view v2 */
3374 RTFLOAT80U2 r80Ex;
3375 /** 8-bit view. */
3376 uint8_t au8[16];
3377 /** 16-bit view. */
3378 uint16_t au16[8];
3379 /** 32-bit view. */
3380 uint32_t au32[4];
3381 /** 64-bit view. */
3382 uint64_t au64[2];
3383 /** 128-bit view. (yeah, very helpful) */
3384 uint128_t au128[1];
3385} X86FPUREG;
3386# ifndef VBOX_FOR_DTRACE_LIB
3387AssertCompileSize(X86FPUREG, 16);
3388# endif
3389/** Pointer to a FPU register. */
3390typedef X86FPUREG *PX86FPUREG;
3391/** Pointer to a const FPU register. */
3392typedef X86FPUREG const *PCX86FPUREG;
3393
3394/** FPU (x87) register - v2 with correct size. */
3395# pragma pack(1)
3396typedef union X86FPUREG2
3397{
3398 /** MMX view. */
3399 uint64_t mmx;
3400 /** FPU view - todo. */
3401 X86FPUMMX fpu;
3402 /** Extended precision floating point view. */
3403 RTFLOAT80U r80;
3404 /** 8-bit view. */
3405 uint8_t au8[10];
3406 /** 16-bit view. */
3407 uint16_t au16[5];
3408 /** 32-bit view. */
3409 uint32_t au32[2];
3410 /** 64-bit view. */
3411 uint64_t au64[1];
3412} X86FPUREG2;
3413# pragma pack()
3414# ifndef VBOX_FOR_DTRACE_LIB
3415AssertCompileSize(X86FPUREG2, 10);
3416# endif
3417/** Pointer to a FPU register - v2. */
3418typedef X86FPUREG2 *PX86FPUREG2;
3419/** Pointer to a const FPU register - v2. */
3420typedef X86FPUREG2 const *PCX86FPUREG2;
3421
3422/**
3423 * XMM register union.
3424 */
3425typedef union X86XMMREG
3426{
3427 /** XMM Register view. */
3428 uint128_t xmm;
3429 /** 8-bit view. */
3430 uint8_t au8[16];
3431 /** 16-bit view. */
3432 uint16_t au16[8];
3433 /** 32-bit view. */
3434 uint32_t au32[4];
3435 /** 64-bit view. */
3436 uint64_t au64[2];
3437 /** Signed 8-bit view. */
3438 int8_t ai8[16];
3439 /** Signed 16-bit view. */
3440 int16_t ai16[8];
3441 /** Signed 32-bit view. */
3442 int32_t ai32[4];
3443 /** Signed 64-bit view. */
3444 int64_t ai64[2];
3445 /** 128-bit view. (yeah, very helpful) */
3446 uint128_t au128[1];
3447 /** Single precision floating point view. */
3448 RTFLOAT32U ar32[4];
3449 /** Double precision floating point view. */
3450 RTFLOAT64U ar64[2];
3451# ifndef VBOX_FOR_DTRACE_LIB
3452 /** Confusing nested 128-bit union view (this is what xmm should've been). */
3453 RTUINT128U uXmm;
3454# endif
3455} X86XMMREG;
3456# ifndef VBOX_FOR_DTRACE_LIB
3457AssertCompileSize(X86XMMREG, 16);
3458# endif
3459/** Pointer to an XMM register state. */
3460typedef X86XMMREG *PX86XMMREG;
3461/** Pointer to a const XMM register state. */
3462typedef X86XMMREG const *PCX86XMMREG;
3463
3464/**
3465 * YMM register union.
3466 */
3467typedef union X86YMMREG
3468{
3469 /** YMM register view. */
3470 RTUINT256U ymm;
3471 /** 8-bit view. */
3472 uint8_t au8[32];
3473 /** 16-bit view. */
3474 uint16_t au16[16];
3475 /** 32-bit view. */
3476 uint32_t au32[8];
3477 /** 64-bit view. */
3478 uint64_t au64[4];
3479 /** 128-bit view. (yeah, very helpful) */
3480 uint128_t au128[2];
3481 /** Single precision floating point view. */
3482 RTFLOAT32U ar32[8];
3483 /** Double precision floating point view. */
3484 RTFLOAT64U ar64[4];
3485 /** XMM sub register view. */
3486 X86XMMREG aXmm[2];
3487} X86YMMREG;
3488# ifndef VBOX_FOR_DTRACE_LIB
3489AssertCompileSize(X86YMMREG, 32);
3490# endif
3491/** Pointer to an YMM register state. */
3492typedef X86YMMREG *PX86YMMREG;
3493/** Pointer to a const YMM register state. */
3494typedef X86YMMREG const *PCX86YMMREG;
3495
3496/**
3497 * ZMM register union.
3498 */
3499typedef union X86ZMMREG
3500{
3501 /** 8-bit view. */
3502 uint8_t au8[64];
3503 /** 16-bit view. */
3504 uint16_t au16[32];
3505 /** 32-bit view. */
3506 uint32_t au32[16];
3507 /** 64-bit view. */
3508 uint64_t au64[8];
3509 /** 128-bit view. (yeah, very helpful) */
3510 uint128_t au128[4];
3511 /** Single precision floating point view. */
3512 RTFLOAT32U ar32[16];
3513 /** Double precision floating point view. */
3514 RTFLOAT64U ar64[8];
3515 /** XMM sub register view. */
3516 X86XMMREG aXmm[4];
3517 /** YMM sub register view. */
3518 X86YMMREG aYmm[2];
3519} X86ZMMREG;
3520# ifndef VBOX_FOR_DTRACE_LIB
3521AssertCompileSize(X86ZMMREG, 64);
3522# endif
3523/** Pointer to an ZMM register state. */
3524typedef X86ZMMREG *PX86ZMMREG;
3525/** Pointer to a const ZMM register state. */
3526typedef X86ZMMREG const *PCX86ZMMREG;
3527
3528
3529/**
3530 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3531 */
3532# pragma pack(1)
3533typedef struct X86FPUSTATE
3534{
3535 /** 0x00 - Control word. */
3536 uint16_t FCW;
3537 /** 0x02 - Alignment word */
3538 uint16_t Dummy1;
3539 /** 0x04 - Status word. */
3540 uint16_t FSW;
3541 /** 0x06 - Alignment word */
3542 uint16_t Dummy2;
3543 /** 0x08 - Tag word */
3544 uint16_t FTW;
3545 /** 0x0a - Alignment word */
3546 uint16_t Dummy3;
3547
3548 /** 0x0c - Instruction pointer. */
3549 uint32_t FPUIP;
3550 /** 0x10 - Code selector. */
3551 uint16_t CS;
3552 /** 0x12 - Opcode. */
3553 uint16_t FOP;
3554 /** 0x14 - Data pointer. */
3555 uint32_t FPUOO;
3556 /** 0x18 - FOS. */
3557 uint16_t FPUOS;
3558 /** 0x0a - Alignment word */
3559 uint16_t Dummy4;
3560 /** 0x1c - FPU register. */
3561 X86FPUREG2 regs[8];
3562} X86FPUSTATE;
3563# pragma pack()
3564AssertCompileSize(X86FPUSTATE, 108);
3565/** Pointer to a FPU state. */
3566typedef X86FPUSTATE *PX86FPUSTATE;
3567/** Pointer to a const FPU state. */
3568typedef const X86FPUSTATE *PCX86FPUSTATE;
3569
3570/**
3571 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3572 */
3573# pragma pack(1)
3574typedef struct X86FXSTATE
3575{
3576 /** 0x00 - Control word. */
3577 uint16_t FCW;
3578 /** 0x02 - Status word. */
3579 uint16_t FSW;
3580 /** 0x04 - Tag word. (The upper byte is always zero.) */
3581 uint16_t FTW;
3582 /** 0x06 - Opcode. */
3583 uint16_t FOP;
3584 /** 0x08 - Instruction pointer. */
3585 uint32_t FPUIP;
3586 /** 0x0c - Code selector. */
3587 uint16_t CS;
3588 uint16_t Rsrvd1;
3589 /** 0x10 - Data pointer. */
3590 uint32_t FPUDP;
3591 /** 0x14 - Data segment */
3592 uint16_t DS;
3593 /** 0x16 */
3594 uint16_t Rsrvd2;
3595 /** 0x18 */
3596 uint32_t MXCSR;
3597 /** 0x1c */
3598 uint32_t MXCSR_MASK;
3599 /** 0x20 - FPU registers. */
3600 X86FPUREG aRegs[8];
3601 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3602 X86XMMREG aXMM[16];
3603 /* - offset 416 - */
3604 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3605 /* - offset 464 - Software usable reserved bits. */
3606 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3607} X86FXSTATE;
3608# pragma pack()
3609/** Pointer to a FPU Extended state. */
3610typedef X86FXSTATE *PX86FXSTATE;
3611/** Pointer to a const FPU Extended state. */
3612typedef const X86FXSTATE *PCX86FXSTATE;
3613
3614#endif /* !__ASSEMBLER__ */
3615
3616
3617/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3618 * magic. Don't forget to update x86.mac if you change this! */
3619#define X86_OFF_FXSTATE_RSVD 0x1d0
3620/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3621 * forget to update x86.mac if you change this!
3622 * @todo r=bird: This has nothing what-so-ever to do here.... */
3623#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3624#ifndef VBOX_FOR_DTRACE_LIB
3625AssertCompileSize(X86FXSTATE, 512);
3626AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3627#endif
3628
3629/** @name FPU status word flags.
3630 * @{ */
3631/** Exception Flag: Invalid operation. */
3632#define X86_FSW_IE RT_BIT_32(0)
3633#define X86_FSW_IE_BIT 0
3634/** Exception Flag: Denormalized operand. */
3635#define X86_FSW_DE RT_BIT_32(1)
3636#define X86_FSW_DE_BIT 1
3637/** Exception Flag: Zero divide. */
3638#define X86_FSW_ZE RT_BIT_32(2)
3639#define X86_FSW_ZE_BIT 2
3640/** Exception Flag: Overflow. */
3641#define X86_FSW_OE RT_BIT_32(3)
3642#define X86_FSW_OE_BIT 3
3643/** Exception Flag: Underflow. */
3644#define X86_FSW_UE RT_BIT_32(4)
3645#define X86_FSW_UE_BIT 4
3646/** Exception Flag: Precision. */
3647#define X86_FSW_PE RT_BIT_32(5)
3648#define X86_FSW_PE_BIT 5
3649/** Stack fault. */
3650#define X86_FSW_SF RT_BIT_32(6)
3651#define X86_FSW_SF_BIT 6
3652/** Error summary status. */
3653#define X86_FSW_ES RT_BIT_32(7)
3654#define X86_FSW_ES_BIT 7
3655/** Mask of exceptions flags, excluding the summary bit. */
3656#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3657/** Mask of exceptions flags, including the summary bit. */
3658#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3659/** Condition code 0. */
3660#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3661#define X86_FSW_C0_BIT 8
3662/** Condition code 1. */
3663#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3664#define X86_FSW_C1_BIT 9
3665/** Condition code 2. */
3666#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3667#define X86_FSW_C2_BIT 10
3668/** Top of the stack mask. */
3669#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3670/** TOP shift value. */
3671#define X86_FSW_TOP_SHIFT 11
3672/** Mask for getting TOP value after shifting it right. */
3673#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3674/** Get the TOP value. */
3675#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3676/** Get the TOP value offsetted by a_iSt (0-7). */
3677#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3678/** Condition code 3. */
3679#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3680#define X86_FSW_C3_BIT 14
3681/** Mask of exceptions flags, including the summary bit. */
3682#define X86_FSW_C_MASK UINT16_C(0x4700)
3683/** FPU busy. */
3684#define X86_FSW_B RT_BIT_32(15)
3685/** For use with FPREM and FPREM1. */
3686#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3687 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3688 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3689 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3690/** For use with FPREM and FPREM1. */
3691#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3692 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3693 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3694 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3695/** @} */
3696
3697
3698/** @name FPU control word flags.
3699 * @{ */
3700/** Exception Mask: Invalid operation. */
3701#define X86_FCW_IM RT_BIT_32(0)
3702#define X86_FCW_IM_BIT 0
3703/** Exception Mask: Denormalized operand. */
3704#define X86_FCW_DM RT_BIT_32(1)
3705#define X86_FCW_DM_BIT 1
3706/** Exception Mask: Zero divide. */
3707#define X86_FCW_ZM RT_BIT_32(2)
3708#define X86_FCW_ZM_BIT 2
3709/** Exception Mask: Overflow. */
3710#define X86_FCW_OM RT_BIT_32(3)
3711#define X86_FCW_OM_BIT 3
3712/** Exception Mask: Underflow. */
3713#define X86_FCW_UM RT_BIT_32(4)
3714#define X86_FCW_UM_BIT 4
3715/** Exception Mask: Precision. */
3716#define X86_FCW_PM RT_BIT_32(5)
3717#define X86_FCW_PM_BIT 5
3718/** Mask all exceptions, the value typically loaded (by for instance fninit).
3719 * @remarks This includes reserved bit 6. */
3720#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3721/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3722#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3723/** Precision control mask. */
3724#define X86_FCW_PC_MASK UINT16_C(0x0300)
3725/** Precision control shift. */
3726#define X86_FCW_PC_SHIFT 8
3727/** Precision control: 24-bit. */
3728#define X86_FCW_PC_24 UINT16_C(0x0000)
3729/** Precision control: Reserved. */
3730#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3731/** Precision control: 53-bit. */
3732#define X86_FCW_PC_53 UINT16_C(0x0200)
3733/** Precision control: 64-bit. */
3734#define X86_FCW_PC_64 UINT16_C(0x0300)
3735/** Rounding control mask. */
3736#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3737/** Rounding control shift. */
3738#define X86_FCW_RC_SHIFT 10
3739/** Rounding control: To nearest. */
3740#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3741/** Rounding control: Down. */
3742#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3743/** Rounding control: Up. */
3744#define X86_FCW_RC_UP UINT16_C(0x0800)
3745/** Rounding control: Towards zero. */
3746#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3747/** Infinity control mask - obsolete, 8087 & 287 only. */
3748#define X86_FCW_IC_MASK UINT16_C(0x1000)
3749/** Infinity control: Affine - positive infinity is distictly different from
3750 * negative infinity.
3751 * @note 8087, 287 only */
3752#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3753/** Infinity control: Projective - positive and negative infinity are the
3754 * same (sign ignored).
3755 * @note 8087, 287 only */
3756#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3757/** Bits which should be zero, apparently. */
3758#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3759/** @} */
3760
3761/** @name SSE MXCSR
3762 * @{ */
3763/** Exception Flag: Invalid operation. */
3764#define X86_MXCSR_IE RT_BIT_32(0)
3765/** Exception Flag: Denormalized operand. */
3766#define X86_MXCSR_DE RT_BIT_32(1)
3767/** Exception Flag: Zero divide. */
3768#define X86_MXCSR_ZE RT_BIT_32(2)
3769/** Exception Flag: Overflow. */
3770#define X86_MXCSR_OE RT_BIT_32(3)
3771/** Exception Flag: Underflow. */
3772#define X86_MXCSR_UE RT_BIT_32(4)
3773/** Exception Flag: Precision. */
3774#define X86_MXCSR_PE RT_BIT_32(5)
3775/** Exception Flags: mask */
3776#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3777
3778/** Denormals are zero. */
3779#define X86_MXCSR_DAZ RT_BIT_32(6)
3780
3781/** Exception Mask: Invalid operation. */
3782#define X86_MXCSR_IM RT_BIT_32(7)
3783/** Exception Mask: Denormalized operand. */
3784#define X86_MXCSR_DM RT_BIT_32(8)
3785/** Exception Mask: Zero divide. */
3786#define X86_MXCSR_ZM RT_BIT_32(9)
3787/** Exception Mask: Overflow. */
3788#define X86_MXCSR_OM RT_BIT_32(10)
3789/** Exception Mask: Underflow. */
3790#define X86_MXCSR_UM RT_BIT_32(11)
3791/** Exception Mask: Precision. */
3792#define X86_MXCSR_PM RT_BIT_32(12)
3793/** Exception Mask: mask. */
3794#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3795/** Exception Mask: shift. */
3796#define X86_MXCSR_XCPT_MASK_SHIFT 7
3797
3798/** Rounding control mask. */
3799#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3800/** Rounding control shift. */
3801#define X86_MXCSR_RC_SHIFT 13
3802/** Rounding control: To nearest. */
3803#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3804/** Rounding control: Down. */
3805#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3806/** Rounding control: Up. */
3807#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3808/** Rounding control: Towards zero. */
3809#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3810
3811/** Flush-to-zero for masked underflow. */
3812#define X86_MXCSR_FZ RT_BIT_32(15)
3813
3814/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3815#define X86_MXCSR_MM RT_BIT_32(17)
3816/** Bits which should be zero, apparently. */
3817#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3818/** @} */
3819
3820#ifndef __ASSEMBLER__
3821
3822/**
3823 * XSAVE header.
3824 */
3825typedef struct X86XSAVEHDR
3826{
3827 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3828 uint64_t bmXState;
3829 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3830 uint64_t bmXComp;
3831 /** Reserved for furture extensions, probably MBZ. */
3832 uint64_t au64Reserved[6];
3833} X86XSAVEHDR;
3834# ifndef VBOX_FOR_DTRACE_LIB
3835AssertCompileSize(X86XSAVEHDR, 64);
3836# endif
3837/** Pointer to an XSAVE header. */
3838typedef X86XSAVEHDR *PX86XSAVEHDR;
3839/** Pointer to a const XSAVE header. */
3840typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3841
3842
3843/**
3844 * The high 128-bit YMM register state (XSAVE_C_YMM).
3845 * (The lower 128-bits being in X86FXSTATE.)
3846 */
3847typedef struct X86XSAVEYMMHI
3848{
3849 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3850 X86XMMREG aYmmHi[16];
3851} X86XSAVEYMMHI;
3852# ifndef VBOX_FOR_DTRACE_LIB
3853AssertCompileSize(X86XSAVEYMMHI, 256);
3854# endif
3855/** Pointer to a high 128-bit YMM register state. */
3856typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3857/** Pointer to a const high 128-bit YMM register state. */
3858typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3859
3860/**
3861 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3862 */
3863typedef struct X86XSAVEBNDREGS
3864{
3865 /** Array of registers (BND0...BND3). */
3866 struct
3867 {
3868 /** Lower bound. */
3869 uint64_t uLowerBound;
3870 /** Upper bound. */
3871 uint64_t uUpperBound;
3872 } aRegs[4];
3873} X86XSAVEBNDREGS;
3874# ifndef VBOX_FOR_DTRACE_LIB
3875AssertCompileSize(X86XSAVEBNDREGS, 64);
3876# endif
3877/** Pointer to a MPX bound register state. */
3878typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3879/** Pointer to a const MPX bound register state. */
3880typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3881
3882/**
3883 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3884 */
3885typedef struct X86XSAVEBNDCFG
3886{
3887 uint64_t fConfig;
3888 uint64_t fStatus;
3889} X86XSAVEBNDCFG;
3890# ifndef VBOX_FOR_DTRACE_LIB
3891AssertCompileSize(X86XSAVEBNDCFG, 16);
3892# endif
3893/** Pointer to a MPX bound config and status register state. */
3894typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3895/** Pointer to a const MPX bound config and status register state. */
3896typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3897
3898/**
3899 * AVX-512 opmask state (XSAVE_C_OPMASK).
3900 */
3901typedef struct X86XSAVEOPMASK
3902{
3903 /** The K0..K7 values. */
3904 uint64_t aKRegs[8];
3905} X86XSAVEOPMASK;
3906# ifndef VBOX_FOR_DTRACE_LIB
3907AssertCompileSize(X86XSAVEOPMASK, 64);
3908# endif
3909/** Pointer to a AVX-512 opmask state. */
3910typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3911/** Pointer to a const AVX-512 opmask state. */
3912typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3913
3914/**
3915 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3916 */
3917typedef struct X86XSAVEZMMHI256
3918{
3919 /** Upper 256-bits of ZMM0-15. */
3920 X86YMMREG aHi256Regs[16];
3921} X86XSAVEZMMHI256;
3922# ifndef VBOX_FOR_DTRACE_LIB
3923AssertCompileSize(X86XSAVEZMMHI256, 512);
3924# endif
3925/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3926typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3927/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3928typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3929
3930/**
3931 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3932 */
3933typedef struct X86XSAVEZMM16HI
3934{
3935 /** ZMM16 thru ZMM31. */
3936 X86ZMMREG aRegs[16];
3937} X86XSAVEZMM16HI;
3938# ifndef VBOX_FOR_DTRACE_LIB
3939AssertCompileSize(X86XSAVEZMM16HI, 1024);
3940# endif
3941/** Pointer to a state comprising ZMM16-32. */
3942typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3943/** Pointer to a const state comprising ZMM16-32. */
3944typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3945
3946/**
3947 * AMD Light weight profiling state (XSAVE_C_LWP).
3948 *
3949 * We probably won't play with this as AMD seems to be dropping from their "zen"
3950 * processor micro architecture.
3951 */
3952typedef struct X86XSAVELWP
3953{
3954 /** Details when needed. */
3955 uint64_t auLater[128/8];
3956} X86XSAVELWP;
3957# ifndef VBOX_FOR_DTRACE_LIB
3958AssertCompileSize(X86XSAVELWP, 128);
3959# endif
3960
3961
3962/**
3963 * x86 FPU/SSE/AVX/XXXX state.
3964 *
3965 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3966 * changes to this structure.
3967 */
3968typedef struct X86XSAVEAREA
3969{
3970 /** The x87 and SSE region (or legacy region if you like). */
3971 X86FXSTATE x87;
3972 /** The XSAVE header. */
3973 X86XSAVEHDR Hdr;
3974 /** Beyond the header, there isn't really a fixed layout, but we can
3975 generally assume the YMM (AVX) register extensions are present and
3976 follows immediately. */
3977 union
3978 {
3979 /** The high 128-bit AVX registers for easy access by IEM.
3980 * @note This ASSUMES they will always be here... */
3981 X86XSAVEYMMHI YmmHi;
3982
3983 /** This is a typical layout on intel CPUs (good for debuggers). */
3984 struct
3985 {
3986 X86XSAVEYMMHI YmmHi;
3987 X86XSAVEBNDREGS BndRegs;
3988 X86XSAVEBNDCFG BndCfg;
3989 uint8_t abFudgeToMatchDocs[0xB0];
3990 X86XSAVEOPMASK Opmask;
3991 X86XSAVEZMMHI256 ZmmHi256;
3992 X86XSAVEZMM16HI Zmm16Hi;
3993 } Intel;
3994
3995 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3996 struct
3997 {
3998 X86XSAVEYMMHI YmmHi;
3999 X86XSAVELWP Lwp;
4000 } AmdBd;
4001
4002 /** To enbling static deployments that have a reasonable chance of working for
4003 * the next 3-6 CPU generations without running short on space, we allocate a
4004 * lot of extra space here, making the structure a round 8KB in size. This
4005 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
4006 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
4007 uint8_t ab[8192 - 512 - 64];
4008 } u;
4009} X86XSAVEAREA;
4010# ifndef VBOX_FOR_DTRACE_LIB
4011AssertCompileSize(X86XSAVEAREA, 8192);
4012AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
4013AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
4014AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
4015AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
4016AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
4017AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
4018AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
4019AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
4020# endif
4021/** Pointer to a XSAVE area. */
4022typedef X86XSAVEAREA *PX86XSAVEAREA;
4023/** Pointer to a const XSAVE area. */
4024typedef X86XSAVEAREA const *PCX86XSAVEAREA;
4025
4026#endif /* __ASSEMBLER__ */
4027
4028
4029/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
4030 * @{ */
4031/** Bit 0 - x87 - Legacy FPU state (bit number) */
4032#define XSAVE_C_X87_BIT 0
4033/** Bit 0 - x87 - Legacy FPU state. */
4034#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
4035/** Bit 1 - SSE - 128-bit SSE state (bit number). */
4036#define XSAVE_C_SSE_BIT 1
4037/** Bit 1 - SSE - 128-bit SSE state. */
4038#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
4039/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
4040#define XSAVE_C_YMM_BIT 2
4041/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
4042#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
4043/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
4044#define XSAVE_C_BNDREGS_BIT 3
4045/** Bit 3 - BNDREGS - MPX bound register state. */
4046#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
4047/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
4048#define XSAVE_C_BNDCSR_BIT 4
4049/** Bit 4 - BNDCSR - MPX bound config and status state. */
4050#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
4051/** Bit 5 - Opmask - opmask state (bit number). */
4052#define XSAVE_C_OPMASK_BIT 5
4053/** Bit 5 - Opmask - opmask state. */
4054#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
4055/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
4056#define XSAVE_C_ZMM_HI256_BIT 6
4057/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
4058#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
4059/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
4060#define XSAVE_C_ZMM_16HI_BIT 7
4061/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
4062#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
4063/** Bit 9 - PKRU - Protection-key state (bit number). */
4064#define XSAVE_C_PKRU_BIT 9
4065/** Bit 9 - PKRU - Protection-key state. */
4066#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
4067/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
4068#define XSAVE_C_LWP_BIT 62
4069/** Bit 62 - LWP - Lightweight Profiling (AMD). */
4070#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
4071/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
4072#define XSAVE_C_X_BIT 63
4073/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
4074#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
4075/** @} */
4076
4077
4078
4079/** @name Selector Descriptor
4080 * @{
4081 */
4082
4083#ifndef __ASSEMBLER__
4084# ifndef VBOX_FOR_DTRACE_LIB
4085/**
4086 * Descriptor attributes (as seen by VT-x).
4087 */
4088typedef struct X86DESCATTRBITS
4089{
4090 /** 00 - Segment Type. */
4091 unsigned u4Type : 4;
4092 /** 04 - Descriptor Type. System(=0) or code/data selector */
4093 unsigned u1DescType : 1;
4094 /** 05 - Descriptor Privilege level. */
4095 unsigned u2Dpl : 2;
4096 /** 07 - Flags selector present(=1) or not. */
4097 unsigned u1Present : 1;
4098 /** 08 - Segment limit 16-19. */
4099 unsigned u4LimitHigh : 4;
4100 /** 0c - Available for system software. */
4101 unsigned u1Available : 1;
4102 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4103 unsigned u1Long : 1;
4104 /** 0e - This flags meaning depends on the segment type. Try make sense out
4105 * of the intel manual yourself. */
4106 unsigned u1DefBig : 1;
4107 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
4108 * clear byte. */
4109 unsigned u1Granularity : 1;
4110 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
4111 unsigned u1Unusable : 1;
4112} X86DESCATTRBITS;
4113# endif /* !VBOX_FOR_DTRACE_LIB */
4114#endif /* !__ASSEMBLER__ */
4115
4116/** @name X86DESCATTR masks
4117 * Fields X86DESCGENERIC::u4Type thru X86DESCGENERIC::u1Granularity (or
4118 * bits[55:40] if you like). The X86DESCATTR_UNUSABLE bit is an Intel addition.
4119 * @{ */
4120#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
4121#define X86DESCATTR_DT UINT32_C(0x00000010) /**< Descriptor type: 0=system, 1=code/data */
4122#define X86DESCATTR_DPL UINT32_C(0x00000060)
4123#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL bitfield. */
4124#define X86DESCATTR_P UINT32_C(0x00000080)
4125#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
4126#define X86DESCATTR_AVL UINT32_C(0x00001000)
4127#define X86DESCATTR_L UINT32_C(0x00002000)
4128#define X86DESCATTR_D UINT32_C(0x00004000)
4129#define X86DESCATTR_G UINT32_C(0x00008000)
4130#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
4131/** @} */
4132
4133
4134#ifndef __ASSEMBLER__
4135# pragma pack(1)
4136typedef union X86DESCATTR
4137{
4138 /** Unsigned integer view. */
4139 uint32_t u;
4140# ifndef VBOX_FOR_DTRACE_LIB
4141 /** Normal view. */
4142 X86DESCATTRBITS n;
4143# endif
4144} X86DESCATTR;
4145# pragma pack()
4146/** Pointer to descriptor attributes. */
4147typedef X86DESCATTR *PX86DESCATTR;
4148/** Pointer to const descriptor attributes. */
4149typedef const X86DESCATTR *PCX86DESCATTR;
4150#endif /* !__ASSEMBLER__ */
4151
4152#ifndef VBOX_FOR_DTRACE_LIB
4153
4154#ifndef __ASSEMBLER__
4155/**
4156 * Generic descriptor table entry
4157 */
4158# pragma pack(1)
4159typedef struct X86DESCGENERIC
4160{
4161 /** 00 - Limit - Low word. */
4162 unsigned u16LimitLow : 16;
4163 /** 10 - Base address - low word.
4164 * Don't try set this to 24 because MSC is doing stupid things then. */
4165 unsigned u16BaseLow : 16;
4166 /** 20 - Base address - first 8 bits of high word. */
4167 unsigned u8BaseHigh1 : 8;
4168 /** 28 - Segment Type. */
4169 unsigned u4Type : 4;
4170 /** 2c - Descriptor Type. System(=0) or code/data selector */
4171 unsigned u1DescType : 1;
4172 /** 2d - Descriptor Privilege level. */
4173 unsigned u2Dpl : 2;
4174 /** 2f - Flags selector present(=1) or not. */
4175 unsigned u1Present : 1;
4176 /** 30 - Segment limit 16-19. */
4177 unsigned u4LimitHigh : 4;
4178 /** 34 - Available for system software. */
4179 unsigned u1Available : 1;
4180 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
4181 unsigned u1Long : 1;
4182 /** 36 - This flags meaning depends on the segment type. Try make sense out
4183 * of the intel manual yourself. */
4184 unsigned u1DefBig : 1;
4185 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
4186 * clear byte. */
4187 unsigned u1Granularity : 1;
4188 /** 38 - Base address - highest 8 bits. */
4189 unsigned u8BaseHigh2 : 8;
4190} X86DESCGENERIC;
4191# pragma pack()
4192/** Pointer to a generic descriptor entry. */
4193typedef X86DESCGENERIC *PX86DESCGENERIC;
4194/** Pointer to a const generic descriptor entry. */
4195typedef const X86DESCGENERIC *PCX86DESCGENERIC;
4196# endif /* !__ASSEMBLER__ */
4197
4198
4199/** @name Bit offsets of X86DESCGENERIC members.
4200 * @{*/
4201# define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
4202# define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
4203# define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
4204# define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
4205# define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
4206# define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
4207# define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
4208# define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
4209# define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
4210# define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
4211# define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
4212# define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
4213# define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
4214/** @} */
4215
4216
4217/** @name LAR mask
4218 * @{ */
4219# define X86LAR_F_TYPE UINT16_C( 0x0f00)
4220# define X86LAR_F_DT UINT16_C( 0x1000)
4221# define X86LAR_F_DPL UINT16_C( 0x6000)
4222# define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
4223# define X86LAR_F_P UINT16_C( 0x8000)
4224# define X86LAR_F_AVL UINT32_C(0x00100000)
4225# define X86LAR_F_L UINT32_C(0x00200000)
4226# define X86LAR_F_D UINT32_C(0x00400000)
4227# define X86LAR_F_G UINT32_C(0x00800000)
4228/** @} */
4229
4230
4231# ifndef __ASSEMBLER__
4232/**
4233 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
4234 */
4235typedef struct X86DESCGATE
4236{
4237 /** 00 - Target code segment offset - Low word.
4238 * Ignored if task-gate. */
4239 unsigned u16OffsetLow : 16;
4240 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
4241 * TSS selector if task-gate. */
4242 unsigned u16Sel : 16;
4243 /** 20 - Number of parameters for a call-gate.
4244 * Ignored if interrupt-, trap- or task-gate. */
4245 unsigned u5ParmCount : 5;
4246 /** 25 - Reserved / ignored. */
4247 unsigned u3Reserved : 3;
4248 /** 28 - Segment Type. */
4249 unsigned u4Type : 4;
4250 /** 2c - Descriptor Type (0 = system). */
4251 unsigned u1DescType : 1;
4252 /** 2d - Descriptor Privilege level. */
4253 unsigned u2Dpl : 2;
4254 /** 2f - Flags selector present(=1) or not. */
4255 unsigned u1Present : 1;
4256 /** 30 - Target code segment offset - High word.
4257 * Ignored if task-gate. */
4258 unsigned u16OffsetHigh : 16;
4259} X86DESCGATE;
4260/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4261typedef X86DESCGATE *PX86DESCGATE;
4262/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4263typedef const X86DESCGATE *PCX86DESCGATE;
4264# endif /* !__ASSEMBLER__ */
4265
4266#endif /* VBOX_FOR_DTRACE_LIB */
4267
4268#ifndef __ASSEMBLER__
4269/**
4270 * Descriptor table entry.
4271 */
4272# pragma pack(1)
4273typedef union X86DESC
4274{
4275# ifndef VBOX_FOR_DTRACE_LIB
4276 /** Generic descriptor view. */
4277 X86DESCGENERIC Gen;
4278 /** Gate descriptor view. */
4279 X86DESCGATE Gate;
4280# endif
4281 /** 8 bit unsigned integer view. */
4282 uint8_t au8[8];
4283 /** 16 bit unsigned integer view. */
4284 uint16_t au16[4];
4285 /** 32 bit unsigned integer view. */
4286 uint32_t au32[2];
4287 /** 64 bit unsigned integer view. */
4288 uint64_t au64[1];
4289 /** Unsigned integer view. */
4290 uint64_t u;
4291} X86DESC;
4292# ifndef VBOX_FOR_DTRACE_LIB
4293AssertCompileSize(X86DESC, 8);
4294# endif
4295# pragma pack()
4296/** Pointer to descriptor table entry. */
4297typedef X86DESC *PX86DESC;
4298/** Pointer to const descriptor table entry. */
4299typedef const X86DESC *PCX86DESC;
4300#endif /* !__ASSEMBLER__ */
4301
4302/** @def X86DESC_BASE
4303 * Return the base address of a descriptor.
4304 */
4305#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
4306 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4307 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4308 | ( (a_pDesc)->Gen.u16BaseLow ) )
4309
4310/** @def X86DESC_LIMIT
4311 * Return the limit of a descriptor.
4312 */
4313#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
4314 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4315 | ( (a_pDesc)->Gen.u16LimitLow ) )
4316
4317/** @def X86DESC_LIMIT_G
4318 * Return the limit of a descriptor with the granularity bit taken into account.
4319 * @returns Selector limit (uint32_t).
4320 * @param a_pDesc Pointer to the descriptor.
4321 */
4322#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
4323 ( (a_pDesc)->Gen.u1Granularity \
4324 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
4325 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
4326 )
4327
4328/** @def X86DESC_GET_HID_ATTR
4329 * Get the descriptor attributes for the hidden register.
4330 */
4331#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
4332 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4333
4334#ifndef __ASSEMBLER__
4335# ifndef VBOX_FOR_DTRACE_LIB
4336
4337/**
4338 * 64 bits generic descriptor table entry
4339 * Note: most of these bits have no meaning in long mode.
4340 */
4341# pragma pack(1)
4342typedef struct X86DESC64GENERIC
4343{
4344 /** Limit - Low word - *IGNORED*. */
4345 uint32_t u16LimitLow : 16;
4346 /** Base address - low word. - *IGNORED*
4347 * Don't try set this to 24 because MSC is doing stupid things then. */
4348 uint32_t u16BaseLow : 16;
4349 /** Base address - first 8 bits of high word. - *IGNORED* */
4350 uint32_t u8BaseHigh1 : 8;
4351 /** Segment Type. */
4352 uint32_t u4Type : 4;
4353 /** Descriptor Type. System(=0) or code/data selector */
4354 uint32_t u1DescType : 1;
4355 /** Descriptor Privilege level. */
4356 uint32_t u2Dpl : 2;
4357 /** Flags selector present(=1) or not. */
4358 uint32_t u1Present : 1;
4359 /** Segment limit 16-19. - *IGNORED* */
4360 uint32_t u4LimitHigh : 4;
4361 /** Available for system software. - *IGNORED* */
4362 uint32_t u1Available : 1;
4363 /** Long mode flag. */
4364 uint32_t u1Long : 1;
4365 /** This flags meaning depends on the segment type. Try make sense out
4366 * of the intel manual yourself. */
4367 uint32_t u1DefBig : 1;
4368 /** Granularity of the limit. If set 4KB granularity is used, if
4369 * clear byte. - *IGNORED* */
4370 uint32_t u1Granularity : 1;
4371 /** Base address - highest 8 bits. - *IGNORED* */
4372 uint32_t u8BaseHigh2 : 8;
4373 /** Base address - bits 63-32. */
4374 uint32_t u32BaseHigh3 : 32;
4375 uint32_t u8Reserved : 8;
4376 uint32_t u5Zeros : 5;
4377 uint32_t u19Reserved : 19;
4378} X86DESC64GENERIC;
4379# pragma pack()
4380/** Pointer to a generic descriptor entry. */
4381typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4382/** Pointer to a const generic descriptor entry. */
4383typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4384
4385/**
4386 * System descriptor table entry (64 bits)
4387 *
4388 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4389 */
4390# pragma pack(1)
4391typedef struct X86DESC64SYSTEM
4392{
4393 /** Limit - Low word. */
4394 uint32_t u16LimitLow : 16;
4395 /** Base address - low word.
4396 * Don't try set this to 24 because MSC is doing stupid things then. */
4397 uint32_t u16BaseLow : 16;
4398 /** Base address - first 8 bits of high word. */
4399 uint32_t u8BaseHigh1 : 8;
4400 /** Segment Type. */
4401 uint32_t u4Type : 4;
4402 /** Descriptor Type. System(=0) or code/data selector */
4403 uint32_t u1DescType : 1;
4404 /** Descriptor Privilege level. */
4405 uint32_t u2Dpl : 2;
4406 /** Flags selector present(=1) or not. */
4407 uint32_t u1Present : 1;
4408 /** Segment limit 16-19. */
4409 uint32_t u4LimitHigh : 4;
4410 /** Available for system software. */
4411 uint32_t u1Available : 1;
4412 /** Reserved - 0. */
4413 uint32_t u1Reserved : 1;
4414 /** This flags meaning depends on the segment type. Try make sense out
4415 * of the intel manual yourself. */
4416 uint32_t u1DefBig : 1;
4417 /** Granularity of the limit. If set 4KB granularity is used, if
4418 * clear byte. */
4419 uint32_t u1Granularity : 1;
4420 /** Base address - bits 31-24. */
4421 uint32_t u8BaseHigh2 : 8;
4422 /** Base address - bits 63-32. */
4423 uint32_t u32BaseHigh3 : 32;
4424 uint32_t u8Reserved : 8;
4425 uint32_t u5Zeros : 5;
4426 uint32_t u19Reserved : 19;
4427} X86DESC64SYSTEM;
4428# pragma pack()
4429/** Pointer to a system descriptor entry. */
4430typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4431/** Pointer to a const system descriptor entry. */
4432typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4433
4434/**
4435 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4436 */
4437typedef struct X86DESC64GATE
4438{
4439 /** Target code segment offset - Low word. */
4440 uint32_t u16OffsetLow : 16;
4441 /** Target code segment selector. */
4442 uint32_t u16Sel : 16;
4443 /** Interrupt stack table for interrupt- and trap-gates.
4444 * Ignored by call-gates. */
4445 uint32_t u3IST : 3;
4446 /** Reserved / ignored. */
4447 uint32_t u5Reserved : 5;
4448 /** Segment Type. */
4449 uint32_t u4Type : 4;
4450 /** Descriptor Type (0 = system). */
4451 uint32_t u1DescType : 1;
4452 /** Descriptor Privilege level. */
4453 uint32_t u2Dpl : 2;
4454 /** Flags selector present(=1) or not. */
4455 uint32_t u1Present : 1;
4456 /** Target code segment offset - High word.
4457 * Ignored if task-gate. */
4458 uint32_t u16OffsetHigh : 16;
4459 /** Target code segment offset - Top dword.
4460 * Ignored if task-gate. */
4461 uint32_t u32OffsetTop : 32;
4462 /** Reserved / ignored / must be zero.
4463 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4464 uint32_t u32Reserved : 32;
4465} X86DESC64GATE;
4466AssertCompileSize(X86DESC64GATE, 16);
4467/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4468typedef X86DESC64GATE *PX86DESC64GATE;
4469/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4470typedef const X86DESC64GATE *PCX86DESC64GATE;
4471
4472# endif /* VBOX_FOR_DTRACE_LIB */
4473
4474/**
4475 * Descriptor table entry.
4476 */
4477# pragma pack(1)
4478typedef union X86DESC64
4479{
4480# ifndef VBOX_FOR_DTRACE_LIB
4481 /** Generic descriptor view. */
4482 X86DESC64GENERIC Gen;
4483 /** System descriptor view. */
4484 X86DESC64SYSTEM System;
4485 /** Gate descriptor view. */
4486 X86DESC64GATE Gate;
4487# endif
4488
4489 /** 8 bit unsigned integer view. */
4490 uint8_t au8[16];
4491 /** 16 bit unsigned integer view. */
4492 uint16_t au16[8];
4493 /** 32 bit unsigned integer view. */
4494 uint32_t au32[4];
4495 /** 64 bit unsigned integer view. */
4496 uint64_t au64[2];
4497} X86DESC64;
4498# ifndef VBOX_FOR_DTRACE_LIB
4499AssertCompileSize(X86DESC64, 16);
4500# endif
4501# pragma pack()
4502/** Pointer to descriptor table entry. */
4503typedef X86DESC64 *PX86DESC64;
4504/** Pointer to const descriptor table entry. */
4505typedef const X86DESC64 *PCX86DESC64;
4506
4507/** @def X86DESC64_BASE
4508 * Return the base of a 64-bit descriptor.
4509 */
4510#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
4511 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4512 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4513 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4514 | ( (a_pDesc)->Gen.u16BaseLow ) )
4515
4516
4517
4518/** @name Host system descriptor table entry - Use with care!
4519 * @{ */
4520/** Host system descriptor table entry. */
4521#if HC_ARCH_BITS == 64
4522typedef X86DESC64 X86DESCHC;
4523#else
4524typedef X86DESC X86DESCHC;
4525#endif
4526/** Pointer to a host system descriptor table entry. */
4527#if HC_ARCH_BITS == 64
4528typedef PX86DESC64 PX86DESCHC;
4529#else
4530typedef PX86DESC PX86DESCHC;
4531#endif
4532/** Pointer to a const host system descriptor table entry. */
4533#if HC_ARCH_BITS == 64
4534typedef PCX86DESC64 PCX86DESCHC;
4535#else
4536typedef PCX86DESC PCX86DESCHC;
4537#endif
4538/** @} */
4539
4540#endif /* !__ASSEMBLER__ */
4541
4542
4543/** @name Selector Descriptor Types.
4544 * @{
4545 */
4546
4547/** @name Non-System Selector Types.
4548 * @{ */
4549/** Code(=set)/Data(=clear) bit. */
4550#define X86_SEL_TYPE_CODE 8
4551/** Memory(=set)/System(=clear) bit. */
4552#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4553/** Accessed bit. */
4554#define X86_SEL_TYPE_ACCESSED 1
4555/** Expand down bit (for data selectors only). */
4556#define X86_SEL_TYPE_DOWN 4
4557/** Conforming bit (for code selectors only). */
4558#define X86_SEL_TYPE_CONF 4
4559/** Write bit (for data selectors only). */
4560#define X86_SEL_TYPE_WRITE 2
4561/** Read bit (for code selectors only). */
4562#define X86_SEL_TYPE_READ 2
4563/** The bit number of the code segment read bit (relative to u4Type). */
4564#define X86_SEL_TYPE_READ_BIT 1
4565
4566/** Read only selector type. */
4567#define X86_SEL_TYPE_RO 0
4568/** Accessed read only selector type. */
4569#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
4570/** Read write selector type. */
4571#define X86_SEL_TYPE_RW 2
4572/** Accessed read write selector type. */
4573#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
4574/** Expand down read only selector type. */
4575#define X86_SEL_TYPE_RO_DOWN 4
4576/** Accessed expand down read only selector type. */
4577#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
4578/** Expand down read write selector type. */
4579#define X86_SEL_TYPE_RW_DOWN 6
4580/** Accessed expand down read write selector type. */
4581#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
4582/** Execute only selector type. */
4583#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
4584/** Accessed execute only selector type. */
4585#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4586/** Execute and read selector type. */
4587#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
4588/** Accessed execute and read selector type. */
4589#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4590/** Conforming execute only selector type. */
4591#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
4592/** Accessed Conforming execute only selector type. */
4593#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4594/** Conforming execute and write selector type. */
4595#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
4596/** Accessed Conforming execute and write selector type. */
4597#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4598/** @} */
4599
4600
4601/** @name System Selector Types.
4602 * @{ */
4603/** The TSS busy bit mask. */
4604#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4605
4606/** Undefined system selector type. */
4607#define X86_SEL_TYPE_SYS_UNDEFINED 0
4608/** 286 TSS selector. */
4609#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4610/** LDT selector. */
4611#define X86_SEL_TYPE_SYS_LDT 2
4612/** 286 TSS selector - Busy. */
4613#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4614/** 286 Callgate selector. */
4615#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4616/** Taskgate selector. */
4617#define X86_SEL_TYPE_SYS_TASK_GATE 5
4618/** 286 Interrupt gate selector. */
4619#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4620/** 286 Trapgate selector. */
4621#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4622/** Undefined system selector. */
4623#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4624/** 386 TSS selector. */
4625#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4626/** Undefined system selector. */
4627#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4628/** 386 TSS selector - Busy. */
4629#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4630/** 386 Callgate selector. */
4631#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4632/** Undefined system selector. */
4633#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4634/** 386 Interruptgate selector. */
4635#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4636/** 386 Trapgate selector. */
4637#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4638/** @} */
4639
4640/** @name AMD64 System Selector Types.
4641 * @{ */
4642/** LDT selector. */
4643#define AMD64_SEL_TYPE_SYS_LDT 2
4644/** TSS selector - Busy. */
4645#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4646/** TSS selector - Busy. */
4647#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4648/** Callgate selector. */
4649#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4650/** Interruptgate selector. */
4651#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4652/** Trapgate selector. */
4653#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4654/** @} */
4655
4656/** @} */
4657
4658
4659/** @name Descriptor Table Entry Flag Masks.
4660 * These are for the 2nd 32-bit word of a descriptor.
4661 * @{ */
4662/** Bits 8-11 - TYPE - Descriptor type mask. */
4663#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4664/** Bit 12 - S - System (=0) or Code/Data (=1). */
4665#define X86_DESC_S RT_BIT_32(12)
4666/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4667#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4668/** Bit 15 - P - Present. */
4669#define X86_DESC_P RT_BIT_32(15)
4670/** Bit 20 - AVL - Available for system software. */
4671#define X86_DESC_AVL RT_BIT_32(20)
4672/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4673#define X86_DESC_DB RT_BIT_32(22)
4674/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4675 * used, if clear byte. */
4676#define X86_DESC_G RT_BIT_32(23)
4677/** @} */
4678
4679/** @} */
4680
4681
4682/** @name Task Segments.
4683 * @{
4684 */
4685
4686/**
4687 * The minimum TSS descriptor limit for 286 tasks.
4688 */
4689#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4690
4691/**
4692 * The minimum TSS descriptor segment limit for 386 tasks.
4693 */
4694#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4695
4696#ifndef __ASSEMBLER__
4697
4698/**
4699 * 16-bit Task Segment (TSS).
4700 */
4701# pragma pack(1)
4702typedef struct X86TSS16
4703{
4704 /** Back link to previous task. (static) */
4705 RTSEL selPrev;
4706 /** Ring-0 stack pointer. (static) */
4707 uint16_t sp0;
4708 /** Ring-0 stack segment. (static) */
4709 RTSEL ss0;
4710 /** Ring-1 stack pointer. (static) */
4711 uint16_t sp1;
4712 /** Ring-1 stack segment. (static) */
4713 RTSEL ss1;
4714 /** Ring-2 stack pointer. (static) */
4715 uint16_t sp2;
4716 /** Ring-2 stack segment. (static) */
4717 RTSEL ss2;
4718 /** IP before task switch. */
4719 uint16_t ip;
4720 /** FLAGS before task switch. */
4721 uint16_t flags;
4722 /** AX before task switch. */
4723 uint16_t ax;
4724 /** CX before task switch. */
4725 uint16_t cx;
4726 /** DX before task switch. */
4727 uint16_t dx;
4728 /** BX before task switch. */
4729 uint16_t bx;
4730 /** SP before task switch. */
4731 uint16_t sp;
4732 /** BP before task switch. */
4733 uint16_t bp;
4734 /** SI before task switch. */
4735 uint16_t si;
4736 /** DI before task switch. */
4737 uint16_t di;
4738 /** ES before task switch. */
4739 RTSEL es;
4740 /** CS before task switch. */
4741 RTSEL cs;
4742 /** SS before task switch. */
4743 RTSEL ss;
4744 /** DS before task switch. */
4745 RTSEL ds;
4746 /** LDTR before task switch. */
4747 RTSEL selLdt;
4748} X86TSS16;
4749# ifndef VBOX_FOR_DTRACE_LIB
4750AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4751# endif
4752# pragma pack()
4753/** Pointer to a 16-bit task segment. */
4754typedef X86TSS16 *PX86TSS16;
4755/** Pointer to a const 16-bit task segment. */
4756typedef const X86TSS16 *PCX86TSS16;
4757
4758
4759/**
4760 * 32-bit Task Segment (TSS).
4761 */
4762# pragma pack(1)
4763typedef struct X86TSS32
4764{
4765 /** Back link to previous task. (static) */
4766 RTSEL selPrev;
4767 uint16_t padding1;
4768 /** Ring-0 stack pointer. (static) */
4769 uint32_t esp0;
4770 /** Ring-0 stack segment. (static) */
4771 RTSEL ss0;
4772 uint16_t padding_ss0;
4773 /** Ring-1 stack pointer. (static) */
4774 uint32_t esp1;
4775 /** Ring-1 stack segment. (static) */
4776 RTSEL ss1;
4777 uint16_t padding_ss1;
4778 /** Ring-2 stack pointer. (static) */
4779 uint32_t esp2;
4780 /** Ring-2 stack segment. (static) */
4781 RTSEL ss2;
4782 uint16_t padding_ss2;
4783 /** Page directory for the task. (static) */
4784 uint32_t cr3;
4785 /** EIP before task switch. */
4786 uint32_t eip;
4787 /** EFLAGS before task switch. */
4788 uint32_t eflags;
4789 /** EAX before task switch. */
4790 uint32_t eax;
4791 /** ECX before task switch. */
4792 uint32_t ecx;
4793 /** EDX before task switch. */
4794 uint32_t edx;
4795 /** EBX before task switch. */
4796 uint32_t ebx;
4797 /** ESP before task switch. */
4798 uint32_t esp;
4799 /** EBP before task switch. */
4800 uint32_t ebp;
4801 /** ESI before task switch. */
4802 uint32_t esi;
4803 /** EDI before task switch. */
4804 uint32_t edi;
4805 /** ES before task switch. */
4806 RTSEL es;
4807 uint16_t padding_es;
4808 /** CS before task switch. */
4809 RTSEL cs;
4810 uint16_t padding_cs;
4811 /** SS before task switch. */
4812 RTSEL ss;
4813 uint16_t padding_ss;
4814 /** DS before task switch. */
4815 RTSEL ds;
4816 uint16_t padding_ds;
4817 /** FS before task switch. */
4818 RTSEL fs;
4819 uint16_t padding_fs;
4820 /** GS before task switch. */
4821 RTSEL gs;
4822 uint16_t padding_gs;
4823 /** LDTR before task switch. */
4824 RTSEL selLdt;
4825 uint16_t padding_ldt;
4826 /** Debug trap flag */
4827 uint16_t fDebugTrap;
4828 /** Offset relative to the TSS of the start of the I/O Bitmap
4829 * and the end of the interrupt redirection bitmap. */
4830 uint16_t offIoBitmap;
4831} X86TSS32;
4832# pragma pack()
4833/** Pointer to task segment. */
4834typedef X86TSS32 *PX86TSS32;
4835/** Pointer to const task segment. */
4836typedef const X86TSS32 *PCX86TSS32;
4837# ifndef VBOX_FOR_DTRACE_LIB
4838AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4839AssertCompileMemberOffset(X86TSS32, cr3, 28);
4840AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4841# endif
4842
4843/**
4844 * 64-bit Task segment.
4845 */
4846# pragma pack(1)
4847typedef struct X86TSS64
4848{
4849 /** Reserved. */
4850 uint32_t u32Reserved;
4851 /** Ring-0 stack pointer. (static) */
4852 uint64_t rsp0;
4853 /** Ring-1 stack pointer. (static) */
4854 uint64_t rsp1;
4855 /** Ring-2 stack pointer. (static) */
4856 uint64_t rsp2;
4857 /** Reserved. */
4858 uint32_t u32Reserved2[2];
4859 /* IST */
4860 uint64_t ist1;
4861 uint64_t ist2;
4862 uint64_t ist3;
4863 uint64_t ist4;
4864 uint64_t ist5;
4865 uint64_t ist6;
4866 uint64_t ist7;
4867 /* Reserved. */
4868 uint16_t u16Reserved[5];
4869 /** Offset relative to the TSS of the start of the I/O Bitmap
4870 * and the end of the interrupt redirection bitmap. */
4871 uint16_t offIoBitmap;
4872} X86TSS64;
4873# pragma pack()
4874/** Pointer to a 64-bit task segment. */
4875typedef X86TSS64 *PX86TSS64;
4876/** Pointer to a const 64-bit task segment. */
4877typedef const X86TSS64 *PCX86TSS64;
4878# ifndef VBOX_FOR_DTRACE_LIB
4879AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4880# endif
4881
4882#endif /* !__ASSEMBLER__ */
4883
4884/** @} */
4885
4886
4887/** @name Selectors.
4888 * @{
4889 */
4890
4891/**
4892 * The shift used to convert a selector from and to index an index (C).
4893 */
4894#define X86_SEL_SHIFT 3
4895
4896/**
4897 * The mask used to mask off the table indicator and RPL of an selector.
4898 */
4899#define X86_SEL_MASK 0xfff8U
4900
4901/**
4902 * The mask used to mask off the RPL of an selector.
4903 * This is suitable for checking for NULL selectors.
4904 */
4905#define X86_SEL_MASK_OFF_RPL 0xfffcU
4906
4907/**
4908 * The bit indicating that a selector is in the LDT and not in the GDT.
4909 */
4910#define X86_SEL_LDT 0x0004U
4911
4912/**
4913 * The bit mask for getting the RPL of a selector.
4914 */
4915#define X86_SEL_RPL 0x0003U
4916
4917/**
4918 * The mask covering both RPL and LDT.
4919 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4920 * checks.
4921 */
4922#define X86_SEL_RPL_LDT 0x0007U
4923
4924/** @} */
4925
4926
4927#ifndef __ASSEMBLER__
4928/**
4929 * x86 Exceptions/Faults/Traps.
4930 */
4931typedef enum X86XCPT
4932{
4933 /** \#DE - Divide error. */
4934 X86_XCPT_DE = 0x00,
4935 /** \#DB - Debug event (single step, DRx, ..) */
4936 X86_XCPT_DB = 0x01,
4937 /** NMI - Non-Maskable Interrupt */
4938 X86_XCPT_NMI = 0x02,
4939 /** \#BP - Breakpoint (INT3). */
4940 X86_XCPT_BP = 0x03,
4941 /** \#OF - Overflow (INTO). */
4942 X86_XCPT_OF = 0x04,
4943 /** \#BR - Bound range exceeded (BOUND). */
4944 X86_XCPT_BR = 0x05,
4945 /** \#UD - Undefined opcode. */
4946 X86_XCPT_UD = 0x06,
4947 /** \#NM - Device not available (math coprocessor device). */
4948 X86_XCPT_NM = 0x07,
4949 /** \#DF - Double fault. */
4950 X86_XCPT_DF = 0x08,
4951 /** ??? - Coprocessor segment overrun (obsolete). */
4952 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4953 /** \#TS - Taskswitch (TSS). */
4954 X86_XCPT_TS = 0x0a,
4955 /** \#NP - Segment no present. */
4956 X86_XCPT_NP = 0x0b,
4957 /** \#SS - Stack segment fault. */
4958 X86_XCPT_SS = 0x0c,
4959 /** \#GP - General protection fault. */
4960 X86_XCPT_GP = 0x0d,
4961 /** \#PF - Page fault. */
4962 X86_XCPT_PF = 0x0e,
4963 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4964 /** \#MF - Math fault (FPU). */
4965 X86_XCPT_MF = 0x10,
4966 /** \#AC - Alignment check. */
4967 X86_XCPT_AC = 0x11,
4968 /** \#MC - Machine check. */
4969 X86_XCPT_MC = 0x12,
4970 /** \#XF - SIMD Floating-Point Exception. */
4971 X86_XCPT_XF = 0x13,
4972 /** \#VE - Virtualization Exception (Intel only). */
4973 X86_XCPT_VE = 0x14,
4974 /** \#CP - Control Protection Exception. */
4975 X86_XCPT_CP = 0x15,
4976 /** \#VC - VMM Communication Exception (AMD only). */
4977 X86_XCPT_VC = 0x1d,
4978 /** \#SX - Security Exception (AMD only). */
4979 X86_XCPT_SX = 0x1e
4980} X86XCPT;
4981/** Pointer to a x86 exception code. */
4982typedef X86XCPT *PX86XCPT;
4983/** Pointer to a const x86 exception code. */
4984typedef const X86XCPT *PCX86XCPT;
4985#endif /* !__ASSEMBLER__ */
4986/** The last valid (currently reserved) exception value. */
4987#define X86_XCPT_LAST 0x1f
4988
4989
4990/** @name Trap Error Codes
4991 * @{
4992 */
4993/** External indicator. */
4994#define X86_TRAP_ERR_EXTERNAL 1
4995/** IDT indicator. */
4996#define X86_TRAP_ERR_IDT 2
4997/** Descriptor table indicator - If set LDT, if clear GDT. */
4998#define X86_TRAP_ERR_TI 4
4999/** Mask for getting the selector. */
5000#define X86_TRAP_ERR_SEL_MASK 0xfff8
5001/** Shift for getting the selector table index (C type index). */
5002#define X86_TRAP_ERR_SEL_SHIFT 3
5003/** @} */
5004
5005
5006/** @name \#PF Trap Error Codes
5007 * @{
5008 */
5009/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
5010#define X86_TRAP_PF_P RT_BIT_32(0)
5011/** Bit 1 - R/W - Read (clear) or write (set) access. */
5012#define X86_TRAP_PF_RW RT_BIT_32(1)
5013/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
5014#define X86_TRAP_PF_US RT_BIT_32(2)
5015/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
5016#define X86_TRAP_PF_RSVD RT_BIT_32(3)
5017/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
5018#define X86_TRAP_PF_ID RT_BIT_32(4)
5019/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
5020#define X86_TRAP_PF_PK RT_BIT_32(5)
5021/** @} */
5022
5023#ifndef __ASSEMBLER__
5024
5025# pragma pack(1)
5026/**
5027 * 16-bit IDTR.
5028 */
5029typedef struct X86IDTR16
5030{
5031 /** Offset. */
5032 uint16_t offSel;
5033 /** Selector. */
5034 uint16_t uSel;
5035} X86IDTR16, *PX86IDTR16;
5036# pragma pack()
5037
5038# pragma pack(1)
5039/**
5040 * 32-bit IDTR/GDTR.
5041 */
5042typedef struct X86XDTR32
5043{
5044 /** Size of the descriptor table. */
5045 uint16_t cb;
5046 /** Address of the descriptor table. */
5047# ifndef VBOX_FOR_DTRACE_LIB
5048 uint32_t uAddr;
5049# else
5050 uint16_t au16Addr[2];
5051# endif
5052} X86XDTR32, *PX86XDTR32;
5053# pragma pack()
5054
5055# pragma pack(1)
5056/**
5057 * 64-bit IDTR/GDTR.
5058 */
5059typedef struct X86XDTR64
5060{
5061 /** Size of the descriptor table. */
5062 uint16_t cb;
5063 /** Address of the descriptor table. */
5064# ifndef VBOX_FOR_DTRACE_LIB
5065 uint64_t uAddr;
5066# else
5067 uint16_t au16Addr[4];
5068# endif
5069} X86XDTR64, *PX86XDTR64;
5070# pragma pack()
5071
5072#endif /* !__ASSEMBLER__ */
5073
5074
5075/** @name ModR/M
5076 * @{ */
5077#define X86_MODRM_RM_MASK UINT8_C(0x07)
5078#define X86_MODRM_REG_MASK UINT8_C(0x38)
5079#define X86_MODRM_REG_SMASK UINT8_C(0x07)
5080#define X86_MODRM_REG_SHIFT 3
5081#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
5082#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
5083#define X86_MODRM_MOD_SHIFT 6
5084
5085#define X86_MOD_MEM0 0 /**< Indirect addressing without displacement (except RM=4 (SIB) and RM=5 (disp32)). */
5086#define X86_MOD_MEM1 1 /**< Indirect addressing with 8-bit displacement. */
5087#define X86_MOD_MEM4 2 /**< Indirect addressing with 32-bit displacement. */
5088#define X86_MOD_REG 3 /**< Registers. */
5089
5090#ifndef VBOX_FOR_DTRACE_LIB
5091AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
5092AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
5093AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
5094/** @def X86_MODRM_MAKE
5095 * @param a_Mod The mod value (0..3) - X86_MOD_XXX.
5096 * @param a_Reg The register value (0..7).
5097 * @param a_RegMem The register or memory value (0..7). */
5098# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
5099#endif
5100
5101/** @} */
5102
5103/** @name SIB
5104 * @{ */
5105#define X86_SIB_BASE_MASK UINT8_C(0x07)
5106#define X86_SIB_INDEX_MASK UINT8_C(0x38)
5107#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
5108#define X86_SIB_INDEX_SHIFT 3
5109#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
5110#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
5111#define X86_SIB_SCALE_SHIFT 6
5112#ifndef VBOX_FOR_DTRACE_LIB
5113/** @def X86_SIB_MAKE
5114 * @param a_BaseReg The base register value (0..7).
5115 * @param a_IndexReg The index register value (0..7).
5116 * @param a_Scale The left shift (0..3) to be applied to the index
5117 * register (0 = none, 1 = x2, 2 = x4, 3 = x8).
5118 * */
5119# define X86_SIB_MAKE(a_BaseReg, a_IndexReg, a_Scale) \
5120 (((a_Scale) << X86_SIB_SCALE_SHIFT) | ((a_IndexReg) << X86_SIB_INDEX_SHIFT) | (a_BaseReg))
5121
5122AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
5123AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
5124AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
5125#endif
5126/** @} */
5127
5128/** @name General register indexes.
5129 * @{ */
5130#define X86_GREG_xAX 0
5131#define X86_GREG_xCX 1
5132#define X86_GREG_xDX 2
5133#define X86_GREG_xBX 3
5134#define X86_GREG_xSP 4
5135#define X86_GREG_xBP 5
5136#define X86_GREG_xSI 6
5137#define X86_GREG_xDI 7
5138#define X86_GREG_x8 8
5139#define X86_GREG_x9 9
5140#define X86_GREG_x10 10
5141#define X86_GREG_x11 11
5142#define X86_GREG_x12 12
5143#define X86_GREG_x13 13
5144#define X86_GREG_x14 14
5145#define X86_GREG_x15 15
5146/** @} */
5147/** General register count. */
5148#define X86_GREG_COUNT 16
5149
5150/** @name X86_SREG_XXX - Segment register indexes.
5151 * @{ */
5152#define X86_SREG_ES 0
5153#define X86_SREG_CS 1
5154#define X86_SREG_SS 2
5155#define X86_SREG_DS 3
5156#define X86_SREG_FS 4
5157#define X86_SREG_GS 5
5158/** @} */
5159/** Segment register count. */
5160#define X86_SREG_COUNT 6
5161
5162
5163/** @name X86_OP_XXX - Prefixes
5164 * @{ */
5165#define X86_OP_PRF_CS UINT8_C(0x2e)
5166#define X86_OP_PRF_SS UINT8_C(0x36)
5167#define X86_OP_PRF_DS UINT8_C(0x3e)
5168#define X86_OP_PRF_ES UINT8_C(0x26)
5169#define X86_OP_PRF_FS UINT8_C(0x64)
5170#define X86_OP_PRF_GS UINT8_C(0x65)
5171#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
5172#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
5173#define X86_OP_PRF_LOCK UINT8_C(0xf0)
5174#define X86_OP_PRF_REPZ UINT8_C(0xf3)
5175#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
5176#define X86_OP_REX UINT8_C(0x40)
5177#define X86_OP_REX_B UINT8_C(0x41)
5178#define X86_OP_REX_X UINT8_C(0x42)
5179#define X86_OP_REX_R UINT8_C(0x44)
5180#define X86_OP_REX_W UINT8_C(0x48)
5181#define X86_OP_VEX3 UINT8_C(0xc4)
5182#define X86_OP_VEX2 UINT8_C(0xc5)
5183/** @} */
5184
5185/** @name X86_OP_VEX2_XXX - 2-byte VEX prefix helpers.
5186 * @{ */
5187#define X86_OP_VEX2_BYTE1_P_MASK 0x3
5188# define X86_OP_VEX2_BYTE1_P_NO_PRF 0
5189# define X86_OP_VEX2_BYTE1_P_066H 1
5190# define X86_OP_VEX2_BYTE1_P_0F3H 2
5191# define X86_OP_VEX2_BYTE1_P_0F2H 3
5192#define X86_OP_VEX2_BYTE1_L RT_BIT(2)
5193#define X86_OP_VEX2_BYTE1_VVVV_MASK 0x78
5194#define X86_OP_VEX2_BYTE1_VVVV_SHIFT 3
5195#define X86_OP_VEX2_BYTE1_VVVV_NONE 15
5196#define X86_OP_VEX2_BYTE1_R RT_BIT(7)
5197
5198#define X86_OP_VEX2_BYTE1_MAKE(a_fRegW, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5199 ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5200 | (~((uint8_t)(a_iSrcReg) & 0xf) << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5201 | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5202 | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5203
5204#define X86_OP_VEX2_BYTE1_MAKE_NO_VVVV(a_fRegW, a_f256BitAvx, a_fPrf) \
5205 ( ((a_fRegW) ? 0 : X86_OP_VEX2_BYTE1_R) \
5206 | (X86_OP_VEX2_BYTE1_VVVV_NONE << X86_OP_VEX2_BYTE1_VVVV_SHIFT) \
5207 | ((a_f256BitAvx) ? X86_OP_VEX2_BYTE1_L : 0) \
5208 | ((a_fPrf) & X86_OP_VEX2_BYTE1_P_MASK))
5209/** @} */
5210
5211/** @name X86_OP_VEX3_XXX - 3-byte VEX prefix helpers.
5212 * @{ */
5213#define X86_OP_VEX3_BYTE1_MAP_MASK 0x1f
5214#define X86_OP_VEX3_BYTE1_B RT_BIT(5)
5215#define X86_OP_VEX3_BYTE1_X RT_BIT(6)
5216#define X86_OP_VEX3_BYTE1_R RT_BIT(7)
5217#define X86_OP_VEX3_BYTE1_MAKE(a_idxMap, a_B, a_X, a_R) \
5218 ( (uint8_t)(a_idxMap) \
5219 | ((a_B) ? 0 : X86_OP_VEX3_BYTE1_B) \
5220 | ((a_X) ? 0 : X86_OP_VEX3_BYTE1_X) \
5221 | ((a_R) ? 0 : X86_OP_VEX3_BYTE1_R))
5222
5223#define X86_OP_VEX3_BYTE2_P_MASK 0x3
5224# define X86_OP_VEX3_BYTE2_P_NO_PRF 0
5225# define X86_OP_VEX3_BYTE2_P_066H 1
5226# define X86_OP_VEX3_BYTE2_P_0F3H 2
5227# define X86_OP_VEX3_BYTE2_P_0F2H 3
5228#define X86_OP_VEX3_BYTE2_L RT_BIT(2)
5229#define X86_OP_VEX3_BYTE2_VVVV_MASK 0x78
5230#define X86_OP_VEX3_BYTE2_VVVV_SHIFT 3
5231#define X86_OP_VEX3_BYTE2_VVVV_NONE 15
5232#define X86_OP_VEX3_BYTE2_W RT_BIT(7)
5233
5234/** @todo r=bird: Is the '& UINT8_C(0xf)' bit needed? You mask it again after
5235 * shifting. */
5236#define X86_OP_VEX3_BYTE2_MAKE(a_f64BitOpSize, a_iSrcReg, a_f256BitAvx, a_fPrf) \
5237 ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5238 | ((~((uint8_t)(a_iSrcReg) & UINT8_C(0xf)) << X86_OP_VEX3_BYTE2_VVVV_SHIFT) & X86_OP_VEX3_BYTE2_VVVV_MASK) \
5239 | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5240 | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5241
5242#define X86_OP_VEX3_BYTE2_MAKE_NO_VVVV(a_f64BitOpSize, a_f256BitAvx, a_fPrf) \
5243 ( ((a_f64BitOpSize) ? X86_OP_VEX3_BYTE2_W : 0) \
5244 | (X86_OP_VEX3_BYTE2_VVVV_NONE << X86_OP_VEX3_BYTE2_VVVV_SHIFT) \
5245 | ((a_f256BitAvx) ? X86_OP_VEX3_BYTE2_L : 0) \
5246 | ((a_fPrf) & X86_OP_VEX3_BYTE2_P_MASK))
5247/** @} */
5248
5249/** @} */
5250
5251#endif /* !IPRT_INCLUDED_x86_h */
5252
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