VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 73768

Last change on this file since 73768 was 73605, checked in by vboxsync, 6 years ago

x86.h: Nested VMX: bugref:9180 IA32_SMM_MONITOR_CTL bits.
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2017 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef ___iprt_x86_h
29#define ___iprt_x86_h
30
31#ifndef VBOX_FOR_DTRACE_LIB
32# include <iprt/types.h>
33# include <iprt/assert.h>
34#else
35# pragma D depends_on library vbox-types.d
36#endif
37
38/* Workaround for Solaris sys/regset.h defining CS, DS */
39#ifdef RT_OS_SOLARIS
40# undef CS
41# undef DS
42#endif
43
44/** @defgroup grp_rt_x86 x86 Types and Definitions
45 * @ingroup grp_rt
46 * @{
47 */
48
49#ifndef VBOX_FOR_DTRACE_LIB
50/**
51 * EFLAGS Bits.
52 */
53typedef struct X86EFLAGSBITS
54{
55 /** Bit 0 - CF - Carry flag - Status flag. */
56 unsigned u1CF : 1;
57 /** Bit 1 - 1 - Reserved flag. */
58 unsigned u1Reserved0 : 1;
59 /** Bit 2 - PF - Parity flag - Status flag. */
60 unsigned u1PF : 1;
61 /** Bit 3 - 0 - Reserved flag. */
62 unsigned u1Reserved1 : 1;
63 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64 unsigned u1AF : 1;
65 /** Bit 5 - 0 - Reserved flag. */
66 unsigned u1Reserved2 : 1;
67 /** Bit 6 - ZF - Zero flag - Status flag. */
68 unsigned u1ZF : 1;
69 /** Bit 7 - SF - Signed flag - Status flag. */
70 unsigned u1SF : 1;
71 /** Bit 8 - TF - Trap flag - System flag. */
72 unsigned u1TF : 1;
73 /** Bit 9 - IF - Interrupt flag - System flag. */
74 unsigned u1IF : 1;
75 /** Bit 10 - DF - Direction flag - Control flag. */
76 unsigned u1DF : 1;
77 /** Bit 11 - OF - Overflow flag - Status flag. */
78 unsigned u1OF : 1;
79 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
80 unsigned u2IOPL : 2;
81 /** Bit 14 - NT - Nested task flag - System flag. */
82 unsigned u1NT : 1;
83 /** Bit 15 - 0 - Reserved flag. */
84 unsigned u1Reserved3 : 1;
85 /** Bit 16 - RF - Resume flag - System flag. */
86 unsigned u1RF : 1;
87 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
88 unsigned u1VM : 1;
89 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90 unsigned u1AC : 1;
91 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
92 unsigned u1VIF : 1;
93 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
94 unsigned u1VIP : 1;
95 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96 unsigned u1ID : 1;
97 /** Bit 22-31 - 0 - Reserved flag. */
98 unsigned u10Reserved4 : 10;
99} X86EFLAGSBITS;
100/** Pointer to EFLAGS bits. */
101typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102/** Pointer to const EFLAGS bits. */
103typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104#endif /* !VBOX_FOR_DTRACE_LIB */
105
106/**
107 * EFLAGS.
108 */
109typedef union X86EFLAGS
110{
111 /** The plain unsigned view. */
112 uint32_t u;
113#ifndef VBOX_FOR_DTRACE_LIB
114 /** The bitfield view. */
115 X86EFLAGSBITS Bits;
116#endif
117 /** The 8-bit view. */
118 uint8_t au8[4];
119 /** The 16-bit view. */
120 uint16_t au16[2];
121 /** The 32-bit view. */
122 uint32_t au32[1];
123 /** The 32-bit view. */
124 uint32_t u32;
125} X86EFLAGS;
126/** Pointer to EFLAGS. */
127typedef X86EFLAGS *PX86EFLAGS;
128/** Pointer to const EFLAGS. */
129typedef const X86EFLAGS *PCX86EFLAGS;
130
131/**
132 * RFLAGS (32 upper bits are reserved).
133 */
134typedef union X86RFLAGS
135{
136 /** The plain unsigned view. */
137 uint64_t u;
138#ifndef VBOX_FOR_DTRACE_LIB
139 /** The bitfield view. */
140 X86EFLAGSBITS Bits;
141#endif
142 /** The 8-bit view. */
143 uint8_t au8[8];
144 /** The 16-bit view. */
145 uint16_t au16[4];
146 /** The 32-bit view. */
147 uint32_t au32[2];
148 /** The 64-bit view. */
149 uint64_t au64[1];
150 /** The 64-bit view. */
151 uint64_t u64;
152} X86RFLAGS;
153/** Pointer to RFLAGS. */
154typedef X86RFLAGS *PX86RFLAGS;
155/** Pointer to const RFLAGS. */
156typedef const X86RFLAGS *PCX86RFLAGS;
157
158
159/** @name EFLAGS
160 * @{
161 */
162/** Bit 0 - CF - Carry flag - Status flag. */
163#define X86_EFL_CF RT_BIT_32(0)
164#define X86_EFL_CF_BIT 0
165/** Bit 1 - Reserved, reads as 1. */
166#define X86_EFL_1 RT_BIT_32(1)
167/** Bit 2 - PF - Parity flag - Status flag. */
168#define X86_EFL_PF RT_BIT_32(2)
169/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
170#define X86_EFL_AF RT_BIT_32(4)
171#define X86_EFL_AF_BIT 4
172/** Bit 6 - ZF - Zero flag - Status flag. */
173#define X86_EFL_ZF RT_BIT_32(6)
174#define X86_EFL_ZF_BIT 6
175/** Bit 7 - SF - Signed flag - Status flag. */
176#define X86_EFL_SF RT_BIT_32(7)
177#define X86_EFL_SF_BIT 7
178/** Bit 8 - TF - Trap flag - System flag. */
179#define X86_EFL_TF RT_BIT_32(8)
180/** Bit 9 - IF - Interrupt flag - System flag. */
181#define X86_EFL_IF RT_BIT_32(9)
182/** Bit 10 - DF - Direction flag - Control flag. */
183#define X86_EFL_DF RT_BIT_32(10)
184/** Bit 11 - OF - Overflow flag - Status flag. */
185#define X86_EFL_OF RT_BIT_32(11)
186#define X86_EFL_OF_BIT 11
187/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
188#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
189/** Bit 14 - NT - Nested task flag - System flag. */
190#define X86_EFL_NT RT_BIT_32(14)
191/** Bit 16 - RF - Resume flag - System flag. */
192#define X86_EFL_RF RT_BIT_32(16)
193/** Bit 17 - VM - Virtual 8086 mode - System flag. */
194#define X86_EFL_VM RT_BIT_32(17)
195/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
196#define X86_EFL_AC RT_BIT_32(18)
197/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
198#define X86_EFL_VIF RT_BIT_32(19)
199/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
200#define X86_EFL_VIP RT_BIT_32(20)
201/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
202#define X86_EFL_ID RT_BIT_32(21)
203/** All live bits. */
204#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
205/** Read as 1 bits. */
206#define X86_EFL_RA1_MASK RT_BIT_32(1)
207/** IOPL shift. */
208#define X86_EFL_IOPL_SHIFT 12
209/** The IOPL level from the flags. */
210#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
211/** Bits restored by popf */
212#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
213 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
217/** The status bits commonly updated by arithmetic instructions. */
218#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
219/** @} */
220
221
222/** CPUID Feature information - ECX.
223 * CPUID query with EAX=1.
224 */
225#ifndef VBOX_FOR_DTRACE_LIB
226typedef struct X86CPUIDFEATECX
227{
228 /** Bit 0 - SSE3 - Supports SSE3 or not. */
229 unsigned u1SSE3 : 1;
230 /** Bit 1 - PCLMULQDQ. */
231 unsigned u1PCLMULQDQ : 1;
232 /** Bit 2 - DS Area 64-bit layout. */
233 unsigned u1DTE64 : 1;
234 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
235 unsigned u1Monitor : 1;
236 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
237 unsigned u1CPLDS : 1;
238 /** Bit 5 - VMX - Virtual Machine Technology. */
239 unsigned u1VMX : 1;
240 /** Bit 6 - SMX: Safer Mode Extensions. */
241 unsigned u1SMX : 1;
242 /** Bit 7 - EST - Enh. SpeedStep Tech. */
243 unsigned u1EST : 1;
244 /** Bit 8 - TM2 - Terminal Monitor 2. */
245 unsigned u1TM2 : 1;
246 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
247 unsigned u1SSSE3 : 1;
248 /** Bit 10 - CNTX-ID - L1 Context ID. */
249 unsigned u1CNTXID : 1;
250 /** Bit 11 - Reserved. */
251 unsigned u1Reserved1 : 1;
252 /** Bit 12 - FMA. */
253 unsigned u1FMA : 1;
254 /** Bit 13 - CX16 - CMPXCHG16B. */
255 unsigned u1CX16 : 1;
256 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
257 unsigned u1TPRUpdate : 1;
258 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
259 unsigned u1PDCM : 1;
260 /** Bit 16 - Reserved. */
261 unsigned u1Reserved2 : 1;
262 /** Bit 17 - PCID - Process-context identifiers. */
263 unsigned u1PCID : 1;
264 /** Bit 18 - Direct Cache Access. */
265 unsigned u1DCA : 1;
266 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
267 unsigned u1SSE4_1 : 1;
268 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
269 unsigned u1SSE4_2 : 1;
270 /** Bit 21 - x2APIC. */
271 unsigned u1x2APIC : 1;
272 /** Bit 22 - MOVBE - Supports MOVBE. */
273 unsigned u1MOVBE : 1;
274 /** Bit 23 - POPCNT - Supports POPCNT. */
275 unsigned u1POPCNT : 1;
276 /** Bit 24 - TSC-Deadline. */
277 unsigned u1TSCDEADLINE : 1;
278 /** Bit 25 - AES. */
279 unsigned u1AES : 1;
280 /** Bit 26 - XSAVE - Supports XSAVE. */
281 unsigned u1XSAVE : 1;
282 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
283 unsigned u1OSXSAVE : 1;
284 /** Bit 28 - AVX - Supports AVX instruction extensions. */
285 unsigned u1AVX : 1;
286 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
287 unsigned u1F16C : 1;
288 /** Bit 30 - RDRAND - Supports RDRAND. */
289 unsigned u1RDRAND : 1;
290 /** Bit 31 - Hypervisor present (we're a guest). */
291 unsigned u1HVP : 1;
292} X86CPUIDFEATECX;
293#else /* VBOX_FOR_DTRACE_LIB */
294typedef uint32_t X86CPUIDFEATECX;
295#endif /* VBOX_FOR_DTRACE_LIB */
296/** Pointer to CPUID Feature Information - ECX. */
297typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
298/** Pointer to const CPUID Feature Information - ECX. */
299typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
300
301
302/** CPUID Feature Information - EDX.
303 * CPUID query with EAX=1.
304 */
305#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
306typedef struct X86CPUIDFEATEDX
307{
308 /** Bit 0 - FPU - x87 FPU on Chip. */
309 unsigned u1FPU : 1;
310 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
311 unsigned u1VME : 1;
312 /** Bit 2 - DE - Debugging extensions. */
313 unsigned u1DE : 1;
314 /** Bit 3 - PSE - Page Size Extension. */
315 unsigned u1PSE : 1;
316 /** Bit 4 - TSC - Time Stamp Counter. */
317 unsigned u1TSC : 1;
318 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
319 unsigned u1MSR : 1;
320 /** Bit 6 - PAE - Physical Address Extension. */
321 unsigned u1PAE : 1;
322 /** Bit 7 - MCE - Machine Check Exception. */
323 unsigned u1MCE : 1;
324 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
325 unsigned u1CX8 : 1;
326 /** Bit 9 - APIC - APIC On-Chip. */
327 unsigned u1APIC : 1;
328 /** Bit 10 - Reserved. */
329 unsigned u1Reserved1 : 1;
330 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
331 unsigned u1SEP : 1;
332 /** Bit 12 - MTRR - Memory Type Range Registers. */
333 unsigned u1MTRR : 1;
334 /** Bit 13 - PGE - PTE Global Bit. */
335 unsigned u1PGE : 1;
336 /** Bit 14 - MCA - Machine Check Architecture. */
337 unsigned u1MCA : 1;
338 /** Bit 15 - CMOV - Conditional Move Instructions. */
339 unsigned u1CMOV : 1;
340 /** Bit 16 - PAT - Page Attribute Table. */
341 unsigned u1PAT : 1;
342 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
343 unsigned u1PSE36 : 1;
344 /** Bit 18 - PSN - Processor Serial Number. */
345 unsigned u1PSN : 1;
346 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
347 unsigned u1CLFSH : 1;
348 /** Bit 20 - Reserved. */
349 unsigned u1Reserved2 : 1;
350 /** Bit 21 - DS - Debug Store. */
351 unsigned u1DS : 1;
352 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
353 unsigned u1ACPI : 1;
354 /** Bit 23 - MMX - Intel MMX 'Technology'. */
355 unsigned u1MMX : 1;
356 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
357 unsigned u1FXSR : 1;
358 /** Bit 25 - SSE - SSE Support. */
359 unsigned u1SSE : 1;
360 /** Bit 26 - SSE2 - SSE2 Support. */
361 unsigned u1SSE2 : 1;
362 /** Bit 27 - SS - Self Snoop. */
363 unsigned u1SS : 1;
364 /** Bit 28 - HTT - Hyper-Threading Technology. */
365 unsigned u1HTT : 1;
366 /** Bit 29 - TM - Thermal Monitor. */
367 unsigned u1TM : 1;
368 /** Bit 30 - Reserved - . */
369 unsigned u1Reserved3 : 1;
370 /** Bit 31 - PBE - Pending Break Enabled. */
371 unsigned u1PBE : 1;
372} X86CPUIDFEATEDX;
373#else /* VBOX_FOR_DTRACE_LIB */
374typedef uint32_t X86CPUIDFEATEDX;
375#endif /* VBOX_FOR_DTRACE_LIB */
376/** Pointer to CPUID Feature Information - EDX. */
377typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
378/** Pointer to const CPUID Feature Information - EDX. */
379typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
380
381/** @name CPUID Vendor information.
382 * CPUID query with EAX=0.
383 * @{
384 */
385#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
386#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
387#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
388
389#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
390#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
391#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
392
393#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
394#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
395#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
396/** @} */
397
398
399/** @name CPUID Feature information.
400 * CPUID query with EAX=1.
401 * @{
402 */
403/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
404#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
405/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
406#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
407/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
408#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
409/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
410#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
411/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
412#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
413/** ECX Bit 5 - VMX - Virtual Machine Technology. */
414#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
415/** ECX Bit 6 - SMX - Safer Mode Extensions. */
416#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
417/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
418#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
419/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
420#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
421/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
422#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
423/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
424#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
425/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
426 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
427#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
428/** ECX Bit 12 - FMA. */
429#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
430/** ECX Bit 13 - CX16 - CMPXCHG16B. */
431#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
432/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
433#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
434/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
435#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
436/** ECX Bit 17 - PCID - Process-context identifiers. */
437#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
438/** ECX Bit 18 - DCA - Direct Cache Access. */
439#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
440/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
441#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
442/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
443#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
444/** ECX Bit 21 - x2APIC support. */
445#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
446/** ECX Bit 22 - MOVBE instruction. */
447#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
448/** ECX Bit 23 - POPCNT instruction. */
449#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
450/** ECX Bir 24 - TSC-Deadline. */
451#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
452/** ECX Bit 25 - AES instructions. */
453#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
454/** ECX Bit 26 - XSAVE instruction. */
455#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
456/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
457#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
458/** ECX Bit 28 - AVX. */
459#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
460/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
461#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
462/** ECX Bit 30 - RDRAND instruction. */
463#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
464/** ECX Bit 31 - Hypervisor Present (software only). */
465#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
466
467
468/** Bit 0 - FPU - x87 FPU on Chip. */
469#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
470/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
471#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
472/** Bit 2 - DE - Debugging extensions. */
473#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
474/** Bit 3 - PSE - Page Size Extension. */
475#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
476#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
477/** Bit 4 - TSC - Time Stamp Counter. */
478#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
479/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
480#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
481/** Bit 6 - PAE - Physical Address Extension. */
482#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
483#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
484/** Bit 7 - MCE - Machine Check Exception. */
485#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
486/** Bit 8 - CX8 - CMPXCHG8B instruction. */
487#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
488/** Bit 9 - APIC - APIC On-Chip. */
489#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
490/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
491#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
492/** Bit 12 - MTRR - Memory Type Range Registers. */
493#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
494/** Bit 13 - PGE - PTE Global Bit. */
495#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
496/** Bit 14 - MCA - Machine Check Architecture. */
497#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
498/** Bit 15 - CMOV - Conditional Move Instructions. */
499#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
500/** Bit 16 - PAT - Page Attribute Table. */
501#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
502/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
503#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
504/** Bit 18 - PSN - Processor Serial Number. */
505#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
506/** Bit 19 - CLFSH - CLFLUSH Instruction. */
507#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
508/** Bit 21 - DS - Debug Store. */
509#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
510/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
511#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
512/** Bit 23 - MMX - Intel MMX Technology. */
513#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
514/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
515#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
516/** Bit 25 - SSE - SSE Support. */
517#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
518/** Bit 26 - SSE2 - SSE2 Support. */
519#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
520/** Bit 27 - SS - Self Snoop. */
521#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
522/** Bit 28 - HTT - Hyper-Threading Technology. */
523#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
524/** Bit 29 - TM - Therm. Monitor. */
525#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
526/** Bit 31 - PBE - Pending Break Enabled. */
527#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
528/** @} */
529
530/** @name CPUID mwait/monitor information.
531 * CPUID query with EAX=5.
532 * @{
533 */
534/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
535#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
536/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
537#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
538/** @} */
539
540
541/** @name CPUID Structured Extended Feature information.
542 * CPUID query with EAX=7.
543 * @{
544 */
545/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
546#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
547/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
548#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
549/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
550#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
551/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
552#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
553/** EBX Bit 4 - HLE - Hardware Lock Elision. */
554#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
555/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
556#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
557/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
558#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
559/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
560#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
561/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
562#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
563/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
564#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
565/** EBX Bit 10 - INVPCID - Supports INVPCID. */
566#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
567/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
568#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
569/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
570#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
571/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
572#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
573/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
574#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
575/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
576#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
577/** EBX Bit 16 - AVX512F - Supports AVX512F. */
578#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
579/** EBX Bit 18 - RDSEED - Supports RDSEED. */
580#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
581/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
582#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
583/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
585/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
586#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
587/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
588#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
589/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
590#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
591/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
592#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
593/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
594#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
595/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
596#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
597
598/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
599#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
600/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
601#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
602/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
603#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
604/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
605#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
606/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
607#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
608/** ECX Bit 22 - RDPID - Support pread process ID. */
609#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
610/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
611#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
612
613/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
614 * IBPB command in IA32_PRED_CMD. */
615#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
616/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
617#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
618
619/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
620#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
621
622/** @} */
623
624
625/** @name CPUID Extended Feature information.
626 * CPUID query with EAX=0x80000001.
627 * @{
628 */
629/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
630#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
631
632/** EDX Bit 11 - SYSCALL/SYSRET. */
633#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
634/** EDX Bit 20 - No-Execute/Execute-Disable. */
635#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
636/** EDX Bit 26 - 1 GB large page. */
637#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
638/** EDX Bit 27 - RDTSCP. */
639#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
640/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
641#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
642/** @}*/
643
644/** @name CPUID AMD Feature information.
645 * CPUID query with EAX=0x80000001.
646 * @{
647 */
648/** Bit 0 - FPU - x87 FPU on Chip. */
649#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
650/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
651#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
652/** Bit 2 - DE - Debugging extensions. */
653#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
654/** Bit 3 - PSE - Page Size Extension. */
655#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
656/** Bit 4 - TSC - Time Stamp Counter. */
657#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
658/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
659#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
660/** Bit 6 - PAE - Physical Address Extension. */
661#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
662/** Bit 7 - MCE - Machine Check Exception. */
663#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
664/** Bit 8 - CX8 - CMPXCHG8B instruction. */
665#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
666/** Bit 9 - APIC - APIC On-Chip. */
667#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
668/** Bit 12 - MTRR - Memory Type Range Registers. */
669#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
670/** Bit 13 - PGE - PTE Global Bit. */
671#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
672/** Bit 14 - MCA - Machine Check Architecture. */
673#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
674/** Bit 15 - CMOV - Conditional Move Instructions. */
675#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
676/** Bit 16 - PAT - Page Attribute Table. */
677#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
678/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
679#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
680/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
681#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
682/** Bit 23 - MMX - Intel MMX Technology. */
683#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
684/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
685#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
686/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
687#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
688/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
689#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
690/** Bit 31 - 3DNOW - AMD 3DNow. */
691#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
692
693/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
694#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
695/** Bit 2 - SVM - AMD VM extensions. */
696#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
697/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
698#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
699/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
700#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
701/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
702#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
703/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
704#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
705/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
706#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
707/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
708#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
709/** Bit 9 - OSVW - AMD OS visible workaround. */
710#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
711/** Bit 10 - IBS - Instruct based sampling. */
712#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
713/** Bit 11 - XOP - Extended operation support (see APM6). */
714#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
715/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
716#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
717/** Bit 13 - WDT - AMD Watchdog timer support. */
718#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
719/** Bit 15 - LWP - Lightweight profiling support. */
720#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
721/** Bit 16 - FMA4 - Four operand FMA instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
723/** Bit 19 - NodeId - Indicates support for
724 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
725#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
726/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
727#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
728/** Bit 22 - TopologyExtensions - . */
729#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
730/** @} */
731
732
733/** @name CPUID AMD Feature information.
734 * CPUID query with EAX=0x80000007.
735 * @{
736 */
737/** Bit 0 - TS - Temperature Sensor. */
738#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
739/** Bit 1 - FID - Frequency ID Control. */
740#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
741/** Bit 2 - VID - Voltage ID Control. */
742#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
743/** Bit 3 - TTP - THERMTRIP. */
744#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
745/** Bit 4 - TM - Hardware Thermal Control. */
746#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
747/** Bit 5 - STC - Software Thermal Control. */
748#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
749/** Bit 6 - MC - 100 Mhz Multiplier Control. */
750#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
751/** Bit 7 - HWPSTATE - Hardware P-State Control. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
753/** Bit 8 - TSCINVAR - TSC Invariant. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
755/** Bit 9 - CPB - TSC Invariant. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
757/** Bit 10 - EffFreqRO - MPERF/APERF. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
759/** Bit 11 - PFI - Processor feedback interface (see EAX). */
760#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
761/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
762#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
763/** @} */
764
765
766/** @name CPUID AMD extended feature extensions ID (EBX).
767 * CPUID query with EAX=0x80000008.
768 * @{
769 */
770/** Bit 0 - CLZERO - Clear zero instruction. */
771#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
772/** Bit 1 - IRPerf - Instructions retired count support. */
773#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
774/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
775#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
776/* AMD pipeline length: 9 feature bits ;-) */
777/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
778#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
779/** @} */
780
781
782/** @name CPUID AMD SVM Feature information.
783 * CPUID query with EAX=0x8000000a.
784 * @{
785 */
786/** Bit 0 - NP - Nested Paging supported. */
787#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
788/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
789#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
790/** Bit 2 - SVML - SVM locking bit supported. */
791#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
792/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
793#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
794/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
795#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
796/** Bit 5 - VmcbClean - Support VMCB clean bits. */
797#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
798/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
799 * VMCB.TLB_Control is supported. */
800#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
801/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
802#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
803/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
804#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
805/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
806 * intercept filter cycle count threshold. */
807#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
808/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
809#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
810/** Bit 15 - V_VMSAVE_VMLOAD - Supports virtualized VMSAVE/VMLOAD. */
811#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
812/** Bit 16 - V_VMSAVE_VMLOAD - Supports virtualized GIF. */
813#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
814/** @} */
815
816
817/** @name CR0
818 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
819 * reserved flags.
820 * @{ */
821/** Bit 0 - PE - Protection Enabled */
822#define X86_CR0_PE RT_BIT_32(0)
823#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
824/** Bit 1 - MP - Monitor Coprocessor */
825#define X86_CR0_MP RT_BIT_32(1)
826#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
827/** Bit 2 - EM - Emulation. */
828#define X86_CR0_EM RT_BIT_32(2)
829#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
830/** Bit 3 - TS - Task Switch. */
831#define X86_CR0_TS RT_BIT_32(3)
832#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
833/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
834#define X86_CR0_ET RT_BIT_32(4)
835#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
836/** Bit 5 - NE - Numeric error (486+). */
837#define X86_CR0_NE RT_BIT_32(5)
838#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
839/** Bit 16 - WP - Write Protect (486+). */
840#define X86_CR0_WP RT_BIT_32(16)
841#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
842/** Bit 18 - AM - Alignment Mask (486+). */
843#define X86_CR0_AM RT_BIT_32(18)
844#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
845/** Bit 29 - NW - Not Write-though (486+). */
846#define X86_CR0_NW RT_BIT_32(29)
847#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
848/** Bit 30 - WP - Cache Disable (486+). */
849#define X86_CR0_CD RT_BIT_32(30)
850#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
851/** Bit 31 - PG - Paging. */
852#define X86_CR0_PG RT_BIT_32(31)
853#define X86_CR0_PAGING RT_BIT_32(31)
854/** @} */
855
856
857/** @name CR3
858 * @{ */
859/** Bit 3 - PWT - Page-level Writes Transparent. */
860#define X86_CR3_PWT RT_BIT_32(3)
861/** Bit 4 - PCD - Page-level Cache Disable. */
862#define X86_CR3_PCD RT_BIT_32(4)
863/** Bits 12-31 - - Page directory page number. */
864#define X86_CR3_PAGE_MASK (0xfffff000)
865/** Bits 5-31 - - PAE Page directory page number. */
866#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
867/** Bits 12-51 - - AMD64 Page directory page number. */
868#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
869/** @} */
870
871
872/** @name CR4
873 * @{ */
874/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
875#define X86_CR4_VME RT_BIT_32(0)
876/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
877#define X86_CR4_PVI RT_BIT_32(1)
878/** Bit 2 - TSD - Time Stamp Disable. */
879#define X86_CR4_TSD RT_BIT_32(2)
880/** Bit 3 - DE - Debugging Extensions. */
881#define X86_CR4_DE RT_BIT_32(3)
882/** Bit 4 - PSE - Page Size Extension. */
883#define X86_CR4_PSE RT_BIT_32(4)
884/** Bit 5 - PAE - Physical Address Extension. */
885#define X86_CR4_PAE RT_BIT_32(5)
886/** Bit 6 - MCE - Machine-Check Enable. */
887#define X86_CR4_MCE RT_BIT_32(6)
888/** Bit 7 - PGE - Page Global Enable. */
889#define X86_CR4_PGE RT_BIT_32(7)
890/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
891#define X86_CR4_PCE RT_BIT_32(8)
892/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
893#define X86_CR4_OSFXSR RT_BIT_32(9)
894/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
895#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
896/** Bit 13 - VMXE - VMX mode is enabled. */
897#define X86_CR4_VMXE RT_BIT_32(13)
898/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
899#define X86_CR4_SMXE RT_BIT_32(14)
900/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
901#define X86_CR4_FSGSBASE RT_BIT_32(16)
902/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
903#define X86_CR4_PCIDE RT_BIT_32(17)
904/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
905 * extended states. */
906#define X86_CR4_OSXSAVE RT_BIT_32(18)
907/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
908#define X86_CR4_SMEP RT_BIT_32(20)
909/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
910#define X86_CR4_SMAP RT_BIT_32(21)
911/** Bit 22 - PKE - Protection Key Enable. */
912#define X86_CR4_PKE RT_BIT_32(22)
913/** @} */
914
915
916/** @name DR6
917 * @{ */
918/** Bit 0 - B0 - Breakpoint 0 condition detected. */
919#define X86_DR6_B0 RT_BIT_32(0)
920/** Bit 1 - B1 - Breakpoint 1 condition detected. */
921#define X86_DR6_B1 RT_BIT_32(1)
922/** Bit 2 - B2 - Breakpoint 2 condition detected. */
923#define X86_DR6_B2 RT_BIT_32(2)
924/** Bit 3 - B3 - Breakpoint 3 condition detected. */
925#define X86_DR6_B3 RT_BIT_32(3)
926/** Mask of all the Bx bits. */
927#define X86_DR6_B_MASK UINT64_C(0x0000000f)
928/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
929#define X86_DR6_BD RT_BIT_32(13)
930/** Bit 14 - BS - Single step */
931#define X86_DR6_BS RT_BIT_32(14)
932/** Bit 15 - BT - Task switch. (TSS T bit.) */
933#define X86_DR6_BT RT_BIT_32(15)
934/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
935#define X86_DR6_RTM RT_BIT_32(16)
936/** Value of DR6 after powerup/reset. */
937#define X86_DR6_INIT_VAL UINT64_C(0xFFFF0FF0)
938/** Bits which must be 1s in DR6. */
939#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
940/** Bits which must be 1s in DR6, when RTM is supported. */
941#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
942/** Bits which must be 0s in DR6. */
943#define X86_DR6_RAZ_MASK RT_BIT_64(12)
944/** Bits which must be 0s on writes to DR6. */
945#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
946/** @} */
947
948/** Get the DR6.Bx bit for a the given breakpoint. */
949#define X86_DR6_B(iBp) RT_BIT_64(iBp)
950
951
952/** @name DR7
953 * @{ */
954/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
955#define X86_DR7_L0 RT_BIT_32(0)
956/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
957#define X86_DR7_G0 RT_BIT_32(1)
958/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
959#define X86_DR7_L1 RT_BIT_32(2)
960/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
961#define X86_DR7_G1 RT_BIT_32(3)
962/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
963#define X86_DR7_L2 RT_BIT_32(4)
964/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
965#define X86_DR7_G2 RT_BIT_32(5)
966/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
967#define X86_DR7_L3 RT_BIT_32(6)
968/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
969#define X86_DR7_G3 RT_BIT_32(7)
970/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
971#define X86_DR7_LE RT_BIT_32(8)
972/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
973#define X86_DR7_GE RT_BIT_32(9)
974
975/** L0, L1, L2, and L3. */
976#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
977/** L0, L1, L2, and L3. */
978#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
979
980/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
981 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
982#define X86_DR7_RTM RT_BIT_32(11)
983/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
984 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
985 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
986 * instruction is executed.
987 * @see http://www.rcollins.org/secrets/DR7.html */
988#define X86_DR7_ICE_IR RT_BIT_32(12)
989/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
990 * any DR register is accessed. */
991#define X86_DR7_GD RT_BIT_32(13)
992/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
993 * Pentium. */
994#define X86_DR7_ICE_TR1 RT_BIT_32(14)
995/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
996#define X86_DR7_ICE_TR2 RT_BIT_32(15)
997/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
998#define X86_DR7_RW0_MASK (3 << 16)
999/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1000#define X86_DR7_LEN0_MASK (3 << 18)
1001/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1002#define X86_DR7_RW1_MASK (3 << 20)
1003/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1004#define X86_DR7_LEN1_MASK (3 << 22)
1005/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1006#define X86_DR7_RW2_MASK (3 << 24)
1007/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1008#define X86_DR7_LEN2_MASK (3 << 26)
1009/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1010#define X86_DR7_RW3_MASK (3 << 28)
1011/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1012#define X86_DR7_LEN3_MASK (3 << 30)
1013
1014/** Bits which reads as 1s. */
1015#define X86_DR7_RA1_MASK RT_BIT_32(10)
1016/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1017#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1018/** Bits which must be 0s when writing to DR7. */
1019#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1020
1021/** Calcs the L bit of Nth breakpoint.
1022 * @param iBp The breakpoint number [0..3].
1023 */
1024#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1025
1026/** Calcs the G bit of Nth breakpoint.
1027 * @param iBp The breakpoint number [0..3].
1028 */
1029#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1030
1031/** Calcs the L and G bits of Nth breakpoint.
1032 * @param iBp The breakpoint number [0..3].
1033 */
1034#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1035
1036/** @name Read/Write values.
1037 * @{ */
1038/** Break on instruction fetch only. */
1039#define X86_DR7_RW_EO UINT32_C(0)
1040/** Break on write only. */
1041#define X86_DR7_RW_WO UINT32_C(1)
1042/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1043#define X86_DR7_RW_IO UINT32_C(2)
1044/** Break on read or write (but not instruction fetches). */
1045#define X86_DR7_RW_RW UINT32_C(3)
1046/** @} */
1047
1048/** Shifts a X86_DR7_RW_* value to its right place.
1049 * @param iBp The breakpoint number [0..3].
1050 * @param fRw One of the X86_DR7_RW_* value.
1051 */
1052#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1053
1054/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1055 * one of the X86_DR7_RW_XXX constants).
1056 *
1057 * @returns X86_DR7_RW_XXX
1058 * @param uDR7 DR7 value
1059 * @param iBp The breakpoint number [0..3].
1060 */
1061#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1062
1063/** R/W0, R/W1, R/W2, and R/W3. */
1064#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1065
1066#ifndef VBOX_FOR_DTRACE_LIB
1067/** Checks if there are any I/O breakpoint types configured in the RW
1068 * registers. Does NOT check if these are enabled, sorry. */
1069# define X86_DR7_ANY_RW_IO(uDR7) \
1070 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1071 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1072AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1073AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1074AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1075AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1076AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1077AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1078AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1079AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1080AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1081#endif /* !VBOX_FOR_DTRACE_LIB */
1082
1083/** @name Length values.
1084 * @{ */
1085#define X86_DR7_LEN_BYTE UINT32_C(0)
1086#define X86_DR7_LEN_WORD UINT32_C(1)
1087#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1088#define X86_DR7_LEN_DWORD UINT32_C(3)
1089/** @} */
1090
1091/** Shifts a X86_DR7_LEN_* value to its right place.
1092 * @param iBp The breakpoint number [0..3].
1093 * @param cb One of the X86_DR7_LEN_* values.
1094 */
1095#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1096
1097/** Fetch the breakpoint length bits from the DR7 value.
1098 * @param uDR7 DR7 value
1099 * @param iBp The breakpoint number [0..3].
1100 */
1101#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1102
1103/** Mask used to check if any breakpoints are enabled. */
1104#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1105
1106/** LEN0, LEN1, LEN2, and LEN3. */
1107#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1108/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1109#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1110
1111/** Value of DR7 after powerup/reset. */
1112#define X86_DR7_INIT_VAL 0x400
1113/** @} */
1114
1115
1116/** @name Machine Specific Registers
1117 * @{
1118 */
1119/** Machine check address register (P5). */
1120#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1121/** Machine check type register (P5). */
1122#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1123/** Time Stamp Counter. */
1124#define MSR_IA32_TSC 0x10
1125#define MSR_IA32_CESR UINT32_C(0x00000011)
1126#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1127#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1128
1129#define MSR_IA32_PLATFORM_ID 0x17
1130
1131#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1132# define MSR_IA32_APICBASE 0x1b
1133/** Local APIC enabled. */
1134# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1135/** X2APIC enabled (requires the EN bit to be set). */
1136# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1137/** The processor is the boot strap processor (BSP). */
1138# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1139/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1140 * width. */
1141# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1142/** The default physical base address of the APIC. */
1143# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1144/** Gets the physical base address from the MSR. */
1145# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1146#endif
1147
1148/** Undocumented intel MSR for reporting thread and core counts.
1149 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1150 * first 16 bits is the thread count. The next 16 bits the core count, except
1151 * on Westmere where it seems it's only the next 4 bits for some reason. */
1152#define MSR_CORE_THREAD_COUNT 0x35
1153
1154/** CPU Feature control. */
1155#define MSR_IA32_FEATURE_CONTROL 0x3A
1156/** Feature control - Lock MSR from writes (R/W0). */
1157#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1158/** Feature control - Enable VMX inside SMX operation (R/WL). */
1159#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1160/** Feature control - Enable VMX outside SMX operation (R/WL). */
1161#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1162/** Feature control - SENTER local functions enable (R/WL). */
1163#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1164#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1165#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1166#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1167#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1168#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1169#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1170/** Feature control - SENTER global enable (R/WL). */
1171#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1172/** Feature control - SGX launch control enable (R/WL). */
1173#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1174/** Feature control - SGX global enable (R/WL). */
1175#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1176/** Feature control - LMCE on (R/WL). */
1177#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1178
1179/** Per-processor TSC adjust MSR. */
1180#define MSR_IA32_TSC_ADJUST 0x3B
1181
1182/** Spectre control register.
1183 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1184#define MSR_IA32_SPEC_CTRL 0x48
1185/** IBRS - Indirect branch restricted speculation. */
1186#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1187/** STIBP - Single thread indirect branch predictors. */
1188#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1189
1190/** Prediction command register.
1191 * Write only, logical processor scope, no state since write only. */
1192#define MSR_IA32_PRED_CMD 0x49
1193/** IBPB - Indirect branch prediction barrie when written as 1. */
1194#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1195
1196/** BIOS update trigger (microcode update). */
1197#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1198
1199/** BIOS update signature (microcode). */
1200#define MSR_IA32_BIOS_SIGN_ID 0x8B
1201
1202/** SMM monitor control. */
1203#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1204/** SMM control - Valid. */
1205#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1206/** SMM control - VMXOFF unblocks SMI. */
1207#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1208/** SMM control - MSEG base physical address. */
1209#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1210
1211/** General performance counter no. 0. */
1212#define MSR_IA32_PMC0 0xC1
1213/** General performance counter no. 1. */
1214#define MSR_IA32_PMC1 0xC2
1215/** General performance counter no. 2. */
1216#define MSR_IA32_PMC2 0xC3
1217/** General performance counter no. 3. */
1218#define MSR_IA32_PMC3 0xC4
1219
1220/** Nehalem power control. */
1221#define MSR_IA32_PLATFORM_INFO 0xCE
1222
1223/** Get FSB clock status (Intel-specific). */
1224#define MSR_IA32_FSB_CLOCK_STS 0xCD
1225
1226/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1227#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1228
1229/** C0 Maximum Frequency Clock Count */
1230#define MSR_IA32_MPERF 0xE7
1231/** C0 Actual Frequency Clock Count */
1232#define MSR_IA32_APERF 0xE8
1233
1234/** MTRR Capabilities. */
1235#define MSR_IA32_MTRR_CAP 0xFE
1236
1237/** Architecture capabilities (bugfixes).
1238 * @note May move */
1239#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1240/** CPU is no subject to spectre problems. */
1241#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
1242/** CPU has better IBRS and you can leave it on all the time. */
1243#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
1244
1245/** Cache control/info. */
1246#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1247
1248#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1249/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1250 * R0 SS == CS + 8
1251 * R3 CS == CS + 16
1252 * R3 SS == CS + 24
1253 */
1254#define MSR_IA32_SYSENTER_CS 0x174
1255/** SYSENTER_ESP - the R0 ESP. */
1256#define MSR_IA32_SYSENTER_ESP 0x175
1257/** SYSENTER_EIP - the R0 EIP. */
1258#define MSR_IA32_SYSENTER_EIP 0x176
1259#endif
1260
1261/** Machine Check Global Capabilities Register. */
1262#define MSR_IA32_MCG_CAP 0x179
1263/** Machine Check Global Status Register. */
1264#define MSR_IA32_MCG_STATUS 0x17A
1265/** Machine Check Global Control Register. */
1266#define MSR_IA32_MCG_CTRL 0x17B
1267
1268/** Page Attribute Table. */
1269#define MSR_IA32_CR_PAT 0x277
1270/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1271 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1272#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1273
1274/** Performance counter MSRs. (Intel only) */
1275#define MSR_IA32_PERFEVTSEL0 0x186
1276#define MSR_IA32_PERFEVTSEL1 0x187
1277/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1278 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1279 * holds a ratio that Apple takes for TSC granularity.
1280 *
1281 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1282#define MSR_FLEX_RATIO 0x194
1283/** Performance state value and starting with Intel core more.
1284 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1285#define MSR_IA32_PERF_STATUS 0x198
1286#define MSR_IA32_PERF_CTL 0x199
1287#define MSR_IA32_THERM_STATUS 0x19c
1288
1289/** Enable misc. processor features (R/W). */
1290#define MSR_IA32_MISC_ENABLE 0x1A0
1291/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1292#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1293/** Automatic Thermal Control Circuit Enable (R/W). */
1294#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1295/** Performance Monitoring Available (R). */
1296#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1297/** Branch Trace Storage Unavailable (R/O). */
1298#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1299/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1300#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1301/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1302#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1303/** If MONITOR/MWAIT is supported (R/W). */
1304#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1305/** Limit CPUID Maxval to 3 leafs (R/W). */
1306#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1307/** When set to 1, xTPR messages are disabled (R/W). */
1308#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1309/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1310#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1311
1312/** Trace/Profile Resource Control (R/W) */
1313#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1314/** Last branch record. */
1315#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1316/** Branch trace flag (single step on branches). */
1317#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1318/** Performance monitoring pin control (AMD only). */
1319#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1320#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1321#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1322#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1323/** Trace message enable (Intel only). */
1324#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1325/** Branch trace store (Intel only). */
1326#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1327/** Branch trace interrupt (Intel only). */
1328#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1329/** Branch trace off in privileged code (Intel only). */
1330#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1331/** Branch trace off in user code (Intel only). */
1332#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1333/** Freeze LBR on PMI flag (Intel only). */
1334#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1335/** Freeze PERFMON on PMI flag (Intel only). */
1336#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1337/** Freeze while SMM enabled (Intel only). */
1338#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1339/** Advanced debugging of RTM regions (Intel only). */
1340#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1341
1342/** The number (0..3 or 0..15) of the last branch record register on P4 and
1343 * related Xeons. */
1344#define MSR_P4_LASTBRANCH_TOS UINT32_C(0x000001da)
1345/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1346 * @{ */
1347#define MSR_P4_LASTBRANCH_0 UINT32_C(0x000001db)
1348#define MSR_P4_LASTBRANCH_1 UINT32_C(0x000001dc)
1349#define MSR_P4_LASTBRANCH_2 UINT32_C(0x000001dd)
1350#define MSR_P4_LASTBRANCH_3 UINT32_C(0x000001de)
1351/** @} */
1352
1353
1354#define IA32_MTRR_PHYSBASE0 0x200
1355#define IA32_MTRR_PHYSMASK0 0x201
1356#define IA32_MTRR_PHYSBASE1 0x202
1357#define IA32_MTRR_PHYSMASK1 0x203
1358#define IA32_MTRR_PHYSBASE2 0x204
1359#define IA32_MTRR_PHYSMASK2 0x205
1360#define IA32_MTRR_PHYSBASE3 0x206
1361#define IA32_MTRR_PHYSMASK3 0x207
1362#define IA32_MTRR_PHYSBASE4 0x208
1363#define IA32_MTRR_PHYSMASK4 0x209
1364#define IA32_MTRR_PHYSBASE5 0x20a
1365#define IA32_MTRR_PHYSMASK5 0x20b
1366#define IA32_MTRR_PHYSBASE6 0x20c
1367#define IA32_MTRR_PHYSMASK6 0x20d
1368#define IA32_MTRR_PHYSBASE7 0x20e
1369#define IA32_MTRR_PHYSMASK7 0x20f
1370#define IA32_MTRR_PHYSBASE8 0x210
1371#define IA32_MTRR_PHYSMASK8 0x211
1372#define IA32_MTRR_PHYSBASE9 0x212
1373#define IA32_MTRR_PHYSMASK9 0x213
1374
1375/** Fixed range MTRRs.
1376 * @{ */
1377#define IA32_MTRR_FIX64K_00000 0x250
1378#define IA32_MTRR_FIX16K_80000 0x258
1379#define IA32_MTRR_FIX16K_A0000 0x259
1380#define IA32_MTRR_FIX4K_C0000 0x268
1381#define IA32_MTRR_FIX4K_C8000 0x269
1382#define IA32_MTRR_FIX4K_D0000 0x26a
1383#define IA32_MTRR_FIX4K_D8000 0x26b
1384#define IA32_MTRR_FIX4K_E0000 0x26c
1385#define IA32_MTRR_FIX4K_E8000 0x26d
1386#define IA32_MTRR_FIX4K_F0000 0x26e
1387#define IA32_MTRR_FIX4K_F8000 0x26f
1388/** @} */
1389
1390/** MTRR Default Range. */
1391#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1392
1393/** Global performance counter control facilities (Intel only). */
1394#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1395#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1396#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1397
1398/** Precise Event Based sampling (Intel only). */
1399#define MSR_IA32_PEBS_ENABLE 0x3F1
1400
1401#define MSR_IA32_MC0_CTL 0x400
1402#define MSR_IA32_MC0_STATUS 0x401
1403
1404/** Basic VMX information. */
1405#define MSR_IA32_VMX_BASIC 0x480
1406/** Allowed settings for pin-based VM execution controls. */
1407#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1408/** Allowed settings for proc-based VM execution controls. */
1409#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1410/** Allowed settings for the VM-exit controls. */
1411#define MSR_IA32_VMX_EXIT_CTLS 0x483
1412/** Allowed settings for the VM-entry controls. */
1413#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1414/** Misc VMX info. */
1415#define MSR_IA32_VMX_MISC 0x485
1416/** Fixed cleared bits in CR0. */
1417#define MSR_IA32_VMX_CR0_FIXED0 0x486
1418/** Fixed set bits in CR0. */
1419#define MSR_IA32_VMX_CR0_FIXED1 0x487
1420/** Fixed cleared bits in CR4. */
1421#define MSR_IA32_VMX_CR4_FIXED0 0x488
1422/** Fixed set bits in CR4. */
1423#define MSR_IA32_VMX_CR4_FIXED1 0x489
1424/** Information for enumerating fields in the VMCS. */
1425#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1426/** Allowed settings for the VM-functions controls. */
1427#define MSR_IA32_VMX_VMFUNC 0x491
1428/** Allowed settings for secondary proc-based VM execution controls */
1429#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1430/** EPT capabilities. */
1431#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1432/** Allowed settings of all pin-based VM execution controls. */
1433#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1434/** Allowed settings of all proc-based VM execution controls. */
1435#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1436/** Allowed settings of all VMX exit controls. */
1437#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1438/** Allowed settings of all VMX entry controls. */
1439#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1440/** Allowed settings for the VM-function controls. */
1441#define MSR_IA32_VMX_VMFUNC 0x491
1442
1443
1444/** DS Save Area (R/W). */
1445#define MSR_IA32_DS_AREA 0x600
1446/** Running Average Power Limit (RAPL) power units. */
1447#define MSR_RAPL_POWER_UNIT 0x606
1448
1449/** X2APIC MSR range start. */
1450#define MSR_IA32_X2APIC_START 0x800
1451/** X2APIC MSR - APIC ID Register. */
1452#define MSR_IA32_X2APIC_ID 0x802
1453/** X2APIC MSR - APIC Version Register. */
1454#define MSR_IA32_X2APIC_VERSION 0x803
1455/** X2APIC MSR - Task Priority Register. */
1456#define MSR_IA32_X2APIC_TPR 0x808
1457/** X2APIC MSR - Processor Priority register. */
1458#define MSR_IA32_X2APIC_PPR 0x80A
1459/** X2APIC MSR - End Of Interrupt register. */
1460#define MSR_IA32_X2APIC_EOI 0x80B
1461/** X2APIC MSR - Logical Destination Register. */
1462#define MSR_IA32_X2APIC_LDR 0x80D
1463/** X2APIC MSR - Spurious Interrupt Vector Register. */
1464#define MSR_IA32_X2APIC_SVR 0x80F
1465/** X2APIC MSR - In-service Register (bits 31:0). */
1466#define MSR_IA32_X2APIC_ISR0 0x810
1467/** X2APIC MSR - In-service Register (bits 63:32). */
1468#define MSR_IA32_X2APIC_ISR1 0x811
1469/** X2APIC MSR - In-service Register (bits 95:64). */
1470#define MSR_IA32_X2APIC_ISR2 0x812
1471/** X2APIC MSR - In-service Register (bits 127:96). */
1472#define MSR_IA32_X2APIC_ISR3 0x813
1473/** X2APIC MSR - In-service Register (bits 159:128). */
1474#define MSR_IA32_X2APIC_ISR4 0x814
1475/** X2APIC MSR - In-service Register (bits 191:160). */
1476#define MSR_IA32_X2APIC_ISR5 0x815
1477/** X2APIC MSR - In-service Register (bits 223:192). */
1478#define MSR_IA32_X2APIC_ISR6 0x816
1479/** X2APIC MSR - In-service Register (bits 255:224). */
1480#define MSR_IA32_X2APIC_ISR7 0x817
1481/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1482#define MSR_IA32_X2APIC_TMR0 0x818
1483/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1484#define MSR_IA32_X2APIC_TMR1 0x819
1485/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1486#define MSR_IA32_X2APIC_TMR2 0x81A
1487/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1488#define MSR_IA32_X2APIC_TMR3 0x81B
1489/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1490#define MSR_IA32_X2APIC_TMR4 0x81C
1491/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1492#define MSR_IA32_X2APIC_TMR5 0x81D
1493/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1494#define MSR_IA32_X2APIC_TMR6 0x81E
1495/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1496#define MSR_IA32_X2APIC_TMR7 0x81F
1497/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1498#define MSR_IA32_X2APIC_IRR0 0x820
1499/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1500#define MSR_IA32_X2APIC_IRR1 0x821
1501/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1502#define MSR_IA32_X2APIC_IRR2 0x822
1503/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1504#define MSR_IA32_X2APIC_IRR3 0x823
1505/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1506#define MSR_IA32_X2APIC_IRR4 0x824
1507/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1508#define MSR_IA32_X2APIC_IRR5 0x825
1509/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1510#define MSR_IA32_X2APIC_IRR6 0x826
1511/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1512#define MSR_IA32_X2APIC_IRR7 0x827
1513/** X2APIC MSR - Error Status Register. */
1514#define MSR_IA32_X2APIC_ESR 0x828
1515/** X2APIC MSR - LVT CMCI Register. */
1516#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1517/** X2APIC MSR - Interrupt Command Register. */
1518#define MSR_IA32_X2APIC_ICR 0x830
1519/** X2APIC MSR - LVT Timer Register. */
1520#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1521/** X2APIC MSR - LVT Thermal Sensor Register. */
1522#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1523/** X2APIC MSR - LVT Performance Counter Register. */
1524#define MSR_IA32_X2APIC_LVT_PERF 0x834
1525/** X2APIC MSR - LVT LINT0 Register. */
1526#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1527/** X2APIC MSR - LVT LINT1 Register. */
1528#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1529/** X2APIC MSR - LVT Error Register . */
1530#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1531/** X2APIC MSR - Timer Initial Count Register. */
1532#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1533/** X2APIC MSR - Timer Current Count Register. */
1534#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1535/** X2APIC MSR - Timer Divide Configuration Register. */
1536#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1537/** X2APIC MSR - Self IPI. */
1538#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1539/** X2APIC MSR range end. */
1540#define MSR_IA32_X2APIC_END 0xBFF
1541/** X2APIC MSR - LVT start range. */
1542#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1543/** X2APIC MSR - LVT end range (inclusive). */
1544#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1545
1546/** K6 EFER - Extended Feature Enable Register. */
1547#define MSR_K6_EFER UINT32_C(0xc0000080)
1548/** @todo document EFER */
1549/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1550#define MSR_K6_EFER_SCE RT_BIT_32(0)
1551/** Bit 8 - LME - Long mode enabled. (R/W) */
1552#define MSR_K6_EFER_LME RT_BIT_32(8)
1553/** Bit 10 - LMA - Long mode active. (R) */
1554#define MSR_K6_EFER_LMA RT_BIT_32(10)
1555/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1556#define MSR_K6_EFER_NXE RT_BIT_32(11)
1557#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1558/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1559#define MSR_K6_EFER_SVME RT_BIT_32(12)
1560/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1561#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1562/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1563#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1564/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1565#define MSR_K6_EFER_TCE RT_BIT_32(15)
1566/** K6 STAR - SYSCALL/RET targets. */
1567#define MSR_K6_STAR UINT32_C(0xc0000081)
1568/** Shift value for getting the SYSRET CS and SS value. */
1569#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1570/** Shift value for getting the SYSCALL CS and SS value. */
1571#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1572/** Selector mask for use after shifting. */
1573#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1574/** The mask which give the SYSCALL EIP. */
1575#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1576/** K6 WHCR - Write Handling Control Register. */
1577#define MSR_K6_WHCR UINT32_C(0xc0000082)
1578/** K6 UWCCR - UC/WC Cacheability Control Register. */
1579#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1580/** K6 PSOR - Processor State Observability Register. */
1581#define MSR_K6_PSOR UINT32_C(0xc0000087)
1582/** K6 PFIR - Page Flush/Invalidate Register. */
1583#define MSR_K6_PFIR UINT32_C(0xc0000088)
1584
1585/** Performance counter MSRs. (AMD only) */
1586#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1587#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1588#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1589#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1590#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1591#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1592#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1593#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1594
1595/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1596#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1597/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1598#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1599/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1600#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1601/** K8 FS.base - The 64-bit base FS register. */
1602#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1603/** K8 GS.base - The 64-bit base GS register. */
1604#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1605/** K8 KernelGSbase - Used with SWAPGS. */
1606#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1607/** K8 TSC_AUX - Used with RDTSCP. */
1608#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1609#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1610#define MSR_K8_HWCR UINT32_C(0xc0010015)
1611#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1612#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1613#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1614#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1615#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1616#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1617/** North bridge config? See BIOS & Kernel dev guides for
1618 * details. */
1619#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1620
1621/** Hypertransport interrupt pending register.
1622 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1623#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1624
1625/** SVM Control. */
1626#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1627/** Disables HDT (Hardware Debug Tool) and certain internal debug
1628 * features. */
1629#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1630/** If set, non-intercepted INIT signals are converted to \#SX
1631 * exceptions. */
1632#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1633/** Disables A20 masking. */
1634#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1635/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1636#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1637/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1638 * clear, EFER.SVME can be written normally. */
1639#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1640
1641#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1642#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1643/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1644 * host state during world switch. */
1645#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1646
1647/** @} */
1648
1649
1650/** @name Page Table / Directory / Directory Pointers / L4.
1651 * @{
1652 */
1653
1654/** Page table/directory entry as an unsigned integer. */
1655typedef uint32_t X86PGUINT;
1656/** Pointer to a page table/directory table entry as an unsigned integer. */
1657typedef X86PGUINT *PX86PGUINT;
1658/** Pointer to an const page table/directory table entry as an unsigned integer. */
1659typedef X86PGUINT const *PCX86PGUINT;
1660
1661/** Number of entries in a 32-bit PT/PD. */
1662#define X86_PG_ENTRIES 1024
1663
1664
1665/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1666typedef uint64_t X86PGPAEUINT;
1667/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1668typedef X86PGPAEUINT *PX86PGPAEUINT;
1669/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1670typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1671
1672/** Number of entries in a PAE PT/PD. */
1673#define X86_PG_PAE_ENTRIES 512
1674/** Number of entries in a PAE PDPT. */
1675#define X86_PG_PAE_PDPE_ENTRIES 4
1676
1677/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1678#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1679/** Number of entries in an AMD64 PDPT.
1680 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1681#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1682
1683/** The size of a default page. */
1684#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1685/** The page shift of a default page. */
1686#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1687/** The default page offset mask. */
1688#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1689/** The default page base mask for virtual addresses. */
1690#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1691/** The default page base mask for virtual addresses - 32bit version. */
1692#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1693
1694/** The size of a 4KB page. */
1695#define X86_PAGE_4K_SIZE _4K
1696/** The page shift of a 4KB page. */
1697#define X86_PAGE_4K_SHIFT 12
1698/** The 4KB page offset mask. */
1699#define X86_PAGE_4K_OFFSET_MASK 0xfff
1700/** The 4KB page base mask for virtual addresses. */
1701#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1702/** The 4KB page base mask for virtual addresses - 32bit version. */
1703#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1704
1705/** The size of a 2MB page. */
1706#define X86_PAGE_2M_SIZE _2M
1707/** The page shift of a 2MB page. */
1708#define X86_PAGE_2M_SHIFT 21
1709/** The 2MB page offset mask. */
1710#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1711/** The 2MB page base mask for virtual addresses. */
1712#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1713/** The 2MB page base mask for virtual addresses - 32bit version. */
1714#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1715
1716/** The size of a 4MB page. */
1717#define X86_PAGE_4M_SIZE _4M
1718/** The page shift of a 4MB page. */
1719#define X86_PAGE_4M_SHIFT 22
1720/** The 4MB page offset mask. */
1721#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1722/** The 4MB page base mask for virtual addresses. */
1723#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1724/** The 4MB page base mask for virtual addresses - 32bit version. */
1725#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1726
1727/** The size of a 1GB page. */
1728#define X86_PAGE_1G_SIZE _1G
1729/** The page shift of a 1GB page. */
1730#define X86_PAGE_1G_SHIFT 30
1731/** The 1GB page offset mask. */
1732#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1733/** The 1GB page base mask for virtual addresses. */
1734#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1735
1736/**
1737 * Check if the given address is canonical.
1738 */
1739#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1740
1741
1742/** @name Page Table Entry
1743 * @{
1744 */
1745/** Bit 0 - P - Present bit. */
1746#define X86_PTE_BIT_P 0
1747/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1748#define X86_PTE_BIT_RW 1
1749/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1750#define X86_PTE_BIT_US 2
1751/** Bit 3 - PWT - Page level write thru bit. */
1752#define X86_PTE_BIT_PWT 3
1753/** Bit 4 - PCD - Page level cache disable bit. */
1754#define X86_PTE_BIT_PCD 4
1755/** Bit 5 - A - Access bit. */
1756#define X86_PTE_BIT_A 5
1757/** Bit 6 - D - Dirty bit. */
1758#define X86_PTE_BIT_D 6
1759/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1760#define X86_PTE_BIT_PAT 7
1761/** Bit 8 - G - Global flag. */
1762#define X86_PTE_BIT_G 8
1763/** Bits 63 - NX - PAE/LM - No execution flag. */
1764#define X86_PTE_PAE_BIT_NX 63
1765
1766/** Bit 0 - P - Present bit mask. */
1767#define X86_PTE_P RT_BIT_32(0)
1768/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1769#define X86_PTE_RW RT_BIT_32(1)
1770/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1771#define X86_PTE_US RT_BIT_32(2)
1772/** Bit 3 - PWT - Page level write thru bit mask. */
1773#define X86_PTE_PWT RT_BIT_32(3)
1774/** Bit 4 - PCD - Page level cache disable bit mask. */
1775#define X86_PTE_PCD RT_BIT_32(4)
1776/** Bit 5 - A - Access bit mask. */
1777#define X86_PTE_A RT_BIT_32(5)
1778/** Bit 6 - D - Dirty bit mask. */
1779#define X86_PTE_D RT_BIT_32(6)
1780/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1781#define X86_PTE_PAT RT_BIT_32(7)
1782/** Bit 8 - G - Global bit mask. */
1783#define X86_PTE_G RT_BIT_32(8)
1784
1785/** Bits 9-11 - - Available for use to system software. */
1786#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1787/** Bits 12-31 - - Physical Page number of the next level. */
1788#define X86_PTE_PG_MASK ( 0xfffff000 )
1789
1790/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1791#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1792/** Bits 63 - NX - PAE/LM - No execution flag. */
1793#define X86_PTE_PAE_NX RT_BIT_64(63)
1794/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1795#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1796/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1797#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1798/** No bits - - LM - MBZ bits when NX is active. */
1799#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1800/** Bits 63 - - LM - MBZ bits when no NX. */
1801#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1802
1803/**
1804 * Page table entry.
1805 */
1806typedef struct X86PTEBITS
1807{
1808 /** Flags whether(=1) or not the page is present. */
1809 uint32_t u1Present : 1;
1810 /** Read(=0) / Write(=1) flag. */
1811 uint32_t u1Write : 1;
1812 /** User(=1) / Supervisor (=0) flag. */
1813 uint32_t u1User : 1;
1814 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1815 uint32_t u1WriteThru : 1;
1816 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1817 uint32_t u1CacheDisable : 1;
1818 /** Accessed flag.
1819 * Indicates that the page have been read or written to. */
1820 uint32_t u1Accessed : 1;
1821 /** Dirty flag.
1822 * Indicates that the page has been written to. */
1823 uint32_t u1Dirty : 1;
1824 /** Reserved / If PAT enabled, bit 2 of the index. */
1825 uint32_t u1PAT : 1;
1826 /** Global flag. (Ignored in all but final level.) */
1827 uint32_t u1Global : 1;
1828 /** Available for use to system software. */
1829 uint32_t u3Available : 3;
1830 /** Physical Page number of the next level. */
1831 uint32_t u20PageNo : 20;
1832} X86PTEBITS;
1833#ifndef VBOX_FOR_DTRACE_LIB
1834AssertCompileSize(X86PTEBITS, 4);
1835#endif
1836/** Pointer to a page table entry. */
1837typedef X86PTEBITS *PX86PTEBITS;
1838/** Pointer to a const page table entry. */
1839typedef const X86PTEBITS *PCX86PTEBITS;
1840
1841/**
1842 * Page table entry.
1843 */
1844typedef union X86PTE
1845{
1846 /** Unsigned integer view */
1847 X86PGUINT u;
1848 /** Bit field view. */
1849 X86PTEBITS n;
1850 /** 32-bit view. */
1851 uint32_t au32[1];
1852 /** 16-bit view. */
1853 uint16_t au16[2];
1854 /** 8-bit view. */
1855 uint8_t au8[4];
1856} X86PTE;
1857#ifndef VBOX_FOR_DTRACE_LIB
1858AssertCompileSize(X86PTE, 4);
1859#endif
1860/** Pointer to a page table entry. */
1861typedef X86PTE *PX86PTE;
1862/** Pointer to a const page table entry. */
1863typedef const X86PTE *PCX86PTE;
1864
1865
1866/**
1867 * PAE page table entry.
1868 */
1869typedef struct X86PTEPAEBITS
1870{
1871 /** Flags whether(=1) or not the page is present. */
1872 uint32_t u1Present : 1;
1873 /** Read(=0) / Write(=1) flag. */
1874 uint32_t u1Write : 1;
1875 /** User(=1) / Supervisor(=0) flag. */
1876 uint32_t u1User : 1;
1877 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
1878 uint32_t u1WriteThru : 1;
1879 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1880 uint32_t u1CacheDisable : 1;
1881 /** Accessed flag.
1882 * Indicates that the page have been read or written to. */
1883 uint32_t u1Accessed : 1;
1884 /** Dirty flag.
1885 * Indicates that the page has been written to. */
1886 uint32_t u1Dirty : 1;
1887 /** Reserved / If PAT enabled, bit 2 of the index. */
1888 uint32_t u1PAT : 1;
1889 /** Global flag. (Ignored in all but final level.) */
1890 uint32_t u1Global : 1;
1891 /** Available for use to system software. */
1892 uint32_t u3Available : 3;
1893 /** Physical Page number of the next level - Low Part. Don't use this. */
1894 uint32_t u20PageNoLow : 20;
1895 /** Physical Page number of the next level - High Part. Don't use this. */
1896 uint32_t u20PageNoHigh : 20;
1897 /** MBZ bits */
1898 uint32_t u11Reserved : 11;
1899 /** No Execute flag. */
1900 uint32_t u1NoExecute : 1;
1901} X86PTEPAEBITS;
1902#ifndef VBOX_FOR_DTRACE_LIB
1903AssertCompileSize(X86PTEPAEBITS, 8);
1904#endif
1905/** Pointer to a page table entry. */
1906typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1907/** Pointer to a page table entry. */
1908typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1909
1910/**
1911 * PAE Page table entry.
1912 */
1913typedef union X86PTEPAE
1914{
1915 /** Unsigned integer view */
1916 X86PGPAEUINT u;
1917 /** Bit field view. */
1918 X86PTEPAEBITS n;
1919 /** 32-bit view. */
1920 uint32_t au32[2];
1921 /** 16-bit view. */
1922 uint16_t au16[4];
1923 /** 8-bit view. */
1924 uint8_t au8[8];
1925} X86PTEPAE;
1926#ifndef VBOX_FOR_DTRACE_LIB
1927AssertCompileSize(X86PTEPAE, 8);
1928#endif
1929/** Pointer to a PAE page table entry. */
1930typedef X86PTEPAE *PX86PTEPAE;
1931/** Pointer to a const PAE page table entry. */
1932typedef const X86PTEPAE *PCX86PTEPAE;
1933/** @} */
1934
1935/**
1936 * Page table.
1937 */
1938typedef struct X86PT
1939{
1940 /** PTE Array. */
1941 X86PTE a[X86_PG_ENTRIES];
1942} X86PT;
1943#ifndef VBOX_FOR_DTRACE_LIB
1944AssertCompileSize(X86PT, 4096);
1945#endif
1946/** Pointer to a page table. */
1947typedef X86PT *PX86PT;
1948/** Pointer to a const page table. */
1949typedef const X86PT *PCX86PT;
1950
1951/** The page shift to get the PT index. */
1952#define X86_PT_SHIFT 12
1953/** The PT index mask (apply to a shifted page address). */
1954#define X86_PT_MASK 0x3ff
1955
1956
1957/**
1958 * Page directory.
1959 */
1960typedef struct X86PTPAE
1961{
1962 /** PTE Array. */
1963 X86PTEPAE a[X86_PG_PAE_ENTRIES];
1964} X86PTPAE;
1965#ifndef VBOX_FOR_DTRACE_LIB
1966AssertCompileSize(X86PTPAE, 4096);
1967#endif
1968/** Pointer to a page table. */
1969typedef X86PTPAE *PX86PTPAE;
1970/** Pointer to a const page table. */
1971typedef const X86PTPAE *PCX86PTPAE;
1972
1973/** The page shift to get the PA PTE index. */
1974#define X86_PT_PAE_SHIFT 12
1975/** The PAE PT index mask (apply to a shifted page address). */
1976#define X86_PT_PAE_MASK 0x1ff
1977
1978
1979/** @name 4KB Page Directory Entry
1980 * @{
1981 */
1982/** Bit 0 - P - Present bit. */
1983#define X86_PDE_P RT_BIT_32(0)
1984/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1985#define X86_PDE_RW RT_BIT_32(1)
1986/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1987#define X86_PDE_US RT_BIT_32(2)
1988/** Bit 3 - PWT - Page level write thru bit. */
1989#define X86_PDE_PWT RT_BIT_32(3)
1990/** Bit 4 - PCD - Page level cache disable bit. */
1991#define X86_PDE_PCD RT_BIT_32(4)
1992/** Bit 5 - A - Access bit. */
1993#define X86_PDE_A RT_BIT_32(5)
1994/** Bit 7 - PS - Page size attribute.
1995 * Clear mean 4KB pages, set means large pages (2/4MB). */
1996#define X86_PDE_PS RT_BIT_32(7)
1997/** Bits 9-11 - - Available for use to system software. */
1998#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1999/** Bits 12-31 - - Physical Page number of the next level. */
2000#define X86_PDE_PG_MASK ( 0xfffff000 )
2001
2002/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2003#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2004/** Bits 63 - NX - PAE/LM - No execution flag. */
2005#define X86_PDE_PAE_NX RT_BIT_64(63)
2006/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2007#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2008/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2009#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2010/** Bit 7 - - LM - MBZ bits when NX is active. */
2011#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2012/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2013#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2014
2015/**
2016 * Page directory entry.
2017 */
2018typedef struct X86PDEBITS
2019{
2020 /** Flags whether(=1) or not the page is present. */
2021 uint32_t u1Present : 1;
2022 /** Read(=0) / Write(=1) flag. */
2023 uint32_t u1Write : 1;
2024 /** User(=1) / Supervisor (=0) flag. */
2025 uint32_t u1User : 1;
2026 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2027 uint32_t u1WriteThru : 1;
2028 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2029 uint32_t u1CacheDisable : 1;
2030 /** Accessed flag.
2031 * Indicates that the page has been read or written to. */
2032 uint32_t u1Accessed : 1;
2033 /** Reserved / Ignored (dirty bit). */
2034 uint32_t u1Reserved0 : 1;
2035 /** Size bit if PSE is enabled - in any event it's 0. */
2036 uint32_t u1Size : 1;
2037 /** Reserved / Ignored (global bit). */
2038 uint32_t u1Reserved1 : 1;
2039 /** Available for use to system software. */
2040 uint32_t u3Available : 3;
2041 /** Physical Page number of the next level. */
2042 uint32_t u20PageNo : 20;
2043} X86PDEBITS;
2044#ifndef VBOX_FOR_DTRACE_LIB
2045AssertCompileSize(X86PDEBITS, 4);
2046#endif
2047/** Pointer to a page directory entry. */
2048typedef X86PDEBITS *PX86PDEBITS;
2049/** Pointer to a const page directory entry. */
2050typedef const X86PDEBITS *PCX86PDEBITS;
2051
2052
2053/**
2054 * PAE page directory entry.
2055 */
2056typedef struct X86PDEPAEBITS
2057{
2058 /** Flags whether(=1) or not the page is present. */
2059 uint32_t u1Present : 1;
2060 /** Read(=0) / Write(=1) flag. */
2061 uint32_t u1Write : 1;
2062 /** User(=1) / Supervisor (=0) flag. */
2063 uint32_t u1User : 1;
2064 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2065 uint32_t u1WriteThru : 1;
2066 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2067 uint32_t u1CacheDisable : 1;
2068 /** Accessed flag.
2069 * Indicates that the page has been read or written to. */
2070 uint32_t u1Accessed : 1;
2071 /** Reserved / Ignored (dirty bit). */
2072 uint32_t u1Reserved0 : 1;
2073 /** Size bit if PSE is enabled - in any event it's 0. */
2074 uint32_t u1Size : 1;
2075 /** Reserved / Ignored (global bit). / */
2076 uint32_t u1Reserved1 : 1;
2077 /** Available for use to system software. */
2078 uint32_t u3Available : 3;
2079 /** Physical Page number of the next level - Low Part. Don't use! */
2080 uint32_t u20PageNoLow : 20;
2081 /** Physical Page number of the next level - High Part. Don't use! */
2082 uint32_t u20PageNoHigh : 20;
2083 /** MBZ bits */
2084 uint32_t u11Reserved : 11;
2085 /** No Execute flag. */
2086 uint32_t u1NoExecute : 1;
2087} X86PDEPAEBITS;
2088#ifndef VBOX_FOR_DTRACE_LIB
2089AssertCompileSize(X86PDEPAEBITS, 8);
2090#endif
2091/** Pointer to a page directory entry. */
2092typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2093/** Pointer to a const page directory entry. */
2094typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2095
2096/** @} */
2097
2098
2099/** @name 2/4MB Page Directory Entry
2100 * @{
2101 */
2102/** Bit 0 - P - Present bit. */
2103#define X86_PDE4M_P RT_BIT_32(0)
2104/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2105#define X86_PDE4M_RW RT_BIT_32(1)
2106/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2107#define X86_PDE4M_US RT_BIT_32(2)
2108/** Bit 3 - PWT - Page level write thru bit. */
2109#define X86_PDE4M_PWT RT_BIT_32(3)
2110/** Bit 4 - PCD - Page level cache disable bit. */
2111#define X86_PDE4M_PCD RT_BIT_32(4)
2112/** Bit 5 - A - Access bit. */
2113#define X86_PDE4M_A RT_BIT_32(5)
2114/** Bit 6 - D - Dirty bit. */
2115#define X86_PDE4M_D RT_BIT_32(6)
2116/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2117#define X86_PDE4M_PS RT_BIT_32(7)
2118/** Bit 8 - G - Global flag. */
2119#define X86_PDE4M_G RT_BIT_32(8)
2120/** Bits 9-11 - AVL - Available for use to system software. */
2121#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2122/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2123#define X86_PDE4M_PAT RT_BIT_32(12)
2124/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2125#define X86_PDE4M_PAT_SHIFT (12 - 7)
2126/** Bits 22-31 - - Physical Page number. */
2127#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2128/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2129#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2130/** The number of bits to the high part of the page number. */
2131#define X86_PDE4M_PG_HIGH_SHIFT 19
2132/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2133#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2134
2135/** Bits 21-51 - - PAE/LM - Physical Page number.
2136 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2137#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2138/** Bits 63 - NX - PAE/LM - No execution flag. */
2139#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2140/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2141#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2142/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2143#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2144/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2145#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2146/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2147#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2148
2149/**
2150 * 4MB page directory entry.
2151 */
2152typedef struct X86PDE4MBITS
2153{
2154 /** Flags whether(=1) or not the page is present. */
2155 uint32_t u1Present : 1;
2156 /** Read(=0) / Write(=1) flag. */
2157 uint32_t u1Write : 1;
2158 /** User(=1) / Supervisor (=0) flag. */
2159 uint32_t u1User : 1;
2160 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2161 uint32_t u1WriteThru : 1;
2162 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2163 uint32_t u1CacheDisable : 1;
2164 /** Accessed flag.
2165 * Indicates that the page have been read or written to. */
2166 uint32_t u1Accessed : 1;
2167 /** Dirty flag.
2168 * Indicates that the page has been written to. */
2169 uint32_t u1Dirty : 1;
2170 /** Page size flag - always 1 for 4MB entries. */
2171 uint32_t u1Size : 1;
2172 /** Global flag. */
2173 uint32_t u1Global : 1;
2174 /** Available for use to system software. */
2175 uint32_t u3Available : 3;
2176 /** Reserved / If PAT enabled, bit 2 of the index. */
2177 uint32_t u1PAT : 1;
2178 /** Bits 32-39 of the page number on AMD64.
2179 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2180 uint32_t u8PageNoHigh : 8;
2181 /** Reserved. */
2182 uint32_t u1Reserved : 1;
2183 /** Physical Page number of the page. */
2184 uint32_t u10PageNo : 10;
2185} X86PDE4MBITS;
2186#ifndef VBOX_FOR_DTRACE_LIB
2187AssertCompileSize(X86PDE4MBITS, 4);
2188#endif
2189/** Pointer to a page table entry. */
2190typedef X86PDE4MBITS *PX86PDE4MBITS;
2191/** Pointer to a const page table entry. */
2192typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2193
2194
2195/**
2196 * 2MB PAE page directory entry.
2197 */
2198typedef struct X86PDE2MPAEBITS
2199{
2200 /** Flags whether(=1) or not the page is present. */
2201 uint32_t u1Present : 1;
2202 /** Read(=0) / Write(=1) flag. */
2203 uint32_t u1Write : 1;
2204 /** User(=1) / Supervisor(=0) flag. */
2205 uint32_t u1User : 1;
2206 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2207 uint32_t u1WriteThru : 1;
2208 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2209 uint32_t u1CacheDisable : 1;
2210 /** Accessed flag.
2211 * Indicates that the page have been read or written to. */
2212 uint32_t u1Accessed : 1;
2213 /** Dirty flag.
2214 * Indicates that the page has been written to. */
2215 uint32_t u1Dirty : 1;
2216 /** Page size flag - always 1 for 2MB entries. */
2217 uint32_t u1Size : 1;
2218 /** Global flag. */
2219 uint32_t u1Global : 1;
2220 /** Available for use to system software. */
2221 uint32_t u3Available : 3;
2222 /** Reserved / If PAT enabled, bit 2 of the index. */
2223 uint32_t u1PAT : 1;
2224 /** Reserved. */
2225 uint32_t u9Reserved : 9;
2226 /** Physical Page number of the next level - Low part. Don't use! */
2227 uint32_t u10PageNoLow : 10;
2228 /** Physical Page number of the next level - High part. Don't use! */
2229 uint32_t u20PageNoHigh : 20;
2230 /** MBZ bits */
2231 uint32_t u11Reserved : 11;
2232 /** No Execute flag. */
2233 uint32_t u1NoExecute : 1;
2234} X86PDE2MPAEBITS;
2235#ifndef VBOX_FOR_DTRACE_LIB
2236AssertCompileSize(X86PDE2MPAEBITS, 8);
2237#endif
2238/** Pointer to a 2MB PAE page table entry. */
2239typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2240/** Pointer to a 2MB PAE page table entry. */
2241typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2242
2243/** @} */
2244
2245/**
2246 * Page directory entry.
2247 */
2248typedef union X86PDE
2249{
2250 /** Unsigned integer view. */
2251 X86PGUINT u;
2252 /** Normal view. */
2253 X86PDEBITS n;
2254 /** 4MB view (big). */
2255 X86PDE4MBITS b;
2256 /** 8 bit unsigned integer view. */
2257 uint8_t au8[4];
2258 /** 16 bit unsigned integer view. */
2259 uint16_t au16[2];
2260 /** 32 bit unsigned integer view. */
2261 uint32_t au32[1];
2262} X86PDE;
2263#ifndef VBOX_FOR_DTRACE_LIB
2264AssertCompileSize(X86PDE, 4);
2265#endif
2266/** Pointer to a page directory entry. */
2267typedef X86PDE *PX86PDE;
2268/** Pointer to a const page directory entry. */
2269typedef const X86PDE *PCX86PDE;
2270
2271/**
2272 * PAE page directory entry.
2273 */
2274typedef union X86PDEPAE
2275{
2276 /** Unsigned integer view. */
2277 X86PGPAEUINT u;
2278 /** Normal view. */
2279 X86PDEPAEBITS n;
2280 /** 2MB page view (big). */
2281 X86PDE2MPAEBITS b;
2282 /** 8 bit unsigned integer view. */
2283 uint8_t au8[8];
2284 /** 16 bit unsigned integer view. */
2285 uint16_t au16[4];
2286 /** 32 bit unsigned integer view. */
2287 uint32_t au32[2];
2288} X86PDEPAE;
2289#ifndef VBOX_FOR_DTRACE_LIB
2290AssertCompileSize(X86PDEPAE, 8);
2291#endif
2292/** Pointer to a page directory entry. */
2293typedef X86PDEPAE *PX86PDEPAE;
2294/** Pointer to a const page directory entry. */
2295typedef const X86PDEPAE *PCX86PDEPAE;
2296
2297/**
2298 * Page directory.
2299 */
2300typedef struct X86PD
2301{
2302 /** PDE Array. */
2303 X86PDE a[X86_PG_ENTRIES];
2304} X86PD;
2305#ifndef VBOX_FOR_DTRACE_LIB
2306AssertCompileSize(X86PD, 4096);
2307#endif
2308/** Pointer to a page directory. */
2309typedef X86PD *PX86PD;
2310/** Pointer to a const page directory. */
2311typedef const X86PD *PCX86PD;
2312
2313/** The page shift to get the PD index. */
2314#define X86_PD_SHIFT 22
2315/** The PD index mask (apply to a shifted page address). */
2316#define X86_PD_MASK 0x3ff
2317
2318
2319/**
2320 * PAE page directory.
2321 */
2322typedef struct X86PDPAE
2323{
2324 /** PDE Array. */
2325 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2326} X86PDPAE;
2327#ifndef VBOX_FOR_DTRACE_LIB
2328AssertCompileSize(X86PDPAE, 4096);
2329#endif
2330/** Pointer to a PAE page directory. */
2331typedef X86PDPAE *PX86PDPAE;
2332/** Pointer to a const PAE page directory. */
2333typedef const X86PDPAE *PCX86PDPAE;
2334
2335/** The page shift to get the PAE PD index. */
2336#define X86_PD_PAE_SHIFT 21
2337/** The PAE PD index mask (apply to a shifted page address). */
2338#define X86_PD_PAE_MASK 0x1ff
2339
2340
2341/** @name Page Directory Pointer Table Entry (PAE)
2342 * @{
2343 */
2344/** Bit 0 - P - Present bit. */
2345#define X86_PDPE_P RT_BIT_32(0)
2346/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2347#define X86_PDPE_RW RT_BIT_32(1)
2348/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2349#define X86_PDPE_US RT_BIT_32(2)
2350/** Bit 3 - PWT - Page level write thru bit. */
2351#define X86_PDPE_PWT RT_BIT_32(3)
2352/** Bit 4 - PCD - Page level cache disable bit. */
2353#define X86_PDPE_PCD RT_BIT_32(4)
2354/** Bit 5 - A - Access bit. Long Mode only. */
2355#define X86_PDPE_A RT_BIT_32(5)
2356/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2357#define X86_PDPE_LM_PS RT_BIT_32(7)
2358/** Bits 9-11 - - Available for use to system software. */
2359#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2360/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2361#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2362/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2363#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2364/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2365#define X86_PDPE_LM_NX RT_BIT_64(63)
2366/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2367#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2368/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2369#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2370/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2371#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2372/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2373#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2374
2375
2376/**
2377 * Page directory pointer table entry.
2378 */
2379typedef struct X86PDPEBITS
2380{
2381 /** Flags whether(=1) or not the page is present. */
2382 uint32_t u1Present : 1;
2383 /** Chunk of reserved bits. */
2384 uint32_t u2Reserved : 2;
2385 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2386 uint32_t u1WriteThru : 1;
2387 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2388 uint32_t u1CacheDisable : 1;
2389 /** Chunk of reserved bits. */
2390 uint32_t u4Reserved : 4;
2391 /** Available for use to system software. */
2392 uint32_t u3Available : 3;
2393 /** Physical Page number of the next level - Low Part. Don't use! */
2394 uint32_t u20PageNoLow : 20;
2395 /** Physical Page number of the next level - High Part. Don't use! */
2396 uint32_t u20PageNoHigh : 20;
2397 /** MBZ bits */
2398 uint32_t u12Reserved : 12;
2399} X86PDPEBITS;
2400#ifndef VBOX_FOR_DTRACE_LIB
2401AssertCompileSize(X86PDPEBITS, 8);
2402#endif
2403/** Pointer to a page directory pointer table entry. */
2404typedef X86PDPEBITS *PX86PTPEBITS;
2405/** Pointer to a const page directory pointer table entry. */
2406typedef const X86PDPEBITS *PCX86PTPEBITS;
2407
2408/**
2409 * Page directory pointer table entry. AMD64 version
2410 */
2411typedef struct X86PDPEAMD64BITS
2412{
2413 /** Flags whether(=1) or not the page is present. */
2414 uint32_t u1Present : 1;
2415 /** Read(=0) / Write(=1) flag. */
2416 uint32_t u1Write : 1;
2417 /** User(=1) / Supervisor (=0) flag. */
2418 uint32_t u1User : 1;
2419 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2420 uint32_t u1WriteThru : 1;
2421 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2422 uint32_t u1CacheDisable : 1;
2423 /** Accessed flag.
2424 * Indicates that the page have been read or written to. */
2425 uint32_t u1Accessed : 1;
2426 /** Chunk of reserved bits. */
2427 uint32_t u3Reserved : 3;
2428 /** Available for use to system software. */
2429 uint32_t u3Available : 3;
2430 /** Physical Page number of the next level - Low Part. Don't use! */
2431 uint32_t u20PageNoLow : 20;
2432 /** Physical Page number of the next level - High Part. Don't use! */
2433 uint32_t u20PageNoHigh : 20;
2434 /** MBZ bits */
2435 uint32_t u11Reserved : 11;
2436 /** No Execute flag. */
2437 uint32_t u1NoExecute : 1;
2438} X86PDPEAMD64BITS;
2439#ifndef VBOX_FOR_DTRACE_LIB
2440AssertCompileSize(X86PDPEAMD64BITS, 8);
2441#endif
2442/** Pointer to a page directory pointer table entry. */
2443typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2444/** Pointer to a const page directory pointer table entry. */
2445typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2446
2447/**
2448 * Page directory pointer table entry for 1GB page. (AMD64 only)
2449 */
2450typedef struct X86PDPE1GB
2451{
2452 /** 0: Flags whether(=1) or not the page is present. */
2453 uint32_t u1Present : 1;
2454 /** 1: Read(=0) / Write(=1) flag. */
2455 uint32_t u1Write : 1;
2456 /** 2: User(=1) / Supervisor (=0) flag. */
2457 uint32_t u1User : 1;
2458 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2459 uint32_t u1WriteThru : 1;
2460 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2461 uint32_t u1CacheDisable : 1;
2462 /** 5: Accessed flag.
2463 * Indicates that the page have been read or written to. */
2464 uint32_t u1Accessed : 1;
2465 /** 6: Dirty flag for 1GB pages. */
2466 uint32_t u1Dirty : 1;
2467 /** 7: Indicates 1GB page if set. */
2468 uint32_t u1Size : 1;
2469 /** 8: Global 1GB page. */
2470 uint32_t u1Global: 1;
2471 /** 9-11: Available for use to system software. */
2472 uint32_t u3Available : 3;
2473 /** 12: PAT bit for 1GB page. */
2474 uint32_t u1PAT : 1;
2475 /** 13-29: MBZ bits. */
2476 uint32_t u17Reserved : 17;
2477 /** 30-31: Physical page number - Low Part. Don't use! */
2478 uint32_t u2PageNoLow : 2;
2479 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2480 uint32_t u20PageNoHigh : 20;
2481 /** 52-62: MBZ bits */
2482 uint32_t u11Reserved : 11;
2483 /** 63: No Execute flag. */
2484 uint32_t u1NoExecute : 1;
2485} X86PDPE1GB;
2486#ifndef VBOX_FOR_DTRACE_LIB
2487AssertCompileSize(X86PDPE1GB, 8);
2488#endif
2489/** Pointer to a page directory pointer table entry for a 1GB page. */
2490typedef X86PDPE1GB *PX86PDPE1GB;
2491/** Pointer to a const page directory pointer table entry for a 1GB page. */
2492typedef const X86PDPE1GB *PCX86PDPE1GB;
2493
2494/**
2495 * Page directory pointer table entry.
2496 */
2497typedef union X86PDPE
2498{
2499 /** Unsigned integer view. */
2500 X86PGPAEUINT u;
2501 /** Normal view. */
2502 X86PDPEBITS n;
2503 /** AMD64 view. */
2504 X86PDPEAMD64BITS lm;
2505 /** AMD64 big view. */
2506 X86PDPE1GB b;
2507 /** 8 bit unsigned integer view. */
2508 uint8_t au8[8];
2509 /** 16 bit unsigned integer view. */
2510 uint16_t au16[4];
2511 /** 32 bit unsigned integer view. */
2512 uint32_t au32[2];
2513} X86PDPE;
2514#ifndef VBOX_FOR_DTRACE_LIB
2515AssertCompileSize(X86PDPE, 8);
2516#endif
2517/** Pointer to a page directory pointer table entry. */
2518typedef X86PDPE *PX86PDPE;
2519/** Pointer to a const page directory pointer table entry. */
2520typedef const X86PDPE *PCX86PDPE;
2521
2522
2523/**
2524 * Page directory pointer table.
2525 */
2526typedef struct X86PDPT
2527{
2528 /** PDE Array. */
2529 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2530} X86PDPT;
2531#ifndef VBOX_FOR_DTRACE_LIB
2532AssertCompileSize(X86PDPT, 4096);
2533#endif
2534/** Pointer to a page directory pointer table. */
2535typedef X86PDPT *PX86PDPT;
2536/** Pointer to a const page directory pointer table. */
2537typedef const X86PDPT *PCX86PDPT;
2538
2539/** The page shift to get the PDPT index. */
2540#define X86_PDPT_SHIFT 30
2541/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2542#define X86_PDPT_MASK_PAE 0x3
2543/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2544#define X86_PDPT_MASK_AMD64 0x1ff
2545
2546/** @} */
2547
2548
2549/** @name Page Map Level-4 Entry (Long Mode PAE)
2550 * @{
2551 */
2552/** Bit 0 - P - Present bit. */
2553#define X86_PML4E_P RT_BIT_32(0)
2554/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2555#define X86_PML4E_RW RT_BIT_32(1)
2556/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2557#define X86_PML4E_US RT_BIT_32(2)
2558/** Bit 3 - PWT - Page level write thru bit. */
2559#define X86_PML4E_PWT RT_BIT_32(3)
2560/** Bit 4 - PCD - Page level cache disable bit. */
2561#define X86_PML4E_PCD RT_BIT_32(4)
2562/** Bit 5 - A - Access bit. */
2563#define X86_PML4E_A RT_BIT_32(5)
2564/** Bits 9-11 - - Available for use to system software. */
2565#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2566/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2567#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2568/** Bits 8, 7 - - MBZ bits when NX is active. */
2569#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2570/** Bits 63, 7 - - MBZ bits when no NX. */
2571#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2572/** Bits 63 - NX - PAE - No execution flag. */
2573#define X86_PML4E_NX RT_BIT_64(63)
2574
2575/**
2576 * Page Map Level-4 Entry
2577 */
2578typedef struct X86PML4EBITS
2579{
2580 /** Flags whether(=1) or not the page is present. */
2581 uint32_t u1Present : 1;
2582 /** Read(=0) / Write(=1) flag. */
2583 uint32_t u1Write : 1;
2584 /** User(=1) / Supervisor (=0) flag. */
2585 uint32_t u1User : 1;
2586 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2587 uint32_t u1WriteThru : 1;
2588 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2589 uint32_t u1CacheDisable : 1;
2590 /** Accessed flag.
2591 * Indicates that the page have been read or written to. */
2592 uint32_t u1Accessed : 1;
2593 /** Chunk of reserved bits. */
2594 uint32_t u3Reserved : 3;
2595 /** Available for use to system software. */
2596 uint32_t u3Available : 3;
2597 /** Physical Page number of the next level - Low Part. Don't use! */
2598 uint32_t u20PageNoLow : 20;
2599 /** Physical Page number of the next level - High Part. Don't use! */
2600 uint32_t u20PageNoHigh : 20;
2601 /** MBZ bits */
2602 uint32_t u11Reserved : 11;
2603 /** No Execute flag. */
2604 uint32_t u1NoExecute : 1;
2605} X86PML4EBITS;
2606#ifndef VBOX_FOR_DTRACE_LIB
2607AssertCompileSize(X86PML4EBITS, 8);
2608#endif
2609/** Pointer to a page map level-4 entry. */
2610typedef X86PML4EBITS *PX86PML4EBITS;
2611/** Pointer to a const page map level-4 entry. */
2612typedef const X86PML4EBITS *PCX86PML4EBITS;
2613
2614/**
2615 * Page Map Level-4 Entry.
2616 */
2617typedef union X86PML4E
2618{
2619 /** Unsigned integer view. */
2620 X86PGPAEUINT u;
2621 /** Normal view. */
2622 X86PML4EBITS n;
2623 /** 8 bit unsigned integer view. */
2624 uint8_t au8[8];
2625 /** 16 bit unsigned integer view. */
2626 uint16_t au16[4];
2627 /** 32 bit unsigned integer view. */
2628 uint32_t au32[2];
2629} X86PML4E;
2630#ifndef VBOX_FOR_DTRACE_LIB
2631AssertCompileSize(X86PML4E, 8);
2632#endif
2633/** Pointer to a page map level-4 entry. */
2634typedef X86PML4E *PX86PML4E;
2635/** Pointer to a const page map level-4 entry. */
2636typedef const X86PML4E *PCX86PML4E;
2637
2638
2639/**
2640 * Page Map Level-4.
2641 */
2642typedef struct X86PML4
2643{
2644 /** PDE Array. */
2645 X86PML4E a[X86_PG_PAE_ENTRIES];
2646} X86PML4;
2647#ifndef VBOX_FOR_DTRACE_LIB
2648AssertCompileSize(X86PML4, 4096);
2649#endif
2650/** Pointer to a page map level-4. */
2651typedef X86PML4 *PX86PML4;
2652/** Pointer to a const page map level-4. */
2653typedef const X86PML4 *PCX86PML4;
2654
2655/** The page shift to get the PML4 index. */
2656#define X86_PML4_SHIFT 39
2657/** The PML4 index mask (apply to a shifted page address). */
2658#define X86_PML4_MASK 0x1ff
2659
2660/** @} */
2661
2662/** @} */
2663
2664/**
2665 * Intel PCID invalidation types.
2666 */
2667/** Individual address invalidation. */
2668#define X86_INVPCID_TYPE_INDV_ADDR 0
2669/** Single-context invalidation. */
2670#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2671/** All-context including globals invalidation. */
2672#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2673/** All-context excluding globals invalidation. */
2674#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2675/** The maximum valid invalidation type value. */
2676#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2677
2678/**
2679 * 32-bit protected mode FSTENV image.
2680 */
2681typedef struct X86FSTENV32P
2682{
2683 uint16_t FCW;
2684 uint16_t padding1;
2685 uint16_t FSW;
2686 uint16_t padding2;
2687 uint16_t FTW;
2688 uint16_t padding3;
2689 uint32_t FPUIP;
2690 uint16_t FPUCS;
2691 uint16_t FOP;
2692 uint32_t FPUDP;
2693 uint16_t FPUDS;
2694 uint16_t padding4;
2695} X86FSTENV32P;
2696/** Pointer to a 32-bit protected mode FSTENV image. */
2697typedef X86FSTENV32P *PX86FSTENV32P;
2698/** Pointer to a const 32-bit protected mode FSTENV image. */
2699typedef X86FSTENV32P const *PCX86FSTENV32P;
2700
2701
2702/**
2703 * 80-bit MMX/FPU register type.
2704 */
2705typedef struct X86FPUMMX
2706{
2707 uint8_t reg[10];
2708} X86FPUMMX;
2709#ifndef VBOX_FOR_DTRACE_LIB
2710AssertCompileSize(X86FPUMMX, 10);
2711#endif
2712/** Pointer to a 80-bit MMX/FPU register type. */
2713typedef X86FPUMMX *PX86FPUMMX;
2714/** Pointer to a const 80-bit MMX/FPU register type. */
2715typedef const X86FPUMMX *PCX86FPUMMX;
2716
2717/** FPU (x87) register. */
2718typedef union X86FPUREG
2719{
2720 /** MMX view. */
2721 uint64_t mmx;
2722 /** FPU view - todo. */
2723 X86FPUMMX fpu;
2724 /** Extended precision floating point view. */
2725 RTFLOAT80U r80;
2726 /** Extended precision floating point view v2 */
2727 RTFLOAT80U2 r80Ex;
2728 /** 8-bit view. */
2729 uint8_t au8[16];
2730 /** 16-bit view. */
2731 uint16_t au16[8];
2732 /** 32-bit view. */
2733 uint32_t au32[4];
2734 /** 64-bit view. */
2735 uint64_t au64[2];
2736 /** 128-bit view. (yeah, very helpful) */
2737 uint128_t au128[1];
2738} X86FPUREG;
2739#ifndef VBOX_FOR_DTRACE_LIB
2740AssertCompileSize(X86FPUREG, 16);
2741#endif
2742/** Pointer to a FPU register. */
2743typedef X86FPUREG *PX86FPUREG;
2744/** Pointer to a const FPU register. */
2745typedef X86FPUREG const *PCX86FPUREG;
2746
2747/**
2748 * XMM register union.
2749 */
2750typedef union X86XMMREG
2751{
2752 /** XMM Register view. */
2753 uint128_t xmm;
2754 /** 8-bit view. */
2755 uint8_t au8[16];
2756 /** 16-bit view. */
2757 uint16_t au16[8];
2758 /** 32-bit view. */
2759 uint32_t au32[4];
2760 /** 64-bit view. */
2761 uint64_t au64[2];
2762 /** 128-bit view. (yeah, very helpful) */
2763 uint128_t au128[1];
2764 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2765 RTUINT128U uXmm;
2766} X86XMMREG;
2767#ifndef VBOX_FOR_DTRACE_LIB
2768AssertCompileSize(X86XMMREG, 16);
2769#endif
2770/** Pointer to an XMM register state. */
2771typedef X86XMMREG *PX86XMMREG;
2772/** Pointer to a const XMM register state. */
2773typedef X86XMMREG const *PCX86XMMREG;
2774
2775/**
2776 * YMM register union.
2777 */
2778typedef union X86YMMREG
2779{
2780 /** 8-bit view. */
2781 uint8_t au8[32];
2782 /** 16-bit view. */
2783 uint16_t au16[16];
2784 /** 32-bit view. */
2785 uint32_t au32[8];
2786 /** 64-bit view. */
2787 uint64_t au64[4];
2788 /** 128-bit view. (yeah, very helpful) */
2789 uint128_t au128[2];
2790 /** XMM sub register view. */
2791 X86XMMREG aXmm[2];
2792} X86YMMREG;
2793#ifndef VBOX_FOR_DTRACE_LIB
2794AssertCompileSize(X86YMMREG, 32);
2795#endif
2796/** Pointer to an YMM register state. */
2797typedef X86YMMREG *PX86YMMREG;
2798/** Pointer to a const YMM register state. */
2799typedef X86YMMREG const *PCX86YMMREG;
2800
2801/**
2802 * ZMM register union.
2803 */
2804typedef union X86ZMMREG
2805{
2806 /** 8-bit view. */
2807 uint8_t au8[64];
2808 /** 16-bit view. */
2809 uint16_t au16[32];
2810 /** 32-bit view. */
2811 uint32_t au32[16];
2812 /** 64-bit view. */
2813 uint64_t au64[8];
2814 /** 128-bit view. (yeah, very helpful) */
2815 uint128_t au128[4];
2816 /** XMM sub register view. */
2817 X86XMMREG aXmm[4];
2818 /** YMM sub register view. */
2819 X86YMMREG aYmm[2];
2820} X86ZMMREG;
2821#ifndef VBOX_FOR_DTRACE_LIB
2822AssertCompileSize(X86ZMMREG, 64);
2823#endif
2824/** Pointer to an ZMM register state. */
2825typedef X86ZMMREG *PX86ZMMREG;
2826/** Pointer to a const ZMM register state. */
2827typedef X86ZMMREG const *PCX86ZMMREG;
2828
2829
2830/**
2831 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
2832 * @todo verify this...
2833 */
2834#pragma pack(1)
2835typedef struct X86FPUSTATE
2836{
2837 /** 0x00 - Control word. */
2838 uint16_t FCW;
2839 /** 0x02 - Alignment word */
2840 uint16_t Dummy1;
2841 /** 0x04 - Status word. */
2842 uint16_t FSW;
2843 /** 0x06 - Alignment word */
2844 uint16_t Dummy2;
2845 /** 0x08 - Tag word */
2846 uint16_t FTW;
2847 /** 0x0a - Alignment word */
2848 uint16_t Dummy3;
2849
2850 /** 0x0c - Instruction pointer. */
2851 uint32_t FPUIP;
2852 /** 0x10 - Code selector. */
2853 uint16_t CS;
2854 /** 0x12 - Opcode. */
2855 uint16_t FOP;
2856 /** 0x14 - FOO. */
2857 uint32_t FPUOO;
2858 /** 0x18 - FOS. */
2859 uint32_t FPUOS;
2860 /** 0x1c - FPU register. */
2861 X86FPUREG regs[8];
2862} X86FPUSTATE;
2863#pragma pack()
2864/** Pointer to a FPU state. */
2865typedef X86FPUSTATE *PX86FPUSTATE;
2866/** Pointer to a const FPU state. */
2867typedef const X86FPUSTATE *PCX86FPUSTATE;
2868
2869/**
2870 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
2871 */
2872#pragma pack(1)
2873typedef struct X86FXSTATE
2874{
2875 /** 0x00 - Control word. */
2876 uint16_t FCW;
2877 /** 0x02 - Status word. */
2878 uint16_t FSW;
2879 /** 0x04 - Tag word. (The upper byte is always zero.) */
2880 uint16_t FTW;
2881 /** 0x06 - Opcode. */
2882 uint16_t FOP;
2883 /** 0x08 - Instruction pointer. */
2884 uint32_t FPUIP;
2885 /** 0x0c - Code selector. */
2886 uint16_t CS;
2887 uint16_t Rsrvd1;
2888 /** 0x10 - Data pointer. */
2889 uint32_t FPUDP;
2890 /** 0x14 - Data segment */
2891 uint16_t DS;
2892 /** 0x16 */
2893 uint16_t Rsrvd2;
2894 /** 0x18 */
2895 uint32_t MXCSR;
2896 /** 0x1c */
2897 uint32_t MXCSR_MASK;
2898 /** 0x20 - FPU registers. */
2899 X86FPUREG aRegs[8];
2900 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
2901 X86XMMREG aXMM[16];
2902 /* - offset 416 - */
2903 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
2904 /* - offset 464 - Software usable reserved bits. */
2905 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
2906} X86FXSTATE;
2907#pragma pack()
2908/** Pointer to a FPU Extended state. */
2909typedef X86FXSTATE *PX86FXSTATE;
2910/** Pointer to a const FPU Extended state. */
2911typedef const X86FXSTATE *PCX86FXSTATE;
2912
2913/** Offset for software usable reserved bits (464:511) where we store a 32-bit
2914 * magic. Don't forget to update x86.mac if you change this! */
2915#define X86_OFF_FXSTATE_RSVD 0x1d0
2916/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
2917 * forget to update x86.mac if you change this!
2918 * @todo r=bird: This has nothing what-so-ever to do here.... */
2919#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
2920#ifndef VBOX_FOR_DTRACE_LIB
2921AssertCompileSize(X86FXSTATE, 512);
2922AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
2923#endif
2924
2925/** @name FPU status word flags.
2926 * @{ */
2927/** Exception Flag: Invalid operation. */
2928#define X86_FSW_IE RT_BIT_32(0)
2929/** Exception Flag: Denormalized operand. */
2930#define X86_FSW_DE RT_BIT_32(1)
2931/** Exception Flag: Zero divide. */
2932#define X86_FSW_ZE RT_BIT_32(2)
2933/** Exception Flag: Overflow. */
2934#define X86_FSW_OE RT_BIT_32(3)
2935/** Exception Flag: Underflow. */
2936#define X86_FSW_UE RT_BIT_32(4)
2937/** Exception Flag: Precision. */
2938#define X86_FSW_PE RT_BIT_32(5)
2939/** Stack fault. */
2940#define X86_FSW_SF RT_BIT_32(6)
2941/** Error summary status. */
2942#define X86_FSW_ES RT_BIT_32(7)
2943/** Mask of exceptions flags, excluding the summary bit. */
2944#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
2945/** Mask of exceptions flags, including the summary bit. */
2946#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
2947/** Condition code 0. */
2948#define X86_FSW_C0 RT_BIT_32(8)
2949/** Condition code 1. */
2950#define X86_FSW_C1 RT_BIT_32(9)
2951/** Condition code 2. */
2952#define X86_FSW_C2 RT_BIT_32(10)
2953/** Top of the stack mask. */
2954#define X86_FSW_TOP_MASK UINT16_C(0x3800)
2955/** TOP shift value. */
2956#define X86_FSW_TOP_SHIFT 11
2957/** Mask for getting TOP value after shifting it right. */
2958#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
2959/** Get the TOP value. */
2960#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
2961/** Condition code 3. */
2962#define X86_FSW_C3 RT_BIT_32(14)
2963/** Mask of exceptions flags, including the summary bit. */
2964#define X86_FSW_C_MASK UINT16_C(0x4700)
2965/** FPU busy. */
2966#define X86_FSW_B RT_BIT_32(15)
2967/** @} */
2968
2969
2970/** @name FPU control word flags.
2971 * @{ */
2972/** Exception Mask: Invalid operation. */
2973#define X86_FCW_IM RT_BIT_32(0)
2974/** Exception Mask: Denormalized operand. */
2975#define X86_FCW_DM RT_BIT_32(1)
2976/** Exception Mask: Zero divide. */
2977#define X86_FCW_ZM RT_BIT_32(2)
2978/** Exception Mask: Overflow. */
2979#define X86_FCW_OM RT_BIT_32(3)
2980/** Exception Mask: Underflow. */
2981#define X86_FCW_UM RT_BIT_32(4)
2982/** Exception Mask: Precision. */
2983#define X86_FCW_PM RT_BIT_32(5)
2984/** Mask all exceptions, the value typically loaded (by for instance fninit).
2985 * @remarks This includes reserved bit 6. */
2986#define X86_FCW_MASK_ALL UINT16_C(0x007f)
2987/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
2988#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
2989/** Precision control mask. */
2990#define X86_FCW_PC_MASK UINT16_C(0x0300)
2991/** Precision control: 24-bit. */
2992#define X86_FCW_PC_24 UINT16_C(0x0000)
2993/** Precision control: Reserved. */
2994#define X86_FCW_PC_RSVD UINT16_C(0x0100)
2995/** Precision control: 53-bit. */
2996#define X86_FCW_PC_53 UINT16_C(0x0200)
2997/** Precision control: 64-bit. */
2998#define X86_FCW_PC_64 UINT16_C(0x0300)
2999/** Rounding control mask. */
3000#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3001/** Rounding control: To nearest. */
3002#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3003/** Rounding control: Down. */
3004#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3005/** Rounding control: Up. */
3006#define X86_FCW_RC_UP UINT16_C(0x0800)
3007/** Rounding control: Towards zero. */
3008#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3009/** Bits which should be zero, apparently. */
3010#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3011/** @} */
3012
3013/** @name SSE MXCSR
3014 * @{ */
3015/** Exception Flag: Invalid operation. */
3016#define X86_MXCSR_IE RT_BIT_32(0)
3017/** Exception Flag: Denormalized operand. */
3018#define X86_MXCSR_DE RT_BIT_32(1)
3019/** Exception Flag: Zero divide. */
3020#define X86_MXCSR_ZE RT_BIT_32(2)
3021/** Exception Flag: Overflow. */
3022#define X86_MXCSR_OE RT_BIT_32(3)
3023/** Exception Flag: Underflow. */
3024#define X86_MXCSR_UE RT_BIT_32(4)
3025/** Exception Flag: Precision. */
3026#define X86_MXCSR_PE RT_BIT_32(5)
3027
3028/** Denormals are zero. */
3029#define X86_MXCSR_DAZ RT_BIT_32(6)
3030
3031/** Exception Mask: Invalid operation. */
3032#define X86_MXCSR_IM RT_BIT_32(7)
3033/** Exception Mask: Denormalized operand. */
3034#define X86_MXCSR_DM RT_BIT_32(8)
3035/** Exception Mask: Zero divide. */
3036#define X86_MXCSR_ZM RT_BIT_32(9)
3037/** Exception Mask: Overflow. */
3038#define X86_MXCSR_OM RT_BIT_32(10)
3039/** Exception Mask: Underflow. */
3040#define X86_MXCSR_UM RT_BIT_32(11)
3041/** Exception Mask: Precision. */
3042#define X86_MXCSR_PM RT_BIT_32(12)
3043
3044/** Rounding control mask. */
3045#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3046/** Rounding control: To nearest. */
3047#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3048/** Rounding control: Down. */
3049#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3050/** Rounding control: Up. */
3051#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3052/** Rounding control: Towards zero. */
3053#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3054
3055/** Flush-to-zero for masked underflow. */
3056#define X86_MXCSR_FZ RT_BIT_32(15)
3057
3058/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3059#define X86_MXCSR_MM RT_BIT_32(17)
3060/** @} */
3061
3062/**
3063 * XSAVE header.
3064 */
3065typedef struct X86XSAVEHDR
3066{
3067 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3068 uint64_t bmXState;
3069 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3070 uint64_t bmXComp;
3071 /** Reserved for furture extensions, probably MBZ. */
3072 uint64_t au64Reserved[6];
3073} X86XSAVEHDR;
3074#ifndef VBOX_FOR_DTRACE_LIB
3075AssertCompileSize(X86XSAVEHDR, 64);
3076#endif
3077/** Pointer to an XSAVE header. */
3078typedef X86XSAVEHDR *PX86XSAVEHDR;
3079/** Pointer to a const XSAVE header. */
3080typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3081
3082
3083/**
3084 * The high 128-bit YMM register state (XSAVE_C_YMM).
3085 * (The lower 128-bits being in X86FXSTATE.)
3086 */
3087typedef struct X86XSAVEYMMHI
3088{
3089 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3090 X86XMMREG aYmmHi[16];
3091} X86XSAVEYMMHI;
3092#ifndef VBOX_FOR_DTRACE_LIB
3093AssertCompileSize(X86XSAVEYMMHI, 256);
3094#endif
3095/** Pointer to a high 128-bit YMM register state. */
3096typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3097/** Pointer to a const high 128-bit YMM register state. */
3098typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3099
3100/**
3101 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3102 */
3103typedef struct X86XSAVEBNDREGS
3104{
3105 /** Array of registers (BND0...BND3). */
3106 struct
3107 {
3108 /** Lower bound. */
3109 uint64_t uLowerBound;
3110 /** Upper bound. */
3111 uint64_t uUpperBound;
3112 } aRegs[4];
3113} X86XSAVEBNDREGS;
3114#ifndef VBOX_FOR_DTRACE_LIB
3115AssertCompileSize(X86XSAVEBNDREGS, 64);
3116#endif
3117/** Pointer to a MPX bound register state. */
3118typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3119/** Pointer to a const MPX bound register state. */
3120typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3121
3122/**
3123 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3124 */
3125typedef struct X86XSAVEBNDCFG
3126{
3127 uint64_t fConfig;
3128 uint64_t fStatus;
3129} X86XSAVEBNDCFG;
3130#ifndef VBOX_FOR_DTRACE_LIB
3131AssertCompileSize(X86XSAVEBNDCFG, 16);
3132#endif
3133/** Pointer to a MPX bound config and status register state. */
3134typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3135/** Pointer to a const MPX bound config and status register state. */
3136typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3137
3138/**
3139 * AVX-512 opmask state (XSAVE_C_OPMASK).
3140 */
3141typedef struct X86XSAVEOPMASK
3142{
3143 /** The K0..K7 values. */
3144 uint64_t aKRegs[8];
3145} X86XSAVEOPMASK;
3146#ifndef VBOX_FOR_DTRACE_LIB
3147AssertCompileSize(X86XSAVEOPMASK, 64);
3148#endif
3149/** Pointer to a AVX-512 opmask state. */
3150typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3151/** Pointer to a const AVX-512 opmask state. */
3152typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3153
3154/**
3155 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3156 */
3157typedef struct X86XSAVEZMMHI256
3158{
3159 /** Upper 256-bits of ZMM0-15. */
3160 X86YMMREG aHi256Regs[16];
3161} X86XSAVEZMMHI256;
3162#ifndef VBOX_FOR_DTRACE_LIB
3163AssertCompileSize(X86XSAVEZMMHI256, 512);
3164#endif
3165/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3166typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3167/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3168typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3169
3170/**
3171 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3172 */
3173typedef struct X86XSAVEZMM16HI
3174{
3175 /** ZMM16 thru ZMM31. */
3176 X86ZMMREG aRegs[16];
3177} X86XSAVEZMM16HI;
3178#ifndef VBOX_FOR_DTRACE_LIB
3179AssertCompileSize(X86XSAVEZMM16HI, 1024);
3180#endif
3181/** Pointer to a state comprising ZMM16-32. */
3182typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3183/** Pointer to a const state comprising ZMM16-32. */
3184typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3185
3186/**
3187 * AMD Light weight profiling state (XSAVE_C_LWP).
3188 *
3189 * We probably won't play with this as AMD seems to be dropping from their "zen"
3190 * processor micro architecture.
3191 */
3192typedef struct X86XSAVELWP
3193{
3194 /** Details when needed. */
3195 uint64_t auLater[128/8];
3196} X86XSAVELWP;
3197#ifndef VBOX_FOR_DTRACE_LIB
3198AssertCompileSize(X86XSAVELWP, 128);
3199#endif
3200
3201
3202/**
3203 * x86 FPU/SSE/AVX/XXXX state.
3204 *
3205 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3206 * changes to this structure.
3207 */
3208typedef struct X86XSAVEAREA
3209{
3210 /** The x87 and SSE region (or legacy region if you like). */
3211 X86FXSTATE x87;
3212 /** The XSAVE header. */
3213 X86XSAVEHDR Hdr;
3214 /** Beyond the header, there isn't really a fixed layout, but we can
3215 generally assume the YMM (AVX) register extensions are present and
3216 follows immediately. */
3217 union
3218 {
3219 /** The high 128-bit AVX registers for easy access by IEM.
3220 * @note This ASSUMES they will always be here... */
3221 X86XSAVEYMMHI YmmHi;
3222
3223 /** This is a typical layout on intel CPUs (good for debuggers). */
3224 struct
3225 {
3226 X86XSAVEYMMHI YmmHi;
3227 X86XSAVEBNDREGS BndRegs;
3228 X86XSAVEBNDCFG BndCfg;
3229 uint8_t abFudgeToMatchDocs[0xB0];
3230 X86XSAVEOPMASK Opmask;
3231 X86XSAVEZMMHI256 ZmmHi256;
3232 X86XSAVEZMM16HI Zmm16Hi;
3233 } Intel;
3234
3235 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3236 struct
3237 {
3238 X86XSAVEYMMHI YmmHi;
3239 X86XSAVELWP Lwp;
3240 } AmdBd;
3241
3242 /** To enbling static deployments that have a reasonable chance of working for
3243 * the next 3-6 CPU generations without running short on space, we allocate a
3244 * lot of extra space here, making the structure a round 8KB in size. This
3245 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3246 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3247 uint8_t ab[8192 - 512 - 64];
3248 } u;
3249} X86XSAVEAREA;
3250#ifndef VBOX_FOR_DTRACE_LIB
3251AssertCompileSize(X86XSAVEAREA, 8192);
3252AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3253AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3254AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3255AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3256AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3257AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3258AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3259AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3260#endif
3261/** Pointer to a XSAVE area. */
3262typedef X86XSAVEAREA *PX86XSAVEAREA;
3263/** Pointer to a const XSAVE area. */
3264typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3265
3266
3267/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3268 * @{ */
3269/** Bit 0 - x87 - Legacy FPU state (bit number) */
3270#define XSAVE_C_X87_BIT 0
3271/** Bit 0 - x87 - Legacy FPU state. */
3272#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3273/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3274#define XSAVE_C_SSE_BIT 1
3275/** Bit 1 - SSE - 128-bit SSE state. */
3276#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3277/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3278#define XSAVE_C_YMM_BIT 2
3279/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3280#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3281/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3282#define XSAVE_C_BNDREGS_BIT 3
3283/** Bit 3 - BNDREGS - MPX bound register state. */
3284#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3285/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3286#define XSAVE_C_BNDCSR_BIT 4
3287/** Bit 4 - BNDCSR - MPX bound config and status state. */
3288#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3289/** Bit 5 - Opmask - opmask state (bit number). */
3290#define XSAVE_C_OPMASK_BIT 5
3291/** Bit 5 - Opmask - opmask state. */
3292#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3293/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3294#define XSAVE_C_ZMM_HI256_BIT 6
3295/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3296#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3297/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3298#define XSAVE_C_ZMM_16HI_BIT 7
3299/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3300#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3301/** Bit 9 - PKRU - Protection-key state (bit number). */
3302#define XSAVE_C_PKRU_BIT 9
3303/** Bit 9 - PKRU - Protection-key state. */
3304#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3305/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3306#define XSAVE_C_LWP_BIT 62
3307/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3308#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3309/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3310#define XSAVE_C_X_BIT 63
3311/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3312#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3313/** @} */
3314
3315
3316
3317/** @name Selector Descriptor
3318 * @{
3319 */
3320
3321#ifndef VBOX_FOR_DTRACE_LIB
3322/**
3323 * Descriptor attributes (as seen by VT-x).
3324 */
3325typedef struct X86DESCATTRBITS
3326{
3327 /** 00 - Segment Type. */
3328 unsigned u4Type : 4;
3329 /** 04 - Descriptor Type. System(=0) or code/data selector */
3330 unsigned u1DescType : 1;
3331 /** 05 - Descriptor Privilege level. */
3332 unsigned u2Dpl : 2;
3333 /** 07 - Flags selector present(=1) or not. */
3334 unsigned u1Present : 1;
3335 /** 08 - Segment limit 16-19. */
3336 unsigned u4LimitHigh : 4;
3337 /** 0c - Available for system software. */
3338 unsigned u1Available : 1;
3339 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3340 unsigned u1Long : 1;
3341 /** 0e - This flags meaning depends on the segment type. Try make sense out
3342 * of the intel manual yourself. */
3343 unsigned u1DefBig : 1;
3344 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3345 * clear byte. */
3346 unsigned u1Granularity : 1;
3347 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3348 unsigned u1Unusable : 1;
3349} X86DESCATTRBITS;
3350#endif /* !VBOX_FOR_DTRACE_LIB */
3351
3352/** @name X86DESCATTR masks
3353 * @{ */
3354#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3355#define X86DESCATTR_DT UINT32_C(0x00000010)
3356#define X86DESCATTR_DPL UINT32_C(0x00000060)
3357#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3358#define X86DESCATTR_P UINT32_C(0x00000080)
3359#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3360#define X86DESCATTR_AVL UINT32_C(0x00001000)
3361#define X86DESCATTR_L UINT32_C(0x00002000)
3362#define X86DESCATTR_D UINT32_C(0x00004000)
3363#define X86DESCATTR_G UINT32_C(0x00008000)
3364#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3365/** @} */
3366
3367#pragma pack(1)
3368typedef union X86DESCATTR
3369{
3370 /** Unsigned integer view. */
3371 uint32_t u;
3372#ifndef VBOX_FOR_DTRACE_LIB
3373 /** Normal view. */
3374 X86DESCATTRBITS n;
3375#endif
3376} X86DESCATTR;
3377#pragma pack()
3378/** Pointer to descriptor attributes. */
3379typedef X86DESCATTR *PX86DESCATTR;
3380/** Pointer to const descriptor attributes. */
3381typedef const X86DESCATTR *PCX86DESCATTR;
3382
3383#ifndef VBOX_FOR_DTRACE_LIB
3384
3385/**
3386 * Generic descriptor table entry
3387 */
3388#pragma pack(1)
3389typedef struct X86DESCGENERIC
3390{
3391 /** 00 - Limit - Low word. */
3392 unsigned u16LimitLow : 16;
3393 /** 10 - Base address - low word.
3394 * Don't try set this to 24 because MSC is doing stupid things then. */
3395 unsigned u16BaseLow : 16;
3396 /** 20 - Base address - first 8 bits of high word. */
3397 unsigned u8BaseHigh1 : 8;
3398 /** 28 - Segment Type. */
3399 unsigned u4Type : 4;
3400 /** 2c - Descriptor Type. System(=0) or code/data selector */
3401 unsigned u1DescType : 1;
3402 /** 2d - Descriptor Privilege level. */
3403 unsigned u2Dpl : 2;
3404 /** 2f - Flags selector present(=1) or not. */
3405 unsigned u1Present : 1;
3406 /** 30 - Segment limit 16-19. */
3407 unsigned u4LimitHigh : 4;
3408 /** 34 - Available for system software. */
3409 unsigned u1Available : 1;
3410 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3411 unsigned u1Long : 1;
3412 /** 36 - This flags meaning depends on the segment type. Try make sense out
3413 * of the intel manual yourself. */
3414 unsigned u1DefBig : 1;
3415 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3416 * clear byte. */
3417 unsigned u1Granularity : 1;
3418 /** 38 - Base address - highest 8 bits. */
3419 unsigned u8BaseHigh2 : 8;
3420} X86DESCGENERIC;
3421#pragma pack()
3422/** Pointer to a generic descriptor entry. */
3423typedef X86DESCGENERIC *PX86DESCGENERIC;
3424/** Pointer to a const generic descriptor entry. */
3425typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3426
3427/** @name Bit offsets of X86DESCGENERIC members.
3428 * @{*/
3429#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3430#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3431#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3432#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3433#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3434#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3435#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3436#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3437#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3438#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3439#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3440#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3441#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3442/** @} */
3443
3444
3445/** @name LAR mask
3446 * @{ */
3447#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3448#define X86LAR_F_DT UINT16_C( 0x1000)
3449#define X86LAR_F_DPL UINT16_C( 0x6000)
3450#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3451#define X86LAR_F_P UINT16_C( 0x8000)
3452#define X86LAR_F_AVL UINT32_C(0x00100000)
3453#define X86LAR_F_L UINT32_C(0x00200000)
3454#define X86LAR_F_D UINT32_C(0x00400000)
3455#define X86LAR_F_G UINT32_C(0x00800000)
3456/** @} */
3457
3458
3459/**
3460 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3461 */
3462typedef struct X86DESCGATE
3463{
3464 /** 00 - Target code segment offset - Low word.
3465 * Ignored if task-gate. */
3466 unsigned u16OffsetLow : 16;
3467 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3468 * TSS selector if task-gate. */
3469 unsigned u16Sel : 16;
3470 /** 20 - Number of parameters for a call-gate.
3471 * Ignored if interrupt-, trap- or task-gate. */
3472 unsigned u5ParmCount : 5;
3473 /** 25 - Reserved / ignored. */
3474 unsigned u3Reserved : 3;
3475 /** 28 - Segment Type. */
3476 unsigned u4Type : 4;
3477 /** 2c - Descriptor Type (0 = system). */
3478 unsigned u1DescType : 1;
3479 /** 2d - Descriptor Privilege level. */
3480 unsigned u2Dpl : 2;
3481 /** 2f - Flags selector present(=1) or not. */
3482 unsigned u1Present : 1;
3483 /** 30 - Target code segment offset - High word.
3484 * Ignored if task-gate. */
3485 unsigned u16OffsetHigh : 16;
3486} X86DESCGATE;
3487/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3488typedef X86DESCGATE *PX86DESCGATE;
3489/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3490typedef const X86DESCGATE *PCX86DESCGATE;
3491
3492#endif /* VBOX_FOR_DTRACE_LIB */
3493
3494/**
3495 * Descriptor table entry.
3496 */
3497#pragma pack(1)
3498typedef union X86DESC
3499{
3500#ifndef VBOX_FOR_DTRACE_LIB
3501 /** Generic descriptor view. */
3502 X86DESCGENERIC Gen;
3503 /** Gate descriptor view. */
3504 X86DESCGATE Gate;
3505#endif
3506
3507 /** 8 bit unsigned integer view. */
3508 uint8_t au8[8];
3509 /** 16 bit unsigned integer view. */
3510 uint16_t au16[4];
3511 /** 32 bit unsigned integer view. */
3512 uint32_t au32[2];
3513 /** 64 bit unsigned integer view. */
3514 uint64_t au64[1];
3515 /** Unsigned integer view. */
3516 uint64_t u;
3517} X86DESC;
3518#ifndef VBOX_FOR_DTRACE_LIB
3519AssertCompileSize(X86DESC, 8);
3520#endif
3521#pragma pack()
3522/** Pointer to descriptor table entry. */
3523typedef X86DESC *PX86DESC;
3524/** Pointer to const descriptor table entry. */
3525typedef const X86DESC *PCX86DESC;
3526
3527/** @def X86DESC_BASE
3528 * Return the base address of a descriptor.
3529 */
3530#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3531 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3532 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3533 | ( (a_pDesc)->Gen.u16BaseLow ) )
3534
3535/** @def X86DESC_LIMIT
3536 * Return the limit of a descriptor.
3537 */
3538#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3539 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3540 | ( (a_pDesc)->Gen.u16LimitLow ) )
3541
3542/** @def X86DESC_LIMIT_G
3543 * Return the limit of a descriptor with the granularity bit taken into account.
3544 * @returns Selector limit (uint32_t).
3545 * @param a_pDesc Pointer to the descriptor.
3546 */
3547#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3548 ( (a_pDesc)->Gen.u1Granularity \
3549 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3550 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3551 )
3552
3553/** @def X86DESC_GET_HID_ATTR
3554 * Get the descriptor attributes for the hidden register.
3555 */
3556#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3557 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3558
3559#ifndef VBOX_FOR_DTRACE_LIB
3560
3561/**
3562 * 64 bits generic descriptor table entry
3563 * Note: most of these bits have no meaning in long mode.
3564 */
3565#pragma pack(1)
3566typedef struct X86DESC64GENERIC
3567{
3568 /** Limit - Low word - *IGNORED*. */
3569 uint32_t u16LimitLow : 16;
3570 /** Base address - low word. - *IGNORED*
3571 * Don't try set this to 24 because MSC is doing stupid things then. */
3572 uint32_t u16BaseLow : 16;
3573 /** Base address - first 8 bits of high word. - *IGNORED* */
3574 uint32_t u8BaseHigh1 : 8;
3575 /** Segment Type. */
3576 uint32_t u4Type : 4;
3577 /** Descriptor Type. System(=0) or code/data selector */
3578 uint32_t u1DescType : 1;
3579 /** Descriptor Privilege level. */
3580 uint32_t u2Dpl : 2;
3581 /** Flags selector present(=1) or not. */
3582 uint32_t u1Present : 1;
3583 /** Segment limit 16-19. - *IGNORED* */
3584 uint32_t u4LimitHigh : 4;
3585 /** Available for system software. - *IGNORED* */
3586 uint32_t u1Available : 1;
3587 /** Long mode flag. */
3588 uint32_t u1Long : 1;
3589 /** This flags meaning depends on the segment type. Try make sense out
3590 * of the intel manual yourself. */
3591 uint32_t u1DefBig : 1;
3592 /** Granularity of the limit. If set 4KB granularity is used, if
3593 * clear byte. - *IGNORED* */
3594 uint32_t u1Granularity : 1;
3595 /** Base address - highest 8 bits. - *IGNORED* */
3596 uint32_t u8BaseHigh2 : 8;
3597 /** Base address - bits 63-32. */
3598 uint32_t u32BaseHigh3 : 32;
3599 uint32_t u8Reserved : 8;
3600 uint32_t u5Zeros : 5;
3601 uint32_t u19Reserved : 19;
3602} X86DESC64GENERIC;
3603#pragma pack()
3604/** Pointer to a generic descriptor entry. */
3605typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3606/** Pointer to a const generic descriptor entry. */
3607typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3608
3609/**
3610 * System descriptor table entry (64 bits)
3611 *
3612 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3613 */
3614#pragma pack(1)
3615typedef struct X86DESC64SYSTEM
3616{
3617 /** Limit - Low word. */
3618 uint32_t u16LimitLow : 16;
3619 /** Base address - low word.
3620 * Don't try set this to 24 because MSC is doing stupid things then. */
3621 uint32_t u16BaseLow : 16;
3622 /** Base address - first 8 bits of high word. */
3623 uint32_t u8BaseHigh1 : 8;
3624 /** Segment Type. */
3625 uint32_t u4Type : 4;
3626 /** Descriptor Type. System(=0) or code/data selector */
3627 uint32_t u1DescType : 1;
3628 /** Descriptor Privilege level. */
3629 uint32_t u2Dpl : 2;
3630 /** Flags selector present(=1) or not. */
3631 uint32_t u1Present : 1;
3632 /** Segment limit 16-19. */
3633 uint32_t u4LimitHigh : 4;
3634 /** Available for system software. */
3635 uint32_t u1Available : 1;
3636 /** Reserved - 0. */
3637 uint32_t u1Reserved : 1;
3638 /** This flags meaning depends on the segment type. Try make sense out
3639 * of the intel manual yourself. */
3640 uint32_t u1DefBig : 1;
3641 /** Granularity of the limit. If set 4KB granularity is used, if
3642 * clear byte. */
3643 uint32_t u1Granularity : 1;
3644 /** Base address - bits 31-24. */
3645 uint32_t u8BaseHigh2 : 8;
3646 /** Base address - bits 63-32. */
3647 uint32_t u32BaseHigh3 : 32;
3648 uint32_t u8Reserved : 8;
3649 uint32_t u5Zeros : 5;
3650 uint32_t u19Reserved : 19;
3651} X86DESC64SYSTEM;
3652#pragma pack()
3653/** Pointer to a system descriptor entry. */
3654typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3655/** Pointer to a const system descriptor entry. */
3656typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3657
3658/**
3659 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3660 */
3661typedef struct X86DESC64GATE
3662{
3663 /** Target code segment offset - Low word. */
3664 uint32_t u16OffsetLow : 16;
3665 /** Target code segment selector. */
3666 uint32_t u16Sel : 16;
3667 /** Interrupt stack table for interrupt- and trap-gates.
3668 * Ignored by call-gates. */
3669 uint32_t u3IST : 3;
3670 /** Reserved / ignored. */
3671 uint32_t u5Reserved : 5;
3672 /** Segment Type. */
3673 uint32_t u4Type : 4;
3674 /** Descriptor Type (0 = system). */
3675 uint32_t u1DescType : 1;
3676 /** Descriptor Privilege level. */
3677 uint32_t u2Dpl : 2;
3678 /** Flags selector present(=1) or not. */
3679 uint32_t u1Present : 1;
3680 /** Target code segment offset - High word.
3681 * Ignored if task-gate. */
3682 uint32_t u16OffsetHigh : 16;
3683 /** Target code segment offset - Top dword.
3684 * Ignored if task-gate. */
3685 uint32_t u32OffsetTop : 32;
3686 /** Reserved / ignored / must be zero.
3687 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3688 uint32_t u32Reserved : 32;
3689} X86DESC64GATE;
3690AssertCompileSize(X86DESC64GATE, 16);
3691/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3692typedef X86DESC64GATE *PX86DESC64GATE;
3693/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3694typedef const X86DESC64GATE *PCX86DESC64GATE;
3695
3696#endif /* VBOX_FOR_DTRACE_LIB */
3697
3698/**
3699 * Descriptor table entry.
3700 */
3701#pragma pack(1)
3702typedef union X86DESC64
3703{
3704#ifndef VBOX_FOR_DTRACE_LIB
3705 /** Generic descriptor view. */
3706 X86DESC64GENERIC Gen;
3707 /** System descriptor view. */
3708 X86DESC64SYSTEM System;
3709 /** Gate descriptor view. */
3710 X86DESC64GATE Gate;
3711#endif
3712
3713 /** 8 bit unsigned integer view. */
3714 uint8_t au8[16];
3715 /** 16 bit unsigned integer view. */
3716 uint16_t au16[8];
3717 /** 32 bit unsigned integer view. */
3718 uint32_t au32[4];
3719 /** 64 bit unsigned integer view. */
3720 uint64_t au64[2];
3721} X86DESC64;
3722#ifndef VBOX_FOR_DTRACE_LIB
3723AssertCompileSize(X86DESC64, 16);
3724#endif
3725#pragma pack()
3726/** Pointer to descriptor table entry. */
3727typedef X86DESC64 *PX86DESC64;
3728/** Pointer to const descriptor table entry. */
3729typedef const X86DESC64 *PCX86DESC64;
3730
3731/** @def X86DESC64_BASE
3732 * Return the base of a 64-bit descriptor.
3733 */
3734#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3735 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3736 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3737 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3738 | ( (a_pDesc)->Gen.u16BaseLow ) )
3739
3740
3741
3742/** @name Host system descriptor table entry - Use with care!
3743 * @{ */
3744/** Host system descriptor table entry. */
3745#if HC_ARCH_BITS == 64
3746typedef X86DESC64 X86DESCHC;
3747#else
3748typedef X86DESC X86DESCHC;
3749#endif
3750/** Pointer to a host system descriptor table entry. */
3751#if HC_ARCH_BITS == 64
3752typedef PX86DESC64 PX86DESCHC;
3753#else
3754typedef PX86DESC PX86DESCHC;
3755#endif
3756/** Pointer to a const host system descriptor table entry. */
3757#if HC_ARCH_BITS == 64
3758typedef PCX86DESC64 PCX86DESCHC;
3759#else
3760typedef PCX86DESC PCX86DESCHC;
3761#endif
3762/** @} */
3763
3764
3765/** @name Selector Descriptor Types.
3766 * @{
3767 */
3768
3769/** @name Non-System Selector Types.
3770 * @{ */
3771/** Code(=set)/Data(=clear) bit. */
3772#define X86_SEL_TYPE_CODE 8
3773/** Memory(=set)/System(=clear) bit. */
3774#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3775/** Accessed bit. */
3776#define X86_SEL_TYPE_ACCESSED 1
3777/** Expand down bit (for data selectors only). */
3778#define X86_SEL_TYPE_DOWN 4
3779/** Conforming bit (for code selectors only). */
3780#define X86_SEL_TYPE_CONF 4
3781/** Write bit (for data selectors only). */
3782#define X86_SEL_TYPE_WRITE 2
3783/** Read bit (for code selectors only). */
3784#define X86_SEL_TYPE_READ 2
3785/** The bit number of the code segment read bit (relative to u4Type). */
3786#define X86_SEL_TYPE_READ_BIT 1
3787
3788/** Read only selector type. */
3789#define X86_SEL_TYPE_RO 0
3790/** Accessed read only selector type. */
3791#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3792/** Read write selector type. */
3793#define X86_SEL_TYPE_RW 2
3794/** Accessed read write selector type. */
3795#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3796/** Expand down read only selector type. */
3797#define X86_SEL_TYPE_RO_DOWN 4
3798/** Accessed expand down read only selector type. */
3799#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3800/** Expand down read write selector type. */
3801#define X86_SEL_TYPE_RW_DOWN 6
3802/** Accessed expand down read write selector type. */
3803#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3804/** Execute only selector type. */
3805#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3806/** Accessed execute only selector type. */
3807#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3808/** Execute and read selector type. */
3809#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
3810/** Accessed execute and read selector type. */
3811#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3812/** Conforming execute only selector type. */
3813#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
3814/** Accessed Conforming execute only selector type. */
3815#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3816/** Conforming execute and write selector type. */
3817#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
3818/** Accessed Conforming execute and write selector type. */
3819#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
3820/** @} */
3821
3822
3823/** @name System Selector Types.
3824 * @{ */
3825/** The TSS busy bit mask. */
3826#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
3827
3828/** Undefined system selector type. */
3829#define X86_SEL_TYPE_SYS_UNDEFINED 0
3830/** 286 TSS selector. */
3831#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
3832/** LDT selector. */
3833#define X86_SEL_TYPE_SYS_LDT 2
3834/** 286 TSS selector - Busy. */
3835#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
3836/** 286 Callgate selector. */
3837#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
3838/** Taskgate selector. */
3839#define X86_SEL_TYPE_SYS_TASK_GATE 5
3840/** 286 Interrupt gate selector. */
3841#define X86_SEL_TYPE_SYS_286_INT_GATE 6
3842/** 286 Trapgate selector. */
3843#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
3844/** Undefined system selector. */
3845#define X86_SEL_TYPE_SYS_UNDEFINED2 8
3846/** 386 TSS selector. */
3847#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
3848/** Undefined system selector. */
3849#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
3850/** 386 TSS selector - Busy. */
3851#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
3852/** 386 Callgate selector. */
3853#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
3854/** Undefined system selector. */
3855#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
3856/** 386 Interruptgate selector. */
3857#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
3858/** 386 Trapgate selector. */
3859#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
3860/** @} */
3861
3862/** @name AMD64 System Selector Types.
3863 * @{ */
3864/** LDT selector. */
3865#define AMD64_SEL_TYPE_SYS_LDT 2
3866/** TSS selector - Busy. */
3867#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
3868/** TSS selector - Busy. */
3869#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
3870/** Callgate selector. */
3871#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
3872/** Interruptgate selector. */
3873#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
3874/** Trapgate selector. */
3875#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
3876/** @} */
3877
3878/** @} */
3879
3880
3881/** @name Descriptor Table Entry Flag Masks.
3882 * These are for the 2nd 32-bit word of a descriptor.
3883 * @{ */
3884/** Bits 8-11 - TYPE - Descriptor type mask. */
3885#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
3886/** Bit 12 - S - System (=0) or Code/Data (=1). */
3887#define X86_DESC_S RT_BIT_32(12)
3888/** Bits 13-14 - DPL - Descriptor Privilege Level. */
3889#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
3890/** Bit 15 - P - Present. */
3891#define X86_DESC_P RT_BIT_32(15)
3892/** Bit 20 - AVL - Available for system software. */
3893#define X86_DESC_AVL RT_BIT_32(20)
3894/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
3895#define X86_DESC_DB RT_BIT_32(22)
3896/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
3897 * used, if clear byte. */
3898#define X86_DESC_G RT_BIT_32(23)
3899/** @} */
3900
3901/** @} */
3902
3903
3904/** @name Task Segments.
3905 * @{
3906 */
3907
3908/**
3909 * The minimum TSS descriptor limit for 286 tasks.
3910 */
3911#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
3912
3913/**
3914 * The minimum TSS descriptor segment limit for 386 tasks.
3915 */
3916#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
3917
3918/**
3919 * 16-bit Task Segment (TSS).
3920 */
3921#pragma pack(1)
3922typedef struct X86TSS16
3923{
3924 /** Back link to previous task. (static) */
3925 RTSEL selPrev;
3926 /** Ring-0 stack pointer. (static) */
3927 uint16_t sp0;
3928 /** Ring-0 stack segment. (static) */
3929 RTSEL ss0;
3930 /** Ring-1 stack pointer. (static) */
3931 uint16_t sp1;
3932 /** Ring-1 stack segment. (static) */
3933 RTSEL ss1;
3934 /** Ring-2 stack pointer. (static) */
3935 uint16_t sp2;
3936 /** Ring-2 stack segment. (static) */
3937 RTSEL ss2;
3938 /** IP before task switch. */
3939 uint16_t ip;
3940 /** FLAGS before task switch. */
3941 uint16_t flags;
3942 /** AX before task switch. */
3943 uint16_t ax;
3944 /** CX before task switch. */
3945 uint16_t cx;
3946 /** DX before task switch. */
3947 uint16_t dx;
3948 /** BX before task switch. */
3949 uint16_t bx;
3950 /** SP before task switch. */
3951 uint16_t sp;
3952 /** BP before task switch. */
3953 uint16_t bp;
3954 /** SI before task switch. */
3955 uint16_t si;
3956 /** DI before task switch. */
3957 uint16_t di;
3958 /** ES before task switch. */
3959 RTSEL es;
3960 /** CS before task switch. */
3961 RTSEL cs;
3962 /** SS before task switch. */
3963 RTSEL ss;
3964 /** DS before task switch. */
3965 RTSEL ds;
3966 /** LDTR before task switch. */
3967 RTSEL selLdt;
3968} X86TSS16;
3969#ifndef VBOX_FOR_DTRACE_LIB
3970AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
3971#endif
3972#pragma pack()
3973/** Pointer to a 16-bit task segment. */
3974typedef X86TSS16 *PX86TSS16;
3975/** Pointer to a const 16-bit task segment. */
3976typedef const X86TSS16 *PCX86TSS16;
3977
3978
3979/**
3980 * 32-bit Task Segment (TSS).
3981 */
3982#pragma pack(1)
3983typedef struct X86TSS32
3984{
3985 /** Back link to previous task. (static) */
3986 RTSEL selPrev;
3987 uint16_t padding1;
3988 /** Ring-0 stack pointer. (static) */
3989 uint32_t esp0;
3990 /** Ring-0 stack segment. (static) */
3991 RTSEL ss0;
3992 uint16_t padding_ss0;
3993 /** Ring-1 stack pointer. (static) */
3994 uint32_t esp1;
3995 /** Ring-1 stack segment. (static) */
3996 RTSEL ss1;
3997 uint16_t padding_ss1;
3998 /** Ring-2 stack pointer. (static) */
3999 uint32_t esp2;
4000 /** Ring-2 stack segment. (static) */
4001 RTSEL ss2;
4002 uint16_t padding_ss2;
4003 /** Page directory for the task. (static) */
4004 uint32_t cr3;
4005 /** EIP before task switch. */
4006 uint32_t eip;
4007 /** EFLAGS before task switch. */
4008 uint32_t eflags;
4009 /** EAX before task switch. */
4010 uint32_t eax;
4011 /** ECX before task switch. */
4012 uint32_t ecx;
4013 /** EDX before task switch. */
4014 uint32_t edx;
4015 /** EBX before task switch. */
4016 uint32_t ebx;
4017 /** ESP before task switch. */
4018 uint32_t esp;
4019 /** EBP before task switch. */
4020 uint32_t ebp;
4021 /** ESI before task switch. */
4022 uint32_t esi;
4023 /** EDI before task switch. */
4024 uint32_t edi;
4025 /** ES before task switch. */
4026 RTSEL es;
4027 uint16_t padding_es;
4028 /** CS before task switch. */
4029 RTSEL cs;
4030 uint16_t padding_cs;
4031 /** SS before task switch. */
4032 RTSEL ss;
4033 uint16_t padding_ss;
4034 /** DS before task switch. */
4035 RTSEL ds;
4036 uint16_t padding_ds;
4037 /** FS before task switch. */
4038 RTSEL fs;
4039 uint16_t padding_fs;
4040 /** GS before task switch. */
4041 RTSEL gs;
4042 uint16_t padding_gs;
4043 /** LDTR before task switch. */
4044 RTSEL selLdt;
4045 uint16_t padding_ldt;
4046 /** Debug trap flag */
4047 uint16_t fDebugTrap;
4048 /** Offset relative to the TSS of the start of the I/O Bitmap
4049 * and the end of the interrupt redirection bitmap. */
4050 uint16_t offIoBitmap;
4051} X86TSS32;
4052#pragma pack()
4053/** Pointer to task segment. */
4054typedef X86TSS32 *PX86TSS32;
4055/** Pointer to const task segment. */
4056typedef const X86TSS32 *PCX86TSS32;
4057#ifndef VBOX_FOR_DTRACE_LIB
4058AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4059AssertCompileMemberOffset(X86TSS32, cr3, 28);
4060AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4061#endif
4062
4063/**
4064 * 64-bit Task segment.
4065 */
4066#pragma pack(1)
4067typedef struct X86TSS64
4068{
4069 /** Reserved. */
4070 uint32_t u32Reserved;
4071 /** Ring-0 stack pointer. (static) */
4072 uint64_t rsp0;
4073 /** Ring-1 stack pointer. (static) */
4074 uint64_t rsp1;
4075 /** Ring-2 stack pointer. (static) */
4076 uint64_t rsp2;
4077 /** Reserved. */
4078 uint32_t u32Reserved2[2];
4079 /* IST */
4080 uint64_t ist1;
4081 uint64_t ist2;
4082 uint64_t ist3;
4083 uint64_t ist4;
4084 uint64_t ist5;
4085 uint64_t ist6;
4086 uint64_t ist7;
4087 /* Reserved. */
4088 uint16_t u16Reserved[5];
4089 /** Offset relative to the TSS of the start of the I/O Bitmap
4090 * and the end of the interrupt redirection bitmap. */
4091 uint16_t offIoBitmap;
4092} X86TSS64;
4093#pragma pack()
4094/** Pointer to a 64-bit task segment. */
4095typedef X86TSS64 *PX86TSS64;
4096/** Pointer to a const 64-bit task segment. */
4097typedef const X86TSS64 *PCX86TSS64;
4098#ifndef VBOX_FOR_DTRACE_LIB
4099AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4100#endif
4101
4102/** @} */
4103
4104
4105/** @name Selectors.
4106 * @{
4107 */
4108
4109/**
4110 * The shift used to convert a selector from and to index an index (C).
4111 */
4112#define X86_SEL_SHIFT 3
4113
4114/**
4115 * The mask used to mask off the table indicator and RPL of an selector.
4116 */
4117#define X86_SEL_MASK 0xfff8U
4118
4119/**
4120 * The mask used to mask off the RPL of an selector.
4121 * This is suitable for checking for NULL selectors.
4122 */
4123#define X86_SEL_MASK_OFF_RPL 0xfffcU
4124
4125/**
4126 * The bit indicating that a selector is in the LDT and not in the GDT.
4127 */
4128#define X86_SEL_LDT 0x0004U
4129
4130/**
4131 * The bit mask for getting the RPL of a selector.
4132 */
4133#define X86_SEL_RPL 0x0003U
4134
4135/**
4136 * The mask covering both RPL and LDT.
4137 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4138 * checks.
4139 */
4140#define X86_SEL_RPL_LDT 0x0007U
4141
4142/** @} */
4143
4144
4145/**
4146 * x86 Exceptions/Faults/Traps.
4147 */
4148typedef enum X86XCPT
4149{
4150 /** \#DE - Divide error. */
4151 X86_XCPT_DE = 0x00,
4152 /** \#DB - Debug event (single step, DRx, ..) */
4153 X86_XCPT_DB = 0x01,
4154 /** NMI - Non-Maskable Interrupt */
4155 X86_XCPT_NMI = 0x02,
4156 /** \#BP - Breakpoint (INT3). */
4157 X86_XCPT_BP = 0x03,
4158 /** \#OF - Overflow (INTO). */
4159 X86_XCPT_OF = 0x04,
4160 /** \#BR - Bound range exceeded (BOUND). */
4161 X86_XCPT_BR = 0x05,
4162 /** \#UD - Undefined opcode. */
4163 X86_XCPT_UD = 0x06,
4164 /** \#NM - Device not available (math coprocessor device). */
4165 X86_XCPT_NM = 0x07,
4166 /** \#DF - Double fault. */
4167 X86_XCPT_DF = 0x08,
4168 /** ??? - Coprocessor segment overrun (obsolete). */
4169 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4170 /** \#TS - Taskswitch (TSS). */
4171 X86_XCPT_TS = 0x0a,
4172 /** \#NP - Segment no present. */
4173 X86_XCPT_NP = 0x0b,
4174 /** \#SS - Stack segment fault. */
4175 X86_XCPT_SS = 0x0c,
4176 /** \#GP - General protection fault. */
4177 X86_XCPT_GP = 0x0d,
4178 /** \#PF - Page fault. */
4179 X86_XCPT_PF = 0x0e,
4180 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4181 /** \#MF - Math fault (FPU). */
4182 X86_XCPT_MF = 0x10,
4183 /** \#AC - Alignment check. */
4184 X86_XCPT_AC = 0x11,
4185 /** \#MC - Machine check. */
4186 X86_XCPT_MC = 0x12,
4187 /** \#XF - SIMD Floating-Pointer Exception. */
4188 X86_XCPT_XF = 0x13,
4189 /** \#VE - Virtualization Exception. */
4190 X86_XCPT_VE = 0x14,
4191 /** \#SX - Security Exception. */
4192 X86_XCPT_SX = 0x1e
4193} X86XCPT;
4194/** Pointer to a x86 exception code. */
4195typedef X86XCPT *PX86XCPT;
4196/** Pointer to a const x86 exception code. */
4197typedef const X86XCPT *PCX86XCPT;
4198/** The last valid (currently reserved) exception value. */
4199#define X86_XCPT_LAST 0x1f
4200
4201
4202/** @name Trap Error Codes
4203 * @{
4204 */
4205/** External indicator. */
4206#define X86_TRAP_ERR_EXTERNAL 1
4207/** IDT indicator. */
4208#define X86_TRAP_ERR_IDT 2
4209/** Descriptor table indicator - If set LDT, if clear GDT. */
4210#define X86_TRAP_ERR_TI 4
4211/** Mask for getting the selector. */
4212#define X86_TRAP_ERR_SEL_MASK 0xfff8
4213/** Shift for getting the selector table index (C type index). */
4214#define X86_TRAP_ERR_SEL_SHIFT 3
4215/** @} */
4216
4217
4218/** @name \#PF Trap Error Codes
4219 * @{
4220 */
4221/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4222#define X86_TRAP_PF_P RT_BIT_32(0)
4223/** Bit 1 - R/W - Read (clear) or write (set) access. */
4224#define X86_TRAP_PF_RW RT_BIT_32(1)
4225/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4226#define X86_TRAP_PF_US RT_BIT_32(2)
4227/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4228#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4229/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4230#define X86_TRAP_PF_ID RT_BIT_32(4)
4231/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4232#define X86_TRAP_PF_PK RT_BIT_32(5)
4233/** @} */
4234
4235#pragma pack(1)
4236/**
4237 * 16-bit IDTR.
4238 */
4239typedef struct X86IDTR16
4240{
4241 /** Offset. */
4242 uint16_t offSel;
4243 /** Selector. */
4244 uint16_t uSel;
4245} X86IDTR16, *PX86IDTR16;
4246#pragma pack()
4247
4248#pragma pack(1)
4249/**
4250 * 32-bit IDTR/GDTR.
4251 */
4252typedef struct X86XDTR32
4253{
4254 /** Size of the descriptor table. */
4255 uint16_t cb;
4256 /** Address of the descriptor table. */
4257#ifndef VBOX_FOR_DTRACE_LIB
4258 uint32_t uAddr;
4259#else
4260 uint16_t au16Addr[2];
4261#endif
4262} X86XDTR32, *PX86XDTR32;
4263#pragma pack()
4264
4265#pragma pack(1)
4266/**
4267 * 64-bit IDTR/GDTR.
4268 */
4269typedef struct X86XDTR64
4270{
4271 /** Size of the descriptor table. */
4272 uint16_t cb;
4273 /** Address of the descriptor table. */
4274#ifndef VBOX_FOR_DTRACE_LIB
4275 uint64_t uAddr;
4276#else
4277 uint16_t au16Addr[4];
4278#endif
4279} X86XDTR64, *PX86XDTR64;
4280#pragma pack()
4281
4282
4283/** @name ModR/M
4284 * @{ */
4285#define X86_MODRM_RM_MASK UINT8_C(0x07)
4286#define X86_MODRM_REG_MASK UINT8_C(0x38)
4287#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4288#define X86_MODRM_REG_SHIFT 3
4289#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4290#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4291#define X86_MODRM_MOD_SHIFT 6
4292#ifndef VBOX_FOR_DTRACE_LIB
4293AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4294AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4295AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4296/** @def X86_MODRM_MAKE
4297 * @param a_Mod The mod value (0..3).
4298 * @param a_Reg The register value (0..7).
4299 * @param a_RegMem The register or memory value (0..7). */
4300# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4301#endif
4302/** @} */
4303
4304/** @name SIB
4305 * @{ */
4306#define X86_SIB_BASE_MASK UINT8_C(0x07)
4307#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4308#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4309#define X86_SIB_INDEX_SHIFT 3
4310#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4311#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4312#define X86_SIB_SCALE_SHIFT 6
4313#ifndef VBOX_FOR_DTRACE_LIB
4314AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4315AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4316AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4317#endif
4318/** @} */
4319
4320/** @name General register indexes
4321 * @{ */
4322#define X86_GREG_xAX 0
4323#define X86_GREG_xCX 1
4324#define X86_GREG_xDX 2
4325#define X86_GREG_xBX 3
4326#define X86_GREG_xSP 4
4327#define X86_GREG_xBP 5
4328#define X86_GREG_xSI 6
4329#define X86_GREG_xDI 7
4330#define X86_GREG_x8 8
4331#define X86_GREG_x9 9
4332#define X86_GREG_x10 10
4333#define X86_GREG_x11 11
4334#define X86_GREG_x12 12
4335#define X86_GREG_x13 13
4336#define X86_GREG_x14 14
4337#define X86_GREG_x15 15
4338/** @} */
4339
4340/** @name X86_SREG_XXX - Segment register indexes.
4341 * @{ */
4342#define X86_SREG_ES 0
4343#define X86_SREG_CS 1
4344#define X86_SREG_SS 2
4345#define X86_SREG_DS 3
4346#define X86_SREG_FS 4
4347#define X86_SREG_GS 5
4348/** @} */
4349/** Segment register count. */
4350#define X86_SREG_COUNT 6
4351
4352
4353/** @name X86_OP_XXX - Prefixes
4354 * @{ */
4355#define X86_OP_PRF_CS UINT8_C(0x2e)
4356#define X86_OP_PRF_SS UINT8_C(0x36)
4357#define X86_OP_PRF_DS UINT8_C(0x3e)
4358#define X86_OP_PRF_ES UINT8_C(0x26)
4359#define X86_OP_PRF_FS UINT8_C(0x64)
4360#define X86_OP_PRF_GS UINT8_C(0x65)
4361#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4362#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4363#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4364#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4365#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4366#define X86_OP_REX_B UINT8_C(0x41)
4367#define X86_OP_REX_X UINT8_C(0x42)
4368#define X86_OP_REX_R UINT8_C(0x44)
4369#define X86_OP_REX_W UINT8_C(0x48)
4370/** @} */
4371
4372
4373/** @} */
4374
4375#endif
4376
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