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source: vbox/trunk/include/iprt/armv8.h@ 104382

Last change on this file since 104382 was 104382, checked in by vboxsync, 7 weeks ago

iprt/armv8.h: Build fix. bugref:10652
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 register encoding - deprecated.
59 * @deprecated Use ARMV8_A64_REG_XXX instead.
60 * @todo correct code and drop these remaining ones.
61 * @{ */
62#define ARMV8_AARCH64_REG_X0 0
63#define ARMV8_AARCH64_REG_X1 1
64#define ARMV8_AARCH64_REG_X2 2
65#define ARMV8_AARCH64_REG_X3 3
66#define ARMV8_AARCH64_REG_ZR 31
67/** @} */
68
69/** @name The AArch64 general purpose register encoding.
70 * @{ */
71#define ARMV8_A64_REG_X0 0
72#define ARMV8_A64_REG_X1 1
73#define ARMV8_A64_REG_X2 2
74#define ARMV8_A64_REG_X3 3
75#define ARMV8_A64_REG_X4 4
76#define ARMV8_A64_REG_X5 5
77#define ARMV8_A64_REG_X6 6
78#define ARMV8_A64_REG_X7 7
79#define ARMV8_A64_REG_X8 8
80#define ARMV8_A64_REG_X9 9
81#define ARMV8_A64_REG_X10 10
82#define ARMV8_A64_REG_X11 11
83#define ARMV8_A64_REG_X12 12
84#define ARMV8_A64_REG_X13 13
85#define ARMV8_A64_REG_X14 14
86#define ARMV8_A64_REG_X15 15
87#define ARMV8_A64_REG_X16 16
88#define ARMV8_A64_REG_X17 17
89#define ARMV8_A64_REG_X18 18
90#define ARMV8_A64_REG_X19 19
91#define ARMV8_A64_REG_X20 20
92#define ARMV8_A64_REG_X21 21
93#define ARMV8_A64_REG_X22 22
94#define ARMV8_A64_REG_X23 23
95#define ARMV8_A64_REG_X24 24
96#define ARMV8_A64_REG_X25 25
97#define ARMV8_A64_REG_X26 26
98#define ARMV8_A64_REG_X27 27
99#define ARMV8_A64_REG_X28 28
100#define ARMV8_A64_REG_X29 29
101#define ARMV8_A64_REG_X30 30
102/** @} */
103
104/** @name The AArch64 32-bit general purpose register names.
105 * @{ */
106#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137/** @} */
138
139/** @name The AArch64 NEON scalar register encoding.
140 * @{ */
141#define ARMV8_A64_REG_Q0 0
142#define ARMV8_A64_REG_Q1 1
143#define ARMV8_A64_REG_Q2 2
144#define ARMV8_A64_REG_Q3 3
145#define ARMV8_A64_REG_Q4 4
146#define ARMV8_A64_REG_Q5 5
147#define ARMV8_A64_REG_Q6 6
148#define ARMV8_A64_REG_Q7 7
149#define ARMV8_A64_REG_Q8 8
150#define ARMV8_A64_REG_Q9 9
151#define ARMV8_A64_REG_Q10 10
152#define ARMV8_A64_REG_Q11 11
153#define ARMV8_A64_REG_Q12 12
154#define ARMV8_A64_REG_Q13 13
155#define ARMV8_A64_REG_Q14 14
156#define ARMV8_A64_REG_Q15 15
157#define ARMV8_A64_REG_Q16 16
158#define ARMV8_A64_REG_Q17 17
159#define ARMV8_A64_REG_Q18 18
160#define ARMV8_A64_REG_Q19 19
161#define ARMV8_A64_REG_Q20 20
162#define ARMV8_A64_REG_Q21 21
163#define ARMV8_A64_REG_Q22 22
164#define ARMV8_A64_REG_Q23 23
165#define ARMV8_A64_REG_Q24 24
166#define ARMV8_A64_REG_Q25 25
167#define ARMV8_A64_REG_Q26 26
168#define ARMV8_A64_REG_Q27 27
169#define ARMV8_A64_REG_Q28 28
170#define ARMV8_A64_REG_Q29 29
171#define ARMV8_A64_REG_Q30 30
172#define ARMV8_A64_REG_Q31 31
173/** @} */
174
175/** @name The AArch64 NEON vector register encoding.
176 * @{ */
177#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209/** @} */
210
211/** @name The AArch64 register 31.
212 * @note Register 31 typically refers to the zero register, but can also in
213 * select case (by instruction and opecode field) refer the to stack
214 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
215 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
216 * 31 will be the zero register.
217 * @{ */
218/** The stack pointer. */
219#define ARMV8_A64_REG_SP 31
220/** The zero register. Reads as zero, writes ignored. */
221#define ARMV8_A64_REG_XZR 31
222/** The zero register, the 32-bit register name. */
223#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224/** @} */
225
226/** @name AArch64 register aliases
227 * @{ */
228/** The link register is typically mapped to x30 as that's the default pick of
229 * the RET instruction. */
230#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231/** Frame base pointer is typically mapped to x29. */
232#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233/** @} */
234
235
236/** @name System register encoding.
237 * @{
238 */
239/** Mask for the op0 part of an MSR/MRS instruction */
240#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
241/** Shift for the op0 part of an MSR/MRS instruction */
242#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243/** Returns the op0 part of the given MRS/MSR instruction. */
244#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245/** Mask for the op1 part of an MSR/MRS instruction */
246#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
247/** Shift for the op1 part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249/** Returns the op1 part of the given MRS/MSR instruction. */
250#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251/** Mask for the CRn part of an MSR/MRS instruction */
252#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
253 | RT_BIT_32(15) )
254/** Shift for the CRn part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256/** Returns the CRn part of the given MRS/MSR instruction. */
257#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258/** Mask for the CRm part of an MSR/MRS instruction */
259#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
260 | RT_BIT_32(11) )
261/** Shift for the CRm part of an MSR/MRS instruction */
262#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263/** Returns the CRn part of the given MRS/MSR instruction. */
264#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265/** Mask for the op2 part of an MSR/MRS instruction */
266#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
267/** Shift for the op2 part of an MSR/MRS instruction */
268#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269/** Returns the op2 part of the given MRS/MSR instruction. */
270#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
273 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
274 | ARMV8_AARCH64_SYSREG_OP2_MASK)
275/** @} */
276
277/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278 * IPRT specific and not part of the ARMv8 specification.
279 * @{ */
280#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281 UINT16_C( (((a_Op0) & 0x3) << 14) \
282 | (((a_Op1) & 0x7) << 11) \
283 | (((a_CRn) & 0xf) << 7) \
284 | (((a_CRm) & 0xf) << 3) \
285 | ((a_Op2) & 0x7))
286/** Returns the internal system register ID from the given MRS/MSR instruction. */
287#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293/** Encodes the given system register ID in the given MSR/MRS instruction. */
294#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296/** @} */
297
298
299/** @name System register IDs.
300 * @{ */
301/** OSLAR_EL1 register - WO. */
302#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
303/** OSLSR_EL1 register - RO. */
304#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
305/** OSDLR_EL1 register - RW. */
306#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
307
308/** MIDR_EL1 register - RO. */
309#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
310/** MIPDR_EL1 register - RO. */
311#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
312/** REVIDR_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
314/** ID_PFR0_EL1 register - RO. */
315#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
316/** ID_PFR1_EL1 register - RO. */
317#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
318/** ID_DFR0_EL1 register - RO. */
319#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
320/** ID_AFR0_EL1 register - RO. */
321#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
322/** ID_MMFR0_EL1 register - RO. */
323#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
324/** ID_MMFR1_EL1 register - RO. */
325#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
326/** ID_MMFR2_EL1 register - RO. */
327#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
328/** ID_MMFR3_EL1 register - RO. */
329#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
330
331/** ID_ISAR0_EL1 register - RO. */
332#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
333/** ID_ISAR1_EL1 register - RO. */
334#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
335/** ID_ISAR2_EL1 register - RO. */
336#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
337/** ID_ISAR3_EL1 register - RO. */
338#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
339/** ID_ISAR4_EL1 register - RO. */
340#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
341/** ID_ISAR5_EL1 register - RO. */
342#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
343/** ID_MMFR4_EL1 register - RO. */
344#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
345/** ID_ISAR6_EL1 register - RO. */
346#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
347
348/** MVFR0_EL1 register - RO. */
349#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
350/** MVFR1_EL1 register - RO. */
351#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
352/** MVFR2_EL1 register - RO. */
353#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
354/** ID_PFR2_EL1 register - RO. */
355#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
356/** ID_DFR1_EL1 register - RO. */
357#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
358/** ID_MMFR5_EL1 register - RO. */
359#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
360
361/** ID_AA64PFR0_EL1 register - RO. */
362#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
363/** ID_AA64PFR0_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
365/** ID_AA64ZFR0_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
367/** ID_AA64SMFR0_EL1 register - RO. */
368#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
369
370/** ID_AA64DFR0_EL1 register - RO. */
371#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
372/** ID_AA64DFR0_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
374/** ID_AA64AFR0_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
376/** ID_AA64AFR1_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
378
379/** ID_AA64ISAR0_EL1 register - RO. */
380#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
381/** ID_AA64ISAR1_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
383/** ID_AA64ISAR2_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
385
386/** ID_AA64MMFR0_EL1 register - RO. */
387#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
388/** ID_AA64MMFR1_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
390/** ID_AA64MMFR2_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
392
393/** SCTRL_EL1 register - RW. */
394#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
395/** ACTRL_EL1 register - RW. */
396#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
397/** CPACR_EL1 register - RW. */
398#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
399/** RGSR_EL1 register - RW. */
400#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
401/** GCR_EL1 register - RW. */
402#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
403
404/** ZCR_EL1 register - RW. */
405#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
406/** TRFCR_EL1 register - RW. */
407#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
408/** SMPRI_EL1 register - RW. */
409#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
410/** SMCR_EL1 register - RW. */
411#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
412
413/** TTBR0_EL1 register - RW. */
414#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
415/** TTBR1_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
417/** TCR_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
419
420/** @todo APIA,APIB,APDA,APDB,APGA registers. */
421
422/** SPSR_EL1 register - RW. */
423#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
424/** ELR_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
426
427/** SP_EL0 register - RW. */
428#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
429
430/** PSTATE.SPSel value. */
431#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
432/** PSTATE.CurrentEL value. */
433#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
434/** PSTATE.PAN value. */
435#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
436/** PSTATE.UAO value. */
437#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
438
439/** PSTATE.ALLINT value. */
440#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
441
442/** ICC_PMR_EL1 register - RW. */
443#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
444
445/** AFSR0_EL1 register - RW. */
446#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
447/** AFSR1_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
449
450/** ESR_EL1 register - RW. */
451#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
452
453/** ERRIDR_EL1 register - RO. */
454#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
455/** ERRSELR_EL1 register - RW. */
456#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
457
458/** ICC_IAR0_EL1 register - RO. */
459#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
460/** ICC_EOIR0_EL1 register - WO. */
461#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
462/** ICC_HPPIR0_EL1 register - WO. */
463#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
464/** ICC_BPR0_EL1 register - RW. */
465#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
466/** ICC_AP0R0_EL1 register - RW. */
467#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
468/** ICC_AP0R1_EL1 register - RW. */
469#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
470/** ICC_AP0R2_EL1 register - RW. */
471#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
472/** ICC_AP0R3_EL1 register - RW. */
473#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
474
475/** ICC_AP1R0_EL1 register - RW. */
476#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
477/** ICC_AP1R1_EL1 register - RW. */
478#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
479/** ICC_AP1R2_EL1 register - RW. */
480#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
481/** ICC_AP1R3_EL1 register - RW. */
482#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
483/** ICC_NMIAR1_EL1 register - RO. */
484#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
485
486/** ICC_DIR_EL1 register - WO. */
487#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
488/** ICC_RPR_EL1 register - RO. */
489#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
490/** ICC_SGI1R_EL1 register - WO. */
491#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
492/** ICC_ASGI1R_EL1 register - WO. */
493#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
494/** ICC_SGI0R_EL1 register - WO. */
495#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
496
497/** ICC_IAR1_EL1 register - RO. */
498#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
499/** ICC_EOIR1_EL1 register - WO. */
500#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
501/** ICC_HPPIR1_EL1 register - RO. */
502#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
503/** ICC_BPR1_EL1 register - RW. */
504#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
505/** ICC_CTLR_EL1 register - RW. */
506#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
507/** ICC_SRE_EL1 register - RW. */
508#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
509/** ICC_IGRPEN0_EL1 register - RW. */
510#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
511/** ICC_IGRPEN1_EL1 register - RW. */
512#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
513
514/** NZCV - Status Flags - ??. */
515#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
516/** DAIF - Interrupt Mask Bits - ??. */
517#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
518/** SVCR - Streaming Vector Control Register - ??. */
519#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
520/** DIT - Data Independent Timing - ??. */
521#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
522/** SSBS - Speculative Store Bypass Safe - ??. */
523#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
524/** TCO - Tag Check Override - ??. */
525#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
526
527/** CNTV_CTL_EL0 register - RW. */
528#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
529/** @} */
530
531
532#ifndef RT_IN_ASSEMBLER
533/**
534 * SPSR_EL2 (according to chapter C5.2.19)
535 */
536typedef union ARMV8SPSREL2
537{
538 /** The plain unsigned view. */
539 uint64_t u;
540 /** The 8-bit view. */
541 uint8_t au8[8];
542 /** The 16-bit view. */
543 uint16_t au16[4];
544 /** The 32-bit view. */
545 uint32_t au32[2];
546 /** The 64-bit view. */
547 uint64_t u64;
548} ARMV8SPSREL2;
549/** Pointer to SPSR_EL2. */
550typedef ARMV8SPSREL2 *PARMV8SPSREL2;
551/** Pointer to const SPSR_EL2. */
552typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
553#endif /* !RT_IN_ASSEMBLER */
554
555
556/** @name SPSR_EL2 (When exception is taken from AArch64 state)
557 * @{
558 */
559/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
560#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
561#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
562/** Bit 0 - SP - Selected stack pointer. */
563#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
564#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
565/** Bit 1 - Reserved (read as zero). */
566#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
567/** Bit 2 - 3 - EL - Exception level. */
568#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
569#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
570#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
571#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
572/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
573#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
574#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
575/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
576#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
577#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
578/** Bit 6 - I - FIQ interrupt mask. */
579#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
580#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
581/** Bit 7 - I - IRQ interrupt mask. */
582#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
583#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
584/** Bit 8 - A - SError interrupt mask. */
585#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
586#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
587/** Bit 9 - D - Debug Exception mask. */
588#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
589#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
590/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
591#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
592#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
593#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
594/** Bit 12 - SSBS - Speculative Store Bypass. */
595#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
596#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
597/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
598#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
599#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
600/** Bit 14 - 19 - Reserved (read as zero). */
601#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
602 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
603/** Bit 20 - IL - Illegal Execution State flag. */
604#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
605#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
606/** Bit 21 - SS - Software Step flag. */
607#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
608#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
609/** Bit 22 - PAN - Privileged Access Never flag. */
610#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
611#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
612/** Bit 23 - UAO - User Access Override flag. */
613#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
614#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
615/** Bit 24 - DIT - Data Independent Timing flag. */
616#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
617#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
618/** Bit 25 - TCO - Tag Check Override flag. */
619#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
620#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
621/** Bit 26 - 27 - Reserved (read as zero). */
622#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
623/** Bit 28 - V - Overflow condition flag. */
624#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
625#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
626/** Bit 29 - C - Carry condition flag. */
627#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
628#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
629/** Bit 30 - Z - Zero condition flag. */
630#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
631#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
632/** Bit 31 - N - Negative condition flag. */
633#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
634#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
635/** Bit 32 - 63 - Reserved (read as zero). */
636#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
637/** Checks whether the given SPSR value contains a AARCH64 execution state. */
638#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
639/** @} */
640
641/** @name Aarch64 Exception levels
642 * @{ */
643/** Exception Level 0 - User mode. */
644#define ARMV8_AARCH64_EL_0 0
645/** Exception Level 1 - Supervisor mode. */
646#define ARMV8_AARCH64_EL_1 1
647/** Exception Level 2 - Hypervisor mode. */
648#define ARMV8_AARCH64_EL_2 2
649/** @} */
650
651
652/** @name ESR_EL2 (Exception Syndrome Register, EL2)
653 * @{
654 */
655/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
656#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
657#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
658/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
659#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
660#define ARMV8_ESR_EL2_IL_BIT 25
661#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
662#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
663/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
664#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
665 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
666#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
667/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
668#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
669 | RT_BIT_64(35) | RT_BIT_64(36))
670#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
671/** @} */
672
673
674/** @name ESR_EL2 Exception Classes (EC)
675 * @{ */
676/** Unknown exception reason. */
677#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
678/** Trapped WF* instruction. */
679#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
680/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
681#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
682/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
683#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
684/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
685#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
686/** AArch32 - Trapped LDC or STC access. */
687#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
688/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
689#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
690/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
691#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
692/** AArch32 - Trapped pointer authentication instruction. */
693#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
694/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
695#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
696/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
697#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
698/** FEAT_BTI - Branch Target Exception. */
699#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
700/** Illegal Execution State. */
701#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
702/** AArch32 - SVC instruction execution. */
703#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
704/** AArch32 - HVC instruction execution. */
705#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
706/** AArch32 - SMC instruction execution. */
707#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
708/** AArch64 - SVC instruction execution. */
709#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
710/** AArch64 - HVC instruction execution. */
711#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
712/** AArch64 - SMC instruction execution. */
713#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
714/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
715#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
716/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
717#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
718/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
719#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
720/** FEAT_TME - Exception from TSTART instruction. */
721#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
722/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
723#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
724/** FEAT_SME - Access to SME functionality trapped. */
725#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
726/** FEAT_RME - Exception from Granule Protection Check. */
727#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
728/** Instruction Abort from a lower Exception level. */
729#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
730/** Instruction Abort from the same Exception level. */
731#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
732/** PC alignment fault exception. */
733#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
734/** Data Abort from a lower Exception level. */
735#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
736/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
737#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
738/** SP alignment fault exception. */
739#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
740/** FEAT_MOPS - Memory Operation Exception. */
741#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
742/** AArch32 - Trapped floating point exception. */
743#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
744/** AArch64 - Trapped floating point exception. */
745#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
746/** SError interrupt. */
747#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
748/** Breakpoint Exception from a lower Exception level. */
749#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
750/** Breakpoint Exception from the same Exception level. */
751#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
752/** Software Step Exception from a lower Exception level. */
753#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
754/** Software Step Exception from the same Exception level. */
755#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
756/** Watchpoint Exception from a lower Exception level. */
757#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
758/** Watchpoint Exception from the same Exception level. */
759#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
760/** AArch32 - BKPT instruction execution. */
761#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
762/** AArch32 - Vector Catch exception. */
763#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
764/** AArch64 - BRK instruction execution. */
765#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
766/** @} */
767
768
769/** @name ISS encoding for Data Abort exceptions.
770 * @{ */
771/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
772#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
773 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
774#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
775/** Bit 6 - WnR - Write not Read. */
776#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
777#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
778/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
779#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
780#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
781/** Bit 8 - CM - Cache maintenance instruction. */
782#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
783#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
784/** Bit 9 - EA - External abort type. */
785#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
786#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
787/** Bit 10 - FnV - FAR not Valid. */
788#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
789#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
790/** Bit 11 - 12 - LST - Load/Store Type. */
791#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
792#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
793/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
794#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
795#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
796/** Bit 14 - AR - Acquire/Release semantics. */
797#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
798#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
799/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
800#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
801#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
802/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
803#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
804 | RT_BIT_32(19) | RT_BIT_32(20))
805#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
806/** Bit 21 - SSE - Syndrome Sign Extend. */
807#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
808#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
809/** Bit 22 - 23 - SAS - Syndrome Access Size. */
810#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
811#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
812/** Bit 24 - ISV - Instruction Syndrome Valid. */
813#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
814#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
815/** @} */
816
817
818/** @name Data Fault Status Code (DFSC).
819 * @{ */
820/** Address size fault, level 0 of translation or translation table base register. */
821#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
822/** Address size fault, level 1. */
823#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
824/** Address size fault, level 2. */
825#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
826/** Address size fault, level 3. */
827#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
828/** Translation fault, level 0. */
829#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
830/** Translation fault, level 1. */
831#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
832/** Translation fault, level 2. */
833#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
834/** Translation fault, level 3. */
835#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
836/** FEAT_LPA2 - Access flag fault, level 0. */
837#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
838/** Access flag fault, level 1. */
839#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
840/** Access flag fault, level 2. */
841#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
842/** Access flag fault, level 3. */
843#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
844/** FEAT_LPA2 - Permission fault, level 0. */
845#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
846/** Permission fault, level 1. */
847#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
848/** Permission fault, level 2. */
849#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
850/** Permission fault, level 3. */
851#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
852/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
853#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
854/** FEAT_MTE2 - Synchronous Tag Check Fault. */
855#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
856/** @todo Do the rest (lazy developer). */
857/** @} */
858
859
860/** @name SAS encoding.
861 * @{ */
862/** Byte access. */
863#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
864/** Halfword access (uint16_t). */
865#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
866/** Word access (uint32_t). */
867#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
868/** Doubleword access (uint64_t). */
869#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
870/** @} */
871
872
873/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
874 * @{ */
875/** Bit 0 - Direction flag. */
876#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
877#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
878/** Bit 1 - 4 - CRm value from the instruction. */
879#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
880 | RT_BIT_32(4))
881#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
882/** Bit 5 - 9 - Rt value from the instruction. */
883#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
884 | RT_BIT_32(8) | RT_BIT_32(9))
885#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
886/** Bit 10 - 13 - CRn value from the instruction. */
887#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
888 | RT_BIT_32(13))
889#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
890/** Bit 14 - 16 - Op2 value from the instruction. */
891#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
892#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
893/** Bit 17 - 19 - Op2 value from the instruction. */
894#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
895#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
896/** Bit 20 - 21 - Op0 value from the instruction. */
897#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
898#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
899/** Bit 22 - 24 - Reserved. */
900#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
901/** @} */
902
903
904/** @name ISS encoding for trapped HVC instruction exceptions.
905 * @{ */
906/** Bit 0 - 15 - imm16 value of the instruction. */
907#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
908#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
909/** @} */
910
911
912/** @name TCR_EL1 - Translation Control Register (EL1)
913 * @{
914 */
915/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
916#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
917 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
918#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
919/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
920#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
921#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
922/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
923#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
924#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
925/** Non cacheable. */
926# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
927/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
928# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
929/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
930# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
931/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
932# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
933/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
934#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
935#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
936/** Non cacheable. */
937# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
938/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
939# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
940/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
941# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
942/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
943# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
944/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
945#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
946#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
947/** Non shareable. */
948# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
949/** Invalid value. */
950# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
951/** Outer Shareable. */
952# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
953/** Inner Shareable. */
954# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
955/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
956#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
957#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
958/** Invalid granule size. */
959# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
960/** 16KiB granule size. */
961# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
962/** 4KiB granule size. */
963# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
964/** 64KiB granule size. */
965# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
966/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
967#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
968 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
969#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
970/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
971#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
972#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
973/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
974#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
975#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
976/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
977#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
978#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
979/** Non cacheable. */
980# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
981/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
982# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
983/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
984# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
985/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
986# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
987/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
988#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
989#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
990/** Non cacheable. */
991# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
992/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
993# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
994/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
995# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
996/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
997# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
998/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
999#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1000#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1001/** Non shareable. */
1002# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1003/** Invalid value. */
1004# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1005/** Outer Shareable. */
1006# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1007/** Inner Shareable. */
1008# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1009/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1010#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1011#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1012/** Invalid granule size. */
1013# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1014/** 16KiB granule size. */
1015# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1016/** 4KiB granule size. */
1017# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1018/** 64KiB granule size. */
1019# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1020/** Bit 32 - 34 - Intermediate Physical Address Size. */
1021#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1022#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1023/** IPA - 32 bits, 4GiB. */
1024# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1025/** IPA - 36 bits, 64GiB. */
1026# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1027/** IPA - 40 bits, 1TiB. */
1028# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1029/** IPA - 42 bits, 4TiB. */
1030# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1031/** IPA - 44 bits, 16TiB. */
1032# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1033/** IPA - 48 bits, 256TiB. */
1034# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1035/** IPA - 52 bits, 4PiB. */
1036# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1037/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1038#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1039#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1040/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1041#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1042#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1043/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1044#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1045#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1046/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1047#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1048#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1049/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1050#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1051#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1052/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1053#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1054#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1055/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1056#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1057#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1058/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1059#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1060#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1061/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1062#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1063#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1064/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1065#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1066#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1067/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1068#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1069#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1070/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1071#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1072#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1073/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1074#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1075#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1076/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1077#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1078#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1079/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1080#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1081#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1082/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1083#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1084#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1085/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1086#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1087#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1088/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1089#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1090#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1091/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1092#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1093#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1094/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1095#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1096#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1097/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1098#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1099#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1100/** Bit 57 - TCMA0 */
1101#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1102#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1103/** Bit 58 - TCMA1 */
1104#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1105#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1106/** Bit 59 - Data Sharing(?). */
1107#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1108#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1109/** @} */
1110
1111
1112/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1113 * @{
1114 */
1115/** Bit 0 - Common not Private (FEAT_TTCNP). */
1116#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1117#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1118/** Bit 1 - 47 - Translation table base address. */
1119#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1120#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1121/** Bit 48 - 63 - ASID. */
1122#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1123#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1124/** @} */
1125
1126
1127/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1128 * @{ */
1129/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1130#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1131#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1132#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1133/** @} */
1134
1135
1136/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1137 * @{ */
1138/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1139#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1140#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1141#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1142/** @} */
1143
1144
1145/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1146 * @{ */
1147/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1148#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1149#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1150#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1151/** @} */
1152
1153
1154/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1155 * @{ */
1156/** Bit 0 - Common Binary Pointer Register - RW. */
1157#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1158#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1159/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1160#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1161#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1162/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1163#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1164#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1165/** Bit 8 - 10 - Priority bits - RO. */
1166#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1167#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1168/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1169#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1170#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1171/** INTIDS are 16-bit wide. */
1172# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1173/** INTIDS are 24-bit wide. */
1174# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1175/** Bit 14 - SEI Supported - RO. */
1176#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1177#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1178/** Bit 15 - Affinity 3 Valid - RO. */
1179#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1180#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1181/** Bit 18 - Range Selector Support - RO. */
1182#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1183#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1184/** Bit 19 - Extended INTID range supported - RO. */
1185#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1186#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1187/** All RW bits. */
1188#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1189/** All RO bits (including Res0). */
1190#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1191/** @} */
1192
1193
1194/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1195 * @{ */
1196/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1197#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1198#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1199/** @} */
1200
1201
1202/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1203 * @{ */
1204/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1205#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1206#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1207/** @} */
1208
1209
1210/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1211 * @{ */
1212/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1213#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1214#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1215/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1216#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1217#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1218/** Bit 24 - 27 - The INTID of the SGI. */
1219#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1220#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1221/* Bit 28 - 31 - Reserved. */
1222/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1223#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1224#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1225/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1226#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1227#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1228/* Bit 41 - 43 - Reserved. */
1229/** Bit 44 - 47 - Range selector. */
1230#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1231#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1232/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1233#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1234#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1235/* Bit 56 - 63 - Reserved. */
1236/** @} */
1237
1238
1239/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1240 * @{ */
1241/** Bit 0 - Enables the timer. */
1242#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1243#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1244/** Bit 1 - Timer interrupt mask bit. */
1245#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1246#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1247/** Bit 2 - Timer status bit. */
1248#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1249#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1250/** @} */
1251
1252
1253/** @name OSLAR_EL1 - OS Lock Access Register.
1254 * @{ */
1255/** Bit 0 - The OS Lock status bit. */
1256#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1257#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1258/** @} */
1259
1260
1261/** @name OSLSR_EL1 - OS Lock Status Register.
1262 * @{ */
1263/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1264#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1265#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1266/** Bit 1 - The OS Lock status bit. */
1267#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1268#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1269/** Bit 2 - Not 32-bit access. */
1270#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1271#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1272/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1273#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1274#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1275/** @} */
1276
1277
1278/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1279 * @{ */
1280/* Bit 0 - 3 - Reserved. */
1281/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1282#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1283#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1284/** No AES instructions implemented. */
1285# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1286/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1287# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1288/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1289# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1290/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1291#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1292#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1293/** No SHA1 instructions implemented. */
1294# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1295/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1296# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1297/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1298#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1299#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1300/** No SHA2 instructions implemented. */
1301# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1302/** SHA256 instructions implemented (FEAT_SHA256). */
1303# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1304/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1305# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1306/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1307#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1308#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1309/** No CRC32 instructions implemented. */
1310# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1311/** CRC32 instructions implemented (FEAT_CRC32). */
1312# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1313/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1314#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1315#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1316/** No Atomic instructions implemented. */
1317# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1318/** Atomic instructions implemented (FEAT_LSE). */
1319# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1320/** Bit 24 - 27 - Indicates support for TME instructions. */
1321#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1322#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1323/** TME instructions are not implemented. */
1324# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1325/** TME instructions are implemented. */
1326# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1327/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1328#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1329#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1330/** No RDMA instructions implemented. */
1331# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1332/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1333# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1334/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1335#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1336#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1337/** No SHA3 instructions implemented. */
1338# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1339/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1340# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1341/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1342#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1343#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1344/** No SM3 instructions implemented. */
1345# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1346/** SM3 instructions implemented (FEAT_SM3). */
1347# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1348/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1349#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1350#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1351/** No SM4 instructions implemented. */
1352# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1353/** SM4 instructions implemented (FEAT_SM4). */
1354# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1355/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1356#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1357#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1358/** No Dot Product instructions implemented. */
1359# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1360/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1361# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1362/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1363#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1364#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1365/** FMLAL and FMLSL instructions are not implemented. */
1366# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1367/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1368# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1369/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1370#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1371#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1372/** No flag manipulation instructions implemented. */
1373# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1374/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1375# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1376/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1377# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1378/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1379#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1380#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1381/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1382# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1383/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1384# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1385/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1386# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1387/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1388#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1389#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1390/** No Random Number instructions implemented. */
1391# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1392/** RNDR and RDNRRS registers are implemented . */
1393# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1394/** @} */
1395
1396
1397/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1398 * @{ */
1399/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1400#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1401#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1402/** DC CVAP not supported. */
1403# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1404/** DC CVAP supported (FEAT_DPB). */
1405# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1406/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1407# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1408/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1409#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1410#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1411/** Address Authentication using the QARMA5 algorithm is not implemented. */
1412# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1413/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1414# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1415/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1416# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1417/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1418# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1419/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1420# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1421/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1422# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1423/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1424#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1425#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1426/** Address Authentication using the QARMA5 algorithm is not implemented. */
1427# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1428/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1429# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1430/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1431# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1432/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1433# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1434/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1435# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1436/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1437# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1438/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1439#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1440#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1441/** No FJCVTZS instruction implemented. */
1442# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1443/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1444# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1445/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1446#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1447#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1448/** No FCMLA and FCADD instructions implemented. */
1449# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1450/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1451# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1452/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1453#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1454#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1455/** No RCpc instructions implemented. */
1456# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1457/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1458# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1459/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1460# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1461/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1462#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1463#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1464/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1465# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1466/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1467# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1468/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1469#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1470#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1471/** Generic Authentication using an implementation defined algorithm is not implemented. */
1472# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1473/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1474# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1475/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1476#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1477#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1478/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1479# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1480/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1481# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1482/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1483#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1484#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1485/** No SB instructions implemented. */
1486# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1487/** SB instructions implemented (FEAT_SB). */
1488# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1489/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1490#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1491#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1492/** Prediction invalidation instructions are not implemented. */
1493# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1494/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1495# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1496/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1497#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1498#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1499/** BFloat16 instructions are not implemented. */
1500# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1501/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1502# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1503/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1504# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1505/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1506#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1507#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1508/** Data Gathering Hint instructions are not implemented. */
1509# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1510/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1511# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1512/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1513#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1514#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1515/** No Int8 matrix multiplication instructions implemented. */
1516# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1517/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1518# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1519/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1520#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1521#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1522/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1523# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1524/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1525# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1526/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1527#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1528#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1529/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1530# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1531/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1532# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1533/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1534# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1535/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1536# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1537/** @} */
1538
1539
1540/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1541 * @{ */
1542/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1543#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1544#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1545/** WFET and WFIT are not supported. */
1546# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1547/** WFET and WFIT are supported (FEAT_WFxT). */
1548# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1549/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1550#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1551#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1552/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1553# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1554/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1555# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1556/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1557#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1558#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1559/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1560# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1561/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1562# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1563/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1564#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1565#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1566/** Address Authentication using the QARMA3 algorithm is not implemented. */
1567# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1568/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1569# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1570/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1571# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1572/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1573# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1574/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1575# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1576/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1577# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1578/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1579#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1580#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1581/** No Memory Copy and Memory Set instructions implemented. */
1582# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1583/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1584# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1585/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1586#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1587#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1588/** BC instruction is not implemented. */
1589# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1590/** BC instruction is implemented (FEAT_HBC). */
1591# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1592/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1593#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1594#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1595/** ConstPACField() returns FALSE. */
1596# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1597/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1598# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1599/* Bit 28 - 63 - Reserved. */
1600/** @} */
1601
1602
1603/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1604 * @{ */
1605/** Bit 0 - 3 - EL0 Exception level handling. */
1606#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1607#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1608/** EL0 can be executed in AArch64 state only. */
1609# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1610/** EL0 can be executed in AArch64 and AArch32 state. */
1611# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1612/** Bit 4 - 7 - EL1 Exception level handling. */
1613#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1614#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1615/** EL1 can be executed in AArch64 state only. */
1616# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1617/** EL1 can be executed in AArch64 and AArch32 state. */
1618# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1619/** Bit 8 - 11 - EL2 Exception level handling. */
1620#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1621#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1622/** EL2 is not implemented. */
1623# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1624/** EL2 can be executed in AArch64 state only. */
1625# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1626/** EL2 can be executed in AArch64 and AArch32 state. */
1627# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1628/** Bit 12 - 15 - EL3 Exception level handling. */
1629#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1630#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1631/** EL3 is not implemented. */
1632# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1633/** EL3 can be executed in AArch64 state only. */
1634# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1635/** EL3 can be executed in AArch64 and AArch32 state. */
1636# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1637/** Bit 16 - 19 - Floating-point support. */
1638#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1639#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1640/** Floating-point is implemented and support single and double precision. */
1641# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1642/** Floating-point is implemented and support single, double and half precision. */
1643# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1644/** Floating-point is not implemented. */
1645# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1646/** Bit 20 - 23 - Advanced SIMD support. */
1647#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1648#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1649/** Advanced SIMD is implemented and support single and double precision. */
1650# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1651/** Advanced SIMD is implemented and support single, double and half precision. */
1652# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1653/** Advanced SIMD is not implemented. */
1654# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1655/** Bit 24 - 27 - System register GIC CPU interface support. */
1656#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1657#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1658/** GIC CPU interface system registers are not implemented. */
1659# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1660/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1661# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1662/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1663# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1664/** Bit 28 - 31 - RAS Extension version. */
1665#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1666#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1667/** No RAS extension. */
1668# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1669/** RAS Extension implemented. */
1670# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1671/** FEAT_RASv1p1 implemented. */
1672# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1673/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1674#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1675#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1676/** SVE is not supported. */
1677# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1678/** SVE is supported. */
1679# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1680/** Bit 36 - 39 - Secure EL2 support. */
1681#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1682#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1683/** Secure EL2 is not supported. */
1684# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1685/** Secure EL2 is implemented. */
1686# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1687/** Bit 40 - 43 - MPAM support. */
1688#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1689#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1690/** MPAM extension major version number is 0. */
1691# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1692/** MPAM extension major version number is 1. */
1693# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1694/** Bit 44 - 47 - Activity Monitor Extension support. */
1695#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1696#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1697/** Activity Monitor extension is not implemented. */
1698# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1699/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1700# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1701/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1702# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1703/** Bit 48 - 51 - Data Independent Timing support. */
1704#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1705#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1706/** AArch64 does not guarantee constant execution time of any instructions. */
1707# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1708/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1709# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1710/** Bit 52 - 55 - Realm Management Extension support. */
1711#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1712#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1713/** Realm Management Extension not implemented. */
1714# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1715/** RMEv1 is implemented (FEAT_RME). */
1716# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1717/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1718#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1719#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1720/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1721# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1722/** FEAT_CSV2 is implemented. */
1723# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1724/** FEAT_CSV2_2 is implemented. */
1725# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1726/** FEAT_CSV2_3 is implemented. */
1727# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1728/** Bit 60 - 63 - Speculative use of faulting data support. */
1729#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1730#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1731/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1732# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1733/** FEAT_CSV3 is supported . */
1734# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1735/** @} */
1736
1737
1738/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1739 * @{ */
1740/** Bit 0 - 3 - Branch Target Identification support. */
1741#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1742#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1743/** The Branch Target Identification mechanism is not implemented. */
1744# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1745/** The Branch Target Identifcation mechanism is implemented. */
1746# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1747/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1748#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1749#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1750/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1751# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1752/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1753# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1754/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1755 * to directly read and write the PSTATE.SSBS field. */
1756# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1757/** Bit 8 - 11 - Memory Tagging Extension support. */
1758#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1759#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1760/** MTE is not implemented. */
1761# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1762/** Instruction only Memory Tagging Extensions implemented. */
1763# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1764/** Full Memory Tagging Extension implemented. */
1765# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1766/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1767# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1768/** Bit 12 - 15 - RAS Extension fractional field. */
1769#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1770#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1771/** RAS Extension is implemented. */
1772# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1773/** FEAT_RASv1p1 is implemented. */
1774# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1775/** Bit 16 - 19 - MPAM minor version number. */
1776#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1777#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1778/** The minor version of number of the MPAM extension is 0. */
1779# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1780/** The minor version of number of the MPAM extension is 1. */
1781# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1782/* Bit 20 - 23 - Reserved. */
1783/** Bit 24 - 27 - Scalable Matrix Extension support. */
1784#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1785#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1786/** Scalable Matrix Extensions are not implemented. */
1787# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1788/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1789# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1790/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1791# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1792/** Bit 28 - 31 - Random Number trap to EL3 support. */
1793#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1794#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1795/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1796# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1797/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1798# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1799/** Bit 32 - 35 - CSV2 fractional field. */
1800#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1801#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1802/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1803# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1804/** FEAT_CSV2_1p1 is implemented. */
1805# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1806/** FEAT_CSV2_1p2 is implemented. */
1807# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1808/** Bit 36 - 39 - Non-maskable Interrupt support. */
1809#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1810#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1811/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1812# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1813/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1814# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1815/** @} */
1816
1817
1818/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1819 * @{ */
1820/** Bit 0 - 3 - Physical Address range supported. */
1821#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1822#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1823/** Physical Address range is 32 bits, 4GiB. */
1824# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1825/** Physical Address range is 36 bits, 64GiB. */
1826# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1827/** Physical Address range is 40 bits, 1TiB. */
1828# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1829/** Physical Address range is 42 bits, 4TiB. */
1830# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1831/** Physical Address range is 44 bits, 16TiB. */
1832# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1833/** Physical Address range is 48 bits, 256TiB. */
1834# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1835/** Physical Address range is 52 bits, 4PiB. */
1836# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1837/** Bit 4 - 7 - Number of ASID bits. */
1838#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1839#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1840/** ASID bits is 8. */
1841# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1842/** ASID bits is 16. */
1843# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1844/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1845#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1846#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1847/** No mixed-endian support. */
1848# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1849/** Mixed-endian supported. */
1850# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1851/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1852#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1853#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1854/** No distinction between Secure and Non-secure Memory supported. */
1855# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1856/** Distinction between Secure and Non-secure Memory supported. */
1857# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1858/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1859#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1860#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1861/** No mixed-endian support at EL0. */
1862# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1863/** Mixed-endian support at EL0. */
1864# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1865/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1866#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1867#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1868/** 16KiB granule size not supported. */
1869# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1870/** 16KiB granule size is supported. */
1871# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1872/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1873# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1874/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1875#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1876#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1877/** 64KiB granule supported. */
1878# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1879/** 64KiB granule not supported. */
1880# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1881/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1882#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1883#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1884/** 4KiB granule supported. */
1885# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1886/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1887# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1888/** 4KiB granule not supported. */
1889# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1890/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1891#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1892#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1893/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1894# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1895/** 16KiB granule not supported at stage 2. */
1896# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1897/** 16KiB granule supported at stage 2. */
1898# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1899/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1900# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1901/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1902#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1903#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1904/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1905# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1906/** 64KiB granule not supported at stage 2. */
1907# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1908/** 64KiB granule supported at stage 2. */
1909# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1910/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1911#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1912#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1913/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1914# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1915/** 4KiB granule not supported at stage 2. */
1916# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1917/** 4KiB granule supported at stage 2. */
1918# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1919/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1920# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1921/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1922#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1923#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1924/** All exception entries and exits are context synchronization events. */
1925# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1926/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1927# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1928/* Bit 48 - 55 - Reserved. */
1929/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1930#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1931#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1932/** Fine-grained trap controls are not implemented. */
1933# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1934/** Fine-grained trap controls are implemented (FEAT_FGT). */
1935# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1936/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1937#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1938#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1939/** Enhanced Counter Virtualization is not implemented. */
1940# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1941/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1942# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1943/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1944# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1945/** @} */
1946
1947
1948/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1949 * @{ */
1950/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1951#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1952#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1953/** Hardware update of the Access flag and dirty state are not supported. */
1954# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1955/** Support for hardware update of the Access flag for Block and Page descriptors. */
1956# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1957/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1958# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1959/** Bit 4 - 7 - EL1 Exception level handling. */
1960#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1961#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1962/** VMID bits is 8. */
1963# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1964/** VMID bits is 16 (FEAT_VMID16). */
1965# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1966/** Bit 8 - 11 - Virtualization Host Extensions support. */
1967#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1968#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
1969/** Virtualization Host Extensions are not supported. */
1970# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
1971/** Virtualization Host Extensions are supported. */
1972# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
1973/** Bit 12 - 15 - Hierarchical Permission Disables. */
1974#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1975#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
1976/** Disabling of hierarchical controls not supported. */
1977# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
1978/** Disabling of hierarchical controls supported (FEAT_HPDS). */
1979# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
1980/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
1981# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
1982/** Bit 16 - 19 - LORegions support. */
1983#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1984#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
1985/** LORegions not supported. */
1986# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
1987/** LORegions supported. */
1988# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
1989/** Bit 20 - 23 - Privileged Access Never support. */
1990#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1991#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
1992/** PAN not supported. */
1993# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
1994/** PAN supported (FEAT_PAN). */
1995# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
1996/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
1997# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
1998/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
1999# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2000/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2001#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2002#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2003/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2004# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2005/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2006# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2007/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2008#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2009#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2010/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2011# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2012/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2013# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2014/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2015#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2016#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2017/** Configurable delayed trapping of WFE is not supported. */
2018# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2019/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2020# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2021/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2022#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2023#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2024/** Enhanced Translation Synchronization is not supported. */
2025# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2026/** Enhanced Translation Synchronization is implemented. */
2027# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2028/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2029#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2030#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2031/** HCRX_EL2 and its associated EL3 trap are not supported. */
2032# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2033/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2034# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2035/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2036#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2037#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2038/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2039# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2040/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2041# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2042/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2043#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2044#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2045/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2046# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2047/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2048# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2049/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2050#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2051#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2052/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2053# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2054/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2055# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2056/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2057#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2058#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2059/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2060# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2061/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2062# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2063/* Bit 60 - 63 - Reserved. */
2064/** @} */
2065
2066
2067/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2068 * @{ */
2069/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2070#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2071#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2072/** Common not Private translations are not supported. */
2073# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2074/** Support for Common not Private translations (FEAT_TTNCP). */
2075# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2076/** Bit 4 - 7 - Indicates support for User Access Override. */
2077#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2078#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2079/** User Access Override is not supported. */
2080# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2081/** User Access Override is supported (FEAT_UAO). */
2082# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2083/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2084#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2085#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2086/** LSMAOE and nTLSMD bits are not supported. */
2087# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2088/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2089# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2090/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2091#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2092#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2093/** IESB bit is not supported. */
2094# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2095/** IESB bit is supported (FEAT_IESB). */
2096# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2097/** Bit 16 - 19 - Indicates support for larger virtual address. */
2098#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2099#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2100/** Virtual address range is 48 bits. */
2101# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2102/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2103# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2104/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2105#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2106#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2107/** CCSIDR_EL1 register format is 32-bit. */
2108# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2109/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2110# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2111/** Bit 24 - 27 - Indicates support for nested virtualization. */
2112#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2113#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2114/** Nested virtualization is not supported. */
2115# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2116/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2117# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2118/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2119# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2120/** Bit 28 - 31 - Indicates support for small translation tables. */
2121#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2122#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2123/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2124# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2125/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2126# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2127/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2128#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2129#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2130/** Unaligned single-copy atomicity and atomic functions are not supported. */
2131# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2132/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2133# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2134/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2135#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2136#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2137/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2138# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2139/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2140# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2141/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2142#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2143#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2144/** HCR_EL2.FWB bit is not supported. */
2145# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2146/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2147# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2148/* Bit 44 - 47 - Reserved. */
2149/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2150#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2151#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2152/** TLB maintenance instructions by address have bits [47:44] Res0. */
2153# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2154/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2155# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2156/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2157 * changing block size for a translation. */
2158#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2159#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2160/** Level 0 support for changing block size is supported (FEAT_BBM). */
2161# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2162/** Level 1 support for changing block size is supported (FEAT_BBM). */
2163# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2164/** Level 2 support for changing block size is supported (FEAT_BBM). */
2165# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2166/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2167#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2168#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2169/** Enhanced Virtualization Traps are not supported. */
2170# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2171/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2172# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2173/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2174# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2175/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2176#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2177#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2178/** E0PDx mechanism is not supported. */
2179# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2180/** E0PDx mechanism is supported (FEAT_E0PD). */
2181# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2182/** @} */
2183
2184
2185/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2186 * @{ */
2187/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2188#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2189#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2190/** Armv8 debug architecture version. */
2191# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2192/** Armv8 debug architecture version with virtualization host extensions. */
2193# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2194/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2195# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2196/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2197# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2198/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2199# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2200/** Bit 4 - 7 - Indicates trace support. */
2201#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2202#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2203/** Trace unit System registers not implemented. */
2204# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2205/** Trace unit System registers supported. */
2206# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2207/** Bit 8 - 11 - Performance Monitors Extension version. */
2208#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2209#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2210/** Performance Monitors Extension not supported. */
2211# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2212/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2213# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2214/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2215# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2216/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2217# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2218/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2219# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2220/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2221# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2222/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2223# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2224/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2225#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2226#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2227/* Bit 16 - 19 - Reserved 0. */
2228/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2229#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2230#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2231/* Bit 24 - 27 - Reserved 0. */
2232/** Bit 28 - 31 - Number of context-aware breakpoints. */
2233#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2234#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2235/** Bit 32 - 35 - Statistical Profiling Extension version. */
2236#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2237#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2238/** Statistical Profiling Extension not implemented. */
2239# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2240/** Statistical Profiling Extension supported (FEAT_SPE). */
2241# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2242/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2243# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2244/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2245# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2246/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2247# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2248/** Bit 36 - 39 - OS Double Lock implemented. */
2249#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2250#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2251/** OS Double Lock is not implemented. */
2252# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2253/** OS Double Lock is supported (FEAT_DoubleLock). */
2254# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2255/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2256#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2257#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2258/** Armv8.4 self-hosted Trace Extension not implemented. */
2259# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2260/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2261# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2262/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2263#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2264#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2265/** Trace Buffer Extension is not implemented. */
2266# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2267/** Trace Buffer Extension is supported (FEAT_TRBE). */
2268# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2269/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2270#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2271#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2272/** Multi-threaded PMU extension is not implemented. */
2273# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2274/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2275# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2276/** Multi-threaded PMU extension is not implemented. */
2277# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2278/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2279#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2280#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2281/** Branch Record Buffer extension is not implemented. */
2282# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2283/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2284# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2285/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2286# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2287/* Bit 56 - 59 - Reserved. */
2288/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2289#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2290#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2291/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2292# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2293/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2294# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2295/** @} */
2296
2297
2298#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2299/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2300 * @ingroup grp_rt_armv8
2301 *
2302 * A few inlined functions and macros for assiting in encoding common ARMv8
2303 * instructions.
2304 *
2305 * @{ */
2306
2307/** A64: Official NOP instruction. */
2308#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2309/** A64: Return instruction. */
2310#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2311/** A64: Return instruction with LR pointer authentication using SP and key A. */
2312#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2313/** A64: Return instruction with LR pointer authentication using SP and key B. */
2314#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2315/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2316#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2317/** A64: Insert pointer authentication code into LR using SP and key B. */
2318#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2319/** A64: Insert pointer authentication code into LR using XZR and key B. */
2320#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2321/** A64: Invert the carry flag (PSTATE.C). */
2322#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2323
2324
2325typedef enum
2326{
2327 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2328 * and update the register. */
2329 kArm64InstrStLdPairType_PostIndex = 1,
2330 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2331 * but don't update the register. */
2332 kArm64InstrStLdPairType_Signed = 2,
2333 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2334 * and update the register. */
2335 kArm64InstrStLdPairType_PreIndex = 3
2336} ARM64INSTRSTLDPAIRTYPE;
2337
2338/**
2339 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2340 *
2341 * @returns The encoded instruction.
2342 * @param fLoad true for ldp, false of stp.
2343 * @param u2Opc When @a fSimdFp is @c false:
2344 * - 0 for 32-bit GPRs (Wt).
2345 * - 1 for encoding stgp or ldpsw.
2346 * - 2 for 64-bit GRPs (Xt).
2347 * - 3 illegal.
2348 * When @a fSimdFp is @c true:
2349 * - 0 for 32-bit SIMD&FP registers (St).
2350 * - 1 for 64-bit SIMD&FP registers (Dt).
2351 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2352 * @param enmType The instruction variant wrt addressing and updating of the
2353 * addressing register.
2354 * @param iReg1 The first register to store/load.
2355 * @param iReg2 The second register to store/load.
2356 * @param iBaseReg The base register to use when addressing. SP is allowed.
2357 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2358 * will be multiplied by the register size.
2359 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2360 * stgp/ldpsw instructions.
2361 */
2362DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2363 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2364 bool fSimdFp = false)
2365{
2366 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2367 return (u2Opc << 30)
2368 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2369 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2370 | ((uint32_t)enmType << 23)
2371 | ((uint32_t)fLoad << 22)
2372 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2373 | (iReg2 << 10)
2374 | (iBaseReg << 5)
2375 | iReg1;
2376}
2377
2378
2379/** A64: ldp x1, x2, [x3] */
2380DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2381 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2382 bool f64Bit = true)
2383{
2384 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2385}
2386
2387
2388/** A64: stp x1, x2, [x3] */
2389DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2390 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2391 bool f64Bit = true)
2392{
2393 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2394}
2395
2396
2397typedef enum /* Size VR Opc */
2398{ /* \ | / */
2399 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2400 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2401 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2402 kArmv8A64InstrLdStType_Shift_Size = 8,
2403 kArmv8A64InstrLdStType_Shift_VR = 4,
2404 kArmv8A64InstrLdStType_Shift_Opc = 0,
2405
2406 kArmv8A64InstrLdStType_St_Byte = 0x000,
2407 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2408 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2409 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2410
2411 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2412 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2413 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2414 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2415
2416 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2417 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2418 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2419
2420 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2421 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2422
2423 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2424
2425 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2426 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2427 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2428 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2429
2430 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2431 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2432
2433 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2434 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2435
2436 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2437 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2438
2439} ARMV8A64INSTRLDSTTYPE;
2440/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2441#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2442
2443
2444/**
2445 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2446 *
2447 * @returns The encoded instruction.
2448 * @param u32Opcode The base opcode value.
2449 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2450 * @param iReg The register to load into / store.
2451 * @param iBaseReg The base register to use when addressing. SP is allowed.
2452 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2453 */
2454DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2455 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2456{
2457 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2458 return u32Opcode
2459 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2460 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2461 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2462 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2463 | (iBaseReg << 5)
2464 | iReg;
2465}
2466
2467
2468/**
2469 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2470 *
2471 * @returns The encoded instruction.
2472 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2473 * @param iReg The register to load into / store.
2474 * @param iBaseReg The base register to use when addressing. SP is allowed.
2475 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2476 */
2477DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2478 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2479{
2480 /* 3 2 1 0 */
2481 /* 10987654321098765432109876543210 */
2482 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2483 enmType, iReg, iBaseReg, i9ImmDisp);
2484}
2485
2486/**
2487 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2488 *
2489 * @returns The encoded instruction.
2490 * @param enmType The load/store instruction type. Prefech not valid.
2491 * @param iReg The register to load into / store.
2492 * @param iBaseReg The base register to use when addressing. SP is allowed.
2493 * Written back.
2494 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2495 */
2496DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2497 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2498{
2499 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2500 /* 10987654321098765432109876543210 */
2501 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2502 enmType, iReg, iBaseReg, i9ImmDisp);
2503}
2504
2505/**
2506 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2507 *
2508 * @returns The encoded instruction.
2509 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2510 * @param iReg The register to load into / store.
2511 * @param iBaseReg The base register to use when addressing. SP is allowed.
2512 * Written back.
2513 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2514 */
2515DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2516 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2517{
2518 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2519 /* 10987654321098765432109876543210 */
2520 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2521 enmType, iReg, iBaseReg, i9ImmDisp);
2522}
2523
2524/**
2525 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2526 *
2527 * @returns The encoded instruction.
2528 * @param enmType The load/store instruction type. Prefech not valid,
2529 * nor any SIMD&FP variants.
2530 * @param iReg The register to load into / store.
2531 * @param iBaseReg The base register to use when addressing. SP is allowed.
2532 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2533 */
2534DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2535 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2536{
2537 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2538 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2539 /* 3 2 1 0 */
2540 /* 10987654321098765432109876543210 */
2541 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2542 enmType, iReg, iBaseReg, i9ImmDisp);
2543}
2544
2545
2546/**
2547 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2548 *
2549 * @returns The encoded instruction.
2550 * @param enmType The load/store instruction type. Prefech not valid,
2551 * nor any SIMD&FP variants.
2552 * @param iReg The register to load into / store.
2553 * @param iBaseReg The base register to use when addressing. SP is allowed.
2554 * @param u12ImmDisp Addressing displacement, scaled by size.
2555 */
2556DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2557 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2558{
2559 Assert(u12ImmDisp < 4096U);
2560 Assert(iReg < 32); /* 3 2 1 0 */
2561 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2562 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2563 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2564 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2565 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2566 | (u12ImmDisp << 10)
2567 | (iBaseReg << 5)
2568 | iReg;
2569}
2570
2571typedef enum
2572{
2573 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
2574 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
2575 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
2576 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
2577} ARMV8A64INSTRLDSTEXTEND;
2578
2579/**
2580 * A64: Encodes load/store w/ index register.
2581 *
2582 * @returns The encoded instruction.
2583 * @param enmType The load/store instruction type.
2584 * @param iReg The register to load into / store.
2585 * @param iBaseReg The base register to use when addressing. SP is allowed.
2586 * @param iRegIndex The index register.
2587 * @param enmExtend The extending to apply to @a iRegIndex.
2588 * @param fShifted Whether to shift the index. The shift amount corresponds
2589 * to the access size (thus irrelevant for byte accesses).
2590 */
2591DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2592 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2593 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2594 bool fShifted = false)
2595{
2596 Assert(iRegIndex < 32);
2597 Assert(iReg < 32); /* 3 2 1 0 */
2598 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2599 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2600 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2601 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2602 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2603 | (iRegIndex << 16)
2604 | ((uint32_t)enmExtend << 13)
2605 | ((uint32_t)fShifted << 12)
2606 | (iBaseReg << 5)
2607 | iReg;
2608}
2609
2610typedef enum /* VR Opc */
2611{ /* \ | */
2612 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2613 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2614 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2615 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2616
2617 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
2618 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
2619 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
2620 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
2621
2622 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
2623 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
2624 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2625} ARMV8A64INSTRLDRLITTERAL;
2626
2627
2628/**
2629 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
2630 *
2631 * @returns The encoded instruction.
2632 * @param enmType The load instruction type.
2633 * @param iReg The register to load into.
2634 * @param i19Imm The signed immediate value, multiplied by 4 regardless
2635 * of access size.
2636 */
2637DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2638{
2639 Assert(i19Imm >= -262144 && i19Imm < 262144);
2640 Assert(iReg < 32); /* 3 2 1 0 */
2641 /* 10987654321098765432109876543210 */
2642 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2643 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2644 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2645 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2646 | iReg;
2647}
2648
2649
2650typedef enum
2651{
2652 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
2653 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
2654 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
2655} ARMV8A64INSTRMOVWIDE;
2656
2657/**
2658 * A64: Encode a move wide immediate instruction.
2659 *
2660 * @returns The encoded instruction.
2661 * @param enmType The load instruction type.
2662 * @param iRegDst The register to mov the immediate into.
2663 * @param uImm16 The immediate value.
2664 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2665 * half-words to target:
2666 * - 0 for bits 15:00,
2667 * - 1 for bits 31:16,
2668 * - 2 for bits 47:32 (f64Bit=true only),
2669 * - 3 for bits 63:48 (f64Bit=true only).
2670 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2671 */
2672DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2673 uint32_t iHalfWord = 0, bool f64Bit = true)
2674{
2675 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2676 return ((uint32_t)f64Bit << 31)
2677 | ((uint32_t)enmType << 29)
2678 | UINT32_C(0x12800000)
2679 | (iHalfWord << 21)
2680 | (uImm16 << 5)
2681 | iRegDst;
2682}
2683
2684/** A64: Encodes a MOVN instruction.
2685 * @see Armv8A64MkInstrMovWide for parameter details. */
2686DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2687{
2688 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2689}
2690
2691/** A64: Encodes a MOVZ instruction.
2692 * @see Armv8A64MkInstrMovWide for parameter details. */
2693DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2694{
2695 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2696}
2697
2698/** A64: Encodes a MOVK instruction.
2699 * @see Armv8A64MkInstrMovWide for parameter details. */
2700DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2701{
2702 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2703}
2704
2705
2706typedef enum
2707{
2708 kArmv8A64InstrShift_Lsl = 0,
2709 kArmv8A64InstrShift_Lsr,
2710 kArmv8A64InstrShift_Asr,
2711 kArmv8A64InstrShift_Ror
2712} ARMV8A64INSTRSHIFT;
2713
2714
2715/**
2716 * A64: Encodes a logical instruction with a shifted 2nd register operand.
2717 *
2718 * @returns The encoded instruction.
2719 * @param u2Opc The logical operation to perform.
2720 * @param fNot Whether to complement the 2nd operand.
2721 * @param iRegResult The output register.
2722 * @param iReg1 The 1st register operand.
2723 * @param iReg2Shifted The 2nd register operand, to which the optional
2724 * shifting is applied.
2725 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2726 * GPRs.
2727 * @param offShift6 The shift amount (default: none).
2728 * @param enmShift The shift operation (default: LSL).
2729 */
2730DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2731 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2732 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2733{
2734 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2735 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2736 return ((uint32_t)f64Bit << 31)
2737 | (u2Opc << 29)
2738 | UINT32_C(0x0a000000)
2739 | ((uint32_t)enmShift << 22)
2740 | ((uint32_t)fNot << 21)
2741 | (iReg2Shifted << 16)
2742 | (offShift6 << 10)
2743 | (iReg1 << 5)
2744 | iRegResult;
2745}
2746
2747
2748/** A64: Encodes an AND instruction.
2749 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2750DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2751 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2752{
2753 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2754}
2755
2756
2757/** A64: Encodes an BIC instruction.
2758 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2759DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2760 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2761{
2762 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2763}
2764
2765
2766/** A64: Encodes an ORR instruction.
2767 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2768DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2769 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2770{
2771 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2772}
2773
2774
2775/** A64: Encodes an MOV instruction.
2776 * This is an alias for "orr dst, xzr, src". */
2777DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2778{
2779 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2780}
2781
2782
2783/** A64: Encodes an ORN instruction.
2784 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2785DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2786 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2787{
2788 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2789}
2790
2791
2792/** A64: Encodes an EOR instruction.
2793 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2794DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2795 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2796{
2797 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2798}
2799
2800
2801/** A64: Encodes an EON instruction.
2802 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2803DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2804 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2805{
2806 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2807}
2808
2809
2810/** A64: Encodes an ANDS instruction.
2811 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2812DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2813 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2814{
2815 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2816}
2817
2818
2819/** A64: Encodes an BICS instruction.
2820 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2821DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2822 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2823{
2824 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2825}
2826
2827
2828
2829/*
2830 * Data processing instructions with two source register operands.
2831 */
2832
2833
2834/** A64: Encodes an SUBP instruction. */
2835DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2836{
2837 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2838 return UINT32_C(0x80000000)
2839 | UINT32_C(0x1ac00000)
2840 | (UINT32_C(0) << 10)
2841 | (iRegSubtrahend << 16)
2842 | (iRegMinuend << 5)
2843 | iRegResult;
2844}
2845
2846
2847/** A64: Encodes an SUBPS instruction. */
2848DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2849{
2850 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2851 return UINT32_C(0x80000000)
2852 | UINT32_C(0x20000000)
2853 | UINT32_C(0x1ac00000)
2854 | (UINT32_C(0) << 10)
2855 | (iRegSubtrahend << 16)
2856 | (iRegMinuend << 5)
2857 | iRegResult;
2858}
2859
2860
2861/** A64: Encodes an UDIV instruction. */
2862DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2863{
2864 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2865 return ((uint32_t)f64Bit << 31)
2866 | UINT32_C(0x1ac00000)
2867 | (UINT32_C(2) << 10)
2868 | (iRegDivisor << 16)
2869 | (iRegDividend << 5)
2870 | iRegResult;
2871}
2872
2873
2874/** A64: Encodes an SDIV instruction. */
2875DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2876{
2877 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2878 return ((uint32_t)f64Bit << 31)
2879 | UINT32_C(0x1ac00000)
2880 | (UINT32_C(3) << 10)
2881 | (iRegDivisor << 16)
2882 | (iRegDividend << 5)
2883 | iRegResult;
2884}
2885
2886
2887/** A64: Encodes an IRG instruction. */
2888DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2889{
2890 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2891 return UINT32_C(0x80000000)
2892 | UINT32_C(0x1ac00000)
2893 | (UINT32_C(4) << 10)
2894 | (iRegSrc2 << 16)
2895 | (iRegSrc1 << 5)
2896 | iRegResult;
2897}
2898
2899
2900/** A64: Encodes a GMI instruction. */
2901DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2902{
2903 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2904 return UINT32_C(0x80000000)
2905 | UINT32_C(0x1ac00000)
2906 | (UINT32_C(5) << 10)
2907 | (iRegSrc2 << 16)
2908 | (iRegSrc1 << 5)
2909 | iRegResult;
2910}
2911
2912
2913/** A64: Encodes an LSLV instruction. */
2914DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2915{
2916 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2917 return ((uint32_t)f64Bit << 31)
2918 | UINT32_C(0x1ac00000)
2919 | (UINT32_C(8) << 10)
2920 | (iRegCount << 16)
2921 | (iRegSrc << 5)
2922 | iRegResult;
2923}
2924
2925
2926/** A64: Encodes an LSRV instruction. */
2927DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2928{
2929 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2930 return ((uint32_t)f64Bit << 31)
2931 | UINT32_C(0x1ac00000)
2932 | (UINT32_C(9) << 10)
2933 | (iRegCount << 16)
2934 | (iRegSrc << 5)
2935 | iRegResult;
2936}
2937
2938
2939/** A64: Encodes an ASRV instruction. */
2940DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2941{
2942 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2943 return ((uint32_t)f64Bit << 31)
2944 | UINT32_C(0x1ac00000)
2945 | (UINT32_C(10) << 10)
2946 | (iRegCount << 16)
2947 | (iRegSrc << 5)
2948 | iRegResult;
2949}
2950
2951
2952/** A64: Encodes a RORV instruction. */
2953DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2954{
2955 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2956 return ((uint32_t)f64Bit << 31)
2957 | UINT32_C(0x1ac00000)
2958 | (UINT32_C(11) << 10)
2959 | (iRegCount << 16)
2960 | (iRegSrc << 5)
2961 | iRegResult;
2962}
2963
2964
2965/** A64: Encodes a PACGA instruction. */
2966DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2967{
2968 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2969 return UINT32_C(0x80000000)
2970 | UINT32_C(0x1ac00000)
2971 | (UINT32_C(12) << 10)
2972 | (iRegSrc2 << 16)
2973 | (iRegSrc1 << 5)
2974 | iRegResult;
2975}
2976
2977
2978/** A64: Encodes a CRC32* instruction. */
2979DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
2980{
2981 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
2982 return ((uint32_t)(uSize == 3) << 31)
2983 | UINT32_C(0x1ac00000)
2984 | (UINT32_C(16) << 10)
2985 | (uSize << 10)
2986 | (iRegValue << 16)
2987 | (iRegCrc << 5)
2988 | iRegResult;
2989}
2990
2991
2992/** A64: Encodes a CRC32B instruction. */
2993DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
2994{
2995 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
2996}
2997
2998
2999/** A64: Encodes a CRC32H instruction. */
3000DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3001{
3002 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3003}
3004
3005
3006/** A64: Encodes a CRC32W instruction. */
3007DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3008{
3009 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3010}
3011
3012
3013/** A64: Encodes a CRC32X instruction. */
3014DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3015{
3016 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3017}
3018
3019
3020/** A64: Encodes a CRC32C* instruction. */
3021DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3022{
3023 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3024 return ((uint32_t)(uSize == 3) << 31)
3025 | UINT32_C(0x1ac00000)
3026 | (UINT32_C(20) << 10)
3027 | (uSize << 10)
3028 | (iRegValue << 16)
3029 | (iRegCrc << 5)
3030 | iRegResult;
3031}
3032
3033
3034/** A64: Encodes a CRC32B instruction. */
3035DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3036{
3037 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3038}
3039
3040
3041/** A64: Encodes a CRC32CH instruction. */
3042DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3043{
3044 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3045}
3046
3047
3048/** A64: Encodes a CRC32CW instruction. */
3049DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3050{
3051 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3052}
3053
3054
3055/** A64: Encodes a CRC32CX instruction. */
3056DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3057{
3058 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3059}
3060
3061
3062/** A64: Encodes an SMAX instruction. */
3063DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3064{
3065 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3066 return ((uint32_t)f64Bit << 31)
3067 | UINT32_C(0x1ac00000)
3068 | (UINT32_C(24) << 10)
3069 | (iRegSrc2 << 16)
3070 | (iRegSrc1 << 5)
3071 | iRegResult;
3072}
3073
3074
3075/** A64: Encodes an UMAX instruction. */
3076DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3077{
3078 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3079 return ((uint32_t)f64Bit << 31)
3080 | UINT32_C(0x1ac00000)
3081 | (UINT32_C(25) << 10)
3082 | (iRegSrc2 << 16)
3083 | (iRegSrc1 << 5)
3084 | iRegResult;
3085}
3086
3087
3088/** A64: Encodes an SMIN instruction. */
3089DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3090{
3091 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3092 return ((uint32_t)f64Bit << 31)
3093 | UINT32_C(0x1ac00000)
3094 | (UINT32_C(26) << 10)
3095 | (iRegSrc2 << 16)
3096 | (iRegSrc1 << 5)
3097 | iRegResult;
3098}
3099
3100
3101/** A64: Encodes an UMIN instruction. */
3102DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3103{
3104 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3105 return ((uint32_t)f64Bit << 31)
3106 | UINT32_C(0x1ac00000)
3107 | (UINT32_C(27) << 10)
3108 | (iRegSrc2 << 16)
3109 | (iRegSrc1 << 5)
3110 | iRegResult;
3111}
3112
3113
3114# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3115
3116/**
3117 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3118 *
3119 * @returns The decoded mask.
3120 * @param uImm6SizeLen The immS value from the instruction. (No N part
3121 * here, as that must be zero for instructions
3122 * operating on 32-bit wide registers.)
3123 * @param uImm6Rotations The immR value from the instruction.
3124 */
3125DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3126{
3127 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3128
3129 /* Determine the element size. */
3130 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3131 Assert(cBitsElementLog2 + 1U != 0U);
3132
3133 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3134 Assert(uImm6Rotations < cBitsElement);
3135
3136 /* Extract the number of bits set to 1: */
3137 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3138 Assert(cBitsSetTo1 < cBitsElement);
3139 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3140
3141 /* Produce the unrotated pattern. */
3142 static const uint32_t s_auReplicate[]
3143 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3144 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3145
3146 /* Rotate it and return. */
3147 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3148}
3149
3150
3151/**
3152 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3153 *
3154 * @returns The decoded mask.
3155 * @param uImm7SizeLen The N:immS value from the instruction.
3156 * @param uImm6Rotations The immR value from the instruction.
3157 */
3158DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3159{
3160 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3161
3162 /* Determine the element size. */
3163 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3164 Assert(cBitsElementLog2 + 1U != 0U);
3165
3166 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3167 Assert(uImm6Rotations < cBitsElement);
3168
3169 /* Extract the number of bits set to 1: */
3170 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3171 Assert(cBitsSetTo1 < cBitsElement);
3172 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3173
3174 /* Produce the unrotated pattern. */
3175 static const uint64_t s_auReplicate[]
3176 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3177 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3178
3179 /* Rotate it and return. */
3180 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3181}
3182
3183
3184/**
3185 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3186 * the immS value.
3187 */
3188DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3189{
3190 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3191}
3192
3193
3194/**
3195 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3196 * 32-bit bitmask to a set of immediates for those instructions.
3197 *
3198 * @returns true if successful, false if not.
3199 * @param fMask The mask value to convert.
3200 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3201 * 32-bit wide masks).
3202 * @param puImm6Rotations Where to return the immR.
3203 */
3204DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3205{
3206 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3207 if ((uint32_t)(fMask + 1U) <= 1)
3208 return false;
3209
3210 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3211 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3212 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3213 if (cRor)
3214 fMask = ASMRotateRightU32(fMask, cRor);
3215 else
3216 fMask = ASMRotateLeftU32(fMask, cRol);
3217 Assert(fMask & RT_BIT_32(0));
3218 Assert(!(fMask & RT_BIT_32(31)));
3219
3220 /* Count the trailing ones and leading zeros. */
3221 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3222 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3223
3224 /* The potential element length is then the sum of the two above. */
3225 unsigned const cBitsElement = cOnes + cZeros;
3226 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3227 return false;
3228
3229 /* Special case: 32 bits element size. Since we're done here. */
3230 if (cBitsElement == 32)
3231 *puImm6SizeLen = cOnes - 1;
3232 else
3233 {
3234 /* Extract the element bits and check that these are replicated in the whole pattern. */
3235 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3236 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3237
3238 static const uint32_t s_auReplicate[]
3239 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3240 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3241 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3242 else
3243 return false;
3244 }
3245 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3246
3247 return true;
3248}
3249
3250
3251/**
3252 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3253 * 64-bit bitmask to a set of immediates for those instructions.
3254 *
3255 * @returns true if successful, false if not.
3256 * @param fMask The mask value to convert.
3257 * @param puImm7SizeLen Where to return the N:immS part.
3258 * @param puImm6Rotations Where to return the immR.
3259 */
3260DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3261{
3262 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3263 if ((uint64_t)(fMask + 1U) <= 1)
3264 return false;
3265
3266 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3267 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3268 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3269 if (cRor)
3270 fMask = ASMRotateRightU64(fMask, cRor);
3271 else
3272 fMask = ASMRotateLeftU64(fMask, cRol);
3273 Assert(fMask & RT_BIT_64(0));
3274 Assert(!(fMask & RT_BIT_64(63)));
3275
3276 /* Count the trailing ones and leading zeros. */
3277 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3278 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3279
3280 /* The potential element length is then the sum of the two above. */
3281 unsigned const cBitsElement = cOnes + cZeros;
3282 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3283 return false;
3284
3285 /* Special case: 64 bits element size. Since we're done here. */
3286 if (cBitsElement == 64)
3287 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
3288 else
3289 {
3290 /* Extract the element bits and check that these are replicated in the whole pattern. */
3291 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3292 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3293
3294 static const uint64_t s_auReplicate[]
3295 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3296 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3297 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3298 else
3299 return false;
3300 }
3301 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3302
3303 return true;
3304}
3305
3306# endif /* IPRT_INCLUDED_asm_h */
3307
3308/**
3309 * A64: Encodes a logical instruction with an complicated immediate mask.
3310 *
3311 * The @a uImm7SizeLen parameter specifies two things:
3312 * 1. the element size and
3313 * 2. the number of bits set to 1 in the pattern.
3314 *
3315 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3316 * top) and using the position of the first bit set as a power of two.
3317 *
3318 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
3319 * |---|---|---|---|---|---|---|--------------|
3320 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
3321 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
3322 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
3323 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
3324 * | 0 | 0 | x | x | x | x | x | 32 bits |
3325 * | 1 | x | x | x | x | x | x | 64 bits |
3326 *
3327 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3328 * there is always one zero bit in the pattern).
3329 *
3330 * The @a uImm6Rotations parameter specifies how many bits to the right,
3331 * the element pattern is rotated. The rotation count must be less than the
3332 * element bit count (size).
3333 *
3334 * @returns The encoded instruction.
3335 * @param u2Opc The logical operation to perform.
3336 * @param iRegResult The output register.
3337 * @param iRegSrc The 1st register operand.
3338 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3339 * field at the top of the 6-bit 'imms' field.
3340 *
3341 * @param uImm6Rotations The rotation count.
3342 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3343 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3344 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3345 */
3346DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3347 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3348{
3349 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3350 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3351 return ((uint32_t)f64Bit << 31)
3352 | (u2Opc << 29)
3353 | UINT32_C(0x12000000)
3354 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3355 | (uImm6Rotations << 16)
3356 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3357 | (iRegSrc << 5)
3358 | iRegResult;
3359}
3360
3361
3362/** A64: Encodes an AND instruction w/ complicated immediate mask.
3363 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3364DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3365 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3366{
3367 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3368}
3369
3370
3371/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3372 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3373DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3374 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3375{
3376 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3377}
3378
3379
3380/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3381 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3382DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3383 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3384{
3385 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3386}
3387
3388
3389/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3390 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3391DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3392 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3393{
3394 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3395}
3396
3397
3398/** A64: Encodes an TST instruction w/ complicated immediate mask.
3399 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3400DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3401 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3402{
3403 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3404}
3405
3406
3407/**
3408 * A64: Encodes a bitfield instruction.
3409 *
3410 * @returns The encoded instruction.
3411 * @param u2Opc The bitfield operation to perform.
3412 * @param iRegResult The output register.
3413 * @param iRegSrc The 1st register operand.
3414 * @param cImm6Ror The right rotation count.
3415 * @param uImm6S The leftmost bit to be moved.
3416 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3417 * @param uN1 This must match @a f64Bit for all instructions
3418 * currently specified.
3419 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3420 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3421 */
3422DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3423 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3424{
3425 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3426 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3427 return ((uint32_t)f64Bit << 31)
3428 | (u2Opc << 29)
3429 | UINT32_C(0x13000000)
3430 | (uN1 << 22)
3431 | (cImm6Ror << 16)
3432 | (uImm6S << 10)
3433 | (iRegSrc << 5)
3434 | iRegResult;
3435}
3436
3437
3438/** A64: Encodes a SBFM instruction.
3439 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3440DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3441 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3442{
3443 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3444}
3445
3446
3447/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3448 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3449DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3450{
3451 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3452}
3453
3454
3455/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3456 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3457DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3458{
3459 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3460}
3461
3462
3463/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3464 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3465DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3466{
3467 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3468}
3469
3470
3471/** A64: Encodes an ASR instruction w/ immediate shift value.
3472 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3473DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3474{
3475 uint32_t const cWidth = f64Bit ? 63 : 31;
3476 Assert(cShift > 0); Assert(cShift <= cWidth);
3477 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3478}
3479
3480
3481/** A64: Encodes a BFM instruction.
3482 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3483DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3484 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3485{
3486 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3487}
3488
3489
3490/** A64: Encodes a BFI instruction (insert).
3491 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3492DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3493 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3494{
3495 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3496 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3497 cBitsWidth - 1, f64Bit);
3498}
3499
3500
3501/** A64: Encodes a BFXIL instruction (insert low).
3502 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3503DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
3504 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3505{
3506 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3507 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
3508 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3509}
3510
3511
3512/** A64: Encodes an UBFM instruction.
3513 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3514DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3515 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3516{
3517 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3518}
3519
3520
3521/** A64: Encodes an UBFX instruction (zero extending extract).
3522 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3523DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3524 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3525{
3526 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3527}
3528
3529
3530/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3531 * shifted into destination).
3532 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3533DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3534 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3535{
3536 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3537 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3538}
3539
3540
3541/** A64: Encodes an LSL instruction w/ immediate shift value.
3542 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3543DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3544{
3545 uint32_t const cWidth = f64Bit ? 63 : 31;
3546 Assert(cShift > 0); Assert(cShift <= cWidth);
3547 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3548 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
3549}
3550
3551
3552/** A64: Encodes an LSR instruction w/ immediate shift value.
3553 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3554DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3555{
3556 uint32_t const cWidth = f64Bit ? 63 : 31;
3557 Assert(cShift > 0); Assert(cShift <= cWidth);
3558 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3559}
3560
3561
3562/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3563 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3564DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3565{
3566 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3567}
3568
3569
3570/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3571 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3572DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3573{
3574 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3575}
3576
3577
3578/**
3579 * A64: Encodes an EXTR instruction with an immediate.
3580 *
3581 * @returns The encoded instruction.
3582 * @param iRegResult The register to store the result in. ZR is valid.
3583 * @param iRegLow The register holding the least significant bits in the
3584 * extraction. ZR is valid.
3585 * @param iRegHigh The register holding the most significant bits in the
3586 * extraction. ZR is valid.
3587 * @param uLsb The bit number of the least significant bit, or where in
3588 * @a iRegLow to start the
3589 * extraction.
3590 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3591 */
3592DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3593 bool f64Bit = true)
3594{
3595 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3596 return ((uint32_t)f64Bit << 31)
3597 | UINT32_C(0x13800000)
3598 | ((uint32_t)f64Bit << 22) /*N*/
3599 | (iRegHigh << 16)
3600 | (uLsb << 10)
3601 | (iRegLow << 5)
3602 | iRegResult;
3603}
3604
3605
3606/** A64: Rotates the value of a register (alias for EXTR). */
3607DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3608{
3609 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3610}
3611
3612
3613/**
3614 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3615 *
3616 * @returns The encoded instruction.
3617 * @param fSub true for sub and subs, false for add and
3618 * adds.
3619 * @param iRegResult The register to store the result in.
3620 * SP is valid when @a fSetFlags = false,
3621 * and ZR is valid otherwise.
3622 * @param iRegSrc The register containing the augend (@a fSub
3623 * = false) or minuend (@a fSub = true). SP is
3624 * a valid registers for all variations.
3625 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3626 * (@a fSub = true).
3627 * @param f64Bit true for 64-bit GRPs (default), false for
3628 * 32-bit GPRs.
3629 * @param fSetFlags Whether to set flags (adds / subs) or not
3630 * (add / sub - default).
3631 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3632 * bits to the left, or not (default).
3633 */
3634DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3635 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3636 bool fSetFlags = false, bool fShift12 = false)
3637{
3638 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3639 return ((uint32_t)f64Bit << 31)
3640 | ((uint32_t)fSub << 30)
3641 | ((uint32_t)fSetFlags << 29)
3642 | UINT32_C(0x11000000)
3643 | ((uint32_t)fShift12 << 22)
3644 | (uImm12AddendSubtrahend << 10)
3645 | (iRegSrc << 5)
3646 | iRegResult;
3647}
3648
3649
3650/** Alias for sub zxr, reg, \#uimm12. */
3651DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3652 bool f64Bit = true, bool fShift12 = false)
3653{
3654 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3655 f64Bit, true /*fSetFlags*/, fShift12);
3656}
3657
3658
3659/** ADD dst, src, \#uimm12 */
3660DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3661 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3662{
3663 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3664}
3665
3666
3667/** SUB dst, src, \#uimm12 */
3668DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3669 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3670{
3671 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3672}
3673
3674
3675/**
3676 * A64: Encodes either add, adds, sub or subs with shifted register.
3677 *
3678 * @returns The encoded instruction.
3679 * @param fSub true for sub and subs, false for add and
3680 * adds.
3681 * @param iRegResult The register to store the result in.
3682 * SP is NOT valid, but ZR is.
3683 * @param iRegSrc1 The register containing the augend (@a fSub
3684 * = false) or minuend (@a fSub = true).
3685 * SP is NOT valid, but ZR is.
3686 * @param iRegSrc2 The register containing the addened (@a fSub
3687 * = false) or subtrahend (@a fSub = true).
3688 * SP is NOT valid, but ZR is.
3689 * @param f64Bit true for 64-bit GRPs (default), false for
3690 * 32-bit GPRs.
3691 * @param fSetFlags Whether to set flags (adds / subs) or not
3692 * (add / sub - default).
3693 * @param cShift The shift count to apply to @a iRegSrc2.
3694 * @param enmShift The shift type to apply to the @a iRegSrc2
3695 * register. kArmv8A64InstrShift_Ror is
3696 * reserved.
3697 */
3698DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3699 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3700 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3701{
3702 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3703 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3704
3705 return ((uint32_t)f64Bit << 31)
3706 | ((uint32_t)fSub << 30)
3707 | ((uint32_t)fSetFlags << 29)
3708 | UINT32_C(0x0b000000)
3709 | ((uint32_t)enmShift << 22)
3710 | (iRegSrc2 << 16)
3711 | (cShift << 10)
3712 | (iRegSrc1 << 5)
3713 | iRegResult;
3714}
3715
3716
3717/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3718DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3719 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3720{
3721 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3722 f64Bit, true /*fSetFlags*/, cShift, enmShift);
3723}
3724
3725
3726/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3727DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3728 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3729 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3730{
3731 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3732}
3733
3734
3735/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3736DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3737 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3738 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3739{
3740 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3741}
3742
3743
3744/** NEG dst */
3745DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3746{
3747 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3748}
3749
3750
3751/** Extension option for 'extended register' instructions. */
3752typedef enum ARMV8A64INSTREXTEND
3753{
3754 kArmv8A64InstrExtend_UxtB = 0,
3755 kArmv8A64InstrExtend_UxtH,
3756 kArmv8A64InstrExtend_UxtW,
3757 kArmv8A64InstrExtend_UxtX,
3758 kArmv8A64InstrExtend_SxtB,
3759 kArmv8A64InstrExtend_SxtH,
3760 kArmv8A64InstrExtend_SxtW,
3761 kArmv8A64InstrExtend_SxtX,
3762 /** The default is either UXTW or UXTX depending on whether the instruction
3763 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3764 * to the f64Bit value. */
3765 kArmv8A64InstrExtend_Default
3766} ARMV8A64INSTREXTEND;
3767
3768
3769/**
3770 * A64: Encodes either add, adds, sub or subs with extended register encoding.
3771 *
3772 * @returns The encoded instruction.
3773 * @param fSub true for sub and subs, false for add and
3774 * adds.
3775 * @param iRegResult The register to store the result in.
3776 * SP is NOT valid, but ZR is.
3777 * @param iRegSrc1 The register containing the augend (@a fSub
3778 * = false) or minuend (@a fSub = true).
3779 * SP is valid, but ZR is NOT.
3780 * @param iRegSrc2 The register containing the addened (@a fSub
3781 * = false) or subtrahend (@a fSub = true).
3782 * SP is NOT valid, but ZR is.
3783 * @param f64Bit true for 64-bit GRPs (default), false for
3784 * 32-bit GPRs.
3785 * @param fSetFlags Whether to set flags (adds / subs) or not
3786 * (add / sub - default).
3787 * @param enmExtend The type of extension to apply to @a
3788 * iRegSrc2.
3789 * @param cShift The left shift count to apply to @a iRegSrc2
3790 * after enmExtend processing is done.
3791 * Max shift is 4 for some reason.
3792 */
3793DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3794 bool f64Bit = true, bool fSetFlags = false,
3795 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3796 uint32_t cShift = 0)
3797{
3798 if (enmExtend == kArmv8A64InstrExtend_Default)
3799 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3800 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3801
3802 return ((uint32_t)f64Bit << 31)
3803 | ((uint32_t)fSub << 30)
3804 | ((uint32_t)fSetFlags << 29)
3805 | UINT32_C(0x0b200000)
3806 | (iRegSrc2 << 16)
3807 | ((uint32_t)enmExtend << 13)
3808 | (cShift << 10)
3809 | (iRegSrc1 << 5)
3810 | iRegResult;
3811}
3812
3813
3814/**
3815 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
3816 *
3817 * @returns The encoded instruction.
3818 * @param fSub true for sbc and sbcs, false for adc and
3819 * adcs.
3820 * @param iRegResult The register to store the result in. SP is
3821 * NOT valid, but ZR is.
3822 * @param iRegSrc1 The register containing the augend (@a fSub
3823 * = false) or minuend (@a fSub = true).
3824 * SP is NOT valid, but ZR is.
3825 * @param iRegSrc2 The register containing the addened (@a fSub
3826 * = false) or subtrahend (@a fSub = true).
3827 * SP is NOT valid, but ZR is.
3828 * @param f64Bit true for 64-bit GRPs (default), false for
3829 * 32-bit GPRs.
3830 * @param fSetFlags Whether to set flags (adds / subs) or not
3831 * (add / sub - default).
3832 */
3833DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3834 bool f64Bit = true, bool fSetFlags = false)
3835{
3836 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3837
3838 return ((uint32_t)f64Bit << 31)
3839 | ((uint32_t)fSub << 30)
3840 | ((uint32_t)fSetFlags << 29)
3841 | UINT32_C(0x1a000000)
3842 | (iRegSrc2 << 16)
3843 | (iRegSrc1 << 5)
3844 | iRegResult;
3845}
3846
3847
3848/** ADC dst, reg1, reg2 */
3849DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3850 bool f64Bit = true, bool fSetFlags = false)
3851{
3852 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3853}
3854
3855
3856/** ADCS dst, reg1, reg2 */
3857DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3858{
3859 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
3860}
3861
3862
3863/** SBC dst, reg1, reg2 */
3864DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3865 bool f64Bit = true, bool fSetFlags = false)
3866{
3867 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3868}
3869
3870
3871/** SBCS dst, reg1, reg2 */
3872DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3873{
3874 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
3875}
3876
3877
3878/**
3879 * A64: Encodes a B (unconditional branch w/ imm) instruction.
3880 *
3881 * @returns The encoded instruction.
3882 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3883 */
3884DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
3885{
3886 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
3887 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
3888}
3889
3890
3891/**
3892 * A64: Encodes a BL (unconditional call w/ imm) instruction.
3893 *
3894 * @returns The encoded instruction.
3895 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3896 */
3897DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
3898{
3899 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
3900}
3901
3902
3903/**
3904 * A64: Encodes a BR (unconditional branch w/ register) instruction.
3905 *
3906 * @returns The encoded instruction.
3907 * @param iReg The register containing the target address.
3908 */
3909DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
3910{
3911 Assert(iReg < 32);
3912 return UINT32_C(0xd61f0000) | (iReg << 5);
3913}
3914
3915
3916/**
3917 * A64: Encodes a BLR instruction.
3918 *
3919 * @returns The encoded instruction.
3920 * @param iReg The register containing the target address.
3921 */
3922DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
3923{
3924 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
3925}
3926
3927
3928/**
3929 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
3930 *
3931 * @returns The encoded instruction.
3932 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3933 * its not zero.
3934 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3935 * @param iReg The GPR to check for zero / non-zero value.
3936 * @param f64Bit true for 64-bit register, false for 32-bit.
3937 */
3938DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3939{
3940 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
3941 return ((uint32_t)f64Bit << 31)
3942 | UINT32_C(0x34000000)
3943 | ((uint32_t)fJmpIfNotZero << 24)
3944 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3945 | iReg;
3946}
3947
3948
3949/** A64: Encodes the CBZ instructions. */
3950DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3951{
3952 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
3953}
3954
3955
3956/** A64: Encodes the CBNZ instructions. */
3957DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3958{
3959 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
3960}
3961
3962
3963/**
3964 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
3965 *
3966 * @returns The encoded instruction.
3967 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3968 * its not zero.
3969 * @param iImm14 Signed number of instruction to jump (i.e. *4).
3970 * @param iReg The GPR to check for zero / non-zero value.
3971 * @param iBitNo The bit to test for.
3972 */
3973DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
3974{
3975 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
3976 return ((uint32_t)(iBitNo & 0x20) << (31-5))
3977 | UINT32_C(0x36000000)
3978 | ((uint32_t)fJmpIfNotZero << 24)
3979 | ((iBitNo & 0x1f) << 19)
3980 | (((uint32_t)iImm14 & 0x3fff) << 5)
3981 | iReg;
3982}
3983
3984
3985
3986/** Armv8 Condition codes. */
3987typedef enum ARMV8INSTRCOND
3988{
3989 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
3990 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
3991
3992 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
3993 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
3994 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
3995 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
3996
3997 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
3998 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
3999
4000 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4001 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4002
4003 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4004 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4005
4006 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4007 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4008
4009 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4010 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4011
4012 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4013 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4014} ARMV8INSTRCOND;
4015
4016/**
4017 * A64: Encodes conditional branch instruction w/ immediate target.
4018 *
4019 * @returns The encoded instruction.
4020 * @param enmCond The branch condition.
4021 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4022 */
4023DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4024{
4025 Assert((unsigned)enmCond < 16);
4026 return UINT32_C(0x54000000)
4027 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4028 | (uint32_t)enmCond;
4029}
4030
4031
4032/**
4033 * A64: Encodes the BRK instruction.
4034 *
4035 * @returns The encoded instruction.
4036 * @param uImm16 Unsigned immediate value.
4037 */
4038DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4039{
4040 Assert(uImm16 < _64K);
4041 return UINT32_C(0xd4200000)
4042 | (uImm16 << 5);
4043}
4044
4045/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4046 * @{ */
4047#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4048#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4049#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4050#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4051#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4052#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4053#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4054#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4055
4056#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4057#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4058#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4059#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4060#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4061#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4062#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4063#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4064/** @} */
4065
4066/**
4067 * A64: Encodes CCMP or CCMN with two register operands.
4068 *
4069 * @returns The encoded instruction.
4070 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4071 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4072 * @param fNzcv The N, Z, C & V flags values to load if the condition
4073 * does not match. See RMA64_NZCV_F_XXX.
4074 * @param enmCond The condition guarding the compare.
4075 * @param fCCmp Set for CCMP (default), clear for CCMN.
4076 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4077 */
4078DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4079 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4080{
4081 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4082
4083 return ((uint32_t)f64Bit << 31)
4084 | ((uint32_t)fCCmp << 30)
4085 | UINT32_C(0x3a400000)
4086 | (iRegSrc2 << 16)
4087 | ((uint32_t)enmCond << 12)
4088 | (iRegSrc1 << 5)
4089 | fNzcv;
4090}
4091
4092/** CCMP w/ reg. */
4093DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4094 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4095{
4096 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4097}
4098
4099
4100/** CCMN w/ reg. */
4101DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4102 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4103{
4104 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4105}
4106
4107
4108/**
4109 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4110 *
4111 * @returns The encoded instruction.
4112 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4113 * @param uImm5 The immediate, to compare iRegSrc with.
4114 * @param fNzcv The N, Z, C & V flags values to load if the condition
4115 * does not match. See RMA64_NZCV_F_XXX.
4116 * @param enmCond The condition guarding the compare.
4117 * @param fCCmp Set for CCMP (default), clear for CCMN.
4118 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4119 */
4120DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4121 bool fCCmp = true, bool f64Bit = true)
4122{
4123 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4124
4125 return ((uint32_t)f64Bit << 31)
4126 | ((uint32_t)fCCmp << 30)
4127 | UINT32_C(0x3a400800)
4128 | (uImm5 << 16)
4129 | ((uint32_t)enmCond << 12)
4130 | (iRegSrc << 5)
4131 | fNzcv;
4132}
4133
4134/** CCMP w/ immediate. */
4135DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4136 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4137{
4138 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4139}
4140
4141
4142/** CCMN w/ immediate. */
4143DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4144 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4145{
4146 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4147}
4148
4149
4150/**
4151 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4152 *
4153 * @returns The encoded instruction.
4154 * @param uOp Opcode bit 30.
4155 * @param uOp2 Opcode bits 11:10.
4156 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4157 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4158 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4159 * @param enmCond The condition guarding the compare.
4160 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4161 */
4162DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4163 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4164{
4165 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4166
4167 return ((uint32_t)f64Bit << 31)
4168 | (uOp << 30)
4169 | UINT32_C(0x1a800000)
4170 | (iRegSrc2 << 16)
4171 | ((uint32_t)enmCond << 12)
4172 | (uOp2 << 10)
4173 | (iRegSrc1 << 5)
4174 | iRegResult;
4175}
4176
4177
4178/** A64: Encodes CSEL.
4179 * @see Armv8A64MkInstrCondSelect for details. */
4180DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4181 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4182{
4183 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4184}
4185
4186
4187/** A64: Encodes CSINC.
4188 * @see Armv8A64MkInstrCondSelect for details. */
4189DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4190 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4191{
4192 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4193}
4194
4195
4196/** A64: Encodes CSET.
4197 * @see Armv8A64MkInstrCondSelect for details. */
4198DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4199{
4200 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4201 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4202 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4203}
4204
4205
4206/** A64: Encodes CSINV.
4207 * @see Armv8A64MkInstrCondSelect for details. */
4208DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4209 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4210{
4211 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4212}
4213
4214/** A64: Encodes CSETM.
4215 * @see Armv8A64MkInstrCondSelect for details. */
4216DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4217{
4218 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4219 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4220 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4221}
4222
4223
4224/** A64: Encodes CSNEG.
4225 * @see Armv8A64MkInstrCondSelect for details. */
4226DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4227 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4228{
4229 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4230}
4231
4232
4233/**
4234 * A64: Encodes REV instruction.
4235 *
4236 * @returns The encoded instruction.
4237 * @param iRegDst The destination register. SP is NOT valid.
4238 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4239 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4240 */
4241DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4242{
4243 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4244
4245 return ((uint32_t)f64Bit << 31)
4246 | UINT32_C(0x5ac00800)
4247 | ((uint32_t)f64Bit << 10)
4248 | (iRegSrc << 5)
4249 | iRegDst;
4250}
4251
4252
4253/**
4254 * A64: Encodes REV16 instruction.
4255 *
4256 * @returns The encoded instruction.
4257 * @param iRegDst The destination register. SP is NOT valid.
4258 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4259 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4260 */
4261DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4262{
4263 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4264
4265 return ((uint32_t)f64Bit << 31)
4266 | UINT32_C(0x5ac00400)
4267 | (iRegSrc << 5)
4268 | iRegDst;
4269}
4270
4271
4272/**
4273 * A64: Encodes SETF8 & SETF16.
4274 *
4275 * @returns The encoded instruction.
4276 * @param iRegResult The register holding the result. SP is NOT valid.
4277 * @param f16Bit Set for SETF16, clear for SETF8.
4278 */
4279DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4280{
4281 Assert(iRegResult < 32);
4282
4283 return UINT32_C(0x3a00080d)
4284 | ((uint32_t)f16Bit << 14)
4285 | (iRegResult << 5);
4286}
4287
4288
4289/**
4290 * A64: Encodes RMIF.
4291 *
4292 * @returns The encoded instruction.
4293 * @param iRegSrc The source register to get flags from.
4294 * @param cRotateRight The right rotate count (LSB bit offset).
4295 * @param fMask Mask of which flag bits to set:
4296 * - bit 0: V
4297 * - bit 1: C
4298 * - bit 2: Z
4299 * - bit 3: N
4300 */
4301DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4302{
4303 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4304
4305 return UINT32_C(0xba000400)
4306 | (cRotateRight << 15)
4307 | (iRegSrc << 5)
4308 | fMask;
4309}
4310
4311
4312/**
4313 * A64: Encodes MRS (for reading a system register into a GPR).
4314 *
4315 * @returns The encoded instruction.
4316 * @param iRegDst The register to put the result into. SP is NOT valid.
4317 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4318 * IPRT specific format, of the register to read.
4319 */
4320DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4321{
4322 Assert(iRegDst < 32);
4323 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4324
4325 /* Note. The top bit of idSysReg must always be set and is also set in
4326 0xd5300000, otherwise we'll be encoding a different instruction. */
4327 return UINT32_C(0xd5300000)
4328 | (idSysReg << 5)
4329 | iRegDst;
4330}
4331
4332
4333/**
4334 * A64: Encodes MSR (for writing a GPR to a system register).
4335 *
4336 * @returns The encoded instruction.
4337 * @param iRegSrc The register which value to write. SP is NOT valid.
4338 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4339 * IPRT specific format, of the register to write.
4340 */
4341DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4342{
4343 Assert(iRegSrc < 32);
4344 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4345
4346 /* Note. The top bit of idSysReg must always be set and is also set in
4347 0xd5100000, otherwise we'll be encoding a different instruction. */
4348 return UINT32_C(0xd5100000)
4349 | (idSysReg << 5)
4350 | iRegSrc;
4351}
4352
4353
4354/** @} */
4355
4356
4357/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4358 * @ingroup grp_rt_armv8_mkinstr
4359 *
4360 * A few inlined functions and macros for assisting in encoding common ARMv8
4361 * Neon/SIMD instructions.
4362 *
4363 * @{ */
4364
4365/**
4366 * A64: Encodes ORR (vector, register).
4367 *
4368 * @returns The encoded instruction.
4369 * @param iVecRegDst The vector register to put the result into.
4370 * @param iVecRegSrc1 The 1st source register.
4371 * @param iVecRegSrc2 The 2nd source register.
4372 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4373 * or just the low 64-bit (false).
4374 */
4375DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4376 bool f128Bit = true)
4377{
4378 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4379
4380 return UINT32_C(0x0ea01c00)
4381 | ((uint32_t)f128Bit << 30)
4382 | (iVecRegSrc2 << 16)
4383 | (iVecRegSrc1 << 5)
4384 | iVecRegDst;
4385}
4386
4387
4388/**
4389 * A64: Encodes EOR (vector, register).
4390 *
4391 * @returns The encoded instruction.
4392 * @param iVecRegDst The vector register to put the result into.
4393 * @param iVecRegSrc1 The 1st source register.
4394 * @param iVecRegSrc2 The 2nd source register.
4395 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4396 * or just the low 64-bit (false).
4397 */
4398DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4399 bool f128Bit = true)
4400{
4401 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4402
4403 return UINT32_C(0x2e201c00)
4404 | ((uint32_t)f128Bit << 30)
4405 | (iVecRegSrc2 << 16)
4406 | (iVecRegSrc1 << 5)
4407 | iVecRegDst;
4408}
4409
4410
4411/**
4412 * A64: Encodes AND (vector, register).
4413 *
4414 * @returns The encoded instruction.
4415 * @param iVecRegDst The vector register to put the result into.
4416 * @param iVecRegSrc1 The 1st source register.
4417 * @param iVecRegSrc2 The 2nd source register.
4418 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4419 * or just the low 64-bit (false).
4420 */
4421DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4422 bool f128Bit = true)
4423{
4424 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4425
4426 return UINT32_C(0x0e201c00)
4427 | ((uint32_t)f128Bit << 30)
4428 | (iVecRegSrc2 << 16)
4429 | (iVecRegSrc1 << 5)
4430 | iVecRegDst;
4431}
4432
4433
4434/** Armv8 UMOV/INS vector element size. */
4435typedef enum ARMV8INSTRUMOVINSSZ
4436{
4437 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
4438 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
4439 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
4440 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
4441} ARMV8INSTRUMOVINSSZ;
4442
4443
4444/**
4445 * A64: Encodes UMOV (vector, register).
4446 *
4447 * @returns The encoded instruction.
4448 * @param iRegDst The register to put the result into.
4449 * @param iVecRegSrc The vector source register.
4450 * @param idxElem The element index.
4451 * @param enmSz Element size of the source vector register.
4452 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
4453 */
4454DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
4455 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
4456{
4457 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
4458 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
4459 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4460 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4461 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4462 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4463
4464 return UINT32_C(0x0e003c00)
4465 | ((uint32_t)fDst64Bit << 30)
4466 | ((uint32_t)idxElem << (16 + enmSz + 1))
4467 | (RT_BIT_32(enmSz) << 16)
4468 | (iVecRegSrc << 5)
4469 | iRegDst;
4470}
4471
4472
4473/**
4474 * A64: Encodes INS (vector, register).
4475 *
4476 * @returns The encoded instruction.
4477 * @param iVecRegDst The vector register to put the result into.
4478 * @param iRegSrc The source register.
4479 * @param idxElem The element index for the destination.
4480 * @param enmSz Element size of the source vector register.
4481 *
4482 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4483 */
4484DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
4485 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
4486{
4487 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4488 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4489 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4490 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4491 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4492
4493 return UINT32_C(0x4e001c00)
4494 | ((uint32_t)idxElem << (16 + enmSz + 1))
4495 | (RT_BIT_32(enmSz) << 16)
4496 | (iRegSrc << 5)
4497 | iVecRegDst;
4498}
4499
4500
4501/**
4502 * A64: Encodes DUP (vector, register).
4503 *
4504 * @returns The encoded instruction.
4505 * @param iVecRegDst The vector register to put the result into.
4506 * @param iRegSrc The source register (ZR is valid).
4507 * @param enmSz Element size of the source vector register.
4508 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
4509 * just the low 64-bit (false).
4510 *
4511 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4512 */
4513DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
4514 bool f128Bit = true)
4515{
4516 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4517 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
4518 || (enmSz == kArmv8InstrUmovInsSz_U16)
4519 || (enmSz == kArmv8InstrUmovInsSz_U32)
4520 || (enmSz == kArmv8InstrUmovInsSz_U64));
4521
4522 return UINT32_C(0x0e000c00)
4523 | ((uint32_t)f128Bit << 30)
4524 | (RT_BIT_32(enmSz) << 16)
4525 | (iRegSrc << 5)
4526 | iVecRegDst;
4527}
4528
4529
4530/** Armv8 vector compare to zero vector element size. */
4531typedef enum ARMV8INSTRVECCMPZEROSZ
4532{
4533 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
4534 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
4535 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
4536 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
4537} ARMV8INSTRVECCMPZEROSZ;
4538
4539
4540/** Armv8 vector compare to zero vector operation. */
4541typedef enum ARMV8INSTRVECCMPZEROOP
4542{
4543 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
4544 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
4545 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
4546 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
4547} ARMV8INSTRVECCMPZEROOP;
4548
4549
4550/**
4551 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
4552 *
4553 * @returns The encoded instruction.
4554 * @param iVecRegDst The vector register to put the result into.
4555 * @param iVecRegSrc The vector source register.
4556 * @param enmSz Vector element size.
4557 * @param enmOp The compare operation against to encode.
4558 */
4559DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
4560 ARMV8INSTRVECCMPZEROOP enmOp)
4561{
4562 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4563
4564 return UINT32_C(0x5e208800)
4565 | ((uint32_t)enmSz << 22)
4566 | (RT_BIT_32(enmSz) << 16)
4567 | (iVecRegSrc << 5)
4568 | iVecRegDst
4569 | (uint32_t)enmOp;
4570}
4571
4572
4573/**
4574 * A64: Encodes CNT (vector, register).
4575 *
4576 * @returns The encoded instruction.
4577 * @param iVecRegDst The vector register to put the result into.
4578 * @param iVecRegSrc The vector source register.
4579 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4580 * or just the low 64-bit (false).
4581 */
4582DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
4583{
4584 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4585
4586 return UINT32_C(0x0e205800)
4587 | ((uint32_t)f128Bit << 30)
4588 | (iVecRegSrc << 5)
4589 | iVecRegDst;
4590}
4591
4592
4593/** Armv8 vector unsigned sum long across vector element size. */
4594typedef enum ARMV8INSTRVECUADDLVSZ
4595{
4596 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
4597 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
4598 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
4599 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
4600 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
4601} ARMV8INSTRVECUADDLVSZ;
4602
4603
4604/**
4605 * A64: Encodes UADDLV (vector, register).
4606 *
4607 * @returns The encoded instruction.
4608 * @param iVecRegDst The vector register to put the result into.
4609 * @param iVecRegSrc The vector source register.
4610 * @param enmSz Element size.
4611 */
4612DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
4613{
4614 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4615
4616 return UINT32_C(0x2e303800)
4617 | ((uint32_t)enmSz)
4618 | (iVecRegSrc << 5)
4619 | iVecRegDst;
4620}
4621
4622
4623/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
4624typedef enum ARMV8INSTRUSHIFTSZ
4625{
4626 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
4627 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
4628 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
4629 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
4630} ARMV8INSTRUSHIFTSZ;
4631
4632/**
4633 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
4634 *
4635 * @returns The encoded instruction.
4636 * @param iVecRegDst The vector register to put the result into.
4637 * @param iVecRegSrc The vector source register.
4638 * @param cShift Number of bits to shift.
4639 * @param enmSz Element size.
4640 * @param fUnsigned Flag whether this a signed or unsigned shift,
4641 * @param fRound Flag whether this is the rounding shift variant.
4642 * @param fAccum Flag whether this is the accumulate shift variant.
4643 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4644 * or just the low 64-bit (false).
4645 */
4646DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4647 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
4648{
4649 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4650 Assert( cShift >= 1
4651 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
4652 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
4653 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
4654 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
4655
4656 return UINT32_C(0x0f000400)
4657 | ((uint32_t)f128Bit << 30)
4658 | ((uint32_t)fUnsigned << 29)
4659 | ((((uint32_t)enmSz << 1) - cShift) << 16)
4660 | ((uint32_t)fRound << 13)
4661 | ((uint32_t)fAccum << 12)
4662 | (iVecRegSrc << 5)
4663 | iVecRegDst;
4664}
4665
4666
4667/**
4668 * A64: Encodes SHL (vector, register).
4669 *
4670 * @returns The encoded instruction.
4671 * @param iVecRegDst The vector register to put the result into.
4672 * @param iVecRegSrc The vector source register.
4673 * @param cShift Number of bits to shift.
4674 * @param enmSz Element size.
4675 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4676 * or just the low 64-bit (false).
4677 */
4678DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4679 bool f128Bit = true)
4680{
4681 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4682 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
4683 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
4684 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
4685 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
4686
4687 return UINT32_C(0x0f005400)
4688 | ((uint32_t)f128Bit << 30)
4689 | (((uint32_t)enmSz | cShift) << 16)
4690 | (iVecRegSrc << 5)
4691 | iVecRegDst;
4692}
4693
4694
4695/** Armv8 vector arith ops element size. */
4696typedef enum ARMV8INSTRVECARITHSZ
4697{
4698 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
4699 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
4700 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
4701 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
4702} ARMV8INSTRVECARITHSZ;
4703
4704/**
4705 * A64: Encodes ADD/SUB (vector, register).
4706 *
4707 * @returns The encoded instruction.
4708 * @param fSub Flag whther this is an addition (false) or subtraction (true) instruction.
4709 * @param iVecRegDst The vector register to put the result into.
4710 * @param iVecRegSrc1 The first vector source register.
4711 * @param iVecRegSrc2 The second vector source register.
4712 * @param enmSz Element size.
4713 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4714 * or just the low 64-bit (false).
4715 */
4716DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAddSub(bool fSub, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4717 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4718{
4719 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4720
4721 return UINT32_C(0x0e208400)
4722 | ((uint32_t)f128Bit << 30)
4723 | ((uint32_t)fSub << 29)
4724 | ((uint32_t)enmSz << 22)
4725 | (iVecRegSrc2 << 16)
4726 | (iVecRegSrc1 << 5)
4727 | iVecRegDst;
4728}
4729
4730
4731/** Armv8 vector compare operation. */
4732typedef enum ARMV8VECINSTRCMPOP
4733{
4734 /* U insn[15:10] */
4735 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
4736 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
4737 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
4738 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
4739 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
4740} ARMV8VECINSTRCMPOP;
4741
4742/**
4743 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
4744 *
4745 * @returns The encoded instruction.
4746 * @param enmOp The operation to perform.
4747 * @param iVecRegDst The vector register to put the result into.
4748 * @param iVecRegSrc1 The first vector source register.
4749 * @param iVecRegSrc2 The second vector source register.
4750 * @param enmSz Element size.
4751 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4752 * or just the low 64-bit (false).
4753 */
4754DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4755 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4756{
4757 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4758
4759 return UINT32_C(0x0e200000)
4760 | ((uint32_t)f128Bit << 30)
4761 | ((uint32_t)enmSz << 22)
4762 | (iVecRegSrc2 << 16)
4763 | ((uint32_t)enmOp)
4764 | (iVecRegSrc1 << 5)
4765 | iVecRegDst;
4766}
4767
4768
4769/** Armv8 vector compare against zero operation. */
4770typedef enum ARMV8VECINSTRCMPZEROOP
4771{
4772 /* U insn[15:10] */
4773 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
4774 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
4775 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
4776 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
4777 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
4778} ARMV8VECINSTRCMPZEROOP;
4779
4780/**
4781 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
4782 *
4783 * @returns The encoded instruction.
4784 * @param enmOp The operation to perform.
4785 * @param iVecRegDst The vector register to put the result into.
4786 * @param iVecRegSrc The first vector source register.
4787 * @param enmSz Element size.
4788 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4789 * or just the low 64-bit (false).
4790 */
4791DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
4792 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4793{
4794 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4795
4796 return UINT32_C(0x0e200000)
4797 | ((uint32_t)f128Bit << 30)
4798 | ((uint32_t)enmSz << 22)
4799 | ((uint32_t)enmOp)
4800 | (iVecRegSrc << 5)
4801 | iVecRegDst;
4802}
4803
4804/** @} */
4805
4806#endif /* !dtrace && __cplusplus */
4807
4808/** @} */
4809
4810#endif /* !IPRT_INCLUDED_armv8_h */
4811
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