VirtualBox

source: vbox/trunk/include/iprt/armv8.h

Last change on this file was 104398, checked in by vboxsync, 3 weeks ago

iprt/armv8.h: Some more system register definitions, bugref:10391
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1/** @file
2 * IPRT - ARMv8 (AArch64 and AArch32) Structures and Definitions.
3 */
4
5/*
6 * Copyright (C) 2023 Oracle and/or its affiliates.
7 *
8 * This file is part of VirtualBox base platform packages, as
9 * available from https://www.virtualbox.org.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation, in version 3 of the
14 * License.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <https://www.gnu.org/licenses>.
23 *
24 * The contents of this file may alternatively be used under the terms
25 * of the Common Development and Distribution License Version 1.0
26 * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
27 * in the VirtualBox distribution, in which case the provisions of the
28 * CDDL are applicable instead of those of the GPL.
29 *
30 * You may elect to license modified versions of this file under the
31 * terms and conditions of either the GPL or the CDDL or both.
32 *
33 * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
34 */
35
36#ifndef IPRT_INCLUDED_armv8_h
37#define IPRT_INCLUDED_armv8_h
38#ifndef RT_WITHOUT_PRAGMA_ONCE
39# pragma once
40#endif
41
42#ifndef VBOX_FOR_DTRACE_LIB
43# include <iprt/cdefs.h>
44# ifndef RT_IN_ASSEMBLER
45# include <iprt/types.h>
46# include <iprt/assert.h>
47# endif
48# include <iprt/assertcompile.h>
49#else
50# pragma D depends_on library vbox-types.d
51#endif
52
53/** @defgroup grp_rt_armv8 ARMv8 Types and Definitions
54 * @ingroup grp_rt
55 * @{
56 */
57
58/** @name The AArch64 register encoding - deprecated.
59 * @deprecated Use ARMV8_A64_REG_XXX instead.
60 * @todo correct code and drop these remaining ones.
61 * @{ */
62#define ARMV8_AARCH64_REG_X0 0
63#define ARMV8_AARCH64_REG_X1 1
64#define ARMV8_AARCH64_REG_X2 2
65#define ARMV8_AARCH64_REG_X3 3
66#define ARMV8_AARCH64_REG_ZR 31
67/** @} */
68
69/** @name The AArch64 general purpose register encoding.
70 * @{ */
71#define ARMV8_A64_REG_X0 0
72#define ARMV8_A64_REG_X1 1
73#define ARMV8_A64_REG_X2 2
74#define ARMV8_A64_REG_X3 3
75#define ARMV8_A64_REG_X4 4
76#define ARMV8_A64_REG_X5 5
77#define ARMV8_A64_REG_X6 6
78#define ARMV8_A64_REG_X7 7
79#define ARMV8_A64_REG_X8 8
80#define ARMV8_A64_REG_X9 9
81#define ARMV8_A64_REG_X10 10
82#define ARMV8_A64_REG_X11 11
83#define ARMV8_A64_REG_X12 12
84#define ARMV8_A64_REG_X13 13
85#define ARMV8_A64_REG_X14 14
86#define ARMV8_A64_REG_X15 15
87#define ARMV8_A64_REG_X16 16
88#define ARMV8_A64_REG_X17 17
89#define ARMV8_A64_REG_X18 18
90#define ARMV8_A64_REG_X19 19
91#define ARMV8_A64_REG_X20 20
92#define ARMV8_A64_REG_X21 21
93#define ARMV8_A64_REG_X22 22
94#define ARMV8_A64_REG_X23 23
95#define ARMV8_A64_REG_X24 24
96#define ARMV8_A64_REG_X25 25
97#define ARMV8_A64_REG_X26 26
98#define ARMV8_A64_REG_X27 27
99#define ARMV8_A64_REG_X28 28
100#define ARMV8_A64_REG_X29 29
101#define ARMV8_A64_REG_X30 30
102/** @} */
103
104/** @name The AArch64 32-bit general purpose register names.
105 * @{ */
106#define ARMV8_A64_REG_W0 ARMV8_A64_REG_X0
107#define ARMV8_A64_REG_W1 ARMV8_A64_REG_X1
108#define ARMV8_A64_REG_W2 ARMV8_A64_REG_X2
109#define ARMV8_A64_REG_W3 ARMV8_A64_REG_X3
110#define ARMV8_A64_REG_W4 ARMV8_A64_REG_X4
111#define ARMV8_A64_REG_W5 ARMV8_A64_REG_X5
112#define ARMV8_A64_REG_W6 ARMV8_A64_REG_X6
113#define ARMV8_A64_REG_W7 ARMV8_A64_REG_X7
114#define ARMV8_A64_REG_W8 ARMV8_A64_REG_X8
115#define ARMV8_A64_REG_W9 ARMV8_A64_REG_X9
116#define ARMV8_A64_REG_W10 ARMV8_A64_REG_X10
117#define ARMV8_A64_REG_W11 ARMV8_A64_REG_X11
118#define ARMV8_A64_REG_W12 ARMV8_A64_REG_X12
119#define ARMV8_A64_REG_W13 ARMV8_A64_REG_X13
120#define ARMV8_A64_REG_W14 ARMV8_A64_REG_X14
121#define ARMV8_A64_REG_W15 ARMV8_A64_REG_X15
122#define ARMV8_A64_REG_W16 ARMV8_A64_REG_X16
123#define ARMV8_A64_REG_W17 ARMV8_A64_REG_X17
124#define ARMV8_A64_REG_W18 ARMV8_A64_REG_X18
125#define ARMV8_A64_REG_W19 ARMV8_A64_REG_X19
126#define ARMV8_A64_REG_W20 ARMV8_A64_REG_X20
127#define ARMV8_A64_REG_W21 ARMV8_A64_REG_X21
128#define ARMV8_A64_REG_W22 ARMV8_A64_REG_X22
129#define ARMV8_A64_REG_W23 ARMV8_A64_REG_X23
130#define ARMV8_A64_REG_W24 ARMV8_A64_REG_X24
131#define ARMV8_A64_REG_W25 ARMV8_A64_REG_X25
132#define ARMV8_A64_REG_W26 ARMV8_A64_REG_X26
133#define ARMV8_A64_REG_W27 ARMV8_A64_REG_X27
134#define ARMV8_A64_REG_W28 ARMV8_A64_REG_X28
135#define ARMV8_A64_REG_W29 ARMV8_A64_REG_X29
136#define ARMV8_A64_REG_W30 ARMV8_A64_REG_X30
137/** @} */
138
139/** @name The AArch64 NEON scalar register encoding.
140 * @{ */
141#define ARMV8_A64_REG_Q0 0
142#define ARMV8_A64_REG_Q1 1
143#define ARMV8_A64_REG_Q2 2
144#define ARMV8_A64_REG_Q3 3
145#define ARMV8_A64_REG_Q4 4
146#define ARMV8_A64_REG_Q5 5
147#define ARMV8_A64_REG_Q6 6
148#define ARMV8_A64_REG_Q7 7
149#define ARMV8_A64_REG_Q8 8
150#define ARMV8_A64_REG_Q9 9
151#define ARMV8_A64_REG_Q10 10
152#define ARMV8_A64_REG_Q11 11
153#define ARMV8_A64_REG_Q12 12
154#define ARMV8_A64_REG_Q13 13
155#define ARMV8_A64_REG_Q14 14
156#define ARMV8_A64_REG_Q15 15
157#define ARMV8_A64_REG_Q16 16
158#define ARMV8_A64_REG_Q17 17
159#define ARMV8_A64_REG_Q18 18
160#define ARMV8_A64_REG_Q19 19
161#define ARMV8_A64_REG_Q20 20
162#define ARMV8_A64_REG_Q21 21
163#define ARMV8_A64_REG_Q22 22
164#define ARMV8_A64_REG_Q23 23
165#define ARMV8_A64_REG_Q24 24
166#define ARMV8_A64_REG_Q25 25
167#define ARMV8_A64_REG_Q26 26
168#define ARMV8_A64_REG_Q27 27
169#define ARMV8_A64_REG_Q28 28
170#define ARMV8_A64_REG_Q29 29
171#define ARMV8_A64_REG_Q30 30
172#define ARMV8_A64_REG_Q31 31
173/** @} */
174
175/** @name The AArch64 NEON vector register encoding.
176 * @{ */
177#define ARMV8_A64_REG_V0 ARMV8_A64_REG_Q0
178#define ARMV8_A64_REG_V1 ARMV8_A64_REG_Q1
179#define ARMV8_A64_REG_V2 ARMV8_A64_REG_Q2
180#define ARMV8_A64_REG_V3 ARMV8_A64_REG_Q3
181#define ARMV8_A64_REG_V4 ARMV8_A64_REG_Q4
182#define ARMV8_A64_REG_V5 ARMV8_A64_REG_Q5
183#define ARMV8_A64_REG_V6 ARMV8_A64_REG_Q6
184#define ARMV8_A64_REG_V7 ARMV8_A64_REG_Q7
185#define ARMV8_A64_REG_V8 ARMV8_A64_REG_Q8
186#define ARMV8_A64_REG_V9 ARMV8_A64_REG_Q9
187#define ARMV8_A64_REG_V10 ARMV8_A64_REG_Q10
188#define ARMV8_A64_REG_V11 ARMV8_A64_REG_Q11
189#define ARMV8_A64_REG_V12 ARMV8_A64_REG_Q12
190#define ARMV8_A64_REG_V13 ARMV8_A64_REG_Q13
191#define ARMV8_A64_REG_V14 ARMV8_A64_REG_Q14
192#define ARMV8_A64_REG_V15 ARMV8_A64_REG_Q15
193#define ARMV8_A64_REG_V16 ARMV8_A64_REG_Q16
194#define ARMV8_A64_REG_V17 ARMV8_A64_REG_Q17
195#define ARMV8_A64_REG_V18 ARMV8_A64_REG_Q18
196#define ARMV8_A64_REG_V19 ARMV8_A64_REG_Q19
197#define ARMV8_A64_REG_V20 ARMV8_A64_REG_Q20
198#define ARMV8_A64_REG_V21 ARMV8_A64_REG_Q21
199#define ARMV8_A64_REG_V22 ARMV8_A64_REG_Q22
200#define ARMV8_A64_REG_V23 ARMV8_A64_REG_Q23
201#define ARMV8_A64_REG_V24 ARMV8_A64_REG_Q24
202#define ARMV8_A64_REG_V25 ARMV8_A64_REG_Q25
203#define ARMV8_A64_REG_V26 ARMV8_A64_REG_Q26
204#define ARMV8_A64_REG_V27 ARMV8_A64_REG_Q27
205#define ARMV8_A64_REG_V28 ARMV8_A64_REG_Q28
206#define ARMV8_A64_REG_V29 ARMV8_A64_REG_Q29
207#define ARMV8_A64_REG_V30 ARMV8_A64_REG_Q30
208#define ARMV8_A64_REG_V31 ARMV8_A64_REG_Q31
209/** @} */
210
211/** @name The AArch64 register 31.
212 * @note Register 31 typically refers to the zero register, but can also in
213 * select case (by instruction and opecode field) refer the to stack
214 * pointer of the current exception level. ARM typically uses \<Xn|SP\>
215 * to indicate that register 31 is taken as SP, if just \<Xn\> is used
216 * 31 will be the zero register.
217 * @{ */
218/** The stack pointer. */
219#define ARMV8_A64_REG_SP 31
220/** The zero register. Reads as zero, writes ignored. */
221#define ARMV8_A64_REG_XZR 31
222/** The zero register, the 32-bit register name. */
223#define ARMV8_A64_REG_WZR ARMV8_A64_REG_XZR
224/** @} */
225
226/** @name AArch64 register aliases
227 * @{ */
228/** The link register is typically mapped to x30 as that's the default pick of
229 * the RET instruction. */
230#define ARMV8_A64_REG_LR ARMV8_A64_REG_X30
231/** Frame base pointer is typically mapped to x29. */
232#define ARMV8_A64_REG_BP ARMV8_A64_REG_X29
233/** @} */
234
235
236/** @name System register encoding.
237 * @{
238 */
239/** Mask for the op0 part of an MSR/MRS instruction */
240#define ARMV8_AARCH64_SYSREG_OP0_MASK (RT_BIT_32(19) | RT_BIT_32(20))
241/** Shift for the op0 part of an MSR/MRS instruction */
242#define ARMV8_AARCH64_SYSREG_OP0_SHIFT 19
243/** Returns the op0 part of the given MRS/MSR instruction. */
244#define ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP0_MASK) >> ARMV8_AARCH64_SYSREG_OP0_SHIFT)
245/** Mask for the op1 part of an MSR/MRS instruction */
246#define ARMV8_AARCH64_SYSREG_OP1_MASK (RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18))
247/** Shift for the op1 part of an MSR/MRS instruction */
248#define ARMV8_AARCH64_SYSREG_OP1_SHIFT 16
249/** Returns the op1 part of the given MRS/MSR instruction. */
250#define ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP1_MASK) >> ARMV8_AARCH64_SYSREG_OP1_SHIFT)
251/** Mask for the CRn part of an MSR/MRS instruction */
252#define ARMV8_AARCH64_SYSREG_CRN_MASK ( RT_BIT_32(12) | RT_BIT_32(13) | RT_BIT_32(14) \
253 | RT_BIT_32(15) )
254/** Shift for the CRn part of an MSR/MRS instruction */
255#define ARMV8_AARCH64_SYSREG_CRN_SHIFT 12
256/** Returns the CRn part of the given MRS/MSR instruction. */
257#define ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRN_MASK) >> ARMV8_AARCH64_SYSREG_CRN_SHIFT)
258/** Mask for the CRm part of an MSR/MRS instruction */
259#define ARMV8_AARCH64_SYSREG_CRM_MASK ( RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) \
260 | RT_BIT_32(11) )
261/** Shift for the CRm part of an MSR/MRS instruction */
262#define ARMV8_AARCH64_SYSREG_CRM_SHIFT 8
263/** Returns the CRn part of the given MRS/MSR instruction. */
264#define ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_CRM_MASK) >> ARMV8_AARCH64_SYSREG_CRM_SHIFT)
265/** Mask for the op2 part of an MSR/MRS instruction */
266#define ARMV8_AARCH64_SYSREG_OP2_MASK (RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7))
267/** Shift for the op2 part of an MSR/MRS instruction */
268#define ARMV8_AARCH64_SYSREG_OP2_SHIFT 5
269/** Returns the op2 part of the given MRS/MSR instruction. */
270#define ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn) (((a_MsrMrsInsn) & ARMV8_AARCH64_SYSREG_OP2_MASK) >> ARMV8_AARCH64_SYSREG_OP2_SHIFT)
271/** Mask for all system register encoding relevant fields in an MRS/MSR instruction. */
272#define ARMV8_AARCH64_SYSREG_MASK ( ARMV8_AARCH64_SYSREG_OP0_MASK | ARMV8_AARCH64_SYSREG_OP1_MASK \
273 | ARMV8_AARCH64_SYSREG_CRN_MASK | ARMV8_AARCH64_SYSREG_CRN_MASK \
274 | ARMV8_AARCH64_SYSREG_OP2_MASK)
275/** @} */
276
277/** @name Mapping of op0:op1:CRn:CRm:op2 to a system register ID. This is
278 * IPRT specific and not part of the ARMv8 specification.
279 * @{ */
280#define ARMV8_AARCH64_SYSREG_ID_CREATE(a_Op0, a_Op1, a_CRn, a_CRm, a_Op2) \
281 UINT16_C( (((a_Op0) & 0x3) << 14) \
282 | (((a_Op1) & 0x7) << 11) \
283 | (((a_CRn) & 0xf) << 7) \
284 | (((a_CRm) & 0xf) << 3) \
285 | ((a_Op2) & 0x7))
286/** Returns the internal system register ID from the given MRS/MSR instruction. */
287#define ARMV8_AARCH64_SYSREG_ID_FROM_MRS_MSR(a_MsrMrsInsn) \
288 ARMV8_AARCH64_SYSREG_ID_CREATE(ARMV8_AARCH64_SYSREG_OP0_GET(a_MsrMrsInsn), \
289 ARMV8_AARCH64_SYSREG_OP1_GET(a_MsrMrsInsn), \
290 ARMV8_AARCH64_SYSREG_CRN_GET(a_MsrMrsInsn), \
291 ARMV8_AARCH64_SYSREG_CRM_GET(a_MsrMrsInsn), \
292 ARMV8_AARCH64_SYSREG_OP2_GET(a_MsrMrsInsn))
293/** Encodes the given system register ID in the given MSR/MRS instruction. */
294#define ARMV8_AARCH64_SYSREG_ID_ENCODE_IN_MRS_MSR(a_MsrMrsInsn, a_SysregId) \
295 ((a_MsrMrsInsn) = ((a_MsrMrsInsn) & ~ARMV8_AARCH64_SYSREG_MASK) | (a_SysregId << ARMV8_AARCH64_SYSREG_OP2_SHIFT))
296/** @} */
297
298
299/** @name System register IDs.
300 * @{ */
301/** MDCCINT_EL1 register - RW. */
302#define ARMV8_AARCH64_SYSREG_MDCCINT_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 0, 2, 0)
303/** OSLAR_EL1 register - WO. */
304#define ARMV8_AARCH64_SYSREG_OSLAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 0, 4)
305/** OSLSR_EL1 register - RO. */
306#define ARMV8_AARCH64_SYSREG_OSLSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 1, 4)
307/** OSDLR_EL1 register - RW. */
308#define ARMV8_AARCH64_SYSREG_OSDLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(2, 0, 1, 3, 4)
309
310/** MIDR_EL1 register - RO. */
311#define ARMV8_AARCH64_SYSREG_MIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 0)
312/** MIPDR_EL1 register - RO. */
313#define ARMV8_AARCH64_SYSREG_MPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 5)
314/** REVIDR_EL1 register - RO. */
315#define ARMV8_AARCH64_SYSREG_REVIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 0, 6)
316/** ID_PFR0_EL1 register - RO. */
317#define ARMV8_AARCH64_SYSREG_ID_PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 0)
318/** ID_PFR1_EL1 register - RO. */
319#define ARMV8_AARCH64_SYSREG_ID_PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 1)
320/** ID_DFR0_EL1 register - RO. */
321#define ARMV8_AARCH64_SYSREG_ID_DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 2)
322/** ID_AFR0_EL1 register - RO. */
323#define ARMV8_AARCH64_SYSREG_ID_AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 3)
324/** ID_MMFR0_EL1 register - RO. */
325#define ARMV8_AARCH64_SYSREG_ID_MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 4)
326/** ID_MMFR1_EL1 register - RO. */
327#define ARMV8_AARCH64_SYSREG_ID_MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 5)
328/** ID_MMFR2_EL1 register - RO. */
329#define ARMV8_AARCH64_SYSREG_ID_MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 6)
330/** ID_MMFR3_EL1 register - RO. */
331#define ARMV8_AARCH64_SYSREG_ID_MMFR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 1, 7)
332
333/** ID_ISAR0_EL1 register - RO. */
334#define ARMV8_AARCH64_SYSREG_ID_ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 0)
335/** ID_ISAR1_EL1 register - RO. */
336#define ARMV8_AARCH64_SYSREG_ID_ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 1)
337/** ID_ISAR2_EL1 register - RO. */
338#define ARMV8_AARCH64_SYSREG_ID_ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 2)
339/** ID_ISAR3_EL1 register - RO. */
340#define ARMV8_AARCH64_SYSREG_ID_ISAR3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 3)
341/** ID_ISAR4_EL1 register - RO. */
342#define ARMV8_AARCH64_SYSREG_ID_ISAR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 4)
343/** ID_ISAR5_EL1 register - RO. */
344#define ARMV8_AARCH64_SYSREG_ID_ISAR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 5)
345/** ID_MMFR4_EL1 register - RO. */
346#define ARMV8_AARCH64_SYSREG_ID_MMFR4_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 6)
347/** ID_ISAR6_EL1 register - RO. */
348#define ARMV8_AARCH64_SYSREG_ID_ISAR6_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 2, 7)
349
350/** MVFR0_EL1 register - RO. */
351#define ARMV8_AARCH64_SYSREG_MVFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 0)
352/** MVFR1_EL1 register - RO. */
353#define ARMV8_AARCH64_SYSREG_MVFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 1)
354/** MVFR2_EL1 register - RO. */
355#define ARMV8_AARCH64_SYSREG_MVFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 2)
356/** ID_PFR2_EL1 register - RO. */
357#define ARMV8_AARCH64_SYSREG_ID_PFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 4)
358/** ID_DFR1_EL1 register - RO. */
359#define ARMV8_AARCH64_SYSREG_ID_DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 5)
360/** ID_MMFR5_EL1 register - RO. */
361#define ARMV8_AARCH64_SYSREG_ID_MMFR5_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 3, 6)
362
363/** ID_AA64PFR0_EL1 register - RO. */
364#define ARMV8_AARCH64_SYSREG_ID_AA64PFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 0)
365/** ID_AA64PFR0_EL1 register - RO. */
366#define ARMV8_AARCH64_SYSREG_ID_AA64PFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 1)
367/** ID_AA64ZFR0_EL1 register - RO. */
368#define ARMV8_AARCH64_SYSREG_ID_AA64ZFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 4)
369/** ID_AA64SMFR0_EL1 register - RO. */
370#define ARMV8_AARCH64_SYSREG_ID_AA64SMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 4, 5)
371
372/** ID_AA64DFR0_EL1 register - RO. */
373#define ARMV8_AARCH64_SYSREG_ID_AA64DFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 0)
374/** ID_AA64DFR0_EL1 register - RO. */
375#define ARMV8_AARCH64_SYSREG_ID_AA64DFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 1)
376/** ID_AA64AFR0_EL1 register - RO. */
377#define ARMV8_AARCH64_SYSREG_ID_AA64AFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 4)
378/** ID_AA64AFR1_EL1 register - RO. */
379#define ARMV8_AARCH64_SYSREG_ID_AA64AFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 5, 5)
380
381/** ID_AA64ISAR0_EL1 register - RO. */
382#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 0)
383/** ID_AA64ISAR1_EL1 register - RO. */
384#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 1)
385/** ID_AA64ISAR2_EL1 register - RO. */
386#define ARMV8_AARCH64_SYSREG_ID_AA64ISAR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 6, 2)
387
388/** ID_AA64MMFR0_EL1 register - RO. */
389#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 0)
390/** ID_AA64MMFR1_EL1 register - RO. */
391#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 1)
392/** ID_AA64MMFR2_EL1 register - RO. */
393#define ARMV8_AARCH64_SYSREG_ID_AA64MMFR2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 0, 7, 2)
394
395/** SCTRL_EL1 register - RW. */
396#define ARMV8_AARCH64_SYSREG_SCTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 0)
397/** ACTRL_EL1 register - RW. */
398#define ARMV8_AARCH64_SYSREG_ACTRL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 1)
399/** CPACR_EL1 register - RW. */
400#define ARMV8_AARCH64_SYSREG_CPACR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 2)
401/** RGSR_EL1 register - RW. */
402#define ARMV8_AARCH64_SYSREG_RGSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 5)
403/** GCR_EL1 register - RW. */
404#define ARMV8_AARCH64_SYSREG_GCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 0, 6)
405
406/** ZCR_EL1 register - RW. */
407#define ARMV8_AARCH64_SYSREG_ZCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 0)
408/** TRFCR_EL1 register - RW. */
409#define ARMV8_AARCH64_SYSREG_TRFCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 1)
410/** SMPRI_EL1 register - RW. */
411#define ARMV8_AARCH64_SYSREG_SMPRI_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 4)
412/** SMCR_EL1 register - RW. */
413#define ARMV8_AARCH64_SYSREG_SMCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 1, 2, 6)
414
415/** TTBR0_EL1 register - RW. */
416#define ARMV8_AARCH64_SYSREG_TTBR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 0)
417/** TTBR1_EL1 register - RW. */
418#define ARMV8_AARCH64_SYSREG_TTBR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 1)
419/** TCR_EL1 register - RW. */
420#define ARMV8_AARCH64_SYSREG_TCR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 2, 0, 2)
421
422/** @todo APIA,APIB,APDA,APDB,APGA registers. */
423
424/** SPSR_EL1 register - RW. */
425#define ARMV8_AARCH64_SYSREG_SPSR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 0)
426/** ELR_EL1 register - RW. */
427#define ARMV8_AARCH64_SYSREG_ELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 0, 1)
428
429/** SP_EL0 register - RW. */
430#define ARMV8_AARCH64_SYSREG_SP_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 1, 0)
431
432/** PSTATE.SPSel value. */
433#define ARMV8_AARCH64_SYSREG_SPSEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 0)
434/** PSTATE.CurrentEL value. */
435#define ARMV8_AARCH64_SYSREG_CURRENTEL ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 2)
436/** PSTATE.PAN value. */
437#define ARMV8_AARCH64_SYSREG_PAN ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 3)
438/** PSTATE.UAO value. */
439#define ARMV8_AARCH64_SYSREG_UAO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 2, 4)
440
441/** PSTATE.ALLINT value. */
442#define ARMV8_AARCH64_SYSREG_ALLINT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 3, 0)
443
444/** ICC_PMR_EL1 register - RW. */
445#define ARMV8_AARCH64_SYSREG_ICC_PMR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 4, 6, 0)
446
447/** AFSR0_EL1 register - RW. */
448#define ARMV8_AARCH64_SYSREG_AFSR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 0)
449/** AFSR1_EL1 register - RW. */
450#define ARMV8_AARCH64_SYSREG_AFSR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 1, 1)
451
452/** ESR_EL1 register - RW. */
453#define ARMV8_AARCH64_SYSREG_ESR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 2, 0)
454
455/** ERRIDR_EL1 register - RO. */
456#define ARMV8_AARCH64_SYSREG_ERRIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 0)
457/** ERRSELR_EL1 register - RW. */
458#define ARMV8_AARCH64_SYSREG_ERRSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 5, 3, 1)
459
460/** FAR_EL1 register - RW. */
461#define ARMV8_AARCH64_SYSREG_FAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 6, 0, 0)
462
463/** PAR_EL1 register - RW. */
464#define ARMV8_AARCH64_SYSREG_PAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 7, 4, 0)
465
466/** MAIR_EL1 register - RW. */
467#define ARMV8_AARCH64_SYSREG_MAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 2, 0)
468
469/** AMAIR_EL1 register - RW. */
470#define ARMV8_AARCH64_SYSREG_AMAIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 10, 3, 0)
471
472/** VBAR_EL1 register - RW. */
473#define ARMV8_AARCH64_SYSREG_VBAR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 0, 0)
474
475/** ICC_IAR0_EL1 register - RO. */
476#define ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 0)
477/** ICC_EOIR0_EL1 register - WO. */
478#define ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 1)
479/** ICC_HPPIR0_EL1 register - WO. */
480#define ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 2)
481/** ICC_BPR0_EL1 register - RW. */
482#define ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 3)
483/** ICC_AP0R0_EL1 register - RW. */
484#define ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 4)
485/** ICC_AP0R1_EL1 register - RW. */
486#define ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 5)
487/** ICC_AP0R2_EL1 register - RW. */
488#define ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 6)
489/** ICC_AP0R3_EL1 register - RW. */
490#define ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 8, 7)
491
492/** ICC_AP1R0_EL1 register - RW. */
493#define ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 0)
494/** ICC_AP1R1_EL1 register - RW. */
495#define ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 1)
496/** ICC_AP1R2_EL1 register - RW. */
497#define ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 2)
498/** ICC_AP1R3_EL1 register - RW. */
499#define ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 3)
500/** ICC_NMIAR1_EL1 register - RO. */
501#define ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 9, 5)
502
503/** ICC_DIR_EL1 register - WO. */
504#define ARMV8_AARCH64_SYSREG_ICC_DIR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 1)
505/** ICC_RPR_EL1 register - RO. */
506#define ARMV8_AARCH64_SYSREG_ICC_RPR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 3)
507/** ICC_SGI1R_EL1 register - WO. */
508#define ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 5)
509/** ICC_ASGI1R_EL1 register - WO. */
510#define ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 6)
511/** ICC_SGI0R_EL1 register - WO. */
512#define ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 11, 7)
513
514/** ICC_IAR1_EL1 register - RO. */
515#define ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 0)
516/** ICC_EOIR1_EL1 register - WO. */
517#define ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 1)
518/** ICC_HPPIR1_EL1 register - RO. */
519#define ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 2)
520/** ICC_BPR1_EL1 register - RW. */
521#define ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 3)
522/** ICC_CTLR_EL1 register - RW. */
523#define ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 4)
524/** ICC_SRE_EL1 register - RW. */
525#define ARMV8_AARCH64_SYSREG_ICC_SRE_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 5)
526/** ICC_IGRPEN0_EL1 register - RW. */
527#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 6)
528/** ICC_IGRPEN1_EL1 register - RW. */
529#define ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 12, 12, 7)
530
531/** CONTEXTIDR_EL1 register - RW. */
532#define ARMV8_AARCH64_SYSREG_CONTEXTIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 1)
533/** TPIDR_EL1 register - RW. */
534#define ARMV8_AARCH64_SYSREG_TPIDR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 13, 0, 4)
535
536/** CNTKCTL_EL1 register - RW. */
537#define ARMV8_AARCH64_SYSREG_CNTKCTL_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 0, 14, 1, 0)
538
539/** CSSELR_EL1 register - RW. */
540#define ARMV8_AARCH64_SYSREG_CSSELR_EL1 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 2, 0, 0, 0)
541
542/** NZCV - Status Flags - ??. */
543#define ARMV8_AARCH64_SYSREG_NZCV ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 0)
544/** DAIF - Interrupt Mask Bits - ??. */
545#define ARMV8_AARCH64_SYSREG_DAIF ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 1)
546/** SVCR - Streaming Vector Control Register - ??. */
547#define ARMV8_AARCH64_SYSREG_SVCR ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 2)
548/** DIT - Data Independent Timing - ??. */
549#define ARMV8_AARCH64_SYSREG_DIT ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 5)
550/** SSBS - Speculative Store Bypass Safe - ??. */
551#define ARMV8_AARCH64_SYSREG_SSBS ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 6)
552/** TCO - Tag Check Override - ??. */
553#define ARMV8_AARCH64_SYSREG_TCO ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 4, 2, 7)
554
555/** TPIDR_EL0 register - RW. */
556#define ARMV8_AARCH64_SYSREG_TPIDR_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 2)
557/** TPIDRRO_EL0 register - RO. */
558#define ARMV8_AARCH64_SYSREG_TPIDRRO_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 13, 0, 3)
559
560/** CNTV_CTL_EL0 register - RW. */
561#define ARMV8_AARCH64_SYSREG_CNTV_CTL_EL0 ARMV8_AARCH64_SYSREG_ID_CREATE(3, 3, 14, 3, 1)
562/** @} */
563
564
565#ifndef RT_IN_ASSEMBLER
566/**
567 * SPSR_EL2 (according to chapter C5.2.19)
568 */
569typedef union ARMV8SPSREL2
570{
571 /** The plain unsigned view. */
572 uint64_t u;
573 /** The 8-bit view. */
574 uint8_t au8[8];
575 /** The 16-bit view. */
576 uint16_t au16[4];
577 /** The 32-bit view. */
578 uint32_t au32[2];
579 /** The 64-bit view. */
580 uint64_t u64;
581} ARMV8SPSREL2;
582/** Pointer to SPSR_EL2. */
583typedef ARMV8SPSREL2 *PARMV8SPSREL2;
584/** Pointer to const SPSR_EL2. */
585typedef const ARMV8SPSREL2 *PCXARMV8SPSREL2;
586#endif /* !RT_IN_ASSEMBLER */
587
588
589/** @name SPSR_EL2 (When exception is taken from AArch64 state)
590 * @{
591 */
592/** Bit 0 - 3 - M - AArch64 Exception level and selected stack pointer. */
593#define ARMV8_SPSR_EL2_AARCH64_M (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
594#define ARMV8_SPSR_EL2_AARCH64_GET_M(a_Spsr) ((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M)
595/** Bit 0 - SP - Selected stack pointer. */
596#define ARMV8_SPSR_EL2_AARCH64_SP RT_BIT_64(0)
597#define ARMV8_SPSR_EL2_AARCH64_SP_BIT 0
598/** Bit 1 - Reserved (read as zero). */
599#define ARMV8_SPSR_EL2_AARCH64_RSVD_1 RT_BIT_64(1)
600/** Bit 2 - 3 - EL - Exception level. */
601#define ARMV8_SPSR_EL2_AARCH64_EL (RT_BIT_64(2) | RT_BIT_64(3))
602#define ARMV8_SPSR_EL2_AARCH64_EL_SHIFT 2
603#define ARMV8_SPSR_EL2_AARCH64_GET_EL(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_EL_SHIFT) & 3)
604#define ARMV8_SPSR_EL2_AARCH64_SET_EL(a_El) ((a_El) << ARMV8_SPSR_EL2_AARCH64_EL_SHIFT)
605/** Bit 4 - M[4] - Execution state (0 means AArch64, when 1 this contains a AArch32 state). */
606#define ARMV8_SPSR_EL2_AARCH64_M4 RT_BIT_64(4)
607#define ARMV8_SPSR_EL2_AARCH64_M4_BIT 4
608/** Bit 5 - T - T32 instruction set state (only valid when ARMV8_SPSR_EL2_AARCH64_M4 is set). */
609#define ARMV8_SPSR_EL2_AARCH64_T RT_BIT_64(5)
610#define ARMV8_SPSR_EL2_AARCH64_T_BIT 5
611/** Bit 6 - I - FIQ interrupt mask. */
612#define ARMV8_SPSR_EL2_AARCH64_F RT_BIT_64(6)
613#define ARMV8_SPSR_EL2_AARCH64_F_BIT 6
614/** Bit 7 - I - IRQ interrupt mask. */
615#define ARMV8_SPSR_EL2_AARCH64_I RT_BIT_64(7)
616#define ARMV8_SPSR_EL2_AARCH64_I_BIT 7
617/** Bit 8 - A - SError interrupt mask. */
618#define ARMV8_SPSR_EL2_AARCH64_A RT_BIT_64(8)
619#define ARMV8_SPSR_EL2_AARCH64_A_BIT 8
620/** Bit 9 - D - Debug Exception mask. */
621#define ARMV8_SPSR_EL2_AARCH64_D RT_BIT_64(9)
622#define ARMV8_SPSR_EL2_AARCH64_D_BIT 9
623/** Bit 10 - 11 - BTYPE - Branch Type indicator. */
624#define ARMV8_SPSR_EL2_AARCH64_BYTPE (RT_BIT_64(10) | RT_BIT_64(11))
625#define ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT 10
626#define ARMV8_SPSR_EL2_AARCH64_GET_BYTPE(a_Spsr) (((a_Spsr) >> ARMV8_SPSR_EL2_AARCH64_BYTPE_SHIFT) & 3)
627/** Bit 12 - SSBS - Speculative Store Bypass. */
628#define ARMV8_SPSR_EL2_AARCH64_SSBS RT_BIT_64(12)
629#define ARMV8_SPSR_EL2_AARCH64_SSBS_BIT 12
630/** Bit 13 - ALLINT - All IRQ or FIQ interrupts mask. */
631#define ARMV8_SPSR_EL2_AARCH64_ALLINT RT_BIT_64(13)
632#define ARMV8_SPSR_EL2_AARCH64_ALLINT_BIT 13
633/** Bit 14 - 19 - Reserved (read as zero). */
634#define ARMV8_SPSR_EL2_AARCH64_RSVD_14_19 ( RT_BIT_64(14) | RT_BIT_64(15) | RT_BIT_64(16) \
635 | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
636/** Bit 20 - IL - Illegal Execution State flag. */
637#define ARMV8_SPSR_EL2_AARCH64_IL RT_BIT_64(20)
638#define ARMV8_SPSR_EL2_AARCH64_IL_BIT 20
639/** Bit 21 - SS - Software Step flag. */
640#define ARMV8_SPSR_EL2_AARCH64_SS RT_BIT_64(21)
641#define ARMV8_SPSR_EL2_AARCH64_SS_BIT 21
642/** Bit 22 - PAN - Privileged Access Never flag. */
643#define ARMV8_SPSR_EL2_AARCH64_PAN RT_BIT_64(25)
644#define ARMV8_SPSR_EL2_AARCH64_PAN_BIT 22
645/** Bit 23 - UAO - User Access Override flag. */
646#define ARMV8_SPSR_EL2_AARCH64_UAO RT_BIT_64(23)
647#define ARMV8_SPSR_EL2_AARCH64_UAO_BIT 23
648/** Bit 24 - DIT - Data Independent Timing flag. */
649#define ARMV8_SPSR_EL2_AARCH64_DIT RT_BIT_64(24)
650#define ARMV8_SPSR_EL2_AARCH64_DIT_BIT 24
651/** Bit 25 - TCO - Tag Check Override flag. */
652#define ARMV8_SPSR_EL2_AARCH64_TCO RT_BIT_64(25)
653#define ARMV8_SPSR_EL2_AARCH64_TCO_BIT 25
654/** Bit 26 - 27 - Reserved (read as zero). */
655#define ARMV8_SPSR_EL2_AARCH64_RSVD_26_27 (RT_BIT_64(26) | RT_BIT_64(27))
656/** Bit 28 - V - Overflow condition flag. */
657#define ARMV8_SPSR_EL2_AARCH64_V RT_BIT_64(28)
658#define ARMV8_SPSR_EL2_AARCH64_V_BIT 28
659/** Bit 29 - C - Carry condition flag. */
660#define ARMV8_SPSR_EL2_AARCH64_C RT_BIT_64(29)
661#define ARMV8_SPSR_EL2_AARCH64_C_BIT 29
662/** Bit 30 - Z - Zero condition flag. */
663#define ARMV8_SPSR_EL2_AARCH64_Z RT_BIT_64(30)
664#define ARMV8_SPSR_EL2_AARCH64_Z_BIT 30
665/** Bit 31 - N - Negative condition flag. */
666#define ARMV8_SPSR_EL2_AARCH64_N RT_BIT_64(31)
667#define ARMV8_SPSR_EL2_AARCH64_N_BIT 31
668/** Bit 32 - 63 - Reserved (read as zero). */
669#define ARMV8_SPSR_EL2_AARCH64_RSVD_32_63 (UINT64_C(0xffffffff00000000))
670/** Checks whether the given SPSR value contains a AARCH64 execution state. */
671#define ARMV8_SPSR_EL2_IS_AARCH64_STATE(a_Spsr) (!((a_Spsr) & ARMV8_SPSR_EL2_AARCH64_M4))
672/** @} */
673
674/** @name Aarch64 Exception levels
675 * @{ */
676/** Exception Level 0 - User mode. */
677#define ARMV8_AARCH64_EL_0 0
678/** Exception Level 1 - Supervisor mode. */
679#define ARMV8_AARCH64_EL_1 1
680/** Exception Level 2 - Hypervisor mode. */
681#define ARMV8_AARCH64_EL_2 2
682/** @} */
683
684
685/** @name ESR_EL2 (Exception Syndrome Register, EL2)
686 * @{
687 */
688/** Bit 0 - 24 - ISS - Instruction Specific Syndrome, encoding depends on the exception class. */
689#define ARMV8_ESR_EL2_ISS UINT64_C(0x1ffffff)
690#define ARMV8_ESR_EL2_ISS_GET(a_Esr) ((a_Esr) & ARMV8_ESR_EL2_ISS)
691/** Bit 25 - IL - Instruction length for synchronous exception (0 means 16-bit instruction, 1 32-bit instruction). */
692#define ARMV8_ESR_EL2_IL RT_BIT_64(25)
693#define ARMV8_ESR_EL2_IL_BIT 25
694#define ARMV8_ESR_EL2_IL_IS_32BIT(a_Esr) RT_BOOL((a_Esr) & ARMV8_ESR_EL2_IL)
695#define ARMV8_ESR_EL2_IL_IS_16BIT(a_Esr) (!((a_Esr) & ARMV8_ESR_EL2_IL))
696/** Bit 26 - 31 - EC - Exception class, indicates reason for the exception that this register holds information about. */
697#define ARMV8_ESR_EL2_EC ( RT_BIT_64(26) | RT_BIT_64(27) | RT_BIT_64(28) \
698 | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
699#define ARMV8_ESR_EL2_EC_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_EC) >> 26)
700/** Bit 32 - 36 - ISS2 - Only valid when FEAT_LS64_V and/or FEAT_LS64_ACCDATA is present. */
701#define ARMV8_ESR_EL2_ISS2 ( RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) \
702 | RT_BIT_64(35) | RT_BIT_64(36))
703#define ARMV8_ESR_EL2_ISS2_GET(a_Esr) (((a_Esr) & ARMV8_ESR_EL2_ISS2) >> 32)
704/** @} */
705
706
707/** @name ESR_EL2 Exception Classes (EC)
708 * @{ */
709/** Unknown exception reason. */
710#define ARMV8_ESR_EL2_EC_UNKNOWN UINT32_C(0)
711/** Trapped WF* instruction. */
712#define ARMV8_ESR_EL2_EC_TRAPPED_WFX UINT32_C(1)
713/** AArch32 - Trapped MCR or MRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
714#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15 UINT32_C(3)
715/** AArch32 - Trapped MCRR or MRRC access (coproc == 0b1111) not reported through ARMV8_ESR_EL2_EC_UNKNOWN. */
716#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15 UINT32_C(4)
717/** AArch32 - Trapped MCR or MRC access (coproc == 0b1110). */
718#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14 UINT32_C(5)
719/** AArch32 - Trapped LDC or STC access. */
720#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC UINT32_C(6)
721/** AArch32 - Trapped access to SME, SVE or Advanced SIMD or floating point fnunctionality. */
722#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON UINT32_C(7)
723/** AArch32 - Trapped VMRS access not reported using ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON. */
724#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS UINT32_C(8)
725/** AArch32 - Trapped pointer authentication instruction. */
726#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN UINT32_C(9)
727/** FEAT_LS64 - Exception from LD64B or ST64B instruction. */
728#define ARMV8_ESR_EL2_EC_LS64_EXCEPTION UINT32_C(10)
729/** AArch32 - Trapped MRRC access (coproc == 0b1110). */
730#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14 UINT32_C(12)
731/** FEAT_BTI - Branch Target Exception. */
732#define ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION UINT32_C(13)
733/** Illegal Execution State. */
734#define ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE UINT32_C(14)
735/** AArch32 - SVC instruction execution. */
736#define ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN UINT32_C(17)
737/** AArch32 - HVC instruction execution. */
738#define ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN UINT32_C(18)
739/** AArch32 - SMC instruction execution. */
740#define ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN UINT32_C(19)
741/** AArch64 - SVC instruction execution. */
742#define ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN UINT32_C(21)
743/** AArch64 - HVC instruction execution. */
744#define ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN UINT32_C(22)
745/** AArch64 - SMC instruction execution. */
746#define ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN UINT32_C(23)
747/** AArch64 - Trapped MSR, MRS or System instruction execution in AArch64 state. */
748#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN UINT32_C(24)
749/** FEAT_SVE - Access to SVE vunctionality not reported using ARMV8_ESR_EL2_EC_UNKNOWN. */
750#define ARMV8_ESR_EL2_EC_SVE_TRAPPED UINT32_C(25)
751/** FEAT_PAuth and FEAT_NV - Trapped ERET, ERETAA or ERTAB instruction. */
752#define ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB UINT32_C(26)
753/** FEAT_TME - Exception from TSTART instruction. */
754#define ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION UINT32_C(27)
755/** FEAT_FPAC - Exception from a Pointer Authentication instruction failure. */
756#define ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION UINT32_C(28)
757/** FEAT_SME - Access to SME functionality trapped. */
758#define ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS UINT32_C(29)
759/** FEAT_RME - Exception from Granule Protection Check. */
760#define ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION UINT32_C(30)
761/** Instruction Abort from a lower Exception level. */
762#define ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL UINT32_C(32)
763/** Instruction Abort from the same Exception level. */
764#define ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2 UINT32_C(33)
765/** PC alignment fault exception. */
766#define ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION UINT32_C(34)
767/** Data Abort from a lower Exception level. */
768#define ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL UINT32_C(36)
769/** Data Abort from the same Exception level (or access associated with VNCR_EL2). */
770#define ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2 UINT32_C(37)
771/** SP alignment fault exception. */
772#define ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION UINT32_C(38)
773/** FEAT_MOPS - Memory Operation Exception. */
774#define ARMV8_ESR_EL2_EC_MOPS_EXCEPTION UINT32_C(39)
775/** AArch32 - Trapped floating point exception. */
776#define ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION UINT32_C(40)
777/** AArch64 - Trapped floating point exception. */
778#define ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION UINT32_C(44)
779/** SError interrupt. */
780#define ARMV8_ESR_EL2_SERROR_INTERRUPT UINT32_C(47)
781/** Breakpoint Exception from a lower Exception level. */
782#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL UINT32_C(48)
783/** Breakpoint Exception from the same Exception level. */
784#define ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2 UINT32_C(49)
785/** Software Step Exception from a lower Exception level. */
786#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL UINT32_C(50)
787/** Software Step Exception from the same Exception level. */
788#define ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2 UINT32_C(51)
789/** Watchpoint Exception from a lower Exception level. */
790#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL UINT32_C(52)
791/** Watchpoint Exception from the same Exception level. */
792#define ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2 UINT32_C(53)
793/** AArch32 - BKPT instruction execution. */
794#define ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN UINT32_C(56)
795/** AArch32 - Vector Catch exception. */
796#define ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION UINT32_C(58)
797/** AArch64 - BRK instruction execution. */
798#define ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN UINT32_C(60)
799/** @} */
800
801
802/** @name ISS encoding for Data Abort exceptions.
803 * @{ */
804/** Bit 0 - 5 - DFSC - Data Fault Status Code. */
805#define ARMV8_EC_ISS_DATA_ABRT_DFSC ( RT_BIT_32(0) | RT_BIT_32(1) | RT_BIT_32(2) \
806 | RT_BIT_32(3) | RT_BIT_32(4) | RT_BIT_32(5))
807#define ARMV8_EC_ISS_DATA_ABRT_DFSC_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_DFSC)
808/** Bit 6 - WnR - Write not Read. */
809#define ARMV8_EC_ISS_DATA_ABRT_WNR RT_BIT_32(6)
810#define ARMV8_EC_ISS_DATA_ABRT_WNR_BIT 6
811/** Bit 7 - S1PTW - Stage 2 translation fault for an access made for a stage 1 translation table walk. */
812#define ARMV8_EC_ISS_DATA_ABRT_S1PTW RT_BIT_32(7)
813#define ARMV8_EC_ISS_DATA_ABRT_S1PTW_BIT 7
814/** Bit 8 - CM - Cache maintenance instruction. */
815#define ARMV8_EC_ISS_DATA_ABRT_CM RT_BIT_32(8)
816#define ARMV8_EC_ISS_DATA_ABRT_CM_BIT 8
817/** Bit 9 - EA - External abort type. */
818#define ARMV8_EC_ISS_DATA_ABRT_EA RT_BIT_32(9)
819#define ARMV8_EC_ISS_DATA_ABRT_EA_BIT 9
820/** Bit 10 - FnV - FAR not Valid. */
821#define ARMV8_EC_ISS_DATA_ABRT_FNV RT_BIT_32(10)
822#define ARMV8_EC_ISS_DATA_ABRT_FNV_BIT 10
823/** Bit 11 - 12 - LST - Load/Store Type. */
824#define ARMV8_EC_ISS_DATA_ABRT_LST (RT_BIT_32(11) | RT_BIT_32(12))
825#define ARMV8_EC_ISS_DATA_ABRT_LST_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_LST) >> 11)
826/** Bit 13 - VNCR - Fault came from use of VNCR_EL2 register by EL1 code. */
827#define ARMV8_EC_ISS_DATA_ABRT_VNCR RT_BIT_32(13)
828#define ARMV8_EC_ISS_DATA_ABRT_VNCR_BIT 13
829/** Bit 14 - AR - Acquire/Release semantics. */
830#define ARMV8_EC_ISS_DATA_ABRT_AR RT_BIT_32(14)
831#define ARMV8_EC_ISS_DATA_ABRT_AR_BIT 14
832/** Bit 15 - SF - Sixty Four bit general-purpose register transfer (only when ISV is 1). */
833#define ARMV8_EC_ISS_DATA_ABRT_SF RT_BIT_32(15)
834#define ARMV8_EC_ISS_DATA_ABRT_SF_BIT 15
835/** Bit 16 - 20 - SRT - Syndrome Register Transfer. */
836#define ARMV8_EC_ISS_DATA_ABRT_SRT ( RT_BIT_32(16) | RT_BIT_32(17) | RT_BIT_32(18) \
837 | RT_BIT_32(19) | RT_BIT_32(20))
838#define ARMV8_EC_ISS_DATA_ABRT_SRT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SRT) >> 16)
839/** Bit 21 - SSE - Syndrome Sign Extend. */
840#define ARMV8_EC_ISS_DATA_ABRT_SSE RT_BIT_32(21)
841#define ARMV8_EC_ISS_DATA_ABRT_SSE_BIT 21
842/** Bit 22 - 23 - SAS - Syndrome Access Size. */
843#define ARMV8_EC_ISS_DATA_ABRT_SAS (RT_BIT_32(22) | RT_BIT_32(23))
844#define ARMV8_EC_ISS_DATA_ABRT_SAS_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_DATA_ABRT_SAS) >> 22)
845/** Bit 24 - ISV - Instruction Syndrome Valid. */
846#define ARMV8_EC_ISS_DATA_ABRT_ISV RT_BIT_32(24)
847#define ARMV8_EC_ISS_DATA_ABRT_ISV_BIT 24
848/** @} */
849
850
851/** @name Data Fault Status Code (DFSC).
852 * @{ */
853/** Address size fault, level 0 of translation or translation table base register. */
854#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL0 0
855/** Address size fault, level 1. */
856#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL1 1
857/** Address size fault, level 2. */
858#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL2 2
859/** Address size fault, level 3. */
860#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ADDR_SIZE_FAULT_LVL3 3
861/** Translation fault, level 0. */
862#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL0 4
863/** Translation fault, level 1. */
864#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL1 5
865/** Translation fault, level 2. */
866#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL2 6
867/** Translation fault, level 3. */
868#define ARMV8_EC_ISS_DATA_ABRT_DFSC_TRANSLATION_FAULT_LVL3 7
869/** FEAT_LPA2 - Access flag fault, level 0. */
870#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL0 8
871/** Access flag fault, level 1. */
872#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL1 9
873/** Access flag fault, level 2. */
874#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL2 10
875/** Access flag fault, level 3. */
876#define ARMV8_EC_ISS_DATA_ABRT_DFSC_ACCESS_FLAG_FAULT_LVL3 11
877/** FEAT_LPA2 - Permission fault, level 0. */
878#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL0 12
879/** Permission fault, level 1. */
880#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL1 13
881/** Permission fault, level 2. */
882#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL2 14
883/** Permission fault, level 3. */
884#define ARMV8_EC_ISS_DATA_ABRT_DFSC_PERMISSION_FAULT_LVL3 15
885/** Synchronous External abort, not a translation table walk or hardware update of translation table. */
886#define ARMV8_EC_ISS_DATA_ABRT_DFSC_SYNC_EXTERNAL 16
887/** FEAT_MTE2 - Synchronous Tag Check Fault. */
888#define ARMV8_EC_ISS_DATA_ABRT_DFSC_MTE2_SYNC_TAG_CHK_FAULT 17
889/** @todo Do the rest (lazy developer). */
890/** @} */
891
892
893/** @name SAS encoding.
894 * @{ */
895/** Byte access. */
896#define ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE 0
897/** Halfword access (uint16_t). */
898#define ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD 1
899/** Word access (uint32_t). */
900#define ARMV8_EC_ISS_DATA_ABRT_SAS_WORD 2
901/** Doubleword access (uint64_t). */
902#define ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD 3
903/** @} */
904
905
906/** @name ISS encoding for trapped MSR, MRS or System instruction exceptions.
907 * @{ */
908/** Bit 0 - Direction flag. */
909#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION RT_BIT_32(0)
910#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(a_Iss) RT_BOOL((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION)
911/** Bit 1 - 4 - CRm value from the instruction. */
912#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM ( RT_BIT_32(1) | RT_BIT_32(2) | RT_BIT_32(3) \
913 | RT_BIT_32(4))
914#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM) >> 1)
915/** Bit 5 - 9 - Rt value from the instruction. */
916#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT ( RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7) \
917 | RT_BIT_32(8) | RT_BIT_32(9))
918#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT) >> 5)
919/** Bit 10 - 13 - CRn value from the instruction. */
920#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN ( RT_BIT_32(10) | RT_BIT_32(11) | RT_BIT_32(12) \
921 | RT_BIT_32(13))
922#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN) >> 10)
923/** Bit 14 - 16 - Op2 value from the instruction. */
924#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1 (RT_BIT_32(14) | RT_BIT_32(15) | RT_BIT_32(16))
925#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1) >> 14)
926/** Bit 17 - 19 - Op2 value from the instruction. */
927#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2 (RT_BIT_32(17) | RT_BIT_32(18) | RT_BIT_32(19))
928#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2) >> 17)
929/** Bit 20 - 21 - Op0 value from the instruction. */
930#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0 (RT_BIT_32(20) | RT_BIT_32(21))
931#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(a_Iss) (((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0) >> 20)
932/** Bit 22 - 24 - Reserved. */
933#define ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RSVD (RT_BIT_32(22) | RT_BIT_32(23) | RT_BIT_32(24))
934/** @} */
935
936
937/** @name ISS encoding for trapped HVC instruction exceptions.
938 * @{ */
939/** Bit 0 - 15 - imm16 value of the instruction. */
940#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM (UINT16_C(0xffff))
941#define ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(a_Iss) ((a_Iss) & ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM)
942/** @} */
943
944
945/** @name TCR_EL1 - Translation Control Register (EL1)
946 * @{
947 */
948/** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */
949#define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \
950 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5))
951#define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ)
952/** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */
953#define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7)
954#define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7
955/** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
956#define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9))
957#define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8)
958/** Non cacheable. */
959# define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0
960/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
961# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1
962/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
963# define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2
964/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
965# define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3
966/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */
967#define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11))
968#define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10)
969/** Non cacheable. */
970# define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0
971/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
972# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1
973/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
974# define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2
975/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
976# define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3
977/** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */
978#define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13))
979#define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12)
980/** Non shareable. */
981# define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0
982/** Invalid value. */
983# define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1
984/** Outer Shareable. */
985# define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2
986/** Inner Shareable. */
987# define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3
988/** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */
989#define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15))
990#define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14)
991/** Invalid granule size. */
992# define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0
993/** 16KiB granule size. */
994# define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1
995/** 4KiB granule size. */
996# define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2
997/** 64KiB granule size. */
998# define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3
999/** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */
1000#define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \
1001 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21))
1002#define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16)
1003/** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */
1004#define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22)
1005#define ARMV8_TCR_EL1_AARCH64_A1_BIT 22
1006/** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */
1007#define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23)
1008#define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23
1009/** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1010#define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25))
1011#define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26)
1012/** Non cacheable. */
1013# define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0
1014/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1015# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1
1016/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1017# define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2
1018/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1019# define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3
1020/** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */
1021#define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27))
1022#define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26)
1023/** Non cacheable. */
1024# define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0
1025/** Write-Back, Read-Allocate, Write-Allocate Cacheable. */
1026# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1
1027/** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */
1028# define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2
1029/** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */
1030# define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3
1031/** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */
1032#define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29))
1033#define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28)
1034/** Non shareable. */
1035# define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0
1036/** Invalid value. */
1037# define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1
1038/** Outer Shareable. */
1039# define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2
1040/** Inner Shareable. */
1041# define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3
1042/** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */
1043#define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31))
1044#define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30)
1045/** Invalid granule size. */
1046# define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0
1047/** 16KiB granule size. */
1048# define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1
1049/** 4KiB granule size. */
1050# define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2
1051/** 64KiB granule size. */
1052# define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3
1053/** Bit 32 - 34 - Intermediate Physical Address Size. */
1054#define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34))
1055#define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32)
1056/** IPA - 32 bits, 4GiB. */
1057# define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0
1058/** IPA - 36 bits, 64GiB. */
1059# define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1
1060/** IPA - 40 bits, 1TiB. */
1061# define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2
1062/** IPA - 42 bits, 4TiB. */
1063# define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3
1064/** IPA - 44 bits, 16TiB. */
1065# define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4
1066/** IPA - 48 bits, 256TiB. */
1067# define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5
1068/** IPA - 52 bits, 4PiB. */
1069# define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6
1070/** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */
1071#define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36)
1072#define ARMV8_TCR_EL1_AARCH64_AS_BIT 36
1073/** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */
1074#define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37)
1075#define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37
1076/** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */
1077#define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38)
1078#define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38
1079/** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */
1080#define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39)
1081#define ARMV8_TCR_EL1_AARCH64_HA_BIT 39
1082/** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */
1083#define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40)
1084#define ARMV8_TCR_EL1_AARCH64_HD_BIT 40
1085/** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */
1086#define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41)
1087#define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41
1088/** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */
1089#define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42)
1090#define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42
1091/** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */
1092#define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43)
1093#define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43
1094/** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */
1095#define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44)
1096#define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44
1097/** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */
1098#define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45)
1099#define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45
1100/** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */
1101#define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46)
1102#define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46
1103/** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */
1104#define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47)
1105#define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47
1106/** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */
1107#define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48)
1108#define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48
1109/** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */
1110#define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49)
1111#define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49
1112/** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */
1113#define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50)
1114#define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50
1115/** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */
1116#define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51)
1117#define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51
1118/** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */
1119#define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52)
1120#define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52
1121/** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */
1122#define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53)
1123#define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53
1124/** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */
1125#define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54)
1126#define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54
1127/** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */
1128#define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55)
1129#define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55
1130/** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */
1131#define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56)
1132#define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56
1133/** Bit 57 - TCMA0 */
1134#define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57)
1135#define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57
1136/** Bit 58 - TCMA1 */
1137#define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58)
1138#define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58
1139/** Bit 59 - Data Sharing(?). */
1140#define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59)
1141#define ARMV8_TCR_EL1_AARCH64_DS_BIT 59
1142/** @} */
1143
1144
1145/** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1)
1146 * @{
1147 */
1148/** Bit 0 - Common not Private (FEAT_TTCNP). */
1149#define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0)
1150#define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0
1151/** Bit 1 - 47 - Translation table base address. */
1152#define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe)
1153#define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1)
1154/** Bit 48 - 63 - ASID. */
1155#define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000)
1156#define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48)
1157/** @} */
1158
1159
1160/** @name ICC_PMR_EL1 - Interrupt Controller Interrupt Priority Mask Register
1161 * @{ */
1162/** Bit 0 - 7 - Priority - The priority mask level for the CPU interface. */
1163#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY UINT64_C(0xff)
1164#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_GET(a_Pmr) ((a_Pmr) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1165#define ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY_SET(a_Prio) ((a_Prio) & ARMV8_ICC_PMR_EL1_AARCH64_PRIORITY)
1166/** @} */
1167
1168
1169/** @name ICC_BPR0_EL1 - The group priority for Group 0 interrupts.
1170 * @{ */
1171/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1172#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1173#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_GET(a_Bpr0) ((a_Bpr0) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1174#define ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR0_EL1_AARCH64_BINARYPOINT)
1175/** @} */
1176
1177
1178/** @name ICC_BPR1_EL1 - The group priority for Group 1 interrupts.
1179 * @{ */
1180/** Bit 0 - 2 - BinaryPoint - Controls how the 8-bit interrupt priority field is split into a group priority and subpriority field. */
1181#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2))
1182#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_GET(a_Bpr1) ((a_Bpr1) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1183#define ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT_SET(a_BinaryPt) ((a_BinaryPt) & ARMV8_ICC_BPR1_EL1_AARCH64_BINARYPOINT)
1184/** @} */
1185
1186
1187/** @name ICC_CTLR_EL1 - Interrupt Controller Control Register (EL1)
1188 * @{ */
1189/** Bit 0 - Common Binary Pointer Register - RW. */
1190#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR RT_BIT_64(0)
1191#define ARMV8_ICC_CTLR_EL1_AARCH64_CBPR_BIT 0
1192/** Bit 1 - EOI mode for current security state, when set ICC_DIR_EL1 provides interrupt deactivation functionality - RW. */
1193#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE RT_BIT_64(1)
1194#define ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE_BIT 1
1195/** Bit 7 - Priority Mask Hint Enable - RW (under circumstances). */
1196#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE RT_BIT_64(7)
1197#define ARMV8_ICC_CTLR_EL1_AARCH64_PMHE_BIT 7
1198/** Bit 8 - 10 - Priority bits - RO. */
1199#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10))
1200#define ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS_SET(a_PriBits) (((a_PriBits) << 8) & ARMV8_ICC_CTLR_EL1_AARCH64_PRIBITS)
1201/** Bit 11 - 13 - Interrupt identifier bits - RO. */
1202#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS (RT_BIT_64(11) | RT_BIT_64(12) | RT_BIT_64(13))
1203#define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_SET(a_IdBits) (((a_IdBits) << 11) & ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS)
1204/** INTIDS are 16-bit wide. */
1205# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_16BITS 0
1206/** INTIDS are 24-bit wide. */
1207# define ARMV8_ICC_CTLR_EL1_AARCH64_IDBITS_24BITS 1
1208/** Bit 14 - SEI Supported - RO. */
1209#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS RT_BIT_64(14)
1210#define ARMV8_ICC_CTLR_EL1_AARCH64_SEIS_BIT 14
1211/** Bit 15 - Affinity 3 Valid - RO. */
1212#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V RT_BIT_64(15)
1213#define ARMV8_ICC_CTLR_EL1_AARCH64_A3V_BIT 15
1214/** Bit 18 - Range Selector Support - RO. */
1215#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS RT_BIT_64(18)
1216#define ARMV8_ICC_CTLR_EL1_AARCH64_RSS_BIT 18
1217/** Bit 19 - Extended INTID range supported - RO. */
1218#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE RT_BIT_64(19)
1219#define ARMV8_ICC_CTLR_EL1_AARCH64_EXTRANGE_BIT 19
1220/** All RW bits. */
1221#define ARMV8_ICC_CTLR_EL1_RW (ARMV8_ICC_CTLR_EL1_AARCH64_CBPR | ARMV8_ICC_CTLR_EL1_AARCH64_EOIMODE | ARMV8_ICC_CTLR_EL1_AARCH64_PMHE)
1222/** All RO bits (including Res0). */
1223#define ARMV8_ICC_CTLR_EL1_RO ~ARMV8_ICC_CTLR_EL1_RW
1224/** @} */
1225
1226
1227/** @name ICC_IGRPEN0_EL1 - Interrupt Controller Interrupt Group 0 Enable Register (EL1)
1228 * @{ */
1229/** Bit 0 - Enables Group 0 interrupts for the current Security state. */
1230#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE RT_BIT_64(0)
1231#define ARMV8_ICC_IGRPEN0_EL1_AARCH64_ENABLE_BIT 0
1232/** @} */
1233
1234
1235/** @name ICC_IGRPEN1_EL1 - Interrupt Controller Interrupt Group 1 Enable Register (EL1)
1236 * @{ */
1237/** Bit 0 - Enables Group 1 interrupts for the current Security state. */
1238#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE RT_BIT_64(0)
1239#define ARMV8_ICC_IGRPEN1_EL1_AARCH64_ENABLE_BIT 0
1240/** @} */
1241
1242
1243/** @name ICC_SGI1R_EL1 - Interrupt Controller Software Generated Interrupt Group 1 Register (EL1) - WO
1244 * @{ */
1245/** Bit 0 - 15 - Target List, the set of PEs for which SGI interrupts will be generated. */
1246#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST (UINT64_C(0x000000000000ffff))
1247#define ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST_GET(a_Sgi1R) ((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_TARGET_LIST)
1248/** Bit 16 - 23 - The affinity 1 of the affinity path of the cluster for which SGI interrupts will be generated. */
1249#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1 (UINT64_C(0x00000000007f0000))
1250#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF1) >> 16)
1251/** Bit 24 - 27 - The INTID of the SGI. */
1252#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1253#define ARMV8_ICC_SGI1R_EL1_AARCH64_INTID_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_INTID) >> 24)
1254/* Bit 28 - 31 - Reserved. */
1255/** Bit 32 - 39 - The affinity 2 of the affinity path of the cluster for which SGI interrupts will be generated. */
1256#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2 (UINT64_C(0x000000ff00000000))
1257#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF2) >> 32)
1258/** Bit 40 - Interrupt Routing Mode - 1 means interrupts to all PEs in the system excluding the generating PE. */
1259#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM RT_BIT_64(40)
1260#define ARMV8_ICC_SGI1R_EL1_AARCH64_IRM_BIT 40
1261/* Bit 41 - 43 - Reserved. */
1262/** Bit 44 - 47 - Range selector. */
1263#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1264#define ARMV8_ICC_SGI1R_EL1_AARCH64_RS_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_RS) >> 44)
1265/** Bit 48 - 55 - The affinity 3 of the affinity path of the cluster for which SGI interrupts will be generated. */
1266#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3 (UINT64_C(0x00ff000000000000))
1267#define ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3_GET(a_Sgi1R) (((a_Sgi1R) & ARMV8_ICC_SGI1R_EL1_AARCH64_AFF3) >> 48)
1268/* Bit 56 - 63 - Reserved. */
1269/** @} */
1270
1271
1272/** @name CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register.
1273 * @{ */
1274/** Bit 0 - Enables the timer. */
1275#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE RT_BIT_64(0)
1276#define ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE_BIT 0
1277/** Bit 1 - Timer interrupt mask bit. */
1278#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK RT_BIT_64(1)
1279#define ARMV8_CNTV_CTL_EL0_AARCH64_IMASK_BIT 1
1280/** Bit 2 - Timer status bit. */
1281#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS RT_BIT_64(2)
1282#define ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS_BIT 2
1283/** @} */
1284
1285
1286/** @name OSLAR_EL1 - OS Lock Access Register.
1287 * @{ */
1288/** Bit 0 - The OS Lock status bit. */
1289#define ARMV8_OSLAR_EL1_AARCH64_OSLK RT_BIT_64(0)
1290#define ARMV8_OSLAR_EL1_AARCH64_OSLK_BIT 0
1291/** @} */
1292
1293
1294/** @name OSLSR_EL1 - OS Lock Status Register.
1295 * @{ */
1296/** Bit 0 - OSLM[0] Bit 0 of OS Lock model implemented. */
1297#define ARMV8_OSLSR_EL1_AARCH64_OSLM0 RT_BIT_64(0)
1298#define ARMV8_OSLSR_EL1_AARCH64_OSLM0_BIT 0
1299/** Bit 1 - The OS Lock status bit. */
1300#define ARMV8_OSLSR_EL1_AARCH64_OSLK RT_BIT_64(1)
1301#define ARMV8_OSLSR_EL1_AARCH64_OSLK_BIT 1
1302/** Bit 2 - Not 32-bit access. */
1303#define ARMV8_OSLSR_EL1_AARCH64_NTT RT_BIT_64(2)
1304#define ARMV8_OSLSR_EL1_AARCH64_NTT_BIT 2
1305/** Bit 0 - OSLM[1] Bit 1 of OS Lock model implemented. */
1306#define ARMV8_OSLSR_EL1_AARCH64_OSLM1 RT_BIT_64(3)
1307#define ARMV8_OSLSR_EL1_AARCH64_OSLM1_BIT 3
1308/** @} */
1309
1310
1311/** @name ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0.
1312 * @{ */
1313/* Bit 0 - 3 - Reserved. */
1314/** Bit 4 - 7 - Indicates support for AES instructions in AArch64 state. */
1315#define ARMV8_ID_AA64ISAR0_EL1_AES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1316#define ARMV8_ID_AA64ISAR0_EL1_AES_SHIFT 4
1317/** No AES instructions implemented. */
1318# define ARMV8_ID_AA64ISAR0_EL1_AES_NOT_IMPL 0
1319/** AES, AESD, AESMC and AESIMC instructions implemented (FEAT_AES). */
1320# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED 1
1321/** AES, AESD, AESMC and AESIMC instructions implemented and PMULL and PMULL2 instructions operating on 64bit source elements (FEAT_PMULL). */
1322# define ARMV8_ID_AA64ISAR0_EL1_AES_SUPPORTED_PMULL 2
1323/** Bit 8 - 11 - Indicates support for SHA1 instructions in AArch64 state. */
1324#define ARMV8_ID_AA64ISAR0_EL1_SHA1_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1325#define ARMV8_ID_AA64ISAR0_EL1_SHA1_SHIFT 8
1326/** No SHA1 instructions implemented. */
1327# define ARMV8_ID_AA64ISAR0_EL1_SHA1_NOT_IMPL 0
1328/** SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0 and SHA1SU1 instructions implemented (FEAT_SHA1). */
1329# define ARMV8_ID_AA64ISAR0_EL1_SHA1_SUPPORTED 1
1330/** Bit 12 - 15 - Indicates support for SHA2 instructions in AArch64 state. */
1331#define ARMV8_ID_AA64ISAR0_EL1_SHA2_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1332#define ARMV8_ID_AA64ISAR0_EL1_SHA2_SHIFT 12
1333/** No SHA2 instructions implemented. */
1334# define ARMV8_ID_AA64ISAR0_EL1_SHA2_NOT_IMPL 0
1335/** SHA256 instructions implemented (FEAT_SHA256). */
1336# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256 1
1337/** SHA256 and SHA512 instructions implemented (FEAT_SHA512). */
1338# define ARMV8_ID_AA64ISAR0_EL1_SHA2_SUPPORTED_SHA256_SHA512 2
1339/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1340#define ARMV8_ID_AA64ISAR0_EL1_CRC32_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1341#define ARMV8_ID_AA64ISAR0_EL1_CRC32_SHIFT 16
1342/** No CRC32 instructions implemented. */
1343# define ARMV8_ID_AA64ISAR0_EL1_CRC32_NOT_IMPL 0
1344/** CRC32 instructions implemented (FEAT_CRC32). */
1345# define ARMV8_ID_AA64ISAR0_EL1_CRC32_SUPPORTED 1
1346/** Bit 20 - 23 - Indicates support for Atomic instructions in AArch64 state. */
1347#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1348#define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
1349/** No Atomic instructions implemented. */
1350# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_NOT_IMPL 0
1351/** Atomic instructions implemented (FEAT_LSE). */
1352# define ARMV8_ID_AA64ISAR0_EL1_ATOMIC_SUPPORTED 2
1353/** Bit 24 - 27 - Indicates support for TME instructions. */
1354#define ARMV8_ID_AA64ISAR0_EL1_TME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1355#define ARMV8_ID_AA64ISAR0_EL1_TME_SHIFT 24
1356/** TME instructions are not implemented. */
1357# define ARMV8_ID_AA64ISAR0_EL1_TME_NOT_IMPL 0
1358/** TME instructions are implemented. */
1359# define ARMV8_ID_AA64ISAR0_EL1_TME_SUPPORTED 1
1360/** Bit 28 - 31 - Indicates support for SQRDMLAH and SQRDMLSH instructions in AArch64 state. */
1361#define ARMV8_ID_AA64ISAR0_EL1_RDM_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1362#define ARMV8_ID_AA64ISAR0_EL1_RDM_SHIFT 28
1363/** No RDMA instructions implemented. */
1364# define ARMV8_ID_AA64ISAR0_EL1_RDM_NOT_IMPL 0
1365/** SQRDMLAH and SQRDMLSH instructions implemented (FEAT_RDM). */
1366# define ARMV8_ID_AA64ISAR0_EL1_RDM_SUPPORTED 1
1367/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1368#define ARMV8_ID_AA64ISAR0_EL1_SHA3_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1369#define ARMV8_ID_AA64ISAR0_EL1_SHA3_SHIFT 32
1370/** No SHA3 instructions implemented. */
1371# define ARMV8_ID_AA64ISAR0_EL1_SHA3_NOT_IMPL 0
1372/** EOR3, RAX1, XAR and BCAX instructions implemented (FEAT_SHA3). */
1373# define ARMV8_ID_AA64ISAR0_EL1_SHA3_SUPPORTED 1
1374/** Bit 36 - 39 - Indicates support for SM3 instructions in AArch64 state. */
1375#define ARMV8_ID_AA64ISAR0_EL1_SM3_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1376#define ARMV8_ID_AA64ISAR0_EL1_SM3_SHIFT 36
1377/** No SM3 instructions implemented. */
1378# define ARMV8_ID_AA64ISAR0_EL1_SM3_NOT_IMPL 0
1379/** SM3 instructions implemented (FEAT_SM3). */
1380# define ARMV8_ID_AA64ISAR0_EL1_SM3_SUPPORTED 1
1381/** Bit 40 - 43 - Indicates support for SM4 instructions in AArch64 state. */
1382#define ARMV8_ID_AA64ISAR0_EL1_SM4_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1383#define ARMV8_ID_AA64ISAR0_EL1_SM4_SHIFT 40
1384/** No SM4 instructions implemented. */
1385# define ARMV8_ID_AA64ISAR0_EL1_SM4_NOT_IMPL 0
1386/** SM4 instructions implemented (FEAT_SM4). */
1387# define ARMV8_ID_AA64ISAR0_EL1_SM4_SUPPORTED 1
1388/** Bit 44 - 47 - Indicates support for Dot Product instructions in AArch64 state. */
1389#define ARMV8_ID_AA64ISAR0_EL1_DP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1390#define ARMV8_ID_AA64ISAR0_EL1_DP_SHIFT 44
1391/** No Dot Product instructions implemented. */
1392# define ARMV8_ID_AA64ISAR0_EL1_DP_NOT_IMPL 0
1393/** UDOT and SDOT instructions implemented (FEAT_DotProd). */
1394# define ARMV8_ID_AA64ISAR0_EL1_DP_SUPPORTED 1
1395/** Bit 48 - 51 - Indicates support for FMLAL and FMLSL instructions. */
1396#define ARMV8_ID_AA64ISAR0_EL1_FHM_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1397#define ARMV8_ID_AA64ISAR0_EL1_FHM_SHIFT 48
1398/** FMLAL and FMLSL instructions are not implemented. */
1399# define ARMV8_ID_AA64ISAR0_EL1_FHM_NOT_IMPL 0
1400/** FMLAL and FMLSL instructions are implemented (FEAT_FHM). */
1401# define ARMV8_ID_AA64ISAR0_EL1_FHM_SUPPORTED 1
1402/** Bit 52 - 55 - Indicates support for flag manipulation instructions. */
1403#define ARMV8_ID_AA64ISAR0_EL1_TS_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1404#define ARMV8_ID_AA64ISAR0_EL1_TS_SHIFT 52
1405/** No flag manipulation instructions implemented. */
1406# define ARMV8_ID_AA64ISAR0_EL1_TS_NOT_IMPL 0
1407/** CFINV, RMIF, SETF16 and SETF8 instrutions are implemented (FEAT_FlagM). */
1408# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED 1
1409/** CFINV, RMIF, SETF16, SETF8, AXFLAG and XAFLAG instrutions are implemented (FEAT_FlagM2). */
1410# define ARMV8_ID_AA64ISAR0_EL1_TS_SUPPORTED_2 2
1411/** Bit 56 - 59 - Indicates support for Outer Shareable and TLB range maintenance instructions. */
1412#define ARMV8_ID_AA64ISAR0_EL1_TLB_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1413#define ARMV8_ID_AA64ISAR0_EL1_TLB_SHIFT 56
1414/** Outer Sahreable and TLB range maintenance instructions are not implemented. */
1415# define ARMV8_ID_AA64ISAR0_EL1_TLB_NOT_IMPL 0
1416/** Outer Shareable TLB maintenance instructions are implemented (FEAT_TLBIOS). */
1417# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED 1
1418/** Outer Shareable and TLB range maintenance instructions are implemented (FEAT_TLBIRANGE). */
1419# define ARMV8_ID_AA64ISAR0_EL1_TLB_SUPPORTED_RANGE 2
1420/** Bit 60 - 63 - Indicates support for Random Number instructons in AArch64 state. */
1421#define ARMV8_ID_AA64ISAR0_EL1_RNDR_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1422#define ARMV8_ID_AA64ISAR0_EL1_RNDR_SHIFT 60
1423/** No Random Number instructions implemented. */
1424# define ARMV8_ID_AA64ISAR0_EL1_RNDR_NOT_IMPL 0
1425/** RNDR and RDNRRS registers are implemented . */
1426# define ARMV8_ID_AA64ISAR0_EL1_RNDR_SUPPORTED 1
1427/** @} */
1428
1429
1430/** @name ID_AA64ISAR1_EL1 - AArch64 Instruction Set Attribute Register 0.
1431 * @{ */
1432/** Bit 0 - 3 - Indicates support for Data Persistence writeback instructions in AArch64 state. */
1433#define ARMV8_ID_AA64ISAR1_EL1_DPB_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1434#define ARMV8_ID_AA64ISAR1_EL1_DPB_SHIFT 0
1435/** DC CVAP not supported. */
1436# define ARMV8_ID_AA64ISAR1_EL1_DPB_NOT_IMPL 0
1437/** DC CVAP supported (FEAT_DPB). */
1438# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED 1
1439/** DC CVAP and DC CVADP supported (FEAT_DPB2). */
1440# define ARMV8_ID_AA64ISAR1_EL1_DPB_SUPPORTED_2 2
1441/** Bit 4 - 7 - Indicates whether QARMA5 algorithm is implemented in the PE for address authentication. */
1442#define ARMV8_ID_AA64ISAR1_EL1_APA_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1443#define ARMV8_ID_AA64ISAR1_EL1_APA_SHIFT 4
1444/** Address Authentication using the QARMA5 algorithm is not implemented. */
1445# define ARMV8_ID_AA64ISAR1_EL1_APA_NOT_IMPL 0
1446/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA5). */
1447# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH 1
1448/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA5). */
1449# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_EPAC 2
1450/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA5). */
1451# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_PAUTH2 3
1452/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA5). */
1453# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPAC 4
1454/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA5). */
1455# define ARMV8_ID_AA64ISAR1_EL1_APA_SUPPORTED_FPACCOMBINE 5
1456/** Bit 8 - 11 - Indicates whether an implementation defined algorithm is implemented in the PE for address authentication. */
1457#define ARMV8_ID_AA64ISAR1_EL1_API_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1458#define ARMV8_ID_AA64ISAR1_EL1_API_SHIFT 8
1459/** Address Authentication using the QARMA5 algorithm is not implemented. */
1460# define ARMV8_ID_AA64ISAR1_EL1_API_NOT_IMPL 0
1461/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACIMP). */
1462# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH 1
1463/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACIMP). */
1464# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_EPAC 2
1465/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACIMP). */
1466# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_PAUTH2 3
1467/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACIMP). */
1468# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPAC 4
1469/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACIMP). */
1470# define ARMV8_ID_AA64ISAR1_EL1_API_SUPPORTED_FPACCOMBINE 5
1471/** Bit 12 - 15 - Indicates support for JavaScript conversion from double precision floating values to integers in AArch64 state. */
1472#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1473#define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SHIFT 12
1474/** No FJCVTZS instruction implemented. */
1475# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_NOT_IMPL 0
1476/** FJCVTZS instruction implemented (FEAT_JSCVT). */
1477# define ARMV8_ID_AA64ISAR1_EL1_FJCVTZS_SUPPORTED 1
1478/** Bit 16 - 19 - Indicates support for CRC32 instructions in AArch64 state. */
1479#define ARMV8_ID_AA64ISAR1_EL1_FCMA_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1480#define ARMV8_ID_AA64ISAR1_EL1_FCMA_SHIFT 16
1481/** No FCMLA and FCADD instructions implemented. */
1482# define ARMV8_ID_AA64ISAR1_EL1_FCMA_NOT_IMPL 0
1483/** FCMLA and FCADD instructions implemented (FEAT_FCMA). */
1484# define ARMV8_ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
1485/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1486#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1487#define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SHIFT 20
1488/** No RCpc instructions implemented. */
1489# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_NOT_IMPL 0
1490/** The no offset LDAPR, LDAPRB and LDAPRH instructions are implemented (FEAT_LRCPC). */
1491# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED 1
1492/** The no offset LDAPR, LDAPRB, LDAPRH, LDAPR and STLR instructions are implemented (FEAT_LRCPC2). */
1493# define ARMV8_ID_AA64ISAR1_EL1_LRCPC_SUPPORTED_2 2
1494/** Bit 24 - 27 - Indicates whether the QARMA5 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1495#define ARMV8_ID_AA64ISAR1_EL1_GPA_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1496#define ARMV8_ID_AA64ISAR1_EL1_GPA_SHIFT 24
1497/** Generic Authentication using the QARMA5 algorithm is not implemented. */
1498# define ARMV8_ID_AA64ISAR1_EL1_GPA_NOT_IMPL 0
1499/** Generic Authentication using the QARMA5 algorithm is implemented (FEAT_PACQARMA5). */
1500# define ARMV8_ID_AA64ISAR1_EL1_GPA_SUPPORTED 1
1501/** Bit 28 - 31 - Indicates whether an implementation defined algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1502#define ARMV8_ID_AA64ISAR1_EL1_GPI_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1503#define ARMV8_ID_AA64ISAR1_EL1_GPI_SHIFT 28
1504/** Generic Authentication using an implementation defined algorithm is not implemented. */
1505# define ARMV8_ID_AA64ISAR1_EL1_GPI_NOT_IMPL 0
1506/** Generic Authentication using an implementation defined algorithm is implemented (FEAT_PACIMP). */
1507# define ARMV8_ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
1508/** Bit 32 - 35 - Indicates support for SHA3 instructions in AArch64 state. */
1509#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1510#define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SHIFT 32
1511/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are not implemented. */
1512# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_NOT_IMPL 0
1513/** FRINT32Z, FRINT32X, FRINT64Z and FRINT64X instructions are implemented (FEAT_FRINTTS). */
1514# define ARMV8_ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
1515/** Bit 36 - 39 - Indicates support for SB instructions in AArch64 state. */
1516#define ARMV8_ID_AA64ISAR1_EL1_SB_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1517#define ARMV8_ID_AA64ISAR1_EL1_SB_SHIFT 36
1518/** No SB instructions implemented. */
1519# define ARMV8_ID_AA64ISAR1_EL1_SB_NOT_IMPL 0
1520/** SB instructions implemented (FEAT_SB). */
1521# define ARMV8_ID_AA64ISAR1_EL1_SB_SUPPORTED 1
1522/** Bit 40 - 43 - Indicates support for prediction invalidation instructions in AArch64 state. */
1523#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1524#define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SHIFT 40
1525/** Prediction invalidation instructions are not implemented. */
1526# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_NOT_IMPL 0
1527/** Prediction invalidation instructions are implemented (FEAT_SPECRES). */
1528# define ARMV8_ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
1529/** Bit 44 - 47 - Indicates support for Advanced SIMD and Floating-point BFloat16 instructions in AArch64 state. */
1530#define ARMV8_ID_AA64ISAR1_EL1_BF16_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1531#define ARMV8_ID_AA64ISAR1_EL1_BF16_SHIFT 44
1532/** BFloat16 instructions are not implemented. */
1533# define ARMV8_ID_AA64ISAR1_EL1_BF16_NOT_IMPL 0
1534/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented (FEAT_BF16). */
1535# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_BF16 1
1536/** BFCVT, BFCVTN, BFCVTN2, BFDOT, BFMLALB, BFMLALT and BFMMLA instructions are implemented and FPCR.EBF is supported (FEAT_EBF16). */
1537# define ARMV8_ID_AA64ISAR1_EL1_BF16_SUPPORTED_EBF16 2
1538/** Bit 48 - 51 - Indicates support for Data Gathering Hint instructions. */
1539#define ARMV8_ID_AA64ISAR1_EL1_DGH_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1540#define ARMV8_ID_AA64ISAR1_EL1_DGH_SHIFT 48
1541/** Data Gathering Hint instructions are not implemented. */
1542# define ARMV8_ID_AA64ISAR1_EL1_DGH_NOT_IMPL 0
1543/** Data Gathering Hint instructions are implemented (FEAT_DGH). */
1544# define ARMV8_ID_AA64ISAR1_EL1_DGH_SUPPORTED 1
1545/** Bit 52 - 55 - Indicates support for Advanced SIMD and Floating-point Int8 matri multiplication instructions. */
1546#define ARMV8_ID_AA64ISAR1_EL1_I8MM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1547#define ARMV8_ID_AA64ISAR1_EL1_I8MM_SHIFT 52
1548/** No Int8 matrix multiplication instructions implemented. */
1549# define ARMV8_ID_AA64ISAR1_EL1_I8MM_NOT_IMPL 0
1550/** SMMLA, SUDOT, UMMLA, USMMLA and USDOT instrutions are implemented (FEAT_I8MM). */
1551# define ARMV8_ID_AA64ISAR1_EL1_I8MM_SUPPORTED 1
1552/** Bit 56 - 59 - Indicates support for the XS attribute, the TLBI and DSB insturctions with the nXS qualifier in AArch64 state. */
1553#define ARMV8_ID_AA64ISAR1_EL1_XS_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1554#define ARMV8_ID_AA64ISAR1_EL1_XS_SHIFT 56
1555/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are not supported. */
1556# define ARMV8_ID_AA64ISAR1_EL1_XS_NOT_IMPL 0
1557/** The XS attribute and the TLBI and DSB instructions with the nXS qualifier are supported (FEAT_XS). */
1558# define ARMV8_ID_AA64ISAR1_EL1_XS_SUPPORTED 1
1559/** Bit 60 - 63 - Indicates support LD64B and ST64B* instructons and the ACCDATA_EL1 register. */
1560#define ARMV8_ID_AA64ISAR1_EL1_LS64_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1561#define ARMV8_ID_AA64ISAR1_EL1_LS64_SHIFT 60
1562/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are not supported. */
1563# define ARMV8_ID_AA64ISAR1_EL1_LS64_NOT_IMPL 0
1564/** The LD64B and ST64B instructions are supported (FEAT_LS64). */
1565# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED 1
1566/** The LD64B, ST64B, ST64BV and associated traps are not supported (FEAT_LS64_V). */
1567# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_V 2
1568/** The LD64B, ST64B, ST64BV and ST64BV0 instructions, the ACCDATA_EL1 register and associated traps are supported (FEAT_LS64_ACCDATA). */
1569# define ARMV8_ID_AA64ISAR1_EL1_LS64_SUPPORTED_ACCDATA 3
1570/** @} */
1571
1572
1573/** @name ID_AA64ISAR2_EL1 - AArch64 Instruction Set Attribute Register 0.
1574 * @{ */
1575/** Bit 0 - 3 - Indicates support for WFET and WFIT instructions in AArch64 state. */
1576#define ARMV8_ID_AA64ISAR2_EL1_WFXT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1577#define ARMV8_ID_AA64ISAR2_EL1_WFXT_SHIFT 0
1578/** WFET and WFIT are not supported. */
1579# define ARMV8_ID_AA64ISAR2_EL1_WFXT_NOT_IMPL 0
1580/** WFET and WFIT are supported (FEAT_WFxT). */
1581# define ARMV8_ID_AA64ISAR2_EL1_WFXT_SUPPORTED 2
1582/** Bit 4 - 7 - Indicates support for 12 bits of mantissa in reciprocal and reciprocal square root instructions in AArch64 state, when FPCR.AH is 1. */
1583#define ARMV8_ID_AA64ISAR2_EL1_RPRES_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1584#define ARMV8_ID_AA64ISAR2_EL1_RPRES_SHIFT 4
1585/** Reciprocal and reciprocal square root estimates give 8 bits of mantissa when FPCR.AH is 1. */
1586# define ARMV8_ID_AA64ISAR2_EL1_RPRES_NOT_IMPL 0
1587/** Reciprocal and reciprocal square root estimates give 12 bits of mantissa when FPCR.AH is 1 (FEAT_RPRES). */
1588# define ARMV8_ID_AA64ISAR2_EL1_RPRES_SUPPORTED 1
1589/** Bit 8 - 11 - Indicates whether the QARMA3 algorithm is implemented in the PE for generic code authentication in AArch64 state. */
1590#define ARMV8_ID_AA64ISAR2_EL1_GPA3_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1591#define ARMV8_ID_AA64ISAR2_EL1_GPA3_SHIFT 8
1592/** Generic Authentication using the QARMA3 algorithm is not implemented. */
1593# define ARMV8_ID_AA64ISAR2_EL1_GPA3_NOT_IMPL 0
1594/** Generic Authentication using the QARMA3 algorithm is implemented (FEAT_PACQARMA3). */
1595# define ARMV8_ID_AA64ISAR2_EL1_GPA3_SUPPORTED 1
1596/** Bit 12 - 15 - Indicates whether QARMA3 algorithm is implemented in the PE for address authentication. */
1597#define ARMV8_ID_AA64ISAR2_EL1_APA3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1598#define ARMV8_ID_AA64ISAR2_EL1_APA3_SHIFT 12
1599/** Address Authentication using the QARMA3 algorithm is not implemented. */
1600# define ARMV8_ID_AA64ISAR2_EL1_APA3_NOT_IMPL 0
1601/** Address Authentication using the QARMA5 algorithm is implemented (FEAT_PAuth, FEAT_PACQARMA3). */
1602# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH 1
1603/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC is supported (FEAT_EPAC, FEAT_PACQARMA3). */
1604# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_EPAC 2
1605/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 is supported (FEAT_PAuth2, FEAT_PACQARMA3). */
1606# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_PAUTH2 3
1607/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and FPAC are supported (FEAT_FPAC, FEAT_PACQARMA3). */
1608# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPAC 4
1609/** Address Authentication using the QARMA5 algorithm is implemented and enhanced PAC 2 and combined FPAC are supported (FEAT_FPACCOMBINE, FEAT_PACQARMA3). */
1610# define ARMV8_ID_AA64ISAR2_EL1_APA3_SUPPORTED_FPACCOMBINE 5
1611/** Bit 16 - 19 - Indicates support for Memory Copy and Memory Set instructions in AArch64 state. */
1612#define ARMV8_ID_AA64ISAR2_EL1_MOPS_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1613#define ARMV8_ID_AA64ISAR2_EL1_MOPS_SHIFT 16
1614/** No Memory Copy and Memory Set instructions implemented. */
1615# define ARMV8_ID_AA64ISAR2_EL1_MOPS_NOT_IMPL 0
1616/** Memory Copy and Memory Set instructions implemented (FEAT_MOPS). */
1617# define ARMV8_ID_AA64ISAR2_EL1_MOPS_SUPPORTED 1
1618/** Bit 20 - 23 - Indicates support for weaker release consistency, RCpc, based model. */
1619#define ARMV8_ID_AA64ISAR2_EL1_BC_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1620#define ARMV8_ID_AA64ISAR2_EL1_BC_SHIFT 20
1621/** BC instruction is not implemented. */
1622# define ARMV8_ID_AA64ISAR2_EL1_BC_NOT_IMPL 0
1623/** BC instruction is implemented (FEAT_HBC). */
1624# define ARMV8_ID_AA64ISAR2_EL1_BC_SUPPORTED 1
1625/** Bit 24 - 27 - Indicates whether the ConstPACField() functions used as part of PAC additions returns FALSE or TRUE. */
1626#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1627#define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_SHIFT 24
1628/** ConstPACField() returns FALSE. */
1629# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_FALSE 0
1630/** ConstPACField() returns TRUE (FEAT_CONSTPACFIELD). */
1631# define ARMV8_ID_AA64ISAR2_EL1_PACFRAC_TRUE 1
1632/* Bit 28 - 63 - Reserved. */
1633/** @} */
1634
1635
1636/** @name ID_AA64PFR0_EL1 - AArch64 Processor Feature Register 0.
1637 * @{ */
1638/** Bit 0 - 3 - EL0 Exception level handling. */
1639#define ARMV8_ID_AA64PFR0_EL1_EL0_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1640#define ARMV8_ID_AA64PFR0_EL1_EL0_SHIFT 0
1641/** EL0 can be executed in AArch64 state only. */
1642# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_ONLY 1
1643/** EL0 can be executed in AArch64 and AArch32 state. */
1644# define ARMV8_ID_AA64PFR0_EL1_EL0_AARCH64_AARCH32 2
1645/** Bit 4 - 7 - EL1 Exception level handling. */
1646#define ARMV8_ID_AA64PFR0_EL1_EL1_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1647#define ARMV8_ID_AA64PFR0_EL1_EL1_SHIFT 4
1648/** EL1 can be executed in AArch64 state only. */
1649# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_ONLY 1
1650/** EL1 can be executed in AArch64 and AArch32 state. */
1651# define ARMV8_ID_AA64PFR0_EL1_EL1_AARCH64_AARCH32 2
1652/** Bit 8 - 11 - EL2 Exception level handling. */
1653#define ARMV8_ID_AA64PFR0_EL1_EL2_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1654#define ARMV8_ID_AA64PFR0_EL1_EL2_SHIFT 8
1655/** EL2 is not implemented. */
1656# define ARMV8_ID_AA64PFR0_EL1_EL2_NOT_IMPL 0
1657/** EL2 can be executed in AArch64 state only. */
1658# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_ONLY 1
1659/** EL2 can be executed in AArch64 and AArch32 state. */
1660# define ARMV8_ID_AA64PFR0_EL1_EL2_AARCH64_AARCH32 2
1661/** Bit 12 - 15 - EL3 Exception level handling. */
1662#define ARMV8_ID_AA64PFR0_EL1_EL3_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1663#define ARMV8_ID_AA64PFR0_EL1_EL3_SHIFT 12
1664/** EL3 is not implemented. */
1665# define ARMV8_ID_AA64PFR0_EL1_EL3_NOT_IMPL 0
1666/** EL3 can be executed in AArch64 state only. */
1667# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_ONLY 1
1668/** EL3 can be executed in AArch64 and AArch32 state. */
1669# define ARMV8_ID_AA64PFR0_EL1_EL3_AARCH64_AARCH32 2
1670/** Bit 16 - 19 - Floating-point support. */
1671#define ARMV8_ID_AA64PFR0_EL1_FP_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1672#define ARMV8_ID_AA64PFR0_EL1_FP_SHIFT 16
1673/** Floating-point is implemented and support single and double precision. */
1674# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP 0
1675/** Floating-point is implemented and support single, double and half precision. */
1676# define ARMV8_ID_AA64PFR0_EL1_FP_IMPL_SP_DP_HP 1
1677/** Floating-point is not implemented. */
1678# define ARMV8_ID_AA64PFR0_EL1_FP_NOT_IMPL 0xf
1679/** Bit 20 - 23 - Advanced SIMD support. */
1680#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1681#define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_SHIFT 20
1682/** Advanced SIMD is implemented and support single and double precision. */
1683# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP 0
1684/** Advanced SIMD is implemented and support single, double and half precision. */
1685# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_IMPL_SP_DP_HP 1
1686/** Advanced SIMD is not implemented. */
1687# define ARMV8_ID_AA64PFR0_EL1_ADVSIMD_NOT_IMPL 0xf
1688/** Bit 24 - 27 - System register GIC CPU interface support. */
1689#define ARMV8_ID_AA64PFR0_EL1_GIC_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1690#define ARMV8_ID_AA64PFR0_EL1_GIC_SHIFT 24
1691/** GIC CPU interface system registers are not implemented. */
1692# define ARMV8_ID_AA64PFR0_EL1_GIC_NOT_IMPL 0
1693/** System register interface to versions 3.0 and 4.0 of the GIC CPU interface is supported. */
1694# define ARMV8_ID_AA64PFR0_EL1_GIC_V3_V4 1
1695/** System register interface to version 4.1 of the GIC CPU interface is supported. */
1696# define ARMV8_ID_AA64PFR0_EL1_GIC_V4_1 3
1697/** Bit 28 - 31 - RAS Extension version. */
1698#define ARMV8_ID_AA64PFR0_EL1_RAS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1699#define ARMV8_ID_AA64PFR0_EL1_RAS_SHIFT 28
1700/** No RAS extension. */
1701# define ARMV8_ID_AA64PFR0_EL1_RAS_NOT_IMPL 0
1702/** RAS Extension implemented. */
1703# define ARMV8_ID_AA64PFR0_EL1_RAS_SUPPORTED 1
1704/** FEAT_RASv1p1 implemented. */
1705# define ARMV8_ID_AA64PFR0_EL1_RAS_V1P1 2
1706/** Bit 32 - 35 - Scalable Vector Extension (SVE) support. */
1707#define ARMV8_ID_AA64PFR0_EL1_SVE_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1708#define ARMV8_ID_AA64PFR0_EL1_SVE_SHIFT 32
1709/** SVE is not supported. */
1710# define ARMV8_ID_AA64PFR0_EL1_SVE_NOT_IMPL 0
1711/** SVE is supported. */
1712# define ARMV8_ID_AA64PFR0_EL1_SVE_SUPPORTED 1
1713/** Bit 36 - 39 - Secure EL2 support. */
1714#define ARMV8_ID_AA64PFR0_EL1_SEL2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1715#define ARMV8_ID_AA64PFR0_EL1_SEL2_SHIFT 36
1716/** Secure EL2 is not supported. */
1717# define ARMV8_ID_AA64PFR0_EL1_SEL2_NOT_IMPL 0
1718/** Secure EL2 is implemented. */
1719# define ARMV8_ID_AA64PFR0_EL1_SEL2_SUPPORTED 1
1720/** Bit 40 - 43 - MPAM support. */
1721#define ARMV8_ID_AA64PFR0_EL1_MPAM_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1722#define ARMV8_ID_AA64PFR0_EL1_MPAM_SHIFT 40
1723/** MPAM extension major version number is 0. */
1724# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V0 0
1725/** MPAM extension major version number is 1. */
1726# define ARMV8_ID_AA64PFR0_EL1_MPAM_MAJOR_V1 1
1727/** Bit 44 - 47 - Activity Monitor Extension support. */
1728#define ARMV8_ID_AA64PFR0_EL1_AMU_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1729#define ARMV8_ID_AA64PFR0_EL1_AMU_SHIFT 44
1730/** Activity Monitor extension is not implemented. */
1731# define ARMV8_ID_AA64PFR0_EL1_AMU_NOT_IMPL 0
1732/** Activity Monitor extension is implemented as of FEAT_AMUv1. */
1733# define ARMV8_ID_AA64PFR0_EL1_AMU_V1 1
1734/** Activity Monitor extension is implemented as of FEAT_AMUv1p1 including virtualization support. */
1735# define ARMV8_ID_AA64PFR0_EL1_AMU_V1P1 2
1736/** Bit 48 - 51 - Data Independent Timing support. */
1737#define ARMV8_ID_AA64PFR0_EL1_DIT_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
1738#define ARMV8_ID_AA64PFR0_EL1_DIT_SHIFT 48
1739/** AArch64 does not guarantee constant execution time of any instructions. */
1740# define ARMV8_ID_AA64PFR0_EL1_DIT_NOT_IMPL 0
1741/** AArch64 provides the PSTATE.DIT mechanism to guarantee constant execution time of certain instructions (FEAT_DIT). */
1742# define ARMV8_ID_AA64PFR0_EL1_DIT_SUPPORTED 1
1743/** Bit 52 - 55 - Realm Management Extension support. */
1744#define ARMV8_ID_AA64PFR0_EL1_RME_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
1745#define ARMV8_ID_AA64PFR0_EL1_RME_SHIFT 52
1746/** Realm Management Extension not implemented. */
1747# define ARMV8_ID_AA64PFR0_EL1_RME_NOT_IMPL 0
1748/** RMEv1 is implemented (FEAT_RME). */
1749# define ARMV8_ID_AA64PFR0_EL1_RME_SUPPORTED 1
1750/** Bit 56 - 59 - Speculative use out of context branch targets support. */
1751#define ARMV8_ID_AA64PFR0_EL1_CSV2_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1752#define ARMV8_ID_AA64PFR0_EL1_CSV2_SHIFT 56
1753/** Implementation does not disclose whether FEAT_CSV2 is implemented. */
1754# define ARMV8_ID_AA64PFR0_EL1_CSV2_NOT_EXPOSED 0
1755/** FEAT_CSV2 is implemented. */
1756# define ARMV8_ID_AA64PFR0_EL1_CSV2_SUPPORTED 1
1757/** FEAT_CSV2_2 is implemented. */
1758# define ARMV8_ID_AA64PFR0_EL1_CSV2_2_SUPPORTED 2
1759/** FEAT_CSV2_3 is implemented. */
1760# define ARMV8_ID_AA64PFR0_EL1_CSV2_3_SUPPORTED 3
1761/** Bit 60 - 63 - Speculative use of faulting data support. */
1762#define ARMV8_ID_AA64PFR0_EL1_CSV3_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1763#define ARMV8_ID_AA64PFR0_EL1_CSV3_SHIFT 60
1764/** Implementation does not disclose whether data loaded under speculation with a permission or domain fault can be used. */
1765# define ARMV8_ID_AA64PFR0_EL1_CSV3_NOT_EXPOSED 0
1766/** FEAT_CSV3 is supported . */
1767# define ARMV8_ID_AA64PFR0_EL1_CSV3_SUPPORTED 1
1768/** @} */
1769
1770
1771/** @name ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1.
1772 * @{ */
1773/** Bit 0 - 3 - Branch Target Identification support. */
1774#define ARMV8_ID_AA64PFR1_EL1_BT_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1775#define ARMV8_ID_AA64PFR1_EL1_BT_SHIFT 0
1776/** The Branch Target Identification mechanism is not implemented. */
1777# define ARMV8_ID_AA64PFR1_EL1_BT_NOT_IMPL 0
1778/** The Branch Target Identifcation mechanism is implemented. */
1779# define ARMV8_ID_AA64PFR1_EL1_BT_SUPPORTED 1
1780/** Bit 4 - 7 - Speculative Store Bypassing control support. */
1781#define ARMV8_ID_AA64PFR1_EL1_SSBS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1782#define ARMV8_ID_AA64PFR1_EL1_SSBS_SHIFT 4
1783/** AArch64 provides no mechanism to control the use of Speculative Store Bypassing. */
1784# define ARMV8_ID_AA64PFR1_EL1_SSBS_NOT_IMPL 0
1785/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe. */
1786# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
1787/** AArch64 provides the PSTATE.SSBS mechanism to mark regions that are Speculative Store Bypass Safe and adds MSR and MRS instructions
1788 * to directly read and write the PSTATE.SSBS field. */
1789# define ARMV8_ID_AA64PFR1_EL1_SSBS_SUPPORTED_MSR_MRS 2
1790/** Bit 8 - 11 - Memory Tagging Extension support. */
1791#define ARMV8_ID_AA64PFR1_EL1_MTE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1792#define ARMV8_ID_AA64PFR1_EL1_MTE_SHIFT 8
1793/** MTE is not implemented. */
1794# define ARMV8_ID_AA64PFR1_EL1_MTE_NOT_IMPL 0
1795/** Instruction only Memory Tagging Extensions implemented. */
1796# define ARMV8_ID_AA64PFR1_EL1_MTE_INSN_ONLY 1
1797/** Full Memory Tagging Extension implemented. */
1798# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL 2
1799/** Full Memory Tagging Extension with asymmetric Tag Check Fault handling implemented. */
1800# define ARMV8_ID_AA64PFR1_EL1_MTE_FULL_ASYM_TAG_FAULT_CHK 3
1801/** Bit 12 - 15 - RAS Extension fractional field. */
1802#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1803#define ARMV8_ID_AA64PFR1_EL1_RASFRAC_SHIFT 12
1804/** RAS Extension is implemented. */
1805# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_IMPL 0
1806/** FEAT_RASv1p1 is implemented. */
1807# define ARMV8_ID_AA64PFR1_EL1_RASFRAC_RASV1P1 1
1808/** Bit 16 - 19 - MPAM minor version number. */
1809#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1810#define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_SHIFT 16
1811/** The minor version of number of the MPAM extension is 0. */
1812# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_0 0
1813/** The minor version of number of the MPAM extension is 1. */
1814# define ARMV8_ID_AA64PFR1_EL1_MPAMFRAC_1 1
1815/* Bit 20 - 23 - Reserved. */
1816/** Bit 24 - 27 - Scalable Matrix Extension support. */
1817#define ARMV8_ID_AA64PFR1_EL1_SME_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1818#define ARMV8_ID_AA64PFR1_EL1_SME_SHIFT 24
1819/** Scalable Matrix Extensions are not implemented. */
1820# define ARMV8_ID_AA64PFR1_EL1_SME_NOT_IMPL 0
1821/** Scalable Matrix Extensions are implemented (FEAT_SME). */
1822# define ARMV8_ID_AA64PFR1_EL1_SME_SUPPORTED 1
1823/** Scalable Matrix Extensions are implemented + SME2 ZT0 register(FEAT_SME2). */
1824# define ARMV8_ID_AA64PFR1_EL1_SME_SME2 2
1825/** Bit 28 - 31 - Random Number trap to EL3 support. */
1826#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1827#define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SHIFT 28
1828/** Trapping of RNDR and RNDRRS to EL3 is not supported. */
1829# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_NOT_IMPL 0
1830/** Trapping of RNDR and RDNRRS to EL3 is supported. */
1831# define ARMV8_ID_AA64PFR1_EL1_RNDRTRAP_SUPPORTED 1
1832/** Bit 32 - 35 - CSV2 fractional field. */
1833#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1834#define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_SHIFT 32
1835/** Either CSV2 not exposed or implementation does not expose whether FEAT_CSV2_1p1 is implemented. */
1836# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_NOT_EXPOSED 0
1837/** FEAT_CSV2_1p1 is implemented. */
1838# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P1 1
1839/** FEAT_CSV2_1p2 is implemented. */
1840# define ARMV8_ID_AA64PFR1_EL1_CSV2FRAC_1P2 2
1841/** Bit 36 - 39 - Non-maskable Interrupt support. */
1842#define ARMV8_ID_AA64PFR1_EL1_NMI_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1843#define ARMV8_ID_AA64PFR1_EL1_NMI_SHIFT 36
1844/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are not supported. */
1845# define ARMV8_ID_AA64PFR1_EL1_NMI_NOT_IMPL 0
1846/** SCTLR_ELx.{SPINTMASK, NMI} and PSTATE.ALLINT and associated instructions are supported (FEAT_NMI). */
1847# define ARMV8_ID_AA64PFR1_EL1_NMI_SUPPORTED 1
1848/** @} */
1849
1850
1851/** @name ID_AA64MMFR0_EL1 - AArch64 Memory Model Feature Register 0.
1852 * @{ */
1853/** Bit 0 - 3 - Physical Address range supported. */
1854#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1855#define ARMV8_ID_AA64MMFR0_EL1_PARANGE_SHIFT 0
1856/** Physical Address range is 32 bits, 4GiB. */
1857# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_32BITS 0
1858/** Physical Address range is 36 bits, 64GiB. */
1859# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_36BITS 1
1860/** Physical Address range is 40 bits, 1TiB. */
1861# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_40BITS 2
1862/** Physical Address range is 42 bits, 4TiB. */
1863# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_42BITS 3
1864/** Physical Address range is 44 bits, 16TiB. */
1865# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_44BITS 4
1866/** Physical Address range is 48 bits, 256TiB. */
1867# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_48BITS 5
1868/** Physical Address range is 52 bits, 4PiB. */
1869# define ARMV8_ID_AA64MMFR0_EL1_PARANGE_52BITS 6
1870/** Bit 4 - 7 - Number of ASID bits. */
1871#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1872#define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_SHIFT 4
1873/** ASID bits is 8. */
1874# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_8 0
1875/** ASID bits is 16. */
1876# define ARMV8_ID_AA64MMFR0_EL1_ASIDBITS_16 2
1877/** Bit 8 - 11 - Indicates support for mixed-endian configuration. */
1878#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
1879#define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SHIFT 8
1880/** No mixed-endian support. */
1881# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_NOT_IMPL 0
1882/** Mixed-endian supported. */
1883# define ARMV8_ID_AA64MMFR0_EL1_BIGEND_SUPPORTED 1
1884/** Bit 12 - 15 - Indicates support for a distinction between Secure and Non-secure Memory. */
1885#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
1886#define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SHIFT 12
1887/** No distinction between Secure and Non-secure Memory supported. */
1888# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_NOT_IMPL 0
1889/** Distinction between Secure and Non-secure Memory supported. */
1890# define ARMV8_ID_AA64MMFR0_EL1_SNSMEM_SUPPORTED 1
1891/** Bit 16 - 19 - Indicates support for mixed-endian at EL0 only. */
1892#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
1893#define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT 16
1894/** No mixed-endian support at EL0. */
1895# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_NOT_IMPL 0
1896/** Mixed-endian support at EL0. */
1897# define ARMV8_ID_AA64MMFR0_EL1_BIGENDEL0_SUPPORTED 1
1898/** Bit 20 - 23 - Indicates support for 16KiB memory translation granule size. */
1899#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
1900#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SHIFT 20
1901/** 16KiB granule size not supported. */
1902# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_NOT_IMPL 0
1903/** 16KiB granule size is supported. */
1904# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED 1
1905/** 16KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1906# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_52BIT 2
1907/** Bit 24 - 27 - Indicates support for 64KiB memory translation granule size. */
1908#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
1909#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SHIFT 24
1910/** 64KiB granule supported. */
1911# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED 0
1912/** 64KiB granule not supported. */
1913# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_NOT_IMPL 0xf
1914/** Bit 28 - 31 - Indicates support for 4KiB memory translation granule size. */
1915#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
1916#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SHIFT 28
1917/** 4KiB granule supported. */
1918# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED 0
1919/** 4KiB granule size is supported and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1920# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_52BIT 1
1921/** 4KiB granule not supported. */
1922# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_NOT_IMPL 0xf
1923/** Bit 32 - 35 - Indicates support for 16KiB granule size at stage 2. */
1924#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
1925#define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 32
1926/** Support for 16KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran16 field. */
1927# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORT_BY_TGRAN16 0
1928/** 16KiB granule not supported at stage 2. */
1929# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_NOT_IMPL 1
1930/** 16KiB granule supported at stage 2. */
1931# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED 2
1932/** 16KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1933# define ARMV8_ID_AA64MMFR0_EL1_TGRAN16_2_SUPPORTED_52BIT 3
1934/** Bit 36 - 39 - Indicates support for 64KiB granule size at stage 2. */
1935#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
1936#define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 36
1937/** Support for 64KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran64 field. */
1938# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORT_BY_TGRAN64 0
1939/** 64KiB granule not supported at stage 2. */
1940# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_NOT_IMPL 1
1941/** 64KiB granule supported at stage 2. */
1942# define ARMV8_ID_AA64MMFR0_EL1_TGRAN64_2_SUPPORTED 2
1943/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
1944#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
1945#define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 40
1946/** Support for 4KiB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran4 field. */
1947# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORT_BY_TGRAN16 0
1948/** 4KiB granule not supported at stage 2. */
1949# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_NOT_IMPL 1
1950/** 4KiB granule supported at stage 2. */
1951# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED 2
1952/** 4KiB granule supported at stage 2 and supports 52-bit input addresses and can describe 52-bit output addresses (FEAT_LPA2). */
1953# define ARMV8_ID_AA64MMFR0_EL1_TGRAN4_2_SUPPORTED_52BIT 3
1954/** Bit 44 - 47 - Indicates support for disabling context synchronizing exception entry and exit. */
1955#define ARMV8_ID_AA64MMFR0_EL1_EXS_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
1956#define ARMV8_ID_AA64MMFR0_EL1_EXS_SHIFT 44
1957/** All exception entries and exits are context synchronization events. */
1958# define ARMV8_ID_AA64MMFR0_EL1_EXS_NOT_IMPL 0
1959/** Non-context synchronizing exception entry and exit are supported (FEAT_ExS). */
1960# define ARMV8_ID_AA64MMFR0_EL1_EXS_SUPPORTED 1
1961/* Bit 48 - 55 - Reserved. */
1962/** Bit 56 - 59 - Indicates the presence of the Fine-Grained Trap controls. */
1963#define ARMV8_ID_AA64MMFR0_EL1_FGT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
1964#define ARMV8_ID_AA64MMFR0_EL1_FGT_SHIFT 56
1965/** Fine-grained trap controls are not implemented. */
1966# define ARMV8_ID_AA64MMFR0_EL1_FGT_NOT_IMPL 0
1967/** Fine-grained trap controls are implemented (FEAT_FGT). */
1968# define ARMV8_ID_AA64MMFR0_EL1_FGT_SUPPORTED 1
1969/** Bit 60 - 63 - Indicates the presence of Enhanced Counter Virtualization. */
1970#define ARMV8_ID_AA64MMFR0_EL1_ECV_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
1971#define ARMV8_ID_AA64MMFR0_EL1_ECV_SHIFT 60
1972/** Enhanced Counter Virtualization is not implemented. */
1973# define ARMV8_ID_AA64MMFR0_EL1_ECV_NOT_IMPL 0
1974/** Enhanced Counter Virtualization is implemented (FEAT_ECV). */
1975# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED 1
1976/** Enhanced Counter Virtualization is implemented and includes support for CNTHCTL_EL2.ECV and CNTPOFF_EL2 (FEAT_ECV). */
1977# define ARMV8_ID_AA64MMFR0_EL1_ECV_SUPPORTED_2 2
1978/** @} */
1979
1980
1981/** @name ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1.
1982 * @{ */
1983/** Bit 0 - 3 - Hardware updates to Access flag and Dirty state in translation tables. */
1984#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
1985#define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SHIFT 0
1986/** Hardware update of the Access flag and dirty state are not supported. */
1987# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_NOT_IMPL 0
1988/** Support for hardware update of the Access flag for Block and Page descriptors. */
1989# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_SUPPORTED 1
1990/** Support for hardware update of the Access flag for Block and Page descriptors, hardware update of dirty state supported. */
1991# define ARMV8_ID_AA64MMFR1_EL1_HAFDBS_DIRTY_SUPPORTED 2
1992/** Bit 4 - 7 - EL1 Exception level handling. */
1993#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
1994#define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_SHIFT 4
1995/** VMID bits is 8. */
1996# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_8 0
1997/** VMID bits is 16 (FEAT_VMID16). */
1998# define ARMV8_ID_AA64MMFR1_EL1_VMIDBITS_16 2
1999/** Bit 8 - 11 - Virtualization Host Extensions support. */
2000#define ARMV8_ID_AA64MMFR1_EL1_VHE_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2001#define ARMV8_ID_AA64MMFR1_EL1_VHE_SHIFT 8
2002/** Virtualization Host Extensions are not supported. */
2003# define ARMV8_ID_AA64MMFR1_EL1_VHE_NOT_IMPL 0
2004/** Virtualization Host Extensions are supported. */
2005# define ARMV8_ID_AA64MMFR1_EL1_VHE_SUPPORTED 1
2006/** Bit 12 - 15 - Hierarchical Permission Disables. */
2007#define ARMV8_ID_AA64MMFR1_EL1_HPDS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2008#define ARMV8_ID_AA64MMFR1_EL1_HPDS_SHIFT 12
2009/** Disabling of hierarchical controls not supported. */
2010# define ARMV8_ID_AA64MMFR1_EL1_HPDS_NOT_IMPL 0
2011/** Disabling of hierarchical controls supported (FEAT_HPDS). */
2012# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
2013/** FEAT_HPDS + possible hardware allocation of bits[62:59] of the translation table descriptors from the final lookup level (FEAT_HPDS2). */
2014# define ARMV8_ID_AA64MMFR1_EL1_HPDS_SUPPORTED_2 2
2015/** Bit 16 - 19 - LORegions support. */
2016#define ARMV8_ID_AA64MMFR1_EL1_LO_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2017#define ARMV8_ID_AA64MMFR1_EL1_LO_SHIFT 16
2018/** LORegions not supported. */
2019# define ARMV8_ID_AA64MMFR1_EL1_LO_NOT_IMPL 0
2020/** LORegions supported. */
2021# define ARMV8_ID_AA64MMFR1_EL1_LO_SUPPORTED 1
2022/** Bit 20 - 23 - Privileged Access Never support. */
2023#define ARMV8_ID_AA64MMFR1_EL1_PAN_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2024#define ARMV8_ID_AA64MMFR1_EL1_PAN_SHIFT 20
2025/** PAN not supported. */
2026# define ARMV8_ID_AA64MMFR1_EL1_PAN_NOT_IMPL 0
2027/** PAN supported (FEAT_PAN). */
2028# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
2029/** PAN supported and AT S1E1RP and AT S1E1WP instructions supported (FEAT_PAN2). */
2030# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_2 2
2031/** PAN supported and AT S1E1RP and AT S1E1WP instructions and SCTRL_EL1.EPAN and SCTRL_EL2.EPAN supported (FEAT_PAN3). */
2032# define ARMV8_ID_AA64MMFR1_EL1_PAN_SUPPORTED_3 3
2033/** Bit 24 - 27 - Describes whether the PE can generate SError interrupt exceptions. */
2034#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2035#define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SHIFT 24
2036/** The PE never generates an SError interrupt due to an External abort on a speculative read. */
2037# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_NOT_IMPL 0
2038/** The PE might generate an SError interrupt due to an External abort on a speculative read. */
2039# define ARMV8_ID_AA64MMFR1_EL1_SPECSEI_SUPPORTED 1
2040/** Bit 28 - 31 - Indicates support for execute-never control distinction by Exception level at stage 2. */
2041#define ARMV8_ID_AA64MMFR1_EL1_XNX_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2042#define ARMV8_ID_AA64MMFR1_EL1_XNX_SHIFT 28
2043/** Distinction between EL0 and EL1 execute-never control at stage 2 not supported. */
2044# define ARMV8_ID_AA64MMFR1_EL1_XNX_NOT_IMPL 0
2045/** Distinction between EL0 and EL1 execute-never control at stage 2 supported (FEAT_XNX). */
2046# define ARMV8_ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
2047/** Bit 32 - 35 - Indicates support for the configurable delayed trapping of WFE. */
2048#define ARMV8_ID_AA64MMFR1_EL1_TWED_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2049#define ARMV8_ID_AA64MMFR1_EL1_TWED_SHIFT 32
2050/** Configurable delayed trapping of WFE is not supported. */
2051# define ARMV8_ID_AA64MMFR1_EL1_TWED_NOT_IMPL 0
2052/** Configurable delayed trapping of WFE is supported (FEAT_TWED). */
2053# define ARMV8_ID_AA64MMFR1_EL1_TWED_SUPPORTED 1
2054/** Bit 36 - 39 - Indicates support for Enhanced Translation Synchronization. */
2055#define ARMV8_ID_AA64MMFR1_EL1_ETS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2056#define ARMV8_ID_AA64MMFR1_EL1_ETS_SHIFT 36
2057/** Enhanced Translation Synchronization is not supported. */
2058# define ARMV8_ID_AA64MMFR1_EL1_ETS_NOT_IMPL 0
2059/** Enhanced Translation Synchronization is implemented. */
2060# define ARMV8_ID_AA64MMFR1_EL1_ETS_SUPPORTED 1
2061/** Bit 40 - 43 - Indicates HCRX_EL2 and its associated EL3 trap support. */
2062#define ARMV8_ID_AA64MMFR1_EL1_HCX_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2063#define ARMV8_ID_AA64MMFR1_EL1_HCX_SHIFT 40
2064/** HCRX_EL2 and its associated EL3 trap are not supported. */
2065# define ARMV8_ID_AA64MMFR1_EL1_HCX_NOT_IMPL 0
2066/** HCRX_EL2 and its associated EL3 trap are supported (FEAT_HCX). */
2067# define ARMV8_ID_AA64MMFR1_EL1_HCX_SUPPORTED 1
2068/** Bit 44 - 47 - Indicates support for FPCR.{AH,FIZ,NEP}. */
2069#define ARMV8_ID_AA64MMFR1_EL1_AFP_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2070#define ARMV8_ID_AA64MMFR1_EL1_AFP_SHIFT 44
2071/** The FPCR.{AH,FIZ,NEP} fields are not supported. */
2072# define ARMV8_ID_AA64MMFR1_EL1_AFP_NOT_IMPL 0
2073/** The FPCR.{AH,FIZ,NEP} fields are supported (FEAT_AFP). */
2074# define ARMV8_ID_AA64MMFR1_EL1_AFP_SUPPORTED 1
2075/** Bit 48 - 51 - Indicates support for intermediate caching of translation table walks. */
2076#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2077#define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_SHIFT 48
2078/** The intermediate caching of translation table walks might include non-coherent physical translation caches. */
2079# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_NON_COHERENT 0
2080/** The intermediate caching of translation table walks does not include non-coherent physical translation caches (FEAT_nTLBPA). */
2081# define ARMV8_ID_AA64MMFR1_EL1_NTLBPA_INCLUDE_COHERENT_ONLY 1
2082/** Bit 52 - 55 - Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state. */
2083#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2084#define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SHIFT 52
2085/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented. */
2086# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_NOT_IMPL 0
2087/** SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are implemented (FEAT_TIDCP1). */
2088# define ARMV8_ID_AA64MMFR1_EL1_TIDCP1_SUPPORTED 1
2089/** Bit 56 - 59 - Indicates support for cache maintenance instruction permission. */
2090#define ARMV8_ID_AA64MMFR1_EL1_CMOW_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2091#define ARMV8_ID_AA64MMFR1_EL1_CMOW_SHIFT 56
2092/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are not implemented. */
2093# define ARMV8_ID_AA64MMFR1_EL1_CMOW_NOT_IMPL 0
2094/** SCTLR_EL1.CMOW, SCTLR_EL2.CMOW and HCRX_EL2.CMOW bits are implemented (FEAT_CMOW). */
2095# define ARMV8_ID_AA64MMFR1_EL1_CMOW_SUPPORTED 1
2096/* Bit 60 - 63 - Reserved. */
2097/** @} */
2098
2099
2100/** @name ID_AA64MMFR2_EL1 - AArch64 Memory Model Feature Register 2.
2101 * @{ */
2102/** Bit 0 - 3 - Indicates support for Common not Private translations. */
2103#define ARMV8_ID_AA64MMFR2_EL1_CNP_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2104#define ARMV8_ID_AA64MMFR2_EL1_CNP_SHIFT 0
2105/** Common not Private translations are not supported. */
2106# define ARMV8_ID_AA64MMFR2_EL1_CNP_NOT_IMPL 0
2107/** Support for Common not Private translations (FEAT_TTNCP). */
2108# define ARMV8_ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
2109/** Bit 4 - 7 - Indicates support for User Access Override. */
2110#define ARMV8_ID_AA64MMFR2_EL1_UAO_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2111#define ARMV8_ID_AA64MMFR2_EL1_UAO_SHIFT 4
2112/** User Access Override is not supported. */
2113# define ARMV8_ID_AA64MMFR2_EL1_UAO_NOT_IMPL 0
2114/** User Access Override is supported (FEAT_UAO). */
2115# define ARMV8_ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
2116/** Bit 8 - 11 - Indicates support for LSMAOE and nTLSMD bits in SCTLR_ELx. */
2117#define ARMV8_ID_AA64MMFR2_EL1_LSM_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2118#define ARMV8_ID_AA64MMFR2_EL1_LSM_SHIFT 8
2119/** LSMAOE and nTLSMD bits are not supported. */
2120# define ARMV8_ID_AA64MMFR2_EL1_LSM_NOT_IMPL 0
2121/** LSMAOE and nTLSMD bits are supported (FEAT_LSMAOC). */
2122# define ARMV8_ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
2123/** Bit 12 - 15 - Indicates support for the IESB bit in SCTLR_ELx registers. */
2124#define ARMV8_ID_AA64MMFR2_EL1_IESB_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2125#define ARMV8_ID_AA64MMFR2_EL1_IESB_SHIFT 12
2126/** IESB bit is not supported. */
2127# define ARMV8_ID_AA64MMFR2_EL1_IESB_NOT_IMPL 0
2128/** IESB bit is supported (FEAT_IESB). */
2129# define ARMV8_ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
2130/** Bit 16 - 19 - Indicates support for larger virtual address. */
2131#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_MASK (RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) | RT_BIT_64(19))
2132#define ARMV8_ID_AA64MMFR2_EL1_VARANGE_SHIFT 16
2133/** Virtual address range is 48 bits. */
2134# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_48BITS 0
2135/** 52 bit virtual addresses supported for 64KiB granules (FEAT_LVA). */
2136# define ARMV8_ID_AA64MMFR2_EL1_VARANGE_52BITS_64KB_GRAN 1
2137/** Bit 20 - 23 - Revised CCSIDR_EL1 register format supported. */
2138#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2139#define ARMV8_ID_AA64MMFR2_EL1_CCIDX_SHIFT 20
2140/** CCSIDR_EL1 register format is 32-bit. */
2141# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_32BIT 0
2142/** CCSIDR_EL1 register format is 64-bit (FEAT_CCIDX). */
2143# define ARMV8_ID_AA64MMFR2_EL1_CCIDX_64BIT 1
2144/** Bit 24 - 27 - Indicates support for nested virtualization. */
2145#define ARMV8_ID_AA64MMFR2_EL1_NV_MASK (RT_BIT_64(24) | RT_BIT_64(25) | RT_BIT_64(26) | RT_BIT_64(27))
2146#define ARMV8_ID_AA64MMFR2_EL1_NV_SHIFT 24
2147/** Nested virtualization is not supported. */
2148# define ARMV8_ID_AA64MMFR2_EL1_NV_NOT_IMPL 0
2149/** The HCR_EL2.{AT,NV1,NV} bits are implemented (FEAT_NV). */
2150# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED 1
2151/** The VNCR_EL2 register and HCR_EL2.{NV2,AT,NV1,NV} bits are implemented (FEAT_NV2). */
2152# define ARMV8_ID_AA64MMFR2_EL1_NV_SUPPORTED_2 2
2153/** Bit 28 - 31 - Indicates support for small translation tables. */
2154#define ARMV8_ID_AA64MMFR2_EL1_ST_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2155#define ARMV8_ID_AA64MMFR2_EL1_ST_SHIFT 28
2156/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 39. */
2157# define ARMV8_ID_AA64MMFR2_EL1_ST_NOT_IMPL 0
2158/** The maximum value of TCR_ELx.{T0SZ,T1SZ} is 48 for 4KiB and 16KiB, and 47 for 64KiB granules (FEAT_TTST). */
2159# define ARMV8_ID_AA64MMFR2_EL1_ST_SUPPORTED 1
2160/** Bit 32 - 35 - Indicates support for unaligned single-copy atomicity and atomic functions. */
2161#define ARMV8_ID_AA64MMFR2_EL1_AT_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2162#define ARMV8_ID_AA64MMFR2_EL1_AT_SHIFT 32
2163/** Unaligned single-copy atomicity and atomic functions are not supported. */
2164# define ARMV8_ID_AA64MMFR2_EL1_AT_NOT_IMPL 0
2165/** Unaligned single-copy atomicity and atomic functions are supported (FEAT_LSE2). */
2166# define ARMV8_ID_AA64MMFR2_EL1_AT_SUPPORTED 1
2167/** Bit 36 - 39 - Indicates value of ESR_ELx.EC that reports an exception generated by a read access to the feature ID space. */
2168#define ARMV8_ID_AA64MMFR2_EL1_IDS_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2169#define ARMV8_ID_AA64MMFR2_EL1_IDS_SHIFT 36
2170/** ESR_ELx.EC is 0 for traps generated by a read access to the feature ID space. */
2171# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_0 0
2172/** ESR_ELx.EC is 0x18 for traps generated by a read access to the feature ID space (FEAT_IDST). */
2173# define ARMV8_ID_AA64MMFR2_EL1_IDS_EC_18H 1
2174/** Bit 40 - 43 - Indicates support for the HCR_EL2.FWB bit. */
2175#define ARMV8_ID_AA64MMFR2_EL1_FWB_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2176#define ARMV8_ID_AA64MMFR2_EL1_FWB_SHIFT 40
2177/** HCR_EL2.FWB bit is not supported. */
2178# define ARMV8_ID_AA64MMFR2_EL1_FWB_NOT_IMPL 0
2179/** HCR_EL2.FWB bit is supported (FEAT_S2FWB). */
2180# define ARMV8_ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
2181/* Bit 44 - 47 - Reserved. */
2182/** Bit 48 - 51 - Indicates support for TTL field in address operations. */
2183#define ARMV8_ID_AA64MMFR2_EL1_TTL_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2184#define ARMV8_ID_AA64MMFR2_EL1_TTL_SHIFT 48
2185/** TLB maintenance instructions by address have bits [47:44] Res0. */
2186# define ARMV8_ID_AA64MMFR2_EL1_TTL_NOT_IMPL 0
2187/** TLB maintenance instructions by address have bits [47:44] holding the TTL field (FEAT_TTL). */
2188# define ARMV8_ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
2189/** Bit 52 - 55 - Identification of the hardware requirements of the hardware to have break-before-make sequences when
2190 * changing block size for a translation. */
2191#define ARMV8_ID_AA64MMFR2_EL1_BBM_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2192#define ARMV8_ID_AA64MMFR2_EL1_BBM_SHIFT 52
2193/** Level 0 support for changing block size is supported (FEAT_BBM). */
2194# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL0 0
2195/** Level 1 support for changing block size is supported (FEAT_BBM). */
2196# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL1 1
2197/** Level 2 support for changing block size is supported (FEAT_BBM). */
2198# define ARMV8_ID_AA64MMFR2_EL1_BBM_LVL2 2
2199/** Bit 56 - 59 - Indicates support for Enhanced Virtualization Traps. */
2200#define ARMV8_ID_AA64MMFR2_EL1_EVT_MASK (RT_BIT_64(56) | RT_BIT_64(57) | RT_BIT_64(58) | RT_BIT_64(59))
2201#define ARMV8_ID_AA64MMFR2_EL1_EVT_SHIFT 56
2202/** Enhanced Virtualization Traps are not supported. */
2203# define ARMV8_ID_AA64MMFR2_EL1_EVT_NOT_IMPL 0
2204/** Enhanced Virtualization Traps are supported (FEAT_EVT). */
2205# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED 1
2206/** Enhanced Virtualization Traps are supported with additional traps (FEAT_EVT). */
2207# define ARMV8_ID_AA64MMFR2_EL1_EVT_SUPPORTED_2 2
2208/** Bit 60 - 63 - Indicates support for E0PDx mechanism. */
2209#define ARMV8_ID_AA64MMFR2_EL1_E0PD_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2210#define ARMV8_ID_AA64MMFR2_EL1_E0PD_SHIFT 60
2211/** E0PDx mechanism is not supported. */
2212# define ARMV8_ID_AA64MMFR2_EL1_E0PD_NOT_IMPL 0
2213/** E0PDx mechanism is supported (FEAT_E0PD). */
2214# define ARMV8_ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
2215/** @} */
2216
2217
2218/** @name ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0.
2219 * @{ */
2220/** Bit 0 - 3 - Indicates the Debug Architecture version supported. */
2221#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_MASK (RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) | RT_BIT_64(3))
2222#define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_SHIFT 0
2223/** Armv8 debug architecture version. */
2224# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8 6
2225/** Armv8 debug architecture version with virtualization host extensions. */
2226# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8_VHE 7
2227/** Armv8.2 debug architecture version (FEAT_Debugv8p2). */
2228# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p2 8
2229/** Armv8.4 debug architecture version (FEAT_Debugv8p4). */
2230# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p4 9
2231/** Armv8.8 debug architecture version (FEAT_Debugv8p8). */
2232# define ARMV8_ID_AA64DFR0_EL1_DEBUGVER_ARMV8p8 10
2233/** Bit 4 - 7 - Indicates trace support. */
2234#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_MASK (RT_BIT_64(4) | RT_BIT_64(5) | RT_BIT_64(6) | RT_BIT_64(7))
2235#define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SHIFT 4
2236/** Trace unit System registers not implemented. */
2237# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_NOT_IMPL 0
2238/** Trace unit System registers supported. */
2239# define ARMV8_ID_AA64DFR0_EL1_TRACEVER_SUPPORTED 1
2240/** Bit 8 - 11 - Performance Monitors Extension version. */
2241#define ARMV8_ID_AA64DFR0_EL1_PMUVER_MASK (RT_BIT_64(8) | RT_BIT_64(9) | RT_BIT_64(10) | RT_BIT_64(11))
2242#define ARMV8_ID_AA64DFR0_EL1_PMUVER_SHIFT 8
2243/** Performance Monitors Extension not supported. */
2244# define ARMV8_ID_AA64DFR0_EL1_PMUVER_NOT_IMPL 0
2245/** Performance Monitors Extension v3 supported (FEAT_PMUv3). */
2246# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3 1
2247/** Performance Monitors Extension v3 supported (FEAT_PMUv3p1). */
2248# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P1 4
2249/** Performance Monitors Extension v3 supported (FEAT_PMUv3p4). */
2250# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P4 5
2251/** Performance Monitors Extension v3 supported (FEAT_PMUv3p5). */
2252# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P5 6
2253/** Performance Monitors Extension v3 supported (FEAT_PMUv3p7). */
2254# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P7 7
2255/** Performance Monitors Extension v3 supported (FEAT_PMUv3p8). */
2256# define ARMV8_ID_AA64DFR0_EL1_PMUVER_SUPPORTED_V3P8 8
2257/** Bit 12 - 15 - Number of breakpoints, minus 1. */
2258#define ARMV8_ID_AA64DFR0_EL1_BRPS_MASK (RT_BIT_64(12) | RT_BIT_64(13) | RT_BIT_64(14) | RT_BIT_64(15))
2259#define ARMV8_ID_AA64DFR0_EL1_BRPS_SHIFT 12
2260/* Bit 16 - 19 - Reserved 0. */
2261/** Bit 20 - 23 - Number of watchpoints, minus 1. */
2262#define ARMV8_ID_AA64DFR0_EL1_WRPS_MASK (RT_BIT_64(20) | RT_BIT_64(21) | RT_BIT_64(22) | RT_BIT_64(23))
2263#define ARMV8_ID_AA64DFR0_EL1_WRPS_SHIFT 20
2264/* Bit 24 - 27 - Reserved 0. */
2265/** Bit 28 - 31 - Number of context-aware breakpoints. */
2266#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_MASK (RT_BIT_64(28) | RT_BIT_64(29) | RT_BIT_64(30) | RT_BIT_64(31))
2267#define ARMV8_ID_AA64DFR0_EL1_CTXCMPS_SHIFT 28
2268/** Bit 32 - 35 - Statistical Profiling Extension version. */
2269#define ARMV8_ID_AA64DFR0_EL1_PMSVER_MASK (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34) | RT_BIT_64(35))
2270#define ARMV8_ID_AA64DFR0_EL1_PMSVER_SHIFT 32
2271/** Statistical Profiling Extension not implemented. */
2272# define ARMV8_ID_AA64DFR0_EL1_PMSVER_NOT_IMPL 0
2273/** Statistical Profiling Extension supported (FEAT_SPE). */
2274# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED 1
2275/** Statistical Profiling Extension supported, version 1.1 (FEAT_SPEv1p1). */
2276# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P1 2
2277/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p2). */
2278# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P2 3
2279/** Statistical Profiling Extension supported, version 1.2 (FEAT_SPEv1p3). */
2280# define ARMV8_ID_AA64DFR0_EL1_PMSVER_SUPPORTED_V1P3 4
2281/** Bit 36 - 39 - OS Double Lock implemented. */
2282#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_MASK (RT_BIT_64(36) | RT_BIT_64(37) | RT_BIT_64(38) | RT_BIT_64(39))
2283#define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SHIFT 36
2284/** OS Double Lock is not implemented. */
2285# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_NOT_IMPL 0xf
2286/** OS Double Lock is supported (FEAT_DoubleLock). */
2287# define ARMV8_ID_AA64DFR0_EL1_DOUBLELOCK_SUPPORTED 0
2288/** Bit 40 - 43 - Indicates the Armv8.4 self-hosted Trace Extension. */
2289#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_MASK (RT_BIT_64(40) | RT_BIT_64(41) | RT_BIT_64(42) | RT_BIT_64(43))
2290#define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SHIFT 40
2291/** Armv8.4 self-hosted Trace Extension not implemented. */
2292# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_NOT_IMPL 0
2293/** Armv8.4 self-hosted Trace Extension is supported (FEAT_TRF). */
2294# define ARMV8_ID_AA64DFR0_EL1_TRACEFILT_SUPPORTED 1
2295/** Bit 44 - 47 - Indicates support for the Trace Buffer Extension. */
2296#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_MASK (RT_BIT_64(44) | RT_BIT_64(45) | RT_BIT_64(46) | RT_BIT_64(47))
2297#define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SHIFT 44
2298/** Trace Buffer Extension is not implemented. */
2299# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_NOT_IMPL 0
2300/** Trace Buffer Extension is supported (FEAT_TRBE). */
2301# define ARMV8_ID_AA64DFR0_EL1_TRACEBUFFER_SUPPORTED 1
2302/** Bit 48 - 51 - Indicates support for the multi-threaded PMU extension. */
2303#define ARMV8_ID_AA64DFR0_EL1_MTPMU_MASK (RT_BIT_64(48) | RT_BIT_64(49) | RT_BIT_64(50) | RT_BIT_64(51))
2304#define ARMV8_ID_AA64DFR0_EL1_MTPMU_SHIFT 48
2305/** Multi-threaded PMU extension is not implemented. */
2306# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL 0
2307/** Multi-threaded PMU extension is supported (FEAT_MTPMU). */
2308# define ARMV8_ID_AA64DFR0_EL1_MTPMU_SUPPORTED 1
2309/** Multi-threaded PMU extension is not implemented. */
2310# define ARMV8_ID_AA64DFR0_EL1_MTPMU_NOT_IMPL_2 0xf
2311/** Bit 52 - 55 - Indicates support for the Branch Record Buffer extension. */
2312#define ARMV8_ID_AA64DFR0_EL1_BRBE_MASK (RT_BIT_64(52) | RT_BIT_64(53) | RT_BIT_64(54) | RT_BIT_64(55))
2313#define ARMV8_ID_AA64DFR0_EL1_BRBE_SHIFT 52
2314/** Branch Record Buffer extension is not implemented. */
2315# define ARMV8_ID_AA64DFR0_EL1_BRBE_NOT_IMPL 0
2316/** Branch Record Buffer extension is supported (FEAT_BRBE). */
2317# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED 1
2318/** Branch Record Buffer extension is supported and supports branch recording at EL3 (FEAT_BRBEv1p1). */
2319# define ARMV8_ID_AA64DFR0_EL1_BRBE_SUPPORTED_V1P1 2
2320/* Bit 56 - 59 - Reserved. */
2321/** Bit 60 - 63 - Indicates support for Zero PMU event counters for guest operating systems. */
2322#define ARMV8_ID_AA64DFR0_EL1_HPMN0_MASK (RT_BIT_64(60) | RT_BIT_64(61) | RT_BIT_64(62) | RT_BIT_64(63))
2323#define ARMV8_ID_AA64DFR0_EL1_HPMN0_SHIFT 60
2324/** Setting MDCE_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior. */
2325# define ARMV8_ID_AA64DFR0_EL1_HPMN0_NOT_IMPL 0
2326/** Setting MDCE_EL2.HPMN to zero has defined behavior (FEAT_HPMN0). */
2327# define ARMV8_ID_AA64DFR0_EL1_HPMN0_SUPPORTED 1
2328/** @} */
2329
2330
2331#if (!defined(VBOX_FOR_DTRACE_LIB) && defined(__cplusplus) && !defined(ARMV8_WITHOUT_MK_INSTR)) || defined(DOXYGEN_RUNNING)
2332/** @defgroup grp_rt_armv8_mkinstr Instruction Encoding Helpers
2333 * @ingroup grp_rt_armv8
2334 *
2335 * A few inlined functions and macros for assiting in encoding common ARMv8
2336 * instructions.
2337 *
2338 * @{ */
2339
2340/** A64: Official NOP instruction. */
2341#define ARMV8_A64_INSTR_NOP UINT32_C(0xd503201f)
2342/** A64: Return instruction. */
2343#define ARMV8_A64_INSTR_RET UINT32_C(0xd65f03c0)
2344/** A64: Return instruction with LR pointer authentication using SP and key A. */
2345#define ARMV8_A64_INSTR_RETAA UINT32_C(0xd65f0bff)
2346/** A64: Return instruction with LR pointer authentication using SP and key B. */
2347#define ARMV8_A64_INSTR_RETAB UINT32_C(0xd65f0fff)
2348/** A64: Insert pointer authentication code into X17 using X16 and key B. */
2349#define ARMV8_A64_INSTR_PACIB1716 UINT32_C(0xd503215f)
2350/** A64: Insert pointer authentication code into LR using SP and key B. */
2351#define ARMV8_A64_INSTR_PACIBSP UINT32_C(0xd503237f)
2352/** A64: Insert pointer authentication code into LR using XZR and key B. */
2353#define ARMV8_A64_INSTR_PACIBZ UINT32_C(0xd503235f)
2354/** A64: Invert the carry flag (PSTATE.C). */
2355#define ARMV8_A64_INSTR_CFINV UINT32_C(0xd500401f)
2356
2357
2358typedef enum
2359{
2360 /** Add @a iImm7*sizeof(reg) to @a iBaseReg after the store/load,
2361 * and update the register. */
2362 kArm64InstrStLdPairType_PostIndex = 1,
2363 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2364 * but don't update the register. */
2365 kArm64InstrStLdPairType_Signed = 2,
2366 /** Add @a iImm7*sizeof(reg) to @a iBaseReg before the store/load,
2367 * and update the register. */
2368 kArm64InstrStLdPairType_PreIndex = 3
2369} ARM64INSTRSTLDPAIRTYPE;
2370
2371/**
2372 * A64: Encodes either stp (store register pair) or ldp (load register pair).
2373 *
2374 * @returns The encoded instruction.
2375 * @param fLoad true for ldp, false of stp.
2376 * @param u2Opc When @a fSimdFp is @c false:
2377 * - 0 for 32-bit GPRs (Wt).
2378 * - 1 for encoding stgp or ldpsw.
2379 * - 2 for 64-bit GRPs (Xt).
2380 * - 3 illegal.
2381 * When @a fSimdFp is @c true:
2382 * - 0 for 32-bit SIMD&FP registers (St).
2383 * - 1 for 64-bit SIMD&FP registers (Dt).
2384 * - 2 for 128-bit SIMD&FP regsiters (Qt).
2385 * @param enmType The instruction variant wrt addressing and updating of the
2386 * addressing register.
2387 * @param iReg1 The first register to store/load.
2388 * @param iReg2 The second register to store/load.
2389 * @param iBaseReg The base register to use when addressing. SP is allowed.
2390 * @param iImm7 Signed addressing immediate value scaled, range -64..63,
2391 * will be multiplied by the register size.
2392 * @param fSimdFp true for SIMD&FP registers, false for GPRs and
2393 * stgp/ldpsw instructions.
2394 */
2395DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdPair(bool fLoad, uint32_t u2Opc, ARM64INSTRSTLDPAIRTYPE enmType,
2396 uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2397 bool fSimdFp = false)
2398{
2399 Assert(u2Opc < 3); Assert(iReg1 <= 31); Assert(iReg2 <= 31); Assert(iBaseReg <= 31); Assert(iImm7 < 64 && iImm7 >= -64);
2400 return (u2Opc << 30)
2401 | UINT32_C(0x28000000) /* 0b101000000000000000000000000000 */
2402 | ((uint32_t)fSimdFp << 26) /* VR bit, see "Top-level encodings for A64" */
2403 | ((uint32_t)enmType << 23)
2404 | ((uint32_t)fLoad << 22)
2405 | (((uint32_t)iImm7 & UINT32_C(0x7f)) << 15)
2406 | (iReg2 << 10)
2407 | (iBaseReg << 5)
2408 | iReg1;
2409}
2410
2411
2412/** A64: ldp x1, x2, [x3] */
2413DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2414 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2415 bool f64Bit = true)
2416{
2417 return Armv8A64MkInstrStLdPair(true /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2418}
2419
2420
2421/** A64: stp x1, x2, [x3] */
2422DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStPairGpr(uint32_t iReg1, uint32_t iReg2, uint32_t iBaseReg, int32_t iImm7 = 0,
2423 ARM64INSTRSTLDPAIRTYPE enmType = kArm64InstrStLdPairType_Signed,
2424 bool f64Bit = true)
2425{
2426 return Armv8A64MkInstrStLdPair(false /*fLoad*/, f64Bit ? 2 : 0, enmType, iReg1, iReg2, iBaseReg, iImm7);
2427}
2428
2429
2430typedef enum /* Size VR Opc */
2431{ /* \ | / */
2432 kArmv8A64InstrLdStType_Mask_Size = 0x300,
2433 kArmv8A64InstrLdStType_Mask_VR = 0x010,
2434 kArmv8A64InstrLdStType_Mask_Opc = 0x003,
2435 kArmv8A64InstrLdStType_Shift_Size = 8,
2436 kArmv8A64InstrLdStType_Shift_VR = 4,
2437 kArmv8A64InstrLdStType_Shift_Opc = 0,
2438
2439 kArmv8A64InstrLdStType_St_Byte = 0x000,
2440 kArmv8A64InstrLdStType_Ld_Byte = 0x001,
2441 kArmv8A64InstrLdStType_Ld_SignByte64 = 0x002,
2442 kArmv8A64InstrLdStType_Ld_SignByte32 = 0x003,
2443
2444 kArmv8A64InstrLdStType_St_Half = 0x100, /**< Half = 16-bit */
2445 kArmv8A64InstrLdStType_Ld_Half = 0x101, /**< Half = 16-bit */
2446 kArmv8A64InstrLdStType_Ld_SignHalf64 = 0x102, /**< Half = 16-bit */
2447 kArmv8A64InstrLdStType_Ld_SignHalf32 = 0x103, /**< Half = 16-bit */
2448
2449 kArmv8A64InstrLdStType_St_Word = 0x200, /**< Word = 32-bit */
2450 kArmv8A64InstrLdStType_Ld_Word = 0x201, /**< Word = 32-bit */
2451 kArmv8A64InstrLdStType_Ld_SignWord64 = 0x202, /**< Word = 32-bit */
2452
2453 kArmv8A64InstrLdStType_St_Dword = 0x300, /**< Dword = 64-bit */
2454 kArmv8A64InstrLdStType_Ld_Dword = 0x301, /**< Dword = 64-bit */
2455
2456 kArmv8A64InstrLdStType_Prefetch = 0x302, /**< Not valid in all variations, check docs. */
2457
2458 kArmv8A64InstrLdStType_St_Vr_Byte = 0x010,
2459 kArmv8A64InstrLdStType_Ld_Vr_Byte = 0x011,
2460 kArmv8A64InstrLdStType_St_Vr_128 = 0x012,
2461 kArmv8A64InstrLdStType_Ld_Vr_128 = 0x013,
2462
2463 kArmv8A64InstrLdStType_St_Vr_Half = 0x110, /**< Half = 16-bit */
2464 kArmv8A64InstrLdStType_Ld_Vr_Half = 0x111, /**< Half = 16-bit */
2465
2466 kArmv8A64InstrLdStType_St_Vr_Word = 0x210, /**< Word = 32-bit */
2467 kArmv8A64InstrLdStType_Ld_Vr_Word = 0x211, /**< Word = 32-bit */
2468
2469 kArmv8A64InstrLdStType_St_Vr_Dword = 0x310, /**< Dword = 64-bit */
2470 kArmv8A64InstrLdStType_Ld_Vr_Dword = 0x311 /**< Dword = 64-bit */
2471
2472} ARMV8A64INSTRLDSTTYPE;
2473/** Checks if a ARMV8A64INSTRLDSTTYPE value is a store operation or not. */
2474#define ARMV8A64INSTRLDSTTYPE_IS_STORE(a_enmLdStType) (((unsigned)a_enmLdStType & (unsigned)kArmv8A64InstrLdStType_Mask_Opc) == 0)
2475
2476
2477/**
2478 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2479 *
2480 * @returns The encoded instruction.
2481 * @param u32Opcode The base opcode value.
2482 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2483 * @param iReg The register to load into / store.
2484 * @param iBaseReg The base register to use when addressing. SP is allowed.
2485 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2486 */
2487DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdImm9Ex(uint32_t u32Opcode, ARMV8A64INSTRLDSTTYPE enmType,
2488 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2489{
2490 Assert(i9ImmDisp >= -256 && i9ImmDisp < 256); Assert(iReg < 32); Assert(iBaseReg < 32);
2491 return u32Opcode
2492 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2493 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2494 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2495 | (((uint32_t)i9ImmDisp & UINT32_C(0x1ff)) << 12)
2496 | (iBaseReg << 5)
2497 | iReg;
2498}
2499
2500
2501/**
2502 * A64: Encodes load/store with unscaled 9-bit signed immediate.
2503 *
2504 * @returns The encoded instruction.
2505 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2506 * @param iReg The register to load into / store.
2507 * @param iBaseReg The base register to use when addressing. SP is allowed.
2508 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2509 */
2510DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSturLdur(ARMV8A64INSTRLDSTTYPE enmType,
2511 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2512{
2513 /* 3 2 1 0 */
2514 /* 10987654321098765432109876543210 */
2515 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000000) /* 0b00111000000000000000000000000000 */,
2516 enmType, iReg, iBaseReg, i9ImmDisp);
2517}
2518
2519/**
2520 * A64: Encodes load/store with unscaled 9-bit signed immediate, post-indexed.
2521 *
2522 * @returns The encoded instruction.
2523 * @param enmType The load/store instruction type. Prefech not valid.
2524 * @param iReg The register to load into / store.
2525 * @param iBaseReg The base register to use when addressing. SP is allowed.
2526 * Written back.
2527 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2528 */
2529DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPostIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2530 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2531{
2532 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2533 /* 10987654321098765432109876543210 */
2534 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000400) /* 0b00111000000000000000010000000000 */,
2535 enmType, iReg, iBaseReg, i9ImmDisp);
2536}
2537
2538/**
2539 * A64: Encodes load/store with unscaled 9-bit signed immediate, pre-indexed
2540 *
2541 * @returns The encoded instruction.
2542 * @param enmType The load/store instruction type. Prefech valid (PRFUM)
2543 * @param iReg The register to load into / store.
2544 * @param iBaseReg The base register to use when addressing. SP is allowed.
2545 * Written back.
2546 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2547 */
2548DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStrLdrPreIndex9(ARMV8A64INSTRLDSTTYPE enmType,
2549 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2550{
2551 Assert(enmType != kArmv8A64InstrLdStType_Prefetch); /* 3 2 1 0 */
2552 /* 10987654321098765432109876543210 */
2553 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000c00) /* 0b00111000000000000000110000000000 */,
2554 enmType, iReg, iBaseReg, i9ImmDisp);
2555}
2556
2557/**
2558 * A64: Encodes unprivileged load/store with unscaled 9-bit signed immediate.
2559 *
2560 * @returns The encoded instruction.
2561 * @param enmType The load/store instruction type. Prefech not valid,
2562 * nor any SIMD&FP variants.
2563 * @param iReg The register to load into / store.
2564 * @param iBaseReg The base register to use when addressing. SP is allowed.
2565 * @param i9ImmDisp The 9-bit signed addressing displacement. Unscaled.
2566 */
2567DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSttrLdtr(ARMV8A64INSTRLDSTTYPE enmType,
2568 uint32_t iReg, uint32_t iBaseReg, int32_t i9ImmDisp = 0)
2569{
2570 Assert(enmType != kArmv8A64InstrLdStType_Prefetch);
2571 Assert(!((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR));
2572 /* 3 2 1 0 */
2573 /* 10987654321098765432109876543210 */
2574 return Armv8A64MkInstrStLdImm9Ex(UINT32_C(0x38000800) /* 0b00111000000000000000100000000000 */,
2575 enmType, iReg, iBaseReg, i9ImmDisp);
2576}
2577
2578
2579/**
2580 * A64: Encodes load/store w/ scaled 12-bit unsigned address displacement.
2581 *
2582 * @returns The encoded instruction.
2583 * @param enmType The load/store instruction type. Prefech not valid,
2584 * nor any SIMD&FP variants.
2585 * @param iReg The register to load into / store.
2586 * @param iBaseReg The base register to use when addressing. SP is allowed.
2587 * @param u12ImmDisp Addressing displacement, scaled by size.
2588 */
2589DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRUOff(ARMV8A64INSTRLDSTTYPE enmType,
2590 uint32_t iReg, uint32_t iBaseReg, uint32_t u12ImmDisp)
2591{
2592 Assert(u12ImmDisp < 4096U);
2593 Assert(iReg < 32); /* 3 2 1 0 */
2594 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2595 return UINT32_C(0x39000000) /* 0b00111001000000000000000000000000 */
2596 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2597 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2598 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2599 | (u12ImmDisp << 10)
2600 | (iBaseReg << 5)
2601 | iReg;
2602}
2603
2604typedef enum
2605{
2606 kArmv8A64InstrLdStExtend_Uxtw = 2, /**< Zero-extend (32-bit) word. */
2607 kArmv8A64InstrLdStExtend_Lsl = 3, /**< Shift left (64-bit). */
2608 kArmv8A64InstrLdStExtend_Sxtw = 6, /**< Sign-extend (32-bit) word. */
2609 kArmv8A64InstrLdStExtend_Sxtx = 7 /**< Sign-extend (64-bit) dword (to 128-bit SIMD&FP reg, presumably). */
2610} ARMV8A64INSTRLDSTEXTEND;
2611
2612/**
2613 * A64: Encodes load/store w/ index register.
2614 *
2615 * @returns The encoded instruction.
2616 * @param enmType The load/store instruction type.
2617 * @param iReg The register to load into / store.
2618 * @param iBaseReg The base register to use when addressing. SP is allowed.
2619 * @param iRegIndex The index register.
2620 * @param enmExtend The extending to apply to @a iRegIndex.
2621 * @param fShifted Whether to shift the index. The shift amount corresponds
2622 * to the access size (thus irrelevant for byte accesses).
2623 */
2624DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrStLdRegIdx(ARMV8A64INSTRLDSTTYPE enmType,
2625 uint32_t iReg, uint32_t iBaseReg, uint32_t iRegIndex,
2626 ARMV8A64INSTRLDSTEXTEND enmExtend = kArmv8A64InstrLdStExtend_Lsl,
2627 bool fShifted = false)
2628{
2629 Assert(iRegIndex < 32);
2630 Assert(iReg < 32); /* 3 2 1 0 */
2631 Assert(iBaseReg < 32); /* 10987654321098765432109876543210 */
2632 return UINT32_C(0x38200800) /* 0b00111000001000000000100000000000 */
2633 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Size) << (30 - kArmv8A64InstrLdStType_Shift_Size))
2634 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_VR) << (26 - kArmv8A64InstrLdStType_Shift_VR))
2635 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdStType_Mask_Opc) << (22 - kArmv8A64InstrLdStType_Shift_Opc))
2636 | (iRegIndex << 16)
2637 | ((uint32_t)enmExtend << 13)
2638 | ((uint32_t)fShifted << 12)
2639 | (iBaseReg << 5)
2640 | iReg;
2641}
2642
2643typedef enum /* VR Opc */
2644{ /* \ | */
2645 kArmv8A64InstrLdrLitteral_Mask_Vr = 0x10,
2646 kArmv8A64InstrLdrLitteral_Mask_Opc = 0x03,
2647 kArmv8A64InstrLdrLitteral_Shift_Vr = 4,
2648 kArmv8A64InstrLdrLitteral_Shift_Opc = 0,
2649
2650 kArmv8A64InstrLdrLitteral_Word = 0x00, /**< word = 32-bit */
2651 kArmv8A64InstrLdrLitteral_Dword = 0x01, /**< dword = 64-bit */
2652 kArmv8A64InstrLdrLitteral_SignWord64 = 0x02, /**< Loads word, signextending it to 64-bit */
2653 kArmv8A64InstrLdrLitteral_Prefetch = 0x03, /**< prfm */
2654
2655 kArmv8A64InstrLdrLitteral_Vr_Word = 0x10, /**< word = 32-bit */
2656 kArmv8A64InstrLdrLitteral_Vr_Dword = 0x11, /**< dword = 64-bit */
2657 kArmv8A64InstrLdrLitteral_Vr_128 = 0x12
2658} ARMV8A64INSTRLDRLITTERAL;
2659
2660
2661/**
2662 * A64: Encodes load w/ a PC relative 19-bit signed immediate.
2663 *
2664 * @returns The encoded instruction.
2665 * @param enmType The load instruction type.
2666 * @param iReg The register to load into.
2667 * @param i19Imm The signed immediate value, multiplied by 4 regardless
2668 * of access size.
2669 */
2670DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLdrLitteral(ARMV8A64INSTRLDRLITTERAL enmType, uint32_t iReg, int32_t i19Imm)
2671{
2672 Assert(i19Imm >= -262144 && i19Imm < 262144);
2673 Assert(iReg < 32); /* 3 2 1 0 */
2674 /* 10987654321098765432109876543210 */
2675 return UINT32_C(0x30000000) /* 0b00110000000000000000000000000000 */
2676 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Vr) << (26 - kArmv8A64InstrLdrLitteral_Shift_Vr))
2677 | (((uint32_t)enmType & (uint32_t)kArmv8A64InstrLdrLitteral_Mask_Opc) << (30 - kArmv8A64InstrLdrLitteral_Shift_Opc))
2678 | (((uint32_t)i19Imm & UINT32_C(0x00ffffe0)) << 5)
2679 | iReg;
2680}
2681
2682
2683typedef enum
2684{
2685 kArmv8A64InstrMovWide_Not = 0, /**< MOVN - reg = ~(imm16 << hw*16; */
2686 kArmv8A64InstrMovWide_Zero = 2, /**< MOVZ - reg = imm16 << hw*16; */
2687 kArmv8A64InstrMovWide_Keep = 3 /**< MOVK - keep the other halfwords. */
2688} ARMV8A64INSTRMOVWIDE;
2689
2690/**
2691 * A64: Encode a move wide immediate instruction.
2692 *
2693 * @returns The encoded instruction.
2694 * @param enmType The load instruction type.
2695 * @param iRegDst The register to mov the immediate into.
2696 * @param uImm16 The immediate value.
2697 * @param iHalfWord Which of the 4 (@a f64Bit = true) or 2 register (16-bit)
2698 * half-words to target:
2699 * - 0 for bits 15:00,
2700 * - 1 for bits 31:16,
2701 * - 2 for bits 47:32 (f64Bit=true only),
2702 * - 3 for bits 63:48 (f64Bit=true only).
2703 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit GPRs.
2704 */
2705DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovWide(ARMV8A64INSTRMOVWIDE enmType, uint32_t iRegDst, uint32_t uImm16,
2706 uint32_t iHalfWord = 0, bool f64Bit = true)
2707{
2708 Assert(iRegDst < 32U); Assert(uImm16 <= (uint32_t)UINT16_MAX); Assert(iHalfWord < 2U + (2U * f64Bit));
2709 return ((uint32_t)f64Bit << 31)
2710 | ((uint32_t)enmType << 29)
2711 | UINT32_C(0x12800000)
2712 | (iHalfWord << 21)
2713 | (uImm16 << 5)
2714 | iRegDst;
2715}
2716
2717/** A64: Encodes a MOVN instruction.
2718 * @see Armv8A64MkInstrMovWide for parameter details. */
2719DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovN(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2720{
2721 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Not, iRegDst, uImm16, iHalfWord, f64Bit);
2722}
2723
2724/** A64: Encodes a MOVZ instruction.
2725 * @see Armv8A64MkInstrMovWide for parameter details. */
2726DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovZ(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2727{
2728 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Zero, iRegDst, uImm16, iHalfWord, f64Bit);
2729}
2730
2731/** A64: Encodes a MOVK instruction.
2732 * @see Armv8A64MkInstrMovWide for parameter details. */
2733DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMovK(uint32_t iRegDst, uint32_t uImm16, uint32_t iHalfWord = 0, bool f64Bit = true)
2734{
2735 return Armv8A64MkInstrMovWide(kArmv8A64InstrMovWide_Keep, iRegDst, uImm16, iHalfWord, f64Bit);
2736}
2737
2738
2739typedef enum
2740{
2741 kArmv8A64InstrShift_Lsl = 0,
2742 kArmv8A64InstrShift_Lsr,
2743 kArmv8A64InstrShift_Asr,
2744 kArmv8A64InstrShift_Ror
2745} ARMV8A64INSTRSHIFT;
2746
2747
2748/**
2749 * A64: Encodes a logical instruction with a shifted 2nd register operand.
2750 *
2751 * @returns The encoded instruction.
2752 * @param u2Opc The logical operation to perform.
2753 * @param fNot Whether to complement the 2nd operand.
2754 * @param iRegResult The output register.
2755 * @param iReg1 The 1st register operand.
2756 * @param iReg2Shifted The 2nd register operand, to which the optional
2757 * shifting is applied.
2758 * @param f64Bit true for 64-bit GPRs (default), @c false for 32-bit
2759 * GPRs.
2760 * @param offShift6 The shift amount (default: none).
2761 * @param enmShift The shift operation (default: LSL).
2762 */
2763DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalShiftedReg(uint32_t u2Opc, bool fNot,
2764 uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted,
2765 bool f64Bit, uint32_t offShift6, ARMV8A64INSTRSHIFT enmShift)
2766{
2767 Assert(u2Opc < 4); Assert(offShift6 < (f64Bit ? UINT32_C(64) : UINT32_C(32)));
2768 Assert(iRegResult < 32); Assert(iReg1 < 32); Assert(iReg2Shifted < 32);
2769 return ((uint32_t)f64Bit << 31)
2770 | (u2Opc << 29)
2771 | UINT32_C(0x0a000000)
2772 | ((uint32_t)enmShift << 22)
2773 | ((uint32_t)fNot << 21)
2774 | (iReg2Shifted << 16)
2775 | (offShift6 << 10)
2776 | (iReg1 << 5)
2777 | iRegResult;
2778}
2779
2780
2781/** A64: Encodes an AND instruction.
2782 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2783DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnd(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2784 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2785{
2786 return Armv8A64MkInstrLogicalShiftedReg(0, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2787}
2788
2789
2790/** A64: Encodes an BIC instruction.
2791 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2792DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBic(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2793 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2794{
2795 return Armv8A64MkInstrLogicalShiftedReg(0, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2796}
2797
2798
2799/** A64: Encodes an ORR instruction.
2800 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2801DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrr(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2802 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2803{
2804 return Armv8A64MkInstrLogicalShiftedReg(1, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2805}
2806
2807
2808/** A64: Encodes an MOV instruction.
2809 * This is an alias for "orr dst, xzr, src". */
2810DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMov(uint32_t iRegResult, uint32_t idxRegSrc, bool f64Bit = true)
2811{
2812 return Armv8A64MkInstrOrr(iRegResult, ARMV8_A64_REG_XZR, idxRegSrc, f64Bit);
2813}
2814
2815
2816/** A64: Encodes an ORN instruction.
2817 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2818DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrn(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2819 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2820{
2821 return Armv8A64MkInstrLogicalShiftedReg(1, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2822}
2823
2824
2825/** A64: Encodes an EOR instruction.
2826 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2827DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEor(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2828 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2829{
2830 return Armv8A64MkInstrLogicalShiftedReg(2, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2831}
2832
2833
2834/** A64: Encodes an EON instruction.
2835 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2836DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEon(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2837 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2838{
2839 return Armv8A64MkInstrLogicalShiftedReg(2, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2840}
2841
2842
2843/** A64: Encodes an ANDS instruction.
2844 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2845DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAnds(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2846 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2847{
2848 return Armv8A64MkInstrLogicalShiftedReg(3, false /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2849}
2850
2851
2852/** A64: Encodes an BICS instruction.
2853 * @see Armv8A64MkInstrLogicalShiftedReg for parameter details. */
2854DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBics(uint32_t iRegResult, uint32_t iReg1, uint32_t iReg2Shifted, bool f64Bit = true,
2855 uint32_t offShift6 = 0, ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
2856{
2857 return Armv8A64MkInstrLogicalShiftedReg(3, true /*fNot*/, iRegResult, iReg1, iReg2Shifted, f64Bit, offShift6, enmShift);
2858}
2859
2860
2861
2862/*
2863 * Data processing instructions with two source register operands.
2864 */
2865
2866
2867/** A64: Encodes an SUBP instruction. */
2868DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubP(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2869{
2870 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2871 return UINT32_C(0x80000000)
2872 | UINT32_C(0x1ac00000)
2873 | (UINT32_C(0) << 10)
2874 | (iRegSubtrahend << 16)
2875 | (iRegMinuend << 5)
2876 | iRegResult;
2877}
2878
2879
2880/** A64: Encodes an SUBPS instruction. */
2881DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubPS(uint32_t iRegResult, uint32_t iRegMinuend, uint32_t iRegSubtrahend)
2882{
2883 Assert(iRegResult < 32); Assert(iRegMinuend < 32); Assert(iRegSubtrahend < 32);
2884 return UINT32_C(0x80000000)
2885 | UINT32_C(0x20000000)
2886 | UINT32_C(0x1ac00000)
2887 | (UINT32_C(0) << 10)
2888 | (iRegSubtrahend << 16)
2889 | (iRegMinuend << 5)
2890 | iRegResult;
2891}
2892
2893
2894/** A64: Encodes an UDIV instruction. */
2895DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2896{
2897 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2898 return ((uint32_t)f64Bit << 31)
2899 | UINT32_C(0x1ac00000)
2900 | (UINT32_C(2) << 10)
2901 | (iRegDivisor << 16)
2902 | (iRegDividend << 5)
2903 | iRegResult;
2904}
2905
2906
2907/** A64: Encodes an SDIV instruction. */
2908DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSDiv(uint32_t iRegResult, uint32_t iRegDividend, uint32_t iRegDivisor, bool f64Bit = true)
2909{
2910 Assert(iRegResult < 32); Assert(iRegDividend < 32); Assert(iRegDivisor < 32);
2911 return ((uint32_t)f64Bit << 31)
2912 | UINT32_C(0x1ac00000)
2913 | (UINT32_C(3) << 10)
2914 | (iRegDivisor << 16)
2915 | (iRegDividend << 5)
2916 | iRegResult;
2917}
2918
2919
2920/** A64: Encodes an IRG instruction. */
2921DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrIrg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2922{
2923 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2924 return UINT32_C(0x80000000)
2925 | UINT32_C(0x1ac00000)
2926 | (UINT32_C(4) << 10)
2927 | (iRegSrc2 << 16)
2928 | (iRegSrc1 << 5)
2929 | iRegResult;
2930}
2931
2932
2933/** A64: Encodes a GMI instruction. */
2934DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrGmi(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
2935{
2936 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
2937 return UINT32_C(0x80000000)
2938 | UINT32_C(0x1ac00000)
2939 | (UINT32_C(5) << 10)
2940 | (iRegSrc2 << 16)
2941 | (iRegSrc1 << 5)
2942 | iRegResult;
2943}
2944
2945
2946/** A64: Encodes an LSLV instruction. */
2947DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2948{
2949 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2950 return ((uint32_t)f64Bit << 31)
2951 | UINT32_C(0x1ac00000)
2952 | (UINT32_C(8) << 10)
2953 | (iRegCount << 16)
2954 | (iRegSrc << 5)
2955 | iRegResult;
2956}
2957
2958
2959/** A64: Encodes an LSRV instruction. */
2960DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2961{
2962 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2963 return ((uint32_t)f64Bit << 31)
2964 | UINT32_C(0x1ac00000)
2965 | (UINT32_C(9) << 10)
2966 | (iRegCount << 16)
2967 | (iRegSrc << 5)
2968 | iRegResult;
2969}
2970
2971
2972/** A64: Encodes an ASRV instruction. */
2973DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2974{
2975 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2976 return ((uint32_t)f64Bit << 31)
2977 | UINT32_C(0x1ac00000)
2978 | (UINT32_C(10) << 10)
2979 | (iRegCount << 16)
2980 | (iRegSrc << 5)
2981 | iRegResult;
2982}
2983
2984
2985/** A64: Encodes a RORV instruction. */
2986DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorv(uint32_t iRegResult, uint32_t iRegSrc, uint32_t iRegCount, bool f64Bit = true)
2987{
2988 Assert(iRegResult < 32); Assert(iRegSrc < 32); Assert(iRegCount < 32);
2989 return ((uint32_t)f64Bit << 31)
2990 | UINT32_C(0x1ac00000)
2991 | (UINT32_C(11) << 10)
2992 | (iRegCount << 16)
2993 | (iRegSrc << 5)
2994 | iRegResult;
2995}
2996
2997
2998/** A64: Encodes a PACGA instruction. */
2999DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrPacga(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2)
3000{
3001 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3002 return UINT32_C(0x80000000)
3003 | UINT32_C(0x1ac00000)
3004 | (UINT32_C(12) << 10)
3005 | (iRegSrc2 << 16)
3006 | (iRegSrc1 << 5)
3007 | iRegResult;
3008}
3009
3010
3011/** A64: Encodes a CRC32* instruction. */
3012DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3013{
3014 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3015 return ((uint32_t)(uSize == 3) << 31)
3016 | UINT32_C(0x1ac00000)
3017 | (UINT32_C(16) << 10)
3018 | (uSize << 10)
3019 | (iRegValue << 16)
3020 | (iRegCrc << 5)
3021 | iRegResult;
3022}
3023
3024
3025/** A64: Encodes a CRC32B instruction. */
3026DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32B(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3027{
3028 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 0);
3029}
3030
3031
3032/** A64: Encodes a CRC32H instruction. */
3033DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32H(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3034{
3035 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 1);
3036}
3037
3038
3039/** A64: Encodes a CRC32W instruction. */
3040DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32W(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3041{
3042 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 2);
3043}
3044
3045
3046/** A64: Encodes a CRC32X instruction. */
3047DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32X(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3048{
3049 return Armv8A64MkInstrCrc32(iRegResult, iRegCrc, iRegValue, 3);
3050}
3051
3052
3053/** A64: Encodes a CRC32C* instruction. */
3054DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32c(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue, uint32_t uSize)
3055{
3056 Assert(iRegResult < 32); Assert(iRegCrc < 32); Assert(iRegValue < 32); Assert(uSize < 4);
3057 return ((uint32_t)(uSize == 3) << 31)
3058 | UINT32_C(0x1ac00000)
3059 | (UINT32_C(20) << 10)
3060 | (uSize << 10)
3061 | (iRegValue << 16)
3062 | (iRegCrc << 5)
3063 | iRegResult;
3064}
3065
3066
3067/** A64: Encodes a CRC32B instruction. */
3068DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cB(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3069{
3070 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 0);
3071}
3072
3073
3074/** A64: Encodes a CRC32CH instruction. */
3075DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cH(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3076{
3077 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 1);
3078}
3079
3080
3081/** A64: Encodes a CRC32CW instruction. */
3082DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cW(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3083{
3084 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 2);
3085}
3086
3087
3088/** A64: Encodes a CRC32CX instruction. */
3089DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCrc32cX(uint32_t iRegResult, uint32_t iRegCrc, uint32_t iRegValue)
3090{
3091 return Armv8A64MkInstrCrc32c(iRegResult, iRegCrc, iRegValue, 3);
3092}
3093
3094
3095/** A64: Encodes an SMAX instruction. */
3096DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3097{
3098 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3099 return ((uint32_t)f64Bit << 31)
3100 | UINT32_C(0x1ac00000)
3101 | (UINT32_C(24) << 10)
3102 | (iRegSrc2 << 16)
3103 | (iRegSrc1 << 5)
3104 | iRegResult;
3105}
3106
3107
3108/** A64: Encodes an UMAX instruction. */
3109DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMax(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3110{
3111 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3112 return ((uint32_t)f64Bit << 31)
3113 | UINT32_C(0x1ac00000)
3114 | (UINT32_C(25) << 10)
3115 | (iRegSrc2 << 16)
3116 | (iRegSrc1 << 5)
3117 | iRegResult;
3118}
3119
3120
3121/** A64: Encodes an SMIN instruction. */
3122DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3123{
3124 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3125 return ((uint32_t)f64Bit << 31)
3126 | UINT32_C(0x1ac00000)
3127 | (UINT32_C(26) << 10)
3128 | (iRegSrc2 << 16)
3129 | (iRegSrc1 << 5)
3130 | iRegResult;
3131}
3132
3133
3134/** A64: Encodes an UMIN instruction. */
3135DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUMin(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3136{
3137 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3138 return ((uint32_t)f64Bit << 31)
3139 | UINT32_C(0x1ac00000)
3140 | (UINT32_C(27) << 10)
3141 | (iRegSrc2 << 16)
3142 | (iRegSrc1 << 5)
3143 | iRegResult;
3144}
3145
3146
3147# ifdef IPRT_INCLUDED_asm_h /* don't want this to be automatically included here. */
3148
3149/**
3150 * Converts immS and immR values (to logical instructions) to a 32-bit mask.
3151 *
3152 * @returns The decoded mask.
3153 * @param uImm6SizeLen The immS value from the instruction. (No N part
3154 * here, as that must be zero for instructions
3155 * operating on 32-bit wide registers.)
3156 * @param uImm6Rotations The immR value from the instruction.
3157 */
3158DECLINLINE(uint32_t) Armv8A64ConvertImmRImmS2Mask32(uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3159{
3160 Assert(uImm6SizeLen < 64); Assert(uImm6Rotations < 64);
3161
3162 /* Determine the element size. */
3163 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm6SizeLen ^ 0x3f) - 1U;
3164 Assert(cBitsElementLog2 + 1U != 0U);
3165
3166 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3167 Assert(uImm6Rotations < cBitsElement);
3168
3169 /* Extract the number of bits set to 1: */
3170 unsigned const cBitsSetTo1 = (uImm6SizeLen & (cBitsElement - 1U)) + 1;
3171 Assert(cBitsSetTo1 < cBitsElement);
3172 uint32_t const uElement = RT_BIT_32(cBitsSetTo1) - 1U;
3173
3174 /* Produce the unrotated pattern. */
3175 static const uint32_t s_auReplicate[]
3176 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3177 uint32_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3178
3179 /* Rotate it and return. */
3180 return ASMRotateRightU32(uPattern, uImm6Rotations & (cBitsElement - 1U));
3181}
3182
3183
3184/**
3185 * Converts N+immS and immR values (to logical instructions) to a 64-bit mask.
3186 *
3187 * @returns The decoded mask.
3188 * @param uImm7SizeLen The N:immS value from the instruction.
3189 * @param uImm6Rotations The immR value from the instruction.
3190 */
3191DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uImm7SizeLen, uint32_t uImm6Rotations)
3192{
3193 Assert(uImm7SizeLen < 128); Assert(uImm6Rotations < 64);
3194
3195 /* Determine the element size. */
3196 unsigned const cBitsElementLog2 = ASMBitLastSetU32(uImm7SizeLen ^ 0x3f) - 1U;
3197 Assert(cBitsElementLog2 + 1U != 0U);
3198
3199 unsigned const cBitsElement = RT_BIT_32(cBitsElementLog2);
3200 Assert(uImm6Rotations < cBitsElement);
3201
3202 /* Extract the number of bits set to 1: */
3203 unsigned const cBitsSetTo1 = (uImm7SizeLen & (cBitsElement - 1U)) + 1;
3204 Assert(cBitsSetTo1 < cBitsElement);
3205 uint64_t const uElement = RT_BIT_64(cBitsSetTo1) - 1U;
3206
3207 /* Produce the unrotated pattern. */
3208 static const uint64_t s_auReplicate[]
3209 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3210 uint64_t const uPattern = s_auReplicate[cBitsElementLog2] * uElement;
3211
3212 /* Rotate it and return. */
3213 return ASMRotateRightU64(uPattern, uImm6Rotations & (cBitsElement - 1U));
3214}
3215
3216
3217/**
3218 * Variant of Armv8A64ConvertImmRImmS2Mask64 where the N bit is separate from
3219 * the immS value.
3220 */
3221DECLINLINE(uint64_t) Armv8A64ConvertImmRImmS2Mask64(uint32_t uN, uint32_t uImm6SizeLen, uint32_t uImm6Rotations)
3222{
3223 return Armv8A64ConvertImmRImmS2Mask64((uN << 6) | uImm6SizeLen, uImm6Rotations);
3224}
3225
3226
3227/**
3228 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3229 * 32-bit bitmask to a set of immediates for those instructions.
3230 *
3231 * @returns true if successful, false if not.
3232 * @param fMask The mask value to convert.
3233 * @param puImm6SizeLen Where to return the immS part (N is always zero for
3234 * 32-bit wide masks).
3235 * @param puImm6Rotations Where to return the immR.
3236 */
3237DECLINLINE(bool) Armv8A64ConvertMask32ToImmRImmS(uint32_t fMask, uint32_t *puImm6SizeLen, uint32_t *puImm6Rotations)
3238{
3239 /* Fend off 0 and UINT32_MAX as these cannot be represented. */
3240 if ((uint32_t)(fMask + 1U) <= 1)
3241 return false;
3242
3243 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3244 unsigned const cRor = ASMCountTrailingZerosU32(fMask);
3245 unsigned const cRol = ASMCountLeadingZerosU32(~fMask);
3246 if (cRor)
3247 fMask = ASMRotateRightU32(fMask, cRor);
3248 else
3249 fMask = ASMRotateLeftU32(fMask, cRol);
3250 Assert(fMask & RT_BIT_32(0));
3251 Assert(!(fMask & RT_BIT_32(31)));
3252
3253 /* Count the trailing ones and leading zeros. */
3254 unsigned const cOnes = ASMCountTrailingZerosU32(~fMask);
3255 unsigned const cZeros = ASMCountLeadingZerosU32(fMask);
3256
3257 /* The potential element length is then the sum of the two above. */
3258 unsigned const cBitsElement = cOnes + cZeros;
3259 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3260 return false;
3261
3262 /* Special case: 32 bits element size. Since we're done here. */
3263 if (cBitsElement == 32)
3264 *puImm6SizeLen = cOnes - 1;
3265 else
3266 {
3267 /* Extract the element bits and check that these are replicated in the whole pattern. */
3268 uint32_t const uElement = RT_BIT_32(cOnes) - 1U;
3269 unsigned const cBitsElementLog2 = ASMBitFirstSetU32(cBitsElement) - 1;
3270
3271 static const uint32_t s_auReplicate[]
3272 = { UINT32_MAX, UINT32_MAX / 3, UINT32_MAX / 15, UINT32_MAX / 255, UINT32_MAX / 65535, 1 };
3273 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3274 *puImm6SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3275 else
3276 return false;
3277 }
3278 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3279
3280 return true;
3281}
3282
3283
3284/**
3285 * Helper for Armv8A64MkInstrLogicalImm and friends that tries to convert a
3286 * 64-bit bitmask to a set of immediates for those instructions.
3287 *
3288 * @returns true if successful, false if not.
3289 * @param fMask The mask value to convert.
3290 * @param puImm7SizeLen Where to return the N:immS part.
3291 * @param puImm6Rotations Where to return the immR.
3292 */
3293DECLINLINE(bool) Armv8A64ConvertMask64ToImmRImmS(uint64_t fMask, uint32_t *puImm7SizeLen, uint32_t *puImm6Rotations)
3294{
3295 /* Fend off 0 and UINT64_MAX as these cannot be represented. */
3296 if ((uint64_t)(fMask + 1U) <= 1)
3297 return false;
3298
3299 /* Rotate the value will we get all 1s at the bottom and the zeros at the top. */
3300 unsigned const cRor = ASMCountTrailingZerosU64(fMask);
3301 unsigned const cRol = ASMCountLeadingZerosU64(~fMask);
3302 if (cRor)
3303 fMask = ASMRotateRightU64(fMask, cRor);
3304 else
3305 fMask = ASMRotateLeftU64(fMask, cRol);
3306 Assert(fMask & RT_BIT_64(0));
3307 Assert(!(fMask & RT_BIT_64(63)));
3308
3309 /* Count the trailing ones and leading zeros. */
3310 unsigned const cOnes = ASMCountTrailingZerosU64(~fMask);
3311 unsigned const cZeros = ASMCountLeadingZerosU64(fMask);
3312
3313 /* The potential element length is then the sum of the two above. */
3314 unsigned const cBitsElement = cOnes + cZeros;
3315 if (!RT_IS_POWER_OF_TWO(cBitsElement) || cBitsElement < 2)
3316 return false;
3317
3318 /* Special case: 64 bits element size. Since we're done here. */
3319 if (cBitsElement == 64)
3320 *puImm7SizeLen = (cOnes - 1) | 0x40 /*N*/;
3321 else
3322 {
3323 /* Extract the element bits and check that these are replicated in the whole pattern. */
3324 uint64_t const uElement = RT_BIT_64(cOnes) - 1U;
3325 unsigned const cBitsElementLog2 = ASMBitFirstSetU64(cBitsElement) - 1;
3326
3327 static const uint64_t s_auReplicate[]
3328 = { UINT64_MAX, UINT64_MAX / 3, UINT64_MAX / 15, UINT64_MAX / 255, UINT64_MAX / 65535, UINT64_MAX / UINT32_MAX, 1 };
3329 if (s_auReplicate[cBitsElementLog2] * uElement == fMask)
3330 *puImm7SizeLen = (cOnes - 1) | ((0x3e << cBitsElementLog2) & 0x3f);
3331 else
3332 return false;
3333 }
3334 *puImm6Rotations = cRor ? cBitsElement - cRor : cRol;
3335
3336 return true;
3337}
3338
3339# endif /* IPRT_INCLUDED_asm_h */
3340
3341/**
3342 * A64: Encodes a logical instruction with an complicated immediate mask.
3343 *
3344 * The @a uImm7SizeLen parameter specifies two things:
3345 * 1. the element size and
3346 * 2. the number of bits set to 1 in the pattern.
3347 *
3348 * The element size is extracted by NOT'ing bits 5:0 (excludes the N bit at the
3349 * top) and using the position of the first bit set as a power of two.
3350 *
3351 * | N | 5 | 4 | 3 | 2 | 1 | 0 | element size |
3352 * |---|---|---|---|---|---|---|--------------|
3353 * | 0 | 1 | 1 | 1 | 1 | 0 | x | 2 bits |
3354 * | 0 | 1 | 1 | 1 | 0 | x | x | 4 bits |
3355 * | 0 | 1 | 1 | 0 | x | x | x | 8 bits |
3356 * | 0 | 1 | 0 | x | x | x | x | 16 bits |
3357 * | 0 | 0 | x | x | x | x | x | 32 bits |
3358 * | 1 | x | x | x | x | x | x | 64 bits |
3359 *
3360 * The 'x' forms the number of 1 bits in the pattern, minus one (i.e.
3361 * there is always one zero bit in the pattern).
3362 *
3363 * The @a uImm6Rotations parameter specifies how many bits to the right,
3364 * the element pattern is rotated. The rotation count must be less than the
3365 * element bit count (size).
3366 *
3367 * @returns The encoded instruction.
3368 * @param u2Opc The logical operation to perform.
3369 * @param iRegResult The output register.
3370 * @param iRegSrc The 1st register operand.
3371 * @param uImm7SizeLen The size/pattern length. We've combined the 1-bit N
3372 * field at the top of the 6-bit 'imms' field.
3373 *
3374 * @param uImm6Rotations The rotation count.
3375 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3376 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3377 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3378 */
3379DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLogicalImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3380 uint32_t uImm7SizeLen, uint32_t uImm6Rotations, bool f64Bit)
3381{
3382 Assert(u2Opc < 4); Assert(uImm7SizeLen < (f64Bit ? UINT32_C(0x7f) : UINT32_C(0x3f)));
3383 Assert(uImm6Rotations <= UINT32_C(0x3f)); Assert(iRegResult < 32); Assert(iRegSrc < 32);
3384 return ((uint32_t)f64Bit << 31)
3385 | (u2Opc << 29)
3386 | UINT32_C(0x12000000)
3387 | ((uImm7SizeLen & UINT32_C(0x40)) << (22 - 6))
3388 | (uImm6Rotations << 16)
3389 | ((uImm7SizeLen & UINT32_C(0x3f)) << 10)
3390 | (iRegSrc << 5)
3391 | iRegResult;
3392}
3393
3394
3395/** A64: Encodes an AND instruction w/ complicated immediate mask.
3396 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3397DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndImm(uint32_t iRegResult, uint32_t iRegSrc,
3398 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3399{
3400 return Armv8A64MkInstrLogicalImm(0, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3401}
3402
3403
3404/** A64: Encodes an ORR instruction w/ complicated immediate mask.
3405 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3406DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrOrrImm(uint32_t iRegResult, uint32_t iRegSrc,
3407 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3408{
3409 return Armv8A64MkInstrLogicalImm(1, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3410}
3411
3412
3413/** A64: Encodes an EOR instruction w/ complicated immediate mask.
3414 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3415DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrEorImm(uint32_t iRegResult, uint32_t iRegSrc,
3416 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3417{
3418 return Armv8A64MkInstrLogicalImm(2, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3419}
3420
3421
3422/** A64: Encodes an ANDS instruction w/ complicated immediate mask.
3423 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3424DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAndsImm(uint32_t iRegResult, uint32_t iRegSrc,
3425 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3426{
3427 return Armv8A64MkInstrLogicalImm(3, iRegResult, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3428}
3429
3430
3431/** A64: Encodes an TST instruction w/ complicated immediate mask.
3432 * @see Armv8A64MkInstrLogicalImm for parameter details. */
3433DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTstImm(uint32_t iRegSrc,
3434 uint32_t uImm7SizeLen, uint32_t uImm6Rotations = 0, bool f64Bit = true)
3435{
3436 return Armv8A64MkInstrAndsImm(ARMV8_A64_REG_XZR, iRegSrc, uImm7SizeLen, uImm6Rotations, f64Bit);
3437}
3438
3439
3440/**
3441 * A64: Encodes a bitfield instruction.
3442 *
3443 * @returns The encoded instruction.
3444 * @param u2Opc The bitfield operation to perform.
3445 * @param iRegResult The output register.
3446 * @param iRegSrc The 1st register operand.
3447 * @param cImm6Ror The right rotation count.
3448 * @param uImm6S The leftmost bit to be moved.
3449 * @param f64Bit true for 64-bit GPRs, @c false for 32-bit GPRs.
3450 * @param uN1 This must match @a f64Bit for all instructions
3451 * currently specified.
3452 * @see https://dinfuehr.github.io/blog/encoding-of-immediate-values-on-aarch64/
3453 * https://gist.githubusercontent.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a/raw/1892a274aa3238d55f83eec5b3828da2aec5f229/aarch64-logical-immediates.txt
3454 */
3455DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBitfieldImm(uint32_t u2Opc, uint32_t iRegResult, uint32_t iRegSrc,
3456 uint32_t cImm6Ror, uint32_t uImm6S, bool f64Bit, uint32_t uN1)
3457{
3458 Assert(cImm6Ror <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegResult < 32); Assert(u2Opc < 4);
3459 Assert(uImm6S <= (f64Bit ? UINT32_C(0x3f) : UINT32_C(0x1f))); Assert(iRegSrc < 32); Assert(uN1 <= (unsigned)f64Bit);
3460 return ((uint32_t)f64Bit << 31)
3461 | (u2Opc << 29)
3462 | UINT32_C(0x13000000)
3463 | (uN1 << 22)
3464 | (cImm6Ror << 16)
3465 | (uImm6S << 10)
3466 | (iRegSrc << 5)
3467 | iRegResult;
3468}
3469
3470
3471/** A64: Encodes a SBFM instruction.
3472 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3473DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3474 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3475{
3476 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3477}
3478
3479
3480/** A64: Encodes a SXTB instruction (sign-extend 8-bit value to 32/64-bit).
3481 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3482DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3483{
3484 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 7, f64Bit);
3485}
3486
3487
3488/** A64: Encodes a SXTH instruction (sign-extend 16-bit value to 32/64-bit).
3489 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3490DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = true)
3491{
3492 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 15, f64Bit);
3493}
3494
3495
3496/** A64: Encodes a SXTH instruction (sign-extend 32-bit value to 64-bit).
3497 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3498DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSxtw(uint32_t iRegResult, uint32_t iRegSrc)
3499{
3500 return Armv8A64MkInstrSbfm(iRegResult, iRegSrc, 0, 31, true /*f64Bit*/);
3501}
3502
3503
3504/** A64: Encodes an ASR instruction w/ immediate shift value.
3505 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3506DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3507{
3508 uint32_t const cWidth = f64Bit ? 63 : 31;
3509 Assert(cShift > 0); Assert(cShift <= cWidth);
3510 return Armv8A64MkInstrBitfieldImm(0, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3511}
3512
3513
3514/** A64: Encodes a BFM instruction.
3515 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3516DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3517 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3518{
3519 return Armv8A64MkInstrBitfieldImm(1, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3520}
3521
3522
3523/** A64: Encodes a BFI instruction (insert).
3524 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3525DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfi(uint32_t iRegResult, uint32_t iRegSrc,
3526 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3527{
3528 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3529 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)-(int32_t)offFirstBit & (f64Bit ? 0x3f : 0x1f),
3530 cBitsWidth - 1, f64Bit);
3531}
3532
3533
3534/** A64: Encodes a BFXIL instruction (insert low).
3535 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3536DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBfxil(uint32_t iRegResult, uint32_t iRegSrc,
3537 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3538{
3539 Assert(cBitsWidth > 0U); Assert(cBitsWidth < (f64Bit ? 64U : 32U)); Assert(offFirstBit < (f64Bit ? 64U : 32U));
3540 Assert(offFirstBit + cBitsWidth <= (f64Bit ? 64U : 32U));
3541 return Armv8A64MkInstrBfm(iRegResult, iRegSrc, (uint32_t)offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3542}
3543
3544
3545/** A64: Encodes an UBFM instruction.
3546 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3547DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cImm6Ror, uint32_t uImm6S,
3548 bool f64Bit = true, uint32_t uN1 = UINT32_MAX)
3549{
3550 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cImm6Ror, uImm6S, f64Bit, uN1 == UINT32_MAX ? f64Bit : uN1);
3551}
3552
3553
3554/** A64: Encodes an UBFX instruction (zero extending extract).
3555 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3556DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfx(uint32_t iRegResult, uint32_t iRegSrc,
3557 uint32_t offFirstBit, uint32_t cBitsWidth, bool f64Bit = true)
3558{
3559 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, offFirstBit, offFirstBit + cBitsWidth - 1, f64Bit);
3560}
3561
3562
3563/** A64: Encodes an UBFIZ instruction (zero extending extract from bit zero,
3564 * shifted into destination).
3565 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3566DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUbfiz(uint32_t iRegResult, uint32_t iRegSrc,
3567 uint32_t offFirstBitDst, uint32_t cBitsWidth, bool f64Bit = true)
3568{
3569 uint32_t fMask = f64Bit ? 0x3f : 0x1f;
3570 return Armv8A64MkInstrUbfm(iRegResult, iRegSrc, -(int32_t)offFirstBitDst & fMask, cBitsWidth - 1, f64Bit);
3571}
3572
3573
3574/** A64: Encodes an LSL instruction w/ immediate shift value.
3575 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3576DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLslImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3577{
3578 uint32_t const cWidth = f64Bit ? 63 : 31;
3579 Assert(cShift > 0); Assert(cShift <= cWidth);
3580 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, (uint32_t)(0 - cShift) & cWidth,
3581 cWidth - cShift /*uImm6S*/, f64Bit, f64Bit);
3582}
3583
3584
3585/** A64: Encodes an LSR instruction w/ immediate shift value.
3586 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3587DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrLsrImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3588{
3589 uint32_t const cWidth = f64Bit ? 63 : 31;
3590 Assert(cShift > 0); Assert(cShift <= cWidth);
3591 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, cShift, cWidth /*uImm6S*/, f64Bit, f64Bit);
3592}
3593
3594
3595/** A64: Encodes an UXTB instruction - zero extend byte (8-bit).
3596 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3597DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxtb(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3598{
3599 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 7, f64Bit, f64Bit);
3600}
3601
3602
3603/** A64: Encodes an UXTH instruction - zero extend half word (16-bit).
3604 * @see Armv8A64MkInstrBitfieldImm for parameter details. */
3605DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrUxth(uint32_t iRegResult, uint32_t iRegSrc, bool f64Bit = false)
3606{
3607 return Armv8A64MkInstrBitfieldImm(2, iRegResult, iRegSrc, 0, 15, f64Bit, f64Bit);
3608}
3609
3610
3611/**
3612 * A64: Encodes an EXTR instruction with an immediate.
3613 *
3614 * @returns The encoded instruction.
3615 * @param iRegResult The register to store the result in. ZR is valid.
3616 * @param iRegLow The register holding the least significant bits in the
3617 * extraction. ZR is valid.
3618 * @param iRegHigh The register holding the most significant bits in the
3619 * extraction. ZR is valid.
3620 * @param uLsb The bit number of the least significant bit, or where in
3621 * @a iRegLow to start the
3622 * extraction.
3623 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
3624 */
3625DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrExtrImm(uint32_t iRegResult, uint32_t iRegLow, uint32_t iRegHigh, uint32_t uLsb,
3626 bool f64Bit = true)
3627{
3628 Assert(uLsb < (uint32_t)(f64Bit ? 64 : 32)); Assert(iRegHigh < 32); Assert(iRegLow < 32); Assert(iRegResult < 32);
3629 return ((uint32_t)f64Bit << 31)
3630 | UINT32_C(0x13800000)
3631 | ((uint32_t)f64Bit << 22) /*N*/
3632 | (iRegHigh << 16)
3633 | (uLsb << 10)
3634 | (iRegLow << 5)
3635 | iRegResult;
3636}
3637
3638
3639/** A64: Rotates the value of a register (alias for EXTR). */
3640DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRorImm(uint32_t iRegResult, uint32_t iRegSrc, uint32_t cShift, bool f64Bit = true)
3641{
3642 return Armv8A64MkInstrExtrImm(iRegResult, iRegSrc, iRegSrc, cShift, f64Bit);
3643}
3644
3645
3646/**
3647 * A64: Encodes either add, adds, sub or subs with unsigned 12-bit immediate.
3648 *
3649 * @returns The encoded instruction.
3650 * @param fSub true for sub and subs, false for add and
3651 * adds.
3652 * @param iRegResult The register to store the result in.
3653 * SP is valid when @a fSetFlags = false,
3654 * and ZR is valid otherwise.
3655 * @param iRegSrc The register containing the augend (@a fSub
3656 * = false) or minuend (@a fSub = true). SP is
3657 * a valid registers for all variations.
3658 * @param uImm12AddendSubtrahend The addend (@a fSub = false) or subtrahend
3659 * (@a fSub = true).
3660 * @param f64Bit true for 64-bit GRPs (default), false for
3661 * 32-bit GPRs.
3662 * @param fSetFlags Whether to set flags (adds / subs) or not
3663 * (add / sub - default).
3664 * @param fShift12 Whether to shift uImm12AddendSubtrahend 12
3665 * bits to the left, or not (default).
3666 */
3667DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubUImm12(bool fSub, uint32_t iRegResult, uint32_t iRegSrc,
3668 uint32_t uImm12AddendSubtrahend, bool f64Bit = true,
3669 bool fSetFlags = false, bool fShift12 = false)
3670{
3671 Assert(uImm12AddendSubtrahend < 4096); Assert(iRegSrc < 32); Assert(iRegResult < 32);
3672 return ((uint32_t)f64Bit << 31)
3673 | ((uint32_t)fSub << 30)
3674 | ((uint32_t)fSetFlags << 29)
3675 | UINT32_C(0x11000000)
3676 | ((uint32_t)fShift12 << 22)
3677 | (uImm12AddendSubtrahend << 10)
3678 | (iRegSrc << 5)
3679 | iRegResult;
3680}
3681
3682
3683/** Alias for sub zxr, reg, \#uimm12. */
3684DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpUImm12(uint32_t iRegSrc, uint32_t uImm12Comprahend,
3685 bool f64Bit = true, bool fShift12 = false)
3686{
3687 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc, uImm12Comprahend,
3688 f64Bit, true /*fSetFlags*/, fShift12);
3689}
3690
3691
3692/** ADD dst, src, \#uimm12 */
3693DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Addend,
3694 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3695{
3696 return Armv8A64MkInstrAddSubUImm12(false /*fSub*/, iRegResult, iRegSrc, uImm12Addend, f64Bit, fSetFlags, fShift12);
3697}
3698
3699
3700/** SUB dst, src, \#uimm12 */
3701DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubUImm12(uint32_t iRegResult, uint32_t iRegSrc, uint32_t uImm12Subtrahend,
3702 bool f64Bit = true, bool fSetFlags = false, bool fShift12 = false)
3703{
3704 return Armv8A64MkInstrAddSubUImm12(true /*fSub*/, iRegResult, iRegSrc, uImm12Subtrahend, f64Bit, fSetFlags, fShift12);
3705}
3706
3707
3708/**
3709 * A64: Encodes either add, adds, sub or subs with shifted register.
3710 *
3711 * @returns The encoded instruction.
3712 * @param fSub true for sub and subs, false for add and
3713 * adds.
3714 * @param iRegResult The register to store the result in.
3715 * SP is NOT valid, but ZR is.
3716 * @param iRegSrc1 The register containing the augend (@a fSub
3717 * = false) or minuend (@a fSub = true).
3718 * SP is NOT valid, but ZR is.
3719 * @param iRegSrc2 The register containing the addened (@a fSub
3720 * = false) or subtrahend (@a fSub = true).
3721 * SP is NOT valid, but ZR is.
3722 * @param f64Bit true for 64-bit GRPs (default), false for
3723 * 32-bit GPRs.
3724 * @param fSetFlags Whether to set flags (adds / subs) or not
3725 * (add / sub - default).
3726 * @param cShift The shift count to apply to @a iRegSrc2.
3727 * @param enmShift The shift type to apply to the @a iRegSrc2
3728 * register. kArmv8A64InstrShift_Ror is
3729 * reserved.
3730 */
3731DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubReg(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3732 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3733 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3734{
3735 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3736 Assert(cShift < (f64Bit ? 64U : 32U)); Assert(enmShift != kArmv8A64InstrShift_Ror);
3737
3738 return ((uint32_t)f64Bit << 31)
3739 | ((uint32_t)fSub << 30)
3740 | ((uint32_t)fSetFlags << 29)
3741 | UINT32_C(0x0b000000)
3742 | ((uint32_t)enmShift << 22)
3743 | (iRegSrc2 << 16)
3744 | (cShift << 10)
3745 | (iRegSrc1 << 5)
3746 | iRegResult;
3747}
3748
3749
3750/** Alias for sub zxr, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx]. */
3751DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true, uint32_t cShift = 0,
3752 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3753{
3754 return Armv8A64MkInstrAddSubReg(true /*fSub*/, ARMV8_A64_REG_XZR, iRegSrc1, iRegSrc2,
3755 f64Bit, true /*fSetFlags*/, cShift, enmShift);
3756}
3757
3758
3759/** ADD dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3760DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3761 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3762 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3763{
3764 return Armv8A64MkInstrAddSubReg(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3765}
3766
3767
3768/** SUB dst, reg1, reg2 [, LSL/LSR/ASR/ROR \#xx] */
3769DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSubReg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3770 bool f64Bit = true, bool fSetFlags = false, uint32_t cShift = 0,
3771 ARMV8A64INSTRSHIFT enmShift = kArmv8A64InstrShift_Lsl)
3772{
3773 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags, cShift, enmShift);
3774}
3775
3776
3777/** NEG dst */
3778DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrNeg(uint32_t iRegResult, bool f64Bit = true, bool fSetFlags = false)
3779{
3780 return Armv8A64MkInstrAddSubReg(true /*fSub*/, iRegResult, ARMV8_A64_REG_XZR, iRegResult, f64Bit, fSetFlags);
3781}
3782
3783
3784/** Extension option for 'extended register' instructions. */
3785typedef enum ARMV8A64INSTREXTEND
3786{
3787 kArmv8A64InstrExtend_UxtB = 0,
3788 kArmv8A64InstrExtend_UxtH,
3789 kArmv8A64InstrExtend_UxtW,
3790 kArmv8A64InstrExtend_UxtX,
3791 kArmv8A64InstrExtend_SxtB,
3792 kArmv8A64InstrExtend_SxtH,
3793 kArmv8A64InstrExtend_SxtW,
3794 kArmv8A64InstrExtend_SxtX,
3795 /** The default is either UXTW or UXTX depending on whether the instruction
3796 * is in 32-bit or 64-bit mode. Thus, this needs to be resolved according
3797 * to the f64Bit value. */
3798 kArmv8A64InstrExtend_Default
3799} ARMV8A64INSTREXTEND;
3800
3801
3802/**
3803 * A64: Encodes either add, adds, sub or subs with extended register encoding.
3804 *
3805 * @returns The encoded instruction.
3806 * @param fSub true for sub and subs, false for add and
3807 * adds.
3808 * @param iRegResult The register to store the result in.
3809 * SP is NOT valid, but ZR is.
3810 * @param iRegSrc1 The register containing the augend (@a fSub
3811 * = false) or minuend (@a fSub = true).
3812 * SP is valid, but ZR is NOT.
3813 * @param iRegSrc2 The register containing the addened (@a fSub
3814 * = false) or subtrahend (@a fSub = true).
3815 * SP is NOT valid, but ZR is.
3816 * @param f64Bit true for 64-bit GRPs (default), false for
3817 * 32-bit GPRs.
3818 * @param fSetFlags Whether to set flags (adds / subs) or not
3819 * (add / sub - default).
3820 * @param enmExtend The type of extension to apply to @a
3821 * iRegSrc2.
3822 * @param cShift The left shift count to apply to @a iRegSrc2
3823 * after enmExtend processing is done.
3824 * Max shift is 4 for some reason.
3825 */
3826DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAddSubRegExtend(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3827 bool f64Bit = true, bool fSetFlags = false,
3828 ARMV8A64INSTREXTEND enmExtend = kArmv8A64InstrExtend_Default,
3829 uint32_t cShift = 0)
3830{
3831 if (enmExtend == kArmv8A64InstrExtend_Default)
3832 enmExtend = f64Bit ? kArmv8A64InstrExtend_UxtW : kArmv8A64InstrExtend_UxtX;
3833 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(cShift <= 4);
3834
3835 return ((uint32_t)f64Bit << 31)
3836 | ((uint32_t)fSub << 30)
3837 | ((uint32_t)fSetFlags << 29)
3838 | UINT32_C(0x0b200000)
3839 | (iRegSrc2 << 16)
3840 | ((uint32_t)enmExtend << 13)
3841 | (cShift << 10)
3842 | (iRegSrc1 << 5)
3843 | iRegResult;
3844}
3845
3846
3847/**
3848 * A64: Encodes either adc, adcs, sbc or sbcs with two source registers.
3849 *
3850 * @returns The encoded instruction.
3851 * @param fSub true for sbc and sbcs, false for adc and
3852 * adcs.
3853 * @param iRegResult The register to store the result in. SP is
3854 * NOT valid, but ZR is.
3855 * @param iRegSrc1 The register containing the augend (@a fSub
3856 * = false) or minuend (@a fSub = true).
3857 * SP is NOT valid, but ZR is.
3858 * @param iRegSrc2 The register containing the addened (@a fSub
3859 * = false) or subtrahend (@a fSub = true).
3860 * SP is NOT valid, but ZR is.
3861 * @param f64Bit true for 64-bit GRPs (default), false for
3862 * 32-bit GPRs.
3863 * @param fSetFlags Whether to set flags (adds / subs) or not
3864 * (add / sub - default).
3865 */
3866DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcSbc(bool fSub, uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3867 bool f64Bit = true, bool fSetFlags = false)
3868{
3869 Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
3870
3871 return ((uint32_t)f64Bit << 31)
3872 | ((uint32_t)fSub << 30)
3873 | ((uint32_t)fSetFlags << 29)
3874 | UINT32_C(0x1a000000)
3875 | (iRegSrc2 << 16)
3876 | (iRegSrc1 << 5)
3877 | iRegResult;
3878}
3879
3880
3881/** ADC dst, reg1, reg2 */
3882DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3883 bool f64Bit = true, bool fSetFlags = false)
3884{
3885 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3886}
3887
3888
3889/** ADCS dst, reg1, reg2 */
3890DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrAdcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3891{
3892 return Armv8A64MkInstrAdcSbc(false /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
3893}
3894
3895
3896/** SBC dst, reg1, reg2 */
3897DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
3898 bool f64Bit = true, bool fSetFlags = false)
3899{
3900 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, fSetFlags);
3901}
3902
3903
3904/** SBCS dst, reg1, reg2 */
3905DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSbcs(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2, bool f64Bit = true)
3906{
3907 return Armv8A64MkInstrAdcSbc(true /*fSub*/, iRegResult, iRegSrc1, iRegSrc2, f64Bit, true /*fSetFlags*/);
3908}
3909
3910
3911/**
3912 * A64: Encodes a B (unconditional branch w/ imm) instruction.
3913 *
3914 * @returns The encoded instruction.
3915 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3916 */
3917DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrB(int32_t iImm26)
3918{
3919 Assert(iImm26 >= -67108864 && iImm26 < 67108864);
3920 return UINT32_C(0x14000000) | ((uint32_t)iImm26 & UINT32_C(0x3ffffff));
3921}
3922
3923
3924/**
3925 * A64: Encodes a BL (unconditional call w/ imm) instruction.
3926 *
3927 * @returns The encoded instruction.
3928 * @param iImm26 Signed number of instruction to jump (i.e. *4).
3929 */
3930DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBl(int32_t iImm26)
3931{
3932 return Armv8A64MkInstrB(iImm26) | RT_BIT_32(31);
3933}
3934
3935
3936/**
3937 * A64: Encodes a BR (unconditional branch w/ register) instruction.
3938 *
3939 * @returns The encoded instruction.
3940 * @param iReg The register containing the target address.
3941 */
3942DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBr(uint32_t iReg)
3943{
3944 Assert(iReg < 32);
3945 return UINT32_C(0xd61f0000) | (iReg << 5);
3946}
3947
3948
3949/**
3950 * A64: Encodes a BLR instruction.
3951 *
3952 * @returns The encoded instruction.
3953 * @param iReg The register containing the target address.
3954 */
3955DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBlr(uint32_t iReg)
3956{
3957 return Armv8A64MkInstrBr(iReg) | RT_BIT_32(21);
3958}
3959
3960
3961/**
3962 * A64: Encodes CBZ and CBNZ (conditional branch w/ immediate) instructions.
3963 *
3964 * @returns The encoded instruction.
3965 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
3966 * its not zero.
3967 * @param iImm19 Signed number of instruction to jump (i.e. *4).
3968 * @param iReg The GPR to check for zero / non-zero value.
3969 * @param f64Bit true for 64-bit register, false for 32-bit.
3970 */
3971DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbzCbnz(bool fJmpIfNotZero, int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3972{
3973 Assert(iReg < 32); Assert(iImm19 >= -262144 && iImm19 < 262144);
3974 return ((uint32_t)f64Bit << 31)
3975 | UINT32_C(0x34000000)
3976 | ((uint32_t)fJmpIfNotZero << 24)
3977 | (((uint32_t)iImm19 & 0x7ffff) << 5)
3978 | iReg;
3979}
3980
3981
3982/** A64: Encodes the CBZ instructions. */
3983DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3984{
3985 return Armv8A64MkInstrCbzCbnz(false /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
3986}
3987
3988
3989/** A64: Encodes the CBNZ instructions. */
3990DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCbnz(int32_t iImm19, uint32_t iReg, bool f64Bit = true)
3991{
3992 return Armv8A64MkInstrCbzCbnz(true /*fJmpIfNotZero*/, iImm19, iReg, f64Bit);
3993}
3994
3995
3996/**
3997 * A64: Encodes TBZ and TBNZ (conditional branch w/ immediate) instructions.
3998 *
3999 * @returns The encoded instruction.
4000 * @param fJmpIfNotZero false to jump if register is zero, true to jump if
4001 * its not zero.
4002 * @param iImm14 Signed number of instruction to jump (i.e. *4).
4003 * @param iReg The GPR to check for zero / non-zero value.
4004 * @param iBitNo The bit to test for.
4005 */
4006DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrTbzTbnz(bool fJmpIfNotZero, int32_t iImm14, uint32_t iReg, uint32_t iBitNo)
4007{
4008 Assert(iReg < 32); Assert(iImm14 >= -8192 && iImm14 < 8192); Assert(iBitNo < 64);
4009 return ((uint32_t)(iBitNo & 0x20) << (31-5))
4010 | UINT32_C(0x36000000)
4011 | ((uint32_t)fJmpIfNotZero << 24)
4012 | ((iBitNo & 0x1f) << 19)
4013 | (((uint32_t)iImm14 & 0x3fff) << 5)
4014 | iReg;
4015}
4016
4017
4018
4019/** Armv8 Condition codes. */
4020typedef enum ARMV8INSTRCOND
4021{
4022 kArmv8InstrCond_Eq = 0, /**< 0 - Equal - Zero set. */
4023 kArmv8InstrCond_Ne, /**< 1 - Not equal - Zero clear. */
4024
4025 kArmv8InstrCond_Cs, /**< 2 - Carry set (also known as 'HS'). */
4026 kArmv8InstrCond_Hs = kArmv8InstrCond_Cs, /**< 2 - Unsigned higher or same. */
4027 kArmv8InstrCond_Cc, /**< 3 - Carry clear (also known as 'LO'). */
4028 kArmv8InstrCond_Lo = kArmv8InstrCond_Cc, /**< 3 - Unsigned lower. */
4029
4030 kArmv8InstrCond_Mi, /**< 4 - Negative result (minus). */
4031 kArmv8InstrCond_Pl, /**< 5 - Positive or zero result (plus). */
4032
4033 kArmv8InstrCond_Vs, /**< 6 - Overflow set. */
4034 kArmv8InstrCond_Vc, /**< 7 - Overflow clear. */
4035
4036 kArmv8InstrCond_Hi, /**< 8 - Unsigned higher. */
4037 kArmv8InstrCond_Ls, /**< 9 - Unsigned lower or same. */
4038
4039 kArmv8InstrCond_Ge, /**< a - Signed greater or equal. */
4040 kArmv8InstrCond_Lt, /**< b - Signed less than. */
4041
4042 kArmv8InstrCond_Gt, /**< c - Signed greater than. */
4043 kArmv8InstrCond_Le, /**< d - Signed less or equal. */
4044
4045 kArmv8InstrCond_Al, /**< e - Condition is always true. */
4046 kArmv8InstrCond_Al1 /**< f - Condition is always true. */
4047} ARMV8INSTRCOND;
4048
4049/**
4050 * A64: Encodes conditional branch instruction w/ immediate target.
4051 *
4052 * @returns The encoded instruction.
4053 * @param enmCond The branch condition.
4054 * @param iImm19 Signed number of instruction to jump (i.e. *4).
4055 */
4056DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBCond(ARMV8INSTRCOND enmCond, int32_t iImm19)
4057{
4058 Assert((unsigned)enmCond < 16);
4059 return UINT32_C(0x54000000)
4060 | (((uint32_t)iImm19 & 0x7ffff) << 5)
4061 | (uint32_t)enmCond;
4062}
4063
4064
4065/**
4066 * A64: Encodes the BRK instruction.
4067 *
4068 * @returns The encoded instruction.
4069 * @param uImm16 Unsigned immediate value.
4070 */
4071DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrBrk(uint32_t uImm16)
4072{
4073 Assert(uImm16 < _64K);
4074 return UINT32_C(0xd4200000)
4075 | (uImm16 << 5);
4076}
4077
4078/** @name RMA64_NZCV_F_XXX - readable NZCV mask for CCMP and friends.
4079 * @{ */
4080#define ARMA64_NZCV_F_N0_Z0_C0_V0 UINT32_C(0x0)
4081#define ARMA64_NZCV_F_N0_Z0_C0_V1 UINT32_C(0x1)
4082#define ARMA64_NZCV_F_N0_Z0_C1_V0 UINT32_C(0x2)
4083#define ARMA64_NZCV_F_N0_Z0_C1_V1 UINT32_C(0x3)
4084#define ARMA64_NZCV_F_N0_Z1_C0_V0 UINT32_C(0x4)
4085#define ARMA64_NZCV_F_N0_Z1_C0_V1 UINT32_C(0x5)
4086#define ARMA64_NZCV_F_N0_Z1_C1_V0 UINT32_C(0x6)
4087#define ARMA64_NZCV_F_N0_Z1_C1_V1 UINT32_C(0x7)
4088
4089#define ARMA64_NZCV_F_N1_Z0_C0_V0 UINT32_C(0x8)
4090#define ARMA64_NZCV_F_N1_Z0_C0_V1 UINT32_C(0x9)
4091#define ARMA64_NZCV_F_N1_Z0_C1_V0 UINT32_C(0xa)
4092#define ARMA64_NZCV_F_N1_Z0_C1_V1 UINT32_C(0xb)
4093#define ARMA64_NZCV_F_N1_Z1_C0_V0 UINT32_C(0xc)
4094#define ARMA64_NZCV_F_N1_Z1_C0_V1 UINT32_C(0xd)
4095#define ARMA64_NZCV_F_N1_Z1_C1_V0 UINT32_C(0xe)
4096#define ARMA64_NZCV_F_N1_Z1_C1_V1 UINT32_C(0xf)
4097/** @} */
4098
4099/**
4100 * A64: Encodes CCMP or CCMN with two register operands.
4101 *
4102 * @returns The encoded instruction.
4103 * @param iRegSrc1 The 1st register. SP is NOT valid, but ZR is.
4104 * @param iRegSrc2 The 2nd register. SP is NOT valid, but ZR is.
4105 * @param fNzcv The N, Z, C & V flags values to load if the condition
4106 * does not match. See RMA64_NZCV_F_XXX.
4107 * @param enmCond The condition guarding the compare.
4108 * @param fCCmp Set for CCMP (default), clear for CCMN.
4109 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4110 */
4111DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4112 ARMV8INSTRCOND enmCond, bool fCCmp = true, bool f64Bit = true)
4113{
4114 Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32); Assert(fNzcv < 16);
4115
4116 return ((uint32_t)f64Bit << 31)
4117 | ((uint32_t)fCCmp << 30)
4118 | UINT32_C(0x3a400000)
4119 | (iRegSrc2 << 16)
4120 | ((uint32_t)enmCond << 12)
4121 | (iRegSrc1 << 5)
4122 | fNzcv;
4123}
4124
4125/** CCMP w/ reg. */
4126DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4127 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4128{
4129 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4130}
4131
4132
4133/** CCMN w/ reg. */
4134DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnReg(uint32_t iRegSrc1, uint32_t iRegSrc2, uint32_t fNzcv,
4135 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4136{
4137 return Armv8A64MkInstrCCmpCmnReg(iRegSrc1, iRegSrc2, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4138}
4139
4140
4141/**
4142 * A64: Encodes CCMP or CCMN with register and 5-bit immediate.
4143 *
4144 * @returns The encoded instruction.
4145 * @param iRegSrc The register. SP is NOT valid, but ZR is.
4146 * @param uImm5 The immediate, to compare iRegSrc with.
4147 * @param fNzcv The N, Z, C & V flags values to load if the condition
4148 * does not match. See RMA64_NZCV_F_XXX.
4149 * @param enmCond The condition guarding the compare.
4150 * @param fCCmp Set for CCMP (default), clear for CCMN.
4151 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4152 */
4153DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv, ARMV8INSTRCOND enmCond,
4154 bool fCCmp = true, bool f64Bit = true)
4155{
4156 Assert(iRegSrc < 32); Assert(uImm5 < 32); Assert(fNzcv < 16);
4157
4158 return ((uint32_t)f64Bit << 31)
4159 | ((uint32_t)fCCmp << 30)
4160 | UINT32_C(0x3a400800)
4161 | (uImm5 << 16)
4162 | ((uint32_t)enmCond << 12)
4163 | (iRegSrc << 5)
4164 | fNzcv;
4165}
4166
4167/** CCMP w/ immediate. */
4168DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmpImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4169 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4170{
4171 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, true /*fCCmp*/, f64Bit);
4172}
4173
4174
4175/** CCMN w/ immediate. */
4176DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCCmnImm(uint32_t iRegSrc, uint32_t uImm5, uint32_t fNzcv,
4177 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4178{
4179 return Armv8A64MkInstrCCmpCmnImm(iRegSrc, uImm5, fNzcv, enmCond, false /*fCCmp*/, f64Bit);
4180}
4181
4182
4183/**
4184 * A64: Encodes CSEL, CSINC, CSINV and CSNEG (three registers)
4185 *
4186 * @returns The encoded instruction.
4187 * @param uOp Opcode bit 30.
4188 * @param uOp2 Opcode bits 11:10.
4189 * @param iRegResult The result register. SP is NOT valid, but ZR is.
4190 * @param iRegSrc1 The 1st source register. SP is NOT valid, but ZR is.
4191 * @param iRegSrc2 The 2nd source register. SP is NOT valid, but ZR is.
4192 * @param enmCond The condition guarding the compare.
4193 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4194 */
4195DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCondSelect(uint32_t uOp, uint32_t uOp2, uint32_t iRegResult, uint32_t iRegSrc1,
4196 uint32_t iRegSrc2, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4197{
4198 Assert(uOp <= 1); Assert(uOp2 <= 1); Assert(iRegResult < 32); Assert(iRegSrc1 < 32); Assert(iRegSrc2 < 32);
4199
4200 return ((uint32_t)f64Bit << 31)
4201 | (uOp << 30)
4202 | UINT32_C(0x1a800000)
4203 | (iRegSrc2 << 16)
4204 | ((uint32_t)enmCond << 12)
4205 | (uOp2 << 10)
4206 | (iRegSrc1 << 5)
4207 | iRegResult;
4208}
4209
4210
4211/** A64: Encodes CSEL.
4212 * @see Armv8A64MkInstrCondSelect for details. */
4213DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSel(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4214 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4215{
4216 return Armv8A64MkInstrCondSelect(0, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4217}
4218
4219
4220/** A64: Encodes CSINC.
4221 * @see Armv8A64MkInstrCondSelect for details. */
4222DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInc(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4223 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4224{
4225 return Armv8A64MkInstrCondSelect(0, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4226}
4227
4228
4229/** A64: Encodes CSET.
4230 * @see Armv8A64MkInstrCondSelect for details. */
4231DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSet(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4232{
4233 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4234 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4235 return Armv8A64MkInstrCSInc(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4236}
4237
4238
4239/** A64: Encodes CSINV.
4240 * @see Armv8A64MkInstrCondSelect for details. */
4241DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSInv(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4242 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4243{
4244 return Armv8A64MkInstrCondSelect(1, 0, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4245}
4246
4247/** A64: Encodes CSETM.
4248 * @see Armv8A64MkInstrCondSelect for details. */
4249DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSetM(uint32_t iRegResult, ARMV8INSTRCOND enmCond, bool f64Bit = true)
4250{
4251 Assert(enmCond != kArmv8InstrCond_Al && enmCond != kArmv8InstrCond_Al1);
4252 enmCond = (ARMV8INSTRCOND)((uint32_t)enmCond ^ 1);
4253 return Armv8A64MkInstrCSInv(iRegResult, ARMV8_A64_REG_XZR, ARMV8_A64_REG_XZR, enmCond, f64Bit);
4254}
4255
4256
4257/** A64: Encodes CSNEG.
4258 * @see Armv8A64MkInstrCondSelect for details. */
4259DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrCSNeg(uint32_t iRegResult, uint32_t iRegSrc1, uint32_t iRegSrc2,
4260 ARMV8INSTRCOND enmCond, bool f64Bit = true)
4261{
4262 return Armv8A64MkInstrCondSelect(1, 1, iRegResult, iRegSrc1, iRegSrc2, enmCond, f64Bit);
4263}
4264
4265
4266/**
4267 * A64: Encodes REV instruction.
4268 *
4269 * @returns The encoded instruction.
4270 * @param iRegDst The destination register. SP is NOT valid.
4271 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4272 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4273 */
4274DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4275{
4276 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4277
4278 return ((uint32_t)f64Bit << 31)
4279 | UINT32_C(0x5ac00800)
4280 | ((uint32_t)f64Bit << 10)
4281 | (iRegSrc << 5)
4282 | iRegDst;
4283}
4284
4285
4286/**
4287 * A64: Encodes REV16 instruction.
4288 *
4289 * @returns The encoded instruction.
4290 * @param iRegDst The destination register. SP is NOT valid.
4291 * @param iRegSrc The source register. SP is NOT valid, but ZR is
4292 * @param f64Bit true for 64-bit GRPs (default), false for 32-bit GPRs.
4293 */
4294DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRev16(uint32_t iRegDst, uint32_t iRegSrc, bool f64Bit = true)
4295{
4296 Assert(iRegDst < 32); Assert(iRegSrc < 32);
4297
4298 return ((uint32_t)f64Bit << 31)
4299 | UINT32_C(0x5ac00400)
4300 | (iRegSrc << 5)
4301 | iRegDst;
4302}
4303
4304
4305/**
4306 * A64: Encodes SETF8 & SETF16.
4307 *
4308 * @returns The encoded instruction.
4309 * @param iRegResult The register holding the result. SP is NOT valid.
4310 * @param f16Bit Set for SETF16, clear for SETF8.
4311 */
4312DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrSetF8SetF16(uint32_t iRegResult, bool f16Bit)
4313{
4314 Assert(iRegResult < 32);
4315
4316 return UINT32_C(0x3a00080d)
4317 | ((uint32_t)f16Bit << 14)
4318 | (iRegResult << 5);
4319}
4320
4321
4322/**
4323 * A64: Encodes RMIF.
4324 *
4325 * @returns The encoded instruction.
4326 * @param iRegSrc The source register to get flags from.
4327 * @param cRotateRight The right rotate count (LSB bit offset).
4328 * @param fMask Mask of which flag bits to set:
4329 * - bit 0: V
4330 * - bit 1: C
4331 * - bit 2: Z
4332 * - bit 3: N
4333 */
4334DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrRmif(uint32_t iRegSrc, uint32_t cRotateRight, uint32_t fMask)
4335{
4336 Assert(iRegSrc < 32); Assert(cRotateRight < 64); Assert(fMask <= 0xf);
4337
4338 return UINT32_C(0xba000400)
4339 | (cRotateRight << 15)
4340 | (iRegSrc << 5)
4341 | fMask;
4342}
4343
4344
4345/**
4346 * A64: Encodes MRS (for reading a system register into a GPR).
4347 *
4348 * @returns The encoded instruction.
4349 * @param iRegDst The register to put the result into. SP is NOT valid.
4350 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4351 * IPRT specific format, of the register to read.
4352 */
4353DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMrs(uint32_t iRegDst, uint32_t idSysReg)
4354{
4355 Assert(iRegDst < 32);
4356 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4357
4358 /* Note. The top bit of idSysReg must always be set and is also set in
4359 0xd5300000, otherwise we'll be encoding a different instruction. */
4360 return UINT32_C(0xd5300000)
4361 | (idSysReg << 5)
4362 | iRegDst;
4363}
4364
4365
4366/**
4367 * A64: Encodes MSR (for writing a GPR to a system register).
4368 *
4369 * @returns The encoded instruction.
4370 * @param iRegSrc The register which value to write. SP is NOT valid.
4371 * @param idSysReg The system register ID (ARMV8_AARCH64_SYSREG_XXX),
4372 * IPRT specific format, of the register to write.
4373 */
4374DECL_FORCE_INLINE(uint32_t) Armv8A64MkInstrMsr(uint32_t iRegSrc, uint32_t idSysReg)
4375{
4376 Assert(iRegSrc < 32);
4377 Assert(idSysReg < RT_BIT_32(16) && (idSysReg & RT_BIT_32(15)));
4378
4379 /* Note. The top bit of idSysReg must always be set and is also set in
4380 0xd5100000, otherwise we'll be encoding a different instruction. */
4381 return UINT32_C(0xd5100000)
4382 | (idSysReg << 5)
4383 | iRegSrc;
4384}
4385
4386
4387/** @} */
4388
4389
4390/** @defgroup grp_rt_armv8_mkinstr_vec Vector Instruction Encoding Helpers
4391 * @ingroup grp_rt_armv8_mkinstr
4392 *
4393 * A few inlined functions and macros for assisting in encoding common ARMv8
4394 * Neon/SIMD instructions.
4395 *
4396 * @{ */
4397
4398/**
4399 * A64: Encodes ORR (vector, register).
4400 *
4401 * @returns The encoded instruction.
4402 * @param iVecRegDst The vector register to put the result into.
4403 * @param iVecRegSrc1 The 1st source register.
4404 * @param iVecRegSrc2 The 2nd source register.
4405 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4406 * or just the low 64-bit (false).
4407 */
4408DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrOrr(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4409 bool f128Bit = true)
4410{
4411 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4412
4413 return UINT32_C(0x0ea01c00)
4414 | ((uint32_t)f128Bit << 30)
4415 | (iVecRegSrc2 << 16)
4416 | (iVecRegSrc1 << 5)
4417 | iVecRegDst;
4418}
4419
4420
4421/**
4422 * A64: Encodes EOR (vector, register).
4423 *
4424 * @returns The encoded instruction.
4425 * @param iVecRegDst The vector register to put the result into.
4426 * @param iVecRegSrc1 The 1st source register.
4427 * @param iVecRegSrc2 The 2nd source register.
4428 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4429 * or just the low 64-bit (false).
4430 */
4431DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrEor(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4432 bool f128Bit = true)
4433{
4434 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4435
4436 return UINT32_C(0x2e201c00)
4437 | ((uint32_t)f128Bit << 30)
4438 | (iVecRegSrc2 << 16)
4439 | (iVecRegSrc1 << 5)
4440 | iVecRegDst;
4441}
4442
4443
4444/**
4445 * A64: Encodes AND (vector, register).
4446 *
4447 * @returns The encoded instruction.
4448 * @param iVecRegDst The vector register to put the result into.
4449 * @param iVecRegSrc1 The 1st source register.
4450 * @param iVecRegSrc2 The 2nd source register.
4451 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4452 * or just the low 64-bit (false).
4453 */
4454DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAnd(uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4455 bool f128Bit = true)
4456{
4457 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4458
4459 return UINT32_C(0x0e201c00)
4460 | ((uint32_t)f128Bit << 30)
4461 | (iVecRegSrc2 << 16)
4462 | (iVecRegSrc1 << 5)
4463 | iVecRegDst;
4464}
4465
4466
4467/** Armv8 UMOV/INS vector element size. */
4468typedef enum ARMV8INSTRUMOVINSSZ
4469{
4470 kArmv8InstrUmovInsSz_U8 = 0, /**< Byte. */
4471 kArmv8InstrUmovInsSz_U16 = 1, /**< Halfword. */
4472 kArmv8InstrUmovInsSz_U32 = 2, /**< 32-bit. */
4473 kArmv8InstrUmovInsSz_U64 = 3 /**< 64-bit (only valid when the destination is a 64-bit register. */
4474} ARMV8INSTRUMOVINSSZ;
4475
4476
4477/**
4478 * A64: Encodes UMOV (vector, register).
4479 *
4480 * @returns The encoded instruction.
4481 * @param iRegDst The register to put the result into.
4482 * @param iVecRegSrc The vector source register.
4483 * @param idxElem The element index.
4484 * @param enmSz Element size of the source vector register.
4485 * @param fDst64Bit Flag whether the destination register is 64-bit (true) or 32-bit (false).
4486 */
4487DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUmov(uint32_t iRegDst, uint32_t iVecRegSrc, uint8_t idxElem,
4488 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64, bool fDst64Bit = true)
4489{
4490 Assert(iRegDst < 32); Assert(iVecRegSrc < 32);
4491 Assert((fDst64Bit && enmSz == kArmv8InstrUmovInsSz_U64) || (!fDst64Bit && enmSz != kArmv8InstrUmovInsSz_U64));
4492 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4493 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4494 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4495 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4496
4497 return UINT32_C(0x0e003c00)
4498 | ((uint32_t)fDst64Bit << 30)
4499 | ((uint32_t)idxElem << (16 + enmSz + 1))
4500 | (RT_BIT_32(enmSz) << 16)
4501 | (iVecRegSrc << 5)
4502 | iRegDst;
4503}
4504
4505
4506/**
4507 * A64: Encodes INS (vector, register).
4508 *
4509 * @returns The encoded instruction.
4510 * @param iVecRegDst The vector register to put the result into.
4511 * @param iRegSrc The source register.
4512 * @param idxElem The element index for the destination.
4513 * @param enmSz Element size of the source vector register.
4514 *
4515 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4516 */
4517DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrIns(uint32_t iVecRegDst, uint32_t iRegSrc, uint8_t idxElem,
4518 ARMV8INSTRUMOVINSSZ enmSz = kArmv8InstrUmovInsSz_U64)
4519{
4520 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4521 Assert( (enmSz == kArmv8InstrUmovInsSz_U8 && idxElem < 16)
4522 || (enmSz == kArmv8InstrUmovInsSz_U16 && idxElem < 8)
4523 || (enmSz == kArmv8InstrUmovInsSz_U32 && idxElem < 4)
4524 || (enmSz == kArmv8InstrUmovInsSz_U64 && idxElem < 2));
4525
4526 return UINT32_C(0x4e001c00)
4527 | ((uint32_t)idxElem << (16 + enmSz + 1))
4528 | (RT_BIT_32(enmSz) << 16)
4529 | (iRegSrc << 5)
4530 | iVecRegDst;
4531}
4532
4533
4534/**
4535 * A64: Encodes DUP (vector, register).
4536 *
4537 * @returns The encoded instruction.
4538 * @param iVecRegDst The vector register to put the result into.
4539 * @param iRegSrc The source register (ZR is valid).
4540 * @param enmSz Element size of the source vector register.
4541 * @param f128Bit Flag whether the instruction operates on the whole 128-bit of the vector register (true) or
4542 * just the low 64-bit (false).
4543 *
4544 * @note This instruction assumes a 32-bit W<n> register for all non 64bit vector sizes.
4545 */
4546DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrDup(uint32_t iVecRegDst, uint32_t iRegSrc, ARMV8INSTRUMOVINSSZ enmSz,
4547 bool f128Bit = true)
4548{
4549 Assert(iRegSrc < 32); Assert(iVecRegDst < 32);
4550 Assert( (enmSz == kArmv8InstrUmovInsSz_U8)
4551 || (enmSz == kArmv8InstrUmovInsSz_U16)
4552 || (enmSz == kArmv8InstrUmovInsSz_U32)
4553 || (enmSz == kArmv8InstrUmovInsSz_U64));
4554
4555 return UINT32_C(0x0e000c00)
4556 | ((uint32_t)f128Bit << 30)
4557 | (RT_BIT_32(enmSz) << 16)
4558 | (iRegSrc << 5)
4559 | iVecRegDst;
4560}
4561
4562
4563/** Armv8 vector compare to zero vector element size. */
4564typedef enum ARMV8INSTRVECCMPZEROSZ
4565{
4566 kArmv8InstrCmpZeroSz_S8 = 0, /**< Byte. */
4567 kArmv8InstrCmpZeroSz_S16 = 1, /**< Halfword. */
4568 kArmv8InstrCmpZeroSz_S32 = 2, /**< 32-bit. */
4569 kArmv8InstrCmpZeroSz_S64 = 3 /**< 64-bit. */
4570} ARMV8INSTRVECCMPZEROSZ;
4571
4572
4573/** Armv8 vector compare to zero vector operation. */
4574typedef enum ARMV8INSTRVECCMPZEROOP
4575{
4576 kArmv8InstrCmpZeroOp_Gt = 0, /**< Greater than. */
4577 kArmv8InstrCmpZeroOp_Ge = RT_BIT_32(29), /**< Greater than or equal to. */
4578 kArmv8InstrCmpZeroOp_Eq = RT_BIT_32(12), /**< Equal to. */
4579 kArmv8InstrCmpZeroOp_Le = RT_BIT_32(29) | RT_BIT_32(12) /**< Lower than or equal to. */
4580} ARMV8INSTRVECCMPZEROOP;
4581
4582
4583/**
4584 * A64: Encodes CMGT, CMGE, CMEQ or CMLE against zero (vector, register).
4585 *
4586 * @returns The encoded instruction.
4587 * @param iVecRegDst The vector register to put the result into.
4588 * @param iVecRegSrc The vector source register.
4589 * @param enmSz Vector element size.
4590 * @param enmOp The compare operation against to encode.
4591 */
4592DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpToZero(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECCMPZEROSZ enmSz,
4593 ARMV8INSTRVECCMPZEROOP enmOp)
4594{
4595 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4596
4597 return UINT32_C(0x5e208800)
4598 | ((uint32_t)enmSz << 22)
4599 | (RT_BIT_32(enmSz) << 16)
4600 | (iVecRegSrc << 5)
4601 | iVecRegDst
4602 | (uint32_t)enmOp;
4603}
4604
4605
4606/**
4607 * A64: Encodes CNT (vector, register).
4608 *
4609 * @returns The encoded instruction.
4610 * @param iVecRegDst The vector register to put the result into.
4611 * @param iVecRegSrc The vector source register.
4612 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4613 * or just the low 64-bit (false).
4614 */
4615DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCnt(uint32_t iVecRegDst, uint32_t iVecRegSrc, bool f128Bit = true)
4616{
4617 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4618
4619 return UINT32_C(0x0e205800)
4620 | ((uint32_t)f128Bit << 30)
4621 | (iVecRegSrc << 5)
4622 | iVecRegDst;
4623}
4624
4625
4626/** Armv8 vector unsigned sum long across vector element size. */
4627typedef enum ARMV8INSTRVECUADDLVSZ
4628{
4629 kArmv8InstrUAddLVSz_8B = 0, /**< 8 x 8-bit. */
4630 kArmv8InstrUAddLVSz_16B = RT_BIT_32(30), /**< 16 x 8-bit. */
4631 kArmv8InstrUAddLVSz_4H = 1, /**< 4 x 16-bit. */
4632 kArmv8InstrUAddLVSz_8H = RT_BIT_32(30) | 1, /**< 8 x 16-bit. */
4633 kArmv8InstrUAddLVSz_4S = RT_BIT_32(30) | 2 /**< 4 x 32-bit. */
4634} ARMV8INSTRVECUADDLVSZ;
4635
4636
4637/**
4638 * A64: Encodes UADDLV (vector, register).
4639 *
4640 * @returns The encoded instruction.
4641 * @param iVecRegDst The vector register to put the result into.
4642 * @param iVecRegSrc The vector source register.
4643 * @param enmSz Element size.
4644 */
4645DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrUAddLV(uint32_t iVecRegDst, uint32_t iVecRegSrc, ARMV8INSTRVECUADDLVSZ enmSz)
4646{
4647 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4648
4649 return UINT32_C(0x2e303800)
4650 | ((uint32_t)enmSz)
4651 | (iVecRegSrc << 5)
4652 | iVecRegDst;
4653}
4654
4655
4656/** Armv8 USHR/USRA/URSRA/SSHR/SRSA/SSHR vector element size. */
4657typedef enum ARMV8INSTRUSHIFTSZ
4658{
4659 kArmv8InstrShiftSz_U8 = 8, /**< Byte. */
4660 kArmv8InstrShiftSz_U16 = 16, /**< Halfword. */
4661 kArmv8InstrShiftSz_U32 = 32, /**< 32-bit. */
4662 kArmv8InstrShiftSz_U64 = 64 /**< 64-bit. */
4663} ARMV8INSTRUSHIFTSZ;
4664
4665/**
4666 * A64: Encodes USHR/USRA/URSRA/SSHR/SRSA/SSHR (vector, register).
4667 *
4668 * @returns The encoded instruction.
4669 * @param iVecRegDst The vector register to put the result into.
4670 * @param iVecRegSrc The vector source register.
4671 * @param cShift Number of bits to shift.
4672 * @param enmSz Element size.
4673 * @param fUnsigned Flag whether this a signed or unsigned shift,
4674 * @param fRound Flag whether this is the rounding shift variant.
4675 * @param fAccum Flag whether this is the accumulate shift variant.
4676 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4677 * or just the low 64-bit (false).
4678 */
4679DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShrImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4680 bool fUnsigned = true, bool fRound = false, bool fAccum = false, bool f128Bit = true)
4681{
4682 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4683 Assert( cShift >= 1
4684 && ( (enmSz == kArmv8InstrShiftSz_U8 && cShift <= 8)
4685 || (enmSz == kArmv8InstrShiftSz_U16 && cShift <= 16)
4686 || (enmSz == kArmv8InstrShiftSz_U32 && cShift <= 32)
4687 || (enmSz == kArmv8InstrShiftSz_U64 && cShift <= 64)));
4688
4689 return UINT32_C(0x0f000400)
4690 | ((uint32_t)f128Bit << 30)
4691 | ((uint32_t)fUnsigned << 29)
4692 | ((((uint32_t)enmSz << 1) - cShift) << 16)
4693 | ((uint32_t)fRound << 13)
4694 | ((uint32_t)fAccum << 12)
4695 | (iVecRegSrc << 5)
4696 | iVecRegDst;
4697}
4698
4699
4700/**
4701 * A64: Encodes SHL (vector, register).
4702 *
4703 * @returns The encoded instruction.
4704 * @param iVecRegDst The vector register to put the result into.
4705 * @param iVecRegSrc The vector source register.
4706 * @param cShift Number of bits to shift.
4707 * @param enmSz Element size.
4708 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4709 * or just the low 64-bit (false).
4710 */
4711DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrShlImm(uint32_t iVecRegDst, uint32_t iVecRegSrc, uint8_t cShift, ARMV8INSTRUSHIFTSZ enmSz,
4712 bool f128Bit = true)
4713{
4714 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4715 Assert( (enmSz == kArmv8InstrShiftSz_U8 && cShift < 8)
4716 || (enmSz == kArmv8InstrShiftSz_U16 && cShift < 16)
4717 || (enmSz == kArmv8InstrShiftSz_U32 && cShift < 32)
4718 || (enmSz == kArmv8InstrShiftSz_U64 && cShift < 64));
4719
4720 return UINT32_C(0x0f005400)
4721 | ((uint32_t)f128Bit << 30)
4722 | (((uint32_t)enmSz | cShift) << 16)
4723 | (iVecRegSrc << 5)
4724 | iVecRegDst;
4725}
4726
4727
4728/** Armv8 vector arith ops element size. */
4729typedef enum ARMV8INSTRVECARITHSZ
4730{
4731 kArmv8VecInstrArithSz_8 = 0, /**< 8-bit. */
4732 kArmv8VecInstrArithSz_16 = 1, /**< 16-bit. */
4733 kArmv8VecInstrArithSz_32 = 2, /**< 32-bit. */
4734 kArmv8VecInstrArithSz_64 = 3 /**< 64-bit. */
4735} ARMV8INSTRVECARITHSZ;
4736
4737/**
4738 * A64: Encodes ADD/SUB (vector, register).
4739 *
4740 * @returns The encoded instruction.
4741 * @param fSub Flag whther this is an addition (false) or subtraction (true) instruction.
4742 * @param iVecRegDst The vector register to put the result into.
4743 * @param iVecRegSrc1 The first vector source register.
4744 * @param iVecRegSrc2 The second vector source register.
4745 * @param enmSz Element size.
4746 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4747 * or just the low 64-bit (false).
4748 */
4749DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrAddSub(bool fSub, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4750 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4751{
4752 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4753
4754 return UINT32_C(0x0e208400)
4755 | ((uint32_t)f128Bit << 30)
4756 | ((uint32_t)fSub << 29)
4757 | ((uint32_t)enmSz << 22)
4758 | (iVecRegSrc2 << 16)
4759 | (iVecRegSrc1 << 5)
4760 | iVecRegDst;
4761}
4762
4763
4764/** Armv8 vector compare operation. */
4765typedef enum ARMV8VECINSTRCMPOP
4766{
4767 /* U insn[15:10] */
4768 kArmv8VecInstrCmpOp_Gt = UINT32_C(0x3400), /**< Greater than (>) (signed) */
4769 kArmv8VecInstrCmpOp_Ge = UINT32_C(0x3c00), /**< Greater or equal (>=) (signed) */
4770 kArmv8VecInstrCmpOp_Hi = RT_BIT_32(29) | UINT32_C(0x3400), /**< Greater than (>) (unsigned) */
4771 kArmv8VecInstrCmpOp_Hs = RT_BIT_32(29) | UINT32_C(0x3c00), /**< Greater or equal (>=) (unsigned) */
4772 kArmv8VecInstrCmpOp_Eq = RT_BIT_32(29) | UINT32_C(0x8c00) /**< Equal (==) (unsigned) */
4773} ARMV8VECINSTRCMPOP;
4774
4775/**
4776 * A64: Encodes CMEQ/CMGE/CMGT/CMHI/CMHS (register variant) (vector, register).
4777 *
4778 * @returns The encoded instruction.
4779 * @param enmOp The operation to perform.
4780 * @param iVecRegDst The vector register to put the result into.
4781 * @param iVecRegSrc1 The first vector source register.
4782 * @param iVecRegSrc2 The second vector source register.
4783 * @param enmSz Element size.
4784 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4785 * or just the low 64-bit (false).
4786 */
4787DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmp(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc1, uint32_t iVecRegSrc2,
4788 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4789{
4790 Assert(iVecRegDst < 32); Assert(iVecRegSrc1 < 32); Assert(iVecRegSrc2 < 32);
4791
4792 return UINT32_C(0x0e200000)
4793 | ((uint32_t)f128Bit << 30)
4794 | ((uint32_t)enmSz << 22)
4795 | (iVecRegSrc2 << 16)
4796 | ((uint32_t)enmOp)
4797 | (iVecRegSrc1 << 5)
4798 | iVecRegDst;
4799}
4800
4801
4802/** Armv8 vector compare against zero operation. */
4803typedef enum ARMV8VECINSTRCMPZEROOP
4804{
4805 /* U insn[15:10] */
4806 kArmv8VecInstrCmpZeroOp_Gt = UINT32_C(0x8800), /**< Greater than zero (>) (signed) */
4807 kArmv8VecInstrCmpZeroOp_Eq = UINT32_C(0x9800), /**< Equal to zero (==) */
4808 kArmv8VecInstrCmpZeroOp_Lt = UINT32_C(0xa800), /**< Lower than zero (>=) (signed) */
4809 kArmv8VecInstrCmpZeroOp_Ge = RT_BIT_32(29) | UINT32_C(0x8800), /**< Greater or equal to zero (>=) (signed) */
4810 kArmv8VecInstrCmpZeroOp_Le = RT_BIT_32(29) | UINT32_C(0x9800) /**< Lower or equal to zero (<=) (signed) */
4811} ARMV8VECINSTRCMPZEROOP;
4812
4813/**
4814 * A64: Encodes CMEQ/CMGE/CMGT/CMLE/CMLT (zero variant) (vector, register).
4815 *
4816 * @returns The encoded instruction.
4817 * @param enmOp The operation to perform.
4818 * @param iVecRegDst The vector register to put the result into.
4819 * @param iVecRegSrc The first vector source register.
4820 * @param enmSz Element size.
4821 * @param f128Bit Flag whether this operates on the full 128-bit (true, default) of the vector register
4822 * or just the low 64-bit (false).
4823 */
4824DECL_FORCE_INLINE(uint32_t) Armv8A64MkVecInstrCmpAgainstZero(ARMV8VECINSTRCMPOP enmOp, uint32_t iVecRegDst, uint32_t iVecRegSrc,
4825 ARMV8INSTRVECARITHSZ enmSz, bool f128Bit = true)
4826{
4827 Assert(iVecRegDst < 32); Assert(iVecRegSrc < 32);
4828
4829 return UINT32_C(0x0e200000)
4830 | ((uint32_t)f128Bit << 30)
4831 | ((uint32_t)enmSz << 22)
4832 | ((uint32_t)enmOp)
4833 | (iVecRegSrc << 5)
4834 | iVecRegDst;
4835}
4836
4837/** @} */
4838
4839#endif /* !dtrace && __cplusplus */
4840
4841/** @} */
4842
4843#endif /* !IPRT_INCLUDED_armv8_h */
4844
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