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source: vbox/trunk/include/VBox/x86.h@ 8536

Last change on this file since 8536 was 8536, checked in by vboxsync, 16 years ago
Split out the long mode only bits from the PDPE. Set accessed bits for the PDPE & PML4E
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 80.3 KB

Line
1	/** @file
2	* X86 (and AMD64) Structures and Definitions.
3	*/
4
5	/*
6	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
7	*
8	* This file is part of VirtualBox Open Source Edition (OSE), as
9	* available from http://www.virtualbox.org. This file is free software;
10	* you can redistribute it and/or modify it under the terms of the GNU
11	* General Public License (GPL) as published by the Free Software
12	* Foundation, in version 2 as it comes in the "COPYING" file of the
13	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
14	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
15	*
16	* The contents of this file may alternatively be used under the terms
17	* of the Common Development and Distribution License Version 1.0
18	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
19	* VirtualBox OSE distribution, in which case the provisions of the
20	* CDDL are applicable instead of those of the GPL.
21	*
22	* You may elect to license modified versions of this file under the
23	* terms and conditions of either the GPL or the CDDL or both.
24	*
25	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
26	* Clara, CA 95054 USA or visit http://www.sun.com if you need
27	* additional information or have any questions.
28	*/
29
30	/*
31	* x86.mac is generated from this file using:
32	* sed -e '/__VBox_x86_h__/d' -e '/#define/!d' -e 's/#define/%define/' include/VBox/x86.h
33	*/
34
35	#ifndef ___VBox_x86_h
36	#define ___VBox_x86_h
37
38	#include <VBox/types.h>
39
40	/* Workaround for Solaris sys/regset.h defining CS, DS */
41	#if defined(RT_OS_SOLARIS)
42	# undef CS
43	# undef DS
44	#endif
45
46	/** @defgroup grp_x86 x86 Types and Definitions
47	* @{
48	*/
49
50	/**
51	* EFLAGS Bits.
52	*/
53	typedef struct X86EFLAGSBITS
54	{
55	/** Bit 0 - CF - Carry flag - Status flag. */
56	unsigned u1CF : 1;
57	/** Bit 1 - 1 - Reserved flag. */
58	unsigned u1Reserved0 : 1;
59	/** Bit 2 - PF - Parity flag - Status flag. */
60	unsigned u1PF : 1;
61	/** Bit 3 - 0 - Reserved flag. */
62	unsigned u1Reserved1 : 1;
63	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
64	unsigned u1AF : 1;
65	/** Bit 5 - 0 - Reserved flag. */
66	unsigned u1Reserved2 : 1;
67	/** Bit 6 - ZF - Zero flag - Status flag. */
68	unsigned u1ZF : 1;
69	/** Bit 7 - SF - Signed flag - Status flag. */
70	unsigned u1SF : 1;
71	/** Bit 8 - TF - Trap flag - System flag. */
72	unsigned u1TF : 1;
73	/** Bit 9 - IF - Interrupt flag - System flag. */
74	unsigned u1IF : 1;
75	/** Bit 10 - DF - Direction flag - Control flag. */
76	unsigned u1DF : 1;
77	/** Bit 11 - OF - Overflow flag - Status flag. */
78	unsigned u1OF : 1;
79	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
80	unsigned u2IOPL : 2;
81	/** Bit 14 - NT - Nested task flag - System flag. */
82	unsigned u1NT : 1;
83	/** Bit 15 - 0 - Reserved flag. */
84	unsigned u1Reserved3 : 1;
85	/** Bit 16 - RF - Resume flag - System flag. */
86	unsigned u1RF : 1;
87	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
88	unsigned u1VM : 1;
89	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
90	unsigned u1AC : 1;
91	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
92	unsigned u1VIF : 1;
93	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
94	unsigned u1VIP : 1;
95	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
96	unsigned u1ID : 1;
97	/** Bit 22-31 - 0 - Reserved flag. */
98	unsigned u10Reserved4 : 10;
99	} X86EFLAGSBITS;
100	/** Pointer to EFLAGS bits. */
101	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
102	/** Pointer to const EFLAGS bits. */
103	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
104
105	/**
106	* EFLAGS.
107	*/
108	typedef union X86EFLAGS
109	{
110	/** The bitfield view. */
111	X86EFLAGSBITS Bits;
112	/** The 8-bit view. */
113	uint8_t au8[4];
114	/** The 16-bit view. */
115	uint16_t au16[2];
116	/** The 32-bit view. */
117	uint32_t au32[1];
118	/** The 32-bit view. */
119	uint32_t u32;
120	/** The plain unsigned view. */
121	uint32_t u;
122	} X86EFLAGS;
123	/** Pointer to EFLAGS. */
124	typedef X86EFLAGS *PX86EFLAGS;
125	/** Pointer to const EFLAGS. */
126	typedef const X86EFLAGS *PCX86EFLAGS;
127
128	/**
129	* RFLAGS (32 upper bits are reserved).
130	*/
131	typedef union X86RFLAGS
132	{
133	/** The bitfield view. */
134	X86EFLAGSBITS Bits;
135	/** The 8-bit view. */
136	uint8_t au8[8];
137	/** The 16-bit view. */
138	uint16_t au16[4];
139	/** The 32-bit view. */
140	uint32_t au32[2];
141	/** The 64-bit view. */
142	uint64_t au64[1];
143	/** The 64-bit view. */
144	uint64_t u64;
145	/** The plain unsigned view. */
146	uint64_t u;
147	} X86RFLAGS;
148	/** Pointer to RFLAGS. */
149	typedef X86RFLAGS *PX86RFLAGS;
150	/** Pointer to const RFLAGS. */
151	typedef const X86RFLAGS *PCX86RFLAGS;
152
153
154	/** @name EFLAGS
155	* @{
156	*/
157	/** Bit 0 - CF - Carry flag - Status flag. */
158	#define X86_EFL_CF RT_BIT(0)
159	/** Bit 2 - PF - Parity flag - Status flag. */
160	#define X86_EFL_PF RT_BIT(2)
161	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
162	#define X86_EFL_AF RT_BIT(4)
163	/** Bit 6 - ZF - Zero flag - Status flag. */
164	#define X86_EFL_ZF RT_BIT(6)
165	/** Bit 7 - SF - Signed flag - Status flag. */
166	#define X86_EFL_SF RT_BIT(7)
167	/** Bit 8 - TF - Trap flag - System flag. */
168	#define X86_EFL_TF RT_BIT(8)
169	/** Bit 9 - IF - Interrupt flag - System flag. */
170	#define X86_EFL_IF RT_BIT(9)
171	/** Bit 10 - DF - Direction flag - Control flag. */
172	#define X86_EFL_DF RT_BIT(10)
173	/** Bit 11 - OF - Overflow flag - Status flag. */
174	#define X86_EFL_OF RT_BIT(11)
175	/** Bit 12-13 - IOPL - I/O prvilege level flag - System flag. */
176	#define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
177	/** Bit 14 - NT - Nested task flag - System flag. */
178	#define X86_EFL_NT RT_BIT(14)
179	/** Bit 16 - RF - Resume flag - System flag. */
180	#define X86_EFL_RF RT_BIT(16)
181	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
182	#define X86_EFL_VM RT_BIT(17)
183	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
184	#define X86_EFL_AC RT_BIT(18)
185	/** Bit 19 - VIF - Virtual interupt flag - System flag. */
186	#define X86_EFL_VIF RT_BIT(19)
187	/** Bit 20 - VIP - Virtual interupt pending flag - System flag. */
188	#define X86_EFL_VIP RT_BIT(20)
189	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
190	#define X86_EFL_ID RT_BIT(21)
191	/** IOPL shift. */
192	#define X86_EFL_IOPL_SHIFT 12
193	/** The the IOPL level from the flags. */
194	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
195	/** @} */
196
197
198	/** CPUID Feature information - ECX.
199	* CPUID query with EAX=1.
200	*/
201	typedef struct X86CPUIDFEATECX
202	{
203	/** Bit 0 - SSE3 - Supports SSE3 or not. */
204	unsigned u1SSE3 : 1;
205	/** Reserved. */
206	unsigned u2Reserved1 : 2;
207	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
208	unsigned u1Monitor : 1;
209	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
210	unsigned u1CPLDS : 1;
211	/** Bit 5 - VMX - Virtual Machine Technology. */
212	unsigned u1VMX : 1;
213	/** Reserved. */
214	unsigned u1Reserved2 : 1;
215	/** Bit 7 - EST - Enh. SpeedStep Tech. */
216	unsigned u1EST : 1;
217	/** Bit 8 - TM2 - Terminal Monitor 2. */
218	unsigned u1TM2 : 1;
219	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
220	unsigned u1SSSE3 : 1;
221	/** Bit 10 - CNTX-ID - L1 Context ID. */
222	unsigned u1CNTXID : 1;
223	/** Reserved. */
224	unsigned u2Reserved4 : 2;
225	/** Bit 13 - CX16 - CMPXCHG16B. */
226	unsigned u1CX16 : 1;
227	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
228	unsigned u1TPRUpdate : 1;
229	/** Reserved. */
230	unsigned u17Reserved5 : 17;
231
232	} X86CPUIDFEATECX;
233	/** Pointer to CPUID Feature Information - ECX. */
234	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
235	/** Pointer to const CPUID Feature Information - ECX. */
236	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
237
238
239	/** CPUID Feature Information - EDX.
240	* CPUID query with EAX=1.
241	*/
242	typedef struct X86CPUIDFEATEDX
243	{
244	/** Bit 0 - FPU - x87 FPU on Chip. */
245	unsigned u1FPU : 1;
246	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
247	unsigned u1VME : 1;
248	/** Bit 2 - DE - Debugging extensions. */
249	unsigned u1DE : 1;
250	/** Bit 3 - PSE - Page Size Extension. */
251	unsigned u1PSE : 1;
252	/** Bit 4 - TSC - Time Stamp Counter. */
253	unsigned u1TSC : 1;
254	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
255	unsigned u1MSR : 1;
256	/** Bit 6 - PAE - Physical Address Extension. */
257	unsigned u1PAE : 1;
258	/** Bit 7 - MCE - Machine Check Exception. */
259	unsigned u1MCE : 1;
260	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
261	unsigned u1CX8 : 1;
262	/** Bit 9 - APIC - APIC On-Chick. */
263	unsigned u1APIC : 1;
264	/** Bit 10 - Reserved. */
265	unsigned u1Reserved1 : 1;
266	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
267	unsigned u1SEP : 1;
268	/** Bit 12 - MTRR - Memory Type Range Registers. */
269	unsigned u1MTRR : 1;
270	/** Bit 13 - PGE - PTE Global Bit. */
271	unsigned u1PGE : 1;
272	/** Bit 14 - MCA - Machine Check Architecture. */
273	unsigned u1MCA : 1;
274	/** Bit 15 - CMOV - Conditional Move Instructions. */
275	unsigned u1CMOV : 1;
276	/** Bit 16 - PAT - Page Attribute Table. */
277	unsigned u1PAT : 1;
278	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
279	unsigned u1PSE36 : 1;
280	/** Bit 18 - PSN - Processor Serial Number. */
281	unsigned u1PSN : 1;
282	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
283	unsigned u1CLFSH : 1;
284	/** Bit 20 - Reserved. */
285	unsigned u1Reserved2 : 1;
286	/** Bit 21 - DS - Debug Store. */
287	unsigned u1DS : 1;
288	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
289	unsigned u1ACPI : 1;
290	/** Bit 23 - MMX - Intel MMX 'Technology'. */
291	unsigned u1MMX : 1;
292	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
293	unsigned u1FXSR : 1;
294	/** Bit 25 - SSE - SSE Support. */
295	unsigned u1SSE : 1;
296	/** Bit 26 - SSE2 - SSE2 Support. */
297	unsigned u1SSE2 : 1;
298	/** Bit 27 - SS - Self Snoop. */
299	unsigned u1SS : 1;
300	/** Bit 28 - HTT - Hyper-Threading Technology. */
301	unsigned u1HTT : 1;
302	/** Bit 29 - TM - Thermal Monitor. */
303	unsigned u1TM : 1;
304	/** Bit 30 - Reserved - . */
305	unsigned u1Reserved3 : 1;
306	/** Bit 31 - PBE - Pending Break Enabled. */
307	unsigned u1PBE : 1;
308	} X86CPUIDFEATEDX;
309	/** Pointer to CPUID Feature Information - EDX. */
310	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
311	/** Pointer to const CPUID Feature Information - EDX. */
312	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
313
314	/** @name CPUID Vendor information.
315	* CPUID query with EAX=0.
316	* @{
317	*/
318	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
319	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
320	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
321
322	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
323	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
324	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
325	/** @} */
326
327
328	/** @name CPUID Feature information.
329	* CPUID query with EAX=1.
330	* @{
331	*/
332	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
333	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
334	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
335	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
336	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
337	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
338	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
339	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
340	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
341	#define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
342	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
343	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
344	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
345	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
346	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
347	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
348	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
349	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
350	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
351	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
352	/** ECX Bit 23 - POPCOUNT instruction. */
353	#define X86_CPUID_FEATURE_ECX_POPCOUNT RT_BIT(23)
354
355
356	/** Bit 0 - FPU - x87 FPU on Chip. */
357	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
358	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
359	#define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
360	/** Bit 2 - DE - Debugging extensions. */
361	#define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
362	/** Bit 3 - PSE - Page Size Extension. */
363	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
364	/** Bit 4 - TSC - Time Stamp Counter. */
365	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
366	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
367	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
368	/** Bit 6 - PAE - Physical Address Extension. */
369	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
370	/** Bit 7 - MCE - Machine Check Exception. */
371	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
372	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
373	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
374	/** Bit 9 - APIC - APIC On-Chip. */
375	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
376	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
377	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
378	/** Bit 12 - MTRR - Memory Type Range Registers. */
379	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
380	/** Bit 13 - PGE - PTE Global Bit. */
381	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
382	/** Bit 14 - MCA - Machine Check Architecture. */
383	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
384	/** Bit 15 - CMOV - Conditional Move Instructions. */
385	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
386	/** Bit 16 - PAT - Page Attribute Table. */
387	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
388	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
389	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
390	/** Bit 18 - PSN - Processor Serial Number. */
391	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
392	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
393	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
394	/** Bit 21 - DS - Debug Store. */
395	#define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
396	/** Bit 22 - ACPI - Termal Monitor and Software Controlled Clock Facilities. */
397	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
398	/** Bit 23 - MMX - Intel MMX Technology. */
399	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
400	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
401	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
402	/** Bit 25 - SSE - SSE Support. */
403	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
404	/** Bit 26 - SSE2 - SSE2 Support. */
405	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
406	/** Bit 27 - SS - Self Snoop. */
407	#define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
408	/** Bit 28 - HTT - Hyper-Threading Technology. */
409	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
410	/** Bit 29 - TM - Therm. Monitor. */
411	#define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
412	/** Bit 31 - PBE - Pending Break Enabled. */
413	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
414	/** @} */
415
416
417	/** @name CPUID AMD Feature information.
418	* CPUID query with EAX=0x80000001.
419	* @{
420	*/
421	/** Bit 0 - FPU - x87 FPU on Chip. */
422	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
423	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
424	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
425	/** Bit 2 - DE - Debugging extensions. */
426	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
427	/** Bit 3 - PSE - Page Size Extension. */
428	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
429	/** Bit 4 - TSC - Time Stamp Counter. */
430	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
431	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
432	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
433	/** Bit 6 - PAE - Physical Address Extension. */
434	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
435	/** Bit 7 - MCE - Machine Check Exception. */
436	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
437	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
438	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
439	/** Bit 9 - APIC - APIC On-Chip. */
440	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
441	/** Bit 11 - SEP - AMD SYSCALL and SYSRET. */
442	#define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
443	/** Bit 12 - MTRR - Memory Type Range Registers. */
444	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
445	/** Bit 13 - PGE - PTE Global Bit. */
446	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
447	/** Bit 14 - MCA - Machine Check Architecture. */
448	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
449	/** Bit 15 - CMOV - Conditional Move Instructions. */
450	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
451	/** Bit 16 - PAT - Page Attribute Table. */
452	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
453	/** Bit 17 - PSE-36 - 36-bit Page Size Extention. */
454	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
455	/** Bit 20 - NX - AMD No-Execute Page Protection. */
456	#define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
457	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
458	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
459	/** Bit 23 - MMX - Intel MMX Technology. */
460	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
461	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
462	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
463	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
464	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
465	/** Bit 26 - PAGE1GB - AMD 1GB large page support. */
466	#define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
467	/** Bit 27 - RDTSCP - AMD RDTSCP instruction. */
468	#define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
469	/** Bit 29 - LM - AMD Long Mode. */
470	#define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
471	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
472	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
473	/** Bit 31 - 3DNOW - AMD 3DNow. */
474	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
475
476	/** Bit 0 - LAHF/SAHF - AMD LAHF and SAHF in 64-bit mode. */
477	#define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
478	/** Bit 1 - CMPL - Core multi-processing legacy mode. */
479	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
480	/** Bit 2 - SVM - AMD VM extensions. */
481	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
482	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
483	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
484	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
485	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
486	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
487	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
488	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
489	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
490	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
491	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
492	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
493	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
494	/** Bit 9 - OSVW - AMD OS visible workaround. */
495	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
496	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
497	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
498	/** Bit 13 - WDT - AMD Watchdog timer support. */
499	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
500
501	/** @} */
502
503
504	/** @name CR0
505	* @{ */
506	/** Bit 0 - PE - Protection Enabled */
507	#define X86_CR0_PE RT_BIT(0)
508	#define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
509	/** Bit 1 - MP - Monitor Coprocessor */
510	#define X86_CR0_MP RT_BIT(1)
511	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
512	/** Bit 2 - EM - Emulation. */
513	#define X86_CR0_EM RT_BIT(2)
514	#define X86_CR0_EMULATE_FPU RT_BIT(2)
515	/** Bit 3 - TS - Task Switch. */
516	#define X86_CR0_TS RT_BIT(3)
517	#define X86_CR0_TASK_SWITCH RT_BIT(3)
518	/** Bit 4 - ET - Extension flag. ('hardcoded' to 1) */
519	#define X86_CR0_ET RT_BIT(4)
520	#define X86_CR0_EXTENSION_TYPE RT_BIT(4)
521	/** Bit 5 - NE - Numeric error. */
522	#define X86_CR0_NE RT_BIT(5)
523	#define X86_CR0_NUMERIC_ERROR RT_BIT(5)
524	/** Bit 16 - WP - Write Protect. */
525	#define X86_CR0_WP RT_BIT(16)
526	#define X86_CR0_WRITE_PROTECT RT_BIT(16)
527	/** Bit 18 - AM - Alignment Mask. */
528	#define X86_CR0_AM RT_BIT(18)
529	#define X86_CR0_ALIGMENT_MASK RT_BIT(18)
530	/** Bit 29 - NW - Not Write-though. */
531	#define X86_CR0_NW RT_BIT(29)
532	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
533	/** Bit 30 - WP - Cache Disable. */
534	#define X86_CR0_CD RT_BIT(30)
535	#define X86_CR0_CACHE_DISABLE RT_BIT(30)
536	/** Bit 31 - PG - Paging. */
537	#define X86_CR0_PG RT_BIT(31)
538	#define X86_CR0_PAGING RT_BIT(31)
539	/** @} */
540
541
542	/** @name CR3
543	* @{ */
544	/** Bit 3 - PWT - Page-level Writes Transparent. */
545	#define X86_CR3_PWT RT_BIT(3)
546	/** Bit 4 - PCD - Page-level Cache Disable. */
547	#define X86_CR3_PCD RT_BIT(4)
548	/** Bits 12-31 - - Page directory page number. */
549	#define X86_CR3_PAGE_MASK (0xfffff000)
550	/** Bits 5-31 - - PAE Page directory page number. */
551	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
552	/** @} */
553
554
555	/** @name CR4
556	* @{ */
557	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
558	#define X86_CR4_VME RT_BIT(0)
559	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
560	#define X86_CR4_PVI RT_BIT(1)
561	/** Bit 2 - TSD - Time Stamp Disable. */
562	#define X86_CR4_TSD RT_BIT(2)
563	/** Bit 3 - DE - Debugging Extensions. */
564	#define X86_CR4_DE RT_BIT(3)
565	/** Bit 4 - PSE - Page Size Extension. */
566	#define X86_CR4_PSE RT_BIT(4)
567	/** Bit 5 - PAE - Physical Address Extension. */
568	#define X86_CR4_PAE RT_BIT(5)
569	/** Bit 6 - MCE - Machine-Check Enable. */
570	#define X86_CR4_MCE RT_BIT(6)
571	/** Bit 7 - PGE - Page Global Enable. */
572	#define X86_CR4_PGE RT_BIT(7)
573	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
574	#define X86_CR4_PCE RT_BIT(8)
575	/** Bit 9 - OSFSXR - Operating System Support for FXSAVE and FXRSTORE instruction. */
576	#define X86_CR4_OSFSXR RT_BIT(9)
577	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
578	#define X86_CR4_OSXMMEEXCPT RT_BIT(10)
579	/** Bit 13 - VMXE - VMX mode is enabled. */
580	#define X86_CR4_VMXE RT_BIT(13)
581	/** @} */
582
583
584	/** @name DR6
585	* @{ */
586	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
587	#define X86_DR6_B0 RT_BIT(0)
588	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
589	#define X86_DR6_B1 RT_BIT(1)
590	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
591	#define X86_DR6_B2 RT_BIT(2)
592	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
593	#define X86_DR6_B3 RT_BIT(3)
594	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
595	#define X86_DR6_BD RT_BIT(13)
596	/** Bit 14 - BS - Single step */
597	#define X86_DR6_BS RT_BIT(14)
598	/** Bit 15 - BT - Task switch. (TSS T bit.) */
599	#define X86_DR6_BT RT_BIT(15)
600	/** @} */
601
602
603	/** @name DR7
604	* @{ */
605	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
606	#define X86_DR7_L0 RT_BIT(0)
607	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
608	#define X86_DR7_G0 RT_BIT(1)
609	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
610	#define X86_DR7_L1 RT_BIT(2)
611	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
612	#define X86_DR7_G1 RT_BIT(3)
613	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
614	#define X86_DR7_L2 RT_BIT(4)
615	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
616	#define X86_DR7_G2 RT_BIT(5)
617	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
618	#define X86_DR7_L3 RT_BIT(6)
619	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
620	#define X86_DR7_G3 RT_BIT(7)
621	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
622	#define X86_DR7_LE RT_BIT(8)
623	/** Bit 9 - GE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
624	#define X86_DR7_GE RT_BIT(9)
625
626	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
627	* any DR register is accessed. */
628	#define X86_DR7_GD RT_BIT(13)
629	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
630	#define X86_DR7_RW0_MASK (3 << 16)
631	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
632	#define X86_DR7_LEN0_MASK (3 << 18)
633	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
634	#define X86_DR7_RW1_MASK (3 << 20)
635	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
636	#define X86_DR7_LEN1_MASK (3 << 22)
637	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
638	#define X86_DR7_RW2_MASK (3 << 24)
639	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
640	#define X86_DR7_LEN2_MASK (3 << 26)
641	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
642	#define X86_DR7_RW3_MASK (3 << 28)
643	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
644	#define X86_DR7_LEN3_MASK (3 << 30)
645
646	/** Bits which must be 1s. */
647	#define X86_DR7_MB1_MASK (RT_BIT(10))
648
649	/** Calcs the L bit of Nth breakpoint.
650	* @param iBp The breakpoint number [0..3].
651	*/
652	#define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
653
654	/** Calcs the G bit of Nth breakpoint.
655	* @param iBp The breakpoint number [0..3].
656	*/
657	#define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
658
659	/** @name Read/Write values.
660	* @{ */
661	/** Break on instruction fetch only. */
662	#define X86_DR7_RW_EO 0
663	/** Break on write only. */
664	#define X86_DR7_RW_WO 1
665	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
666	#define X86_DR7_RW_IO 2
667	/** Break on read or write (but not instruction fetches). */
668	#define X86_DR7_RW_RW 3
669	/** @} */
670
671	/** Shifts a X86_DR7_RW_* value to its right place.
672	* @param iBp The breakpoint number [0..3].
673	* @param fRw One of the X86_DR7_RW_* value.
674	*/
675	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
676
677	/** @name Length values.
678	* @{ */
679	#define X86_DR7_LEN_BYTE 0
680	#define X86_DR7_LEN_WORD 1
681	#define X86_DR7_LEN_QWORD 2 /*< AMD64 long mode only. /
682	#define X86_DR7_LEN_DWORD 3
683	/** @} */
684
685	/** Shifts a X86_DR7_LEN_* value to its right place.
686	* @param iBp The breakpoint number [0..3].
687	* @param cb One of the X86_DR7_LEN_* values.
688	*/
689	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
690
691	/** Mask used to check if any breakpoints are enabled. */
692	#define X86_DR7_ENABLED_MASK (RT_BIT(0) \| RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3) \| RT_BIT(4) \| RT_BIT(6) \| RT_BIT(7))
693
694	/** @} */
695
696
697	/** @name Machine Specific Registers
698	* @{
699	*/
700	/** CPU Feature control. */
701	#define MSR_IA32_FEATURE_CONTROL 0x3A
702	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
703	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
704
705
706	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h klugde */
707	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
708	* R0 SS == CS + 8
709	* R3 CS == CS + 16
710	* R3 SS == CS + 24
711	*/
712	#define MSR_IA32_SYSENTER_CS 0x174
713	/** SYSENTER_ESP - the R0 ESP. */
714	#define MSR_IA32_SYSENTER_ESP 0x175
715	/** SYSENTER_EIP - the R0 EIP. */
716	#define MSR_IA32_SYSENTER_EIP 0x176
717	#endif
718
719	/* Page Attribute Table. */
720	#define IA32_CR_PAT 0x277
721
722	/** Basic VMX information. */
723	#define MSR_IA32_VMX_BASIC_INFO 0x480
724	/** Allowed settings for pin-based VM execution controls */
725	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
726	/** Allowed settings for proc-based VM execution controls */
727	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
728	/** Allowed settings for the VMX exit controls. */
729	#define MSR_IA32_VMX_EXIT_CTLS 0x483
730	/** Allowed settings for the VMX entry controls. */
731	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
732	/** Misc VMX info. */
733	#define MSR_IA32_VMX_MISC 0x485
734	/** Fixed cleared bits in CR0. */
735	#define MSR_IA32_VMX_CR0_FIXED0 0x486
736	/** Fixed set bits in CR0. */
737	#define MSR_IA32_VMX_CR0_FIXED1 0x487
738	/** Fixed cleared bits in CR4. */
739	#define MSR_IA32_VMX_CR4_FIXED0 0x488
740	/** Fixed set bits in CR4. */
741	#define MSR_IA32_VMX_CR4_FIXED1 0x489
742	/** Information for enumerating fields in the VMCS. */
743	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
744
745
746	/** K6 EFER - Extended Feature Enable Register. */
747	#define MSR_K6_EFER 0xc0000080
748	/** @todo document EFER */
749	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
750	#define MSR_K6_EFER_SCE RT_BIT(0)
751	/** Bit 8 - LME - Long mode enabled. (R/W) */
752	#define MSR_K6_EFER_LME RT_BIT(8)
753	/** Bit 10 - LMA - Long mode active. (R) */
754	#define MSR_K6_EFER_LMA RT_BIT(10)
755	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
756	#define MSR_K6_EFER_NXE RT_BIT(11)
757	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
758	#define MSR_K6_EFER_SVME RT_BIT(12)
759	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
760	#define MSR_K6_EFER_LMSLE RT_BIT(13)
761	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
762	#define MSR_K6_EFER_FFXSR RT_BIT(14)
763	/** K6 STAR - SYSCALL/RET targets. */
764	#define MSR_K6_STAR 0xc0000081
765	/** Shift value for getting the SYSRET CS and SS value. */
766	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
767	/** Shift value for getting the SYSCALL CS and SS value. */
768	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
769	/** Selector mask for use after shifting. */
770	#define MSR_K6_STAR_SEL_MASK 0xffff
771	/** The mask which give the SYSCALL EIP. */
772	#define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
773	/** K6 WHCR - Write Handling Control Register. */
774	#define MSR_K6_WHCR 0xc0000082
775	/** K6 UWCCR - UC/WC Cacheability Control Register. */
776	#define MSR_K6_UWCCR 0xc0000085
777	/** K6 PSOR - Processor State Observability Register. */
778	#define MSR_K6_PSOR 0xc0000087
779	/** K6 PFIR - Page Flush/Invalidate Register. */
780	#define MSR_K6_PFIR 0xc0000088
781
782	#define MSR_K7_EVNTSEL0 0xc0010000
783	#define MSR_K7_EVNTSEL1 0xc0010001
784	#define MSR_K7_EVNTSEL2 0xc0010002
785	#define MSR_K7_EVNTSEL3 0xc0010003
786	#define MSR_K7_PERFCTR0 0xc0010004
787	#define MSR_K7_PERFCTR1 0xc0010005
788	#define MSR_K7_PERFCTR2 0xc0010006
789	#define MSR_K7_PERFCTR3 0xc0010007
790
791	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
792	#define MSR_K8_LSTAR 0xc0000082
793	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
794	#define MSR_K8_CSTAR 0xc0000083
795	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
796	#define MSR_K8_SF_MASK 0xc0000084
797	/** K8 FS.base - The 64-bit base FS register. */
798	#define MSR_K8_FS_BASE 0xc0000100
799	/** K8 GS.base - The 64-bit base GS register. */
800	#define MSR_K8_GS_BASE 0xc0000101
801	/** K8 KernelGSbase - Used with SWAPGS. */
802	#define MSR_K8_KERNEL_GS_BASE 0xc0000102
803	#define MSR_K8_TSC_AUX 0xc0000103
804	#define MSR_K8_SYSCFG 0xc0010010
805	#define MSR_K8_HWCR 0xc0010015
806	#define MSR_K8_IORRBASE0 0xc0010016
807	#define MSR_K8_IORRMASK0 0xc0010017
808	#define MSR_K8_IORRBASE1 0xc0010018
809	#define MSR_K8_IORRMASK1 0xc0010019
810	#define MSR_K8_TOP_MEM1 0xc001001a
811	#define MSR_K8_TOP_MEM2 0xc001001d
812	#define MSR_K8_VM_CR 0xc0010114
813	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
814
815	#define MSR_K8_IGNNE 0xc0010115
816	#define MSR_K8_SMM_CTL 0xc0010116
817	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
818	* host state during world switch.
819	*/
820	#define MSR_K8_VM_HSAVE_PA 0xc0010117
821
822	/** @} */
823
824
825	/** @name Page Table / Directory / Directory Pointers / L4.
826	* @{
827	*/
828
829	/** Page table/directory entry as an unsigned integer. */
830	typedef uint32_t X86PGUINT;
831	/** Pointer to a page table/directory table entry as an unsigned integer. */
832	typedef X86PGUINT *PX86PGUINT;
833
834	/** Number of entries in a 32-bit PT/PD. */
835	#define X86_PG_ENTRIES 1024
836
837
838	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
839	typedef uint64_t X86PGPAEUINT;
840	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
841	typedef X86PGPAEUINT *PX86PGPAEUINT;
842
843	/** Number of entries in a PAE PT/PD. */
844	#define X86_PG_PAE_ENTRIES 512
845	/** Number of entries in a PAE PDPT. */
846	#define X86_PG_PAE_PDPE_ENTRIES 4
847
848	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
849	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
850	/** Number of entries in an AMD64 PDPT.
851	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
852	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
853
854	/** The size of a 4KB page. */
855	#define X86_PAGE_4K_SIZE _4K
856	/** The page shift of a 4KB page. */
857	#define X86_PAGE_4K_SHIFT 12
858	/** The 4KB page offset mask. */
859	#define X86_PAGE_4K_OFFSET_MASK 0xfff
860	/** The 4KB page base mask for virtual addresses. */
861	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
862	/** The 4KB page base mask for virtual addresses - 32bit version. */
863	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
864
865	/** The size of a 2MB page. */
866	#define X86_PAGE_2M_SIZE _2M
867	/** The page shift of a 2MB page. */
868	#define X86_PAGE_2M_SHIFT 21
869	/** The 2MB page offset mask. */
870	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
871	/** The 2MB page base mask for virtual addresses. */
872	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
873	/** The 2MB page base mask for virtual addresses - 32bit version. */
874	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
875
876	/** The size of a 4MB page. */
877	#define X86_PAGE_4M_SIZE _4M
878	/** The page shift of a 4MB page. */
879	#define X86_PAGE_4M_SHIFT 22
880	/** The 4MB page offset mask. */
881	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
882	/** The 4MB page base mask for virtual addresses. */
883	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
884	/** The 4MB page base mask for virtual addresses - 32bit version. */
885	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
886
887
888
889	/** @name Page Table Entry
890	* @{
891	*/
892	/** Bit 0 - P - Present bit. */
893	#define X86_PTE_P RT_BIT(0)
894	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
895	#define X86_PTE_RW RT_BIT(1)
896	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
897	#define X86_PTE_US RT_BIT(2)
898	/** Bit 3 - PWT - Page level write thru bit. */
899	#define X86_PTE_PWT RT_BIT(3)
900	/** Bit 4 - PCD - Page level cache disable bit. */
901	#define X86_PTE_PCD RT_BIT(4)
902	/** Bit 5 - A - Access bit. */
903	#define X86_PTE_A RT_BIT(5)
904	/** Bit 6 - D - Dirty bit. */
905	#define X86_PTE_D RT_BIT(6)
906	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
907	#define X86_PTE_PAT RT_BIT(7)
908	/** Bit 8 - G - Global flag. */
909	#define X86_PTE_G RT_BIT(8)
910	/** Bits 9-11 - - Available for use to system software. */
911	#define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
912	/** Bits 12-31 - - Physical Page number of the next level. */
913	#define X86_PTE_PG_MASK ( 0xfffff000 )
914
915	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
916	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
917	#define X86_PTE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
918	#else
919	#define X86_PTE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
920	#endif
921	/** Bits 63 - NX - PAE - No execution flag. */
922	#define X86_PTE_PAE_NX RT_BIT_64(63)
923
924	/**
925	* Page table entry.
926	*/
927	typedef struct X86PTEBITS
928	{
929	/** Flags whether(=1) or not the page is present. */
930	unsigned u1Present : 1;
931	/** Read(=0) / Write(=1) flag. */
932	unsigned u1Write : 1;
933	/** User(=1) / Supervisor (=0) flag. */
934	unsigned u1User : 1;
935	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
936	unsigned u1WriteThru : 1;
937	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
938	unsigned u1CacheDisable : 1;
939	/** Accessed flag.
940	* Indicates that the page have been read or written to. */
941	unsigned u1Accessed : 1;
942	/** Dirty flag.
943	* Indicates that the page have been written to. */
944	unsigned u1Dirty : 1;
945	/** Reserved / If PAT enabled, bit 2 of the index. */
946	unsigned u1PAT : 1;
947	/** Global flag. (Ignored in all but final level.) */
948	unsigned u1Global : 1;
949	/** Available for use to system software. */
950	unsigned u3Available : 3;
951	/** Physical Page number of the next level. */
952	unsigned u20PageNo : 20;
953	} X86PTEBITS;
954	/** Pointer to a page table entry. */
955	typedef X86PTEBITS *PX86PTEBITS;
956	/** Pointer to a const page table entry. */
957	typedef const X86PTEBITS *PCX86PTEBITS;
958
959	/**
960	* Page table entry.
961	*/
962	typedef union X86PTE
963	{
964	/** Bit field view. */
965	X86PTEBITS n;
966	/** Unsigned integer view */
967	X86PGUINT u;
968	/** 32-bit view. */
969	uint32_t au32[1];
970	/** 16-bit view. */
971	uint16_t au16[2];
972	/** 8-bit view. */
973	uint8_t au8[4];
974	} X86PTE;
975	/** Pointer to a page table entry. */
976	typedef X86PTE *PX86PTE;
977	/** Pointer to a const page table entry. */
978	typedef const X86PTE *PCX86PTE;
979
980
981	/**
982	* PAE page table entry.
983	*/
984	typedef struct X86PTEPAEBITS
985	{
986	/** Flags whether(=1) or not the page is present. */
987	uint32_t u1Present : 1;
988	/** Read(=0) / Write(=1) flag. */
989	uint32_t u1Write : 1;
990	/** User(=1) / Supervisor(=0) flag. */
991	uint32_t u1User : 1;
992	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
993	uint32_t u1WriteThru : 1;
994	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
995	uint32_t u1CacheDisable : 1;
996	/** Accessed flag.
997	* Indicates that the page have been read or written to. */
998	uint32_t u1Accessed : 1;
999	/** Dirty flag.
1000	* Indicates that the page have been written to. */
1001	uint32_t u1Dirty : 1;
1002	/** Reserved / If PAT enabled, bit 2 of the index. */
1003	uint32_t u1PAT : 1;
1004	/** Global flag. (Ignored in all but final level.) */
1005	uint32_t u1Global : 1;
1006	/** Available for use to system software. */
1007	uint32_t u3Available : 3;
1008	/** Physical Page number of the next level - Low Part. Don't use this. */
1009	uint32_t u20PageNoLow : 20;
1010	/** Physical Page number of the next level - High Part. Don't use this. */
1011	uint32_t u20PageNoHigh : 20;
1012	/** MBZ bits */
1013	uint32_t u11Reserved : 11;
1014	/** No Execute flag. */
1015	uint32_t u1NoExecute : 1;
1016	} X86PTEPAEBITS;
1017	/** Pointer to a page table entry. */
1018	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
1019	/** Pointer to a page table entry. */
1020	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
1021
1022	/**
1023	* PAE Page table entry.
1024	*/
1025	typedef union X86PTEPAE
1026	{
1027	/** Bit field view. */
1028	X86PTEPAEBITS n;
1029	/** Unsigned integer view */
1030	X86PGPAEUINT u;
1031	/** 32-bit view. */
1032	uint32_t au32[2];
1033	/** 16-bit view. */
1034	uint16_t au16[4];
1035	/** 8-bit view. */
1036	uint8_t au8[8];
1037	} X86PTEPAE;
1038	/** Pointer to a PAE page table entry. */
1039	typedef X86PTEPAE *PX86PTEPAE;
1040	/** Pointer to a const PAE page table entry. */
1041	typedef const X86PTEPAE *PCX86PTEPAE;
1042	/** @} */
1043
1044	/**
1045	* Page table.
1046	*/
1047	typedef struct X86PT
1048	{
1049	/** PTE Array. */
1050	X86PTE a[X86_PG_ENTRIES];
1051	} X86PT;
1052	/** Pointer to a page table. */
1053	typedef X86PT *PX86PT;
1054	/** Pointer to a const page table. */
1055	typedef const X86PT *PCX86PT;
1056
1057	/** The page shift to get the PT index. */
1058	#define X86_PT_SHIFT 12
1059	/** The PT index mask (apply to a shifted page address). */
1060	#define X86_PT_MASK 0x3ff
1061
1062
1063	/**
1064	* Page directory.
1065	*/
1066	typedef struct X86PTPAE
1067	{
1068	/** PTE Array. */
1069	X86PTEPAE a[X86_PG_PAE_ENTRIES];
1070	} X86PTPAE;
1071	/** Pointer to a page table. */
1072	typedef X86PTPAE *PX86PTPAE;
1073	/** Pointer to a const page table. */
1074	typedef const X86PTPAE *PCX86PTPAE;
1075
1076	/** The page shift to get the PA PTE index. */
1077	#define X86_PT_PAE_SHIFT 12
1078	/** The PAE PT index mask (apply to a shifted page address). */
1079	#define X86_PT_PAE_MASK 0x1ff
1080
1081
1082	/** @name 4KB Page Directory Entry
1083	* @{
1084	*/
1085	/** Bit 0 - P - Present bit. */
1086	#define X86_PDE_P RT_BIT(0)
1087	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1088	#define X86_PDE_RW RT_BIT(1)
1089	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1090	#define X86_PDE_US RT_BIT(2)
1091	/** Bit 3 - PWT - Page level write thru bit. */
1092	#define X86_PDE_PWT RT_BIT(3)
1093	/** Bit 4 - PCD - Page level cache disable bit. */
1094	#define X86_PDE_PCD RT_BIT(4)
1095	/** Bit 5 - A - Access bit. */
1096	#define X86_PDE_A RT_BIT(5)
1097	/** Bit 7 - PS - Page size attribute.
1098	* Clear mean 4KB pages, set means large pages (2/4MB). */
1099	#define X86_PDE_PS RT_BIT(7)
1100	/** Bits 9-11 - - Available for use to system software. */
1101	#define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1102	/** Bits 12-31 - - Physical Page number of the next level. */
1103	#define X86_PDE_PG_MASK ( 0xfffff000 )
1104
1105	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1106	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1107	#define X86_PDE_PAE_PG_MASK ( 0x0000fffffffff000ULL )
1108	#else
1109	#define X86_PDE_PAE_PG_MASK ( 0x000ffffffffff000ULL )
1110	#endif
1111	/** Bits 63 - NX - PAE - No execution flag. */
1112	#define X86_PDE_PAE_NX RT_BIT_64(63)
1113
1114	/**
1115	* Page directory entry.
1116	*/
1117	typedef struct X86PDEBITS
1118	{
1119	/** Flags whether(=1) or not the page is present. */
1120	unsigned u1Present : 1;
1121	/** Read(=0) / Write(=1) flag. */
1122	unsigned u1Write : 1;
1123	/** User(=1) / Supervisor (=0) flag. */
1124	unsigned u1User : 1;
1125	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1126	unsigned u1WriteThru : 1;
1127	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1128	unsigned u1CacheDisable : 1;
1129	/** Accessed flag.
1130	* Indicates that the page have been read or written to. */
1131	unsigned u1Accessed : 1;
1132	/** Reserved / Ignored (dirty bit). */
1133	unsigned u1Reserved0 : 1;
1134	/** Size bit if PSE is enabled - in any event it's 0. */
1135	unsigned u1Size : 1;
1136	/** Reserved / Ignored (global bit). */
1137	unsigned u1Reserved1 : 1;
1138	/** Available for use to system software. */
1139	unsigned u3Available : 3;
1140	/** Physical Page number of the next level. */
1141	unsigned u20PageNo : 20;
1142	} X86PDEBITS;
1143	/** Pointer to a page directory entry. */
1144	typedef X86PDEBITS *PX86PDEBITS;
1145	/** Pointer to a const page directory entry. */
1146	typedef const X86PDEBITS *PCX86PDEBITS;
1147
1148
1149	/**
1150	* PAE page directory entry.
1151	*/
1152	typedef struct X86PDEPAEBITS
1153	{
1154	/** Flags whether(=1) or not the page is present. */
1155	uint32_t u1Present : 1;
1156	/** Read(=0) / Write(=1) flag. */
1157	uint32_t u1Write : 1;
1158	/** User(=1) / Supervisor (=0) flag. */
1159	uint32_t u1User : 1;
1160	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1161	uint32_t u1WriteThru : 1;
1162	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1163	uint32_t u1CacheDisable : 1;
1164	/** Accessed flag.
1165	* Indicates that the page have been read or written to. */
1166	uint32_t u1Accessed : 1;
1167	/** Reserved / Ignored (dirty bit). */
1168	uint32_t u1Reserved0 : 1;
1169	/** Size bit if PSE is enabled - in any event it's 0. */
1170	uint32_t u1Size : 1;
1171	/** Reserved / Ignored (global bit). / */
1172	uint32_t u1Reserved1 : 1;
1173	/** Available for use to system software. */
1174	uint32_t u3Available : 3;
1175	/** Physical Page number of the next level - Low Part. Don't use! */
1176	uint32_t u20PageNoLow : 20;
1177	/** Physical Page number of the next level - High Part. Don't use! */
1178	uint32_t u20PageNoHigh : 20;
1179	/** MBZ bits */
1180	uint32_t u11Reserved : 11;
1181	/** No Execute flag. */
1182	uint32_t u1NoExecute : 1;
1183	} X86PDEPAEBITS;
1184	/** Pointer to a page directory entry. */
1185	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
1186	/** Pointer to a const page directory entry. */
1187	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
1188
1189	/** @} */
1190
1191
1192	/** @name 2/4MB Page Directory Entry
1193	* @{
1194	*/
1195	/** Bit 0 - P - Present bit. */
1196	#define X86_PDE4M_P RT_BIT(0)
1197	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1198	#define X86_PDE4M_RW RT_BIT(1)
1199	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1200	#define X86_PDE4M_US RT_BIT(2)
1201	/** Bit 3 - PWT - Page level write thru bit. */
1202	#define X86_PDE4M_PWT RT_BIT(3)
1203	/** Bit 4 - PCD - Page level cache disable bit. */
1204	#define X86_PDE4M_PCD RT_BIT(4)
1205	/** Bit 5 - A - Access bit. */
1206	#define X86_PDE4M_A RT_BIT(5)
1207	/** Bit 6 - D - Dirty bit. */
1208	#define X86_PDE4M_D RT_BIT(6)
1209	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
1210	#define X86_PDE4M_PS RT_BIT(7)
1211	/** Bit 8 - G - Global flag. */
1212	#define X86_PDE4M_G RT_BIT(8)
1213	/** Bits 9-11 - AVL - Available for use to system software. */
1214	#define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1215	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1216	#define X86_PDE4M_PAT RT_BIT(12)
1217	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
1218	#define X86_PDE4M_PAT_SHIFT (12 - 7)
1219	/** Bits 22-31 - - Physical Page number. */
1220	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
1221	/** Bits 13-20 - - Physical Page number high part (32-39 bits). AMD64 hack. */
1222	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
1223	/** The number of bits to the high part of the page number. */
1224	#define X86_PDE4M_PG_HIGH_SHIFT 19
1225
1226	/** Bits 21-51 - - PAE & AMD64 - Physical Page number.
1227	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
1228	#define X86_PDE2M_PAE_PG_MASK ( 0x000fffffffe00000ULL )
1229	/** Bits 63 - NX - PAE & AMD64 - No execution flag. */
1230	#define X86_PDE2M_PAE_NX X86_PDE2M_PAE_NX
1231
1232	/**
1233	* 4MB page directory entry.
1234	*/
1235	typedef struct X86PDE4MBITS
1236	{
1237	/** Flags whether(=1) or not the page is present. */
1238	unsigned u1Present : 1;
1239	/** Read(=0) / Write(=1) flag. */
1240	unsigned u1Write : 1;
1241	/** User(=1) / Supervisor (=0) flag. */
1242	unsigned u1User : 1;
1243	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1244	unsigned u1WriteThru : 1;
1245	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1246	unsigned u1CacheDisable : 1;
1247	/** Accessed flag.
1248	* Indicates that the page have been read or written to. */
1249	unsigned u1Accessed : 1;
1250	/** Dirty flag.
1251	* Indicates that the page have been written to. */
1252	unsigned u1Dirty : 1;
1253	/** Page size flag - always 1 for 4MB entries. */
1254	unsigned u1Size : 1;
1255	/** Global flag. */
1256	unsigned u1Global : 1;
1257	/** Available for use to system software. */
1258	unsigned u3Available : 3;
1259	/** Reserved / If PAT enabled, bit 2 of the index. */
1260	unsigned u1PAT : 1;
1261	/** Bits 32-39 of the page number on AMD64.
1262	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
1263	unsigned u8PageNoHigh : 8;
1264	/** Reserved. */
1265	unsigned u1Reserved : 1;
1266	/** Physical Page number of the page. */
1267	unsigned u10PageNo : 10;
1268	} X86PDE4MBITS;
1269	/** Pointer to a page table entry. */
1270	typedef X86PDE4MBITS *PX86PDE4MBITS;
1271	/** Pointer to a const page table entry. */
1272	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
1273
1274
1275	/**
1276	* 2MB PAE page directory entry.
1277	*/
1278	typedef struct X86PDE2MPAEBITS
1279	{
1280	/** Flags whether(=1) or not the page is present. */
1281	uint32_t u1Present : 1;
1282	/** Read(=0) / Write(=1) flag. */
1283	uint32_t u1Write : 1;
1284	/** User(=1) / Supervisor(=0) flag. */
1285	uint32_t u1User : 1;
1286	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1287	uint32_t u1WriteThru : 1;
1288	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1289	uint32_t u1CacheDisable : 1;
1290	/** Accessed flag.
1291	* Indicates that the page have been read or written to. */
1292	uint32_t u1Accessed : 1;
1293	/** Dirty flag.
1294	* Indicates that the page have been written to. */
1295	uint32_t u1Dirty : 1;
1296	/** Page size flag - always 1 for 2MB entries. */
1297	uint32_t u1Size : 1;
1298	/** Global flag. */
1299	uint32_t u1Global : 1;
1300	/** Available for use to system software. */
1301	uint32_t u3Available : 3;
1302	/** Reserved / If PAT enabled, bit 2 of the index. */
1303	uint32_t u1PAT : 1;
1304	/** Reserved. */
1305	uint32_t u9Reserved : 9;
1306	/** Physical Page number of the next level - Low part. Don't use! */
1307	uint32_t u10PageNoLow : 10;
1308	/** Physical Page number of the next level - High part. Don't use! */
1309	uint32_t u20PageNoHigh : 20;
1310	/** MBZ bits */
1311	uint32_t u11Reserved : 11;
1312	/** No Execute flag. */
1313	uint32_t u1NoExecute : 1;
1314	} X86PDE2MPAEBITS;
1315	/** Pointer to a 4MB PAE page table entry. */
1316	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
1317	/** Pointer to a 4MB PAE page table entry. */
1318	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
1319
1320	/** @} */
1321
1322	/**
1323	* Page directory entry.
1324	*/
1325	typedef union X86PDE
1326	{
1327	/** Normal view. */
1328	X86PDEBITS n;
1329	/** 4MB view (big). */
1330	X86PDE4MBITS b;
1331	/** Unsigned integer view. */
1332	X86PGUINT u;
1333	/** 8 bit unsigned integer view. */
1334	uint8_t au8[4];
1335	/** 16 bit unsigned integer view. */
1336	uint16_t au16[2];
1337	/** 32 bit unsigned integer view. */
1338	uint32_t au32[1];
1339	} X86PDE;
1340	/** Pointer to a page directory entry. */
1341	typedef X86PDE *PX86PDE;
1342	/** Pointer to a const page directory entry. */
1343	typedef const X86PDE *PCX86PDE;
1344
1345	/**
1346	* PAE page directory entry.
1347	*/
1348	typedef union X86PDEPAE
1349	{
1350	/** Normal view. */
1351	X86PDEPAEBITS n;
1352	/** 2MB page view (big). */
1353	X86PDE2MPAEBITS b;
1354	/** Unsigned integer view. */
1355	X86PGPAEUINT u;
1356	/** 8 bit unsigned integer view. */
1357	uint8_t au8[8];
1358	/** 16 bit unsigned integer view. */
1359	uint16_t au16[4];
1360	/** 32 bit unsigned integer view. */
1361	uint32_t au32[2];
1362	} X86PDEPAE;
1363	/** Pointer to a page directory entry. */
1364	typedef X86PDEPAE *PX86PDEPAE;
1365	/** Pointer to a const page directory entry. */
1366	typedef const X86PDEPAE *PCX86PDEPAE;
1367
1368	/**
1369	* Page directory.
1370	*/
1371	typedef struct X86PD
1372	{
1373	/** PDE Array. */
1374	X86PDE a[X86_PG_ENTRIES];
1375	} X86PD;
1376	/** Pointer to a page directory. */
1377	typedef X86PD *PX86PD;
1378	/** Pointer to a const page directory. */
1379	typedef const X86PD *PCX86PD;
1380
1381	/** The page shift to get the PD index. */
1382	#define X86_PD_SHIFT 22
1383	/** The PD index mask (apply to a shifted page address). */
1384	#define X86_PD_MASK 0x3ff
1385
1386
1387	/**
1388	* PAE page directory.
1389	*/
1390	typedef struct X86PDPAE
1391	{
1392	/** PDE Array. */
1393	X86PDEPAE a[X86_PG_PAE_ENTRIES];
1394	} X86PDPAE;
1395	/** Pointer to a PAE page directory. */
1396	typedef X86PDPAE *PX86PDPAE;
1397	/** Pointer to a const PAE page directory. */
1398	typedef const X86PDPAE *PCX86PDPAE;
1399
1400	/** The page shift to get the PAE PD index. */
1401	#define X86_PD_PAE_SHIFT 21
1402	/** The PAE PD index mask (apply to a shifted page address). */
1403	#define X86_PD_PAE_MASK 0x1ff
1404
1405
1406	/** @name Page Directory Pointer Table Entry (PAE)
1407	* @{
1408	*/
1409	/** Bit 0 - P - Present bit. */
1410	#define X86_PDPE_P RT_BIT(0)
1411	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
1412	#define X86_PDPE_RW RT_BIT(1)
1413	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
1414	#define X86_PDPE_US RT_BIT(2)
1415	/** Bit 3 - PWT - Page level write thru bit. */
1416	#define X86_PDPE_PWT RT_BIT(3)
1417	/** Bit 4 - PCD - Page level cache disable bit. */
1418	#define X86_PDPE_PCD RT_BIT(4)
1419	/** Bit 5 - A - Access bit. Long Mode only. */
1420	#define X86_PDPE_A RT_BIT(5)
1421	/** Bits 9-11 - - Available for use to system software. */
1422	#define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1423	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1424	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1425	#define X86_PDPE_PG_MASK ( 0x0000fffffffff000ULL )
1426	#else
1427	#define X86_PDPE_PG_MASK ( 0x000ffffffffff000ULL )
1428	#endif
1429	/** Bits 63 - NX - PAE - No execution flag. Long Mode only. */
1430	#define X86_PDPE_NX RT_BIT_64(63)
1431
1432	/**
1433	* Page directory pointer table entry.
1434	*/
1435	typedef struct X86PDPEBITS
1436	{
1437	/** Flags whether(=1) or not the page is present. */
1438	uint32_t u1Present : 1;
1439	/** Chunk of reserved bits. */
1440	uint32_t u2Reserved : 2;
1441	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1442	uint32_t u1WriteThru : 1;
1443	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1444	uint32_t u1CacheDisable : 1;
1445	/** Chunk of reserved bits. */
1446	uint32_t u4Reserved : 4;
1447	/** Available for use to system software. */
1448	uint32_t u3Available : 3;
1449	/** Physical Page number of the next level - Low Part. Don't use! */
1450	uint32_t u20PageNoLow : 20;
1451	/** Physical Page number of the next level - High Part. Don't use! */
1452	uint32_t u20PageNoHigh : 20;
1453	/** MBZ bits */
1454	uint32_t u12Reserved : 12;
1455	} X86PDPEBITS;
1456	/** Pointer to a page directory pointer table entry. */
1457	typedef X86PDPEBITS *PX86PTPEBITS;
1458	/** Pointer to a const page directory pointer table entry. */
1459	typedef const X86PDPEBITS *PCX86PTPEBITS;
1460
1461	/**
1462	* Page directory pointer table entry. AMD64 version
1463	*/
1464	typedef struct X86PDPEAMD64BITS
1465	{
1466	/** Flags whether(=1) or not the page is present. */
1467	uint32_t u1Present : 1;
1468	/** Read(=0) / Write(=1) flag. */
1469	uint32_t u1Write : 1;
1470	/** User(=1) / Supervisor (=0) flag. */
1471	uint32_t u1User : 1;
1472	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1473	uint32_t u1WriteThru : 1;
1474	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1475	uint32_t u1CacheDisable : 1;
1476	/** Accessed flag.
1477	* Indicates that the page have been read or written to. */
1478	uint32_t u1Accessed : 1;
1479	/** Chunk of reserved bits. */
1480	uint32_t u3Reserved : 3;
1481	/** Available for use to system software. */
1482	uint32_t u3Available : 3;
1483	/** Physical Page number of the next level - Low Part. Don't use! */
1484	uint32_t u20PageNoLow : 20;
1485	/** Physical Page number of the next level - High Part. Don't use! */
1486	uint32_t u20PageNoHigh : 20;
1487	/** MBZ bits */
1488	uint32_t u11Reserved : 11;
1489	/** No Execute flag. */
1490	uint32_t u1NoExecute : 1;
1491	} X86PDPEAMD64BITS;
1492	/** Pointer to a page directory pointer table entry. */
1493	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
1494	/** Pointer to a const page directory pointer table entry. */
1495	typedef const X86PDPEBITS *PCX86PDPEAMD64BITS;
1496
1497	/**
1498	* Page directory pointer table entry.
1499	*/
1500	typedef union X86PDPE
1501	{
1502	/** Normal view. */
1503	X86PDPEBITS n;
1504	/** AMD64 view. */
1505	X86PDPEAMD64BITS lm;
1506	/** Unsigned integer view. */
1507	X86PGPAEUINT u;
1508	/** 8 bit unsigned integer view. */
1509	uint8_t au8[8];
1510	/** 16 bit unsigned integer view. */
1511	uint16_t au16[4];
1512	/** 32 bit unsigned integer view. */
1513	uint32_t au32[2];
1514	} X86PDPE;
1515	/** Pointer to a page directory pointer table entry. */
1516	typedef X86PDPE *PX86PDPE;
1517	/** Pointer to a const page directory pointer table entry. */
1518	typedef const X86PDPE *PCX86PDPE;
1519
1520
1521	/**
1522	* Page directory pointer table.
1523	*/
1524	typedef struct X86PDPT
1525	{
1526	/** PDE Array. */
1527	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
1528	} X86PDPT;
1529	/** Pointer to a page directory pointer table. */
1530	typedef X86PDPT *PX86PDPT;
1531	/** Pointer to a const page directory pointer table. */
1532	typedef const X86PDPT *PCX86PDPT;
1533
1534	/** The page shift to get the PDPT index. */
1535	#define X86_PDPT_SHIFT 30
1536	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
1537	#define X86_PDPT_MASK_PAE 0x3
1538	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
1539	#define X86_PDPT_MASK_AMD64 0x1ff
1540
1541	/** @} */
1542
1543
1544	/** @name Page Map Level-4 Entry (Long Mode PAE)
1545	* @{
1546	*/
1547	/** Bit 0 - P - Present bit. */
1548	#define X86_PML4E_P RT_BIT(0)
1549	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1550	#define X86_PML4E_RW RT_BIT(1)
1551	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1552	#define X86_PML4E_US RT_BIT(2)
1553	/** Bit 3 - PWT - Page level write thru bit. */
1554	#define X86_PML4E_PWT RT_BIT(3)
1555	/** Bit 4 - PCD - Page level cache disable bit. */
1556	#define X86_PML4E_PCD RT_BIT(4)
1557	/** Bit 5 - A - Access bit. */
1558	#define X86_PML4E_A RT_BIT(5)
1559	/** Bits 9-11 - - Available for use to system software. */
1560	#define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
1561	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1562	#if 1 /* we're using this internally and have to mask of the top 16-bit. */
1563	#define X86_PML4E_PG_MASK ( 0x0000fffffffff000ULL )
1564	#else
1565	#define X86_PML4E_PG_MASK ( 0x000ffffffffff000ULL )
1566	#endif
1567	/** Bits 63 - NX - PAE - No execution flag. */
1568	#define X86_PML4E_NX RT_BIT_64(63)
1569
1570	/**
1571	* Page Map Level-4 Entry
1572	*/
1573	typedef struct X86PML4EBITS
1574	{
1575	/** Flags whether(=1) or not the page is present. */
1576	uint32_t u1Present : 1;
1577	/** Read(=0) / Write(=1) flag. */
1578	uint32_t u1Write : 1;
1579	/** User(=1) / Supervisor (=0) flag. */
1580	uint32_t u1User : 1;
1581	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
1582	uint32_t u1WriteThru : 1;
1583	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
1584	uint32_t u1CacheDisable : 1;
1585	/** Accessed flag.
1586	* Indicates that the page have been read or written to. */
1587	uint32_t u1Accessed : 1;
1588	/** Chunk of reserved bits. */
1589	uint32_t u3Reserved : 3;
1590	/** Available for use to system software. */
1591	uint32_t u3Available : 3;
1592	/** Physical Page number of the next level - Low Part. Don't use! */
1593	uint32_t u20PageNoLow : 20;
1594	/** Physical Page number of the next level - High Part. Don't use! */
1595	uint32_t u20PageNoHigh : 20;
1596	/** MBZ bits */
1597	uint32_t u11Reserved : 11;
1598	/** No Execute flag. */
1599	uint32_t u1NoExecute : 1;
1600	} X86PML4EBITS;
1601	/** Pointer to a page map level-4 entry. */
1602	typedef X86PML4EBITS *PX86PML4EBITS;
1603	/** Pointer to a const page map level-4 entry. */
1604	typedef const X86PML4EBITS *PCX86PML4EBITS;
1605
1606	/**
1607	* Page Map Level-4 Entry.
1608	*/
1609	typedef union X86PML4E
1610	{
1611	/** Normal view. */
1612	X86PML4EBITS n;
1613	/** Unsigned integer view. */
1614	X86PGPAEUINT u;
1615	/** 8 bit unsigned integer view. */
1616	uint8_t au8[8];
1617	/** 16 bit unsigned integer view. */
1618	uint16_t au16[4];
1619	/** 32 bit unsigned integer view. */
1620	uint32_t au32[2];
1621	} X86PML4E;
1622	/** Pointer to a page map level-4 entry. */
1623	typedef X86PML4E *PX86PML4E;
1624	/** Pointer to a const page map level-4 entry. */
1625	typedef const X86PML4E *PCX86PML4E;
1626
1627
1628	/**
1629	* Page Map Level-4.
1630	*/
1631	typedef struct X86PML4
1632	{
1633	/** PDE Array. */
1634	X86PML4E a[X86_PG_PAE_ENTRIES];
1635	} X86PML4;
1636	/** Pointer to a page map level-4. */
1637	typedef X86PML4 *PX86PML4;
1638	/** Pointer to a const page map level-4. */
1639	typedef const X86PML4 *PCX86PML4;
1640
1641	/** The page shift to get the PML4 index. */
1642	#define X86_PML4_SHIFT 39
1643	/** The PML4 index mask (apply to a shifted page address). */
1644	#define X86_PML4_MASK 0x1ff
1645
1646	/** @} */
1647
1648	/** @} */
1649
1650
1651	/**
1652	* 80-bit MMX/FPU register type.
1653	*/
1654	typedef struct X86FPUMMX
1655	{
1656	uint8_t reg[10];
1657	} X86FPUMMX;
1658	/** Pointer to a 80-bit MMX/FPU register type. */
1659	typedef X86FPUMMX *PX86FPUMMX;
1660	/** Pointer to a const 80-bit MMX/FPU register type. */
1661	typedef const X86FPUMMX *PCX86FPUMMX;
1662
1663	/**
1664	* FPU state (aka FSAVE/FRSTOR Memory Region).
1665	*/
1666	#pragma pack(1)
1667	typedef struct X86FPUSTATE
1668	{
1669	/** Control word. */
1670	uint16_t FCW;
1671	/** Alignment word */
1672	uint16_t Dummy1;
1673	/** Status word. */
1674	uint16_t FSW;
1675	/** Alignment word */
1676	uint16_t Dummy2;
1677	/** Tag word */
1678	uint16_t FTW;
1679	/** Alignment word */
1680	uint16_t Dummy3;
1681
1682	/** Instruction pointer. */
1683	uint32_t FPUIP;
1684	/** Code selector. */
1685	uint16_t CS;
1686	/** Opcode. */
1687	uint16_t FOP;
1688	/** FOO. */
1689	uint32_t FPUOO;
1690	/** FOS. */
1691	uint32_t FPUOS;
1692	/** FPU view - todo. */
1693	X86FPUMMX regs[8];
1694	} X86FPUSTATE;
1695	#pragma pack()
1696	/** Pointer to a FPU state. */
1697	typedef X86FPUSTATE *PX86FPUSTATE;
1698	/** Pointer to a const FPU state. */
1699	typedef const X86FPUSTATE *PCX86FPUSTATE;
1700
1701	/**
1702	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
1703	*/
1704	#pragma pack(1)
1705	typedef struct X86FXSTATE
1706	{
1707	/** Control word. */
1708	uint16_t FCW;
1709	/** Status word. */
1710	uint16_t FSW;
1711	/** Tag word (it's a byte actually). */
1712	uint8_t FTW;
1713	uint8_t huh1;
1714	/** Opcode. */
1715	uint16_t FOP;
1716	/** Instruction pointer. */
1717	uint32_t FPUIP;
1718	/** Code selector. */
1719	uint16_t CS;
1720	uint16_t Rsvrd1;
1721	/* - offset 16 - */
1722	/** Data pointer. */
1723	uint32_t FPUDP;
1724	/** Data segment */
1725	uint16_t DS;
1726	uint16_t Rsrvd2;
1727	uint32_t MXCSR;
1728	uint32_t MXCSR_MASK;
1729	/* - offset 32 - */
1730	union
1731	{
1732	/** MMX view. */
1733	uint64_t mmx;
1734	/** FPU view - todo. */
1735	X86FPUMMX fpu;
1736	/** 8-bit view. */
1737	uint8_t au8[16];
1738	/** 16-bit view. */
1739	uint16_t au16[8];
1740	/** 32-bit view. */
1741	uint32_t au32[4];
1742	/** 64-bit view. */
1743	uint64_t au64[2];
1744	/** 128-bit view. (yeah, very helpful) */
1745	uint128_t au128[1];
1746	} aRegs[8];
1747	/* - offset 160 - */
1748	union
1749	{
1750	/** XMM Register view . /
1751	uint128_t xmm;
1752	/** 8-bit view. */
1753	uint8_t au8[16];
1754	/** 16-bit view. */
1755	uint16_t au16[8];
1756	/** 32-bit view. */
1757	uint32_t au32[4];
1758	/** 64-bit view. */
1759	uint64_t au64[2];
1760	/** 128-bit view. (yeah, very helpful) */
1761	uint128_t au128[1];
1762	} aXMM[16]; /* 8 registers in 32 bits mode; 16 in long mode */
1763	/* - offset 416 - */
1764	uint32_t au32RsrvdRest[(512 - 416) / sizeof(uint32_t)];
1765	} X86FXSTATE;
1766	#pragma pack()
1767	/** Pointer to a FPU Extended state. */
1768	typedef X86FXSTATE *PX86FXSTATE;
1769	/** Pointer to a const FPU Extended state. */
1770	typedef const X86FXSTATE *PCX86FXSTATE;
1771
1772
1773	/** @name Selector Descriptor
1774	* @{
1775	*/
1776
1777	/**
1778	* Generic descriptor table entry
1779	*/
1780	#pragma pack(1)
1781	typedef struct X86DESCGENERIC
1782	{
1783	/** Limit - Low word. */
1784	unsigned u16LimitLow : 16;
1785	/** Base address - lowe word.
1786	* Don't try set this to 24 because MSC is doing studing things then. */
1787	unsigned u16BaseLow : 16;
1788	/** Base address - first 8 bits of high word. */
1789	unsigned u8BaseHigh1 : 8;
1790	/** Segment Type. */
1791	unsigned u4Type : 4;
1792	/** Descriptor Type. System(=0) or code/data selector */
1793	unsigned u1DescType : 1;
1794	/** Descriptor Privelege level. */
1795	unsigned u2Dpl : 2;
1796	/** Flags selector present(=1) or not. */
1797	unsigned u1Present : 1;
1798	/** Segment limit 16-19. */
1799	unsigned u4LimitHigh : 4;
1800	/** Available for system software. */
1801	unsigned u1Available : 1;
1802	/** Reserved - 0. */
1803	unsigned u1Reserved : 1;
1804	/** This flags meaning depends on the segment type. Try make sense out
1805	* of the intel manual yourself. */
1806	unsigned u1DefBig : 1;
1807	/** Granularity of the limit. If set 4KB granularity is used, if
1808	* clear byte. */
1809	unsigned u1Granularity : 1;
1810	/** Base address - highest 8 bits. */
1811	unsigned u8BaseHigh2 : 8;
1812	} X86DESCGENERIC;
1813	#pragma pack()
1814	/** Pointer to a generic descriptor entry. */
1815	typedef X86DESCGENERIC *PX86DESCGENERIC;
1816	/** Pointer to a const generic descriptor entry. */
1817	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
1818
1819
1820	/**
1821	* Descriptor attributes.
1822	*/
1823	typedef struct X86DESCATTRBITS
1824	{
1825	/** Segment Type. */
1826	unsigned u4Type : 4;
1827	/** Descriptor Type. System(=0) or code/data selector */
1828	unsigned u1DescType : 1;
1829	/** Descriptor Privelege level. */
1830	unsigned u2Dpl : 2;
1831	/** Flags selector present(=1) or not. */
1832	unsigned u1Present : 1;
1833	/** Segment limit 16-19. */
1834	unsigned u4LimitHigh : 4;
1835	/** Available for system software. */
1836	unsigned u1Available : 1;
1837	/** Reserved - 0. */
1838	unsigned u1Reserved : 1;
1839	/** This flags meaning depends on the segment type. Try make sense out
1840	* of the intel manual yourself. */
1841	unsigned u1DefBig : 1;
1842	/** Granularity of the limit. If set 4KB granularity is used, if
1843	* clear byte. */
1844	unsigned u1Granularity : 1;
1845	} X86DESCATTRBITS;
1846
1847
1848	#pragma pack(1)
1849	typedef union X86DESCATTR
1850	{
1851	/** Normal view. */
1852	X86DESCATTRBITS n;
1853	/** Unsigned integer view. */
1854	uint32_t u;
1855	} X86DESCATTR;
1856	#pragma pack()
1857
1858	/** Pointer to descriptor attributes. */
1859	typedef X86DESCATTR *PX86DESCATTR;
1860	/** Pointer to const descriptor attributes. */
1861	typedef const X86DESCATTR *PCX86DESCATTR;
1862
1863
1864	/**
1865	* Descriptor table entry.
1866	*/
1867	#pragma pack(1)
1868	typedef union X86DESC
1869	{
1870	/** Generic descriptor view. */
1871	X86DESCGENERIC Gen;
1872	#if 0
1873	/** IDT view. */
1874	VBOXIDTE Idt;
1875	#endif
1876
1877	/** 8 bit unsigned interger view. */
1878	uint8_t au8[8];
1879	/** 16 bit unsigned interger view. */
1880	uint16_t au16[4];
1881	/** 32 bit unsigned interger view. */
1882	uint32_t au32[2];
1883	} X86DESC;
1884	#pragma pack()
1885	/** Pointer to descriptor table entry. */
1886	typedef X86DESC *PX86DESC;
1887	/** Pointer to const descriptor table entry. */
1888	typedef const X86DESC *PCX86DESC;
1889
1890
1891	/**
1892	* 64 bits generic descriptor table entry
1893	* Note: most of these bits have no meaning in long mode.
1894	*/
1895	#pragma pack(1)
1896	typedef struct X86DESC64GENERIC
1897	{
1898	/** Limit - Low word - IGNORED. */
1899	unsigned u16LimitLow : 16;
1900	/** Base address - lowe word. - IGNORED
1901	* Don't try set this to 24 because MSC is doing studing things then. */
1902	unsigned u16BaseLow : 16;
1903	/** Base address - first 8 bits of high word. - IGNORED */
1904	unsigned u8BaseHigh1 : 8;
1905	/** Segment Type. */
1906	unsigned u4Type : 4;
1907	/** Descriptor Type. System(=0) or code/data selector */
1908	unsigned u1DescType : 1;
1909	/** Descriptor Privelege level. */
1910	unsigned u2Dpl : 2;
1911	/** Flags selector present(=1) or not. */
1912	unsigned u1Present : 1;
1913	/** Segment limit 16-19. - IGNORED */
1914	unsigned u4LimitHigh : 4;
1915	/** Available for system software. - IGNORED */
1916	unsigned u1Available : 1;
1917	/** Long mode flag. */
1918	unsigned u1Long : 1;
1919	/** This flags meaning depends on the segment type. Try make sense out
1920	* of the intel manual yourself. */
1921	unsigned u1DefBig : 1;
1922	/** Granularity of the limit. If set 4KB granularity is used, if
1923	* clear byte. - IGNORED */
1924	unsigned u1Granularity : 1;
1925	/** Base address - highest 8 bits. - IGNORED */
1926	unsigned u8BaseHigh2 : 8;
1927	/** Base address - bits 63-32. */
1928	unsigned u32BaseHigh3 : 32;
1929	unsigned u8Reserved : 8;
1930	unsigned u5Zeros : 5;
1931	unsigned u19Reserved : 19;
1932	} X86DESC64GENERIC;
1933	#pragma pack()
1934	/** Pointer to a generic descriptor entry. */
1935	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
1936	/** Pointer to a const generic descriptor entry. */
1937	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
1938
1939	/**
1940	* System descriptor table entry (64 bits)
1941	*/
1942	#pragma pack(1)
1943	typedef struct X86DESC64SYSTEM
1944	{
1945	/** Limit - Low word. */
1946	unsigned u16LimitLow : 16;
1947	/** Base address - lowe word.
1948	* Don't try set this to 24 because MSC is doing studing things then. */
1949	unsigned u16BaseLow : 16;
1950	/** Base address - first 8 bits of high word. */
1951	unsigned u8BaseHigh1 : 8;
1952	/** Segment Type. */
1953	unsigned u4Type : 4;
1954	/** Descriptor Type. System(=0) or code/data selector */
1955	unsigned u1DescType : 1;
1956	/** Descriptor Privelege level. */
1957	unsigned u2Dpl : 2;
1958	/** Flags selector present(=1) or not. */
1959	unsigned u1Present : 1;
1960	/** Segment limit 16-19. */
1961	unsigned u4LimitHigh : 4;
1962	/** Available for system software. */
1963	unsigned u1Available : 1;
1964	/** Reserved - 0. */
1965	unsigned u1Reserved : 1;
1966	/** This flags meaning depends on the segment type. Try make sense out
1967	* of the intel manual yourself. */
1968	unsigned u1DefBig : 1;
1969	/** Granularity of the limit. If set 4KB granularity is used, if
1970	* clear byte. */
1971	unsigned u1Granularity : 1;
1972	/** Base address - bits 31-24. */
1973	unsigned u8BaseHigh2 : 8;
1974	/** Base address - bits 63-32. */
1975	unsigned u32BaseHigh3 : 32;
1976	unsigned u8Reserved : 8;
1977	unsigned u5Zeros : 5;
1978	unsigned u19Reserved : 19;
1979	} X86DESC64SYSTEM;
1980	#pragma pack()
1981	/** Pointer to a generic descriptor entry. */
1982	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
1983	/** Pointer to a const generic descriptor entry. */
1984	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
1985
1986
1987	/**
1988	* Descriptor table entry.
1989	*/
1990	#pragma pack(1)
1991	typedef union X86DESC64
1992	{
1993	/** Generic descriptor view. */
1994	X86DESC64GENERIC Gen;
1995	/** System descriptor view. */
1996	X86DESC64SYSTEM System;
1997	#if 0
1998	X86DESC64GATE Gate;
1999	#endif
2000
2001	/** 8 bit unsigned interger view. */
2002	uint8_t au8[16];
2003	/** 16 bit unsigned interger view. */
2004	uint16_t au16[8];
2005	/** 32 bit unsigned interger view. */
2006	uint32_t au32[4];
2007	/** 64 bit unsigned interger view. */
2008	uint64_t au64[2];
2009	} X86DESC64;
2010	#pragma pack()
2011	/** Pointer to descriptor table entry. */
2012	typedef X86DESC64 *PX86DESC64;
2013	/** Pointer to const descriptor table entry. */
2014	typedef const X86DESC64 *PCX86DESC64;
2015
2016	#if HC_ARCH_BITS == 64
2017	typedef X86DESC64 X86DESCHC;
2018	typedef X86DESC64 *PX86DESCHC;
2019	#else
2020	typedef X86DESC X86DESCHC;
2021	typedef X86DESC *PX86DESCHC;
2022	#endif
2023
2024	/** @name Selector Descriptor Types.
2025	* @{
2026	*/
2027
2028	/** @name Non-System Selector Types.
2029	* @{ */
2030	/** Code(=set)/Data(=clear) bit. */
2031	#define X86_SEL_TYPE_CODE 8
2032	/** Memory(=set)/System(=clear) bit. */
2033	#define X86_SEL_TYPE_MEMORY RT_BIT(4)
2034	/** Accessed bit. */
2035	#define X86_SEL_TYPE_ACCESSED 1
2036	/** Expand down bit (for data selectors only). */
2037	#define X86_SEL_TYPE_DOWN 4
2038	/** Conforming bit (for code selectors only). */
2039	#define X86_SEL_TYPE_CONF 4
2040	/** Write bit (for data selectors only). */
2041	#define X86_SEL_TYPE_WRITE 2
2042	/** Read bit (for code selectors only). */
2043	#define X86_SEL_TYPE_READ 2
2044
2045	/** Read only selector type. */
2046	#define X86_SEL_TYPE_RO 0
2047	/** Accessed read only selector type. */
2048	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
2049	/** Read write selector type. */
2050	#define X86_SEL_TYPE_RW 2
2051	/** Accessed read write selector type. */
2052	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
2053	/** Expand down read only selector type. */
2054	#define X86_SEL_TYPE_RO_DOWN 4
2055	/** Accessed expand down read only selector type. */
2056	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
2057	/** Expand down read write selector type. */
2058	#define X86_SEL_TYPE_RW_DOWN 6
2059	/** Accessed expand down read write selector type. */
2060	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
2061	/** Execute only selector type. */
2062	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
2063	/** Accessed execute only selector type. */
2064	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2065	/** Execute and read selector type. */
2066	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
2067	/** Accessed execute and read selector type. */
2068	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2069	/** Conforming execute only selector type. */
2070	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
2071	/** Accessed Conforming execute only selector type. */
2072	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2073	/** Conforming execute and write selector type. */
2074	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
2075	/** Accessed Conforming execute and write selector type. */
2076	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
2077	/** @} */
2078
2079
2080	/** @name System Selector Types.
2081	* @{ */
2082	/** Undefined system selector type. */
2083	#define X86_SEL_TYPE_SYS_UNDEFINED 0
2084	/** 286 TSS selector. */
2085	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
2086	/** LDT selector. */
2087	#define X86_SEL_TYPE_SYS_LDT 2
2088	/** 286 TSS selector - Busy. */
2089	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
2090	/** 286 Callgate selector. */
2091	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
2092	/** Taskgate selector. */
2093	#define X86_SEL_TYPE_SYS_TASK_GATE 5
2094	/** 286 Interrupt gate selector. */
2095	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
2096	/** 286 Trapgate selector. */
2097	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
2098	/** Undefined system selector. */
2099	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
2100	/** 386 TSS selector. */
2101	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
2102	/** Undefined system selector. */
2103	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
2104	/** 386 TSS selector - Busy. */
2105	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
2106	/** 386 Callgate selector. */
2107	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
2108	/** Undefined system selector. */
2109	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
2110	/** 386 Interruptgate selector. */
2111	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
2112	/** 386 Trapgate selector. */
2113	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
2114	/** @} */
2115
2116	/** @name AMD64 System Selector Types.
2117	* @{ */
2118	#define AMD64_SEL_TYPE_SYS_LDT 2
2119	/** 286 TSS selector - Busy. */
2120	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
2121	/** 386 TSS selector - Busy. */
2122	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
2123	/** 386 Callgate selector. */
2124	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
2125	/** 386 Interruptgate selector. */
2126	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
2127	/** 386 Trapgate selector. */
2128	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
2129	/** @} */
2130
2131	/** @} */
2132
2133
2134	/** @name Descriptor Table Entry Flag Masks.
2135	* These are for the 2nd 32-bit word of a descriptor.
2136	* @{ */
2137	/** Bits 8-11 - TYPE - Descriptor type mask. */
2138	#define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
2139	/** Bit 12 - S - System (=0) or Code/Data (=1). */
2140	#define X86_DESC_S RT_BIT(12)
2141	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
2142	#define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
2143	/** Bit 15 - P - Present. */
2144	#define X86_DESC_P RT_BIT(15)
2145	/** Bit 20 - AVL - Available for system software. */
2146	#define X86_DESC_AVL RT_BIT(20)
2147	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
2148	#define X86_DESC_DB RT_BIT(22)
2149	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
2150	* used, if clear byte. */
2151	#define X86_DESC_G RT_BIT(23)
2152	/** @} */
2153
2154	/** @} */
2155
2156
2157	/** @name Selectors.
2158	* @{
2159	*/
2160
2161	/**
2162	* The shift used to convert a selector from and to index an index (C).
2163	*/
2164	#define X86_SEL_SHIFT 3
2165
2166	/**
2167	* The shift used to convert a selector from and to index an index (C).
2168	*/
2169	#define AMD64_SEL_SHIFT 4
2170
2171	#if HC_ARCH_BITS == 64
2172	#define X86_SEL_SHIFT_HC AMD64_SEL_SHIFT
2173	#else
2174	#define X86_SEL_SHIFT_HC X86_SEL_SHIFT
2175	#endif
2176
2177	/**
2178	* The mask used to mask off the table indicator and CPL of an selector.
2179	*/
2180	#define X86_SEL_MASK 0xfff8
2181
2182	/**
2183	* The bit indicating that a selector is in the LDT and not in the GDT.
2184	*/
2185	#define X86_SEL_LDT 0x0004
2186	/**
2187	* The bit mask for getting the RPL of a selector.
2188	*/
2189	#define X86_SEL_RPL 0x0003
2190
2191	/** @} */
2192
2193
2194	/**
2195	* x86 Exceptions/Faults/Traps.
2196	*/
2197	typedef enum X86XCPT
2198	{
2199	/** \#DE - Divide error. */
2200	X86_XCPT_DE = 0x00,
2201	/** \#DB - Debug event (single step, DRx, ..) */
2202	X86_XCPT_DB = 0x01,
2203	/** NMI - Non-Maskable Interrupt */
2204	X86_XCPT_NMI = 0x02,
2205	/** \#BP - Breakpoint (INT3). */
2206	X86_XCPT_BP = 0x03,
2207	/** \#OF - Overflow (INTO). */
2208	X86_XCPT_OF = 0x04,
2209	/** \#BR - Bound range exceeded (BOUND). */
2210	X86_XCPT_BR = 0x05,
2211	/** \#UD - Undefined opcode. */
2212	X86_XCPT_UD = 0x06,
2213	/** \#NM - Device not available (math coprocessor device). */
2214	X86_XCPT_NM = 0x07,
2215	/** \#DF - Double fault. */
2216	X86_XCPT_DF = 0x08,
2217	/** ??? - Coprocessor segment overrun (obsolete). */
2218	X86_XCPT_CO_SEG_OVERRUN = 0x09,
2219	/** \#TS - Taskswitch (TSS). */
2220	X86_XCPT_TS = 0x0a,
2221	/** \#NP - Segment no present. */
2222	X86_XCPT_NP = 0x0b,
2223	/** \#SS - Stack segment fault. */
2224	X86_XCPT_SS = 0x0c,
2225	/** \#GP - General protection fault. */
2226	X86_XCPT_GP = 0x0d,
2227	/** \#PF - Page fault. */
2228	X86_XCPT_PF = 0x0e,
2229	/* 0x0f is reserved. */
2230	/** \#MF - Math fault (FPU). */
2231	X86_XCPT_MF = 0x10,
2232	/** \#AC - Alignment check. */
2233	X86_XCPT_AC = 0x11,
2234	/** \#MC - Machine check. */
2235	X86_XCPT_MC = 0x12,
2236	/** \#XF - SIMD Floating-Pointer Exception. */
2237	X86_XCPT_XF = 0x13
2238	} X86XCPT;
2239	/** Pointer to a x86 exception code. */
2240	typedef X86XCPT *PX86XCPT;
2241	/** Pointer to a const x86 exception code. */
2242	typedef const X86XCPT *PCX86XCPT;
2243
2244
2245	/** @name Trap Error Codes
2246	* @{
2247	*/
2248	/** External indicator. */
2249	#define X86_TRAP_ERR_EXTERNAL 1
2250	/** IDT indicator. */
2251	#define X86_TRAP_ERR_IDT 2
2252	/** Descriptor table indicator - If set LDT, if clear GDT. */
2253	#define X86_TRAP_ERR_TI 4
2254	/** Mask for getting the selector. */
2255	#define X86_TRAP_ERR_SEL_MASK 0xfff8
2256	/** Shift for getting the selector table index (C type index). */
2257	#define X86_TRAP_ERR_SEL_SHIFT 3
2258	/** @} */
2259
2260
2261	/** @name \#PF Trap Error Codes
2262	* @{
2263	*/
2264	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
2265	#define X86_TRAP_PF_P RT_BIT(0)
2266	/** Bit 1 - R/W - Read (clear) or write (set) access. */
2267	#define X86_TRAP_PF_RW RT_BIT(1)
2268	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
2269	#define X86_TRAP_PF_US RT_BIT(2)
2270	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
2271	#define X86_TRAP_PF_RSVD RT_BIT(3)
2272	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
2273	#define X86_TRAP_PF_ID RT_BIT(4)
2274	/** @} */
2275
2276	#pragma pack(1)
2277	/**
2278	* 32-bit IDTR/GDTR.
2279	*/
2280	typedef struct X86XDTR32
2281	{
2282	/** Size of the descriptor table. */
2283	uint16_t cb;
2284	/** Address of the descriptor table. */
2285	uint32_t uAddr;
2286	} X86XDTR32, *PX86XDTR32;
2287	#pragma pack()
2288
2289	#pragma pack(1)
2290	/**
2291	* 64-bit IDTR/GDTR.
2292	*/
2293	typedef struct X86XDTR64
2294	{
2295	/** Size of the descriptor table. */
2296	uint16_t cb;
2297	/** Address of the descriptor table. */
2298	uint64_t uAddr;
2299	} X86XDTR64, *PX86XDTR64;
2300	#pragma pack()
2301
2302	/** @} */
2303
2304	#endif
2305

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